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rtos: hwthread: fix clang error core.NullDereference
[openocd.git] / src / target / mips_m4k.c
blobe85018c878382c810d39668c19f16f81a6906ad1
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2008 by Spencer Oliver *
5 * spen@spen-soft.co.uk *
6 * *
7 * Copyright (C) 2008 by David T.L. Wong *
8 * *
9 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
10 * *
11 * Copyright (C) 2011 by Drasko DRASKOVIC *
12 * drasko.draskovic@gmail.com *
13 ***************************************************************************/
14
15 #ifdef HAVE_CONFIG_H
16 #include "config.h"
17 #endif
18
19 #include "breakpoints.h"
20 #include "mips32.h"
21 #include "mips_m4k.h"
22 #include "mips32_dmaacc.h"
23 #include "target_type.h"
24 #include "register.h"
25 #include "smp.h"
26
27 static void mips_m4k_enable_breakpoints(struct target *target);
28 static void mips_m4k_enable_watchpoints(struct target *target);
29 static int mips_m4k_set_breakpoint(struct target *target,
30 struct breakpoint *breakpoint);
31 static int mips_m4k_unset_breakpoint(struct target *target,
32 struct breakpoint *breakpoint);
33 static int mips_m4k_internal_restore(struct target *target, int current,
34 target_addr_t address, int handle_breakpoints,
35 int debug_execution);
36 static int mips_m4k_halt(struct target *target);
37 static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
38 uint32_t count, const uint8_t *buffer);
39
40 static int mips_m4k_examine_debug_reason(struct target *target)
41 {
42 struct mips32_common *mips32 = target_to_mips32(target);
43 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
44 uint32_t break_status;
45 int retval;
46
47 if ((target->debug_reason != DBG_REASON_DBGRQ)
48 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
49 if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
50 /* get info about inst breakpoint support */
51 retval = target_read_u32(target,
52 ejtag_info->ejtag_ibs_addr, &break_status);
53 if (retval != ERROR_OK)
54 return retval;
55 if (break_status & 0x1f) {
56 /* we have halted on a breakpoint */
57 retval = target_write_u32(target,
58 ejtag_info->ejtag_ibs_addr, 0);
59 if (retval != ERROR_OK)
60 return retval;
61 target->debug_reason = DBG_REASON_BREAKPOINT;
62 }
63 }
64
65 if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
66 /* get info about data breakpoint support */
67 retval = target_read_u32(target,
68 ejtag_info->ejtag_dbs_addr, &break_status);
69 if (retval != ERROR_OK)
70 return retval;
71 if (break_status & 0x1f) {
72 /* we have halted on a breakpoint */
73 retval = target_write_u32(target,
74 ejtag_info->ejtag_dbs_addr, 0);
75 if (retval != ERROR_OK)
76 return retval;
77 target->debug_reason = DBG_REASON_WATCHPOINT;
78 }
79 }
80 }
81
82 return ERROR_OK;
83 }
84
85 static int mips_m4k_debug_entry(struct target *target)
86 {
87 struct mips32_common *mips32 = target_to_mips32(target);
88 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
89
90 mips32_save_context(target);
91
92 /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
93 mips_ejtag_config_step(ejtag_info, 0);
94
95 /* make sure break unit configured */
96 mips32_configure_break_unit(target);
97
98 /* attempt to find halt reason */
99 mips_m4k_examine_debug_reason(target);
100
101 mips32_read_config_regs(target);
102
103 /* default to mips32 isa, it will be changed below if required */
104 mips32->isa_mode = MIPS32_ISA_MIPS32;
105
106 /* other than mips32 only and isa bit set ? */
107 if (mips32->isa_imp && buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1))
108 mips32->isa_mode = mips32->isa_imp == 2 ? MIPS32_ISA_MIPS16E : MIPS32_ISA_MMIPS32;
109
110 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
111 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
112 target_state_name(target));
113
114 return ERROR_OK;
115 }
116
117 static struct target *get_mips_m4k(struct target *target, int32_t coreid)
118 {
119 struct target_list *head;
120
121 foreach_smp_target(head, target->smp_targets) {
122 struct target *curr = head->target;
123 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
124 return curr;
125 }
126 return target;
127 }
128
129 static int mips_m4k_halt_smp(struct target *target)
130 {
131 int retval = ERROR_OK;
132 struct target_list *head;
133
134 foreach_smp_target(head, target->smp_targets) {
135 int ret = ERROR_OK;
136 struct target *curr = head->target;
137 if ((curr != target) && (curr->state != TARGET_HALTED))
138 ret = mips_m4k_halt(curr);
139
140 if (ret != ERROR_OK) {
141 LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid);
142 retval = ret;
143 }
144 }
145 return retval;
146 }
147
148 static int update_halt_gdb(struct target *target)
149 {
150 int retval = ERROR_OK;
151 if (target->gdb_service->core[0] == -1) {
152 target->gdb_service->target = target;
153 target->gdb_service->core[0] = target->coreid;
154 retval = mips_m4k_halt_smp(target);
155 }
156 return retval;
157 }
158
159 static int mips_m4k_poll(struct target *target)
160 {
161 int retval = ERROR_OK;
162 struct mips32_common *mips32 = target_to_mips32(target);
163 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
164 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
165 enum target_state prev_target_state = target->state;
166
167 /* toggle to another core is done by gdb as follow */
168 /* maint packet J core_id */
169 /* continue */
170 /* the next polling trigger an halt event sent to gdb */
171 if ((target->state == TARGET_HALTED) && (target->smp) &&
172 (target->gdb_service) &&
173 (!target->gdb_service->target)) {
174 target->gdb_service->target =
175 get_mips_m4k(target, target->gdb_service->core[1]);
176 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
177 return retval;
178 }
179
180 /* read ejtag control reg */
181 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
182 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
183 if (retval != ERROR_OK)
184 return retval;
185
186 ejtag_info->isa = (ejtag_ctrl & EJTAG_CTRL_DBGISA) ? 1 : 0;
187
188 /* clear this bit before handling polling
189 * as after reset registers will read zero */
190 if (ejtag_ctrl & EJTAG_CTRL_ROCC) {
191 /* we have detected a reset, clear flag
192 * otherwise ejtag will not work */
193 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
194
195 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
196 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
197 if (retval != ERROR_OK)
198 return retval;
199 LOG_DEBUG("Reset Detected");
200 }
201
202 /* check for processor halted */
203 if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
204 if ((target->state != TARGET_HALTED)
205 && (target->state != TARGET_DEBUG_RUNNING)) {
206 if (target->state == TARGET_UNKNOWN)
207 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
208
209 /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
210 * (maybe put on by HALT-ing the board in the previous session).
211 *
212 * Force enable debug entry for this session.
213 */
214 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
215 target->state = TARGET_HALTED;
216 retval = mips_m4k_debug_entry(target);
217 if (retval != ERROR_OK)
218 return retval;
219
220 if (target->smp &&
221 ((prev_target_state == TARGET_RUNNING)
222 || (prev_target_state == TARGET_RESET))) {
223 retval = update_halt_gdb(target);
224 if (retval != ERROR_OK)
225 return retval;
226 }
227 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
228 } else if (target->state == TARGET_DEBUG_RUNNING) {
229 target->state = TARGET_HALTED;
230
231 retval = mips_m4k_debug_entry(target);
232 if (retval != ERROR_OK)
233 return retval;
234
235 if (target->smp) {
236 retval = update_halt_gdb(target);
237 if (retval != ERROR_OK)
238 return retval;
239 }
240
241 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
242 }
243 } else
244 target->state = TARGET_RUNNING;
245
246 /* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
247
248 return ERROR_OK;
249 }
250
251 static int mips_m4k_halt(struct target *target)
252 {
253 struct mips32_common *mips32 = target_to_mips32(target);
254 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
255
256 LOG_DEBUG("target->state: %s", target_state_name(target));
257
258 if (target->state == TARGET_HALTED) {
259 LOG_DEBUG("target was already halted");
260 return ERROR_OK;
261 }
262
263 if (target->state == TARGET_UNKNOWN)
264 LOG_WARNING("target was in unknown state when halt was requested");
265
266 if (target->state == TARGET_RESET) {
267 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
268 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
269 return ERROR_TARGET_FAILURE;
270 } else {
271 /* we came here in a reset_halt or reset_init sequence
272 * debug entry was already prepared in mips_m4k_assert_reset()
273 */
274 target->debug_reason = DBG_REASON_DBGRQ;
275
276 return ERROR_OK;
277 }
278 }
279
280 /* break processor */
281 mips_ejtag_enter_debug(ejtag_info);
282
283 target->debug_reason = DBG_REASON_DBGRQ;
284
285 return ERROR_OK;
286 }
287
288 static int mips_m4k_assert_reset(struct target *target)
289 {
290 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
291 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
292
293 /* TODO: apply hw reset signal in not examined state */
294 if (!(target_was_examined(target))) {
295 LOG_WARNING("Reset is not asserted because the target is not examined.");
296 LOG_WARNING("Use a reset button or power cycle the target.");
297 return ERROR_TARGET_NOT_EXAMINED;
298 }
299
300 LOG_DEBUG("target->state: %s",
301 target_state_name(target));
302
303 enum reset_types jtag_reset_config = jtag_get_reset_config();
304
305 /* some cores support connecting while srst is asserted
306 * use that mode is it has been configured */
307
308 bool srst_asserted = false;
309
310 if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
311 (jtag_reset_config & RESET_SRST_NO_GATING)) {
312 jtag_add_reset(0, 1);
313 srst_asserted = true;
314 }
315
316
317 /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
318 if (ejtag_info->ejtag_version != EJTAG_VERSION_20) {
319 if (target->reset_halt) {
320 /* use hardware to catch reset */
321 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
322 } else
323 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
324 }
325
326 if (jtag_reset_config & RESET_HAS_SRST) {
327 /* here we should issue a srst only, but we may have to assert trst as well */
328 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
329 jtag_add_reset(1, 1);
330 else if (!srst_asserted)
331 jtag_add_reset(0, 1);
332 } else if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
333 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
334 } else {
335 if (mips_m4k->is_pic32mx) {
336 LOG_DEBUG("Using MTAP reset to reset processor...");
337
338 /* use microchip specific MTAP reset */
339 mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
340 mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
341
342 mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
343 mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
344 mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
345 } else {
346 /* use ejtag reset - not supported by all cores */
347 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
348 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
349 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
350 mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
351 }
352 }
353
354 target->state = TARGET_RESET;
355 jtag_add_sleep(50000);
356
357 register_cache_invalidate(mips_m4k->mips32.core_cache);
358
359 if (target->reset_halt) {
360 int retval = target_halt(target);
361 if (retval != ERROR_OK)
362 return retval;
363 }
364
365 return ERROR_OK;
366 }
367
368 static int mips_m4k_deassert_reset(struct target *target)
369 {
370 LOG_DEBUG("target->state: %s", target_state_name(target));
371
372 /* deassert reset lines */
373 jtag_add_reset(0, 0);
374
375 return ERROR_OK;
376 }
377
378 static int mips_m4k_single_step_core(struct target *target)
379 {
380 struct mips32_common *mips32 = target_to_mips32(target);
381 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
382
383 /* configure single step mode */
384 mips_ejtag_config_step(ejtag_info, 1);
385
386 /* disable interrupts while stepping */
387 mips32_enable_interrupts(target, 0);
388
389 /* exit debug mode */
390 mips_ejtag_exit_debug(ejtag_info);
391
392 mips_m4k_debug_entry(target);
393
394 return ERROR_OK;
395 }
396
397 static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
398 {
399 int retval = ERROR_OK;
400 struct target_list *head;
401
402 foreach_smp_target(head, target->smp_targets) {
403 int ret = ERROR_OK;
404 struct target *curr = head->target;
405 if ((curr != target) && (curr->state != TARGET_RUNNING)) {
406 /* resume current address , not in step mode */
407 ret = mips_m4k_internal_restore(curr, 1, address,
408 handle_breakpoints, 0);
409
410 if (ret != ERROR_OK) {
411 LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32,
412 curr->coreid, address);
413 retval = ret;
414 }
415 }
416 }
417 return retval;
418 }
419
420 static int mips_m4k_internal_restore(struct target *target, int current,
421 target_addr_t address, int handle_breakpoints, int debug_execution)
422 {
423 struct mips32_common *mips32 = target_to_mips32(target);
424 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
425 struct breakpoint *breakpoint = NULL;
426 uint32_t resume_pc;
427
428 if (target->state != TARGET_HALTED) {
429 LOG_WARNING("target not halted");
430 return ERROR_TARGET_NOT_HALTED;
431 }
432
433 if (!debug_execution) {
434 target_free_all_working_areas(target);
435 mips_m4k_enable_breakpoints(target);
436 mips_m4k_enable_watchpoints(target);
437 }
438
439 /* current = 1: continue on current pc, otherwise continue at <address> */
440 if (!current) {
441 mips_m4k_isa_filter(mips32->isa_imp, &address);
442 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
443 mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
444 mips32->core_cache->reg_list[MIPS32_PC].valid = true;
445 }
446
447 if ((mips32->isa_imp > 1) && debug_execution) /* if more than one isa supported */
448 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
449
450 if (!current)
451 resume_pc = address;
452 else
453 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
454
455 mips32_restore_context(target);
456
457 /* the front-end may request us not to handle breakpoints */
458 if (handle_breakpoints) {
459 /* Single step past breakpoint at current address */
460 breakpoint = breakpoint_find(target, resume_pc);
461 if (breakpoint) {
462 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",
463 breakpoint->address);
464 mips_m4k_unset_breakpoint(target, breakpoint);
465 mips_m4k_single_step_core(target);
466 mips_m4k_set_breakpoint(target, breakpoint);
467 }
468 }
469
470 /* enable interrupts if we are running */
471 mips32_enable_interrupts(target, !debug_execution);
472
473 /* exit debug mode */
474 mips_ejtag_exit_debug(ejtag_info);
475 target->debug_reason = DBG_REASON_NOTHALTED;
476
477 /* registers are now invalid */
478 register_cache_invalidate(mips32->core_cache);
479
480 if (!debug_execution) {
481 target->state = TARGET_RUNNING;
482 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
483 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
484 } else {
485 target->state = TARGET_DEBUG_RUNNING;
486 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
487 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
488 }
489
490 return ERROR_OK;
491 }
492
493 static int mips_m4k_resume(struct target *target, int current,
494 target_addr_t address, int handle_breakpoints, int debug_execution)
495 {
496 int retval = ERROR_OK;
497
498 /* dummy resume for smp toggle in order to reduce gdb impact */
499 if ((target->smp) && (target->gdb_service->core[1] != -1)) {
500 /* simulate a start and halt of target */
501 target->gdb_service->target = NULL;
502 target->gdb_service->core[0] = target->gdb_service->core[1];
503 /* fake resume at next poll we play the target core[1], see poll*/
504 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
505 return retval;
506 }
507
508 retval = mips_m4k_internal_restore(target, current, address,
509 handle_breakpoints,
510 debug_execution);
511
512 if (retval == ERROR_OK && target->smp) {
513 target->gdb_service->core[0] = -1;
514 retval = mips_m4k_restore_smp(target, address, handle_breakpoints);
515 }
516
517 return retval;
518 }
519
520 static int mips_m4k_step(struct target *target, int current,
521 target_addr_t address, int handle_breakpoints)
522 {
523 /* get pointers to arch-specific information */
524 struct mips32_common *mips32 = target_to_mips32(target);
525 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
526 struct breakpoint *breakpoint = NULL;
527
528 if (target->state != TARGET_HALTED) {
529 LOG_WARNING("target not halted");
530 return ERROR_TARGET_NOT_HALTED;
531 }
532
533 /* current = 1: continue on current pc, otherwise continue at <address> */
534 if (!current) {
535 mips_m4k_isa_filter(mips32->isa_imp, &address);
536 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
537 mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
538 mips32->core_cache->reg_list[MIPS32_PC].valid = true;
539 }
540
541 /* the front-end may request us not to handle breakpoints */
542 if (handle_breakpoints) {
543 breakpoint = breakpoint_find(target,
544 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
545 if (breakpoint)
546 mips_m4k_unset_breakpoint(target, breakpoint);
547 }
548
549 /* restore context */
550 mips32_restore_context(target);
551
552 /* configure single step mode */
553 mips_ejtag_config_step(ejtag_info, 1);
554
555 target->debug_reason = DBG_REASON_SINGLESTEP;
556
557 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
558
559 /* disable interrupts while stepping */
560 mips32_enable_interrupts(target, 0);
561
562 /* exit debug mode */
563 mips_ejtag_exit_debug(ejtag_info);
564
565 /* registers are now invalid */
566 register_cache_invalidate(mips32->core_cache);
567
568 LOG_DEBUG("target stepped ");
569 mips_m4k_debug_entry(target);
570
571 if (breakpoint)
572 mips_m4k_set_breakpoint(target, breakpoint);
573
574 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
575
576 return ERROR_OK;
577 }
578
579 static void mips_m4k_enable_breakpoints(struct target *target)
580 {
581 struct breakpoint *breakpoint = target->breakpoints;
582
583 /* set any pending breakpoints */
584 while (breakpoint) {
585 if (!breakpoint->is_set)
586 mips_m4k_set_breakpoint(target, breakpoint);
587 breakpoint = breakpoint->next;
588 }
589 }
590
591 static int mips_m4k_set_breakpoint(struct target *target,
592 struct breakpoint *breakpoint)
593 {
594 struct mips32_common *mips32 = target_to_mips32(target);
595 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
596 struct mips32_comparator *comparator_list = mips32->inst_break_list;
597 int retval;
598
599 if (breakpoint->is_set) {
600 LOG_WARNING("breakpoint already set");
601 return ERROR_OK;
602 }
603
604 if (breakpoint->type == BKPT_HARD) {
605 int bp_num = 0;
606
607 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
608 bp_num++;
609 if (bp_num >= mips32->num_inst_bpoints) {
610 LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")",
611 breakpoint->unique_id);
612 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
613 }
614 breakpoint_hw_set(breakpoint, bp_num);
615 comparator_list[bp_num].used = 1;
616 comparator_list[bp_num].bp_value = breakpoint->address;
617
618 if (breakpoint->length != 4) /* make sure isa bit set */
619 comparator_list[bp_num].bp_value |= 1;
620 else /* make sure isa bit cleared */
621 comparator_list[bp_num].bp_value &= ~1;
622
623 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
624 * Warning: there is no IB ASID registers in 2.0.
625 * Do not set it! :) */
626 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
627 comparator_list[bp_num].bp_value &= 0xFFFFFFFC;
628
629 target_write_u32(target, comparator_list[bp_num].reg_address,
630 comparator_list[bp_num].bp_value);
631 target_write_u32(target, comparator_list[bp_num].reg_address +
632 ejtag_info->ejtag_ibm_offs, 0x00000000);
633 target_write_u32(target, comparator_list[bp_num].reg_address +
634 ejtag_info->ejtag_ibc_offs, 1);
635 LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
636 breakpoint->unique_id,
637 bp_num, comparator_list[bp_num].bp_value);
638 } else if (breakpoint->type == BKPT_SOFT) {
639 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
640
641 uint32_t isa_req = breakpoint->length & 1; /* micro mips request bit */
642 uint32_t bplength = breakpoint->length & ~1; /* drop micro mips request bit for length */
643 uint32_t bpaddr = breakpoint->address & ~1; /* drop isa bit from address, if set */
644
645 if (bplength == 4) {
646 uint32_t verify = 0xffffffff;
647 uint32_t sdbbp32_instr = MIPS32_SDBBP(isa_req);
648 if (ejtag_info->endianness && isa_req)
649 sdbbp32_instr = SWAP16(sdbbp32_instr);
650
651 if ((breakpoint->address & 3) == 0) { /* word aligned */
652
653 retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);
654 if (retval != ERROR_OK)
655 return retval;
656
657 retval = target_write_u32(target, bpaddr, sdbbp32_instr);
658 if (retval != ERROR_OK)
659 return retval;
660
661 retval = target_read_u32(target, bpaddr, &verify);
662 if (retval != ERROR_OK)
663 return retval;
664
665 if (verify != sdbbp32_instr)
666 verify = 0;
667
668 } else { /* 16 bit aligned */
669 retval = target_read_memory(target, bpaddr, 2, 2, breakpoint->orig_instr);
670 if (retval != ERROR_OK)
671 return retval;
672
673 uint8_t sdbbp_buf[4];
674 target_buffer_set_u32(target, sdbbp_buf, sdbbp32_instr);
675
676 retval = target_write_memory(target, bpaddr, 2, 2, sdbbp_buf);
677 if (retval != ERROR_OK)
678 return retval;
679
680 retval = target_read_memory(target, bpaddr, 2, 2, sdbbp_buf);
681 if (retval != ERROR_OK)
682 return retval;
683
684 if (target_buffer_get_u32(target, sdbbp_buf) != sdbbp32_instr)
685 verify = 0;
686 }
687
688 if (verify == 0) {
689 LOG_ERROR("Unable to set 32bit breakpoint at address %08" TARGET_PRIxADDR
690 " - check that memory is read/writable", breakpoint->address);
691 return ERROR_OK;
692 }
693
694 } else {
695 uint16_t verify = 0xffff;
696
697 retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);
698 if (retval != ERROR_OK)
699 return retval;
700
701 retval = target_write_u16(target, bpaddr, MIPS16_SDBBP(isa_req));
702 if (retval != ERROR_OK)
703 return retval;
704
705 retval = target_read_u16(target, bpaddr, &verify);
706 if (retval != ERROR_OK)
707 return retval;
708
709 if (verify != MIPS16_SDBBP(isa_req)) {
710 LOG_ERROR("Unable to set 16bit breakpoint at address %08" TARGET_PRIxADDR
711 " - check that memory is read/writable", breakpoint->address);
712 return ERROR_OK;
713 }
714 }
715
716 breakpoint->is_set = true;
717 }
718
719 return ERROR_OK;
720 }
721
722 static int mips_m4k_unset_breakpoint(struct target *target,
723 struct breakpoint *breakpoint)
724 {
725 /* get pointers to arch-specific information */
726 struct mips32_common *mips32 = target_to_mips32(target);
727 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
728 struct mips32_comparator *comparator_list = mips32->inst_break_list;
729 int retval;
730
731 if (!breakpoint->is_set) {
732 LOG_WARNING("breakpoint not set");
733 return ERROR_OK;
734 }
735
736 if (breakpoint->type == BKPT_HARD) {
737 int bp_num = breakpoint->number;
738 if (bp_num >= mips32->num_inst_bpoints) {
739 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
740 breakpoint->unique_id);
741 return ERROR_OK;
742 }
743 LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
744 breakpoint->unique_id,
745 bp_num);
746 comparator_list[bp_num].used = 0;
747 comparator_list[bp_num].bp_value = 0;
748 target_write_u32(target, comparator_list[bp_num].reg_address +
749 ejtag_info->ejtag_ibc_offs, 0);
750
751 } else {
752 /* restore original instruction (kept in target endianness) */
753 uint32_t isa_req = breakpoint->length & 1;
754 uint32_t bplength = breakpoint->length & ~1;
755 uint8_t current_instr[4];
756 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
757 if (bplength == 4) {
758 uint32_t sdbbp32_instr = MIPS32_SDBBP(isa_req);
759 if (ejtag_info->endianness && isa_req)
760 sdbbp32_instr = SWAP16(sdbbp32_instr);
761
762 if ((breakpoint->address & 3) == 0) { /* 32bit aligned */
763 /* check that user program has not modified breakpoint instruction */
764 retval = target_read_memory(target, breakpoint->address, 4, 1, current_instr);
765 if (retval != ERROR_OK)
766 return retval;
767 /**
768 * target_read_memory() gets us data in _target_ endianness.
769 * If we want to use this data on the host for comparisons with some macros
770 * we must first transform it to _host_ endianness using target_buffer_get_u16().
771 */
772 if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {
773 retval = target_write_memory(target, breakpoint->address, 4, 1,
774 breakpoint->orig_instr);
775 if (retval != ERROR_OK)
776 return retval;
777 }
778 } else { /* 16bit aligned */
779 retval = target_read_memory(target, breakpoint->address, 2, 2, current_instr);
780 if (retval != ERROR_OK)
781 return retval;
782
783 if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {
784 retval = target_write_memory(target, breakpoint->address, 2, 2,
785 breakpoint->orig_instr);
786 if (retval != ERROR_OK)
787 return retval;
788 }
789 }
790 } else {
791 /* check that user program has not modified breakpoint instruction */
792 retval = target_read_memory(target, breakpoint->address, 2, 1, current_instr);
793 if (retval != ERROR_OK)
794 return retval;
795
796 if (target_buffer_get_u16(target, current_instr) == MIPS16_SDBBP(isa_req)) {
797 retval = target_write_memory(target, breakpoint->address, 2, 1,
798 breakpoint->orig_instr);
799 if (retval != ERROR_OK)
800 return retval;
801 }
802 }
803 }
804
805 breakpoint->is_set = false;
806
807 return ERROR_OK;
808 }
809
810 static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
811 {
812 struct mips32_common *mips32 = target_to_mips32(target);
813
814 if ((breakpoint->length > 5 || breakpoint->length < 2) || /* out of range */
815 (breakpoint->length == 4 && (breakpoint->address & 2)) || /* mips32 unaligned */
816 (mips32->isa_imp == MIPS32_ONLY && breakpoint->length != 4) || /* misp32 specific */
817 ((mips32->isa_imp & 1) != (breakpoint->length & 1))) /* isa not implemented */
818 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
819
820 if (breakpoint->type == BKPT_HARD) {
821 if (mips32->num_inst_bpoints_avail < 1) {
822 LOG_INFO("no hardware breakpoint available");
823 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
824 }
825
826 mips32->num_inst_bpoints_avail--;
827 }
828
829 return mips_m4k_set_breakpoint(target, breakpoint);
830 }
831
832 static int mips_m4k_remove_breakpoint(struct target *target,
833 struct breakpoint *breakpoint)
834 {
835 /* get pointers to arch-specific information */
836 struct mips32_common *mips32 = target_to_mips32(target);
837
838 if (target->state != TARGET_HALTED) {
839 LOG_WARNING("target not halted");
840 return ERROR_TARGET_NOT_HALTED;
841 }
842
843 if (breakpoint->is_set)
844 mips_m4k_unset_breakpoint(target, breakpoint);
845
846 if (breakpoint->type == BKPT_HARD)
847 mips32->num_inst_bpoints_avail++;
848
849 return ERROR_OK;
850 }
851
852 static int mips_m4k_set_watchpoint(struct target *target,
853 struct watchpoint *watchpoint)
854 {
855 struct mips32_common *mips32 = target_to_mips32(target);
856 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
857 struct mips32_comparator *comparator_list = mips32->data_break_list;
858 int wp_num = 0;
859 /*
860 * watchpoint enabled, ignore all byte lanes in value register
861 * and exclude both load and store accesses from watchpoint
862 * condition evaluation
863 */
864 int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE |
865 (0xff << EJTAG_DBCN_BLM_SHIFT);
866
867 if (watchpoint->is_set) {
868 LOG_WARNING("watchpoint already set");
869 return ERROR_OK;
870 }
871
872 while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
873 wp_num++;
874 if (wp_num >= mips32->num_data_bpoints) {
875 LOG_ERROR("Can not find free FP Comparator");
876 return ERROR_FAIL;
877 }
878
879 if (watchpoint->length != 4) {
880 LOG_ERROR("Only watchpoints of length 4 are supported");
881 return ERROR_TARGET_UNALIGNED_ACCESS;
882 }
883
884 if (watchpoint->address % 4) {
885 LOG_ERROR("Watchpoints address should be word aligned");
886 return ERROR_TARGET_UNALIGNED_ACCESS;
887 }
888
889 switch (watchpoint->rw) {
890 case WPT_READ:
891 enable &= ~EJTAG_DBCN_NOLB;
892 break;
893 case WPT_WRITE:
894 enable &= ~EJTAG_DBCN_NOSB;
895 break;
896 case WPT_ACCESS:
897 enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB);
898 break;
899 default:
900 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
901 }
902
903 watchpoint->number = wp_num;
904 comparator_list[wp_num].used = 1;
905 comparator_list[wp_num].bp_value = watchpoint->address;
906
907 /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
908 * There is as well no ASID register support. */
909 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
910 comparator_list[wp_num].bp_value &= 0xFFFFFFF8;
911 else
912 target_write_u32(target, comparator_list[wp_num].reg_address +
913 ejtag_info->ejtag_dbasid_offs, 0x00000000);
914
915 target_write_u32(target, comparator_list[wp_num].reg_address,
916 comparator_list[wp_num].bp_value);
917 target_write_u32(target, comparator_list[wp_num].reg_address +
918 ejtag_info->ejtag_dbm_offs, 0x00000000);
919
920 target_write_u32(target, comparator_list[wp_num].reg_address +
921 ejtag_info->ejtag_dbc_offs, enable);
922 /* TODO: probably this value is ignored on 2.0 */
923 target_write_u32(target, comparator_list[wp_num].reg_address +
924 ejtag_info->ejtag_dbv_offs, 0);
925 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
926
927 return ERROR_OK;
928 }
929
930 static int mips_m4k_unset_watchpoint(struct target *target,
931 struct watchpoint *watchpoint)
932 {
933 /* get pointers to arch-specific information */
934 struct mips32_common *mips32 = target_to_mips32(target);
935 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
936 struct mips32_comparator *comparator_list = mips32->data_break_list;
937
938 if (!watchpoint->is_set) {
939 LOG_WARNING("watchpoint not set");
940 return ERROR_OK;
941 }
942
943 int wp_num = watchpoint->number;
944 if (wp_num >= mips32->num_data_bpoints) {
945 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
946 return ERROR_OK;
947 }
948 comparator_list[wp_num].used = 0;
949 comparator_list[wp_num].bp_value = 0;
950 target_write_u32(target, comparator_list[wp_num].reg_address +
951 ejtag_info->ejtag_dbc_offs, 0);
952 watchpoint->is_set = false;
953
954 return ERROR_OK;
955 }
956
957 static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
958 {
959 struct mips32_common *mips32 = target_to_mips32(target);
960
961 if (mips32->num_data_bpoints_avail < 1) {
962 LOG_INFO("no hardware watchpoints available");
963 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
964 }
965
966 mips32->num_data_bpoints_avail--;
967
968 mips_m4k_set_watchpoint(target, watchpoint);
969 return ERROR_OK;
970 }
971
972 static int mips_m4k_remove_watchpoint(struct target *target,
973 struct watchpoint *watchpoint)
974 {
975 /* get pointers to arch-specific information */
976 struct mips32_common *mips32 = target_to_mips32(target);
977
978 if (target->state != TARGET_HALTED) {
979 LOG_WARNING("target not halted");
980 return ERROR_TARGET_NOT_HALTED;
981 }
982
983 if (watchpoint->is_set)
984 mips_m4k_unset_watchpoint(target, watchpoint);
985
986 mips32->num_data_bpoints_avail++;
987
988 return ERROR_OK;
989 }
990
991 static void mips_m4k_enable_watchpoints(struct target *target)
992 {
993 struct watchpoint *watchpoint = target->watchpoints;
994
995 /* set any pending watchpoints */
996 while (watchpoint) {
997 if (!watchpoint->is_set)
998 mips_m4k_set_watchpoint(target, watchpoint);
999 watchpoint = watchpoint->next;
1000 }
1001 }
1002
1003 static int mips_m4k_read_memory(struct target *target, target_addr_t address,
1004 uint32_t size, uint32_t count, uint8_t *buffer)
1005 {
1006 struct mips32_common *mips32 = target_to_mips32(target);
1007 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1008
1009 LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1010 address, size, count);
1011
1012 if (target->state != TARGET_HALTED) {
1013 LOG_WARNING("target not halted");
1014 return ERROR_TARGET_NOT_HALTED;
1015 }
1016
1017 /* sanitize arguments */
1018 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1019 return ERROR_COMMAND_SYNTAX_ERROR;
1020
1021 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1022 return ERROR_TARGET_UNALIGNED_ACCESS;
1023
1024 /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
1025 void *t = NULL;
1026
1027 if (size > 1) {
1028 t = malloc(count * size * sizeof(uint8_t));
1029 if (!t) {
1030 LOG_ERROR("Out of memory");
1031 return ERROR_FAIL;
1032 }
1033 } else
1034 t = buffer;
1035
1036 /* if noDMA off, use DMAACC mode for memory read */
1037 int retval;
1038 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1039 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, t);
1040 else
1041 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, t);
1042
1043 /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
1044 /* endianness, but byte array should represent target endianness */
1045 if (retval == ERROR_OK) {
1046 switch (size) {
1047 case 4:
1048 target_buffer_set_u32_array(target, buffer, count, t);
1049 break;
1050 case 2:
1051 target_buffer_set_u16_array(target, buffer, count, t);
1052 break;
1053 }
1054 }
1055
1056 if (size > 1)
1057 free(t);
1058
1059 return retval;
1060 }
1061
1062 static int mips_m4k_write_memory(struct target *target, target_addr_t address,
1063 uint32_t size, uint32_t count, const uint8_t *buffer)
1064 {
1065 struct mips32_common *mips32 = target_to_mips32(target);
1066 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1067
1068 LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1069 address, size, count);
1070
1071 if (target->state != TARGET_HALTED) {
1072 LOG_WARNING("target not halted");
1073 return ERROR_TARGET_NOT_HALTED;
1074 }
1075
1076 if (size == 4 && count > 32) {
1077 int retval = mips_m4k_bulk_write_memory(target, address, count, buffer);
1078 if (retval == ERROR_OK)
1079 return ERROR_OK;
1080 LOG_WARNING("Falling back to non-bulk write");
1081 }
1082
1083 /* sanitize arguments */
1084 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1085 return ERROR_COMMAND_SYNTAX_ERROR;
1086
1087 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1088 return ERROR_TARGET_UNALIGNED_ACCESS;
1089
1090 /** correct endianness if we have word or hword access */
1091 void *t = NULL;
1092 if (size > 1) {
1093 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1094 /* endianness, but byte array represents target endianness */
1095 t = malloc(count * size * sizeof(uint8_t));
1096 if (!t) {
1097 LOG_ERROR("Out of memory");
1098 return ERROR_FAIL;
1099 }
1100
1101 switch (size) {
1102 case 4:
1103 target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);
1104 break;
1105 case 2:
1106 target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);
1107 break;
1108 }
1109 buffer = t;
1110 }
1111
1112 /* if noDMA off, use DMAACC mode for memory write */
1113 int retval;
1114 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1115 retval = mips32_pracc_write_mem(ejtag_info, address, size, count, buffer);
1116 else
1117 retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
1118
1119 free(t);
1120
1121 if (retval != ERROR_OK)
1122 return retval;
1123
1124 return ERROR_OK;
1125 }
1126
1127 static int mips_m4k_init_target(struct command_context *cmd_ctx,
1128 struct target *target)
1129 {
1130 mips32_build_reg_cache(target);
1131
1132 return ERROR_OK;
1133 }
1134
1135 static int mips_m4k_init_arch_info(struct target *target,
1136 struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
1137 {
1138 struct mips32_common *mips32 = &mips_m4k->mips32;
1139
1140 mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
1141
1142 /* initialize mips4k specific info */
1143 mips32_init_arch_info(target, mips32, tap);
1144 mips32->arch_info = mips_m4k;
1145
1146 return ERROR_OK;
1147 }
1148
1149 static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
1150 {
1151 struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
1152
1153 mips_m4k_init_arch_info(target, mips_m4k, target->tap);
1154
1155 return ERROR_OK;
1156 }
1157
1158 static int mips_m4k_examine(struct target *target)
1159 {
1160 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1161 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1162
1163 if (!target_was_examined(target)) {
1164 int retval = mips_ejtag_get_idcode(ejtag_info);
1165 if (retval != ERROR_OK) {
1166 LOG_ERROR("idcode read failed");
1167 return retval;
1168 }
1169 if (((ejtag_info->idcode >> 1) & 0x7FF) == 0x29) {
1170 /* we are using a pic32mx so select ejtag port
1171 * as it is not selected by default */
1172 mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
1173 LOG_DEBUG("PIC32 Detected - using EJTAG Interface");
1174 mips_m4k->is_pic32mx = true;
1175 }
1176 }
1177
1178 /* init rest of ejtag interface */
1179 int retval = mips_ejtag_init(ejtag_info);
1180 if (retval != ERROR_OK)
1181 return retval;
1182
1183 return mips32_examine(target);
1184 }
1185
1186 static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
1187 uint32_t count, const uint8_t *buffer)
1188 {
1189 struct mips32_common *mips32 = target_to_mips32(target);
1190 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1191 struct working_area *fast_data_area;
1192 int retval;
1193 int write_t = 1;
1194
1195 LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
1196 address, count);
1197
1198 /* check alignment */
1199 if (address & 0x3u)
1200 return ERROR_TARGET_UNALIGNED_ACCESS;
1201
1202 if (!mips32->fast_data_area) {
1203 /* Get memory for block write handler
1204 * we preserve this area between calls and gain a speed increase
1205 * of about 3kb/sec when writing flash
1206 * this will be released/nulled by the system when the target is resumed or reset */
1207 retval = target_alloc_working_area(target,
1208 MIPS32_FASTDATA_HANDLER_SIZE,
1209 &mips32->fast_data_area);
1210 if (retval != ERROR_OK) {
1211 LOG_ERROR("No working area available");
1212 return retval;
1213 }
1214
1215 /* reset fastadata state so the algo get reloaded */
1216 ejtag_info->fast_access_save = -1;
1217 }
1218
1219 fast_data_area = mips32->fast_data_area;
1220
1221 if (address <= fast_data_area->address + fast_data_area->size &&
1222 fast_data_area->address <= address + count) {
1223 LOG_ERROR("fast_data (" TARGET_ADDR_FMT ") is within write area "
1224 "(" TARGET_ADDR_FMT "-" TARGET_ADDR_FMT ").",
1225 fast_data_area->address, address, address + count);
1226 LOG_ERROR("Change work-area-phys or load_image address!");
1227 return ERROR_FAIL;
1228 }
1229
1230 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1231 /* but byte array represents target endianness */
1232 uint32_t *t = NULL;
1233 t = malloc(count * sizeof(uint32_t));
1234 if (!t) {
1235 LOG_ERROR("Out of memory");
1236 return ERROR_FAIL;
1237 }
1238
1239 target_buffer_get_u32_array(target, buffer, count, t);
1240
1241 retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
1242 count, t);
1243
1244 free(t);
1245
1246 if (retval != ERROR_OK)
1247 LOG_ERROR("Fastdata access Failed");
1248
1249 return retval;
1250 }
1251
1252 static int mips_m4k_verify_pointer(struct command_invocation *cmd,
1253 struct mips_m4k_common *mips_m4k)
1254 {
1255 if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
1256 command_print(cmd, "target is not an MIPS_M4K");
1257 return ERROR_TARGET_INVALID;
1258 }
1259 return ERROR_OK;
1260 }
1261
1262 COMMAND_HANDLER(mips_m4k_handle_cp0_command)
1263 {
1264 int retval;
1265 struct target *target = get_current_target(CMD_CTX);
1266 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1267 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1268
1269 retval = mips_m4k_verify_pointer(CMD, mips_m4k);
1270 if (retval != ERROR_OK)
1271 return retval;
1272
1273 if (target->state != TARGET_HALTED) {
1274 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
1275 return ERROR_OK;
1276 }
1277
1278 /* two or more argument, access a single register/select (write if third argument is given) */
1279 if (CMD_ARGC < 2)
1280 return ERROR_COMMAND_SYNTAX_ERROR;
1281 else {
1282 uint32_t cp0_reg, cp0_sel;
1283 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1284 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1285
1286 if (CMD_ARGC == 2) {
1287 uint32_t value;
1288 retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
1289 if (retval != ERROR_OK) {
1290 command_print(CMD,
1291 "couldn't access reg %" PRIu32,
1292 cp0_reg);
1293 return ERROR_OK;
1294 }
1295 command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
1296 cp0_reg, cp0_sel, value);
1297
1298 } else if (CMD_ARGC == 3) {
1299 uint32_t value;
1300 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1301 retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
1302 if (retval != ERROR_OK) {
1303 command_print(CMD,
1304 "couldn't access cp0 reg %" PRIu32 ", select %" PRIu32,
1305 cp0_reg, cp0_sel);
1306 return ERROR_OK;
1307 }
1308 command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
1309 cp0_reg, cp0_sel, value);
1310 }
1311 }
1312
1313 return ERROR_OK;
1314 }
1315
1316 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
1317 {
1318 struct target *target = get_current_target(CMD_CTX);
1319 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1320 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1321
1322 if (CMD_ARGC == 1)
1323 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
1324 else if (CMD_ARGC > 1)
1325 return ERROR_COMMAND_SYNTAX_ERROR;
1326
1327 command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
1328 if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
1329 ejtag_info->mode = 0;
1330 command_print(CMD, "running in legacy mode");
1331 } else {
1332 ejtag_info->mode = 1;
1333 command_print(CMD, "running in fast queued mode");
1334 }
1335
1336 return ERROR_OK;
1337 }
1338
1339 static const struct command_registration mips_m4k_exec_command_handlers[] = {
1340 {
1341 .name = "cp0",
1342 .handler = mips_m4k_handle_cp0_command,
1343 .mode = COMMAND_EXEC,
1344 .usage = "regnum [value]",
1345 .help = "display/modify cp0 register",
1346 },
1347 {
1348 .name = "scan_delay",
1349 .handler = mips_m4k_handle_scan_delay_command,
1350 .mode = COMMAND_ANY,
1351 .help = "display/set scan delay in nano seconds",
1352 .usage = "[value]",
1353 },
1354 {
1355 .chain = smp_command_handlers,
1356 },
1357 COMMAND_REGISTRATION_DONE
1358 };
1359
1360 static const struct command_registration mips_m4k_command_handlers[] = {
1361 {
1362 .chain = mips32_command_handlers,
1363 },
1364 {
1365 .name = "mips_m4k",
1366 .mode = COMMAND_ANY,
1367 .help = "mips_m4k command group",
1368 .usage = "",
1369 .chain = mips_m4k_exec_command_handlers,
1370 },
1371 COMMAND_REGISTRATION_DONE
1372 };
1373
1374 struct target_type mips_m4k_target = {
1375 .name = "mips_m4k",
1376
1377 .poll = mips_m4k_poll,
1378 .arch_state = mips32_arch_state,
1379
1380 .halt = mips_m4k_halt,
1381 .resume = mips_m4k_resume,
1382 .step = mips_m4k_step,
1383
1384 .assert_reset = mips_m4k_assert_reset,
1385 .deassert_reset = mips_m4k_deassert_reset,
1386
1387 .get_gdb_reg_list = mips32_get_gdb_reg_list,
1388
1389 .read_memory = mips_m4k_read_memory,
1390 .write_memory = mips_m4k_write_memory,
1391 .checksum_memory = mips32_checksum_memory,
1392 .blank_check_memory = mips32_blank_check_memory,
1393
1394 .run_algorithm = mips32_run_algorithm,
1395
1396 .add_breakpoint = mips_m4k_add_breakpoint,
1397 .remove_breakpoint = mips_m4k_remove_breakpoint,
1398 .add_watchpoint = mips_m4k_add_watchpoint,
1399 .remove_watchpoint = mips_m4k_remove_watchpoint,
1400
1401 .commands = mips_m4k_command_handlers,
1402 .target_create = mips_m4k_target_create,
1403 .init_target = mips_m4k_init_target,
1404 .examine = mips_m4k_examine,
1405 };
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