1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2008 digenius technology GmbH. *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 ***************************************************************************/
10 #ifndef OPENOCD_TARGET_ARM11_H
11 #define OPENOCD_TARGET_ARM11_H
16 #define ARM11_TAP_DEFAULT TAP_INVALID
18 #define CHECK_RETVAL(action) \
20 int __retval = (action); \
21 if (__retval != ERROR_OK) { \
22 LOG_DEBUG("error while calling \"%s\"", \
28 /* bits from ARMv7 DIDR */
29 enum arm11_debug_version
{
30 ARM11_DEBUG_V6
= 0x01,
31 ARM11_DEBUG_V61
= 0x02,
32 ARM11_DEBUG_V7
= 0x03,
33 ARM11_DEBUG_V7_CP14
= 0x04,
39 /** Debug module state. */
41 struct arm11_sc7_action
*bpwp_actions
;
44 size_t brp
; /**< Number of Breakpoint Register Pairs from DIDR */
45 size_t free_brps
; /**< Number of breakpoints allocated */
47 uint32_t dscr
; /**< Last retrieved DSCR value. */
55 bool simulate_reset_on_next_halt
; /**< Perform cleanups of the ARM state on next halt **/
57 /* Per-core configurable options.
58 * NOTE that several of these boolean options should not exist
59 * once the relevant code is known to work correctly.
62 bool memwrite_error_fatal
;
66 /** Configured Vector Catch Register settings. */
69 struct arm_jtag jtag_info
;
72 static inline struct arm11_common
*target_to_arm11(struct target
*target
)
74 return container_of(target
->arch_info
, struct arm11_common
, arm
);
78 * ARM11 DBGTAP instructions
80 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
82 enum arm11_instructions
{
100 ARM11_SC7_WCR0
= 112,
103 #endif /* OPENOCD_TARGET_ARM11_H */