arm920t: memory writes were broken when MMU was disabled
[openocd.git] / src / target / armv7a.h
blob5814c13decf2e4f184b4f1df3f26d8b89b2ebd03
1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19 #ifndef ARMV7A_H
20 #define ARMV7A_H
22 #include "register.h"
23 #include "target.h"
24 #include "log.h"
25 #include "arm_adi_v5.h"
26 #include "armv4_5.h"
27 #include "armv4_5_mmu.h"
28 #include "armv4_5_cache.h"
30 typedef enum armv7a_mode
32 ARMV7A_MODE_USR = 16,
33 ARMV7A_MODE_FIQ = 17,
34 ARMV7A_MODE_IRQ = 18,
35 ARMV7A_MODE_SVC = 19,
36 ARMV7A_MODE_ABT = 23,
37 ARMV7A_MODE_UND = 27,
38 ARMV7A_MODE_SYS = 31,
39 ARMV7A_MODE_MON = 22,
40 ARMV7A_MODE_ANY = -1
41 } armv7a_t;
43 extern char **armv7a_mode_strings;
45 typedef enum armv7a_state
47 ARMV7A_STATE_ARM,
48 ARMV7A_STATE_THUMB,
49 ARMV7A_STATE_JAZELLE,
50 ARMV7A_STATE_THUMBEE,
51 } armv7a_state_t;
53 extern char *armv7a_state_strings[];
55 extern int armv7a_core_reg_map[8][17];
57 #define ARMV7A_CORE_REG_MODE(cache, mode, num) \
58 cache->reg_list[armv7a_core_reg_map[armv7a_mode_to_number(mode)][num]]
59 #define ARMV7A_CORE_REG_MODENUM(cache, mode, num) \
60 cache->reg_list[armv7a_core_reg_map[mode][num]]
62 enum
64 ARM_PC = 15,
65 ARM_CPSR = 16
68 /* offsets into armv4_5 core register cache */
69 enum
71 ARMV7A_CPSR = 31,
72 ARMV7A_SPSR_FIQ = 32,
73 ARMV7A_SPSR_IRQ = 33,
74 ARMV7A_SPSR_SVC = 34,
75 ARMV7A_SPSR_ABT = 35,
76 ARMV7A_SPSR_UND = 36
79 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
80 #define ARMV7_COMMON_MAGIC 0x0A450999
82 /* VA to PA translation operations opc2 values*/
83 #define V2PCWPR 0
84 #define V2PCWPW 1
85 #define V2PCWUR 2
86 #define V2PCWUW 3
87 #define V2POWPR 4
88 #define V2POWPW 5
89 #define V2POWUR 6
90 #define V2POWUW 7
92 typedef struct armv7a_common_s
94 int common_magic;
95 reg_cache_t *core_cache;
96 enum armv7a_mode core_mode;
97 enum armv7a_state core_state;
99 /* arm adp debug port */
100 swjdp_common_t swjdp_info;
102 /* Core Debug Unit */
103 uint32_t debug_base;
104 uint8_t debug_ap;
105 uint8_t memory_ap;
107 /* Cache and Memory Management Unit */
108 armv4_5_mmu_common_t armv4_5_mmu;
109 armv4_5_common_t armv4_5_common;
110 void *arch_info;
112 // int (*full_context)(struct target_s *target);
113 // int (*read_core_reg)(struct target_s *target, int num, enum armv7a_mode mode);
114 // int (*write_core_reg)(struct target_s *target, int num, enum armv7a_mode mode, u32 value);
115 int (*read_cp15)(struct target_s *target,
116 uint32_t op1, uint32_t op2,
117 uint32_t CRn, uint32_t CRm, uint32_t *value);
118 int (*write_cp15)(struct target_s *target,
119 uint32_t op1, uint32_t op2,
120 uint32_t CRn, uint32_t CRm, uint32_t value);
122 int (*examine_debug_reason)(target_t *target);
123 void (*pre_debug_entry)(target_t *target);
124 void (*post_debug_entry)(target_t *target);
126 void (*pre_restore_context)(target_t *target);
127 void (*post_restore_context)(target_t *target);
129 } armv7a_common_t;
131 typedef struct armv7a_algorithm_s
133 int common_magic;
135 enum armv7a_mode core_mode;
136 enum armv7a_state core_state;
137 } armv7a_algorithm_t;
139 typedef struct armv7a_core_reg_s
141 int num;
142 enum armv7a_mode mode;
143 target_t *target;
144 armv7a_common_t *armv7a_common;
145 } armv7a_core_reg_t;
147 int armv7a_arch_state(struct target_s *target);
148 reg_cache_t *armv7a_build_reg_cache(target_t *target,
149 armv7a_common_t *armv7a_common);
150 int armv7a_register_commands(struct command_context_s *cmd_ctx);
151 int armv7a_init_arch_info(target_t *target, armv7a_common_t *armv7a);
153 /* map psr mode bits to linear number */
154 static inline int armv7a_mode_to_number(enum armv7a_mode mode)
156 switch (mode)
158 case ARMV7A_MODE_USR: return 0; break;
159 case ARMV7A_MODE_FIQ: return 1; break;
160 case ARMV7A_MODE_IRQ: return 2; break;
161 case ARMV7A_MODE_SVC: return 3; break;
162 case ARMV7A_MODE_ABT: return 4; break;
163 case ARMV7A_MODE_UND: return 5; break;
164 case ARMV7A_MODE_SYS: return 6; break;
165 case ARMV7A_MODE_MON: return 7; break;
166 case ARMV7A_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
167 default:
168 LOG_ERROR("invalid mode value encountered, val %d", mode);
169 return -1;
173 /* map linear number to mode bits */
174 static inline enum armv7a_mode armv7a_number_to_mode(int number)
176 switch(number)
178 case 0: return ARMV7A_MODE_USR; break;
179 case 1: return ARMV7A_MODE_FIQ; break;
180 case 2: return ARMV7A_MODE_IRQ; break;
181 case 3: return ARMV7A_MODE_SVC; break;
182 case 4: return ARMV7A_MODE_ABT; break;
183 case 5: return ARMV7A_MODE_UND; break;
184 case 6: return ARMV7A_MODE_SYS; break;
185 case 7: return ARMV7A_MODE_MON; break;
186 default:
187 LOG_ERROR("mode index out of bounds");
188 return ARMV7A_MODE_ANY;
193 #endif /* ARMV4_5_H */