1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2009 by David Brownell *
5 ***************************************************************************/
7 #ifndef OPENOCD_TARGET_ARMV7A_H
8 #define OPENOCD_TARGET_ARMV7A_H
10 #include "arm_adi_v5.h"
11 #include "armv7a_cache.h"
13 #include "armv4_5_mmu.h"
14 #include "armv4_5_cache.h"
22 #define ARMV7_COMMON_MAGIC 0x0A450999U
24 /* VA to PA translation operations opc2 values*/
33 /* L210/L220 cache controller support */
34 struct armv7a_l2x_cache
{
39 struct armv7a_cachesize
{
40 /* cache dimensioning */
42 uint32_t associativity
;
45 /* info for set way operation on cache */
52 /* information about one architecture cache at any level */
53 struct armv7a_arch_cache
{
54 int ctype
; /* cache type, CLIDR encoding */
55 struct armv7a_cachesize d_u_size
; /* data cache */
56 struct armv7a_cachesize i_size
; /* instruction cache */
59 /* common cache information */
60 struct armv7a_cache_common
{
61 int info
; /* -1 invalid, else valid */
62 int loc
; /* level of coherency */
63 uint32_t dminline
; /* minimum d-cache linelen */
64 uint32_t iminline
; /* minimum i-cache linelen */
65 struct armv7a_arch_cache arch
[6]; /* cache info, L1 - L7 */
67 int d_u_cache_enabled
;
68 /* outer unified cache if some */
70 int (*flush_all_data_cache
)(struct target
*target
);
73 struct armv7a_mmu_common
{
74 /* following field mmu working way */
75 int32_t cached
; /* 0: not initialized, 1: initialized */
76 uint32_t ttbcr
; /* cache for ttbcr register */
78 uint32_t ttbr_mask
[2];
79 uint32_t ttbr_range
[2];
81 int (*read_physical_memory
)(struct target
*target
, target_addr_t address
, uint32_t size
,
82 uint32_t count
, uint8_t *buffer
);
83 struct armv7a_cache_common armv7a_cache
;
87 struct armv7a_common
{
88 unsigned int common_magic
;
91 struct reg_cache
*core_cache
;
95 target_addr_t debug_base
;
96 struct adiv5_ap
*debug_ap
;
98 uint8_t multi_processor_system
;
99 uint8_t multi_threading_processor
;
108 uint32_t implementor
;
110 /* cache specific to V7 Memory Management Unit compatible with v4_5*/
111 struct armv7a_mmu_common armv7a_mmu
;
113 int (*examine_debug_reason
)(struct target
*target
);
114 int (*post_debug_entry
)(struct target
*target
);
116 void (*pre_restore_context
)(struct target
*target
);
119 static inline struct armv7a_common
*
120 target_to_armv7a(struct target
*target
)
122 return container_of(target
->arch_info
, struct armv7a_common
, arm
);
125 static inline bool is_armv7a(struct armv7a_common
*armv7a
)
127 return armv7a
->common_magic
== ARMV7_COMMON_MAGIC
;
131 /* register offsets from armv7a.debug_base */
133 /* See ARMv7a arch spec section C10.2 */
134 #define CPUDBG_DIDR 0x000
136 /* See ARMv7a arch spec section C10.3 */
137 #define CPUDBG_WFAR 0x018
138 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
139 #define CPUDBG_DSCR 0x088
140 #define CPUDBG_DRCR 0x090
141 #define CPUDBG_PRCR 0x310
142 #define CPUDBG_PRSR 0x314
144 /* See ARMv7a arch spec section C10.4 */
145 #define CPUDBG_DTRRX 0x080
146 #define CPUDBG_ITR 0x084
147 #define CPUDBG_DTRTX 0x08c
149 /* See ARMv7a arch spec section C10.5 */
150 #define CPUDBG_BVR_BASE 0x100
151 #define CPUDBG_BCR_BASE 0x140
152 #define CPUDBG_WVR_BASE 0x180
153 #define CPUDBG_WCR_BASE 0x1C0
154 #define CPUDBG_VCR 0x01C
156 /* See ARMv7a arch spec section C10.6 */
157 #define CPUDBG_OSLAR 0x300
158 #define CPUDBG_OSLSR 0x304
159 #define CPUDBG_OSSRR 0x308
160 #define CPUDBG_ECR 0x024
162 /* See ARMv7a arch spec section C10.7 */
163 #define CPUDBG_DSCCR 0x028
164 #define CPUDBG_DSMCR 0x02C
166 /* See ARMv7a arch spec section C10.8 */
167 #define CPUDBG_AUTHSTATUS 0xFB8
169 /* See ARMv7a arch spec DDI 0406C C11.10 */
170 #define CPUDBG_ID_PFR1 0xD24
172 /* Masks for Vector Catch register */
173 #define DBG_VCR_FIQ_MASK ((1 << 31) | (1 << 7))
174 #define DBG_VCR_IRQ_MASK ((1 << 30) | (1 << 6))
175 #define DBG_VCR_DATA_ABORT_MASK ((1 << 28) | (1 << 4))
176 #define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3))
177 #define DBG_VCR_SVC_MASK ((1 << 26) | (1 << 2))
179 /* Masks for Multiprocessor Affinity Register */
180 #define MPIDR_MP_EXT (1UL << 31)
182 int armv7a_arch_state(struct target
*target
);
183 int armv7a_identify_cache(struct target
*target
);
184 int armv7a_init_arch_info(struct target
*target
, struct armv7a_common
*armv7a
);
186 int armv7a_handle_cache_info_command(struct command_invocation
*cmd
,
187 struct armv7a_cache_common
*armv7a_cache
);
188 int armv7a_read_ttbcr(struct target
*target
);
190 extern const struct command_registration armv7a_command_handlers
[];
192 #endif /* OPENOCD_TARGET_ARMV7A_H */