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STM32: flash loader cleanup
[openocd.git] / src / flash / nand / davinci.c
blob96cbfeae75b23ce09a9f106956872932ebe62491
1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19
20 /*
21 * DaVinci family NAND controller support for OpenOCD.
22 *
23 * This driver uses hardware ECC (1-bit or 4-bit) unless
24 * the chip is accessed in "raw" mode.
25 */
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include "arm_io.h"
33 #include <target/target.h>
34
35 enum ecc {
36 HWECC1, /* all controllers support 1-bit ECC */
37 HWECC4, /* newer chips also have 4-bit ECC hardware */
38 HWECC4_INFIX, /* avoid this layout, except maybe for boot code */
39 };
40
41 struct davinci_nand {
42 struct target *target;
43
44 uint8_t chipsel; /* chipselect 0..3 == CS2..CS5 */
45 uint8_t eccmode;
46
47 /* Async EMIF controller base */
48 uint32_t aemif;
49
50 /* NAND chip addresses */
51 uint32_t data; /* without CLE or ALE */
52 uint32_t cmd; /* with CLE */
53 uint32_t addr; /* with ALE */
54
55 /* write acceleration */
56 struct arm_nand_data io;
57
58 /* page i/o for the relevant flavor of hardware ECC */
59 int (*read_page)(struct nand_device *nand, uint32_t page,
60 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
61 int (*write_page)(struct nand_device *nand, uint32_t page,
62 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
63 };
64
65 #define NANDFCR 0x60 /* flash control register */
66 #define NANDFSR 0x64 /* flash status register */
67 #define NANDFECC 0x70 /* 1-bit ECC data, CS0, 1st of 4 */
68 #define NAND4BITECCLOAD 0xbc /* 4-bit ECC, load saved values */
69 #define NAND4BITECC 0xc0 /* 4-bit ECC data, 1st of 4 */
70 #define NANDERRADDR 0xd0 /* 4-bit ECC err addr, 1st of 2 */
71 #define NANDERRVAL 0xd8 /* 4-bit ECC err value, 1st of 2 */
72
73 static int halted(struct target *target, const char *label)
74 {
75 if (target->state == TARGET_HALTED)
76 return true;
77
78 LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
79 return false;
80 }
81
82 static int davinci_init(struct nand_device *nand)
83 {
84 struct davinci_nand *info = nand->controller_priv;
85 struct target *target = info->target;
86 uint32_t nandfcr;
87
88 if (!halted(target, "init"))
89 return ERROR_NAND_OPERATION_FAILED;
90
91 /* We require something else to have configured AEMIF to talk
92 * to NAND chip in this range (including timings and width).
93 */
94 target_read_u32(target, info->aemif + NANDFCR, &nandfcr);
95 if (!(nandfcr & (1 << info->chipsel))) {
96 LOG_ERROR("chip address %08" PRIx32 " not NAND-enabled?", info->data);
97 return ERROR_NAND_OPERATION_FAILED;
98 }
99
100 /* REVISIT verify: AxCR must be in 8-bit mode, since that's all we
101 * tested. 16 bit support should work too; but not with 4-bit ECC.
102 */
103
104 return ERROR_OK;
105 }
106
107 static int davinci_reset(struct nand_device *nand)
108 {
109 return ERROR_OK;
110 }
111
112 static int davinci_nand_ready(struct nand_device *nand, int timeout)
113 {
114 struct davinci_nand *info = nand->controller_priv;
115 struct target *target = info->target;
116 uint32_t nandfsr;
117
118 /* NOTE: return code is zero/error, else success; not ERROR_* */
119
120 if (!halted(target, "ready"))
121 return 0;
122
123 do {
124 target_read_u32(target, info->aemif + NANDFSR, &nandfsr);
125
126 if (nandfsr & 0x01)
127 return 1;
128
129 alive_sleep(1);
130 } while (timeout-- > 0);
131
132 return 0;
133 }
134
135 static int davinci_command(struct nand_device *nand, uint8_t command)
136 {
137 struct davinci_nand *info = nand->controller_priv;
138 struct target *target = info->target;
139
140 if (!halted(target, "command"))
141 return ERROR_NAND_OPERATION_FAILED;
142
143 target_write_u8(target, info->cmd, command);
144 return ERROR_OK;
145 }
146
147 static int davinci_address(struct nand_device *nand, uint8_t address)
148 {
149 struct davinci_nand *info = nand->controller_priv;
150 struct target *target = info->target;
151
152 if (!halted(target, "address"))
153 return ERROR_NAND_OPERATION_FAILED;
154
155 target_write_u8(target, info->addr, address);
156 return ERROR_OK;
157 }
158
159 static int davinci_write_data(struct nand_device *nand, uint16_t data)
160 {
161 struct davinci_nand *info = nand->controller_priv;
162 struct target *target = info->target;
163
164 if (!halted(target, "write_data"))
165 return ERROR_NAND_OPERATION_FAILED;
166
167 target_write_u8(target, info->data, data);
168 return ERROR_OK;
169 }
170
171 static int davinci_read_data(struct nand_device *nand, void *data)
172 {
173 struct davinci_nand *info = nand->controller_priv;
174 struct target *target = info->target;
175
176 if (!halted(target, "read_data"))
177 return ERROR_NAND_OPERATION_FAILED;
178
179 target_read_u8(target, info->data, data);
180 return ERROR_OK;
181 }
182
183 /* REVISIT a bit of native code should let block reads be MUCH faster */
184
185 static int davinci_read_block_data(struct nand_device *nand,
186 uint8_t *data, int data_size)
187 {
188 struct davinci_nand *info = nand->controller_priv;
189 struct target *target = info->target;
190 uint32_t nfdata = info->data;
191 uint32_t tmp;
192
193 if (!halted(target, "read_block"))
194 return ERROR_NAND_OPERATION_FAILED;
195
196 while (data_size >= 4) {
197 target_read_u32(target, nfdata, &tmp);
198
199 data[0] = tmp;
200 data[1] = tmp >> 8;
201 data[2] = tmp >> 16;
202 data[3] = tmp >> 24;
203
204 data_size -= 4;
205 data += 4;
206 }
207
208 while (data_size > 0) {
209 target_read_u8(target, nfdata, data);
210
211 data_size -= 1;
212 data += 1;
213 }
214
215 return ERROR_OK;
216 }
217
218 static int davinci_write_block_data(struct nand_device *nand,
219 uint8_t *data, int data_size)
220 {
221 struct davinci_nand *info = nand->controller_priv;
222 struct target *target = info->target;
223 uint32_t nfdata = info->data;
224 uint32_t tmp;
225 int status;
226
227 if (!halted(target, "write_block"))
228 return ERROR_NAND_OPERATION_FAILED;
229
230 /* try the fast way first */
231 status = arm_nandwrite(&info->io, data, data_size);
232 if (status != ERROR_NAND_NO_BUFFER)
233 return status;
234
235 /* else do it slowly */
236 while (data_size >= 4) {
237 tmp = le_to_h_u32(data);
238 target_write_u32(target, nfdata, tmp);
239
240 data_size -= 4;
241 data += 4;
242 }
243
244 while (data_size > 0) {
245 target_write_u8(target, nfdata, *data);
246
247 data_size -= 1;
248 data += 1;
249 }
250
251 return ERROR_OK;
252 }
253
254 static int davinci_write_page(struct nand_device *nand, uint32_t page,
255 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
256 {
257 struct davinci_nand *info = nand->controller_priv;
258 uint8_t *ooballoc = NULL;
259 int status;
260
261 if (!nand->device)
262 return ERROR_NAND_DEVICE_NOT_PROBED;
263 if (!halted(info->target, "write_page"))
264 return ERROR_NAND_OPERATION_FAILED;
265
266 /* Always write both data and OOB ... we are not "raw" I/O! */
267 if (!data) {
268 LOG_ERROR("Missing NAND data; try 'nand raw_access enable'\n");
269 return ERROR_NAND_OPERATION_FAILED;
270 }
271
272 /* If we're not given OOB, write 0xff where we don't write ECC codes. */
273 switch (nand->page_size) {
274 case 512:
275 oob_size = 16;
276 break;
277 case 2048:
278 oob_size = 64;
279 break;
280 case 4096:
281 oob_size = 128;
282 break;
283 default:
284 return ERROR_NAND_OPERATION_FAILED;
285 }
286 if (!oob) {
287 ooballoc = malloc(oob_size);
288 if (!ooballoc)
289 return ERROR_NAND_OPERATION_FAILED;
290 oob = ooballoc;
291 memset(oob, 0x0ff, oob_size);
292 }
293
294 /* REVISIT avoid wasting SRAM: unless nand->use_raw is set,
295 * use 512 byte chunks. Read side support will often want
296 * to include oob_size ...
297 */
298 info->io.chunk_size = nand->page_size;
299
300 status = info->write_page(nand, page, data, data_size, oob, oob_size);
301 free(ooballoc);
302 return status;
303 }
304
305 static int davinci_read_page(struct nand_device *nand, uint32_t page,
306 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
307 {
308 struct davinci_nand *info = nand->controller_priv;
309
310 if (!nand->device)
311 return ERROR_NAND_DEVICE_NOT_PROBED;
312 if (!halted(info->target, "read_page"))
313 return ERROR_NAND_OPERATION_FAILED;
314
315 return info->read_page(nand, page, data, data_size, oob, oob_size);
316 }
317
318 static void davinci_write_pagecmd(struct nand_device *nand, uint8_t cmd, uint32_t page)
319 {
320 struct davinci_nand *info = nand->controller_priv;
321 struct target *target = info->target;
322 int page3 = nand->address_cycles - (nand->page_size == 512);
323
324 /* write command ({page,otp}x{read,program} */
325 target_write_u8(target, info->cmd, cmd);
326
327 /* column address (beginning-of-page) */
328 target_write_u8(target, info->addr, 0);
329 if (nand->page_size > 512)
330 target_write_u8(target, info->addr, 0);
331
332 /* page address */
333 target_write_u8(target, info->addr, page);
334 target_write_u8(target, info->addr, page >> 8);
335 if (page3)
336 target_write_u8(target, info->addr, page >> 16);
337 if (page3 == 2)
338 target_write_u8(target, info->addr, page >> 24);
339 }
340
341 static int davinci_writepage_tail(struct nand_device *nand,
342 uint8_t *oob, uint32_t oob_size)
343 {
344 struct davinci_nand *info = nand->controller_priv;
345 struct target *target = info->target;
346 uint8_t status;
347
348 if (oob_size)
349 davinci_write_block_data(nand, oob, oob_size);
350
351 /* non-cachemode page program */
352 target_write_u8(target, info->cmd, NAND_CMD_PAGEPROG);
353
354 if (!davinci_nand_ready(nand, 100))
355 return ERROR_NAND_OPERATION_TIMEOUT;
356
357 if (nand_read_status(nand, &status) != ERROR_OK) {
358 LOG_ERROR("couldn't read status");
359 return ERROR_NAND_OPERATION_FAILED;
360 }
361
362 if (status & NAND_STATUS_FAIL) {
363 LOG_ERROR("write operation failed, status: 0x%02x", status);
364 return ERROR_NAND_OPERATION_FAILED;
365 }
366
367 return ERROR_OK;
368 }
369
370 /*
371 * All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
372 */
373 static int davinci_write_page_ecc1(struct nand_device *nand, uint32_t page,
374 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
375 {
376 unsigned oob_offset;
377 struct davinci_nand *info = nand->controller_priv;
378 struct target *target = info->target;
379 const uint32_t fcr_addr = info->aemif + NANDFCR;
380 const uint32_t ecc1_addr = info->aemif + NANDFECC + (4 * info->chipsel);
381 uint32_t fcr, ecc1;
382
383 /* Write contiguous ECC bytes starting at specified offset.
384 * NOTE: Linux reserves twice as many bytes as we need; and
385 * for 16-bit OOB, those extra bytes are discontiguous.
386 */
387 switch (nand->page_size) {
388 case 512:
389 oob_offset = 0;
390 break;
391 case 2048:
392 oob_offset = 40;
393 break;
394 default:
395 oob_offset = 80;
396 break;
397 }
398
399 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
400
401 /* scrub any old ECC state */
402 target_read_u32(target, ecc1_addr, &ecc1);
403
404 target_read_u32(target, fcr_addr, &fcr);
405 fcr |= 1 << (8 + info->chipsel);
406
407 do {
408 /* set "start csX 1bit ecc" bit */
409 target_write_u32(target, fcr_addr, fcr);
410
411 /* write 512 bytes */
412 davinci_write_block_data(nand, data, 512);
413 data += 512;
414 data_size -= 512;
415
416 /* read the ecc, pack to 3 bytes, and invert so the ecc
417 * in an erased block is correct
418 */
419 target_read_u32(target, ecc1_addr, &ecc1);
420 ecc1 = (ecc1 & 0x0fff) | ((ecc1 & 0x0fff0000) >> 4);
421 ecc1 = ~ecc1;
422
423 /* save correct ECC code into oob data */
424 oob[oob_offset++] = (uint8_t)(ecc1);
425 oob[oob_offset++] = (uint8_t)(ecc1 >> 8);
426 oob[oob_offset++] = (uint8_t)(ecc1 >> 16);
427
428 } while (data_size);
429
430 /* write OOB into spare area */
431 return davinci_writepage_tail(nand, oob, oob_size);
432 }
433
434 /*
435 * Preferred "new style" ECC layout for use with 4-bit ECC. This somewhat
436 * slows down large page reads done with error correction (since the OOB
437 * is read first, so its ECC data can be used incrementally), but the
438 * manufacturer bad block markers are safe. Contrast: old "infix" style.
439 */
440 static int davinci_write_page_ecc4(struct nand_device *nand, uint32_t page,
441 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
442 {
443 static const uint8_t ecc512[] = {
444 0, 1, 2, 3, 4, /* 5== mfr badblock */
445 6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15,
446 };
447 static const uint8_t ecc2048[] = {
448 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
449 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
450 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
451 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
452 };
453 static const uint8_t ecc4096[] = {
454 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
455 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
456 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
457 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
458 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
459 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
460 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
461 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
462 };
463
464 struct davinci_nand *info = nand->controller_priv;
465 const uint8_t *l;
466 struct target *target = info->target;
467 const uint32_t fcr_addr = info->aemif + NANDFCR;
468 const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
469 uint32_t fcr, ecc4;
470
471 /* Use the same ECC layout Linux uses. For small page chips
472 * it's a bit cramped.
473 *
474 * NOTE: at this writing, 4KB pages have issues in Linux
475 * because they need more than 64 bytes of ECC data, which
476 * the standard ECC logic can't handle.
477 */
478 switch (nand->page_size) {
479 case 512:
480 l = ecc512;
481 break;
482 case 2048:
483 l = ecc2048;
484 break;
485 default:
486 l = ecc4096;
487 break;
488 }
489
490 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
491
492 /* scrub any old ECC state */
493 target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
494
495 target_read_u32(target, fcr_addr, &fcr);
496 fcr &= ~(0x03 << 4);
497 fcr |= (1 << 12) | (info->chipsel << 4);
498
499 do {
500 uint32_t raw_ecc[4], *p;
501 int i;
502
503 /* start 4bit ecc on csX */
504 target_write_u32(target, fcr_addr, fcr);
505
506 /* write 512 bytes */
507 davinci_write_block_data(nand, data, 512);
508 data += 512;
509 data_size -= 512;
510
511 /* read the ecc, then save it into 10 bytes in the oob */
512 for (i = 0; i < 4; i++) {
513 target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
514 raw_ecc[i] &= 0x03ff03ff;
515 }
516 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
517 oob[*l++] = p[0] & 0xff;
518 oob[*l++] = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
519 oob[*l++] = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
520 oob[*l++] = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
521 oob[*l++] = (p[1] >> 18) & 0xff;
522 }
523
524 } while (data_size);
525
526 /* write OOB into spare area */
527 return davinci_writepage_tail(nand, oob, oob_size);
528 }
529
530 /*
531 * "Infix" OOB ... like Linux ECC_HW_SYNDROME. Avoided because it trashes
532 * manufacturer bad block markers, except on small page chips. Once you
533 * write to a page using this scheme, you need specialized code to update
534 * it (code which ignores now-invalid bad block markers).
535 *
536 * This is needed *only* to support older firmware. Older ROM Boot Loaders
537 * need it to read their second stage loader (UBL) into SRAM, but from then
538 * on the whole system can use the cleaner non-infix layouts. Systems with
539 * older second stage loaders (ABL/U-Boot, etc) or other system software
540 * (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
541 */
542 static int davinci_write_page_ecc4infix(struct nand_device *nand, uint32_t page,
543 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
544 {
545 struct davinci_nand *info = nand->controller_priv;
546 struct target *target = info->target;
547 const uint32_t fcr_addr = info->aemif + NANDFCR;
548 const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
549 uint32_t fcr, ecc4;
550
551 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
552
553 /* scrub any old ECC state */
554 target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
555
556 target_read_u32(target, fcr_addr, &fcr);
557 fcr &= ~(0x03 << 4);
558 fcr |= (1 << 12) | (info->chipsel << 4);
559
560 do {
561 uint32_t raw_ecc[4], *p;
562 uint8_t *l;
563 int i;
564
565 /* start 4bit ecc on csX */
566 target_write_u32(target, fcr_addr, fcr);
567
568 /* write 512 bytes */
569 davinci_write_block_data(nand, data, 512);
570 data += 512;
571 data_size -= 512;
572
573 /* read the ecc */
574 for (i = 0; i < 4; i++) {
575 target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
576 raw_ecc[i] &= 0x03ff03ff;
577 }
578
579 /* skip 6 bytes of prepad, then pack 10 packed ecc bytes */
580 for (i = 0, l = oob + 6, p = raw_ecc; i < 2; i++, p += 2) {
581 *l++ = p[0] & 0xff;
582 *l++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
583 *l++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
584 *l++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
585 *l++ = (p[1] >> 18) & 0xff;
586 }
587
588 /* write this "out-of-band" data -- infix */
589 davinci_write_block_data(nand, oob, 16);
590 oob += 16;
591 oob_size -= 16;
592
593 } while (data_size);
594
595 /* the last data and OOB writes included the spare area */
596 return davinci_writepage_tail(nand, NULL, 0);
597 }
598
599 static int davinci_read_page_ecc4infix(struct nand_device *nand, uint32_t page,
600 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
601 {
602 davinci_write_pagecmd(nand, NAND_CMD_READ0, page);
603
604 /* large page devices need a start command */
605 if (nand->page_size > 512)
606 davinci_command(nand, NAND_CMD_READSTART);
607
608 if (!davinci_nand_ready(nand, 100))
609 return ERROR_NAND_OPERATION_TIMEOUT;
610
611 /* NOTE: not bothering to compute and use ECC data for now */
612
613 do {
614 /* write 512 bytes */
615 davinci_read_block_data(nand, data, 512);
616 data += 512;
617 data_size -= 512;
618
619 /* read this "out-of-band" data -- infix */
620 davinci_read_block_data(nand, oob, 16);
621 oob += 16;
622 oob_size -= 16;
623 } while (data_size);
624
625 return ERROR_OK;
626 }
627
628 NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command)
629 {
630 struct davinci_nand *info;
631 struct target *target;
632 unsigned long chip, aemif;
633 enum ecc eccmode;
634 int chipsel;
635
636 /* arguments:
637 * - "davinci"
638 * - target
639 * - nand chip address
640 * - ecc mode
641 * - aemif address
642 * Plus someday, optionally, ALE and CLE masks.
643 */
644 if (CMD_ARGC < 5) {
645 LOG_ERROR("parameters: %s target "
646 "chip_addr hwecc_mode aemif_addr",
647 CMD_ARGV[0]);
648 goto fail;
649 }
650
651 target = get_target(CMD_ARGV[1]);
652 if (!target) {
653 LOG_ERROR("invalid target %s", CMD_ARGV[1]);
654 goto fail;
655 }
656
657 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip);
658 if (chip == 0) {
659 LOG_ERROR("Invalid NAND chip address %s", CMD_ARGV[2]);
660 goto fail;
661 }
662
663 if (strcmp(CMD_ARGV[3], "hwecc1") == 0)
664 eccmode = HWECC1;
665 else if (strcmp(CMD_ARGV[3], "hwecc4") == 0)
666 eccmode = HWECC4;
667 else if (strcmp(CMD_ARGV[3], "hwecc4_infix") == 0)
668 eccmode = HWECC4_INFIX;
669 else {
670 LOG_ERROR("Invalid ecc mode %s", CMD_ARGV[3]);
671 goto fail;
672 }
673
674 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[4], aemif);
675 if (aemif == 0) {
676 LOG_ERROR("Invalid AEMIF controller address %s", CMD_ARGV[4]);
677 goto fail;
678 }
679
680 /* REVISIT what we'd *like* to do is look up valid ranges using
681 * target-specific declarations, and not even need to pass the
682 * AEMIF controller address.
683 */
684 if (aemif == 0x01e00000 /* dm6446, dm357 */
685 || aemif == 0x01e10000 /* dm335, dm355 */
686 || aemif == 0x01d10000 /* dm365 */
687 ) {
688 if (chip < 0x02000000 || chip >= 0x0a000000) {
689 LOG_ERROR("NAND address %08lx out of range?", chip);
690 goto fail;
691 }
692 chipsel = (chip - 0x02000000) >> 25;
693 } else {
694 LOG_ERROR("unrecognized AEMIF controller address %08lx", aemif);
695 goto fail;
696 }
697
698 info = calloc(1, sizeof *info);
699 if (info == NULL)
700 goto fail;
701
702 info->target = target;
703 info->eccmode = eccmode;
704 info->chipsel = chipsel;
705 info->aemif = aemif;
706 info->data = chip;
707 info->cmd = chip | 0x10;
708 info->addr = chip | 0x08;
709
710 nand->controller_priv = info;
711
712 info->io.target = target;
713 info->io.data = info->data;
714 info->io.op = ARM_NAND_NONE;
715
716 /* NOTE: for now we don't do any error correction on read.
717 * Nothing else in OpenOCD currently corrects read errors,
718 * and in any case it's *writing* that we care most about.
719 */
720 info->read_page = nand_read_page_raw;
721
722 switch (eccmode) {
723 case HWECC1:
724 /* ECC_HW, 1-bit corrections, 3 bytes ECC per 512 data bytes */
725 info->write_page = davinci_write_page_ecc1;
726 break;
727 case HWECC4:
728 /* ECC_HW, 4-bit corrections, 10 bytes ECC per 512 data bytes */
729 info->write_page = davinci_write_page_ecc4;
730 break;
731 case HWECC4_INFIX:
732 /* Same 4-bit ECC HW, with problematic page/ecc layout */
733 info->read_page = davinci_read_page_ecc4infix;
734 info->write_page = davinci_write_page_ecc4infix;
735 break;
736 }
737
738 return ERROR_OK;
739
740 fail:
741 return ERROR_NAND_OPERATION_FAILED;
742 }
743
744 struct nand_flash_controller davinci_nand_controller = {
745 .name = "davinci",
746 .nand_device_command = davinci_nand_device_command,
747 .init = davinci_init,
748 .reset = davinci_reset,
749 .command = davinci_command,
750 .address = davinci_address,
751 .write_data = davinci_write_data,
752 .read_data = davinci_read_data,
753 .write_page = davinci_write_page,
754 .read_page = davinci_read_page,
755 .write_block_data = davinci_write_block_data,
756 .read_block_data = davinci_read_block_data,
757 .nand_ready = davinci_nand_ready,
758 };
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