1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2009 by David Brownell *
5 ***************************************************************************/
8 * DaVinci family NAND controller support for OpenOCD.
10 * This driver uses hardware ECC (1-bit or 4-bit) unless
11 * the chip is accessed in "raw" mode.
20 #include <target/target.h>
23 HWECC1
, /* all controllers support 1-bit ECC */
24 HWECC4
, /* newer chips also have 4-bit ECC hardware */
25 HWECC4_INFIX
, /* avoid this layout, except maybe for boot code */
29 uint8_t chipsel
; /* chipselect 0..3 == CS2..CS5 */
32 /* Async EMIF controller base */
35 /* NAND chip addresses */
36 uint32_t data
; /* without CLE or ALE */
37 uint32_t cmd
; /* with CLE */
38 uint32_t addr
; /* with ALE */
40 /* write acceleration */
41 struct arm_nand_data io
;
43 /* page i/o for the relevant flavor of hardware ECC */
44 int (*read_page
)(struct nand_device
*nand
, uint32_t page
,
45 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
);
46 int (*write_page
)(struct nand_device
*nand
, uint32_t page
,
47 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
);
50 #define NANDFCR 0x60 /* flash control register */
51 #define NANDFSR 0x64 /* flash status register */
52 #define NANDFECC 0x70 /* 1-bit ECC data, CS0, 1st of 4 */
53 #define NAND4BITECCLOAD 0xbc /* 4-bit ECC, load saved values */
54 #define NAND4BITECC 0xc0 /* 4-bit ECC data, 1st of 4 */
55 #define NANDERRADDR 0xd0 /* 4-bit ECC err addr, 1st of 2 */
56 #define NANDERRVAL 0xd8 /* 4-bit ECC err value, 1st of 2 */
58 static int halted(struct target
*target
, const char *label
)
60 if (target
->state
== TARGET_HALTED
)
63 LOG_ERROR("Target must be halted to use NAND controller (%s)", label
);
67 static int davinci_init(struct nand_device
*nand
)
69 struct davinci_nand
*info
= nand
->controller_priv
;
70 struct target
*target
= nand
->target
;
73 if (!halted(target
, "init"))
74 return ERROR_NAND_OPERATION_FAILED
;
76 /* We require something else to have configured AEMIF to talk
77 * to NAND chip in this range (including timings and width).
79 target_read_u32(target
, info
->aemif
+ NANDFCR
, &nandfcr
);
80 if (!(nandfcr
& (1 << info
->chipsel
))) {
81 LOG_ERROR("chip address %08" PRIx32
" not NAND-enabled?", info
->data
);
82 return ERROR_NAND_OPERATION_FAILED
;
85 /* REVISIT verify: AxCR must be in 8-bit mode, since that's all we
86 * tested. 16 bit support should work too; but not with 4-bit ECC.
92 static int davinci_reset(struct nand_device
*nand
)
97 static int davinci_nand_ready(struct nand_device
*nand
, int timeout
)
99 struct davinci_nand
*info
= nand
->controller_priv
;
100 struct target
*target
= nand
->target
;
103 /* NOTE: return code is zero/error, else success; not ERROR_* */
105 if (!halted(target
, "ready"))
109 target_read_u32(target
, info
->aemif
+ NANDFSR
, &nandfsr
);
115 } while (timeout
-- > 0);
120 static int davinci_command(struct nand_device
*nand
, uint8_t command
)
122 struct davinci_nand
*info
= nand
->controller_priv
;
123 struct target
*target
= nand
->target
;
125 if (!halted(target
, "command"))
126 return ERROR_NAND_OPERATION_FAILED
;
128 target_write_u8(target
, info
->cmd
, command
);
132 static int davinci_address(struct nand_device
*nand
, uint8_t address
)
134 struct davinci_nand
*info
= nand
->controller_priv
;
135 struct target
*target
= nand
->target
;
137 if (!halted(target
, "address"))
138 return ERROR_NAND_OPERATION_FAILED
;
140 target_write_u8(target
, info
->addr
, address
);
144 static int davinci_write_data(struct nand_device
*nand
, uint16_t data
)
146 struct davinci_nand
*info
= nand
->controller_priv
;
147 struct target
*target
= nand
->target
;
149 if (!halted(target
, "write_data"))
150 return ERROR_NAND_OPERATION_FAILED
;
152 target_write_u8(target
, info
->data
, data
);
156 static int davinci_read_data(struct nand_device
*nand
, void *data
)
158 struct davinci_nand
*info
= nand
->controller_priv
;
159 struct target
*target
= nand
->target
;
161 if (!halted(target
, "read_data"))
162 return ERROR_NAND_OPERATION_FAILED
;
164 target_read_u8(target
, info
->data
, data
);
168 /* REVISIT a bit of native code should let block reads be MUCH faster */
170 static int davinci_read_block_data(struct nand_device
*nand
,
171 uint8_t *data
, int data_size
)
173 struct davinci_nand
*info
= nand
->controller_priv
;
174 struct target
*target
= nand
->target
;
175 uint32_t nfdata
= info
->data
;
178 if (!halted(target
, "read_block"))
179 return ERROR_NAND_OPERATION_FAILED
;
181 while (data_size
>= 4) {
182 target_read_u32(target
, nfdata
, &tmp
);
193 while (data_size
> 0) {
194 target_read_u8(target
, nfdata
, data
);
203 static int davinci_write_block_data(struct nand_device
*nand
,
204 uint8_t *data
, int data_size
)
206 struct davinci_nand
*info
= nand
->controller_priv
;
207 struct target
*target
= nand
->target
;
208 uint32_t nfdata
= info
->data
;
212 if (!halted(target
, "write_block"))
213 return ERROR_NAND_OPERATION_FAILED
;
215 /* try the fast way first */
216 status
= arm_nandwrite(&info
->io
, data
, data_size
);
217 if (status
!= ERROR_NAND_NO_BUFFER
)
220 /* else do it slowly */
221 while (data_size
>= 4) {
222 tmp
= le_to_h_u32(data
);
223 target_write_u32(target
, nfdata
, tmp
);
229 while (data_size
> 0) {
230 target_write_u8(target
, nfdata
, *data
);
239 static int davinci_write_page(struct nand_device
*nand
, uint32_t page
,
240 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
242 struct davinci_nand
*info
= nand
->controller_priv
;
243 uint8_t *ooballoc
= NULL
;
247 return ERROR_NAND_DEVICE_NOT_PROBED
;
248 if (!halted(nand
->target
, "write_page"))
249 return ERROR_NAND_OPERATION_FAILED
;
251 /* Always write both data and OOB ... we are not "raw" I/O! */
253 LOG_ERROR("Missing NAND data; try 'nand raw_access enable'");
254 return ERROR_NAND_OPERATION_FAILED
;
257 /* If we're not given OOB, write 0xff where we don't write ECC codes. */
258 switch (nand
->page_size
) {
269 return ERROR_NAND_OPERATION_FAILED
;
272 ooballoc
= malloc(oob_size
);
274 return ERROR_NAND_OPERATION_FAILED
;
276 memset(oob
, 0x0ff, oob_size
);
279 /* REVISIT avoid wasting SRAM: unless nand->use_raw is set,
280 * use 512 byte chunks. Read side support will often want
281 * to include oob_size ...
283 info
->io
.chunk_size
= nand
->page_size
;
285 status
= info
->write_page(nand
, page
, data
, data_size
, oob
, oob_size
);
290 static int davinci_read_page(struct nand_device
*nand
, uint32_t page
,
291 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
293 struct davinci_nand
*info
= nand
->controller_priv
;
296 return ERROR_NAND_DEVICE_NOT_PROBED
;
297 if (!halted(nand
->target
, "read_page"))
298 return ERROR_NAND_OPERATION_FAILED
;
300 return info
->read_page(nand
, page
, data
, data_size
, oob
, oob_size
);
303 static void davinci_write_pagecmd(struct nand_device
*nand
, uint8_t cmd
, uint32_t page
)
305 struct davinci_nand
*info
= nand
->controller_priv
;
306 struct target
*target
= nand
->target
;
307 int page3
= nand
->address_cycles
- (nand
->page_size
== 512);
309 /* write command ({page,otp}x{read,program} */
310 target_write_u8(target
, info
->cmd
, cmd
);
312 /* column address (beginning-of-page) */
313 target_write_u8(target
, info
->addr
, 0);
314 if (nand
->page_size
> 512)
315 target_write_u8(target
, info
->addr
, 0);
318 target_write_u8(target
, info
->addr
, page
);
319 target_write_u8(target
, info
->addr
, page
>> 8);
321 target_write_u8(target
, info
->addr
, page
>> 16);
323 target_write_u8(target
, info
->addr
, page
>> 24);
326 static int davinci_seek_column(struct nand_device
*nand
, uint16_t column
)
328 struct davinci_nand
*info
= nand
->controller_priv
;
329 struct target
*target
= nand
->target
;
331 /* Random read, we must have issued a page read already */
332 target_write_u8(target
, info
->cmd
, NAND_CMD_RNDOUT
);
334 target_write_u8(target
, info
->addr
, column
);
336 if (nand
->page_size
> 512) {
337 target_write_u8(target
, info
->addr
, column
>> 8);
338 target_write_u8(target
, info
->cmd
, NAND_CMD_RNDOUTSTART
);
341 if (!davinci_nand_ready(nand
, 100))
342 return ERROR_NAND_OPERATION_TIMEOUT
;
347 static int davinci_writepage_tail(struct nand_device
*nand
,
348 uint8_t *oob
, uint32_t oob_size
)
350 struct davinci_nand
*info
= nand
->controller_priv
;
351 struct target
*target
= nand
->target
;
355 davinci_write_block_data(nand
, oob
, oob_size
);
357 /* non-cachemode page program */
358 target_write_u8(target
, info
->cmd
, NAND_CMD_PAGEPROG
);
360 if (!davinci_nand_ready(nand
, 100))
361 return ERROR_NAND_OPERATION_TIMEOUT
;
363 if (nand_read_status(nand
, &status
) != ERROR_OK
) {
364 LOG_ERROR("couldn't read status");
365 return ERROR_NAND_OPERATION_FAILED
;
368 if (status
& NAND_STATUS_FAIL
) {
369 LOG_ERROR("write operation failed, status: 0x%02x", status
);
370 return ERROR_NAND_OPERATION_FAILED
;
377 * All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
379 static int davinci_write_page_ecc1(struct nand_device
*nand
, uint32_t page
,
380 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
383 struct davinci_nand
*info
= nand
->controller_priv
;
384 struct target
*target
= nand
->target
;
385 const uint32_t fcr_addr
= info
->aemif
+ NANDFCR
;
386 const uint32_t ecc1_addr
= info
->aemif
+ NANDFECC
+ (4 * info
->chipsel
);
389 /* Write contiguous ECC bytes starting at specified offset.
390 * NOTE: Linux reserves twice as many bytes as we need; and
391 * for 16-bit OOB, those extra bytes are discontiguous.
393 switch (nand
->page_size
) {
405 davinci_write_pagecmd(nand
, NAND_CMD_SEQIN
, page
);
407 /* scrub any old ECC state */
408 target_read_u32(target
, ecc1_addr
, &ecc1
);
410 target_read_u32(target
, fcr_addr
, &fcr
);
411 fcr
|= 1 << (8 + info
->chipsel
);
414 /* set "start csX 1bit ecc" bit */
415 target_write_u32(target
, fcr_addr
, fcr
);
417 /* write 512 bytes */
418 davinci_write_block_data(nand
, data
, 512);
422 /* read the ecc, pack to 3 bytes, and invert so the ecc
423 * in an erased block is correct
425 target_read_u32(target
, ecc1_addr
, &ecc1
);
426 ecc1
= (ecc1
& 0x0fff) | ((ecc1
& 0x0fff0000) >> 4);
429 /* save correct ECC code into oob data */
430 oob
[oob_offset
++] = (uint8_t)(ecc1
);
431 oob
[oob_offset
++] = (uint8_t)(ecc1
>> 8);
432 oob
[oob_offset
++] = (uint8_t)(ecc1
>> 16);
436 /* write OOB into spare area */
437 return davinci_writepage_tail(nand
, oob
, oob_size
);
441 * Preferred "new style" ECC layout for use with 4-bit ECC. This somewhat
442 * slows down large page reads done with error correction (since the OOB
443 * is read first, so its ECC data can be used incrementally), but the
444 * manufacturer bad block markers are safe. Contrast: old "infix" style.
446 static int davinci_write_page_ecc4(struct nand_device
*nand
, uint32_t page
,
447 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
449 static const uint8_t ecc512
[] = {
450 0, 1, 2, 3, 4, /* 5== mfr badblock */
451 6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15,
453 static const uint8_t ecc2048
[] = {
454 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
455 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
456 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
457 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
459 static const uint8_t ecc4096
[] = {
460 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
461 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
462 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
463 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
464 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
465 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
466 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
467 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
470 struct davinci_nand
*info
= nand
->controller_priv
;
472 struct target
*target
= nand
->target
;
473 const uint32_t fcr_addr
= info
->aemif
+ NANDFCR
;
474 const uint32_t ecc4_addr
= info
->aemif
+ NAND4BITECC
;
477 /* Use the same ECC layout Linux uses. For small page chips
478 * it's a bit cramped.
480 * NOTE: at this writing, 4KB pages have issues in Linux
481 * because they need more than 64 bytes of ECC data, which
482 * the standard ECC logic can't handle.
484 switch (nand
->page_size
) {
496 davinci_write_pagecmd(nand
, NAND_CMD_SEQIN
, page
);
498 /* scrub any old ECC state */
499 target_read_u32(target
, info
->aemif
+ NANDERRVAL
, &ecc4
);
501 target_read_u32(target
, fcr_addr
, &fcr
);
503 fcr
|= (1 << 12) | (info
->chipsel
<< 4);
506 uint32_t raw_ecc
[4], *p
;
509 /* start 4bit ecc on csX */
510 target_write_u32(target
, fcr_addr
, fcr
);
512 /* write 512 bytes */
513 davinci_write_block_data(nand
, data
, 512);
517 /* read the ecc, then save it into 10 bytes in the oob */
518 for (i
= 0; i
< 4; i
++) {
519 target_read_u32(target
, ecc4_addr
+ 4 * i
, &raw_ecc
[i
]);
520 raw_ecc
[i
] &= 0x03ff03ff;
522 for (i
= 0, p
= raw_ecc
; i
< 2; i
++, p
+= 2) {
523 oob
[*l
++] = p
[0] & 0xff;
524 oob
[*l
++] = ((p
[0] >> 8) & 0x03) | ((p
[0] >> 14) & 0xfc);
525 oob
[*l
++] = ((p
[0] >> 22) & 0x0f) | ((p
[1] << 4) & 0xf0);
526 oob
[*l
++] = ((p
[1] >> 4) & 0x3f) | ((p
[1] >> 10) & 0xc0);
527 oob
[*l
++] = (p
[1] >> 18) & 0xff;
532 /* write OOB into spare area */
533 return davinci_writepage_tail(nand
, oob
, oob_size
);
537 * "Infix" OOB ... like Linux ECC_HW_SYNDROME. Avoided because it trashes
538 * manufacturer bad block markers, except on small page chips. Once you
539 * write to a page using this scheme, you need specialized code to update
540 * it (code which ignores now-invalid bad block markers).
542 * This is needed *only* to support older firmware. Older ROM Boot Loaders
543 * need it to read their second stage loader (UBL) into SRAM, but from then
544 * on the whole system can use the cleaner non-infix layouts. Systems with
545 * older second stage loaders (ABL/U-Boot, etc) or other system software
546 * (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
548 static int davinci_write_page_ecc4infix(struct nand_device
*nand
, uint32_t page
,
549 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
551 struct davinci_nand
*info
= nand
->controller_priv
;
552 struct target
*target
= nand
->target
;
553 const uint32_t fcr_addr
= info
->aemif
+ NANDFCR
;
554 const uint32_t ecc4_addr
= info
->aemif
+ NAND4BITECC
;
557 davinci_write_pagecmd(nand
, NAND_CMD_SEQIN
, page
);
559 /* scrub any old ECC state */
560 target_read_u32(target
, info
->aemif
+ NANDERRVAL
, &ecc4
);
562 target_read_u32(target
, fcr_addr
, &fcr
);
564 fcr
|= (1 << 12) | (info
->chipsel
<< 4);
567 uint32_t raw_ecc
[4], *p
;
571 /* start 4bit ecc on csX */
572 target_write_u32(target
, fcr_addr
, fcr
);
574 /* write 512 bytes */
575 davinci_write_block_data(nand
, data
, 512);
580 for (i
= 0; i
< 4; i
++) {
581 target_read_u32(target
, ecc4_addr
+ 4 * i
, &raw_ecc
[i
]);
582 raw_ecc
[i
] &= 0x03ff03ff;
585 /* skip 6 bytes of prepad, then pack 10 packed ecc bytes */
586 for (i
= 0, l
= oob
+ 6, p
= raw_ecc
; i
< 2; i
++, p
+= 2) {
588 *l
++ = ((p
[0] >> 8) & 0x03) | ((p
[0] >> 14) & 0xfc);
589 *l
++ = ((p
[0] >> 22) & 0x0f) | ((p
[1] << 4) & 0xf0);
590 *l
++ = ((p
[1] >> 4) & 0x3f) | ((p
[1] >> 10) & 0xc0);
591 *l
++ = (p
[1] >> 18) & 0xff;
594 /* write this "out-of-band" data -- infix */
595 davinci_write_block_data(nand
, oob
, 16);
599 /* the last data and OOB writes included the spare area */
600 return davinci_writepage_tail(nand
, NULL
, 0);
603 static int davinci_read_page_ecc4infix(struct nand_device
*nand
, uint32_t page
,
604 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
607 int want_col
, at_col
;
610 davinci_write_pagecmd(nand
, NAND_CMD_READ0
, page
);
612 /* large page devices need a start command */
613 if (nand
->page_size
> 512)
614 davinci_command(nand
, NAND_CMD_READSTART
);
616 if (!davinci_nand_ready(nand
, 100))
617 return ERROR_NAND_OPERATION_TIMEOUT
;
619 /* NOTE: not bothering to compute and use ECC data for now */
623 while ((data
&& data_size
) || (oob
&& oob_size
)) {
625 if (data
&& data_size
) {
626 if (want_col
!= at_col
) {
627 /* Reads are slow, so seek past them when we can */
628 ret
= davinci_seek_column(nand
, want_col
);
633 /* read 512 bytes or data_size, whichever is smaller*/
634 read_size
= data_size
> 512 ? 512 : data_size
;
635 davinci_read_block_data(nand
, data
, read_size
);
637 data_size
-= read_size
;
642 if (oob
&& oob_size
) {
643 if (want_col
!= at_col
) {
644 ret
= davinci_seek_column(nand
, want_col
);
649 /* read this "out-of-band" data -- infix */
650 read_size
= oob_size
> 16 ? 16 : oob_size
;
651 davinci_read_block_data(nand
, oob
, read_size
);
653 oob_size
-= read_size
;
661 NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command
)
663 struct davinci_nand
*info
;
664 unsigned long chip
, aemif
;
671 * - nand chip address
674 * Plus someday, optionally, ALE and CLE masks.
677 return ERROR_COMMAND_SYNTAX_ERROR
;
679 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[2], chip
);
681 LOG_ERROR("Invalid NAND chip address %s", CMD_ARGV
[2]);
685 if (strcmp(CMD_ARGV
[3], "hwecc1") == 0)
687 else if (strcmp(CMD_ARGV
[3], "hwecc4") == 0)
689 else if (strcmp(CMD_ARGV
[3], "hwecc4_infix") == 0)
690 eccmode
= HWECC4_INFIX
;
692 LOG_ERROR("Invalid ecc mode %s", CMD_ARGV
[3]);
696 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[4], aemif
);
698 LOG_ERROR("Invalid AEMIF controller address %s", CMD_ARGV
[4]);
702 /* REVISIT what we'd *like* to do is look up valid ranges using
703 * target-specific declarations, and not even need to pass the
704 * AEMIF controller address.
706 if (aemif
== 0x01e00000 /* dm6446, dm357 */
707 || aemif
== 0x01e10000 /* dm335, dm355 */
708 || aemif
== 0x01d10000 /* dm365 */
710 if (chip
< 0x02000000 || chip
>= 0x0a000000) {
711 LOG_ERROR("NAND address %08lx out of range?", chip
);
714 chipsel
= (chip
- 0x02000000) >> 25;
716 LOG_ERROR("unrecognized AEMIF controller address %08lx", aemif
);
720 info
= calloc(1, sizeof(*info
));
724 info
->eccmode
= eccmode
;
725 info
->chipsel
= chipsel
;
728 info
->cmd
= chip
| 0x10;
729 info
->addr
= chip
| 0x08;
731 nand
->controller_priv
= info
;
733 info
->io
.target
= nand
->target
;
734 info
->io
.data
= info
->data
;
735 info
->io
.op
= ARM_NAND_NONE
;
737 /* NOTE: for now we don't do any error correction on read.
738 * Nothing else in OpenOCD currently corrects read errors,
739 * and in any case it's *writing* that we care most about.
741 info
->read_page
= nand_read_page_raw
;
745 /* ECC_HW, 1-bit corrections, 3 bytes ECC per 512 data bytes */
746 info
->write_page
= davinci_write_page_ecc1
;
749 /* ECC_HW, 4-bit corrections, 10 bytes ECC per 512 data bytes */
750 info
->write_page
= davinci_write_page_ecc4
;
753 /* Same 4-bit ECC HW, with problematic page/ecc layout */
754 info
->read_page
= davinci_read_page_ecc4infix
;
755 info
->write_page
= davinci_write_page_ecc4infix
;
762 return ERROR_NAND_OPERATION_FAILED
;
765 struct nand_flash_controller davinci_nand_controller
= {
767 .usage
= "chip_addr hwecc_mode aemif_addr",
768 .nand_device_command
= davinci_nand_device_command
,
769 .init
= davinci_init
,
770 .reset
= davinci_reset
,
771 .command
= davinci_command
,
772 .address
= davinci_address
,
773 .write_data
= davinci_write_data
,
774 .read_data
= davinci_read_data
,
775 .write_page
= davinci_write_page
,
776 .read_page
= davinci_read_page
,
777 .write_block_data
= davinci_write_block_data
,
778 .read_block_data
= davinci_read_block_data
,
779 .nand_ready
= davinci_nand_ready
,