1 # SPDX-License-Identifier: GPL-2.0-or-later
2 # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
4 # Texas Instruments K3 devices:
5 # * AM243: https://www.ti.com/lit/pdf/spruim2
6 # Has 4 R5 Cores, M4F and an M3
7 # * AM263: https://www.ti.com/lit/pdf/spruj17
8 # Has 4 R5 Cores and an M3
9 # * AM625: https://www.ti.com/lit/pdf/spruiv7a
10 # Has 4 ARMV8 Cores and 1 R5 Core and an M4F
11 # * AM62A7: https://www.ti.com/lit/pdf/spruj16a
12 # Has 4 ARMV8 Cores and 2 R5 Cores
13 # * AM62P: https://www.ti.com/lit/pdf/spruj83
14 # Has 4 ARMV8 Cores and 2 R5 Cores
15 # * AM642: https://www.ti.com/lit/pdf/spruim2
16 # Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
17 # * AM654x: https://www.ti.com/lit/pdf/spruid7
18 # Has 4 ARMV8 Cores and 2 R5 Cores and an M3
19 # * J7200: https://www.ti.com/lit/pdf/spruiu1
20 # Has 2 ARMV8 Cores and 4 R5 Cores and an M3
21 # * J721E: https://www.ti.com/lit/pdf/spruil1
22 # Has 2 ARMV8 Cores and 6 R5 Cores and an M3
23 # * J721S2: https://www.ti.com/lit/pdf/spruj28
24 # Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
25 # * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
26 # Has 8 ARMV8 Cores and 8 R5 Cores
29 source [find target/swj-dp.tcl]
31 if { [info exists SOC] } {
37 # set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
38 if { [info exists V8_SMP_DEBUG] } {
39 set _v8_smp_debug $V8_SMP_DEBUG
46 # System Controller is the very first processor - all current SoCs have it.
47 set CM3_CTIBASE {0x3C016000}
49 # sysctrl power-ap unlock offsets
50 set _sysctrl_ap_unlock_offsets {0xf0 0x44}
53 # All the ARMV8s are the next processors.
54 # CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1
55 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
56 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
58 # And we add up the R5s
59 # (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
60 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
61 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
62 set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
65 # Finally an General Purpose(GP) MCU
66 set CM4_CTIBASE {0x20001000}
68 # General Purpose MCU (M4) may be present on some very few SoCs
70 # General Purpose MCU power-ap unlock offsets
71 set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
73 # Generic mem-ap port number
76 # Set configuration overrides for each SOC
79 set _K3_DAP_TAPID 0x2bb7d02f
84 # AM263 has 0 ARMV8 CPUs
87 # AM263 has 2 cluster of 2 R5s cores.
89 set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
90 set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000}
91 set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000}
95 set _K3_DAP_TAPID 0x0bb5a02f
97 # AM654 has 2 clusters of 2 A53 cores each.
98 set _armv8_cpu_name a53
101 # AM654 has 1 cluster of 2 R5s cores.
103 set R5_NAMES {mcu_r5.0 mcu_r5.1}
105 # Sysctrl power-ap unlock offsets
106 set _sysctrl_ap_unlock_offsets {0xf0 0x50}
110 set _K3_DAP_TAPID 0x0bb3802f
112 # AM642 has 1 clusters of 2 A53 cores each.
113 set _armv8_cpu_name a53
115 set ARMV8_DBGBASE {0x90010000 0x90110000}
116 set ARMV8_CTIBASE {0x90020000 0x90120000}
118 # AM642 has 2 cluster of 2 R5s cores.
120 set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
121 set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
122 set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
127 # Overrides for am243
128 if { "$_soc" == "am243" } {
129 # Uses the same JTAG ID
134 set _K3_DAP_TAPID 0x0bb7e02f
136 # AM625 has 1 clusters of 4 A53 cores.
137 set _armv8_cpu_name a53
139 set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
140 set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
142 # AM625 has 1 cluster of 1 R5s core.
144 set R5_NAMES {main0_r5.0}
145 set R5_DBGBASE {0x9d410000}
146 set R5_CTIBASE {0x9d418000}
149 set CM3_CTIBASE {0x20001000}
150 # Sysctrl power-ap unlock offsets
151 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
155 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
157 # Setup DMEM access descriptions
158 # DAPBUS (Debugger) description
159 set _dmem_base_address 0x740002000
160 set _dmem_ap_address_offset 0x100
162 # Emulated AP description
163 set _dmem_emu_base_address 0x760000000
164 set _dmem_emu_base_address_map_to 0x1d500000
165 set _dmem_emu_ap_list 1
169 set _K3_DAP_TAPID 0x0bb8d02f
171 # AM62a7/AM62P has 1 cluster of 4 A53 cores.
172 set _armv8_cpu_name a53
174 set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
175 set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
177 # AM62a7/AM62P has 2 cluster of 1 R5 core.
179 set R5_NAMES {main0_r5.0 mcu0_r5.0}
180 set R5_DBGBASE {0x9d410000 0x9d810000}
181 set R5_CTIBASE {0x9d418000 0x9d818000}
184 set CM3_CTIBASE {0x20001000}
185 # Sysctrl power-ap unlock offsets
186 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
188 # Overrides for am62p
189 if { "$_soc" == "am62p" } {
190 set _K3_DAP_TAPID 0x0bb9d02f
191 set R5_NAMES {wkup0_r5.0 mcu0_r5.0}
195 set _K3_DAP_TAPID 0x0bb6402f
196 # J721E has 1 cluster of 2 A72 cores.
197 set _armv8_cpu_name a72
200 # J721E has 3 clusters of 2 R5 cores each.
203 # Setup DMEM access descriptions
204 # DAPBUS (Debugger) description
205 set _dmem_base_address 0x4c40002000
206 set _dmem_ap_address_offset 0x100
208 # Emulated AP description
209 set _dmem_emu_base_address 0x4c60000000
210 set _dmem_emu_base_address_map_to 0x1d600000
211 set _dmem_emu_ap_list 1
214 set _K3_DAP_TAPID 0x0bb6d02f
216 # J7200 has 1 cluster of 2 A72 cores.
217 set _armv8_cpu_name a72
220 # J7200 has 2 clusters of 2 R5 cores each.
222 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
223 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
226 set CM3_CTIBASE {0x20001000}
229 set _K3_DAP_TAPID 0x0bb7502f
231 # J721s2 has 1 cluster of 2 A72 cores.
232 set _armv8_cpu_name a72
235 # J721s2 has 3 clusters of 2 R5 cores each.
239 set CM3_CTIBASE {0x20001000}
240 # Sysctrl power-ap unlock offsets
241 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
245 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
248 set _K3_DAP_TAPID 0x0bb8002f
250 # j784s4 has 2 cluster of 4 A72 cores each.
251 set _armv8_cpu_name a72
253 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000
254 0x90810000 0x90910000 0x90a10000 0x90b10000}
255 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000
256 0x90820000 0x90920000 0x90a20000 0x90b20000}
258 # J721s2 has 4 clusters of 2 R5 cores each.
260 set R5_DBGBASE {0x9d010000 0x9d012000
261 0x9d410000 0x9d412000
262 0x9d510000 0x9d512000
263 0x9d610000 0x9d612000}
264 set R5_CTIBASE {0x9d018000 0x9d019000
265 0x9d418000 0x9d419000
266 0x9d518000 0x9d519000
267 0x9d618000 0x9d619000}
268 set R5_NAMES {mcu_r5.0 mcu_r5.1
269 main0_r5.0 main0_r5.1
270 main1_r5.0 main1_r5.1
271 main2_r5.0 main2_r5.1}
274 set CM3_CTIBASE {0x20001000}
275 # Sysctrl power-ap unlock offsets
276 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
279 echo "'$_soc' is invalid!"
283 proc _get_rtos_type_for_cpu { target_name } {
284 if { [info exists ::RTOS($target_name)] } {
285 return $::RTOS($target_name)
292 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
294 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
296 set _TARGETNAME $_CHIPNAME.cpu
298 set _CTINAME $_CHIPNAME.cti
300 # sysctrl is always present
301 cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \
302 -ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0]
304 target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \
305 -ap-num $_sysctrl_ap_num -defer-examine \
306 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
308 $_TARGETNAME.sysctrl configure -event reset-assert { }
311 # To access sysctrl, we need to enable the JTAG access for the same.
312 # Ensure Power-AP unlocked
313 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
314 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
316 $::_TARGETNAME.sysctrl arp_examine
319 $_TARGETNAME.sysctrl configure -event gdb-attach {
321 # gdb-attach default rule
325 proc _cpu_no_smp_up {} {
326 set _current_target [target current]
327 set _current_type [$_current_target cget -type]
329 $_current_target arp_examine
330 $_current_target $_current_type dbginit
333 proc _armv8_smp_up {} {
334 for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
335 $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
336 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
337 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
339 # Set Default target as core 0
340 targets $::_TARGETNAME.$::_armv8_cpu_name.0
343 set _v8_smp_targets ""
345 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
347 cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
348 -baseaddr [lindex $ARMV8_CTIBASE $_core]
350 target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
351 -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \
352 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core]
354 set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
356 if { $_v8_smp_debug == 0 } {
357 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
359 # gdb-attach default rule
363 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
365 # gdb-attach default rule
371 if { $_armv8_cores > 0 } {
372 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
373 set _armv8_up_cmd "$_armv8_cpu_name"_up
374 # Available if V8_SMP_DEBUG is set to non-zero value
375 set _armv8_smp_cmd "$_armv8_cpu_name"_smp
377 if { $_v8_smp_debug == 0 } {
378 proc $_armv8_up_cmd { args } {
379 foreach _core $args {
385 proc $_armv8_smp_cmd { args } {
389 target smp {*}$_v8_smp_targets
393 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
394 set _r5_name [lindex $R5_NAMES $_core]
395 cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \
396 -baseaddr [lindex $R5_CTIBASE $_core]
398 # inactive core examination will fail - wait till startup of additional core
399 target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
400 -dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \
401 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
403 $_TARGETNAME.$_r5_name configure -event gdb-attach {
405 # gdb-attach default rule
410 proc r5_up { args } {
411 foreach _core $args {
417 if { $_gp_mcu_cores != 0 } {
418 cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
419 target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \
420 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu]
421 $_TARGETNAME.gp_mcu configure -event reset-assert { }
424 # To access GP MCU, we need to enable the JTAG access for the same.
425 # Ensure Power-AP unlocked
426 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
427 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
429 $::_TARGETNAME.gp_mcu arp_examine
432 $_TARGETNAME.gp_mcu configure -event gdb-attach {
434 # gdb-attach default rule
439 # In case of DMEM access, configure the dmem adapter with offsets from above.
440 if { 0 == [string compare [adapter name] dmem ] } {
441 if { [info exists _dmem_base_address] } {
442 # DAPBUS (Debugger) description
443 dmem base_address $_dmem_base_address
444 dmem ap_address_offset $_dmem_ap_address_offset
445 dmem max_aps $_dmem_max_aps
447 # The following are the details of APs to be emulated for direct address access.
448 # Debug Config (Debugger) description
449 dmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to
450 dmem emu_ap_list $_dmem_emu_ap_list
451 # We are going local bus, so speed is really dummy here.
454 puts "ERROR: ${SOC} data is missing to support dmem access!"
457 # AXI AP access port for SoC address map
458 target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num