1 # SPDX-License-Identifier: GPL-2.0-or-later
2 # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
4 # Texas Instruments K3 devices:
5 # * AM243: https://www.ti.com/lit/pdf/spruim2
6 # Has 4 R5 Cores, M4F and an M3
7 # * AM263: https://www.ti.com/lit/pdf/spruj17
8 # Has 4 R5 Cores and an M3
9 # * AM273: https://www.ti.com/lit/pdf/spruiu0
10 # Has 2 R5 Cores and an M3
11 # * AM625: https://www.ti.com/lit/pdf/spruiv7a
12 # Has 4 ARMV8 Cores and 1 R5 Core and an M4F
13 # * AM62A7: https://www.ti.com/lit/pdf/spruj16a
14 # Has 4 ARMV8 Cores and 2 R5 Cores
15 # * AM62P: https://www.ti.com/lit/pdf/spruj83
16 # Has 4 ARMV8 Cores and 2 R5 Cores
17 # * AM642: https://www.ti.com/lit/pdf/spruim2
18 # Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
19 # * AM654x: https://www.ti.com/lit/pdf/spruid7
20 # Has 4 ARMV8 Cores and 2 R5 Cores and an M3
21 # * J7200: https://www.ti.com/lit/pdf/spruiu1
22 # Has 2 ARMV8 Cores and 4 R5 Cores and an M3
23 # * J721E: https://www.ti.com/lit/pdf/spruil1
24 # Has 2 ARMV8 Cores and 6 R5 Cores and an M3
25 # * J721S2: https://www.ti.com/lit/pdf/spruj28
26 # Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
27 # * J722S: https://www.ti.com/lit/zip/sprujb3
28 # Has 4 ARMV8 Cores and 3 R5 Cores
29 # * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
30 # Has 8 ARMV8 Cores and 8 R5 Cores
33 source [find target/swj-dp.tcl]
35 if { [info exists SOC] } {
41 # set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
42 if { [info exists V8_SMP_DEBUG] } {
43 set _v8_smp_debug $V8_SMP_DEBUG
50 # System Controller is the very first processor - all current SoCs have it.
51 set CM3_CTIBASE {0x3C016000}
53 # sysctrl power-ap unlock offsets
54 set _sysctrl_ap_unlock_offsets {0xf0 0x44}
57 # All the ARMV8s are the next processors.
58 # CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1
59 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
60 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
62 # And we add up the R5s
63 # (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
64 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
65 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
66 set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
69 # Finally an General Purpose(GP) MCU
70 set CM4_CTIBASE {0x20001000}
72 # General Purpose MCU (M4) may be present on some very few SoCs
74 # General Purpose MCU power-ap unlock offsets
75 set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
77 # Generic mem-ap port number
80 # Set configuration overrides for each SOC
83 set _K3_DAP_TAPID 0x2bb7d02f
88 # AM263 has 0 ARMV8 CPUs
91 # AM263 has 2 cluster of 2 R5s cores.
93 set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
94 set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000}
95 set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000}
99 set _K3_DAP_TAPID 0x1bb6a02f
104 # system controller is on AP0
105 set _sysctrl_ap_num 0
107 # AM273 has 0 ARMV8 CPUs
110 # AM273 has 1 cluster of 2 R5s cores.
112 set R5_NAMES {main0_r5.0 main0_r5.1}
113 set R5_DBGBASE {0x90030000 0x90032000}
114 set R5_CTIBASE {0x90038000 0x90039000}
118 set _K3_DAP_TAPID 0x0bb5a02f
120 # AM654 has 2 clusters of 2 A53 cores each.
121 set _armv8_cpu_name a53
124 # AM654 has 1 cluster of 2 R5s cores.
126 set R5_NAMES {mcu_r5.0 mcu_r5.1}
128 # Sysctrl power-ap unlock offsets
129 set _sysctrl_ap_unlock_offsets {0xf0 0x50}
133 set _K3_DAP_TAPID 0x0bb3802f
135 # AM642 has 1 clusters of 2 A53 cores each.
136 set _armv8_cpu_name a53
138 set ARMV8_DBGBASE {0x90010000 0x90110000}
139 set ARMV8_CTIBASE {0x90020000 0x90120000}
141 # AM642 has 2 cluster of 2 R5s cores.
143 set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
144 set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
145 set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
150 # Overrides for am243
151 if { "$_soc" == "am243" } {
152 # Uses the same JTAG ID
157 set _K3_DAP_TAPID 0x0bb7e02f
159 # AM625 has 1 clusters of 4 A53 cores.
160 set _armv8_cpu_name a53
162 set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
163 set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
165 # AM625 has 1 cluster of 1 R5s core.
167 set R5_NAMES {main0_r5.0}
168 set R5_DBGBASE {0x9d410000}
169 set R5_CTIBASE {0x9d418000}
172 set CM3_CTIBASE {0x20001000}
173 # Sysctrl power-ap unlock offsets
174 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
178 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
180 # Setup DMEM access descriptions
181 # DAPBUS (Debugger) description
182 set _dmem_base_address 0x740002000
183 set _dmem_ap_address_offset 0x100
185 # Emulated AP description
186 set _dmem_emu_base_address 0x760000000
187 set _dmem_emu_base_address_map_to 0x1d500000
188 set _dmem_emu_ap_list 1
193 set _K3_DAP_TAPID 0x0bb8d02f
195 # AM62a7/AM62P has 1 cluster of 4 A53 cores.
196 set _armv8_cpu_name a53
198 set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
199 set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
201 # AM62a7/AM62P has 2 cluster of 1 R5 core.
203 set R5_NAMES {main0_r5.0 mcu0_r5.0}
204 set R5_DBGBASE {0x9d410000 0x9d810000}
205 set R5_CTIBASE {0x9d418000 0x9d818000}
208 set CM3_CTIBASE {0x20001000}
209 # Sysctrl power-ap unlock offsets
210 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
212 # Overrides for am62p
213 if { "$_soc" == "am62p" } {
214 set _K3_DAP_TAPID 0x0bb9d02f
215 set R5_NAMES {wkup0_r5.0 mcu0_r5.0}
217 # Overrides for j722s
218 if { "$_soc" == "j722s" } {
219 set _K3_DAP_TAPID 0x0bba002f
221 set R5_NAMES {wkup0_r5.0 main0_r5.0 mcu0_r5.0}
222 set R5_DBGBASE {0x9d410000 0x9d510000 0x9d810000}
223 set R5_CTIBASE {0x9d418000 0x9d518000 0x9d818000}
227 set _K3_DAP_TAPID 0x0bb6402f
228 # J721E has 1 cluster of 2 A72 cores.
229 set _armv8_cpu_name a72
232 # J721E has 3 clusters of 2 R5 cores each.
235 # Setup DMEM access descriptions
236 # DAPBUS (Debugger) description
237 set _dmem_base_address 0x4c40002000
238 set _dmem_ap_address_offset 0x100
240 # Emulated AP description
241 set _dmem_emu_base_address 0x4c60000000
242 set _dmem_emu_base_address_map_to 0x1d600000
243 set _dmem_emu_ap_list 1
246 set _K3_DAP_TAPID 0x0bb6d02f
248 # J7200 has 1 cluster of 2 A72 cores.
249 set _armv8_cpu_name a72
252 # J7200 has 2 clusters of 2 R5 cores each.
254 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
255 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
258 set CM3_CTIBASE {0x20001000}
261 set _K3_DAP_TAPID 0x0bb7502f
263 # J721s2 has 1 cluster of 2 A72 cores.
264 set _armv8_cpu_name a72
267 # J721s2 has 3 clusters of 2 R5 cores each.
271 set CM3_CTIBASE {0x20001000}
272 # Sysctrl power-ap unlock offsets
273 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
277 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
280 set _K3_DAP_TAPID 0x0bb8002f
282 # j784s4 has 2 cluster of 4 A72 cores each.
283 set _armv8_cpu_name a72
285 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000
286 0x90810000 0x90910000 0x90a10000 0x90b10000}
287 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000
288 0x90820000 0x90920000 0x90a20000 0x90b20000}
290 # J721s2 has 4 clusters of 2 R5 cores each.
292 set R5_DBGBASE {0x9d010000 0x9d012000
293 0x9d410000 0x9d412000
294 0x9d510000 0x9d512000
295 0x9d610000 0x9d612000}
296 set R5_CTIBASE {0x9d018000 0x9d019000
297 0x9d418000 0x9d419000
298 0x9d518000 0x9d519000
299 0x9d618000 0x9d619000}
300 set R5_NAMES {mcu_r5.0 mcu_r5.1
301 main0_r5.0 main0_r5.1
302 main1_r5.0 main1_r5.1
303 main2_r5.0 main2_r5.1}
306 set CM3_CTIBASE {0x20001000}
307 # Sysctrl power-ap unlock offsets
308 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
311 echo "'$_soc' is invalid!"
315 proc _get_rtos_type_for_cpu { target_name } {
316 if { [info exists ::RTOS($target_name)] } {
317 return $::RTOS($target_name)
324 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
326 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
328 set _TARGETNAME $_CHIPNAME.cpu
330 set _CTINAME $_CHIPNAME.cti
332 # sysctrl is always present
333 cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \
334 -ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0]
336 target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \
337 -ap-num $_sysctrl_ap_num -defer-examine \
338 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
340 $_TARGETNAME.sysctrl configure -event reset-assert { }
343 # To access sysctrl, we need to enable the JTAG access for the same.
344 # Ensure Power-AP unlocked
345 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
346 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
348 $::_TARGETNAME.sysctrl arp_examine
351 $_TARGETNAME.sysctrl configure -event gdb-attach {
353 # gdb-attach default rule
357 proc _cpu_no_smp_up {} {
358 set _current_target [target current]
359 set _current_type [$_current_target cget -type]
361 $_current_target arp_examine
362 $_current_target $_current_type dbginit
365 proc _armv8_smp_up {} {
366 for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
367 $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
368 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
369 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
371 # Set Default target as core 0
372 targets $::_TARGETNAME.$::_armv8_cpu_name.0
375 set _v8_smp_targets ""
377 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
379 cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
380 -baseaddr [lindex $ARMV8_CTIBASE $_core]
382 target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
383 -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \
384 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core]
386 set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
388 if { $_v8_smp_debug == 0 } {
389 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
391 # gdb-attach default rule
395 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
397 # gdb-attach default rule
403 if { $_armv8_cores > 0 } {
404 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
405 set _armv8_up_cmd "$_armv8_cpu_name"_up
406 # Available if V8_SMP_DEBUG is set to non-zero value
407 set _armv8_smp_cmd "$_armv8_cpu_name"_smp
409 if { $_v8_smp_debug == 0 } {
410 proc $_armv8_up_cmd { args } {
411 foreach _core $args {
417 proc $_armv8_smp_cmd { args } {
421 target smp {*}$_v8_smp_targets
425 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
426 set _r5_name [lindex $R5_NAMES $_core]
427 cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \
428 -baseaddr [lindex $R5_CTIBASE $_core]
430 # inactive core examination will fail - wait till startup of additional core
431 target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
432 -dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \
433 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
435 $_TARGETNAME.$_r5_name configure -event gdb-attach {
437 # gdb-attach default rule
442 proc r5_up { args } {
443 foreach _core $args {
449 if { $_gp_mcu_cores != 0 } {
450 cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
451 target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \
452 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu]
453 $_TARGETNAME.gp_mcu configure -event reset-assert { }
456 # To access GP MCU, we need to enable the JTAG access for the same.
457 # Ensure Power-AP unlocked
458 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
459 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
461 $::_TARGETNAME.gp_mcu arp_examine
464 $_TARGETNAME.gp_mcu configure -event gdb-attach {
466 # gdb-attach default rule
471 # In case of DMEM access, configure the dmem adapter with offsets from above.
472 if { 0 == [string compare [adapter name] dmem ] } {
473 if { [info exists _dmem_base_address] } {
474 # DAPBUS (Debugger) description
475 dmem base_address $_dmem_base_address
476 dmem ap_address_offset $_dmem_ap_address_offset
477 dmem max_aps $_dmem_max_aps
479 # The following are the details of APs to be emulated for direct address access.
480 # Debug Config (Debugger) description
481 dmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to
482 dmem emu_ap_list $_dmem_emu_ap_list
483 # We are going local bus, so speed is really dummy here.
486 puts "ERROR: ${SOC} data is missing to support dmem access!"
489 # AXI AP access port for SoC address map
490 target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num