src/target/mips32_pracc.h

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
   8  *   drasko.draskovic@gmail.com                                            *
   9  *                                                                         *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General Public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General Public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General Public License     *
  21  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  22  ***************************************************************************/
  23
  24 #ifndef OPENOCD_TARGET_MIPS32_PRACC_H
  25 #define OPENOCD_TARGET_MIPS32_PRACC_H
  26
  27 #include <target/mips32.h>
  28 #include <target/mips_ejtag.h>
  29
  30 #define MIPS32_PRACC_FASTDATA_AREA              0xFF200000
  31 #define MIPS32_PRACC_FASTDATA_SIZE              16
  32 #define MIPS32_PRACC_BASE_ADDR                  0xFF200000
  33 #define MIPS32_PRACC_TEXT                               0xFF200200
  34 #define MIPS32_PRACC_PARAM_OUT                  0xFF202000
  35
  36 #define PRACC_UPPER_BASE_ADDR                   (MIPS32_PRACC_BASE_ADDR >> 16)
  37 #define PRACC_OUT_OFFSET                        (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_BASE_ADDR)
  38
  39 #define MIPS32_FASTDATA_HANDLER_SIZE    0x80
  40 #define UPPER16(uint32_t)                               (uint32_t >> 16)
  41 #define LOWER16(uint32_t)                               (uint32_t & 0xFFFF)
  42 #define NEG16(v)                                                (((~(v)) + 1) & 0xFFFF)
  43 /*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF)*/
  44
  45 #define PRACC_BLOCK     128     /* 1 Kbyte */
  46
  47 typedef struct {
  48         uint32_t instr;
  49         uint32_t addr;
  50 } pa_list;
  51
  52 struct pracc_queue_info {
  53         int retval;
  54         int code_count;
  55         int store_count;
  56         int max_code;           /* max intstructions with currently allocated memory */
  57         pa_list *pracc_list;    /* Code and store addresses at dmseg */
  58 };
  59 void pracc_queue_init(struct pracc_queue_info *ctx);
  60 void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr);
  61 void pracc_add_li32(struct pracc_queue_info *ctx, uint32_t reg_num, uint32_t data, bool optimize);
  62 void pracc_queue_free(struct pracc_queue_info *ctx);
  63 int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info,
  64                             struct pracc_queue_info *ctx, uint32_t *buf, bool check_last);
  65
  66 int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info,
  67                 uint32_t addr, int size, int count, void *buf);
  68 int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info,
  69                 uint32_t addr, int size, int count, const void *buf);
  70 int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source,
  71                 int write_t, uint32_t addr, int count, uint32_t *buf);
  72
  73 int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
  74 int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
  75
  76 int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx,
  77                                 uint32_t *param_out, bool check_last);
  78
  79 /**
  80  * \b mips32_cp0_read
  81  *
  82  * Simulates mfc0 ASM instruction (Move From C0),
  83  * i.e. implements copro C0 Register read.
  84  *
  85  * @param[in] ejtag_info
  86  * @param[in] val Storage to hold read value
  87  * @param[in] cp0_reg Number of copro C0 register we want to read
  88  * @param[in] cp0_sel Select for the given C0 register
  89  *
  90  * @return ERROR_OK on Sucess, ERROR_FAIL otherwise
  91  */
  92 int mips32_cp0_read(struct mips_ejtag *ejtag_info,
  93                 uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel);
  94
  95 /**
  96  * \b mips32_cp0_write
  97  *
  98  * Simulates mtc0 ASM instruction (Move To C0),
  99  * i.e. implements copro C0 Register read.
 100  *
 101  * @param[in] ejtag_info
 102  * @param[in] val Value to be written
 103  * @param[in] cp0_reg Number of copro C0 register we want to write to
 104  * @param[in] cp0_sel Select for the given C0 register
 105  *
 106  * @return ERROR_OK on Sucess, ERROR_FAIL otherwise
 107  */
 108 int mips32_cp0_write(struct mips_ejtag *ejtag_info,
 109                 uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel);
 110
 111 #endif /* OPENOCD_TARGET_MIPS32_PRACC_H */