src/target/mips32_pracc.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2008 by Spencer Oliver                                  *
   5  *   spen@spen-soft.co.uk                                                  *
   6  *                                                                         *
   7  *   Copyright (C) 2008 by David T.L. Wong                                 *
   8  *                                                                         *
   9  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
  10  *   drasko.draskovic@gmail.com                                            *
  11  ***************************************************************************/
  12
  13 #ifndef OPENOCD_TARGET_MIPS32_PRACC_H
  14 #define OPENOCD_TARGET_MIPS32_PRACC_H
  15
  16 #include <target/mips32.h>
  17 #include <target/mips_ejtag.h>
  18
  19 #define MIPS32_PRACC_FASTDATA_AREA              0xFF200000
  20 #define MIPS32_PRACC_FASTDATA_SIZE              16
  21 #define MIPS32_PRACC_BASE_ADDR                  0xFF200000
  22 #define MIPS32_PRACC_TEXT                       0xFF200200
  23 #define MIPS32_PRACC_PARAM_OUT                  0xFF202000
  24
  25 #define PRACC_UPPER_BASE_ADDR                   (MIPS32_PRACC_BASE_ADDR >> 16)
  26 #define PRACC_MAX_CODE                          (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_TEXT)
  27 #define PRACC_MAX_INSTRUCTIONS                  (PRACC_MAX_CODE / 4)
  28 #define PRACC_OUT_OFFSET                        (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_BASE_ADDR)
  29
  30 #define MIPS32_FASTDATA_HANDLER_SIZE            0x80
  31 #define UPPER16(addr)                           ((addr) >> 16)
  32 #define LOWER16(addr)                           ((addr) & 0xFFFF)
  33 #define NEG16(v)                                (((~(v)) + 1) & 0xFFFF)
  34 #define SWAP16(v)                               ((LOWER16(v) << 16) | (UPPER16(v)))
  35 /*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF)*/
  36
  37 #define PRACC_BLOCK     128     /* 1 Kbyte */
  38
  39 struct mips32_common;
  40
  41 struct pa_list {
  42         uint32_t instr;
  43         uint32_t addr;
  44 };
  45
  46 struct pracc_queue_info {
  47         struct mips_ejtag *ejtag_info;
  48         unsigned isa;
  49         int retval;
  50         int code_count;
  51         int store_count;
  52         int max_code;           /* max instructions with currently allocated memory */
  53         struct pa_list *pracc_list;     /* Code and store addresses at dmseg */
  54 };
  55
  56 struct mips32_common;
  57
  58 void pracc_queue_init(struct pracc_queue_info *ctx);
  59 void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr);
  60 void pracc_queue_free(struct pracc_queue_info *ctx);
  61 int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info,
  62                             struct pracc_queue_info *ctx, uint32_t *buf, bool check_last);
  63
  64 int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info,
  65                 uint32_t addr, int size, int count, void *buf);
  66 int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info,
  67                 uint32_t addr, int size, int count, const void *buf);
  68 int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source,
  69                 int write_t, uint32_t addr, int count, uint32_t *buf);
  70
  71 int mips32_pracc_read_regs(struct mips32_common *mips32);
  72 int mips32_pracc_write_regs(struct mips32_common *mips32);
  73
  74 /**
  75  * \b mips32_cp0_read
  76  *
  77  * Simulates mfc0 ASM instruction (Move From C0),
  78  * i.e. implements copro C0 Register read.
  79  *
  80  * @param[in] ejtag_info
  81  * @param[in] val Storage to hold read value
  82  * @param[in] cp0_reg Number of copro C0 register we want to read
  83  * @param[in] cp0_sel Select for the given C0 register
  84  *
  85  * @return ERROR_OK on Success, ERROR_FAIL otherwise
  86  */
  87 int mips32_cp0_read(struct mips_ejtag *ejtag_info,
  88                 uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel);
  89
  90 /**
  91  * \b mips32_cp0_write
  92  *
  93  * Simulates mtc0 ASM instruction (Move To C0),
  94  * i.e. implements copro C0 Register read.
  95  *
  96  * @param[in] ejtag_info
  97  * @param[in] val Value to be written
  98  * @param[in] cp0_reg Number of copro C0 register we want to write to
  99  * @param[in] cp0_sel Select for the given C0 register
 100  *
 101  * @return ERROR_OK on Success, ERROR_FAIL otherwise
 102  */
 103 int mips32_cp0_write(struct mips_ejtag *ejtag_info,
 104                 uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel);
 105
 106 /**
 107  * mips32_cp1_control_read
 108  *
 109  * @brief Simulates cfc1 ASM instruction (Move Control Word From Floating Point),
 110  * i.e. implements copro C1 Control Register read.
 111  *
 112  * @param[in] ejtag_info
 113  * @param[in] val Storage to hold read value
 114  * @param[in] cp1_c_reg Number of copro C1 control register we want to read
 115  *
 116  * @return ERROR_OK on Success, ERROR_FAIL otherwise
 117  */
 118 int mips32_cp1_control_read(struct mips_ejtag *ejtag_info,
 119                 uint32_t *val, uint32_t cp1_c_reg);
 120
 121 static inline void pracc_swap16_array(struct mips_ejtag *ejtag_info, uint32_t *buf, int count)
 122 {
 123         if (ejtag_info->isa && ejtag_info->endianness)
 124                 for (int i = 0; i != count; i++)
 125                         buf[i] = SWAP16(buf[i]);
 126 }
 127
 128 #endif /* OPENOCD_TARGET_MIPS32_PRACC_H */