1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
60 * Relevant specifications from ARM include:
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "jtag/interface.h"
75 #include "arm_adi_v5.h"
76 #include <helper/jep106.h>
77 #include <helper/time_support.h>
78 #include <helper/list.h>
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
88 return tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
);
91 /***************************************************************************
93 * DP and MEM-AP register access through APACC and DPACC *
95 ***************************************************************************/
97 static int mem_ap_setup_csw(struct adiv5_ap
*ap
, uint32_t csw
)
99 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
|
102 if (csw
!= ap
->csw_value
) {
103 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
104 int retval
= dap_queue_ap_write(ap
, MEM_AP_REG_CSW
, csw
);
105 if (retval
!= ERROR_OK
)
112 static int mem_ap_setup_tar(struct adiv5_ap
*ap
, uint32_t tar
)
114 if (tar
!= ap
->tar_value
||
115 (ap
->csw_value
& CSW_ADDRINC_MASK
)) {
116 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
117 int retval
= dap_queue_ap_write(ap
, MEM_AP_REG_TAR
, tar
);
118 if (retval
!= ERROR_OK
)
126 * Queue transactions setting up transfer parameters for the
127 * currently selected MEM-AP.
129 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
130 * initiate data reads or writes using memory or peripheral addresses.
131 * If the CSW is configured for it, the TAR may be automatically
132 * incremented after each transfer.
134 * @param ap The MEM-AP.
135 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
136 * matches the cached value, the register is not changed.
137 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
138 * matches the cached address, the register is not changed.
140 * @return ERROR_OK if the transaction was properly queued, else a fault code.
142 static int mem_ap_setup_transfer(struct adiv5_ap
*ap
, uint32_t csw
, uint32_t tar
)
145 retval
= mem_ap_setup_csw(ap
, csw
);
146 if (retval
!= ERROR_OK
)
148 retval
= mem_ap_setup_tar(ap
, tar
);
149 if (retval
!= ERROR_OK
)
155 * Asynchronous (queued) read of a word from memory or a system register.
157 * @param ap The MEM-AP to access.
158 * @param address Address of the 32-bit word to read; it must be
159 * readable by the currently selected MEM-AP.
160 * @param value points to where the word will be stored when the
161 * transaction queue is flushed (assuming no errors).
163 * @return ERROR_OK for success. Otherwise a fault code.
165 int mem_ap_read_u32(struct adiv5_ap
*ap
, uint32_t address
,
170 /* Use banked addressing (REG_BDx) to avoid some link traffic
171 * (updating TAR) when reading several consecutive addresses.
173 retval
= mem_ap_setup_transfer(ap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
174 address
& 0xFFFFFFF0);
175 if (retval
!= ERROR_OK
)
178 return dap_queue_ap_read(ap
, MEM_AP_REG_BD0
| (address
& 0xC), value
);
182 * Synchronous read of a word from memory or a system register.
183 * As a side effect, this flushes any queued transactions.
185 * @param ap The MEM-AP to access.
186 * @param address Address of the 32-bit word to read; it must be
187 * readable by the currently selected MEM-AP.
188 * @param value points to where the result will be stored.
190 * @return ERROR_OK for success; *value holds the result.
191 * Otherwise a fault code.
193 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
, uint32_t address
,
198 retval
= mem_ap_read_u32(ap
, address
, value
);
199 if (retval
!= ERROR_OK
)
202 return dap_run(ap
->dap
);
206 * Asynchronous (queued) write of a word to memory or a system register.
208 * @param ap The MEM-AP to access.
209 * @param address Address to be written; it must be writable by
210 * the currently selected MEM-AP.
211 * @param value Word that will be written to the address when transaction
212 * queue is flushed (assuming no errors).
214 * @return ERROR_OK for success. Otherwise a fault code.
216 int mem_ap_write_u32(struct adiv5_ap
*ap
, uint32_t address
,
221 /* Use banked addressing (REG_BDx) to avoid some link traffic
222 * (updating TAR) when writing several consecutive addresses.
224 retval
= mem_ap_setup_transfer(ap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
225 address
& 0xFFFFFFF0);
226 if (retval
!= ERROR_OK
)
229 return dap_queue_ap_write(ap
, MEM_AP_REG_BD0
| (address
& 0xC),
234 * Synchronous write of a word to memory or a system register.
235 * As a side effect, this flushes any queued transactions.
237 * @param ap The MEM-AP to access.
238 * @param address Address to be written; it must be writable by
239 * the currently selected MEM-AP.
240 * @param value Word that will be written.
242 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
244 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
, uint32_t address
,
247 int retval
= mem_ap_write_u32(ap
, address
, value
);
249 if (retval
!= ERROR_OK
)
252 return dap_run(ap
->dap
);
256 * Synchronous write of a block of memory, using a specific access size.
258 * @param ap The MEM-AP to access.
259 * @param buffer The data buffer to write. No particular alignment is assumed.
260 * @param size Which access size to use, in bytes. 1, 2 or 4.
261 * @param count The number of writes to do (in size units, not bytes).
262 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
263 * @param addrinc Whether the target address should be increased for each write or not. This
264 * should normally be true, except when writing to e.g. a FIFO.
265 * @return ERROR_OK on success, otherwise an error code.
267 static int mem_ap_write(struct adiv5_ap
*ap
, const uint8_t *buffer
, uint32_t size
, uint32_t count
,
268 uint32_t address
, bool addrinc
)
270 struct adiv5_dap
*dap
= ap
->dap
;
271 size_t nbytes
= size
* count
;
272 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
277 /* TI BE-32 Quirks mode:
278 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
279 * size write address bytes written in order
280 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
281 * 2 TAR ^ 2 (val >> 8), (val)
283 * For example, if you attempt to write a single byte to address 0, the processor
284 * will actually write a byte to address 3.
286 * To make writes of size < 4 work as expected, we xor a value with the address before
287 * setting the TAP, and we set the TAP after every transfer rather then relying on
288 * address increment. */
291 csw_size
= CSW_32BIT
;
293 } else if (size
== 2) {
294 csw_size
= CSW_16BIT
;
295 addr_xor
= dap
->ti_be_32_quirks
? 2 : 0;
296 } else if (size
== 1) {
298 addr_xor
= dap
->ti_be_32_quirks
? 3 : 0;
300 return ERROR_TARGET_UNALIGNED_ACCESS
;
303 if (ap
->unaligned_access_bad
&& (address
% size
!= 0))
304 return ERROR_TARGET_UNALIGNED_ACCESS
;
306 retval
= mem_ap_setup_tar(ap
, address
^ addr_xor
);
307 if (retval
!= ERROR_OK
)
311 uint32_t this_size
= size
;
313 /* Select packed transfer if possible */
314 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
315 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
317 retval
= mem_ap_setup_csw(ap
, csw_size
| CSW_ADDRINC_PACKED
);
319 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrincr
);
322 if (retval
!= ERROR_OK
)
325 /* How many source bytes each transfer will consume, and their location in the DRW,
326 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
327 uint32_t outvalue
= 0;
328 if (dap
->ti_be_32_quirks
) {
331 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
332 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
333 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
334 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
337 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (address
++ & 3) ^ addr_xor
);
338 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (address
++ & 3) ^ addr_xor
);
341 outvalue
|= (uint32_t)*buffer
++ << 8 * (0 ^ (address
++ & 3) ^ addr_xor
);
347 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
348 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
350 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
352 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
358 retval
= dap_queue_ap_write(ap
, MEM_AP_REG_DRW
, outvalue
);
359 if (retval
!= ERROR_OK
)
362 /* Rewrite TAR if it wrapped or we're xoring addresses */
363 if (addrinc
&& (addr_xor
|| (address
% ap
->tar_autoincr_block
< size
&& nbytes
> 0))) {
364 retval
= mem_ap_setup_tar(ap
, address
^ addr_xor
);
365 if (retval
!= ERROR_OK
)
370 /* REVISIT: Might want to have a queued version of this function that does not run. */
371 if (retval
== ERROR_OK
)
372 retval
= dap_run(dap
);
374 if (retval
!= ERROR_OK
) {
376 if (dap_queue_ap_read(ap
, MEM_AP_REG_TAR
, &tar
) == ERROR_OK
377 && dap_run(dap
) == ERROR_OK
)
378 LOG_ERROR("Failed to write memory at 0x%08"PRIx32
, tar
);
380 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
387 * Synchronous read of a block of memory, using a specific access size.
389 * @param ap The MEM-AP to access.
390 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
391 * @param size Which access size to use, in bytes. 1, 2 or 4.
392 * @param count The number of reads to do (in size units, not bytes).
393 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
394 * @param addrinc Whether the target address should be increased after each read or not. This
395 * should normally be true, except when reading from e.g. a FIFO.
396 * @return ERROR_OK on success, otherwise an error code.
398 static int mem_ap_read(struct adiv5_ap
*ap
, uint8_t *buffer
, uint32_t size
, uint32_t count
,
399 uint32_t adr
, bool addrinc
)
401 struct adiv5_dap
*dap
= ap
->dap
;
402 size_t nbytes
= size
* count
;
403 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
405 uint32_t address
= adr
;
408 /* TI BE-32 Quirks mode:
409 * Reads on big-endian TMS570 behave strangely differently than writes.
410 * They read from the physical address requested, but with DRW byte-reversed.
411 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
412 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
416 csw_size
= CSW_32BIT
;
418 csw_size
= CSW_16BIT
;
422 return ERROR_TARGET_UNALIGNED_ACCESS
;
424 if (ap
->unaligned_access_bad
&& (adr
% size
!= 0))
425 return ERROR_TARGET_UNALIGNED_ACCESS
;
427 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
428 * over-allocation if packed transfers are going to be used, but determining the real need at
429 * this point would be messy. */
430 uint32_t *read_buf
= malloc(count
* sizeof(uint32_t));
431 uint32_t *read_ptr
= read_buf
;
432 if (read_buf
== NULL
) {
433 LOG_ERROR("Failed to allocate read buffer");
437 retval
= mem_ap_setup_tar(ap
, address
);
438 if (retval
!= ERROR_OK
) {
443 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
444 * useful bytes it contains, and their location in the word, depends on the type of transfer
447 uint32_t this_size
= size
;
449 /* Select packed transfer if possible */
450 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
451 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
453 retval
= mem_ap_setup_csw(ap
, csw_size
| CSW_ADDRINC_PACKED
);
455 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrincr
);
457 if (retval
!= ERROR_OK
)
460 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_DRW
, read_ptr
++);
461 if (retval
!= ERROR_OK
)
465 address
+= this_size
;
467 /* Rewrite TAR if it wrapped */
468 if (addrinc
&& address
% ap
->tar_autoincr_block
< size
&& nbytes
> 0) {
469 retval
= mem_ap_setup_tar(ap
, address
);
470 if (retval
!= ERROR_OK
)
475 if (retval
== ERROR_OK
)
476 retval
= dap_run(dap
);
480 nbytes
= size
* count
;
483 /* If something failed, read TAR to find out how much data was successfully read, so we can
484 * at least give the caller what we have. */
485 if (retval
!= ERROR_OK
) {
487 if (dap_queue_ap_read(ap
, MEM_AP_REG_TAR
, &tar
) == ERROR_OK
488 && dap_run(dap
) == ERROR_OK
) {
489 LOG_ERROR("Failed to read memory at 0x%08"PRIx32
, tar
);
490 if (nbytes
> tar
- address
)
491 nbytes
= tar
- address
;
493 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
498 /* Replay loop to populate caller's buffer from the correct word and byte lane */
500 uint32_t this_size
= size
;
502 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
503 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
507 if (dap
->ti_be_32_quirks
) {
510 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
511 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
513 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
515 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
520 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
521 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
523 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
525 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
537 int mem_ap_read_buf(struct adiv5_ap
*ap
,
538 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
540 return mem_ap_read(ap
, buffer
, size
, count
, address
, true);
543 int mem_ap_write_buf(struct adiv5_ap
*ap
,
544 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
546 return mem_ap_write(ap
, buffer
, size
, count
, address
, true);
549 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
550 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
552 return mem_ap_read(ap
, buffer
, size
, count
, address
, false);
555 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
556 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
558 return mem_ap_write(ap
, buffer
, size
, count
, address
, false);
561 /*--------------------------------------------------------------------------*/
564 #define DAP_POWER_DOMAIN_TIMEOUT (10)
566 /* FIXME don't import ... just initialize as
567 * part of DAP transport setup
569 extern const struct dap_ops jtag_dp_ops
;
571 /*--------------------------------------------------------------------------*/
576 struct adiv5_dap
*dap_init(void)
578 struct adiv5_dap
*dap
= calloc(1, sizeof(struct adiv5_dap
));
580 /* Set up with safe defaults */
581 for (i
= 0; i
<= 255; i
++) {
582 dap
->ap
[i
].dap
= dap
;
583 dap
->ap
[i
].ap_num
= i
;
584 /* memaccess_tck max is 255 */
585 dap
->ap
[i
].memaccess_tck
= 255;
586 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
587 dap
->ap
[i
].tar_autoincr_block
= (1<<10);
589 INIT_LIST_HEAD(&dap
->cmd_journal
);
594 * Initialize a DAP. This sets up the power domains, prepares the DP
595 * for further use and activates overrun checking.
597 * @param dap The DAP being initialized.
599 int dap_dp_init(struct adiv5_dap
*dap
)
604 /* JTAG-DP or SWJ-DP, in JTAG mode
605 * ... for SWD mode this is patched as part
607 * FIXME: This should already be setup by the respective transport specific DAP creation.
610 dap
->ops
= &jtag_dp_ops
;
612 dap
->select
= DP_SELECT_INVALID
;
613 dap
->last_read
= NULL
;
615 for (size_t i
= 0; i
< 30; i
++) {
616 /* DP initialization */
618 retval
= dap_dp_read_atomic(dap
, DP_CTRL_STAT
, NULL
);
619 if (retval
== ERROR_OK
)
623 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, SSTICKYERR
);
624 if (retval
!= ERROR_OK
)
627 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
628 if (retval
!= ERROR_OK
)
631 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
632 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
633 if (retval
!= ERROR_OK
)
636 /* Check that we have debug power domains activated */
637 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
638 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
639 CDBGPWRUPACK
, CDBGPWRUPACK
,
640 DAP_POWER_DOMAIN_TIMEOUT
);
641 if (retval
!= ERROR_OK
)
644 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
645 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
646 CSYSPWRUPACK
, CSYSPWRUPACK
,
647 DAP_POWER_DOMAIN_TIMEOUT
);
648 if (retval
!= ERROR_OK
)
651 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
652 if (retval
!= ERROR_OK
)
655 /* With debug power on we can activate OVERRUN checking */
656 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
657 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
658 if (retval
!= ERROR_OK
)
660 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
661 if (retval
!= ERROR_OK
)
664 retval
= dap_run(dap
);
665 if (retval
!= ERROR_OK
)
672 * Initialize a DAP. This sets up the power domains, prepares the DP
673 * for further use, and arranges to use AP #0 for all AP operations
674 * until dap_ap-select() changes that policy.
676 * @param ap The MEM-AP being initialized.
678 int mem_ap_init(struct adiv5_ap
*ap
)
680 /* check that we support packed transfers */
683 struct adiv5_dap
*dap
= ap
->dap
;
685 retval
= mem_ap_setup_transfer(ap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, 0);
686 if (retval
!= ERROR_OK
)
689 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CSW
, &csw
);
690 if (retval
!= ERROR_OK
)
693 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CFG
, &cfg
);
694 if (retval
!= ERROR_OK
)
697 retval
= dap_run(dap
);
698 if (retval
!= ERROR_OK
)
701 if (csw
& CSW_ADDRINC_PACKED
)
702 ap
->packed_transfers
= true;
704 ap
->packed_transfers
= false;
706 /* Packed transfers on TI BE-32 processors do not work correctly in
708 if (dap
->ti_be_32_quirks
)
709 ap
->packed_transfers
= false;
711 LOG_DEBUG("MEM_AP Packed Transfers: %s",
712 ap
->packed_transfers
? "enabled" : "disabled");
714 /* The ARM ADI spec leaves implementation-defined whether unaligned
715 * memory accesses work, only work partially, or cause a sticky error.
716 * On TI BE-32 processors, reads seem to return garbage in some bytes
717 * and unaligned writes seem to cause a sticky error.
718 * TODO: it would be nice to have a way to detect whether unaligned
719 * operations are supported on other processors. */
720 ap
->unaligned_access_bad
= dap
->ti_be_32_quirks
;
722 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
723 !!(cfg
& 0x04), !!(cfg
& 0x02), !!(cfg
& 0x01));
728 /* CID interpretation -- see ARM IHI 0029B section 3
729 * and ARM IHI 0031A table 13-3.
731 static const char *class_description
[16] = {
732 "Reserved", "ROM table", "Reserved", "Reserved",
733 "Reserved", "Reserved", "Reserved", "Reserved",
734 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
735 "Reserved", "OptimoDE DESS",
736 "Generic IP component", "PrimeCell or System component"
739 static bool is_dap_cid_ok(uint32_t cid
)
741 return (cid
& 0xffff0fff) == 0xb105000d;
745 * This function checks the ID for each access port to find the requested Access Port type
747 int dap_find_ap(struct adiv5_dap
*dap
, enum ap_type type_to_find
, struct adiv5_ap
**ap_out
)
751 /* Maximum AP number is 255 since the SELECT register is 8 bits */
752 for (ap_num
= 0; ap_num
<= 255; ap_num
++) {
754 /* read the IDR register of the Access Port */
757 int retval
= dap_queue_ap_read(dap_ap(dap
, ap_num
), AP_REG_IDR
, &id_val
);
758 if (retval
!= ERROR_OK
)
761 retval
= dap_run(dap
);
765 * 27-24 : JEDEC bank (0x4 for ARM)
766 * 23-17 : JEDEC code (0x3B for ARM)
767 * 16-13 : Class (0b1000=Mem-AP)
769 * 7-4 : AP Variant (non-zero for JTAG-AP)
770 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
773 /* Reading register for a non-existant AP should not cause an error,
774 * but just to be sure, try to continue searching if an error does happen.
776 if ((retval
== ERROR_OK
) && /* Register read success */
777 ((id_val
& IDR_JEP106
) == IDR_JEP106_ARM
) && /* Jedec codes match */
778 ((id_val
& IDR_TYPE
) == type_to_find
)) { /* type matches*/
780 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32
")",
781 (type_to_find
== AP_TYPE_AHB_AP
) ? "AHB-AP" :
782 (type_to_find
== AP_TYPE_APB_AP
) ? "APB-AP" :
783 (type_to_find
== AP_TYPE_AXI_AP
) ? "AXI-AP" :
784 (type_to_find
== AP_TYPE_JTAG_AP
) ? "JTAG-AP" : "Unknown",
787 *ap_out
= &dap
->ap
[ap_num
];
792 LOG_DEBUG("No %s found",
793 (type_to_find
== AP_TYPE_AHB_AP
) ? "AHB-AP" :
794 (type_to_find
== AP_TYPE_APB_AP
) ? "APB-AP" :
795 (type_to_find
== AP_TYPE_AXI_AP
) ? "AXI-AP" :
796 (type_to_find
== AP_TYPE_JTAG_AP
) ? "JTAG-AP" : "Unknown");
800 int dap_get_debugbase(struct adiv5_ap
*ap
,
801 uint32_t *dbgbase
, uint32_t *apid
)
803 struct adiv5_dap
*dap
= ap
->dap
;
806 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE
, dbgbase
);
807 if (retval
!= ERROR_OK
)
809 retval
= dap_queue_ap_read(ap
, AP_REG_IDR
, apid
);
810 if (retval
!= ERROR_OK
)
812 retval
= dap_run(dap
);
813 if (retval
!= ERROR_OK
)
819 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
820 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
, int32_t *idx
)
822 uint32_t romentry
, entry_offset
= 0, component_base
, devtype
;
828 retval
= mem_ap_read_atomic_u32(ap
, (dbgbase
&0xFFFFF000) |
829 entry_offset
, &romentry
);
830 if (retval
!= ERROR_OK
)
833 component_base
= (dbgbase
& 0xFFFFF000)
834 + (romentry
& 0xFFFFF000);
836 if (romentry
& 0x1) {
838 retval
= mem_ap_read_atomic_u32(ap
, component_base
| 0xff4, &c_cid1
);
839 if (retval
!= ERROR_OK
) {
840 LOG_ERROR("Can't read component with base address 0x%" PRIx32
841 ", the corresponding core might be turned off", component_base
);
844 if (((c_cid1
>> 4) & 0x0f) == 1) {
845 retval
= dap_lookup_cs_component(ap
, component_base
,
847 if (retval
== ERROR_OK
)
849 if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
853 retval
= mem_ap_read_atomic_u32(ap
,
854 (component_base
& 0xfffff000) | 0xfcc,
856 if (retval
!= ERROR_OK
)
858 if ((devtype
& 0xff) == type
) {
860 *addr
= component_base
;
867 } while (romentry
> 0);
870 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
875 static int dap_read_part_id(struct adiv5_ap
*ap
, uint32_t component_base
, uint32_t *cid
, uint64_t *pid
)
877 assert((component_base
& 0xFFF) == 0);
878 assert(ap
!= NULL
&& cid
!= NULL
&& pid
!= NULL
);
880 uint32_t cid0
, cid1
, cid2
, cid3
;
881 uint32_t pid0
, pid1
, pid2
, pid3
, pid4
;
884 /* IDs are in last 4K section */
885 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFE0, &pid0
);
886 if (retval
!= ERROR_OK
)
888 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFE4, &pid1
);
889 if (retval
!= ERROR_OK
)
891 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFE8, &pid2
);
892 if (retval
!= ERROR_OK
)
894 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFEC, &pid3
);
895 if (retval
!= ERROR_OK
)
897 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFD0, &pid4
);
898 if (retval
!= ERROR_OK
)
900 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFF0, &cid0
);
901 if (retval
!= ERROR_OK
)
903 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFF4, &cid1
);
904 if (retval
!= ERROR_OK
)
906 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFF8, &cid2
);
907 if (retval
!= ERROR_OK
)
909 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFFC, &cid3
);
910 if (retval
!= ERROR_OK
)
913 retval
= dap_run(ap
->dap
);
914 if (retval
!= ERROR_OK
)
917 *cid
= (cid3
& 0xff) << 24
918 | (cid2
& 0xff) << 16
921 *pid
= (uint64_t)(pid4
& 0xff) << 32
922 | (pid3
& 0xff) << 24
923 | (pid2
& 0xff) << 16
930 /* The designer identity code is encoded as:
931 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
932 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
933 * a legacy ASCII Identity Code.
934 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
935 * JEP106 is a standard available from jedec.org
938 /* Part number interpretations are from Cortex
939 * core specs, the CoreSight components TRM
940 * (ARM DDI 0314H), CoreSight System Design
941 * Guide (ARM DGI 0012D) and ETM specs; also
942 * from chip observation (e.g. TI SDTI).
945 /* The legacy code only used the part number field to identify CoreSight peripherals.
946 * This meant that the same part number from two different manufacturers looked the same.
947 * It is desirable for all future additions to identify with both part number and JEP106.
948 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
951 #define ANY_ID 0x1000
955 static const struct {
956 uint16_t designer_id
;
961 { ARM_ID
, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
962 { ARM_ID
, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
963 { ARM_ID
, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
964 { ARM_ID
, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
965 { ARM_ID
, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
966 { ARM_ID
, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
967 { ARM_ID
, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
968 { ARM_ID
, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
969 { ARM_ID
, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
970 { ARM_ID
, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
971 { ARM_ID
, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
972 { ARM_ID
, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
973 { ARM_ID
, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
974 { ARM_ID
, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
975 { ARM_ID
, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
976 { ARM_ID
, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
977 { ARM_ID
, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
978 { ARM_ID
, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
979 { ARM_ID
, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
980 { ARM_ID
, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
981 { ARM_ID
, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
982 { ARM_ID
, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
983 { ARM_ID
, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
984 { ARM_ID
, 0x906, "CoreSight CTI", "(Cross Trigger)", },
985 { ARM_ID
, 0x907, "CoreSight ETB", "(Trace Buffer)", },
986 { ARM_ID
, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
987 { ARM_ID
, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
988 { ARM_ID
, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
989 { ARM_ID
, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
990 { ARM_ID
, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
991 { ARM_ID
, 0x914, "CoreSight SWO", "(Single Wire Output)", },
992 { ARM_ID
, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
993 { ARM_ID
, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
994 { ARM_ID
, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
995 { ARM_ID
, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
996 { ARM_ID
, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
997 { ARM_ID
, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
998 { ARM_ID
, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
999 { ARM_ID
, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1000 { ARM_ID
, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1001 { ARM_ID
, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1002 { ARM_ID
, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1003 { ARM_ID
, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1004 { ARM_ID
, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1005 { ARM_ID
, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1006 { ARM_ID
, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1007 { ARM_ID
, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1008 { ARM_ID
, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1009 { ARM_ID
, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1010 { ARM_ID
, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1011 { ARM_ID
, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1012 { ARM_ID
, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1013 { ARM_ID
, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1014 { ARM_ID
, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1015 { ARM_ID
, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1016 { ARM_ID
, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1017 { ARM_ID
, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1018 { ARM_ID
, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1019 { ARM_ID
, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1020 { ARM_ID
, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1021 { ARM_ID
, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1022 { ARM_ID
, 0x9b7, "Cortex-R7 PMU", "(Performance Monitoring Unit)", },
1023 { ARM_ID
, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1024 { ARM_ID
, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1025 { ARM_ID
, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1026 { ARM_ID
, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1027 { ARM_ID
, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1028 { ARM_ID
, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1029 { ARM_ID
, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1030 { ARM_ID
, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1031 { ARM_ID
, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1032 { ARM_ID
, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1033 { ARM_ID
, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1034 { ARM_ID
, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1035 { ARM_ID
, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1036 { ARM_ID
, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1037 { ARM_ID
, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1038 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1039 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1040 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1041 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1042 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1043 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1044 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1045 /* legacy comment: 0x113: what? */
1046 { ANY_ID
, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1047 { ANY_ID
, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1050 static int dap_rom_display(struct command_context
*cmd_ctx
,
1051 struct adiv5_ap
*ap
, uint32_t dbgbase
, int depth
)
1059 command_print(cmd_ctx
, "\tTables too deep");
1064 snprintf(tabs
, sizeof(tabs
), "[L%02d] ", depth
);
1066 uint32_t base_addr
= dbgbase
& 0xFFFFF000;
1067 command_print(cmd_ctx
, "\t\tComponent base address 0x%08" PRIx32
, base_addr
);
1069 retval
= dap_read_part_id(ap
, base_addr
, &cid
, &pid
);
1070 if (retval
!= ERROR_OK
) {
1071 command_print(cmd_ctx
, "\t\tCan't read component, the corresponding core might be turned off");
1072 return ERROR_OK
; /* Don't abort recursion */
1075 if (!is_dap_cid_ok(cid
)) {
1076 command_print(cmd_ctx
, "\t\tInvalid CID 0x%08" PRIx32
, cid
);
1077 return ERROR_OK
; /* Don't abort recursion */
1080 /* component may take multiple 4K pages */
1081 uint32_t size
= (pid
>> 36) & 0xf;
1083 command_print(cmd_ctx
, "\t\tStart address 0x%08" PRIx32
, (uint32_t)(base_addr
- 0x1000 * size
));
1085 command_print(cmd_ctx
, "\t\tPeripheral ID 0x%010" PRIx64
, pid
);
1087 uint8_t class = (cid
>> 12) & 0xf;
1088 uint16_t part_num
= pid
& 0xfff;
1089 uint16_t designer_id
= ((pid
>> 32) & 0xf) << 8 | ((pid
>> 12) & 0xff);
1091 if (designer_id
& 0x80) {
1093 command_print(cmd_ctx
, "\t\tDesigner is 0x%03" PRIx16
", %s",
1094 designer_id
, jep106_manufacturer(designer_id
>> 8, designer_id
& 0x7f));
1096 /* Legacy ASCII ID, clear invalid bits */
1097 designer_id
&= 0x7f;
1098 command_print(cmd_ctx
, "\t\tDesigner ASCII code 0x%02" PRIx16
", %s",
1099 designer_id
, designer_id
== 0x41 ? "ARM" : "<unknown>");
1102 /* default values to be overwritten upon finding a match */
1103 const char *type
= "Unrecognized";
1104 const char *full
= "";
1106 /* search dap_partnums[] array for a match */
1107 for (unsigned entry
= 0; entry
< ARRAY_SIZE(dap_partnums
); entry
++) {
1109 if ((dap_partnums
[entry
].designer_id
!= designer_id
) && (dap_partnums
[entry
].designer_id
!= ANY_ID
))
1112 if (dap_partnums
[entry
].part_num
!= part_num
)
1115 type
= dap_partnums
[entry
].type
;
1116 full
= dap_partnums
[entry
].full
;
1120 command_print(cmd_ctx
, "\t\tPart is 0x%" PRIx16
", %s %s", part_num
, type
, full
);
1121 command_print(cmd_ctx
, "\t\tComponent class is 0x%" PRIx8
", %s", class, class_description
[class]);
1123 if (class == 1) { /* ROM Table */
1125 retval
= mem_ap_read_atomic_u32(ap
, base_addr
| 0xFCC, &memtype
);
1126 if (retval
!= ERROR_OK
)
1130 command_print(cmd_ctx
, "\t\tMEMTYPE system memory present on bus");
1132 command_print(cmd_ctx
, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1134 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1135 for (uint16_t entry_offset
= 0; entry_offset
< 0xF00; entry_offset
+= 4) {
1137 retval
= mem_ap_read_atomic_u32(ap
, base_addr
| entry_offset
, &romentry
);
1138 if (retval
!= ERROR_OK
)
1140 command_print(cmd_ctx
, "\t%sROMTABLE[0x%x] = 0x%" PRIx32
"",
1141 tabs
, entry_offset
, romentry
);
1142 if (romentry
& 0x01) {
1144 retval
= dap_rom_display(cmd_ctx
, ap
, base_addr
+ (romentry
& 0xFFFFF000), depth
+ 1);
1145 if (retval
!= ERROR_OK
)
1147 } else if (romentry
!= 0) {
1148 command_print(cmd_ctx
, "\t\tComponent not present");
1150 command_print(cmd_ctx
, "\t%s\tEnd of ROM table", tabs
);
1154 } else if (class == 9) { /* CoreSight component */
1155 const char *major
= "Reserved", *subtype
= "Reserved";
1158 retval
= mem_ap_read_atomic_u32(ap
, base_addr
| 0xFCC, &devtype
);
1159 if (retval
!= ERROR_OK
)
1161 unsigned minor
= (devtype
>> 4) & 0x0f;
1162 switch (devtype
& 0x0f) {
1164 major
= "Miscellaneous";
1170 subtype
= "Validation component";
1175 major
= "Trace Sink";
1192 major
= "Trace Link";
1198 subtype
= "Funnel, router";
1204 subtype
= "FIFO, buffer";
1209 major
= "Trace Source";
1215 subtype
= "Processor";
1221 subtype
= "Engine/Coprocessor";
1227 subtype
= "Software";
1232 major
= "Debug Control";
1238 subtype
= "Trigger Matrix";
1241 subtype
= "Debug Auth";
1244 subtype
= "Power Requestor";
1249 major
= "Debug Logic";
1255 subtype
= "Processor";
1261 subtype
= "Engine/Coprocessor";
1272 major
= "Perfomance Monitor";
1278 subtype
= "Processor";
1284 subtype
= "Engine/Coprocessor";
1295 command_print(cmd_ctx
, "\t\tType is 0x%02" PRIx8
", %s, %s",
1296 (uint8_t)(devtype
& 0xff),
1298 /* REVISIT also show 0xfc8 DevId */
1304 static int dap_info_command(struct command_context
*cmd_ctx
,
1305 struct adiv5_ap
*ap
)
1308 uint32_t dbgbase
, apid
;
1311 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1312 retval
= dap_get_debugbase(ap
, &dbgbase
, &apid
);
1313 if (retval
!= ERROR_OK
)
1316 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1318 command_print(cmd_ctx
, "No AP found at this ap 0x%x", ap
->ap_num
);
1322 switch (apid
& (IDR_JEP106
| IDR_TYPE
)) {
1323 case IDR_JEP106_ARM
| AP_TYPE_JTAG_AP
:
1324 command_print(cmd_ctx
, "\tType is JTAG-AP");
1326 case IDR_JEP106_ARM
| AP_TYPE_AHB_AP
:
1327 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1329 case IDR_JEP106_ARM
| AP_TYPE_APB_AP
:
1330 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1332 case IDR_JEP106_ARM
| AP_TYPE_AXI_AP
:
1333 command_print(cmd_ctx
, "\tType is MEM-AP AXI");
1336 command_print(cmd_ctx
, "\tUnknown AP type");
1340 /* NOTE: a MEM-AP may have a single CoreSight component that's
1341 * not a ROM table ... or have no such components at all.
1343 mem_ap
= (apid
& IDR_CLASS
) == AP_CLASS_MEM_AP
;
1345 command_print(cmd_ctx
, "MEM-AP BASE 0x%8.8" PRIx32
, dbgbase
);
1347 if (dbgbase
== 0xFFFFFFFF || (dbgbase
& 0x3) == 0x2) {
1348 command_print(cmd_ctx
, "\tNo ROM table present");
1351 command_print(cmd_ctx
, "\tValid ROM table present");
1353 command_print(cmd_ctx
, "\tROM table in legacy format");
1355 dap_rom_display(cmd_ctx
, ap
, dbgbase
& 0xFFFFF000, 0);
1362 int adiv5_jim_configure(struct target
*target
, Jim_GetOptInfo
*goi
)
1364 struct adiv5_private_config
*pc
;
1369 /* check if argv[0] is for us */
1370 arg
= Jim_GetString(goi
->argv
[0], NULL
);
1371 if (strcmp(arg
, "-ap-num"))
1372 return JIM_CONTINUE
;
1374 e
= Jim_GetOpt_String(goi
, &arg
, NULL
);
1378 if (goi
->argc
== 0) {
1379 Jim_WrongNumArgs(goi
->interp
, goi
->argc
, goi
->argv
, "-ap-num ?ap-number? ...");
1383 e
= Jim_GetOpt_Wide(goi
, &ap_num
);
1387 if (target
->private_config
== NULL
) {
1388 pc
= calloc(1, sizeof(struct adiv5_private_config
));
1389 target
->private_config
= pc
;
1390 pc
->ap_num
= ap_num
;
1397 COMMAND_HANDLER(handle_dap_info_command
)
1399 struct target
*target
= get_current_target(CMD_CTX
);
1400 struct arm
*arm
= target_to_arm(target
);
1401 struct adiv5_dap
*dap
= arm
->dap
;
1409 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1411 return ERROR_COMMAND_SYNTAX_ERROR
;
1414 return ERROR_COMMAND_SYNTAX_ERROR
;
1417 return dap_info_command(CMD_CTX
, &dap
->ap
[apsel
]);
1420 COMMAND_HANDLER(dap_baseaddr_command
)
1422 struct target
*target
= get_current_target(CMD_CTX
);
1423 struct arm
*arm
= target_to_arm(target
);
1424 struct adiv5_dap
*dap
= arm
->dap
;
1426 uint32_t apsel
, baseaddr
;
1434 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1435 /* AP address is in bits 31:24 of DP_SELECT */
1437 return ERROR_COMMAND_SYNTAX_ERROR
;
1440 return ERROR_COMMAND_SYNTAX_ERROR
;
1443 /* NOTE: assumes we're talking to a MEM-AP, which
1444 * has a base address. There are other kinds of AP,
1445 * though they're not common for now. This should
1446 * use the ID register to verify it's a MEM-AP.
1448 retval
= dap_queue_ap_read(dap_ap(dap
, apsel
), MEM_AP_REG_BASE
, &baseaddr
);
1449 if (retval
!= ERROR_OK
)
1451 retval
= dap_run(dap
);
1452 if (retval
!= ERROR_OK
)
1455 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1460 COMMAND_HANDLER(dap_memaccess_command
)
1462 struct target
*target
= get_current_target(CMD_CTX
);
1463 struct arm
*arm
= target_to_arm(target
);
1464 struct adiv5_dap
*dap
= arm
->dap
;
1466 uint32_t memaccess_tck
;
1470 memaccess_tck
= dap
->ap
[dap
->apsel
].memaccess_tck
;
1473 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1476 return ERROR_COMMAND_SYNTAX_ERROR
;
1478 dap
->ap
[dap
->apsel
].memaccess_tck
= memaccess_tck
;
1480 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1481 dap
->ap
[dap
->apsel
].memaccess_tck
);
1486 COMMAND_HANDLER(dap_apsel_command
)
1488 struct target
*target
= get_current_target(CMD_CTX
);
1489 struct arm
*arm
= target_to_arm(target
);
1490 struct adiv5_dap
*dap
= arm
->dap
;
1492 uint32_t apsel
, apid
;
1500 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1501 /* AP address is in bits 31:24 of DP_SELECT */
1503 return ERROR_COMMAND_SYNTAX_ERROR
;
1506 return ERROR_COMMAND_SYNTAX_ERROR
;
1511 retval
= dap_queue_ap_read(dap_ap(dap
, apsel
), AP_REG_IDR
, &apid
);
1512 if (retval
!= ERROR_OK
)
1514 retval
= dap_run(dap
);
1515 if (retval
!= ERROR_OK
)
1518 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1524 COMMAND_HANDLER(dap_apcsw_command
)
1526 struct target
*target
= get_current_target(CMD_CTX
);
1527 struct arm
*arm
= target_to_arm(target
);
1528 struct adiv5_dap
*dap
= arm
->dap
;
1530 uint32_t apcsw
= dap
->ap
[dap
->apsel
].csw_default
, sprot
= 0;
1534 command_print(CMD_CTX
, "apsel %" PRIi32
" selected, csw 0x%8.8" PRIx32
,
1535 (dap
->apsel
), apcsw
);
1538 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], sprot
);
1539 /* AP address is in bits 31:24 of DP_SELECT */
1541 return ERROR_COMMAND_SYNTAX_ERROR
;
1545 apcsw
&= ~CSW_SPROT
;
1548 return ERROR_COMMAND_SYNTAX_ERROR
;
1550 dap
->ap
[dap
->apsel
].csw_default
= apcsw
;
1557 COMMAND_HANDLER(dap_apid_command
)
1559 struct target
*target
= get_current_target(CMD_CTX
);
1560 struct arm
*arm
= target_to_arm(target
);
1561 struct adiv5_dap
*dap
= arm
->dap
;
1563 uint32_t apsel
, apid
;
1571 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1572 /* AP address is in bits 31:24 of DP_SELECT */
1574 return ERROR_COMMAND_SYNTAX_ERROR
;
1577 return ERROR_COMMAND_SYNTAX_ERROR
;
1580 retval
= dap_queue_ap_read(dap_ap(dap
, apsel
), AP_REG_IDR
, &apid
);
1581 if (retval
!= ERROR_OK
)
1583 retval
= dap_run(dap
);
1584 if (retval
!= ERROR_OK
)
1587 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1592 COMMAND_HANDLER(dap_apreg_command
)
1594 struct target
*target
= get_current_target(CMD_CTX
);
1595 struct arm
*arm
= target_to_arm(target
);
1596 struct adiv5_dap
*dap
= arm
->dap
;
1598 uint32_t apsel
, reg
, value
;
1601 if (CMD_ARGC
< 2 || CMD_ARGC
> 3)
1602 return ERROR_COMMAND_SYNTAX_ERROR
;
1604 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1605 /* AP address is in bits 31:24 of DP_SELECT */
1607 return ERROR_COMMAND_SYNTAX_ERROR
;
1609 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg
);
1610 if (reg
>= 256 || (reg
& 3))
1611 return ERROR_COMMAND_SYNTAX_ERROR
;
1613 if (CMD_ARGC
== 3) {
1614 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
1615 retval
= dap_queue_ap_write(dap_ap(dap
, apsel
), reg
, value
);
1617 retval
= dap_queue_ap_read(dap_ap(dap
, apsel
), reg
, &value
);
1619 if (retval
== ERROR_OK
)
1620 retval
= dap_run(dap
);
1622 if (retval
!= ERROR_OK
)
1626 command_print(CMD_CTX
, "0x%08" PRIx32
, value
);
1631 COMMAND_HANDLER(dap_ti_be_32_quirks_command
)
1633 struct target
*target
= get_current_target(CMD_CTX
);
1634 struct arm
*arm
= target_to_arm(target
);
1635 struct adiv5_dap
*dap
= arm
->dap
;
1637 uint32_t enable
= dap
->ti_be_32_quirks
;
1643 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], enable
);
1645 return ERROR_COMMAND_SYNTAX_ERROR
;
1648 return ERROR_COMMAND_SYNTAX_ERROR
;
1650 dap
->ti_be_32_quirks
= enable
;
1651 command_print(CMD_CTX
, "TI BE-32 quirks mode %s",
1652 enable
? "enabled" : "disabled");
1657 static const struct command_registration dap_commands
[] = {
1660 .handler
= handle_dap_info_command
,
1661 .mode
= COMMAND_EXEC
,
1662 .help
= "display ROM table for MEM-AP "
1663 "(default currently selected AP)",
1664 .usage
= "[ap_num]",
1668 .handler
= dap_apsel_command
,
1669 .mode
= COMMAND_EXEC
,
1670 .help
= "Set the currently selected AP (default 0) "
1671 "and display the result",
1672 .usage
= "[ap_num]",
1676 .handler
= dap_apcsw_command
,
1677 .mode
= COMMAND_EXEC
,
1678 .help
= "Set csw access bit ",
1684 .handler
= dap_apid_command
,
1685 .mode
= COMMAND_EXEC
,
1686 .help
= "return ID register from AP "
1687 "(default currently selected AP)",
1688 .usage
= "[ap_num]",
1692 .handler
= dap_apreg_command
,
1693 .mode
= COMMAND_EXEC
,
1694 .help
= "read/write a register from AP "
1695 "(reg is byte address of a word register, like 0 4 8...)",
1696 .usage
= "ap_num reg [value]",
1700 .handler
= dap_baseaddr_command
,
1701 .mode
= COMMAND_EXEC
,
1702 .help
= "return debug base address from MEM-AP "
1703 "(default currently selected AP)",
1704 .usage
= "[ap_num]",
1707 .name
= "memaccess",
1708 .handler
= dap_memaccess_command
,
1709 .mode
= COMMAND_EXEC
,
1710 .help
= "set/get number of extra tck for MEM-AP memory "
1711 "bus access [0-255]",
1712 .usage
= "[cycles]",
1715 .name
= "ti_be_32_quirks",
1716 .handler
= dap_ti_be_32_quirks_command
,
1717 .mode
= COMMAND_CONFIG
,
1718 .help
= "set/get quirks mode for TI TMS450/TMS570 processors",
1719 .usage
= "[enable]",
1721 COMMAND_REGISTRATION_DONE
1724 const struct command_registration dap_command_handlers
[] = {
1727 .mode
= COMMAND_EXEC
,
1728 .help
= "DAP command group",
1730 .chain
= dap_commands
,
1732 COMMAND_REGISTRATION_DONE