src/target/xscale.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  22  ***************************************************************************/
  23
  24 #ifndef XSCALE_H
  25 #define XSCALE_H
  26
  27 #include "arm.h"
  28 #include "armv4_5_mmu.h"
  29 #include "trace.h"
  30
  31 #define XSCALE_COMMON_MAGIC 0x58534341
  32
  33 /* These four JTAG instructions are architecturally defined.
  34  * Lengths are core-specific; originally 5 bits, later 7.
  35  */
  36 #define XSCALE_DBGRX    0x02
  37 #define XSCALE_DBGTX    0x10
  38 #define XSCALE_LDIC     0x07
  39 #define XSCALE_SELDCSR  0x09
  40
  41 /* Possible CPU types */
  42 #define XSCALE_IXP4XX_PXA2XX    0x0
  43 #define XSCALE_PXA3XX           0x4
  44
  45 enum xscale_debug_reason {
  46         XSCALE_DBG_REASON_GENERIC,
  47         XSCALE_DBG_REASON_RESET,
  48         XSCALE_DBG_REASON_TB_FULL,
  49 };
  50
  51 enum xscale_trace_entry_type {
  52         XSCALE_TRACE_MESSAGE = 0x0,
  53         XSCALE_TRACE_ADDRESS = 0x1,
  54 };
  55
  56 struct xscale_trace_entry {
  57         uint8_t data;
  58         enum xscale_trace_entry_type type;
  59 };
  60
  61 struct xscale_trace_data {
  62         struct xscale_trace_entry *entries;
  63         int depth;
  64         uint32_t chkpt0;
  65         uint32_t chkpt1;
  66         uint32_t last_instruction;
  67         unsigned int num_checkpoints;
  68         struct xscale_trace_data *next;
  69 };
  70
  71 enum trace_mode {
  72         XSCALE_TRACE_DISABLED,
  73         XSCALE_TRACE_FILL,
  74         XSCALE_TRACE_WRAP
  75 };
  76
  77 struct xscale_trace {
  78         struct image *image;                                    /* source for target opcodes */
  79         struct xscale_trace_data *data;         /* linked list of collected trace data */
  80         int buffer_fill;                                /* maximum number of trace runs to read */
  81         int fill_counter;                               /* running count during trace collection */
  82         enum trace_mode mode;
  83         enum arm_state core_state;      /* current core state (ARM, Thumb) */
  84 };
  85
  86 struct xscale_common {
  87         /* armv4/5 common stuff */
  88         struct arm arm;
  89
  90         int common_magic;
  91
  92         /* XScale registers (CP15, DBG) */
  93         struct reg_cache *reg_cache;
  94
  95         /* current state of the debug handler */
  96         uint32_t handler_address;
  97
  98         /* target-endian buffers with exception vectors */
  99         uint32_t low_vectors[8];
 100         uint32_t high_vectors[8];
 101
 102         /* static low vectors */
 103         uint8_t static_low_vectors_set; /* bit field with static vectors set by the user */
 104         uint8_t static_high_vectors_set; /* bit field with static vectors set by the user */
 105         uint32_t static_low_vectors[8];
 106         uint32_t static_high_vectors[8];
 107
 108         /* DCache cleaning */
 109         uint32_t cache_clean_address;
 110
 111         /* whether hold_rst and ext_dbg_break should be set */
 112         int hold_rst;
 113         int external_debug_break;
 114
 115         /* breakpoint / watchpoint handling */
 116         int dbr_available;
 117         int dbr0_used;
 118         int dbr1_used;
 119         int ibcr_available;
 120         int ibcr0_used;
 121         int     ibcr1_used;
 122         uint32_t arm_bkpt;
 123         uint16_t thumb_bkpt;
 124
 125         uint8_t vector_catch;
 126
 127         struct xscale_trace trace;
 128
 129         int arch_debug_reason;
 130
 131         /* MMU/Caches */
 132         struct armv4_5_mmu_common armv4_5_mmu;
 133         uint32_t cp15_control_reg;
 134
 135         int fast_memory_access;
 136
 137         /* CPU variant */
 138         int xscale_variant;
 139 };
 140
 141 static inline struct xscale_common *
 142 target_to_xscale(struct target *target)
 143 {
 144         return container_of(target->arch_info, struct xscale_common, arm);
 145 }
 146
 147 struct xscale_reg {
 148         int dbg_handler_number;
 149         struct target *target;
 150 };
 151
 152 enum {
 153         XSCALE_MAINID,          /* 0 */
 154         XSCALE_CACHETYPE,
 155         XSCALE_CTRL,
 156         XSCALE_AUXCTRL,
 157         XSCALE_TTB,
 158         XSCALE_DAC,
 159         XSCALE_FSR,
 160         XSCALE_FAR,
 161         XSCALE_PID,
 162         XSCALE_CPACCESS,
 163         XSCALE_IBCR0,           /* 10 */
 164         XSCALE_IBCR1,
 165         XSCALE_DBR0,
 166         XSCALE_DBR1,
 167         XSCALE_DBCON,
 168         XSCALE_TBREG,
 169         XSCALE_CHKPT0,
 170         XSCALE_CHKPT1,
 171         XSCALE_DCSR,
 172         XSCALE_TX,
 173         XSCALE_RX,                      /* 20 */
 174         XSCALE_TXRXCTRL,
 175 };
 176
 177 #define ERROR_XSCALE_NO_TRACE_DATA      (-700)
 178
 179 /* DCSR bit and field definitions */
 180 #define DCSR_TR (1 << 16)
 181 #define DCSR_TU (1 << 17)
 182 #define DCSR_TS (1 << 18)
 183 #define DCSR_TA (1 << 19)
 184 #define DCSR_TD (1 << 20)
 185 #define DCSR_TI (1 << 22)
 186 #define DCSR_TF (1 << 23)
 187 #define DCSR_TRAP_MASK \
 188         (DCSR_TF | DCSR_TI | DCSR_TD | DCSR_TA | DCSR_TS | DCSR_TU | DCSR_TR)
 189
 190 #endif /* XSCALE_H */