1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
9 ***************************************************************************/
11 #ifndef OPENOCD_TARGET_XSCALE_H
12 #define OPENOCD_TARGET_XSCALE_H
15 #include "armv4_5_mmu.h"
18 #define XSCALE_COMMON_MAGIC 0x58534341U
20 /* These four JTAG instructions are architecturally defined.
21 * Lengths are core-specific; originally 5 bits, later 7.
23 #define XSCALE_DBGRX 0x02
24 #define XSCALE_DBGTX 0x10
25 #define XSCALE_LDIC 0x07
26 #define XSCALE_SELDCSR 0x09
28 /* Possible CPU types */
29 #define XSCALE_IXP4XX_PXA2XX 0x0
30 #define XSCALE_PXA3XX 0x4
32 enum xscale_debug_reason
{
33 XSCALE_DBG_REASON_GENERIC
,
34 XSCALE_DBG_REASON_RESET
,
35 XSCALE_DBG_REASON_TB_FULL
,
38 enum xscale_trace_entry_type
{
39 XSCALE_TRACE_MESSAGE
= 0x0,
40 XSCALE_TRACE_ADDRESS
= 0x1,
43 struct xscale_trace_entry
{
45 enum xscale_trace_entry_type type
;
48 struct xscale_trace_data
{
49 struct xscale_trace_entry
*entries
;
53 uint32_t last_instruction
;
54 unsigned int num_checkpoints
;
55 struct xscale_trace_data
*next
;
59 XSCALE_TRACE_DISABLED
,
65 struct image
*image
; /* source for target opcodes */
66 struct xscale_trace_data
*data
; /* linked list of collected trace data */
67 int buffer_fill
; /* maximum number of trace runs to read */
68 int fill_counter
; /* running count during trace collection */
70 enum arm_state core_state
; /* current core state (ARM, Thumb) */
73 struct xscale_common
{
74 unsigned int common_magic
;
76 /* armv4/5 common stuff */
79 /* XScale registers (CP15, DBG) */
80 struct reg_cache
*reg_cache
;
82 /* current state of the debug handler */
83 uint32_t handler_address
;
85 /* target-endian buffers with exception vectors */
86 uint32_t low_vectors
[8];
87 uint32_t high_vectors
[8];
89 /* static low vectors */
90 uint8_t static_low_vectors_set
; /* bit field with static vectors set by the user */
91 uint8_t static_high_vectors_set
; /* bit field with static vectors set by the user */
92 uint32_t static_low_vectors
[8];
93 uint32_t static_high_vectors
[8];
96 uint32_t cache_clean_address
;
98 /* whether hold_rst and ext_dbg_break should be set */
100 int external_debug_break
;
102 /* breakpoint / watchpoint handling */
112 uint8_t vector_catch
;
114 struct xscale_trace trace
;
116 int arch_debug_reason
;
119 struct armv4_5_mmu_common armv4_5_mmu
;
120 uint32_t cp15_control_reg
;
122 int fast_memory_access
;
128 static inline struct xscale_common
*
129 target_to_xscale(struct target
*target
)
131 return container_of(target
->arch_info
, struct xscale_common
, arm
);
135 int dbg_handler_number
;
136 struct target
*target
;
140 XSCALE_MAINID
, /* 0 */
150 XSCALE_IBCR0
, /* 10 */
164 #define ERROR_XSCALE_NO_TRACE_DATA (-700)
166 /* DCSR bit and field definitions */
167 #define DCSR_TR (1 << 16)
168 #define DCSR_TU (1 << 17)
169 #define DCSR_TS (1 << 18)
170 #define DCSR_TA (1 << 19)
171 #define DCSR_TD (1 << 20)
172 #define DCSR_TI (1 << 22)
173 #define DCSR_TF (1 << 23)
174 #define DCSR_TRAP_MASK \
175 (DCSR_TF | DCSR_TI | DCSR_TD | DCSR_TA | DCSR_TS | DCSR_TU | DCSR_TR)
177 #endif /* OPENOCD_TARGET_XSCALE_H */