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openocd: src/flash: replace the GPL-2.0-or-later license tag
[openocd.git] / src / flash / nand / davinci.c
blob28e31f2a45b4bacbd7666dbba17e7995879c9c7d
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 /***************************************************************************
4 * Copyright (C) 2009 by David Brownell *
5 ***************************************************************************/
6
7 /*
8 * DaVinci family NAND controller support for OpenOCD.
9 *
10 * This driver uses hardware ECC (1-bit or 4-bit) unless
11 * the chip is accessed in "raw" mode.
12 */
13
14 #ifdef HAVE_CONFIG_H
15 #include "config.h"
16 #endif
17
18 #include "imp.h"
19 #include "arm_io.h"
20 #include <target/target.h>
21
22 enum ecc {
23 HWECC1, /* all controllers support 1-bit ECC */
24 HWECC4, /* newer chips also have 4-bit ECC hardware */
25 HWECC4_INFIX, /* avoid this layout, except maybe for boot code */
26 };
27
28 struct davinci_nand {
29 uint8_t chipsel; /* chipselect 0..3 == CS2..CS5 */
30 uint8_t eccmode;
31
32 /* Async EMIF controller base */
33 uint32_t aemif;
34
35 /* NAND chip addresses */
36 uint32_t data; /* without CLE or ALE */
37 uint32_t cmd; /* with CLE */
38 uint32_t addr; /* with ALE */
39
40 /* write acceleration */
41 struct arm_nand_data io;
42
43 /* page i/o for the relevant flavor of hardware ECC */
44 int (*read_page)(struct nand_device *nand, uint32_t page,
45 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
46 int (*write_page)(struct nand_device *nand, uint32_t page,
47 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
48 };
49
50 #define NANDFCR 0x60 /* flash control register */
51 #define NANDFSR 0x64 /* flash status register */
52 #define NANDFECC 0x70 /* 1-bit ECC data, CS0, 1st of 4 */
53 #define NAND4BITECCLOAD 0xbc /* 4-bit ECC, load saved values */
54 #define NAND4BITECC 0xc0 /* 4-bit ECC data, 1st of 4 */
55 #define NANDERRADDR 0xd0 /* 4-bit ECC err addr, 1st of 2 */
56 #define NANDERRVAL 0xd8 /* 4-bit ECC err value, 1st of 2 */
57
58 static int halted(struct target *target, const char *label)
59 {
60 if (target->state == TARGET_HALTED)
61 return true;
62
63 LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
64 return false;
65 }
66
67 static int davinci_init(struct nand_device *nand)
68 {
69 struct davinci_nand *info = nand->controller_priv;
70 struct target *target = nand->target;
71 uint32_t nandfcr;
72
73 if (!halted(target, "init"))
74 return ERROR_NAND_OPERATION_FAILED;
75
76 /* We require something else to have configured AEMIF to talk
77 * to NAND chip in this range (including timings and width).
78 */
79 target_read_u32(target, info->aemif + NANDFCR, &nandfcr);
80 if (!(nandfcr & (1 << info->chipsel))) {
81 LOG_ERROR("chip address %08" PRIx32 " not NAND-enabled?", info->data);
82 return ERROR_NAND_OPERATION_FAILED;
83 }
84
85 /* REVISIT verify: AxCR must be in 8-bit mode, since that's all we
86 * tested. 16 bit support should work too; but not with 4-bit ECC.
87 */
88
89 return ERROR_OK;
90 }
91
92 static int davinci_reset(struct nand_device *nand)
93 {
94 return ERROR_OK;
95 }
96
97 static int davinci_nand_ready(struct nand_device *nand, int timeout)
98 {
99 struct davinci_nand *info = nand->controller_priv;
100 struct target *target = nand->target;
101 uint32_t nandfsr;
102
103 /* NOTE: return code is zero/error, else success; not ERROR_* */
104
105 if (!halted(target, "ready"))
106 return 0;
107
108 do {
109 target_read_u32(target, info->aemif + NANDFSR, &nandfsr);
110
111 if (nandfsr & 0x01)
112 return 1;
113
114 alive_sleep(1);
115 } while (timeout-- > 0);
116
117 return 0;
118 }
119
120 static int davinci_command(struct nand_device *nand, uint8_t command)
121 {
122 struct davinci_nand *info = nand->controller_priv;
123 struct target *target = nand->target;
124
125 if (!halted(target, "command"))
126 return ERROR_NAND_OPERATION_FAILED;
127
128 target_write_u8(target, info->cmd, command);
129 return ERROR_OK;
130 }
131
132 static int davinci_address(struct nand_device *nand, uint8_t address)
133 {
134 struct davinci_nand *info = nand->controller_priv;
135 struct target *target = nand->target;
136
137 if (!halted(target, "address"))
138 return ERROR_NAND_OPERATION_FAILED;
139
140 target_write_u8(target, info->addr, address);
141 return ERROR_OK;
142 }
143
144 static int davinci_write_data(struct nand_device *nand, uint16_t data)
145 {
146 struct davinci_nand *info = nand->controller_priv;
147 struct target *target = nand->target;
148
149 if (!halted(target, "write_data"))
150 return ERROR_NAND_OPERATION_FAILED;
151
152 target_write_u8(target, info->data, data);
153 return ERROR_OK;
154 }
155
156 static int davinci_read_data(struct nand_device *nand, void *data)
157 {
158 struct davinci_nand *info = nand->controller_priv;
159 struct target *target = nand->target;
160
161 if (!halted(target, "read_data"))
162 return ERROR_NAND_OPERATION_FAILED;
163
164 target_read_u8(target, info->data, data);
165 return ERROR_OK;
166 }
167
168 /* REVISIT a bit of native code should let block reads be MUCH faster */
169
170 static int davinci_read_block_data(struct nand_device *nand,
171 uint8_t *data, int data_size)
172 {
173 struct davinci_nand *info = nand->controller_priv;
174 struct target *target = nand->target;
175 uint32_t nfdata = info->data;
176 uint32_t tmp;
177
178 if (!halted(target, "read_block"))
179 return ERROR_NAND_OPERATION_FAILED;
180
181 while (data_size >= 4) {
182 target_read_u32(target, nfdata, &tmp);
183
184 data[0] = tmp;
185 data[1] = tmp >> 8;
186 data[2] = tmp >> 16;
187 data[3] = tmp >> 24;
188
189 data_size -= 4;
190 data += 4;
191 }
192
193 while (data_size > 0) {
194 target_read_u8(target, nfdata, data);
195
196 data_size -= 1;
197 data += 1;
198 }
199
200 return ERROR_OK;
201 }
202
203 static int davinci_write_block_data(struct nand_device *nand,
204 uint8_t *data, int data_size)
205 {
206 struct davinci_nand *info = nand->controller_priv;
207 struct target *target = nand->target;
208 uint32_t nfdata = info->data;
209 uint32_t tmp;
210 int status;
211
212 if (!halted(target, "write_block"))
213 return ERROR_NAND_OPERATION_FAILED;
214
215 /* try the fast way first */
216 status = arm_nandwrite(&info->io, data, data_size);
217 if (status != ERROR_NAND_NO_BUFFER)
218 return status;
219
220 /* else do it slowly */
221 while (data_size >= 4) {
222 tmp = le_to_h_u32(data);
223 target_write_u32(target, nfdata, tmp);
224
225 data_size -= 4;
226 data += 4;
227 }
228
229 while (data_size > 0) {
230 target_write_u8(target, nfdata, *data);
231
232 data_size -= 1;
233 data += 1;
234 }
235
236 return ERROR_OK;
237 }
238
239 static int davinci_write_page(struct nand_device *nand, uint32_t page,
240 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
241 {
242 struct davinci_nand *info = nand->controller_priv;
243 uint8_t *ooballoc = NULL;
244 int status;
245
246 if (!nand->device)
247 return ERROR_NAND_DEVICE_NOT_PROBED;
248 if (!halted(nand->target, "write_page"))
249 return ERROR_NAND_OPERATION_FAILED;
250
251 /* Always write both data and OOB ... we are not "raw" I/O! */
252 if (!data) {
253 LOG_ERROR("Missing NAND data; try 'nand raw_access enable'");
254 return ERROR_NAND_OPERATION_FAILED;
255 }
256
257 /* If we're not given OOB, write 0xff where we don't write ECC codes. */
258 switch (nand->page_size) {
259 case 512:
260 oob_size = 16;
261 break;
262 case 2048:
263 oob_size = 64;
264 break;
265 case 4096:
266 oob_size = 128;
267 break;
268 default:
269 return ERROR_NAND_OPERATION_FAILED;
270 }
271 if (!oob) {
272 ooballoc = malloc(oob_size);
273 if (!ooballoc)
274 return ERROR_NAND_OPERATION_FAILED;
275 oob = ooballoc;
276 memset(oob, 0x0ff, oob_size);
277 }
278
279 /* REVISIT avoid wasting SRAM: unless nand->use_raw is set,
280 * use 512 byte chunks. Read side support will often want
281 * to include oob_size ...
282 */
283 info->io.chunk_size = nand->page_size;
284
285 status = info->write_page(nand, page, data, data_size, oob, oob_size);
286 free(ooballoc);
287 return status;
288 }
289
290 static int davinci_read_page(struct nand_device *nand, uint32_t page,
291 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
292 {
293 struct davinci_nand *info = nand->controller_priv;
294
295 if (!nand->device)
296 return ERROR_NAND_DEVICE_NOT_PROBED;
297 if (!halted(nand->target, "read_page"))
298 return ERROR_NAND_OPERATION_FAILED;
299
300 return info->read_page(nand, page, data, data_size, oob, oob_size);
301 }
302
303 static void davinci_write_pagecmd(struct nand_device *nand, uint8_t cmd, uint32_t page)
304 {
305 struct davinci_nand *info = nand->controller_priv;
306 struct target *target = nand->target;
307 int page3 = nand->address_cycles - (nand->page_size == 512);
308
309 /* write command ({page,otp}x{read,program} */
310 target_write_u8(target, info->cmd, cmd);
311
312 /* column address (beginning-of-page) */
313 target_write_u8(target, info->addr, 0);
314 if (nand->page_size > 512)
315 target_write_u8(target, info->addr, 0);
316
317 /* page address */
318 target_write_u8(target, info->addr, page);
319 target_write_u8(target, info->addr, page >> 8);
320 if (page3)
321 target_write_u8(target, info->addr, page >> 16);
322 if (page3 == 2)
323 target_write_u8(target, info->addr, page >> 24);
324 }
325
326 static int davinci_seek_column(struct nand_device *nand, uint16_t column)
327 {
328 struct davinci_nand *info = nand->controller_priv;
329 struct target *target = nand->target;
330
331 /* Random read, we must have issued a page read already */
332 target_write_u8(target, info->cmd, NAND_CMD_RNDOUT);
333
334 target_write_u8(target, info->addr, column);
335
336 if (nand->page_size > 512) {
337 target_write_u8(target, info->addr, column >> 8);
338 target_write_u8(target, info->cmd, NAND_CMD_RNDOUTSTART);
339 }
340
341 if (!davinci_nand_ready(nand, 100))
342 return ERROR_NAND_OPERATION_TIMEOUT;
343
344 return ERROR_OK;
345 }
346
347 static int davinci_writepage_tail(struct nand_device *nand,
348 uint8_t *oob, uint32_t oob_size)
349 {
350 struct davinci_nand *info = nand->controller_priv;
351 struct target *target = nand->target;
352 uint8_t status;
353
354 if (oob_size)
355 davinci_write_block_data(nand, oob, oob_size);
356
357 /* non-cachemode page program */
358 target_write_u8(target, info->cmd, NAND_CMD_PAGEPROG);
359
360 if (!davinci_nand_ready(nand, 100))
361 return ERROR_NAND_OPERATION_TIMEOUT;
362
363 if (nand_read_status(nand, &status) != ERROR_OK) {
364 LOG_ERROR("couldn't read status");
365 return ERROR_NAND_OPERATION_FAILED;
366 }
367
368 if (status & NAND_STATUS_FAIL) {
369 LOG_ERROR("write operation failed, status: 0x%02x", status);
370 return ERROR_NAND_OPERATION_FAILED;
371 }
372
373 return ERROR_OK;
374 }
375
376 /*
377 * All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
378 */
379 static int davinci_write_page_ecc1(struct nand_device *nand, uint32_t page,
380 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
381 {
382 unsigned oob_offset;
383 struct davinci_nand *info = nand->controller_priv;
384 struct target *target = nand->target;
385 const uint32_t fcr_addr = info->aemif + NANDFCR;
386 const uint32_t ecc1_addr = info->aemif + NANDFECC + (4 * info->chipsel);
387 uint32_t fcr, ecc1;
388
389 /* Write contiguous ECC bytes starting at specified offset.
390 * NOTE: Linux reserves twice as many bytes as we need; and
391 * for 16-bit OOB, those extra bytes are discontiguous.
392 */
393 switch (nand->page_size) {
394 case 512:
395 oob_offset = 0;
396 break;
397 case 2048:
398 oob_offset = 40;
399 break;
400 default:
401 oob_offset = 80;
402 break;
403 }
404
405 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
406
407 /* scrub any old ECC state */
408 target_read_u32(target, ecc1_addr, &ecc1);
409
410 target_read_u32(target, fcr_addr, &fcr);
411 fcr |= 1 << (8 + info->chipsel);
412
413 do {
414 /* set "start csX 1bit ecc" bit */
415 target_write_u32(target, fcr_addr, fcr);
416
417 /* write 512 bytes */
418 davinci_write_block_data(nand, data, 512);
419 data += 512;
420 data_size -= 512;
421
422 /* read the ecc, pack to 3 bytes, and invert so the ecc
423 * in an erased block is correct
424 */
425 target_read_u32(target, ecc1_addr, &ecc1);
426 ecc1 = (ecc1 & 0x0fff) | ((ecc1 & 0x0fff0000) >> 4);
427 ecc1 = ~ecc1;
428
429 /* save correct ECC code into oob data */
430 oob[oob_offset++] = (uint8_t)(ecc1);
431 oob[oob_offset++] = (uint8_t)(ecc1 >> 8);
432 oob[oob_offset++] = (uint8_t)(ecc1 >> 16);
433
434 } while (data_size);
435
436 /* write OOB into spare area */
437 return davinci_writepage_tail(nand, oob, oob_size);
438 }
439
440 /*
441 * Preferred "new style" ECC layout for use with 4-bit ECC. This somewhat
442 * slows down large page reads done with error correction (since the OOB
443 * is read first, so its ECC data can be used incrementally), but the
444 * manufacturer bad block markers are safe. Contrast: old "infix" style.
445 */
446 static int davinci_write_page_ecc4(struct nand_device *nand, uint32_t page,
447 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
448 {
449 static const uint8_t ecc512[] = {
450 0, 1, 2, 3, 4, /* 5== mfr badblock */
451 6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15,
452 };
453 static const uint8_t ecc2048[] = {
454 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
455 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
456 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
457 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
458 };
459 static const uint8_t ecc4096[] = {
460 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
461 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
462 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
463 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
464 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
465 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
466 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
467 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
468 };
469
470 struct davinci_nand *info = nand->controller_priv;
471 const uint8_t *l;
472 struct target *target = nand->target;
473 const uint32_t fcr_addr = info->aemif + NANDFCR;
474 const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
475 uint32_t fcr, ecc4;
476
477 /* Use the same ECC layout Linux uses. For small page chips
478 * it's a bit cramped.
479 *
480 * NOTE: at this writing, 4KB pages have issues in Linux
481 * because they need more than 64 bytes of ECC data, which
482 * the standard ECC logic can't handle.
483 */
484 switch (nand->page_size) {
485 case 512:
486 l = ecc512;
487 break;
488 case 2048:
489 l = ecc2048;
490 break;
491 default:
492 l = ecc4096;
493 break;
494 }
495
496 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
497
498 /* scrub any old ECC state */
499 target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
500
501 target_read_u32(target, fcr_addr, &fcr);
502 fcr &= ~(0x03 << 4);
503 fcr |= (1 << 12) | (info->chipsel << 4);
504
505 do {
506 uint32_t raw_ecc[4], *p;
507 int i;
508
509 /* start 4bit ecc on csX */
510 target_write_u32(target, fcr_addr, fcr);
511
512 /* write 512 bytes */
513 davinci_write_block_data(nand, data, 512);
514 data += 512;
515 data_size -= 512;
516
517 /* read the ecc, then save it into 10 bytes in the oob */
518 for (i = 0; i < 4; i++) {
519 target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
520 raw_ecc[i] &= 0x03ff03ff;
521 }
522 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
523 oob[*l++] = p[0] & 0xff;
524 oob[*l++] = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
525 oob[*l++] = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
526 oob[*l++] = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
527 oob[*l++] = (p[1] >> 18) & 0xff;
528 }
529
530 } while (data_size);
531
532 /* write OOB into spare area */
533 return davinci_writepage_tail(nand, oob, oob_size);
534 }
535
536 /*
537 * "Infix" OOB ... like Linux ECC_HW_SYNDROME. Avoided because it trashes
538 * manufacturer bad block markers, except on small page chips. Once you
539 * write to a page using this scheme, you need specialized code to update
540 * it (code which ignores now-invalid bad block markers).
541 *
542 * This is needed *only* to support older firmware. Older ROM Boot Loaders
543 * need it to read their second stage loader (UBL) into SRAM, but from then
544 * on the whole system can use the cleaner non-infix layouts. Systems with
545 * older second stage loaders (ABL/U-Boot, etc) or other system software
546 * (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
547 */
548 static int davinci_write_page_ecc4infix(struct nand_device *nand, uint32_t page,
549 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
550 {
551 struct davinci_nand *info = nand->controller_priv;
552 struct target *target = nand->target;
553 const uint32_t fcr_addr = info->aemif + NANDFCR;
554 const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
555 uint32_t fcr, ecc4;
556
557 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
558
559 /* scrub any old ECC state */
560 target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
561
562 target_read_u32(target, fcr_addr, &fcr);
563 fcr &= ~(0x03 << 4);
564 fcr |= (1 << 12) | (info->chipsel << 4);
565
566 do {
567 uint32_t raw_ecc[4], *p;
568 uint8_t *l;
569 int i;
570
571 /* start 4bit ecc on csX */
572 target_write_u32(target, fcr_addr, fcr);
573
574 /* write 512 bytes */
575 davinci_write_block_data(nand, data, 512);
576 data += 512;
577 data_size -= 512;
578
579 /* read the ecc */
580 for (i = 0; i < 4; i++) {
581 target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
582 raw_ecc[i] &= 0x03ff03ff;
583 }
584
585 /* skip 6 bytes of prepad, then pack 10 packed ecc bytes */
586 for (i = 0, l = oob + 6, p = raw_ecc; i < 2; i++, p += 2) {
587 *l++ = p[0] & 0xff;
588 *l++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
589 *l++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
590 *l++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
591 *l++ = (p[1] >> 18) & 0xff;
592 }
593
594 /* write this "out-of-band" data -- infix */
595 davinci_write_block_data(nand, oob, 16);
596 oob += 16;
597 } while (data_size);
598
599 /* the last data and OOB writes included the spare area */
600 return davinci_writepage_tail(nand, NULL, 0);
601 }
602
603 static int davinci_read_page_ecc4infix(struct nand_device *nand, uint32_t page,
604 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
605 {
606 int read_size;
607 int want_col, at_col;
608 int ret;
609
610 davinci_write_pagecmd(nand, NAND_CMD_READ0, page);
611
612 /* large page devices need a start command */
613 if (nand->page_size > 512)
614 davinci_command(nand, NAND_CMD_READSTART);
615
616 if (!davinci_nand_ready(nand, 100))
617 return ERROR_NAND_OPERATION_TIMEOUT;
618
619 /* NOTE: not bothering to compute and use ECC data for now */
620
621 want_col = 0;
622 at_col = 0;
623 while ((data && data_size) || (oob && oob_size)) {
624
625 if (data && data_size) {
626 if (want_col != at_col) {
627 /* Reads are slow, so seek past them when we can */
628 ret = davinci_seek_column(nand, want_col);
629 if (ret != ERROR_OK)
630 return ret;
631 at_col = want_col;
632 }
633 /* read 512 bytes or data_size, whichever is smaller*/
634 read_size = data_size > 512 ? 512 : data_size;
635 davinci_read_block_data(nand, data, read_size);
636 data += read_size;
637 data_size -= read_size;
638 at_col += read_size;
639 }
640 want_col += 512;
641
642 if (oob && oob_size) {
643 if (want_col != at_col) {
644 ret = davinci_seek_column(nand, want_col);
645 if (ret != ERROR_OK)
646 return ret;
647 at_col = want_col;
648 }
649 /* read this "out-of-band" data -- infix */
650 read_size = oob_size > 16 ? 16 : oob_size;
651 davinci_read_block_data(nand, oob, read_size);
652 oob += read_size;
653 oob_size -= read_size;
654 at_col += read_size;
655 }
656 want_col += 16;
657 }
658 return ERROR_OK;
659 }
660
661 NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command)
662 {
663 struct davinci_nand *info;
664 unsigned long chip, aemif;
665 enum ecc eccmode;
666 int chipsel;
667
668 /* arguments:
669 * - "davinci"
670 * - target
671 * - nand chip address
672 * - ecc mode
673 * - aemif address
674 * Plus someday, optionally, ALE and CLE masks.
675 */
676 if (CMD_ARGC < 5)
677 return ERROR_COMMAND_SYNTAX_ERROR;
678
679 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip);
680 if (chip == 0) {
681 LOG_ERROR("Invalid NAND chip address %s", CMD_ARGV[2]);
682 goto fail;
683 }
684
685 if (strcmp(CMD_ARGV[3], "hwecc1") == 0)
686 eccmode = HWECC1;
687 else if (strcmp(CMD_ARGV[3], "hwecc4") == 0)
688 eccmode = HWECC4;
689 else if (strcmp(CMD_ARGV[3], "hwecc4_infix") == 0)
690 eccmode = HWECC4_INFIX;
691 else {
692 LOG_ERROR("Invalid ecc mode %s", CMD_ARGV[3]);
693 goto fail;
694 }
695
696 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[4], aemif);
697 if (aemif == 0) {
698 LOG_ERROR("Invalid AEMIF controller address %s", CMD_ARGV[4]);
699 goto fail;
700 }
701
702 /* REVISIT what we'd *like* to do is look up valid ranges using
703 * target-specific declarations, and not even need to pass the
704 * AEMIF controller address.
705 */
706 if (aemif == 0x01e00000 /* dm6446, dm357 */
707 || aemif == 0x01e10000 /* dm335, dm355 */
708 || aemif == 0x01d10000 /* dm365 */
709 ) {
710 if (chip < 0x02000000 || chip >= 0x0a000000) {
711 LOG_ERROR("NAND address %08lx out of range?", chip);
712 goto fail;
713 }
714 chipsel = (chip - 0x02000000) >> 25;
715 } else {
716 LOG_ERROR("unrecognized AEMIF controller address %08lx", aemif);
717 goto fail;
718 }
719
720 info = calloc(1, sizeof(*info));
721 if (!info)
722 goto fail;
723
724 info->eccmode = eccmode;
725 info->chipsel = chipsel;
726 info->aemif = aemif;
727 info->data = chip;
728 info->cmd = chip | 0x10;
729 info->addr = chip | 0x08;
730
731 nand->controller_priv = info;
732
733 info->io.target = nand->target;
734 info->io.data = info->data;
735 info->io.op = ARM_NAND_NONE;
736
737 /* NOTE: for now we don't do any error correction on read.
738 * Nothing else in OpenOCD currently corrects read errors,
739 * and in any case it's *writing* that we care most about.
740 */
741 info->read_page = nand_read_page_raw;
742
743 switch (eccmode) {
744 case HWECC1:
745 /* ECC_HW, 1-bit corrections, 3 bytes ECC per 512 data bytes */
746 info->write_page = davinci_write_page_ecc1;
747 break;
748 case HWECC4:
749 /* ECC_HW, 4-bit corrections, 10 bytes ECC per 512 data bytes */
750 info->write_page = davinci_write_page_ecc4;
751 break;
752 case HWECC4_INFIX:
753 /* Same 4-bit ECC HW, with problematic page/ecc layout */
754 info->read_page = davinci_read_page_ecc4infix;
755 info->write_page = davinci_write_page_ecc4infix;
756 break;
757 }
758
759 return ERROR_OK;
760
761 fail:
762 return ERROR_NAND_OPERATION_FAILED;
763 }
764
765 struct nand_flash_controller davinci_nand_controller = {
766 .name = "davinci",
767 .usage = "chip_addr hwecc_mode aemif_addr",
768 .nand_device_command = davinci_nand_device_command,
769 .init = davinci_init,
770 .reset = davinci_reset,
771 .command = davinci_command,
772 .address = davinci_address,
773 .write_data = davinci_write_data,
774 .read_data = davinci_read_data,
775 .write_page = davinci_write_page,
776 .read_page = davinci_read_page,
777 .write_block_data = davinci_write_block_data,
778 .read_block_data = davinci_read_block_data,
779 .nand_ready = davinci_nand_ready,
780 };
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