?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
adi_v5: Remove unnecessary MEM-AP access functions
[openocd.git] / src / target / arm_adi_v5.c
blob41bd26153ffb0df984e90eb1ef595222e074667d
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
31
32 /**
33 * @file
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
39 *
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
48 *
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 */
60
61 /*
62 * Relevant specifications from ARM include:
63 *
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
66 *
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
69 */
70
71 #ifdef HAVE_CONFIG_H
72 #include "config.h"
73 #endif
74
75 #include "jtag/interface.h"
76 #include "arm.h"
77 #include "arm_adi_v5.h"
78 #include <helper/time_support.h>
79
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
81
82 /*
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
85 */
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
87 {
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
89 }
90
91 /***************************************************************************
92 * *
93 * DP and MEM-AP register access through APACC and DPACC *
94 * *
95 ***************************************************************************/
96
97 /**
98 * Select one of the APs connected to the specified DAP. The
99 * selection is implicitly used with future AP transactions.
100 * This is a NOP if the specified AP is already selected.
101 *
102 * @param dap The DAP
103 * @param apsel Number of the AP to (implicitly) use with further
104 * transactions. This normally identifies a MEM-AP.
105 */
106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
107 {
108 uint32_t new_ap = (ap << 24) & 0xFF000000;
109
110 if (new_ap != dap->ap_current) {
111 dap->ap_current = new_ap;
112 /* Switching AP invalidates cached values.
113 * Values MUST BE UPDATED BEFORE AP ACCESS.
114 */
115 dap->ap_bank_value = -1;
116 dap->ap_csw_value = -1;
117 dap->ap_tar_value = -1;
118 }
119 }
120
121 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
122 {
123 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
124 dap->apcsw[dap->ap_current >> 24];
125
126 if (csw != dap->ap_csw_value) {
127 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
128 int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
129 if (retval != ERROR_OK)
130 return retval;
131 dap->ap_csw_value = csw;
132 }
133 return ERROR_OK;
134 }
135
136 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
137 {
138 if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
139 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
140 int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
141 if (retval != ERROR_OK)
142 return retval;
143 dap->ap_tar_value = tar;
144 }
145 return ERROR_OK;
146 }
147
148 /**
149 * Queue transactions setting up transfer parameters for the
150 * currently selected MEM-AP.
151 *
152 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
153 * initiate data reads or writes using memory or peripheral addresses.
154 * If the CSW is configured for it, the TAR may be automatically
155 * incremented after each transfer.
156 *
157 * @todo Rename to reflect it being specifically a MEM-AP function.
158 *
159 * @param dap The DAP connected to the MEM-AP.
160 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
161 * matches the cached value, the register is not changed.
162 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
163 * matches the cached address, the register is not changed.
164 *
165 * @return ERROR_OK if the transaction was properly queued, else a fault code.
166 */
167 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
168 {
169 int retval;
170 retval = dap_setup_accessport_csw(dap, csw);
171 if (retval != ERROR_OK)
172 return retval;
173 retval = dap_setup_accessport_tar(dap, tar);
174 if (retval != ERROR_OK)
175 return retval;
176 return ERROR_OK;
177 }
178
179 /**
180 * Asynchronous (queued) read of a word from memory or a system register.
181 *
182 * @param dap The DAP connected to the MEM-AP performing the read.
183 * @param address Address of the 32-bit word to read; it must be
184 * readable by the currently selected MEM-AP.
185 * @param value points to where the word will be stored when the
186 * transaction queue is flushed (assuming no errors).
187 *
188 * @return ERROR_OK for success. Otherwise a fault code.
189 */
190 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
191 uint32_t *value)
192 {
193 int retval;
194
195 /* Use banked addressing (REG_BDx) to avoid some link traffic
196 * (updating TAR) when reading several consecutive addresses.
197 */
198 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
199 address & 0xFFFFFFF0);
200 if (retval != ERROR_OK)
201 return retval;
202
203 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
204 }
205
206 /**
207 * Synchronous read of a word from memory or a system register.
208 * As a side effect, this flushes any queued transactions.
209 *
210 * @param dap The DAP connected to the MEM-AP performing the read.
211 * @param address Address of the 32-bit word to read; it must be
212 * readable by the currently selected MEM-AP.
213 * @param value points to where the result will be stored.
214 *
215 * @return ERROR_OK for success; *value holds the result.
216 * Otherwise a fault code.
217 */
218 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
219 uint32_t *value)
220 {
221 int retval;
222
223 retval = mem_ap_read_u32(dap, address, value);
224 if (retval != ERROR_OK)
225 return retval;
226
227 return dap_run(dap);
228 }
229
230 /**
231 * Asynchronous (queued) write of a word to memory or a system register.
232 *
233 * @param dap The DAP connected to the MEM-AP.
234 * @param address Address to be written; it must be writable by
235 * the currently selected MEM-AP.
236 * @param value Word that will be written to the address when transaction
237 * queue is flushed (assuming no errors).
238 *
239 * @return ERROR_OK for success. Otherwise a fault code.
240 */
241 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
242 uint32_t value)
243 {
244 int retval;
245
246 /* Use banked addressing (REG_BDx) to avoid some link traffic
247 * (updating TAR) when writing several consecutive addresses.
248 */
249 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
250 address & 0xFFFFFFF0);
251 if (retval != ERROR_OK)
252 return retval;
253
254 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
255 value);
256 }
257
258 /**
259 * Synchronous write of a word to memory or a system register.
260 * As a side effect, this flushes any queued transactions.
261 *
262 * @param dap The DAP connected to the MEM-AP.
263 * @param address Address to be written; it must be writable by
264 * the currently selected MEM-AP.
265 * @param value Word that will be written.
266 *
267 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
268 */
269 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
270 uint32_t value)
271 {
272 int retval = mem_ap_write_u32(dap, address, value);
273
274 if (retval != ERROR_OK)
275 return retval;
276
277 return dap_run(dap);
278 }
279
280 /**
281 * Synchronous write of a block of memory, using a specific access size.
282 *
283 * @param dap The DAP connected to the MEM-AP.
284 * @param buffer The data buffer to write. No particular alignment is assumed.
285 * @param size Which access size to use, in bytes. 1, 2 or 4.
286 * @param count The number of writes to do (in size units, not bytes).
287 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
288 * @param addrinc Whether the target address should be increased for each write or not. This
289 * should normally be true, except when writing to e.g. a FIFO.
290 * @return ERROR_OK on success, otherwise an error code.
291 */
292 int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
293 uint32_t address, bool addrinc)
294 {
295 size_t nbytes = size * count;
296 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
297 uint32_t csw_size;
298 int retval;
299
300 if (size == 4)
301 csw_size = CSW_32BIT;
302 else if (size == 2)
303 csw_size = CSW_16BIT;
304 else if (size == 1)
305 csw_size = CSW_8BIT;
306 else
307 return ERROR_TARGET_UNALIGNED_ACCESS;
308
309 retval = dap_setup_accessport_tar(dap, address);
310 if (retval != ERROR_OK)
311 return retval;
312
313 while (nbytes > 0) {
314 uint32_t this_size = size;
315
316 /* Select packed transfer if possible */
317 if (addrinc && dap->packed_transfers && nbytes >= 4
318 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
319 this_size = 4;
320 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
321 } else {
322 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
323 }
324
325 if (retval != ERROR_OK)
326 break;
327
328 /* How many source bytes each transfer will consume, and their location in the DRW,
329 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
330 uint32_t outvalue = 0;
331 switch (this_size) {
332 case 4:
333 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
334 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
335 case 2:
336 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
337 case 1:
338 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
339 }
340
341 nbytes -= this_size;
342
343 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
344 if (retval != ERROR_OK)
345 break;
346
347 /* Rewrite TAR if it wrapped */
348 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
349 retval = dap_setup_accessport_tar(dap, address);
350 if (retval != ERROR_OK)
351 break;
352 }
353 }
354
355 /* REVISIT: Might want to have a queued version of this function that does not run. */
356 if (retval == ERROR_OK)
357 retval = dap_run(dap);
358
359 if (retval != ERROR_OK) {
360 uint32_t tar;
361 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
362 && dap_run(dap) == ERROR_OK)
363 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
364 else
365 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
366 }
367
368 return retval;
369 }
370
371 /**
372 * Synchronous read of a block of memory, using a specific access size.
373 *
374 * @param dap The DAP connected to the MEM-AP.
375 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
376 * @param size Which access size to use, in bytes. 1, 2 or 4.
377 * @param count The number of reads to do (in size units, not bytes).
378 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
379 * @param addrinc Whether the target address should be increased after each read or not. This
380 * should normally be true, except when reading from e.g. a FIFO.
381 * @return ERROR_OK on success, otherwise an error code.
382 */
383 int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
384 uint32_t adr, bool addrinc)
385 {
386 size_t nbytes = size * count;
387 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
388 uint32_t csw_size;
389 uint32_t address = adr;
390 int retval;
391
392 if (size == 4)
393 csw_size = CSW_32BIT;
394 else if (size == 2)
395 csw_size = CSW_16BIT;
396 else if (size == 1)
397 csw_size = CSW_8BIT;
398 else
399 return ERROR_TARGET_UNALIGNED_ACCESS;
400
401 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
402 * over-allocation if packed transfers are going to be used, but determining the real need at
403 * this point would be messy. */
404 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
405 uint32_t *read_ptr = read_buf;
406 if (read_buf == NULL) {
407 LOG_ERROR("Failed to allocate read buffer");
408 return ERROR_FAIL;
409 }
410
411 retval = dap_setup_accessport_tar(dap, address);
412 if (retval != ERROR_OK)
413 return retval;
414
415 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
416 * useful bytes it contains, and their location in the word, depends on the type of transfer
417 * and alignment. */
418 while (nbytes > 0) {
419 uint32_t this_size = size;
420
421 /* Select packed transfer if possible */
422 if (addrinc && dap->packed_transfers && nbytes >= 4
423 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
424 this_size = 4;
425 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
426 } else {
427 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
428 }
429 if (retval != ERROR_OK)
430 break;
431
432 retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++);
433 if (retval != ERROR_OK)
434 break;
435
436 nbytes -= this_size;
437 address += this_size;
438
439 /* Rewrite TAR if it wrapped */
440 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
441 retval = dap_setup_accessport_tar(dap, address);
442 if (retval != ERROR_OK)
443 break;
444 }
445 }
446
447 if (retval == ERROR_OK)
448 retval = dap_run(dap);
449
450 /* Restore state */
451 address = adr;
452 nbytes = size * count;
453 read_ptr = read_buf;
454
455 /* If something failed, read TAR to find out how much data was successfully read, so we can
456 * at least give the caller what we have. */
457 if (retval != ERROR_OK) {
458 uint32_t tar;
459 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
460 && dap_run(dap) == ERROR_OK) {
461 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
462 if (nbytes > tar - address)
463 nbytes = tar - address;
464 } else {
465 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
466 nbytes = 0;
467 }
468 }
469
470 /* Replay loop to populate caller's buffer from the correct word and byte lane */
471 while (nbytes > 0) {
472 uint32_t this_size = size;
473
474 if (addrinc && dap->packed_transfers && nbytes >= 4
475 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
476 this_size = 4;
477 }
478
479 switch (this_size) {
480 case 4:
481 *buffer++ = *read_ptr >> 8 * (address++ & 3);
482 *buffer++ = *read_ptr >> 8 * (address++ & 3);
483 case 2:
484 *buffer++ = *read_ptr >> 8 * (address++ & 3);
485 case 1:
486 *buffer++ = *read_ptr >> 8 * (address++ & 3);
487 }
488
489 read_ptr++;
490 nbytes -= this_size;
491 }
492
493 free(read_buf);
494 return retval;
495 }
496
497 /*--------------------------------------------------------------------*/
498 /* Wrapping function with selection of AP */
499 /*--------------------------------------------------------------------*/
500 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
501 uint32_t address, uint32_t *value)
502 {
503 dap_ap_select(swjdp, ap);
504 return mem_ap_read_u32(swjdp, address, value);
505 }
506
507 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
508 uint32_t address, uint32_t value)
509 {
510 dap_ap_select(swjdp, ap);
511 return mem_ap_write_u32(swjdp, address, value);
512 }
513
514 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
515 uint32_t address, uint32_t *value)
516 {
517 dap_ap_select(swjdp, ap);
518 return mem_ap_read_atomic_u32(swjdp, address, value);
519 }
520
521 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
522 uint32_t address, uint32_t value)
523 {
524 dap_ap_select(swjdp, ap);
525 return mem_ap_write_atomic_u32(swjdp, address, value);
526 }
527
528 int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
529 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
530 {
531 dap_ap_select(swjdp, ap);
532 return mem_ap_read(swjdp, buffer, size, count, address, true);
533 }
534
535 int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
536 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
537 {
538 dap_ap_select(swjdp, ap);
539 return mem_ap_write(swjdp, buffer, size, count, address, true);
540 }
541
542 int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
543 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
544 {
545 dap_ap_select(swjdp, ap);
546 return mem_ap_read(swjdp, buffer, size, count, address, false);
547 }
548
549 int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
550 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
551 {
552 dap_ap_select(swjdp, ap);
553 return mem_ap_write(swjdp, buffer, size, count, address, false);
554 }
555
556 #define MDM_REG_STAT 0x00
557 #define MDM_REG_CTRL 0x04
558 #define MDM_REG_ID 0xfc
559
560 #define MDM_STAT_FMEACK (1<<0)
561 #define MDM_STAT_FREADY (1<<1)
562 #define MDM_STAT_SYSSEC (1<<2)
563 #define MDM_STAT_SYSRES (1<<3)
564 #define MDM_STAT_FMEEN (1<<5)
565 #define MDM_STAT_BACKDOOREN (1<<6)
566 #define MDM_STAT_LPEN (1<<7)
567 #define MDM_STAT_VLPEN (1<<8)
568 #define MDM_STAT_LLSMODEXIT (1<<9)
569 #define MDM_STAT_VLLSXMODEXIT (1<<10)
570 #define MDM_STAT_CORE_HALTED (1<<16)
571 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
572 #define MDM_STAT_CORESLEEPING (1<<18)
573
574 #define MEM_CTRL_FMEIP (1<<0)
575 #define MEM_CTRL_DBG_DIS (1<<1)
576 #define MEM_CTRL_DBG_REQ (1<<2)
577 #define MEM_CTRL_SYS_RES_REQ (1<<3)
578 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
579 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
580 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
581 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
582
583 #define MDM_ACCESS_TIMEOUT 3000 /* ms */
584
585 /**
586 *
587 */
588 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
589 {
590 uint32_t val;
591 int retval;
592 int timeout = 0;
593 enum reset_types jtag_reset_config = jtag_get_reset_config();
594
595 dap_ap_select(dap, 1);
596
597 /* first check mdm-ap id register */
598 retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
599 if (retval != ERROR_OK)
600 return retval;
601 dap_run(dap);
602
603 if (val != 0x001C0000) {
604 LOG_DEBUG("id doesn't match %08" PRIX32 " != 0x001C0000", val);
605 dap_ap_select(dap, 0);
606 return ERROR_FAIL;
607 }
608
609 /* read and parse status register
610 * it's important that the device is out of
611 * reset here
612 */
613 while (1) {
614 if (timeout++ > MDM_ACCESS_TIMEOUT) {
615 LOG_DEBUG("MDMAP : flash ready timeout");
616 return ERROR_FAIL;
617 }
618 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
619 if (retval != ERROR_OK)
620 return retval;
621 dap_run(dap);
622
623 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
624 if (val & MDM_STAT_FREADY)
625 break;
626 alive_sleep(1);
627 }
628
629 if ((val & MDM_STAT_SYSSEC)) {
630 LOG_DEBUG("MDMAP: system is secured, masserase needed");
631
632 if (!(val & MDM_STAT_FMEEN))
633 LOG_DEBUG("MDMAP: masserase is disabled");
634 else {
635 /* we need to assert reset */
636 if (jtag_reset_config & RESET_HAS_SRST) {
637 /* default to asserting srst */
638 adapter_assert_reset();
639 } else {
640 LOG_DEBUG("SRST not configured");
641 dap_ap_select(dap, 0);
642 return ERROR_FAIL;
643 }
644 timeout = 0;
645 while (1) {
646 if (timeout++ > MDM_ACCESS_TIMEOUT) {
647 LOG_DEBUG("MDMAP : flash ready timeout");
648 return ERROR_FAIL;
649 }
650 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
651 if (retval != ERROR_OK)
652 return retval;
653 dap_run(dap);
654 /* read status register and wait for ready */
655 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
656 if (retval != ERROR_OK)
657 return retval;
658 dap_run(dap);
659 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
660
661 if ((val & 1))
662 break;
663 alive_sleep(1);
664 }
665 timeout = 0;
666 while (1) {
667 if (timeout++ > MDM_ACCESS_TIMEOUT) {
668 LOG_DEBUG("MDMAP : flash ready timeout");
669 return ERROR_FAIL;
670 }
671 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
672 if (retval != ERROR_OK)
673 return retval;
674 dap_run(dap);
675 /* read status register */
676 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
677 if (retval != ERROR_OK)
678 return retval;
679 dap_run(dap);
680 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
681 /* read control register and wait for ready */
682 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
683 if (retval != ERROR_OK)
684 return retval;
685 dap_run(dap);
686 LOG_DEBUG("MDM_REG_CTRL %08" PRIX32, val);
687
688 if (val == 0x00)
689 break;
690 alive_sleep(1);
691 }
692 }
693 }
694
695 dap_ap_select(dap, 0);
696
697 return ERROR_OK;
698 }
699
700 /** */
701 struct dap_syssec_filter {
702 /** */
703 uint32_t idcode;
704 /** */
705 int (*dap_init)(struct adiv5_dap *dap);
706 };
707
708 /** */
709 static struct dap_syssec_filter dap_syssec_filter_data[] = {
710 { 0x4BA00477, dap_syssec_kinetis_mdmap }
711 };
712
713 /**
714 *
715 */
716 int dap_syssec(struct adiv5_dap *dap)
717 {
718 unsigned int i;
719 struct jtag_tap *tap;
720
721 for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
722 tap = dap->jtag_info->tap;
723
724 while (tap != NULL) {
725 if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
726 LOG_DEBUG("DAP: mdmap_init for idcode: %08" PRIx32, tap->idcode);
727 dap_syssec_filter_data[i].dap_init(dap);
728 }
729 tap = tap->next_tap;
730 }
731 }
732
733 return ERROR_OK;
734 }
735
736 /*--------------------------------------------------------------------------*/
737
738
739 /* FIXME don't import ... just initialize as
740 * part of DAP transport setup
741 */
742 extern const struct dap_ops jtag_dp_ops;
743
744 /*--------------------------------------------------------------------------*/
745
746 /**
747 * Initialize a DAP. This sets up the power domains, prepares the DP
748 * for further use, and arranges to use AP #0 for all AP operations
749 * until dap_ap-select() changes that policy.
750 *
751 * @param dap The DAP being initialized.
752 *
753 * @todo Rename this. We also need an initialization scheme which account
754 * for SWD transports not just JTAG; that will need to address differences
755 * in layering. (JTAG is useful without any debug target; but not SWD.)
756 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
757 */
758 int ahbap_debugport_init(struct adiv5_dap *dap)
759 {
760 uint32_t ctrlstat;
761 int cnt = 0;
762 int retval;
763
764 LOG_DEBUG(" ");
765
766 /* JTAG-DP or SWJ-DP, in JTAG mode
767 * ... for SWD mode this is patched as part
768 * of link switchover
769 */
770 if (!dap->ops)
771 dap->ops = &jtag_dp_ops;
772
773 /* Default MEM-AP setup.
774 *
775 * REVISIT AP #0 may be an inappropriate default for this.
776 * Should we probe, or take a hint from the caller?
777 * Presumably we can ignore the possibility of multiple APs.
778 */
779 dap->ap_current = !0;
780 dap_ap_select(dap, 0);
781
782 /* DP initialization */
783
784 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
785 if (retval != ERROR_OK)
786 return retval;
787
788 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
789 if (retval != ERROR_OK)
790 return retval;
791
792 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
793 if (retval != ERROR_OK)
794 return retval;
795
796 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
797 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
798 if (retval != ERROR_OK)
799 return retval;
800
801 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
802 if (retval != ERROR_OK)
803 return retval;
804 retval = dap_run(dap);
805 if (retval != ERROR_OK)
806 return retval;
807
808 /* Check that we have debug power domains activated */
809 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
810 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
811 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
812 if (retval != ERROR_OK)
813 return retval;
814 retval = dap_run(dap);
815 if (retval != ERROR_OK)
816 return retval;
817 alive_sleep(10);
818 }
819
820 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
821 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
822 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
823 if (retval != ERROR_OK)
824 return retval;
825 retval = dap_run(dap);
826 if (retval != ERROR_OK)
827 return retval;
828 alive_sleep(10);
829 }
830
831 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
832 if (retval != ERROR_OK)
833 return retval;
834 /* With debug power on we can activate OVERRUN checking */
835 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
836 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
837 if (retval != ERROR_OK)
838 return retval;
839 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
840 if (retval != ERROR_OK)
841 return retval;
842
843 dap_syssec(dap);
844
845 /* check that we support packed transfers */
846 uint32_t csw;
847
848 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
849 if (retval != ERROR_OK)
850 return retval;
851
852 retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
853 if (retval != ERROR_OK)
854 return retval;
855
856 retval = dap_run(dap);
857 if (retval != ERROR_OK)
858 return retval;
859
860 if (csw & CSW_ADDRINC_PACKED)
861 dap->packed_transfers = true;
862 else
863 dap->packed_transfers = false;
864
865 LOG_DEBUG("MEM_AP Packed Transfers: %s",
866 dap->packed_transfers ? "enabled" : "disabled");
867
868 return ERROR_OK;
869 }
870
871 /* CID interpretation -- see ARM IHI 0029B section 3
872 * and ARM IHI 0031A table 13-3.
873 */
874 static const char *class_description[16] = {
875 "Reserved", "ROM table", "Reserved", "Reserved",
876 "Reserved", "Reserved", "Reserved", "Reserved",
877 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
878 "Reserved", "OptimoDE DESS",
879 "Generic IP component", "PrimeCell or System component"
880 };
881
882 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
883 {
884 return cid3 == 0xb1 && cid2 == 0x05
885 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
886 }
887
888 /*
889 * This function checks the ID for each access port to find the requested Access Port type
890 */
891 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
892 {
893 int ap;
894
895 /* Maximum AP number is 255 since the SELECT register is 8 bits */
896 for (ap = 0; ap <= 255; ap++) {
897
898 /* read the IDR register of the Access Port */
899 uint32_t id_val = 0;
900 dap_ap_select(dap, ap);
901
902 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
903 if (retval != ERROR_OK)
904 return retval;
905
906 retval = dap_run(dap);
907
908 /* IDR bits:
909 * 31-28 : Revision
910 * 27-24 : JEDEC bank (0x4 for ARM)
911 * 23-17 : JEDEC code (0x3B for ARM)
912 * 16 : Mem-AP
913 * 15-8 : Reserved
914 * 7-0 : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
915 */
916
917 /* Reading register for a non-existant AP should not cause an error,
918 * but just to be sure, try to continue searching if an error does happen.
919 */
920 if ((retval == ERROR_OK) && /* Register read success */
921 ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
922 ((id_val & 0xFF) == type_to_find)) { /* type matches*/
923
924 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
925 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
926 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
927 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
928 ap, id_val);
929
930 *ap_num_out = ap;
931 return ERROR_OK;
932 }
933 }
934
935 LOG_DEBUG("No %s found",
936 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
937 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
938 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
939 return ERROR_FAIL;
940 }
941
942 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
943 uint32_t *out_dbgbase, uint32_t *out_apid)
944 {
945 uint32_t ap_old;
946 int retval;
947 uint32_t dbgbase, apid;
948
949 /* AP address is in bits 31:24 of DP_SELECT */
950 if (ap >= 256)
951 return ERROR_COMMAND_SYNTAX_ERROR;
952
953 ap_old = dap->ap_current;
954 dap_ap_select(dap, ap);
955
956 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
957 if (retval != ERROR_OK)
958 return retval;
959 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
960 if (retval != ERROR_OK)
961 return retval;
962 retval = dap_run(dap);
963 if (retval != ERROR_OK)
964 return retval;
965
966 /* Excavate the device ID code */
967 struct jtag_tap *tap = dap->jtag_info->tap;
968 while (tap != NULL) {
969 if (tap->hasidcode)
970 break;
971 tap = tap->next_tap;
972 }
973 if (tap == NULL || !tap->hasidcode)
974 return ERROR_OK;
975
976 dap_ap_select(dap, ap_old);
977
978 /* The asignment happens only here to prevent modification of these
979 * values before they are certain. */
980 *out_dbgbase = dbgbase;
981 *out_apid = apid;
982
983 return ERROR_OK;
984 }
985
986 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
987 uint32_t dbgbase, uint8_t type, uint32_t *addr)
988 {
989 uint32_t ap_old;
990 uint32_t romentry, entry_offset = 0, component_base, devtype;
991 int retval = ERROR_FAIL;
992
993 if (ap >= 256)
994 return ERROR_COMMAND_SYNTAX_ERROR;
995
996 ap_old = dap->ap_current;
997 dap_ap_select(dap, ap);
998
999 do {
1000 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1001 entry_offset, &romentry);
1002 if (retval != ERROR_OK)
1003 return retval;
1004
1005 component_base = (dbgbase & 0xFFFFF000)
1006 + (romentry & 0xFFFFF000);
1007
1008 if (romentry & 0x1) {
1009 retval = mem_ap_read_atomic_u32(dap,
1010 (component_base & 0xfffff000) | 0xfcc,
1011 &devtype);
1012 if (retval != ERROR_OK)
1013 return retval;
1014 if ((devtype & 0xff) == type) {
1015 *addr = component_base;
1016 retval = ERROR_OK;
1017 break;
1018 }
1019 }
1020 entry_offset += 4;
1021 } while (romentry > 0);
1022
1023 dap_ap_select(dap, ap_old);
1024
1025 return retval;
1026 }
1027
1028 static int dap_info_command(struct command_context *cmd_ctx,
1029 struct adiv5_dap *dap, int ap)
1030 {
1031 int retval;
1032 uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1033 int romtable_present = 0;
1034 uint8_t mem_ap;
1035 uint32_t ap_old;
1036
1037 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1038 if (retval != ERROR_OK)
1039 return retval;
1040
1041 ap_old = dap->ap_current;
1042 dap_ap_select(dap, ap);
1043
1044 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1045 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1046 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1047 if (apid) {
1048 switch (apid&0x0F) {
1049 case 0:
1050 command_print(cmd_ctx, "\tType is JTAG-AP");
1051 break;
1052 case 1:
1053 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1054 break;
1055 case 2:
1056 command_print(cmd_ctx, "\tType is MEM-AP APB");
1057 break;
1058 default:
1059 command_print(cmd_ctx, "\tUnknown AP type");
1060 break;
1061 }
1062
1063 /* NOTE: a MEM-AP may have a single CoreSight component that's
1064 * not a ROM table ... or have no such components at all.
1065 */
1066 if (mem_ap)
1067 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1068 } else
1069 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1070
1071 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1072 if (romtable_present) {
1073 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1074 uint16_t entry_offset;
1075
1076 /* bit 16 of apid indicates a memory access port */
1077 if (dbgbase & 0x02)
1078 command_print(cmd_ctx, "\tValid ROM table present");
1079 else
1080 command_print(cmd_ctx, "\tROM table in legacy format");
1081
1082 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1083 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1084 if (retval != ERROR_OK)
1085 return retval;
1086 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1087 if (retval != ERROR_OK)
1088 return retval;
1089 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1090 if (retval != ERROR_OK)
1091 return retval;
1092 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1093 if (retval != ERROR_OK)
1094 return retval;
1095 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1096 if (retval != ERROR_OK)
1097 return retval;
1098 retval = dap_run(dap);
1099 if (retval != ERROR_OK)
1100 return retval;
1101
1102 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1103 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1104 ", CID2 0x%2.2x"
1105 ", CID1 0x%2.2x"
1106 ", CID0 0x%2.2x",
1107 (unsigned) cid3, (unsigned)cid2,
1108 (unsigned) cid1, (unsigned) cid0);
1109 if (memtype & 0x01)
1110 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1111 else
1112 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1113 "Dedicated debug bus.");
1114
1115 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1116 entry_offset = 0;
1117 do {
1118 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1119 if (retval != ERROR_OK)
1120 return retval;
1121 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry);
1122 if (romentry & 0x01) {
1123 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1124 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1125 uint32_t component_base;
1126 unsigned part_num;
1127 char *type, *full;
1128
1129 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1130
1131 /* IDs are in last 4K section */
1132 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1133 if (retval != ERROR_OK)
1134 return retval;
1135 c_pid0 &= 0xff;
1136 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1137 if (retval != ERROR_OK)
1138 return retval;
1139 c_pid1 &= 0xff;
1140 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1141 if (retval != ERROR_OK)
1142 return retval;
1143 c_pid2 &= 0xff;
1144 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1145 if (retval != ERROR_OK)
1146 return retval;
1147 c_pid3 &= 0xff;
1148 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1149 if (retval != ERROR_OK)
1150 return retval;
1151 c_pid4 &= 0xff;
1152
1153 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1154 if (retval != ERROR_OK)
1155 return retval;
1156 c_cid0 &= 0xff;
1157 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1158 if (retval != ERROR_OK)
1159 return retval;
1160 c_cid1 &= 0xff;
1161 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1162 if (retval != ERROR_OK)
1163 return retval;
1164 c_cid2 &= 0xff;
1165 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1166 if (retval != ERROR_OK)
1167 return retval;
1168 c_cid3 &= 0xff;
1169
1170 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ","
1171 "start address 0x%" PRIx32, component_base,
1172 /* component may take multiple 4K pages */
1173 component_base - 0x1000*(c_pid4 >> 4));
1174 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1175 (int) (c_cid1 >> 4) & 0xf,
1176 /* See ARM IHI 0029B Table 3-3 */
1177 class_description[(c_cid1 >> 4) & 0xf]);
1178
1179 /* CoreSight component? */
1180 if (((c_cid1 >> 4) & 0x0f) == 9) {
1181 uint32_t devtype;
1182 unsigned minor;
1183 char *major = "Reserved", *subtype = "Reserved";
1184
1185 retval = mem_ap_read_atomic_u32(dap,
1186 (component_base & 0xfffff000) | 0xfcc,
1187 &devtype);
1188 if (retval != ERROR_OK)
1189 return retval;
1190 minor = (devtype >> 4) & 0x0f;
1191 switch (devtype & 0x0f) {
1192 case 0:
1193 major = "Miscellaneous";
1194 switch (minor) {
1195 case 0:
1196 subtype = "other";
1197 break;
1198 case 4:
1199 subtype = "Validation component";
1200 break;
1201 }
1202 break;
1203 case 1:
1204 major = "Trace Sink";
1205 switch (minor) {
1206 case 0:
1207 subtype = "other";
1208 break;
1209 case 1:
1210 subtype = "Port";
1211 break;
1212 case 2:
1213 subtype = "Buffer";
1214 break;
1215 }
1216 break;
1217 case 2:
1218 major = "Trace Link";
1219 switch (minor) {
1220 case 0:
1221 subtype = "other";
1222 break;
1223 case 1:
1224 subtype = "Funnel, router";
1225 break;
1226 case 2:
1227 subtype = "Filter";
1228 break;
1229 case 3:
1230 subtype = "FIFO, buffer";
1231 break;
1232 }
1233 break;
1234 case 3:
1235 major = "Trace Source";
1236 switch (minor) {
1237 case 0:
1238 subtype = "other";
1239 break;
1240 case 1:
1241 subtype = "Processor";
1242 break;
1243 case 2:
1244 subtype = "DSP";
1245 break;
1246 case 3:
1247 subtype = "Engine/Coprocessor";
1248 break;
1249 case 4:
1250 subtype = "Bus";
1251 break;
1252 }
1253 break;
1254 case 4:
1255 major = "Debug Control";
1256 switch (minor) {
1257 case 0:
1258 subtype = "other";
1259 break;
1260 case 1:
1261 subtype = "Trigger Matrix";
1262 break;
1263 case 2:
1264 subtype = "Debug Auth";
1265 break;
1266 }
1267 break;
1268 case 5:
1269 major = "Debug Logic";
1270 switch (minor) {
1271 case 0:
1272 subtype = "other";
1273 break;
1274 case 1:
1275 subtype = "Processor";
1276 break;
1277 case 2:
1278 subtype = "DSP";
1279 break;
1280 case 3:
1281 subtype = "Engine/Coprocessor";
1282 break;
1283 }
1284 break;
1285 }
1286 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1287 (unsigned) (devtype & 0xff),
1288 major, subtype);
1289 /* REVISIT also show 0xfc8 DevId */
1290 }
1291
1292 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1293 command_print(cmd_ctx,
1294 "\t\tCID3 0%2.2x"
1295 ", CID2 0%2.2x"
1296 ", CID1 0%2.2x"
1297 ", CID0 0%2.2x",
1298 (int) c_cid3,
1299 (int) c_cid2,
1300 (int)c_cid1,
1301 (int)c_cid0);
1302 command_print(cmd_ctx,
1303 "\t\tPeripheral ID[4..0] = hex "
1304 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1305 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1306 (int) c_pid1, (int) c_pid0);
1307
1308 /* Part number interpretations are from Cortex
1309 * core specs, the CoreSight components TRM
1310 * (ARM DDI 0314H), CoreSight System Design
1311 * Guide (ARM DGI 0012D) and ETM specs; also
1312 * from chip observation (e.g. TI SDTI).
1313 */
1314 part_num = (c_pid0 & 0xff);
1315 part_num |= (c_pid1 & 0x0f) << 8;
1316 switch (part_num) {
1317 case 0x000:
1318 type = "Cortex-M3 NVIC";
1319 full = "(Interrupt Controller)";
1320 break;
1321 case 0x001:
1322 type = "Cortex-M3 ITM";
1323 full = "(Instrumentation Trace Module)";
1324 break;
1325 case 0x002:
1326 type = "Cortex-M3 DWT";
1327 full = "(Data Watchpoint and Trace)";
1328 break;
1329 case 0x003:
1330 type = "Cortex-M3 FBP";
1331 full = "(Flash Patch and Breakpoint)";
1332 break;
1333 case 0x00c:
1334 type = "Cortex-M4 SCS";
1335 full = "(System Control Space)";
1336 break;
1337 case 0x00d:
1338 type = "CoreSight ETM11";
1339 full = "(Embedded Trace)";
1340 break;
1341 /* case 0x113: what? */
1342 case 0x120: /* from OMAP3 memmap */
1343 type = "TI SDTI";
1344 full = "(System Debug Trace Interface)";
1345 break;
1346 case 0x343: /* from OMAP3 memmap */
1347 type = "TI DAPCTL";
1348 full = "";
1349 break;
1350 case 0x906:
1351 type = "Coresight CTI";
1352 full = "(Cross Trigger)";
1353 break;
1354 case 0x907:
1355 type = "Coresight ETB";
1356 full = "(Trace Buffer)";
1357 break;
1358 case 0x908:
1359 type = "Coresight CSTF";
1360 full = "(Trace Funnel)";
1361 break;
1362 case 0x910:
1363 type = "CoreSight ETM9";
1364 full = "(Embedded Trace)";
1365 break;
1366 case 0x912:
1367 type = "Coresight TPIU";
1368 full = "(Trace Port Interface Unit)";
1369 break;
1370 case 0x921:
1371 type = "Cortex-A8 ETM";
1372 full = "(Embedded Trace)";
1373 break;
1374 case 0x922:
1375 type = "Cortex-A8 CTI";
1376 full = "(Cross Trigger)";
1377 break;
1378 case 0x923:
1379 type = "Cortex-M3 TPIU";
1380 full = "(Trace Port Interface Unit)";
1381 break;
1382 case 0x924:
1383 type = "Cortex-M3 ETM";
1384 full = "(Embedded Trace)";
1385 break;
1386 case 0x925:
1387 type = "Cortex-M4 ETM";
1388 full = "(Embedded Trace)";
1389 break;
1390 case 0x930:
1391 type = "Cortex-R4 ETM";
1392 full = "(Embedded Trace)";
1393 break;
1394 case 0x9a1:
1395 type = "Cortex-M4 TPUI";
1396 full = "(Trace Port Interface Unit)";
1397 break;
1398 case 0xc08:
1399 type = "Cortex-A8 Debug";
1400 full = "(Debug Unit)";
1401 break;
1402 default:
1403 type = "-*- unrecognized -*-";
1404 full = "";
1405 break;
1406 }
1407 command_print(cmd_ctx, "\t\tPart is %s %s",
1408 type, full);
1409 } else {
1410 if (romentry)
1411 command_print(cmd_ctx, "\t\tComponent not present");
1412 else
1413 command_print(cmd_ctx, "\t\tEnd of ROM table");
1414 }
1415 entry_offset += 4;
1416 } while (romentry > 0);
1417 } else
1418 command_print(cmd_ctx, "\tNo ROM table present");
1419 dap_ap_select(dap, ap_old);
1420
1421 return ERROR_OK;
1422 }
1423
1424 COMMAND_HANDLER(handle_dap_info_command)
1425 {
1426 struct target *target = get_current_target(CMD_CTX);
1427 struct arm *arm = target_to_arm(target);
1428 struct adiv5_dap *dap = arm->dap;
1429 uint32_t apsel;
1430
1431 switch (CMD_ARGC) {
1432 case 0:
1433 apsel = dap->apsel;
1434 break;
1435 case 1:
1436 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1437 break;
1438 default:
1439 return ERROR_COMMAND_SYNTAX_ERROR;
1440 }
1441
1442 return dap_info_command(CMD_CTX, dap, apsel);
1443 }
1444
1445 COMMAND_HANDLER(dap_baseaddr_command)
1446 {
1447 struct target *target = get_current_target(CMD_CTX);
1448 struct arm *arm = target_to_arm(target);
1449 struct adiv5_dap *dap = arm->dap;
1450
1451 uint32_t apsel, baseaddr;
1452 int retval;
1453
1454 switch (CMD_ARGC) {
1455 case 0:
1456 apsel = dap->apsel;
1457 break;
1458 case 1:
1459 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1460 /* AP address is in bits 31:24 of DP_SELECT */
1461 if (apsel >= 256)
1462 return ERROR_COMMAND_SYNTAX_ERROR;
1463 break;
1464 default:
1465 return ERROR_COMMAND_SYNTAX_ERROR;
1466 }
1467
1468 dap_ap_select(dap, apsel);
1469
1470 /* NOTE: assumes we're talking to a MEM-AP, which
1471 * has a base address. There are other kinds of AP,
1472 * though they're not common for now. This should
1473 * use the ID register to verify it's a MEM-AP.
1474 */
1475 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1476 if (retval != ERROR_OK)
1477 return retval;
1478 retval = dap_run(dap);
1479 if (retval != ERROR_OK)
1480 return retval;
1481
1482 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1483
1484 return retval;
1485 }
1486
1487 COMMAND_HANDLER(dap_memaccess_command)
1488 {
1489 struct target *target = get_current_target(CMD_CTX);
1490 struct arm *arm = target_to_arm(target);
1491 struct adiv5_dap *dap = arm->dap;
1492
1493 uint32_t memaccess_tck;
1494
1495 switch (CMD_ARGC) {
1496 case 0:
1497 memaccess_tck = dap->memaccess_tck;
1498 break;
1499 case 1:
1500 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1501 break;
1502 default:
1503 return ERROR_COMMAND_SYNTAX_ERROR;
1504 }
1505 dap->memaccess_tck = memaccess_tck;
1506
1507 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1508 dap->memaccess_tck);
1509
1510 return ERROR_OK;
1511 }
1512
1513 COMMAND_HANDLER(dap_apsel_command)
1514 {
1515 struct target *target = get_current_target(CMD_CTX);
1516 struct arm *arm = target_to_arm(target);
1517 struct adiv5_dap *dap = arm->dap;
1518
1519 uint32_t apsel, apid;
1520 int retval;
1521
1522 switch (CMD_ARGC) {
1523 case 0:
1524 apsel = 0;
1525 break;
1526 case 1:
1527 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1528 /* AP address is in bits 31:24 of DP_SELECT */
1529 if (apsel >= 256)
1530 return ERROR_COMMAND_SYNTAX_ERROR;
1531 break;
1532 default:
1533 return ERROR_COMMAND_SYNTAX_ERROR;
1534 }
1535
1536 dap->apsel = apsel;
1537 dap_ap_select(dap, apsel);
1538
1539 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1540 if (retval != ERROR_OK)
1541 return retval;
1542 retval = dap_run(dap);
1543 if (retval != ERROR_OK)
1544 return retval;
1545
1546 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1547 apsel, apid);
1548
1549 return retval;
1550 }
1551
1552 COMMAND_HANDLER(dap_apcsw_command)
1553 {
1554 struct target *target = get_current_target(CMD_CTX);
1555 struct arm *arm = target_to_arm(target);
1556 struct adiv5_dap *dap = arm->dap;
1557
1558 uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
1559
1560 switch (CMD_ARGC) {
1561 case 0:
1562 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1563 (dap->apsel), apcsw);
1564 break;
1565 case 1:
1566 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1567 /* AP address is in bits 31:24 of DP_SELECT */
1568 if (sprot > 1)
1569 return ERROR_COMMAND_SYNTAX_ERROR;
1570 if (sprot)
1571 apcsw |= CSW_SPROT;
1572 else
1573 apcsw &= ~CSW_SPROT;
1574 break;
1575 default:
1576 return ERROR_COMMAND_SYNTAX_ERROR;
1577 }
1578 dap->apcsw[dap->apsel] = apcsw;
1579
1580 return 0;
1581 }
1582
1583
1584
1585 COMMAND_HANDLER(dap_apid_command)
1586 {
1587 struct target *target = get_current_target(CMD_CTX);
1588 struct arm *arm = target_to_arm(target);
1589 struct adiv5_dap *dap = arm->dap;
1590
1591 uint32_t apsel, apid;
1592 int retval;
1593
1594 switch (CMD_ARGC) {
1595 case 0:
1596 apsel = dap->apsel;
1597 break;
1598 case 1:
1599 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1600 /* AP address is in bits 31:24 of DP_SELECT */
1601 if (apsel >= 256)
1602 return ERROR_COMMAND_SYNTAX_ERROR;
1603 break;
1604 default:
1605 return ERROR_COMMAND_SYNTAX_ERROR;
1606 }
1607
1608 dap_ap_select(dap, apsel);
1609
1610 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1611 if (retval != ERROR_OK)
1612 return retval;
1613 retval = dap_run(dap);
1614 if (retval != ERROR_OK)
1615 return retval;
1616
1617 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1618
1619 return retval;
1620 }
1621
1622 static const struct command_registration dap_commands[] = {
1623 {
1624 .name = "info",
1625 .handler = handle_dap_info_command,
1626 .mode = COMMAND_EXEC,
1627 .help = "display ROM table for MEM-AP "
1628 "(default currently selected AP)",
1629 .usage = "[ap_num]",
1630 },
1631 {
1632 .name = "apsel",
1633 .handler = dap_apsel_command,
1634 .mode = COMMAND_EXEC,
1635 .help = "Set the currently selected AP (default 0) "
1636 "and display the result",
1637 .usage = "[ap_num]",
1638 },
1639 {
1640 .name = "apcsw",
1641 .handler = dap_apcsw_command,
1642 .mode = COMMAND_EXEC,
1643 .help = "Set csw access bit ",
1644 .usage = "[sprot]",
1645 },
1646
1647 {
1648 .name = "apid",
1649 .handler = dap_apid_command,
1650 .mode = COMMAND_EXEC,
1651 .help = "return ID register from AP "
1652 "(default currently selected AP)",
1653 .usage = "[ap_num]",
1654 },
1655 {
1656 .name = "baseaddr",
1657 .handler = dap_baseaddr_command,
1658 .mode = COMMAND_EXEC,
1659 .help = "return debug base address from MEM-AP "
1660 "(default currently selected AP)",
1661 .usage = "[ap_num]",
1662 },
1663 {
1664 .name = "memaccess",
1665 .handler = dap_memaccess_command,
1666 .mode = COMMAND_EXEC,
1667 .help = "set/get number of extra tck for MEM-AP memory "
1668 "bus access [0-255]",
1669 .usage = "[cycles]",
1670 },
1671 COMMAND_REGISTRATION_DONE
1672 };
1673
1674 const struct command_registration dap_command_handlers[] = {
1675 {
1676 .name = "dap",
1677 .mode = COMMAND_EXEC,
1678 .help = "DAP command group",
1679 .usage = "",
1680 .chain = dap_commands,
1681 },
1682 COMMAND_REGISTRATION_DONE
1683 };
Official OpenOCD Mirror