1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 @title Open On-Chip Debugger (openocd)
15 @subtitle Edition @value{EDITION} for openocd version @value{VERSION}
16 @subtitle @value{UPDATED}
18 @vskip 0pt plus 1filll
23 @node Top, About, , (dir)
26 This is edition @value{EDITION} of the openocd manual for version
27 @value{VERSION}, @value{UPDATED}
30 * About:: About Openocd.
32 * Building:: Building Openocd
33 * Running:: Running Openocd
34 * Configuration:: Openocd Configuration.
35 * Commands:: Openocd Commands
36 * Sample Scripts:: Sample Target Scripts
37 * GDB and Openocd:: Using GDB and Openocd
38 * FAQ:: Frequently Asked Questions
39 * License:: GNU Free Documentation License
47 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
48 and boundary-scan testing for embedded target devices. The targets are interfaced
49 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
50 connection types in the future.
52 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
53 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
54 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
55 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
57 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
58 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
59 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
65 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
66 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
67 Others interested in improving the state of free and open debug and testing technology
68 are welcome to participate.
70 Other developers have contributed support for additional targets and flashes as well
71 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
75 @cindex building openocd
77 You can download the current SVN version with SVN client of your choice from the
78 following repositories:
80 (@uref{svn://svn.berlios.de/openocd/trunk})
84 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
86 Using the SVN command line client, you could use the following command to fetch the
87 latest version (make sure there is no (non-svn) directory called "openocd" in the
91 svn checkout svn://svn.berlios.de/openocd/trunk
94 Building the OpenOCD requires a recent version of the GNU autotools.
95 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
96 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
97 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
98 paths, resulting in obscure dependency errors (This is an observation I've gathered
99 from the logs of one user - correct me if I'm wrong).
101 You further need the appropriate driver files, if you want to build support for
102 a FTDI FT2232 based interface:
104 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
105 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
106 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
107 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
110 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
111 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
113 In general, the D2XX driver provides superior performance (several times as fast),
114 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
115 a kernel module, only a user space library.
117 To build OpenOCD (on both Linux and Cygwin), use the following commands:
121 Bootstrap generates the configure script, and prepares building on your system.
125 Configure generates the Makefiles used to build OpenOCD
129 Make builds the OpenOCD, and places the final executable in ./src/
131 The configure script takes several options, specifying which JTAG interfaces
138 --enable-parport_ppdev
140 --enable-amtjtagaccel
142 --enable-ft2232_ftd2xx
143 @footnote{Using the latest D2XX drivers from FTDI and following their installation
144 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
147 --enable-ft2232_libftdi
149 --with-ftd2xx=/path/to/d2xx/
152 If you want to access the parallel port using the PPDEV interface you have to specify
153 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
154 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
155 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
157 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
158 absolute path containing no spaces.
160 Linux users should copy the various parts of the D2XX package to the appropriate
161 locations, i.e. /usr/include, /usr/lib.
165 @cindex running openocd
167 @cindex --debug_level
170 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
171 Run with @option{--help} or @option{-h} to view the available command line arguments.
173 It reads its configuration by default from the file openocd.cfg located in the current
174 working directory. This may be overwritten with the @option{-f <configfile>} command line
177 To enable debug output (when reporting problems or working on OpenOCD itself), use
178 the @option{-d} command line switch. This sets the debug_level to "3", outputting
179 the most information, including debug messages. The default setting is "2", outputting
180 only informational messages, warnings and errors. You can also change this setting
181 from within a telnet or gdb session (@option{debug_level <n>}).
183 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
185 Search paths for config/script files can be added to openocd by using
186 the @option{-s <search>} switch.
189 @chapter Configuration
190 @cindex configuration
191 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
192 by default from the file openocd.cfg in the current directory. A different configuration
193 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
195 The configuration file is used to specify on which ports the daemon listens for new
196 connections, the JTAG interface used to connect to the target, the layout of the JTAG
197 chain, the targets that should be debugged, and connected flashes.
199 @section Daemon configuration
202 @item @b{telnet_port} <@var{number}>
204 Port on which to listen for incoming telnet connections
205 @item @b{gdb_port} <@var{number}>
207 First port on which to listen for incoming GDB connections. The GDB port for the
208 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
209 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
211 Configures what openocd will do when gdb detaches from the daeman.
212 Default behaviour is <@var{resume}>
213 @item @b{gdb_memory_map} <@var{enable|disable}>
214 @cindex gdb_memory_map
215 Set to <@var{enable}> so that openocd will send the memory configuration to gdb when
216 requested. gdb will then know when to set hardware breakpoints, and program flash
217 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
218 for flash programming to work.
219 Default behaviour is <@var{disable}>
220 @item @b{gdb_flash_program} <@var{enable|disable}>
221 @cindex gdb_flash_program
222 Set to <@var{enable}> so that openocd will program the flash memory when a
223 vFlash packet is received.
224 Default behaviour is <@var{disable}>
225 @item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}
226 @cindex daemon_startup
227 Tells the OpenOCD whether it should reset the target when the daemon is launched, or
228 if it should just attach to the target.
231 @section JTAG interface configuration
234 @item @b{interface} <@var{name}>
236 Use the interface driver <@var{name}> to connect to the target. Currently supported
240 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
244 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
249 FTDI FT2232 based devices using either the open-source libftdi or the binary only
250 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
251 platform. The libftdi uses libusb, and should be portable to all systems that provide
256 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
261 @item @b{jtag_speed} <@var{number}>
263 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
264 speed. The actual effect of this option depends on the JTAG interface used.
267 @item wiggler: maximum speed / @var{number}
268 @item ft2232: 6MHz / (@var{number}+1)
269 @item amt jtagaccel: 8 / 2**@var{number}
272 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
273 especially true for synthesized cores (-S).
275 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
277 The configuration of the reset signals available on the JTAG interface AND the target.
278 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
279 then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},
280 @samp{srst_only} or @samp{trst_and_srst}.
281 [@var{combination}] is an optional value specifying broken reset signal implementations.
282 @samp{srst_pulls_trst} states that the testlogic is reset together with the reset of
283 the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says
284 that the system is reset together with the test logic (only hypothetical, I haven't
285 seen hardware with such a bug, and can be worked around).
287 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
288 reset lines to be specified. Possible values are @samp{trst_push_pull} (default)
289 and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}
290 (default) and @samp{srst_push_pull} for the system reset. These values only affect
291 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
293 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
295 Describes the devices that form the JTAG daisy chain, with the first device being
296 the one closest to TDO. The parameters are the length of the instruction register
297 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
298 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
299 The IDCODE instruction will in future be used to query devices for their JTAG
300 identification code. This line is the same for all ARM7 and ARM9 devices.
301 Other devices, like CPLDs, require different parameters. An example configuration
302 line for a Xilinx XC9500 CPLD would look like this:
304 jtag_device 8 0x01 0x0e3 0xfe
306 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
307 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
308 The IDCODE instruction is 0xfe.
310 @item @b{jtag_nsrst_delay} <@var{ms}>
311 @cindex jtag_nsrst_delay
312 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
313 starting new JTAG operations.
314 @item @b{jtag_ntrst_delay} <@var{ms}>
315 @cindex jtag_ntrst_delay
316 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
317 starting new JTAG operations.
319 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
320 or on-chip features) keep a reset line asserted for some time after the external reset
324 @section parport options
327 @item @b{parport_port} <@var{number}>
329 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
330 the @file{/dev/parport} device
332 When using PPDEV to access the parallel port, use the number of the parallel port:
333 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
334 you may encounter a problem.
335 @item @b{parport_cable} <@var{name}>
336 @cindex parport_cable
337 The layout of the parallel port cable used to connect to the target.
338 Currently supported cables are
342 Original Wiggler layout, also supported by several clones, such
343 as the Olimex ARM-JTAG
344 @item old_amt_wiggler
345 @cindex old_amt_wiggler
346 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
347 version available from the website uses the original Wiggler layout ('@var{wiggler}')
350 Describes the connection of the Amontec Chameleon's CPLD when operated in
351 configuration mode. This is only used to program the Chameleon itself, not
355 Xilinx Parallel cable III.
358 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
359 This is also the layout used by the HollyGates design
360 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
365 @item @b{parport_write_on_exit} <@var{on|off}>
366 @cindex parport_write_on_exit
367 This will configure the parallel driver to write a known value to the parallel
368 interface on exiting openocd
371 @section amt_jtagaccel options
373 @item @b{parport_port} <@var{number}>
375 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
376 @file{/dev/parport} device
378 @section ft2232 options
381 @item @b{ft2232_device_desc} <@var{description}>
382 @cindex ft2232_device_desc
383 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
384 default value is used. This setting is only valid if compiled with FTD2XX support.
385 @item @b{ft2232_layout} <@var{name}>
386 @cindex ft2232_layout
387 The layout of the FT2232 GPIO signals used to control output-enables and reset
388 signals. Valid layouts are
391 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
393 Amontec JTAGkey and JTAGkey-tiny
399 American Microsystems M5960
401 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
402 SRST signals on external connector
406 Hitex STM32 Performance Stick
408 Tin Can Tools Flyswatter
410 egnite Software turtelizer2
415 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
416 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
417 default values are used. This command is not available on Windows.
418 @item @b{ft2232_latency} <@var{ms}>
419 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
420 ft2232_read() fails to return the expected number of bytes. This can be caused by
421 USB communication delays and has proved hard to reproduce and debug. Setting the
422 FT2232 latency timer to a larger value increases delays for short USB packages but it
423 also reduces the risk of timeouts before receiving the expected number of bytes.
424 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
427 @section ep93xx options
428 @cindex ep93xx options
429 Currently, there are no options available for the ep93xx interface.
432 @section Target configuration
435 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
438 Defines a target that should be debugged. Currently supported types are:
452 If you want to use a target board that is not on this list, see Adding a new
455 Endianess may be @option{little} or @option{big}.
457 The reset_mode specifies what should happen to the target when a reset occurs:
461 Immediately request a target halt after reset. This allows targets to be debugged
462 from the very first instruction. This is only possible with targets and JTAG
463 interfaces that correctly implement the reset signals.
466 Similar to @option{reset_halt}, but executes the script file defined to handle the
467 'reset' event for the target. Like @option{reset_halt} this only works with
468 correct reset implementations.
471 Simply let the target run after a reset.
474 Let the target run for some time (default: 1s), and then request halt.
477 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
478 to run for some time, then halted, and the @option{reset} event script is executed.
481 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
482 completely independent (like the LPC2000 series), or where the JTAG interface is
483 unavailable for some time during startup (like the STR7 series), you can't use
484 @option{reset_halt} or @option{reset_init}.
486 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
487 @cindex target_script
488 Event is either @option{reset}, @option{post_halt}, @option{pre_resume} or @option{gdb_program_config}
490 TODO: describe exact semantic of events
491 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
492 @cindex run_and_halt_time
493 The amount of time the debugger should wait after releasing reset before it asserts
494 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
496 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
497 <@var{backup}|@var{nobackup}>
499 Specifies a working area for the debugger to use. This may be used to speed-up
500 downloads to target memory and flash operations, or to perform otherwise unavailable
501 operations (some coprocessor operations on ARM7/9 systems, for example). The last
502 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
503 a working_area that doesn't need to be backed up, as that slows down operation.
506 @subsection arm7tdmi options
507 @cindex arm7tdmi options
508 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
509 The arm7tdmi target definition requires at least one additional argument, specifying
510 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
511 The optional [@var{variant}] parameter has been removed in recent versions.
512 The correct feature set is determined at runtime.
514 @subsection arm720t options
515 @cindex arm720t options
516 ARM720t options are similar to ARM7TDMI options.
518 @subsection arm9tdmi options
519 @cindex arm9tdmi options
520 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
521 @option{arm920t}, @option{arm922t} and @option{arm940t}.
522 This enables the hardware single-stepping support found on these cores.
524 @subsection arm920t options
525 @cindex arm920t options
526 ARM920t options are similar to ARM9TDMI options.
528 @subsection arm966e options
529 @cindex arm966e options
530 ARM966e options are similar to ARM9TDMI options.
532 @subsection xscale options
533 @cindex xscale options
534 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
535 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
537 @section Flash configuration
538 @cindex Flash configuration
541 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
542 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
544 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
545 and <@var{bus_width}> bytes using the selected flash <driver>.
547 @item @b{flash auto_erase} <@option{on}|@option{off}>
548 @cindex flash auto_erase
549 auto erase flash banks prior to writing. Currently only works when using
550 @option{flash write_image} command. Default is @option{off}.
553 @subsection lpc2000 options
554 @cindex lpc2000 options
556 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
557 <@var{clock}> [@var{calc_checksum}]
558 LPC flashes don't require the chip and bus width to be specified. Additional
559 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
560 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
561 of the target this flash belongs to (first is 0), the frequency at which the core
562 is currently running (in kHz - must be an integral number), and the optional keyword
563 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
566 @subsection cfi options
569 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
571 CFI flashes require the number of the target they're connected to as an additional
572 argument. The CFI driver makes use of a working area (specified for the target)
573 to significantly speed up operation.
575 @var{chip_width} and @var{bus_width} are specified in bytes.
577 @subsection at91sam7 options
578 @cindex at91sam7 options
580 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
581 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
582 reading the chip-id and type.
584 @subsection str7 options
587 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
588 variant can be either STR71x, STR73x or STR75x.
590 @subsection str9 options
593 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
594 The str9 needs the flash controller to be configured prior to Flash programming, eg.
596 str9x flash_config 0 4 2 0 0x80000
598 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
600 @subsection str9 options (str9xpec driver)
602 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
603 Before using the flash commands the turbo mode will need enabling using str9xpec
604 @option{enable_turbo} <@var{num>.}
606 Only use this driver for locking/unlocking the device or configuring the option bytes.
607 Use the standard str9 driver for programming.
609 @subsection stellaris (LM3Sxxx) options
610 @cindex stellaris (LM3Sxxx) options
612 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
613 stellaris flash plugin only require the @var{target#}.
615 @subsection stm32x options
616 @cindex stm32x options
618 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
619 stm32x flash plugin only require the @var{target#}.
625 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
626 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
627 is available from both the telnet interface and a GDB session. To issue commands to the
628 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
629 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
635 @item @b{sleep} <@var{msec}>
637 Wait for n milliseconds before resuming. Useful in connection with script files
638 (@var{script} command and @var{target_script} configuration).
642 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
644 @item @b{debug_level} [@var{n}]
646 Display or adjust debug level to n<0-3>
648 @item @b{log_output} <@var{file}>
650 Redirect logging to <file> (default: stderr)
652 @item @b{script} <@var{file}>
654 Execute commands from <file>
658 @subsection Target state handling
660 @item @b{poll} [@option{on}|@option{off}]
662 Poll the target for its current state. If the target is in debug mode, architecture
663 specific information about the current state are printed. An optional parameter
664 allows continuous polling to be enabled and disabled.
666 @item @b{halt} [@option{ms}]
668 Send a halt request to the target and waits for it to halt for [@option{ms}].
669 Default [@option{ms}] is 5 seconds if no arg given.
670 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
671 will stop openocd from waiting.
673 @item @b{wait_halt} [@option{ms}]
675 Wait for the target to enter debug mode. Optional [@option{ms}] is
676 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
679 @item @b{resume} [@var{address}]
681 Resume the target at its current code position, or at an optional address.
682 Openocd will wait 5 seconds for the target to resume.
684 @item @b{step} [@var{address}]
686 Single-step the target at its current code position, or at an optional address.
688 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
689 |@option{run_and_init}]
691 Do a hard-reset. The optional parameter specifies what should happen after the reset.
692 This optional parameter overwrites the setting specified in the configuration file,
693 making the new behaviour the default for the @option{reset} command.
700 Immediately halt the target (works only with certain configurations).
703 Immediately halt the target, and execute the reset script (works only with certain
706 @cindex reset run_and_halt
707 Let the target run for a certain amount of time, then request a halt.
709 @cindex reset run_and_init
710 Let the target run for a certain amount of time, then request a halt. Execute the
711 reset script once the target entered debug mode.
715 @subsection Memory access commands
716 These commands allow accesses of a specific size to the memory system:
718 @item @b{mdw} <@var{addr}> [@var{count}]
721 @item @b{mdh} <@var{addr}> [@var{count}]
723 display memory half-words
724 @item @b{mdb} <@var{addr}> [@var{count}]
727 @item @b{mww} <@var{addr}> <@var{value}>
730 @item @b{mwh} <@var{addr}> <@var{value}>
732 write memory half-word
733 @item @b{mwb} <@var{addr}> <@var{value}>
737 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
739 Load image <@var{file}> to target memory at <@var{address}>
740 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
742 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
743 (binary) <@var{file}>.
744 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
746 Verify <@var{file}> to target memory starting at <@var{address}>.
747 This will first attempt using a crc checksum, if this fails it will try a binary compare.
748 @item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]
750 Load binary <@var{file}> to target memory at <@var{address}>
751 @item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]
753 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
754 (binary) <@var{file}>.
757 @subsection Flash commands
758 @cindex Flash commands
760 @item @b{flash banks}
762 List configured flash banks
763 @item @b{flash info} <@var{num}>
765 Print info about flash bank <@option{num}>
766 @item @b{flash probe} <@var{num}>
768 Identify the flash, or validate the parameters of the configured flash. Operation
769 depends on the flash type.
770 @item @b{flash erase_check} <@var{num}>
771 @cindex flash erase_check
772 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
773 updates the erase state information displayed by @option{flash info}. That means you have
774 to issue an @option{erase_check} command after erasing or programming the device to get
776 @item @b{flash protect_check} <@var{num}>
777 @cindex flash protect_check
778 Check protection state of sectors in flash bank <num>.
780 @item @b{flash erase} <@var{num}> <@var{first}> <@var{last}> [DEPRECATED]
782 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
783 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
784 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
785 the CFI driver). This command was replaced by the new command
786 @option{flash erase_sector} using the same syntax.
787 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
788 @cindex flash erase_sector
789 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
790 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
791 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
793 @item @b{flash erase_address} <@var{address}> <@var{length}>
794 @cindex flash erase_address
795 Erase sectors starting at <@var{address}> for <@var{length}> number of bytes
796 @item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]
798 Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>
799 bytes from the beginning of the bank. This command was replaced by the new command
800 @option{flash write_binary} using the same syntax.
801 @item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>
802 @cindex flash write_binary
803 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
804 <@option{offset}> bytes from the beginning of the bank.
805 @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
806 @cindex flash write_image
807 Write the image <@var{file}> to the current target's flash bank(s). A relocation
808 [@var{offset}] can be specified and the file [@var{type}] can be specified
809 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
810 (ELF file) or @option{s19} (Motorola s19).
811 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
812 @cindex flash protect
813 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
814 <@var{last}> of @option{flash bank} <@var{num}>.
815 @item @b{flash auto_erase} <@var{on}|@var{off}>
816 @cindex flash auto_erase
817 Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
818 only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
822 @section Target Specific Commands
823 @cindex Target Specific Commands
825 @subsection AT91SAM7 specific commands
826 @cindex AT91SAM7 specific commands
827 The flash configuration is deduced from the chip identification register. The flash
828 controller handles erases automatically on a page (128/265 byte) basis so erase is
829 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
830 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
831 that can be erased separatly.Only an EraseAll command is supported by the controller
832 for each flash plane and this is called with
834 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
835 bulk erase flash planes first_plane to last_plane.
836 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
837 @cindex at91sam7 gpnvm
838 set or clear a gpnvm bit for the processor
841 @subsection STR9 specific commands
842 @cindex STR9 specific commands
843 These are flash specific commands when using the str9xpec driver.
845 @item @b{str9xpec enable_turbo} <@var{num}>
846 @cindex str9xpec enable_turbo
847 enable turbo mode, simply this will remove the str9 from the chain and talk
848 directly to the embedded flash controller.
849 @item @b{str9xpec disable_turbo} <@var{num}>
850 @cindex str9xpec disable_turbo
851 restore the str9 into jtag chain.
852 @item @b{str9xpec lock} <@var{num}>
853 @cindex str9xpec lock
854 lock str9 device. The str9 will only respond to an unlock command that will
856 @item @b{str9xpec unlock} <@var{num}>
857 @cindex str9xpec unlock
859 @item @b{str9xpec options_read} <@var{num}>
860 @cindex str9xpec options_read
861 read str9 option bytes.
862 @item @b{str9xpec options_write} <@var{num}>
863 @cindex str9xpec options_write
864 write str9 option bytes.
867 @subsection STR9 configuration
868 @cindex STR9 configuration
870 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
871 <@var{BBADR}> <@var{NBBADR}>
872 @cindex str9x flash_config
873 Configure str9 flash controller.
875 eg. str9x flash_config 0 4 2 0 0x80000
877 BBSR - Boot Bank Size register
878 NBBSR - Non Boot Bank Size register
879 BBADR - Boot Bank Start Address register
880 NBBADR - Boot Bank Start Address register
884 @subsection STR9 option byte configuration
885 @cindex STR9 option byte configuration
887 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
888 @cindex str9xpec options_cmap
889 configure str9 boot bank.
890 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
891 @cindex str9xpec options_lvdthd
892 configure str9 lvd threshold.
893 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
894 @cindex str9xpec options_lvdsel
895 configure str9 lvd source.
896 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
897 @cindex str9xpec options_lvdwarn
898 configure str9 lvd reset warning source.
901 @subsection STM32x specific commands
902 @cindex STM32x specific commands
904 These are flash specific commands when using the stm32x driver.
906 @item @b{stm32x lock} <@var{num}>
909 @item @b{stm32x unlock} <@var{num}>
910 @cindex stm32x unlock
912 @item @b{stm32x options_read} <@var{num}>
913 @cindex stm32x options_read
914 read stm32 option bytes.
915 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
916 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
917 @cindex stm32x options_write
918 write stm32 option bytes.
919 @item @b{stm32x mass_erase} <@var{num}>
920 @cindex stm32x mass_erase
921 mass erase flash memory.
925 @section Architecture Specific Commands
926 @cindex Architecture Specific Commands
928 @subsection ARMV4/5 specific commands
929 @cindex ARMV4/5 specific commands
931 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
932 or Intel XScale (XScale isn't supported yet).
934 @item @b{armv4_5 reg}
936 Display a list of all banked core registers, fetching the current value from every
937 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
939 @item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]
940 @cindex armv4_5 core_mode
941 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
942 The target is resumed in the currently set @option{core_mode}.
945 @subsection ARM7/9 specific commands
946 @cindex ARM7/9 specific commands
948 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
949 ARM920t or ARM926EJ-S.
951 @item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>
952 @cindex arm7_9 sw_bkpts
953 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
954 one of the watchpoint registers to implement software breakpoints. Disabling
955 SW Bkpts frees that register again.
956 @item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>
957 @cindex arm7_9 force_hw_bkpts
958 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
959 breakpoints are turned into hardware breakpoints.
960 @item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>
962 Enable use of the DBGRQ bit to force entry into debug mode. This should be
963 safe for all but ARM7TDMI--S cores (like Philips LPC).
964 @item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>
965 @cindex arm7_9 fast_writes [DEPRECATED]
966 See @option{arm7_9 fast_memory_access} instead.
967 @item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>
968 @cindex arm7_9 fast_memory_access
969 Allow the OpenOCD to read and write memory without checking completion of
970 the operation. This provides a huge speed increase, especially with USB JTAG
971 cables (FT2232), but might be unsafe if used with targets running at a very low
972 speed, like the 32kHz startup clock of an AT91RM9200.
973 @item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>
974 @cindex arm7_9 dcc_downloads
975 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
976 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
977 unsafe, especially with targets running at a very low speed. This command was introduced
978 with OpenOCD rev. 60.
981 @subsection ARM920T specific commands
982 @cindex ARM920T specific commands
985 @item @b{arm920t cache_info}
986 @cindex arm920t cache_info
987 Print information about the caches found. This allows you to see if your target
988 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
989 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
990 @cindex arm920t md<bhw>_phys
991 Display memory at physical address addr.
992 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
993 @cindex arm920t mw<bhw>_phys
994 Write memory at physical address addr.
995 @item @b{arm920t read_cache} <@var{filename}>
996 @cindex arm920t read_cache
997 Dump the content of ICache and DCache to a file.
998 @item @b{arm920t read_mmu} <@var{filename}>
999 @cindex arm920t read_mmu
1000 Dump the content of the ITLB and DTLB to a file.
1001 @item @b{arm920t virt2phys} <@var{VA}>
1002 @cindex arm920t virt2phys
1003 Translate a virtual address to a physical address.
1007 @section Debug commands
1008 @cindex Debug commands
1009 The following commands give direct access to the core, and are most likely
1010 only useful while debugging the OpenOCD.
1012 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1013 @cindex arm7_9 write_xpsr
1014 Immediately write either the current program status register (CPSR) or the saved
1015 program status register (SPSR), without changing the register cache (as displayed
1016 by the @option{reg} and @option{armv4_5 reg} commands).
1017 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1018 <@var{0=cpsr},@var{1=spsr}>
1019 @cindex arm7_9 write_xpsr_im8
1020 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1021 operation (similar to @option{write_xpsr}).
1022 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1023 @cindex arm7_9 write_core_reg
1024 Write a core register, without changing the register cache (as displayed by the
1025 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1026 encoding of the [M4:M0] bits of the PSR.
1030 @section JTAG commands
1031 @cindex JTAG commands
1033 @item @b{scan_chain}
1035 Print current scan chain configuration.
1036 @item @b{jtag_reset}
1038 Toggle reset lines <@var{trst}> <@var{srst}>.
1039 @item @b{endstate} <@var{tap_state}>
1041 Finish JTAG operations in <@var{tap_state}>.
1042 @item @b{runtest} <@var{num_cycles}>
1044 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1045 @item @b{statemove} [@var{tap_state}]
1047 Move to current endstate or [@var{tap_state}]
1050 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1053 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1054 @item @b{verify_ircapture}
1055 @cindex verify_ircapture
1056 Verify value captured during Capture-IR <@option{enable}|@option{disable}>
1059 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1062 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1065 @node Sample Scripts
1066 @chapter Sample Scripts
1069 This page will collect some script examples for different CPUs.
1071 The configuration script can be divided in the following section:
1073 @item daemon configuration
1075 @item jtag scan chain
1076 @item target configuration
1077 @item flash configuration
1080 Detailed information about each section can be found at OpenOCD configuration
1082 @section OMAP5912 Flash Debug
1083 @cindex OMAP5912 Flash Debug
1084 The following two scripts were used with a wiggler PP and and a TI OMAP5912
1085 dual core processor - (@uref{http://www.ti.com}), on a OMAP5912 OSK board
1086 - (@uref{http://www.spectrumdigital.com}).
1087 @subsection Openocd config
1089 #daemon configuration
1096 parport_cable wiggler
1099 #use combined on interfaces or targets that can't set TRST/SRST separately
1100 reset_config trst_and_srst
1103 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1104 jtag_device 38 0x0 0x0 0x0
1105 jtag_device 4 0x1 0x0 0xe
1106 jtag_device 8 0x0 0x0 0x0
1108 #target configuration
1109 daemon_startup reset
1111 #target <type> <endianness> <reset mode> <chainpos> <variant>
1112 target arm926ejs little run_and_init 1 arm926ejs
1113 target_script 0 reset omap5912_osk.init
1114 run_and_halt_time 0 30
1116 # omap5912 lcd frame buffer as working area
1117 working_area 0 0x20000000 0x3e800 nobackup
1119 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1120 flash bank cfi 0x00000000 0x1000000 2 2 0
1123 @subsection Openocd init
1135 mww 0xfffec808 0x000000f5
1136 mww 0xfffec808 0x000000a0
1138 mww 0xfffeb048 0x0000aaaa
1140 mww 0xfffeb048 0x00005555
1149 @section STR71x Script
1150 @cindex STR71x Script
1151 The following script was used with an Amontec JTAGkey and a STR710 / STR711 cpu:
1153 #daemon configuration
1159 ft2232_device_desc "Amontec JTAGkey A"
1160 ft2232_layout jtagkey
1161 ft2232_vid_pid 0x0403 0xcff8
1164 #use combined on interfaces or targets that can't set TRST/SRST separately
1165 reset_config trst_and_srst srst_pulls_trst
1168 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1169 jtag_device 4 0x1 0xf 0xe
1171 #target configuration
1172 daemon_startup reset
1174 #target <type> <startup mode>
1175 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1176 target arm7tdmi little run_and_halt 0 arm7tdmi
1177 run_and_halt_time 0 30
1179 working_area 0 0x2000C000 0x4000 nobackup
1181 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1182 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
1185 @section STR750 Script
1186 @cindex STR750 Script
1187 The following script was used with an Amontec JTAGkey and a STR750 cpu:
1189 #daemon configuration
1195 ft2232_device_desc "Amontec JTAGkey A"
1196 ft2232_layout jtagkey
1197 ft2232_vid_pid 0x0403 0xcff8
1200 #use combined on interfaces or targets that can't set TRST/SRST separately
1201 #reset_config trst_and_srst srst_pulls_trst
1202 reset_config trst_and_srst srst_pulls_trst
1205 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1206 jtag_device 4 0x1 0xf 0xe
1208 #jtag nTRST and nSRST delay
1209 jtag_nsrst_delay 500
1210 jtag_ntrst_delay 500
1212 #target configuration
1213 daemon_startup reset
1215 #target <type> <startup mode>
1216 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1217 target arm7tdmi little run_and_halt 0 arm7tdmi
1218 run_and_halt_time 0 30
1220 working_area 0 0x40000000 0x4000 nobackup
1222 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1223 flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
1226 @section STR912 Script
1227 @cindex STR912 Script
1228 The following script was used with an Amontec JTAGkey and a STR912 cpu:
1230 #daemon configuration
1236 ft2232_device_desc "Amontec JTAGkey A"
1237 ft2232_layout jtagkey
1240 #use combined on interfaces or targets that can't set TRST/SRST separately
1241 reset_config trst_and_srst
1244 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1245 jtag_device 8 0x1 0x1 0xfe
1246 jtag_device 4 0x1 0xf 0xe
1247 jtag_device 5 0x1 0x1 0x1e
1249 #target configuration
1250 daemon_startup reset
1252 #target <type> <startup mode>
1253 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1254 target arm966e little reset_halt 1 arm966e
1255 run_and_halt_time 0 30
1257 working_area 0 0x50000000 16384 nobackup
1259 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1260 flash bank str9x 0x00000000 0x00080000 0 0 0
1263 @section STR912 comstick
1264 @cindex STR912 comstick Script
1265 The following script was used with a Hitex STR9 Comstick:
1267 #daemon configuration
1273 ft2232_device_desc "STR9-comStick A"
1274 ft2232_layout comstick
1277 jtag_nsrst_delay 100
1278 jtag_ntrst_delay 100
1280 #use combined on interfaces or targets that can't set TRST/SRST separately
1281 reset_config trst_and_srst
1284 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1285 jtag_device 8 0x1 0x1 0xfe
1286 jtag_device 4 0x1 0xf 0xe
1287 jtag_device 5 0x1 0x1 0x1e
1289 #target configuration
1290 daemon_startup reset
1292 #target <type> <startup mode>
1293 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1294 target arm966e little reset_halt 1 arm966e
1295 run_and_halt_time 0 30
1297 working_area 0 0x50000000 16384 nobackup
1299 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1300 flash bank str9x 0x00000000 0x00080000 0 0 0
1303 @section STM32x Script
1304 @cindex STM32x Script
1305 The following script was used with an Amontec JTAGkey and a STM32x cpu:
1307 #daemon configuration
1313 ft2232_device_desc "Amontec JTAGkey A"
1314 ft2232_layout jtagkey
1317 jtag_nsrst_delay 100
1318 jtag_ntrst_delay 100
1320 #use combined on interfaces or targets that can't set TRST/SRST separately
1321 reset_config trst_and_srst
1324 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1325 jtag_device 4 0x1 0xf 0xe
1326 jtag_device 5 0x1 0x1 0x1e
1328 #target configuration
1329 daemon_startup reset
1331 #target <type> <startup mode>
1332 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1333 target cortex_m3 little run_and_halt 0
1334 run_and_halt_time 0 30
1336 working_area 0 0x20000000 16384 nobackup
1338 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1339 flash bank stm32x 0x08000000 0x00020000 0 0 0
1342 @section STM32x Performance Stick
1343 @cindex STM32x Performance Stick Script
1344 The following script was used with the Hitex STM32 Performance Stick
1346 #daemon configuration
1352 ft2232_device_desc "STM32-PerformanceStick A"
1353 ft2232_layout stm32stick
1356 jtag_nsrst_delay 100
1357 jtag_ntrst_delay 100
1359 #use combined on interfaces or targets that can't set TRST/SRST separately
1360 reset_config trst_and_srst
1363 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1364 jtag_device 4 0x1 0xf 0xe
1365 jtag_device 5 0x1 0x1 0x1e
1366 jtag_device 4 0x1 0xf 0xe
1368 #target configuration
1369 daemon_startup reset
1371 #target <type> <startup mode>
1372 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1373 target cortex_m3 little run_and_halt 0
1374 run_and_halt_time 0 30
1376 working_area 0 0x20000000 16384 nobackup
1378 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1379 flash bank stm32x 0x08000000 0x00020000 0 0 0
1382 @section LPC2129 Script
1383 @cindex LPC2129 Script
1384 The following script was used with an wiggler PP and a LPC-2129 cpu:
1386 #daemon configuration
1393 parport_cable wiggler
1396 #use combined on interfaces or targets that can't set TRST/SRST separately
1397 reset_config trst_and_srst srst_pulls_trst
1400 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1401 jtag_device 4 0x1 0xf 0xe
1403 #target configuration
1404 daemon_startup reset
1406 #target <type> <startup mode>
1407 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1408 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1409 run_and_halt_time 0 30
1411 working_area 0 0x40000000 0x4000 nobackup
1413 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1414 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1417 @section LPC2148 Script
1418 @cindex LPC2148 Script
1419 The following script was used with an Amontec JTAGkey and a LPC2148 cpu:
1421 #daemon configuration
1427 ft2232_device_desc "Amontec JTAGkey A"
1428 ft2232_layout jtagkey
1429 ft2232_vid_pid 0x0403 0xcff8
1432 #use combined on interfaces or targets that can't set TRST/SRST separately
1433 reset_config trst_and_srst srst_pulls_trst
1436 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1437 jtag_device 4 0x1 0xf 0xe
1439 #target configuration
1440 daemon_startup reset
1442 #target <type> <startup mode>
1443 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1444 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1445 run_and_halt_time 0 30
1447 working_area 0 0x40000000 0x8000 nobackup
1449 #flash configuration
1450 flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v1 14765 calc_checksum
1453 @section LPC2294 Script
1454 @cindex LPC2294 Script
1455 The following script was used with an Amontec JTAGkey and a LPC2294 cpu:
1457 #daemon configuration
1463 ft2232_device_desc "Amontec JTAGkey A"
1464 ft2232_layout jtagkey
1465 ft2232_vid_pid 0x0403 0xcff8
1468 #use combined on interfaces or targets that can't set TRST/SRST separately
1469 reset_config trst_and_srst srst_pulls_trst
1472 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1473 jtag_device 4 0x1 0xf 0xe
1475 #target configuration
1476 daemon_startup reset
1478 #target <type> <startup mode>
1479 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1480 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1481 run_and_halt_time 0 30
1483 working_area 0 0x40000000 0x4000 nobackup
1485 #flash configuration
1486 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1489 @section AT91R40008 Script
1490 @cindex AT91R40008 Script
1491 The following script was used with an Amontec JTAGkey and a AT91R40008 cpu:
1493 #daemon configuration
1499 ft2232_device_desc "Amontec JTAGkey A"
1500 ft2232_layout jtagkey
1501 ft2232_vid_pid 0x0403 0xcff8
1503 jtag_nsrst_delay 200
1504 jtag_ntrst_delay 200
1506 #use combined on interfaces or targets that can't set TRST/SRST separately
1507 reset_config srst_only srst_pulls_trst
1510 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1511 jtag_device 4 0x1 0xf 0xe
1513 #target configuration
1514 daemon_startup reset
1516 #target <type> <startup mode>
1517 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1518 target arm7tdmi little run_and_halt 0 arm7tdmi
1519 run_and_halt_time 0 30
1522 @section AT91SAM7s Script
1523 @cindex AT91SAM7s Script
1524 The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 cpu:
1526 #daemon configuration
1532 ft2232_device_desc "Olimex OpenOCD JTAG A"
1533 ft2232_layout olimex-jtag
1534 ft2232_vid_pid 0x15BA 0x0003
1536 jtag_nsrst_delay 200
1537 jtag_ntrst_delay 200
1539 #use combined on interfaces or targets that can't set TRST/SRST separately
1540 reset_config srst_only srst_pulls_trst
1543 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1544 jtag_device 4 0x1 0xf 0xe
1546 #target configuration
1547 daemon_startup reset
1549 #target <type> <startup mode>
1550 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1551 target arm7tdmi little run_and_halt 0 arm7tdmi
1552 run_and_halt_time 0 30
1554 # flash-options AT91
1555 working_area 0 0x00200000 0x4000 nobackup
1556 flash bank at91sam7 0 0 0 0 0
1559 # erase command (telnet-interface) for complete flash:
1560 # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
1561 # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
1562 # set/clear NVM-Bits:
1563 # at91sam7 gpnvm <num> <bit> <set|clear>
1564 # disable locking from SAM-BA:
1565 # flash protect 0 0 1 off
1568 @section XSCALE IXP42x Script
1569 @cindex XSCALE IXP42x Script
1570 The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x cpu:
1572 #daemon configuration
1578 ft2232_device_desc "Amontec JTAGkey A"
1579 ft2232_layout jtagkey
1580 ft2232_vid_pid 0x0403 0xcff8
1582 jtag_nsrst_delay 200
1583 jtag_ntrst_delay 200
1585 #use combined on interfaces or targets that can't set TRST/SRST separately
1586 reset_config srst_only srst_pulls_trst
1589 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1590 jtag_device 7 0x1 0x7f 0x7e
1592 #target configuration
1593 daemon_startup reset
1595 #target <type> <startup mode>
1596 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1597 target xscale big run_and_halt 0 IXP42x
1598 run_and_halt_time 0 30
1601 @section Cirrus Logic EP9301 Script
1602 @cindex Cirrus Logic EP9301 Script
1603 The following script was used with FT2232 based JTAG interfaces and a
1604 Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
1606 #daemon configuration
1614 #ft2232_device_desc "Olimex OpenOCD JTAG"
1615 #ft2232_layout olimex-jtag
1616 #ft2232_vid_pid 0x15ba 0x0003
1618 #Amontec JTAGkey (and JTAGkey-Tiny)
1619 #Serial is only necessary if more than one JTAGkey is connected
1620 ft2232_device_desc "Amontec JTAGkey A"
1621 #ft2232_serial AMTJKV31
1622 #ft2232_serial T1P3S2W8
1623 ft2232_layout jtagkey
1624 ft2232_vid_pid 0x0403 0xcff8
1626 #wiggler/parallel port interface
1629 #parport_cable wiggler
1632 reset_config trst_and_srst
1635 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1636 jtag_device 4 0x1 0xf 0xe
1638 jtag_nsrst_delay 100
1639 jtag_ntrst_delay 100
1641 #target configuration
1642 daemon_startup attach
1644 #target <type> <endianess> <reset mode>
1645 target arm920t little reset_halt 0
1646 working_area 0 0x80014000 0x1000 backup
1648 #flash configuration
1649 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
1650 flash bank cfi 0x60000000 0x1000000 2 2 0
1653 @section Hilscher netX 100 / 500 Script
1654 @cindex Hilscher netX 100 / 500 Script
1655 The following script was used with an Amontec JTAGkey and a Hilscher
1658 #daemon configuration
1664 ft2232_device_desc "Amontec JTAGkey A"
1665 ft2232_layout jtagkey
1666 ft2232_vid_pid 0x0403 0xcff8
1669 #use combined on interfaces or targets that can't set TRST/SRST separately
1670 reset_config trst_and_srst
1673 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1674 jtag_device 4 0x1 0xf 0xe
1676 jtag_nsrst_delay 100
1677 jtag_ntrst_delay 100
1679 #target configuration
1680 daemon_startup reset
1682 #target <type> <endianness> <startup mode> <chainpos> <variant>
1683 target arm926ejs little run_and_halt 0 arm926ejs
1684 run_and_halt_time 0 500
1687 @section Marvell/Intel PXA270 Script
1688 @cindex Marvell/Intel PXA270 Script
1690 # config for Intel PXA270
1691 # not, as of 2007-06-22, openocd only works with the
1692 # libftd2xx library from ftdi. libftdi does not work.
1698 ft2232_layout olimex-jtag
1699 ft2232_vid_pid 0x15BA 0x0003
1700 ft2232_device_desc "Olimex OpenOCD JTAG"
1702 # set jtag_nsrst_delay to the delay introduced by your reset circuit
1703 # the rest of the needed delays are built into the openocd program
1704 jtag_nsrst_delay 260
1705 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
1706 # the rest of the needed delays are built into the openocd program
1709 #use combined on interfaces or targets that can't set TRST/SRST separately
1710 reset_config trst_and_srst separate
1713 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1714 jtag_device 7 0x1 0x7f 0x7e
1716 #target configuration
1717 daemon_startup reset
1719 target xscale little reset_halt 0 pxa27x
1721 # maps to PXA internal RAM. If you are using a PXA255
1722 # you must initialize SDRAM or leave this option off
1723 working_area 0 0x5c000000 0x10000 nobackup
1725 run_and_halt_time 0 30
1727 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1728 # works for P30 flash
1729 flash bank cfi 0x00000000 0x1000000 2 4 0
1732 @node GDB and Openocd
1733 @chapter GDB and Openocd
1734 @cindex GDB and Openocd
1735 Openocd complies with the remote gdbserver protocol, and as such can be used
1736 to debug remote targets.
1738 @section Connecting to gdb
1739 @cindex Connecting to gdb
1740 A connection is typically started as follows:
1742 target remote localhost:3333
1744 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1746 To see a list of available openocd commands type @option{monitor help} on the
1749 Openocd supports the gdb @option{qSupported} packet, this enables information
1750 to be sent by the gdb server (openocd) to gdb. Typical information includes
1751 packet size and device memory map.
1753 Previous versions of openocd required the following gdb options to increase
1754 the packet size and speed up gdb communication.
1756 set remote memory-write-packet-size 1024
1757 set remote memory-write-packet-size fixed
1758 set remote memory-read-packet-size 1024
1759 set remote memory-read-packet-size fixed
1761 This is now handled in the @option{qSupported} PacketSize.
1763 @section Programming using gdb
1764 @cindex Programming using gdb
1766 By default the target memory map is not sent to gdb, this can be enabled by
1767 the following openocd config option:
1769 gdb_memory_map enable
1771 For this to function correctly a valid flash config must also be configured
1772 in openocd. For speed also configure a valid working area.
1774 Informing gdb of the memory map of the target will enable gdb to protect any
1775 flash area of the target and use hardware breakpoints by default. This means
1776 that the openocd option @option{arm7_9 force_hw_bkpts} is not required when
1779 To view the configured memory map in gdb, use the gdb command @option{info mem}
1780 All other unasigned addresses within gdb are treated as ram.
1782 If @option{gdb_flash_program enable} is also used, gdb will be able to
1783 program any flash memory using the vFlash interface.
1785 gdb will look at the target memory map when a load command is given, if any
1786 areas to be programmed lie within the target flash area the vFlash packets
1789 Incase the target needs configuring before gdb programming, a script can be executed.
1791 target_script 0 gdb_program_config config.script
1794 To verify any flash programming the gdb command @option{compare-sections}
1801 @item OpenOCD complains about a missing cygwin1.dll
1803 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1804 claims to come with all the necessary dlls. When using Cygwin, try launching
1805 the OpenOCD from the Cygwin shell.
1807 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1808 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1809 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1811 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1812 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1813 software breakpoints consume one of the two available hardware breakpoints,
1814 and are therefor disabled by default. If your code is running from RAM, you
1815 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1816 your code resides in Flash, you can't use software breakpoints, but you can force
1817 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1819 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1820 and works sometimes fine.
1822 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1823 clock at the time you're programming the flash. If you've specified the crystal's
1824 frequency, make sure the PLL is disabled, if you've specified the full core speed
1825 (e.g. 60MHz), make sure the PLL is enabled.
1827 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1828 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1829 out while waiting for end of scan, rtck was disabled".
1831 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1832 settings in your PC Bios (ECP, EPP, and different versions of those).
1834 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1835 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1836 memory read caused data abort".
1838 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1839 beyond the last valid frame. It might be possible to prevent this by setting up
1840 a proper "initial" stack frame, if you happen to know what exactly has to
1841 be done, feel free to add this here.
1843 @item I get the following message in the OpenOCD console (or log file):
1844 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1846 This warning doesn't indicate any serious problem, as long as you don't want to
1847 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1848 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
1849 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1850 independently. With this setup, it's not possible to halt the core right out of
1851 reset, everything else should work fine.
1853 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1854 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1855 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1856 quit with an error message. Is there a stability issue with OpenOCD?
1858 No, this is not a stability issue concering OpenOCD. Most users have solved
1859 this issue by simply using a self-powered USB Hub, which they connect their
1860 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1861 supply stable enough for the Amontec JTAGkey to be operated.
1863 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1864 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1865 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1866 What does that mean and what might be the reason for this?
1868 First of all, the reason might be the USB power supply. Try using a self-powered
1869 hub instead of a direct connection to your computer. Secondly, the error code 4
1870 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1871 Chip ran into some sort of error - this points us to a USB problem.
1873 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1874 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1875 What does that mean and what might be the reason for this?
1877 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1878 has closed the connection to OpenOCD. This might be a GDB issue.
1880 @item In the configuration file in the section where flash device configurations
1881 are described, there is a parameter for specifying the clock frequency for
1882 LPC2000 internal flash devices (e.g.
1883 @option{flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14746 calc_checksum}),
1884 which must be sepcified in kilohertz. However, I do have a quartz crystal of a
1885 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1886 Is it possible to specify real numbers for the clock frequency?
1888 No. The clock frequency specified here must be given as an integral number.
1889 However, this clock frequency is used by the In-Application-Programming (IAP)
1890 routines of the LPC2000 family only, which seems to be very tolerant concerning
1891 the given clock frequency, so a slight difference between the specified clock
1892 frequency and the actual clock frequency will not cause any trouble.
1894 @item Do I have to keep a specific order for the commands in the configuration file?
1896 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1897 listed for the JTAG scan chain must be given in the right order (jtag_device),
1898 with the device closest to the TDO-Pin being listed first. In general,
1899 whenever objects of the same type exist which require an index number, then
1900 these objects must be given in the right order (jtag_devices, targets and flash
1901 banks - a target references a jtag_device and a flash bank references a target).
1903 @item Sometimes my debugging session terminates with an error. When I look into the
1904 log file, I can see these error messages: Error: arm7_9_common.c:561
1905 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP