1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2006 by Magnus Lundin *
7 * Copyright (C) 2008 by Spencer Oliver *
8 * spen@spen-soft.co.uk *
10 * Copyright (C) 2009-2010 by Oyvind Harboe *
11 * oyvind.harboe@zylin.com *
13 * Copyright (C) 2009-2010 by David Brownell *
15 * Copyright (C) 2013 by Andreas Fritiofson *
16 * andreas.fritiofson@gmail.com *
18 * Copyright (C) 2019-2021, Ampere Computing LLC *
19 ***************************************************************************/
23 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
24 * debugging architecture. Compared with previous versions, this includes
25 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
26 * transport, and focuses on memory mapped resources as defined by the
27 * CoreSight architecture.
29 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
30 * basic components: a Debug Port (DP) transporting messages to and from a
31 * debugger, and an Access Port (AP) accessing resources. Three types of DP
32 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
33 * One uses only SWD for communication, and is called SW-DP. The third can
34 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
35 * is used to access memory mapped resources and is called a MEM-AP. Also a
36 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
38 * This programming interface allows DAP pipelined operations through a
39 * transaction queue. This primarily affects AP operations (such as using
40 * a MEM-AP to access memory or registers). If the current transaction has
41 * not finished by the time the next one must begin, and the ORUNDETECT bit
42 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
43 * further AP operations will fail. There are two basic methods to avoid
44 * such overrun errors. One involves polling for status instead of using
45 * transaction pipelining. The other involves adding delays to ensure the
46 * AP has enough time to complete one operation before starting the next
47 * one. (For JTAG these delays are controlled by memaccess_tck.)
51 * Relevant specifications from ARM include:
53 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031F
54 * ARM(tm) Debug Interface v6 Architecture Specification ARM IHI 0074C
55 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
57 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
58 * Cortex-M3(tm) TRM, ARM DDI 0337G
65 #include "jtag/interface.h"
67 #include "arm_adi_v5.h"
68 #include "arm_coresight.h"
70 #include "transport/transport.h"
71 #include <helper/align.h>
72 #include <helper/jep106.h>
73 #include <helper/time_support.h>
74 #include <helper/list.h>
75 #include <helper/jim-nvp.h>
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, target_addr_t address
)
85 return tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
);
88 /***************************************************************************
90 * DP and MEM-AP register access through APACC and DPACC *
92 ***************************************************************************/
94 static int mem_ap_setup_csw(struct adiv5_ap
*ap
, uint32_t csw
)
96 csw
|= ap
->csw_default
;
98 if (csw
!= ap
->csw_value
) {
99 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
100 int retval
= dap_queue_ap_write(ap
, MEM_AP_REG_CSW(ap
->dap
), csw
);
101 if (retval
!= ERROR_OK
) {
110 static int mem_ap_setup_tar(struct adiv5_ap
*ap
, target_addr_t tar
)
112 if (!ap
->tar_valid
|| tar
!= ap
->tar_value
) {
113 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
114 int retval
= dap_queue_ap_write(ap
, MEM_AP_REG_TAR(ap
->dap
), (uint32_t)(tar
& 0xffffffffUL
));
115 if (retval
== ERROR_OK
&& is_64bit_ap(ap
)) {
116 /* See if bits 63:32 of tar is different from last setting */
117 if (!ap
->tar_valid
|| (ap
->tar_value
>> 32) != (tar
>> 32))
118 retval
= dap_queue_ap_write(ap
, MEM_AP_REG_TAR64(ap
->dap
), (uint32_t)(tar
>> 32));
120 if (retval
!= ERROR_OK
) {
121 ap
->tar_valid
= false;
125 ap
->tar_valid
= true;
130 static int mem_ap_read_tar(struct adiv5_ap
*ap
, target_addr_t
*tar
)
135 int retval
= dap_queue_ap_read(ap
, MEM_AP_REG_TAR(ap
->dap
), &lower
);
136 if (retval
== ERROR_OK
&& is_64bit_ap(ap
))
137 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_TAR64(ap
->dap
), &upper
);
139 if (retval
!= ERROR_OK
) {
140 ap
->tar_valid
= false;
144 retval
= dap_run(ap
->dap
);
145 if (retval
!= ERROR_OK
) {
146 ap
->tar_valid
= false;
150 *tar
= (((target_addr_t
)upper
) << 32) | (target_addr_t
)lower
;
152 ap
->tar_value
= *tar
;
153 ap
->tar_valid
= true;
157 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap
*ap
)
159 switch (ap
->csw_value
& CSW_ADDRINC_MASK
) {
160 case CSW_ADDRINC_SINGLE
:
161 switch (ap
->csw_value
& CSW_SIZE_MASK
) {
177 case CSW_ADDRINC_PACKED
:
183 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
185 static void mem_ap_update_tar_cache(struct adiv5_ap
*ap
)
190 uint32_t inc
= mem_ap_get_tar_increment(ap
);
191 if (inc
>= max_tar_block_size(ap
->tar_autoincr_block
, ap
->tar_value
))
192 ap
->tar_valid
= false;
194 ap
->tar_value
+= inc
;
198 * Queue transactions setting up transfer parameters for the
199 * currently selected MEM-AP.
201 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
202 * initiate data reads or writes using memory or peripheral addresses.
203 * If the CSW is configured for it, the TAR may be automatically
204 * incremented after each transfer.
206 * @param ap The MEM-AP.
207 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
208 * matches the cached value, the register is not changed.
209 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
210 * matches the cached address, the register is not changed.
212 * @return ERROR_OK if the transaction was properly queued, else a fault code.
214 static int mem_ap_setup_transfer(struct adiv5_ap
*ap
, uint32_t csw
, target_addr_t tar
)
217 retval
= mem_ap_setup_csw(ap
, csw
);
218 if (retval
!= ERROR_OK
)
220 retval
= mem_ap_setup_tar(ap
, tar
);
221 if (retval
!= ERROR_OK
)
227 * Asynchronous (queued) read of a word from memory or a system register.
229 * @param ap The MEM-AP to access.
230 * @param address Address of the 32-bit word to read; it must be
231 * readable by the currently selected MEM-AP.
232 * @param value points to where the word will be stored when the
233 * transaction queue is flushed (assuming no errors).
235 * @return ERROR_OK for success. Otherwise a fault code.
237 int mem_ap_read_u32(struct adiv5_ap
*ap
, target_addr_t address
,
242 /* Use banked addressing (REG_BDx) to avoid some link traffic
243 * (updating TAR) when reading several consecutive addresses.
245 retval
= mem_ap_setup_transfer(ap
,
246 CSW_32BIT
| (ap
->csw_value
& CSW_ADDRINC_MASK
),
247 address
& 0xFFFFFFFFFFFFFFF0ull
);
248 if (retval
!= ERROR_OK
)
251 return dap_queue_ap_read(ap
, MEM_AP_REG_BD0(ap
->dap
) | (address
& 0xC), value
);
255 * Synchronous read of a word from memory or a system register.
256 * As a side effect, this flushes any queued transactions.
258 * @param ap The MEM-AP to access.
259 * @param address Address of the 32-bit word to read; it must be
260 * readable by the currently selected MEM-AP.
261 * @param value points to where the result will be stored.
263 * @return ERROR_OK for success; *value holds the result.
264 * Otherwise a fault code.
266 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
, target_addr_t address
,
271 retval
= mem_ap_read_u32(ap
, address
, value
);
272 if (retval
!= ERROR_OK
)
275 return dap_run(ap
->dap
);
279 * Asynchronous (queued) write of a word to memory or a system register.
281 * @param ap The MEM-AP to access.
282 * @param address Address to be written; it must be writable by
283 * the currently selected MEM-AP.
284 * @param value Word that will be written to the address when transaction
285 * queue is flushed (assuming no errors).
287 * @return ERROR_OK for success. Otherwise a fault code.
289 int mem_ap_write_u32(struct adiv5_ap
*ap
, target_addr_t address
,
294 /* Use banked addressing (REG_BDx) to avoid some link traffic
295 * (updating TAR) when writing several consecutive addresses.
297 retval
= mem_ap_setup_transfer(ap
,
298 CSW_32BIT
| (ap
->csw_value
& CSW_ADDRINC_MASK
),
299 address
& 0xFFFFFFFFFFFFFFF0ull
);
300 if (retval
!= ERROR_OK
)
303 return dap_queue_ap_write(ap
, MEM_AP_REG_BD0(ap
->dap
) | (address
& 0xC),
308 * Synchronous write of a word to memory or a system register.
309 * As a side effect, this flushes any queued transactions.
311 * @param ap The MEM-AP to access.
312 * @param address Address to be written; it must be writable by
313 * the currently selected MEM-AP.
314 * @param value Word that will be written.
316 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
318 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
, target_addr_t address
,
321 int retval
= mem_ap_write_u32(ap
, address
, value
);
323 if (retval
!= ERROR_OK
)
326 return dap_run(ap
->dap
);
330 * Queue transactions setting up transfer parameters for the
331 * currently selected MEM-AP. If transfer size or packing
332 * has not been probed, run the queue, read back CSW and check if the requested
333 * transfer mode is supported.
335 * @param ap The MEM-AP.
336 * @param size Transfer width in bytes. Corresponding CSW.Size will be set.
337 * @param address Transfer address, MEM-AP TAR will be set to this value.
338 * @param addrinc TAR will be autoincremented.
339 * @param pack Try to setup packed transfer.
340 * @param this_size Points to a variable set to the size of single transfer
341 * or to 4 when transferring packed bytes or halfwords
343 * @return ERROR_OK if the transaction was properly queued, else a fault code.
345 static int mem_ap_setup_transfer_verify_size_packing(struct adiv5_ap
*ap
,
346 unsigned int size
, target_addr_t address
,
347 bool addrinc
, bool pack
, unsigned int *this_size
)
357 csw_size
= CSW_16BIT
;
360 csw_size
= CSW_32BIT
;
363 csw_size
= CSW_64BIT
;
366 csw_size
= CSW_128BIT
;
369 csw_size
= CSW_256BIT
;
372 LOG_ERROR("Size %u not supported", size
);
373 return ERROR_TARGET_SIZE_NOT_SUPPORTED
;
376 if (!addrinc
|| size
>= 4
377 || (ap
->packed_transfers_probed
&& !ap
->packed_transfers_supported
)
378 || max_tar_block_size(ap
->tar_autoincr_block
, address
) < 4)
381 uint32_t csw_addrinc
= pack
? CSW_ADDRINC_PACKED
:
382 addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
383 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrinc
);
384 if (retval
!= ERROR_OK
)
387 bool do_probe
= !(ap
->csw_size_probed_mask
& size
)
388 || (pack
&& !ap
->packed_transfers_probed
);
390 uint32_t csw_readback
;
391 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CSW(ap
->dap
), &csw_readback
);
392 if (retval
!= ERROR_OK
)
395 retval
= dap_run(ap
->dap
);
396 if (retval
!= ERROR_OK
)
399 bool size_supported
= ((csw_readback
& CSW_SIZE_MASK
) == csw_size
);
400 LOG_DEBUG("AP#0x%" PRIx64
" probed size %u: %s", ap
->ap_num
, size
,
401 size_supported
? "supported" : "not supported");
402 ap
->csw_size_probed_mask
|= size
;
403 if (size_supported
) {
404 ap
->csw_size_supported_mask
|= size
;
405 if (pack
&& !ap
->packed_transfers_probed
) {
406 ap
->packed_transfers_probed
= true;
407 ap
->packed_transfers_supported
=
408 ((csw_readback
& CSW_ADDRINC_MASK
) == csw_addrinc
);
409 LOG_DEBUG("probed packing: %s",
410 ap
->packed_transfers_supported
? "supported" : "not supported");
415 if (!(ap
->csw_size_supported_mask
& size
)) {
416 LOG_ERROR("Size %u not supported", size
);
417 return ERROR_TARGET_SIZE_NOT_SUPPORTED
;
420 if (pack
&& !ap
->packed_transfers_supported
)
421 return ERROR_TARGET_PACKING_NOT_SUPPORTED
;
423 *this_size
= pack
? 4 : size
;
425 return mem_ap_setup_tar(ap
, address
);
429 * Queue transactions setting up transfer parameters for the
430 * currently selected MEM-AP. If transfer size or packing
431 * has not been probed, run the queue, read back CSW and check if the requested
432 * transfer mode is supported.
433 * If packing is not supported fallback and prepare CSW for unpacked transfer.
435 * @param ap The MEM-AP.
436 * @param size Transfer width in bytes. Corresponding CSW.Size will be set.
437 * @param address Transfer address, MEM-AP TAR will be set to this value.
438 * @param addrinc TAR will be autoincremented.
439 * @param pack Try to setup packed transfer.
440 * @param this_size Points to a variable set to the size of single transfer
441 * or to 4 when transferring packed bytes or halfwords
443 * @return ERROR_OK if the transaction was properly queued, else a fault code.
445 static int mem_ap_setup_transfer_verify_size_packing_fallback(struct adiv5_ap
*ap
,
446 unsigned int size
, target_addr_t address
,
447 bool addrinc
, bool pack
, unsigned int *this_size
)
449 int retval
= mem_ap_setup_transfer_verify_size_packing(ap
,
451 addrinc
, pack
, this_size
);
452 if (retval
== ERROR_TARGET_PACKING_NOT_SUPPORTED
) {
453 /* Retry without packing */
454 retval
= mem_ap_setup_transfer_verify_size_packing(ap
,
456 addrinc
, false, this_size
);
462 * Synchronous write of a block of memory, using a specific access size.
464 * @param ap The MEM-AP to access.
465 * @param buffer The data buffer to write. No particular alignment is assumed.
466 * @param size Which access size to use, in bytes. 1, 2, or 4.
467 * If large data extension is available also accepts sizes 8, 16, 32.
468 * @param count The number of writes to do (in size units, not bytes).
469 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
470 * @param addrinc Whether the target address should be increased for each write or not. This
471 * should normally be true, except when writing to e.g. a FIFO.
472 * @return ERROR_OK on success, otherwise an error code.
474 static int mem_ap_write(struct adiv5_ap
*ap
, const uint8_t *buffer
, uint32_t size
, uint32_t count
,
475 target_addr_t address
, bool addrinc
)
477 struct adiv5_dap
*dap
= ap
->dap
;
478 size_t nbytes
= size
* count
;
479 int retval
= ERROR_OK
;
481 /* TI BE-32 Quirks mode:
482 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
483 * size write address bytes written in order
484 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
485 * 2 TAR ^ 2 (val >> 8), (val)
487 * For example, if you attempt to write a single byte to address 0, the processor
488 * will actually write a byte to address 3.
490 * To make writes of size < 4 work as expected, we xor a value with the address before
491 * setting the TAP, and we set the TAP after every transfer rather then relying on
492 * address increment. */
493 target_addr_t ti_be_addr_xor
= 0;
494 target_addr_t ti_be_lane_xor
= 0;
495 if (dap
->ti_be_32_quirks
) {
507 LOG_ERROR("Write more than 32 bits not supported with ti_be_32_quirks");
508 return ERROR_TARGET_SIZE_NOT_SUPPORTED
;
512 if (ap
->unaligned_access_bad
&& (address
% size
!= 0))
513 return ERROR_TARGET_UNALIGNED_ACCESS
;
515 /* Nuvoton NPCX quirks prevent packed writes */
516 bool pack
= !dap
->nu_npcx_quirks
;
519 unsigned int this_size
;
520 retval
= mem_ap_setup_transfer_verify_size_packing_fallback(ap
,
521 size
, address
^ ti_be_addr_xor
,
522 addrinc
, pack
&& nbytes
>= 4, &this_size
);
523 if (retval
!= ERROR_OK
)
526 /* How many source bytes each transfer will consume, and their location in the DRW,
527 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
528 uint32_t drw_byte_idx
= address
;
529 unsigned int drw_ops
= DIV_ROUND_UP(this_size
, 4);
532 uint32_t outvalue
= 0;
533 if (dap
->nu_npcx_quirks
&& this_size
<= 2) {
537 /* Alternate low and high byte to all byte lanes */
538 uint32_t low
= *buffer
++;
539 uint32_t high
= *buffer
++;
540 outvalue
|= low
<< 8 * (drw_byte_idx
++ & 3);
541 outvalue
|= high
<< 8 * (drw_byte_idx
++ & 3);
542 outvalue
|= low
<< 8 * (drw_byte_idx
++ & 3);
543 outvalue
|= high
<< 8 * (drw_byte_idx
& 3);
548 /* Mirror output byte to all byte lanes */
549 uint32_t data
= *buffer
++;
551 outvalue
|= data
<< 8;
552 outvalue
|= data
<< 16;
553 outvalue
|= data
<< 24;
557 unsigned int drw_bytes
= MIN(this_size
, 4);
559 outvalue
|= (uint32_t)*buffer
++ <<
560 8 * ((drw_byte_idx
++ & 3) ^ ti_be_lane_xor
);
563 retval
= dap_queue_ap_write(ap
, MEM_AP_REG_DRW(dap
), outvalue
);
564 if (retval
!= ERROR_OK
)
567 if (retval
!= ERROR_OK
)
570 mem_ap_update_tar_cache(ap
);
573 address
+= this_size
;
576 /* REVISIT: Might want to have a queued version of this function that does not run. */
577 if (retval
== ERROR_OK
)
578 retval
= dap_run(dap
);
580 if (retval
!= ERROR_OK
) {
582 if (mem_ap_read_tar(ap
, &tar
) == ERROR_OK
)
583 LOG_ERROR("Failed to write memory at " TARGET_ADDR_FMT
, tar
);
585 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
592 * Synchronous read of a block of memory, using a specific access size.
594 * @param ap The MEM-AP to access.
595 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
596 * @param size Which access size to use, in bytes. 1, 2, or 4.
597 * If large data extension is available also accepts sizes 8, 16, 32.
598 * @param count The number of reads to do (in size units, not bytes).
599 * @param adr Address to be read; it must be readable by the currently selected MEM-AP.
600 * @param addrinc Whether the target address should be increased after each read or not. This
601 * should normally be true, except when reading from e.g. a FIFO.
602 * @return ERROR_OK on success, otherwise an error code.
604 static int mem_ap_read(struct adiv5_ap
*ap
, uint8_t *buffer
, uint32_t size
, uint32_t count
,
605 target_addr_t adr
, bool addrinc
)
607 struct adiv5_dap
*dap
= ap
->dap
;
608 size_t nbytes
= size
* count
;
609 target_addr_t address
= adr
;
610 int retval
= ERROR_OK
;
612 /* TI BE-32 Quirks mode:
613 * Reads on big-endian TMS570 behave strangely differently than writes.
614 * They read from the physical address requested, but with DRW byte-reversed.
615 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
616 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
617 * so avoid them (ap->packed_transfers is forced to false in mem_ap_init). */
619 if (dap
->ti_be_32_quirks
&& size
> 4) {
620 LOG_ERROR("Read more than 32 bits not supported with ti_be_32_quirks");
621 return ERROR_TARGET_SIZE_NOT_SUPPORTED
;
624 if (ap
->unaligned_access_bad
&& (adr
% size
!= 0))
625 return ERROR_TARGET_UNALIGNED_ACCESS
;
627 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
628 * over-allocation if packed transfers are going to be used, but determining the real need at
629 * this point would be messy. */
630 uint32_t *read_buf
= calloc(count
, MAX(sizeof(uint32_t), size
));
632 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
633 uint32_t *read_ptr
= read_buf
;
635 LOG_ERROR("Failed to allocate read buffer");
639 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
640 * useful bytes it contains, and their location in the word, depends on the type of transfer
643 unsigned int this_size
;
644 retval
= mem_ap_setup_transfer_verify_size_packing_fallback(ap
,
646 addrinc
, nbytes
>= 4, &this_size
);
647 if (retval
!= ERROR_OK
)
651 unsigned int drw_ops
= DIV_ROUND_UP(this_size
, 4);
653 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_DRW(dap
), read_ptr
++);
654 if (retval
!= ERROR_OK
)
660 address
+= this_size
;
662 mem_ap_update_tar_cache(ap
);
665 if (retval
== ERROR_OK
)
666 retval
= dap_run(dap
);
670 nbytes
= size
* count
;
673 /* If something failed, read TAR to find out how much data was successfully read, so we can
674 * at least give the caller what we have. */
675 if (retval
== ERROR_TARGET_SIZE_NOT_SUPPORTED
) {
677 } else if (retval
!= ERROR_OK
) {
679 if (mem_ap_read_tar(ap
, &tar
) == ERROR_OK
) {
680 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
681 LOG_ERROR("Failed to read memory at " TARGET_ADDR_FMT
, tar
);
682 if (nbytes
> tar
- address
)
683 nbytes
= tar
- address
;
685 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
690 target_addr_t ti_be_lane_xor
= dap
->ti_be_32_quirks
? 3 : 0;
692 /* Replay loop to populate caller's buffer from the correct word and byte lane */
694 /* Convert transfers longer than 32-bit on word-at-a-time basis */
695 unsigned int this_size
= MIN(size
, 4);
697 if (size
< 4 && addrinc
&& ap
->packed_transfers_supported
&& nbytes
>= 4
698 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
699 this_size
= 4; /* Packed read of 4 bytes or 2 halfwords */
704 *buffer
++ = *read_ptr
>> 8 * ((address
++ & 3) ^ ti_be_lane_xor
);
705 *buffer
++ = *read_ptr
>> 8 * ((address
++ & 3) ^ ti_be_lane_xor
);
708 *buffer
++ = *read_ptr
>> 8 * ((address
++ & 3) ^ ti_be_lane_xor
);
711 *buffer
++ = *read_ptr
>> 8 * ((address
++ & 3) ^ ti_be_lane_xor
);
722 int mem_ap_read_buf(struct adiv5_ap
*ap
,
723 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
)
725 return mem_ap_read(ap
, buffer
, size
, count
, address
, true);
728 int mem_ap_write_buf(struct adiv5_ap
*ap
,
729 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
)
731 return mem_ap_write(ap
, buffer
, size
, count
, address
, true);
734 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
735 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
)
737 return mem_ap_read(ap
, buffer
, size
, count
, address
, false);
740 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
741 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
)
743 return mem_ap_write(ap
, buffer
, size
, count
, address
, false);
746 /*--------------------------------------------------------------------------*/
749 #define DAP_POWER_DOMAIN_TIMEOUT (10)
751 /*--------------------------------------------------------------------------*/
754 * Invalidate cached DP select and cached TAR and CSW of all APs
756 void dap_invalidate_cache(struct adiv5_dap
*dap
)
758 dap
->select
= 0; /* speculate the first AP access will select AP 0, bank 0 */
759 dap
->select_valid
= false;
760 dap
->select1_valid
= false;
761 dap
->select_dpbanksel_valid
= false;
763 dap
->last_read
= NULL
;
766 for (i
= 0; i
<= DP_APSEL_MAX
; i
++) {
767 /* force csw and tar write on the next mem-ap access */
768 dap
->ap
[i
].tar_valid
= false;
769 dap
->ap
[i
].csw_value
= 0;
774 * Initialize a DAP. This sets up the power domains, prepares the DP
775 * for further use and activates overrun checking.
777 * @param dap The DAP being initialized.
779 int dap_dp_init(struct adiv5_dap
*dap
)
783 LOG_DEBUG("%s", adiv5_dap_name(dap
));
785 dap
->do_reconnect
= false;
786 dap_invalidate_cache(dap
);
789 * Early initialize dap->dp_ctrl_stat.
790 * In jtag mode only, if the following queue run (in dap_dp_poll_register)
791 * fails and sets the sticky error, it will trigger the clearing
792 * of the sticky. Without this initialization system and debug power
793 * would be disabled while clearing the sticky error bit.
795 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
798 * This write operation clears the sticky error bit in jtag mode only and
799 * is ignored in swd mode. It also powers-up system and debug domains in
800 * both jtag and swd modes, if not done before.
802 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
| SSTICKYERR
);
803 if (retval
!= ERROR_OK
)
806 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
807 if (retval
!= ERROR_OK
)
810 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
811 if (retval
!= ERROR_OK
)
814 /* Check that we have debug power domains activated */
815 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
816 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
817 CDBGPWRUPACK
, CDBGPWRUPACK
,
818 DAP_POWER_DOMAIN_TIMEOUT
);
819 if (retval
!= ERROR_OK
)
822 if (!dap
->ignore_syspwrupack
) {
823 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
824 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
825 CSYSPWRUPACK
, CSYSPWRUPACK
,
826 DAP_POWER_DOMAIN_TIMEOUT
);
827 if (retval
!= ERROR_OK
)
831 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
832 if (retval
!= ERROR_OK
)
835 /* With debug power on we can activate OVERRUN checking */
836 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
837 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
838 if (retval
!= ERROR_OK
)
840 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
841 if (retval
!= ERROR_OK
)
844 retval
= dap_run(dap
);
845 if (retval
!= ERROR_OK
)
852 * Initialize a DAP or do reconnect if DAP is not accessible.
854 * @param dap The DAP being initialized.
856 int dap_dp_init_or_reconnect(struct adiv5_dap
*dap
)
858 LOG_DEBUG("%s", adiv5_dap_name(dap
));
861 * Early initialize dap->dp_ctrl_stat.
862 * In jtag mode only, if the following atomic reads fail and set the
863 * sticky error, it will trigger the clearing of the sticky. Without this
864 * initialization system and debug power would be disabled while clearing
865 * the sticky error bit.
867 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
869 dap
->do_reconnect
= false;
871 dap_dp_read_atomic(dap
, DP_CTRL_STAT
, NULL
);
872 if (dap
->do_reconnect
) {
873 /* dap connect calls dap_dp_init() after transport dependent initialization */
874 return dap
->ops
->connect(dap
);
876 return dap_dp_init(dap
);
881 * Initialize a DAP. This sets up the power domains, prepares the DP
882 * for further use, and arranges to use AP #0 for all AP operations
883 * until dap_ap-select() changes that policy.
885 * @param ap The MEM-AP being initialized.
887 int mem_ap_init(struct adiv5_ap
*ap
)
889 /* check that we support packed transfers */
892 struct adiv5_dap
*dap
= ap
->dap
;
894 /* Set ap->cfg_reg before calling mem_ap_setup_transfer(). */
895 /* mem_ap_setup_transfer() needs to know if the MEM_AP supports LPAE. */
896 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CFG(dap
), &cfg
);
897 if (retval
!= ERROR_OK
)
900 retval
= dap_run(dap
);
901 if (retval
!= ERROR_OK
)
905 ap
->tar_valid
= false;
906 ap
->csw_value
= 0; /* force csw and tar write */
908 /* CSW 32-bit size must be supported (IHI 0031F and 0074D). */
909 ap
->csw_size_supported_mask
= BIT(CSW_32BIT
);
910 ap
->csw_size_probed_mask
= BIT(CSW_32BIT
);
912 /* Suppress probing sizes longer than 32 bit if AP has no large data extension */
913 if (!(cfg
& MEM_AP_REG_CFG_LD
))
914 ap
->csw_size_probed_mask
|= BIT(CSW_64BIT
) | BIT(CSW_128BIT
) | BIT(CSW_256BIT
);
916 /* Both IHI 0031F and 0074D state: Implementations that support transfers
917 * smaller than a word must support packed transfers. Unfortunately at least
918 * Cortex-M0 and Cortex-M0+ do not comply with this rule.
919 * Probe for packed transfers except we know they are broken.
920 * Packed transfers on TI BE-32 processors do not work correctly in
922 ap
->packed_transfers_supported
= false;
923 ap
->packed_transfers_probed
= dap
->ti_be_32_quirks
? true : false;
925 /* The ARM ADI spec leaves implementation-defined whether unaligned
926 * memory accesses work, only work partially, or cause a sticky error.
927 * On TI BE-32 processors, reads seem to return garbage in some bytes
928 * and unaligned writes seem to cause a sticky error.
929 * TODO: it would be nice to have a way to detect whether unaligned
930 * operations are supported on other processors. */
931 ap
->unaligned_access_bad
= dap
->ti_be_32_quirks
;
933 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
934 !!(cfg
& MEM_AP_REG_CFG_LD
), !!(cfg
& MEM_AP_REG_CFG_LA
), !!(cfg
& MEM_AP_REG_CFG_BE
));
940 * Put the debug link into SWD mode, if the target supports it.
941 * The link's initial mode may be either JTAG (for example,
942 * with SWJ-DP after reset) or SWD.
944 * Note that targets using the JTAG-DP do not support SWD, and that
945 * some targets which could otherwise support it may have been
946 * configured to disable SWD signaling
948 * @param dap The DAP used
949 * @return ERROR_OK or else a fault code.
951 int dap_to_swd(struct adiv5_dap
*dap
)
953 LOG_DEBUG("Enter SWD mode");
955 return dap_send_sequence(dap
, JTAG_TO_SWD
);
959 * Put the debug link into JTAG mode, if the target supports it.
960 * The link's initial mode may be either SWD or JTAG.
962 * Note that targets implemented with SW-DP do not support JTAG, and
963 * that some targets which could otherwise support it may have been
964 * configured to disable JTAG signaling
966 * @param dap The DAP used
967 * @return ERROR_OK or else a fault code.
969 int dap_to_jtag(struct adiv5_dap
*dap
)
971 LOG_DEBUG("Enter JTAG mode");
973 return dap_send_sequence(dap
, SWD_TO_JTAG
);
976 /* CID interpretation -- see ARM IHI 0029E table B2-7
977 * and ARM IHI 0031E table D1-2.
979 * From 2009/11/25 commit 21378f58b604:
980 * "OptimoDE DESS" is ARM's semicustom DSPish stuff.
981 * Let's keep it as is, for the time being
983 static const char *class_description
[16] = {
984 [0x0] = "Generic verification component",
993 [0x9] = "CoreSight component",
995 [0xB] = "Peripheral Test Block",
997 [0xD] = "OptimoDE DESS", /* see above */
998 [0xE] = "Generic IP component",
999 [0xF] = "CoreLink, PrimeCell or System component",
1002 #define ARCH_ID(architect, archid) ( \
1003 (((architect) << ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT) & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) | \
1004 (((archid) << ARM_CS_C9_DEVARCH_ARCHID_SHIFT) & ARM_CS_C9_DEVARCH_ARCHID_MASK) \
1007 static const struct {
1009 const char *description
;
1010 } class0x9_devarch
[] = {
1011 /* keep same unsorted order as in ARM IHI0029E */
1012 { ARCH_ID(ARM_ID
, 0x0A00), "RAS architecture" },
1013 { ARCH_ID(ARM_ID
, 0x1A01), "Instrumentation Trace Macrocell (ITM) architecture" },
1014 { ARCH_ID(ARM_ID
, 0x1A02), "DWT architecture" },
1015 { ARCH_ID(ARM_ID
, 0x1A03), "Flash Patch and Breakpoint unit (FPB) architecture" },
1016 { ARCH_ID(ARM_ID
, 0x2A04), "Processor debug architecture (ARMv8-M)" },
1017 { ARCH_ID(ARM_ID
, 0x6A05), "Processor debug architecture (ARMv8-R)" },
1018 { ARCH_ID(ARM_ID
, 0x0A10), "PC sample-based profiling" },
1019 { ARCH_ID(ARM_ID
, 0x4A13), "Embedded Trace Macrocell (ETM) architecture" },
1020 { ARCH_ID(ARM_ID
, 0x1A14), "Cross Trigger Interface (CTI) architecture" },
1021 { ARCH_ID(ARM_ID
, 0x6A15), "Processor debug architecture (v8.0-A)" },
1022 { ARCH_ID(ARM_ID
, 0x7A15), "Processor debug architecture (v8.1-A)" },
1023 { ARCH_ID(ARM_ID
, 0x8A15), "Processor debug architecture (v8.2-A)" },
1024 { ARCH_ID(ARM_ID
, 0x2A16), "Processor Performance Monitor (PMU) architecture" },
1025 { ARCH_ID(ARM_ID
, 0x0A17), "Memory Access Port v2 architecture" },
1026 { ARCH_ID(ARM_ID
, 0x0A27), "JTAG Access Port v2 architecture" },
1027 { ARCH_ID(ARM_ID
, 0x0A31), "Basic trace router" },
1028 { ARCH_ID(ARM_ID
, 0x0A37), "Power requestor" },
1029 { ARCH_ID(ARM_ID
, 0x0A47), "Unknown Access Port v2 architecture" },
1030 { ARCH_ID(ARM_ID
, 0x0A50), "HSSTP architecture" },
1031 { ARCH_ID(ARM_ID
, 0x0A63), "System Trace Macrocell (STM) architecture" },
1032 { ARCH_ID(ARM_ID
, 0x0A75), "CoreSight ELA architecture" },
1033 { ARCH_ID(ARM_ID
, 0x0AF7), "CoreSight ROM architecture" },
1036 #define DEVARCH_ID_MASK (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
1037 #define DEVARCH_MEM_AP ARCH_ID(ARM_ID, 0x0A17)
1038 #define DEVARCH_ROM_C_0X9 ARCH_ID(ARM_ID, 0x0AF7)
1039 #define DEVARCH_UNKNOWN_V2 ARCH_ID(ARM_ID, 0x0A47)
1041 static const char *class0x9_devarch_description(uint32_t devarch
)
1043 if (!(devarch
& ARM_CS_C9_DEVARCH_PRESENT
))
1044 return "not present";
1046 for (unsigned int i
= 0; i
< ARRAY_SIZE(class0x9_devarch
); i
++)
1047 if ((devarch
& DEVARCH_ID_MASK
) == class0x9_devarch
[i
].arch_id
)
1048 return class0x9_devarch
[i
].description
;
1053 static const struct {
1055 const char *description
;
1057 { AP_TYPE_JTAG_AP
, "JTAG-AP" },
1058 { AP_TYPE_COM_AP
, "COM-AP" },
1059 { AP_TYPE_AHB3_AP
, "MEM-AP AHB3" },
1060 { AP_TYPE_APB_AP
, "MEM-AP APB2 or APB3" },
1061 { AP_TYPE_AXI_AP
, "MEM-AP AXI3 or AXI4" },
1062 { AP_TYPE_AHB5_AP
, "MEM-AP AHB5" },
1063 { AP_TYPE_APB4_AP
, "MEM-AP APB4" },
1064 { AP_TYPE_AXI5_AP
, "MEM-AP AXI5" },
1065 { AP_TYPE_AHB5H_AP
, "MEM-AP AHB5 with enhanced HPROT" },
1068 static const char *ap_type_to_description(enum ap_type type
)
1070 for (unsigned int i
= 0; i
< ARRAY_SIZE(ap_types
); i
++)
1071 if (type
== ap_types
[i
].type
)
1072 return ap_types
[i
].description
;
1077 bool is_ap_num_valid(struct adiv5_dap
*dap
, uint64_t ap_num
)
1082 /* no autodetection, by now, so uninitialized is equivalent to ADIv5 for
1083 * backward compatibility */
1084 if (!is_adiv6(dap
)) {
1085 if (ap_num
> DP_APSEL_MAX
)
1090 if (is_adiv6(dap
)) {
1091 if (ap_num
& 0x0fffULL
)
1093 if (dap
->asize
!= 0)
1094 if (ap_num
& ((~0ULL) << dap
->asize
))
1103 * This function checks the ID for each access port to find the requested Access Port type
1104 * It also calls dap_get_ap() to increment the AP refcount
1106 int dap_find_get_ap(struct adiv5_dap
*dap
, enum ap_type type_to_find
, struct adiv5_ap
**ap_out
)
1108 if (is_adiv6(dap
)) {
1109 /* TODO: scan the ROM table and detect the AP available */
1110 LOG_DEBUG("On ADIv6 we cannot scan all the possible AP");
1114 /* Maximum AP number is 255 since the SELECT register is 8 bits */
1115 for (unsigned int ap_num
= 0; ap_num
<= DP_APSEL_MAX
; ap_num
++) {
1116 struct adiv5_ap
*ap
= dap_get_ap(dap
, ap_num
);
1120 /* read the IDR register of the Access Port */
1121 uint32_t id_val
= 0;
1123 int retval
= dap_queue_ap_read(ap
, AP_REG_IDR(dap
), &id_val
);
1124 if (retval
!= ERROR_OK
) {
1129 retval
= dap_run(dap
);
1131 /* Reading register for a non-existent AP should not cause an error,
1132 * but just to be sure, try to continue searching if an error does happen.
1134 if (retval
== ERROR_OK
&& (id_val
& AP_TYPE_MASK
) == type_to_find
) {
1135 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32
")",
1136 ap_type_to_description(type_to_find
),
1145 LOG_DEBUG("No %s found", ap_type_to_description(type_to_find
));
1149 static inline bool is_ap_in_use(struct adiv5_ap
*ap
)
1151 return ap
->refcount
> 0 || ap
->config_ap_never_release
;
1154 static struct adiv5_ap
*_dap_get_ap(struct adiv5_dap
*dap
, uint64_t ap_num
)
1156 if (!is_ap_num_valid(dap
, ap_num
)) {
1157 LOG_ERROR("Invalid AP#0x%" PRIx64
, ap_num
);
1160 if (is_adiv6(dap
)) {
1161 for (unsigned int i
= 0; i
<= DP_APSEL_MAX
; i
++) {
1162 struct adiv5_ap
*ap
= &dap
->ap
[i
];
1163 if (is_ap_in_use(ap
) && ap
->ap_num
== ap_num
) {
1168 for (unsigned int i
= 0; i
<= DP_APSEL_MAX
; i
++) {
1169 struct adiv5_ap
*ap
= &dap
->ap
[i
];
1170 if (!is_ap_in_use(ap
)) {
1171 ap
->ap_num
= ap_num
;
1176 LOG_ERROR("No more AP available!");
1181 struct adiv5_ap
*ap
= &dap
->ap
[ap_num
];
1182 ap
->ap_num
= ap_num
;
1187 /* Return AP with specified ap_num. Increment AP refcount */
1188 struct adiv5_ap
*dap_get_ap(struct adiv5_dap
*dap
, uint64_t ap_num
)
1190 struct adiv5_ap
*ap
= _dap_get_ap(dap
, ap_num
);
1192 LOG_DEBUG("refcount AP#0x%" PRIx64
" get %u", ap_num
, ap
->refcount
);
1196 /* Return AP with specified ap_num. Increment AP refcount and keep it non-zero */
1197 struct adiv5_ap
*dap_get_config_ap(struct adiv5_dap
*dap
, uint64_t ap_num
)
1199 struct adiv5_ap
*ap
= _dap_get_ap(dap
, ap_num
);
1201 ap
->config_ap_never_release
= true;
1202 LOG_DEBUG("refcount AP#0x%" PRIx64
" get_config %u", ap_num
, ap
->refcount
);
1207 /* Decrement AP refcount and release the AP when refcount reaches zero */
1208 int dap_put_ap(struct adiv5_ap
*ap
)
1210 if (ap
->refcount
== 0) {
1211 LOG_ERROR("BUG: refcount AP#0x%" PRIx64
" put underflow", ap
->ap_num
);
1217 LOG_DEBUG("refcount AP#0x%" PRIx64
" put %u", ap
->ap_num
, ap
->refcount
);
1218 if (!is_ap_in_use(ap
)) {
1219 /* defaults from dap_instance_init() */
1220 ap
->ap_num
= DP_APSEL_INVALID
;
1221 ap
->memaccess_tck
= 255;
1222 ap
->tar_autoincr_block
= (1 << 10);
1223 ap
->csw_default
= CSW_AHB_DEFAULT
;
1224 ap
->cfg_reg
= MEM_AP_REG_CFG_INVALID
;
1229 static int dap_get_debugbase(struct adiv5_ap
*ap
,
1230 target_addr_t
*dbgbase
, uint32_t *apid
)
1232 struct adiv5_dap
*dap
= ap
->dap
;
1234 uint32_t baseptr_upper
, baseptr_lower
;
1236 if (ap
->cfg_reg
== MEM_AP_REG_CFG_INVALID
) {
1237 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CFG(dap
), &ap
->cfg_reg
);
1238 if (retval
!= ERROR_OK
)
1241 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE(dap
), &baseptr_lower
);
1242 if (retval
!= ERROR_OK
)
1244 retval
= dap_queue_ap_read(ap
, AP_REG_IDR(dap
), apid
);
1245 if (retval
!= ERROR_OK
)
1247 /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
1248 if (ap
->cfg_reg
== MEM_AP_REG_CFG_INVALID
|| is_64bit_ap(ap
)) {
1249 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE64(dap
), &baseptr_upper
);
1250 if (retval
!= ERROR_OK
)
1254 retval
= dap_run(dap
);
1255 if (retval
!= ERROR_OK
)
1258 if (!is_64bit_ap(ap
))
1260 *dbgbase
= (((target_addr_t
)baseptr_upper
) << 32) | baseptr_lower
;
1265 int adiv6_dap_read_baseptr(struct command_invocation
*cmd
, struct adiv5_dap
*dap
, uint64_t *baseptr
)
1267 uint32_t baseptr_lower
, baseptr_upper
= 0;
1270 if (dap
->asize
> 32) {
1271 retval
= dap_queue_dp_read(dap
, DP_BASEPTR1
, &baseptr_upper
);
1272 if (retval
!= ERROR_OK
)
1276 retval
= dap_dp_read_atomic(dap
, DP_BASEPTR0
, &baseptr_lower
);
1277 if (retval
!= ERROR_OK
)
1280 if ((baseptr_lower
& DP_BASEPTR0_VALID
) != DP_BASEPTR0_VALID
) {
1281 command_print(cmd
, "System root table not present");
1285 baseptr_lower
&= ~0x0fff;
1286 *baseptr
= (((uint64_t)baseptr_upper
) << 32) | baseptr_lower
;
1292 * Method to access the CoreSight component.
1293 * On ADIv5, CoreSight components are on the bus behind a MEM-AP.
1294 * On ADIv6, CoreSight components can either be on the bus behind a MEM-AP
1295 * or directly in the AP.
1297 enum coresight_access_mode
{
1302 /** Holds registers and coordinates of a CoreSight component */
1303 struct cs_component_vals
{
1304 struct adiv5_ap
*ap
;
1305 target_addr_t component_base
;
1310 uint32_t devtype_memtype
;
1311 enum coresight_access_mode mode
;
1315 * Helper to read CoreSight component's registers, either on the bus
1316 * behind a MEM-AP or directly in the AP.
1318 * @param mode Method to access the component (AP or MEM-AP).
1319 * @param ap Pointer to AP containing the component.
1320 * @param component_base On MEM-AP access method, base address of the component.
1321 * @param reg Offset of the component's register to read.
1322 * @param value Pointer to the store the read value.
1324 * @return ERROR_OK on success, else a fault code.
1326 static int dap_queue_read_reg(enum coresight_access_mode mode
, struct adiv5_ap
*ap
,
1327 uint64_t component_base
, unsigned int reg
, uint32_t *value
)
1329 if (mode
== CS_ACCESS_AP
)
1330 return dap_queue_ap_read(ap
, reg
, value
);
1332 /* mode == CS_ACCESS_MEM_AP */
1333 return mem_ap_read_u32(ap
, component_base
+ reg
, value
);
1337 * Read the CoreSight registers needed during ROM Table Parsing (RTP).
1339 * @param mode Method to access the component (AP or MEM-AP).
1340 * @param ap Pointer to AP containing the component.
1341 * @param component_base On MEM-AP access method, base address of the component.
1342 * @param v Pointer to the struct holding the value of registers.
1344 * @return ERROR_OK on success, else a fault code.
1346 static int rtp_read_cs_regs(enum coresight_access_mode mode
, struct adiv5_ap
*ap
,
1347 target_addr_t component_base
, struct cs_component_vals
*v
)
1349 assert(IS_ALIGNED(component_base
, ARM_CS_ALIGN
));
1352 uint32_t cid0
, cid1
, cid2
, cid3
;
1353 uint32_t pid0
, pid1
, pid2
, pid3
, pid4
;
1354 int retval
= ERROR_OK
;
1357 v
->component_base
= component_base
;
1360 /* sort by offset to gain speed */
1363 * Registers DEVARCH, DEVID and DEVTYPE are valid on Class 0x9 devices
1364 * only, but are at offset above 0xf00, so can be read on any device
1365 * without triggering error. Read them for eventual use on Class 0x9.
1367 if (retval
== ERROR_OK
)
1368 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_C9_DEVARCH
, &v
->devarch
);
1370 if (retval
== ERROR_OK
)
1371 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_C9_DEVID
, &v
->devid
);
1373 /* Same address as ARM_CS_C1_MEMTYPE */
1374 if (retval
== ERROR_OK
)
1375 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_C9_DEVTYPE
, &v
->devtype_memtype
);
1377 if (retval
== ERROR_OK
)
1378 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_PIDR4
, &pid4
);
1380 if (retval
== ERROR_OK
)
1381 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_PIDR0
, &pid0
);
1382 if (retval
== ERROR_OK
)
1383 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_PIDR1
, &pid1
);
1384 if (retval
== ERROR_OK
)
1385 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_PIDR2
, &pid2
);
1386 if (retval
== ERROR_OK
)
1387 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_PIDR3
, &pid3
);
1389 if (retval
== ERROR_OK
)
1390 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_CIDR0
, &cid0
);
1391 if (retval
== ERROR_OK
)
1392 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_CIDR1
, &cid1
);
1393 if (retval
== ERROR_OK
)
1394 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_CIDR2
, &cid2
);
1395 if (retval
== ERROR_OK
)
1396 retval
= dap_queue_read_reg(mode
, ap
, component_base
, ARM_CS_CIDR3
, &cid3
);
1398 if (retval
== ERROR_OK
)
1399 retval
= dap_run(ap
->dap
);
1400 if (retval
!= ERROR_OK
) {
1401 LOG_DEBUG("Failed read CoreSight registers");
1405 v
->cid
= (cid3
& 0xff) << 24
1406 | (cid2
& 0xff) << 16
1407 | (cid1
& 0xff) << 8
1409 v
->pid
= (uint64_t)(pid4
& 0xff) << 32
1410 | (pid3
& 0xff) << 24
1411 | (pid2
& 0xff) << 16
1412 | (pid1
& 0xff) << 8
1418 /* Part number interpretations are from Cortex
1419 * core specs, the CoreSight components TRM
1420 * (ARM DDI 0314H), CoreSight System Design
1421 * Guide (ARM DGI 0012D) and ETM specs; also
1422 * from chip observation (e.g. TI SDTI).
1425 static const struct dap_part_nums
{
1426 uint16_t designer_id
;
1430 } dap_part_nums
[] = {
1431 { ARM_ID
, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1432 { ARM_ID
, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1433 { ARM_ID
, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1434 { ARM_ID
, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1435 { ARM_ID
, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1436 { ARM_ID
, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1437 { ARM_ID
, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1438 { ARM_ID
, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1439 { ARM_ID
, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1440 { ARM_ID
, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1441 { ARM_ID
, 0x193, "SoC-600 TSGEN", "(Timestamp Generator)", },
1442 { ARM_ID
, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1443 { ARM_ID
, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1444 { ARM_ID
, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1445 { ARM_ID
, 0x492, "Cortex-R52 GICD", "(Distributor)", },
1446 { ARM_ID
, 0x493, "Cortex-R52 GICR", "(Redistributor)", },
1447 { ARM_ID
, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1448 { ARM_ID
, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1449 { ARM_ID
, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1450 { ARM_ID
, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1451 { ARM_ID
, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1452 { ARM_ID
, 0x4aa, "Cortex-A35 ROM", "(v8 Memory Map ROM Table)", },
1453 { ARM_ID
, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1454 { ARM_ID
, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1455 { ARM_ID
, 0x4b8, "Cortex-R52 ROM", "(ROM Table)", },
1456 { ARM_ID
, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1457 { ARM_ID
, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1458 { ARM_ID
, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1459 { ARM_ID
, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1460 { ARM_ID
, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1461 { ARM_ID
, 0x4e0, "Cortex-A35 ROM", "(v7 Memory Map ROM Table)", },
1462 { ARM_ID
, 0x4e4, "Cortex-A76 ROM", "(ROM Table)", },
1463 { ARM_ID
, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1464 { ARM_ID
, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1465 { ARM_ID
, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1466 { ARM_ID
, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1467 { ARM_ID
, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1468 { ARM_ID
, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1469 { ARM_ID
, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1470 { ARM_ID
, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1471 { ARM_ID
, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1472 { ARM_ID
, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1473 { ARM_ID
, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1474 { ARM_ID
, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1475 { ARM_ID
, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1476 { ARM_ID
, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1477 { ARM_ID
, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1478 { ARM_ID
, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1479 { ARM_ID
, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1480 { ARM_ID
, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1481 { ARM_ID
, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1482 { ARM_ID
, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1483 { ARM_ID
, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1484 { ARM_ID
, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1485 { ARM_ID
, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1486 { ARM_ID
, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1487 { ARM_ID
, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1488 { ARM_ID
, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1489 { ARM_ID
, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1490 { ARM_ID
, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1491 { ARM_ID
, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1492 { ARM_ID
, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1493 { ARM_ID
, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1494 { ARM_ID
, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1495 { ARM_ID
, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1496 { ARM_ID
, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1497 { ARM_ID
, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1498 { ARM_ID
, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1499 { ARM_ID
, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1500 { ARM_ID
, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1501 { ARM_ID
, 0x9b6, "Cortex-R52 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1502 { ARM_ID
, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1503 { ARM_ID
, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1504 { ARM_ID
, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1505 { ARM_ID
, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1506 { ARM_ID
, 0x9da, "Cortex-A35 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1507 { ARM_ID
, 0x9e2, "SoC-600 APB-AP", "(APB4 Memory Access Port)", },
1508 { ARM_ID
, 0x9e3, "SoC-600 AHB-AP", "(AHB5 Memory Access Port)", },
1509 { ARM_ID
, 0x9e4, "SoC-600 AXI-AP", "(AXI Memory Access Port)", },
1510 { ARM_ID
, 0x9e5, "SoC-600 APv1 Adapter", "(Access Port v1 Adapter)", },
1511 { ARM_ID
, 0x9e6, "SoC-600 JTAG-AP", "(JTAG Access Port)", },
1512 { ARM_ID
, 0x9e7, "SoC-600 TPIU", "(Trace Port Interface Unit)", },
1513 { ARM_ID
, 0x9e8, "SoC-600 TMC ETR/ETS", "(Embedded Trace Router/Streamer)", },
1514 { ARM_ID
, 0x9e9, "SoC-600 TMC ETB", "(Embedded Trace Buffer)", },
1515 { ARM_ID
, 0x9ea, "SoC-600 TMC ETF", "(Embedded Trace FIFO)", },
1516 { ARM_ID
, 0x9eb, "SoC-600 ATB Funnel", "(Trace Funnel)", },
1517 { ARM_ID
, 0x9ec, "SoC-600 ATB Replicator", "(Trace Replicator)", },
1518 { ARM_ID
, 0x9ed, "SoC-600 CTI", "(Cross Trigger)", },
1519 { ARM_ID
, 0x9ee, "SoC-600 CATU", "(Address Translation Unit)", },
1520 { ARM_ID
, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1521 { ARM_ID
, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1522 { ARM_ID
, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1523 { ARM_ID
, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1524 { ARM_ID
, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1525 { ARM_ID
, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1526 { ARM_ID
, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1527 { ARM_ID
, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1528 { ARM_ID
, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1529 { ARM_ID
, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1530 { ARM_ID
, 0xd04, "Cortex-A35 Debug", "(Debug Unit)", },
1531 { ARM_ID
, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1532 { ARM_ID
, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1533 { ARM_ID
, 0xd0b, "Cortex-A76 Debug", "(Debug Unit)", },
1534 { ARM_ID
, 0xd0c, "Neoverse N1", "(Debug Unit)", },
1535 { ARM_ID
, 0xd13, "Cortex-R52 Debug", "(Debug Unit)", },
1536 { ARM_ID
, 0xd49, "Neoverse N2", "(Debug Unit)", },
1537 { 0x017, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1538 { 0x017, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1539 { 0x017, 0x9af, "MSP432 ROM", "(ROM Table)" },
1540 { 0x01f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1541 { 0x041, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1542 { 0x041, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1543 { 0x041, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1544 { 0x065, 0x000, "SHARC+/Blackfin+", "", },
1545 { 0x070, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1546 { 0x0bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", },
1547 { 0x0bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", },
1548 { 0x0bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", },
1549 { 0x0bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", },
1550 { 0x1eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1551 { 0x1eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1552 { 0x1eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1553 { 0x1eb, 0x302, "Denver Debug", "(Debug Unit)", },
1554 { 0x1eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1557 static const struct dap_part_nums
*pidr_to_part_num(unsigned int designer_id
, unsigned int part_num
)
1559 static const struct dap_part_nums unknown
= {
1560 .type
= "Unrecognized",
1564 for (unsigned int i
= 0; i
< ARRAY_SIZE(dap_part_nums
); i
++)
1565 if (dap_part_nums
[i
].designer_id
== designer_id
&& dap_part_nums
[i
].part_num
== part_num
)
1566 return &dap_part_nums
[i
];
1571 static int dap_devtype_display(struct command_invocation
*cmd
, uint32_t devtype
)
1573 const char *major
= "Reserved", *subtype
= "Reserved";
1574 const unsigned int minor
= (devtype
& ARM_CS_C9_DEVTYPE_SUB_MASK
) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT
;
1575 const unsigned int devtype_major
= (devtype
& ARM_CS_C9_DEVTYPE_MAJOR_MASK
) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT
;
1576 switch (devtype_major
) {
1578 major
= "Miscellaneous";
1584 subtype
= "Validation component";
1589 major
= "Trace Sink";
1606 major
= "Trace Link";
1612 subtype
= "Funnel, router";
1618 subtype
= "FIFO, buffer";
1623 major
= "Trace Source";
1629 subtype
= "Processor";
1635 subtype
= "Engine/Coprocessor";
1641 subtype
= "Software";
1646 major
= "Debug Control";
1652 subtype
= "Trigger Matrix";
1655 subtype
= "Debug Auth";
1658 subtype
= "Power Requestor";
1663 major
= "Debug Logic";
1669 subtype
= "Processor";
1675 subtype
= "Engine/Coprocessor";
1686 major
= "Performance Monitor";
1692 subtype
= "Processor";
1698 subtype
= "Engine/Coprocessor";
1709 command_print(cmd
, "\t\tType is 0x%02x, %s, %s",
1710 devtype
& ARM_CS_C9_DEVTYPE_MASK
,
1716 * Actions/operations to be executed while parsing ROM tables.
1720 * Executed at the start of a new AP, typically to print the AP header.
1721 * @param ap Pointer to AP.
1722 * @param depth The current depth level of ROM table.
1723 * @param priv Pointer to private data.
1724 * @return ERROR_OK on success, else a fault code.
1726 int (*ap_header
)(struct adiv5_ap
*ap
, int depth
, void *priv
);
1728 * Executed at the start of a new MEM-AP, typically to print the MEM-AP header.
1729 * @param retval Error encountered while reading AP.
1730 * @param ap Pointer to AP.
1731 * @param dbgbase Value of MEM-AP Debug Base Address register.
1732 * @param apid Value of MEM-AP IDR Identification Register.
1733 * @param depth The current depth level of ROM table.
1734 * @param priv Pointer to private data.
1735 * @return ERROR_OK on success, else a fault code.
1737 int (*mem_ap_header
)(int retval
, struct adiv5_ap
*ap
, uint64_t dbgbase
,
1738 uint32_t apid
, int depth
, void *priv
);
1740 * Executed when a CoreSight component is parsed, typically to print
1741 * information on the component.
1742 * @param retval Error encountered while reading component's registers.
1743 * @param v Pointer to a container of the component's registers.
1744 * @param depth The current depth level of ROM table.
1745 * @param priv Pointer to private data.
1746 * @return ERROR_OK on success, else a fault code.
1748 int (*cs_component
)(int retval
, struct cs_component_vals
*v
, int depth
, void *priv
);
1750 * Executed for each entry of a ROM table, typically to print the entry
1751 * and information about validity or end-of-table mark.
1752 * @param retval Error encountered while reading the ROM table entry.
1753 * @param depth The current depth level of ROM table.
1754 * @param offset The offset of the entry in the ROM table.
1755 * @param romentry The value of the ROM table entry.
1756 * @param priv Pointer to private data.
1757 * @return ERROR_OK on success, else a fault code.
1759 int (*rom_table_entry
)(int retval
, int depth
, unsigned int offset
, uint64_t romentry
,
1768 * Wrapper around struct rtp_ops::ap_header.
1770 static int rtp_ops_ap_header(const struct rtp_ops
*ops
,
1771 struct adiv5_ap
*ap
, int depth
)
1774 return ops
->ap_header(ap
, depth
, ops
->priv
);
1780 * Wrapper around struct rtp_ops::mem_ap_header.
1781 * Input parameter @a retval is propagated.
1783 static int rtp_ops_mem_ap_header(const struct rtp_ops
*ops
,
1784 int retval
, struct adiv5_ap
*ap
, uint64_t dbgbase
, uint32_t apid
, int depth
)
1786 if (!ops
->mem_ap_header
)
1789 int retval1
= ops
->mem_ap_header(retval
, ap
, dbgbase
, apid
, depth
, ops
->priv
);
1790 if (retval
!= ERROR_OK
)
1796 * Wrapper around struct rtp_ops::cs_component.
1797 * Input parameter @a retval is propagated.
1799 static int rtp_ops_cs_component(const struct rtp_ops
*ops
,
1800 int retval
, struct cs_component_vals
*v
, int depth
)
1802 if (!ops
->cs_component
)
1805 int retval1
= ops
->cs_component(retval
, v
, depth
, ops
->priv
);
1806 if (retval
!= ERROR_OK
)
1812 * Wrapper around struct rtp_ops::rom_table_entry.
1813 * Input parameter @a retval is propagated.
1815 static int rtp_ops_rom_table_entry(const struct rtp_ops
*ops
,
1816 int retval
, int depth
, unsigned int offset
, uint64_t romentry
)
1818 if (!ops
->rom_table_entry
)
1821 int retval1
= ops
->rom_table_entry(retval
, depth
, offset
, romentry
, ops
->priv
);
1822 if (retval
!= ERROR_OK
)
1827 /* Broken ROM tables can have circular references. Stop after a while */
1828 #define ROM_TABLE_MAX_DEPTH (16)
1831 * Value used only during lookup of a CoreSight component in ROM table.
1832 * Return CORESIGHT_COMPONENT_FOUND when component is found.
1833 * Return ERROR_OK when component is not found yet.
1834 * Return any other ERROR_* in case of error.
1836 #define CORESIGHT_COMPONENT_FOUND (1)
1838 static int rtp_ap(const struct rtp_ops
*ops
, struct adiv5_ap
*ap
, int depth
);
1839 static int rtp_cs_component(enum coresight_access_mode mode
, const struct rtp_ops
*ops
,
1840 struct adiv5_ap
*ap
, target_addr_t dbgbase
, bool *is_mem_ap
, int depth
);
1842 static int rtp_rom_loop(enum coresight_access_mode mode
, const struct rtp_ops
*ops
,
1843 struct adiv5_ap
*ap
, target_addr_t base_address
, int depth
,
1844 unsigned int width
, unsigned int max_entries
)
1846 /* ADIv6 AP ROM table provide offset from current AP */
1847 if (mode
== CS_ACCESS_AP
)
1848 base_address
= ap
->ap_num
;
1850 assert(IS_ALIGNED(base_address
, ARM_CS_ALIGN
));
1852 unsigned int offset
= 0;
1853 while (max_entries
--) {
1855 uint32_t romentry_low
, romentry_high
;
1856 target_addr_t component_base
;
1857 unsigned int saved_offset
= offset
;
1859 int retval
= dap_queue_read_reg(mode
, ap
, base_address
, offset
, &romentry_low
);
1861 if (retval
== ERROR_OK
&& width
== 64) {
1862 retval
= dap_queue_read_reg(mode
, ap
, base_address
, offset
, &romentry_high
);
1865 if (retval
== ERROR_OK
)
1866 retval
= dap_run(ap
->dap
);
1867 if (retval
!= ERROR_OK
) {
1868 LOG_DEBUG("Failed read ROM table entry");
1873 romentry
= (((uint64_t)romentry_high
) << 32) | romentry_low
;
1874 component_base
= base_address
+
1875 ((((uint64_t)romentry_high
) << 32) | (romentry_low
& ARM_CS_ROMENTRY_OFFSET_MASK
));
1877 romentry
= romentry_low
;
1878 /* "romentry" is signed */
1879 component_base
= base_address
+ (int32_t)(romentry_low
& ARM_CS_ROMENTRY_OFFSET_MASK
);
1880 if (!is_64bit_ap(ap
))
1881 component_base
= (uint32_t)component_base
;
1883 retval
= rtp_ops_rom_table_entry(ops
, retval
, depth
, saved_offset
, romentry
);
1884 if (retval
!= ERROR_OK
)
1887 if (romentry
== 0) {
1888 /* End of ROM table */
1892 if (!(romentry
& ARM_CS_ROMENTRY_PRESENT
))
1896 if (mode
== CS_ACCESS_AP
) {
1897 struct adiv5_ap
*next_ap
= dap_get_ap(ap
->dap
, component_base
);
1899 LOG_DEBUG("Wrong AP # 0x%" PRIx64
, component_base
);
1902 retval
= rtp_ap(ops
, next_ap
, depth
+ 1);
1903 dap_put_ap(next_ap
);
1905 /* mode == CS_ACCESS_MEM_AP */
1906 retval
= rtp_cs_component(mode
, ops
, ap
, component_base
, NULL
, depth
+ 1);
1908 if (retval
== CORESIGHT_COMPONENT_FOUND
)
1909 return CORESIGHT_COMPONENT_FOUND
;
1910 if (retval
!= ERROR_OK
) {
1911 /* TODO: do we need to send an ABORT before continuing? */
1912 LOG_DEBUG("Ignore error parsing CoreSight component");
1920 static int rtp_cs_component(enum coresight_access_mode mode
, const struct rtp_ops
*ops
,
1921 struct adiv5_ap
*ap
, target_addr_t base_address
, bool *is_mem_ap
, int depth
)
1923 struct cs_component_vals v
;
1926 assert(IS_ALIGNED(base_address
, ARM_CS_ALIGN
));
1931 if (depth
> ROM_TABLE_MAX_DEPTH
)
1932 retval
= ERROR_FAIL
;
1934 retval
= rtp_read_cs_regs(mode
, ap
, base_address
, &v
);
1936 retval
= rtp_ops_cs_component(ops
, retval
, &v
, depth
);
1937 if (retval
== CORESIGHT_COMPONENT_FOUND
)
1938 return CORESIGHT_COMPONENT_FOUND
;
1939 if (retval
!= ERROR_OK
)
1940 return ERROR_OK
; /* Don't abort recursion */
1942 if (!is_valid_arm_cs_cidr(v
.cid
))
1943 return ERROR_OK
; /* Don't abort recursion */
1945 const unsigned int class = ARM_CS_CIDR_CLASS(v
.cid
);
1947 if (class == ARM_CS_CLASS_0X1_ROM_TABLE
)
1948 return rtp_rom_loop(mode
, ops
, ap
, base_address
, depth
, 32, 960);
1950 if (class == ARM_CS_CLASS_0X9_CS_COMPONENT
) {
1951 if ((v
.devarch
& ARM_CS_C9_DEVARCH_PRESENT
) == 0)
1955 if ((v
.devarch
& DEVARCH_ID_MASK
) == DEVARCH_MEM_AP
)
1958 /* SoC-600 APv1 Adapter */
1959 if ((v
.devarch
& DEVARCH_ID_MASK
) == DEVARCH_UNKNOWN_V2
&&
1960 ARM_CS_PIDR_DESIGNER(v
.pid
) == ARM_ID
&&
1961 ARM_CS_PIDR_PART(v
.pid
) == 0x9e5)
1965 /* quit if not ROM table */
1966 if ((v
.devarch
& DEVARCH_ID_MASK
) != DEVARCH_ROM_C_0X9
)
1969 if ((v
.devid
& ARM_CS_C9_DEVID_FORMAT_MASK
) == ARM_CS_C9_DEVID_FORMAT_64BIT
)
1970 return rtp_rom_loop(mode
, ops
, ap
, base_address
, depth
, 64, 256);
1972 return rtp_rom_loop(mode
, ops
, ap
, base_address
, depth
, 32, 512);
1975 /* Class other than 0x1 and 0x9 */
1979 static int rtp_ap(const struct rtp_ops
*ops
, struct adiv5_ap
*ap
, int depth
)
1982 target_addr_t dbgbase
, invalid_entry
;
1984 int retval
= rtp_ops_ap_header(ops
, ap
, depth
);
1985 if (retval
!= ERROR_OK
|| depth
> ROM_TABLE_MAX_DEPTH
)
1986 return ERROR_OK
; /* Don't abort recursion */
1988 if (is_adiv6(ap
->dap
)) {
1990 retval
= rtp_cs_component(CS_ACCESS_AP
, ops
, ap
, 0, &is_mem_ap
, depth
);
1991 if (retval
== CORESIGHT_COMPONENT_FOUND
)
1992 return CORESIGHT_COMPONENT_FOUND
;
1993 if (retval
!= ERROR_OK
)
1994 return ERROR_OK
; /* Don't abort recursion */
1998 /* Continue for an ADIv6 MEM-AP or SoC-600 APv1 Adapter */
2001 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
2002 retval
= dap_get_debugbase(ap
, &dbgbase
, &apid
);
2003 if (retval
!= ERROR_OK
)
2005 retval
= rtp_ops_mem_ap_header(ops
, retval
, ap
, dbgbase
, apid
, depth
);
2006 if (retval
!= ERROR_OK
)
2012 /* NOTE: a MEM-AP may have a single CoreSight component that's
2013 * not a ROM table ... or have no such components at all.
2015 const unsigned int class = (apid
& AP_REG_IDR_CLASS_MASK
) >> AP_REG_IDR_CLASS_SHIFT
;
2017 if (class == AP_REG_IDR_CLASS_MEM_AP
) {
2018 if (is_64bit_ap(ap
))
2019 invalid_entry
= 0xFFFFFFFFFFFFFFFFull
;
2021 invalid_entry
= 0xFFFFFFFFul
;
2023 if (dbgbase
!= invalid_entry
&& (dbgbase
& 0x3) != 0x2) {
2024 retval
= rtp_cs_component(CS_ACCESS_MEM_AP
, ops
, ap
,
2025 dbgbase
& 0xFFFFFFFFFFFFF000ull
, NULL
, depth
);
2026 if (retval
== CORESIGHT_COMPONENT_FOUND
)
2027 return CORESIGHT_COMPONENT_FOUND
;
2034 /* Actions for command "dap info" */
2036 static int dap_info_ap_header(struct adiv5_ap
*ap
, int depth
, void *priv
)
2038 struct command_invocation
*cmd
= priv
;
2040 if (depth
> ROM_TABLE_MAX_DEPTH
) {
2041 command_print(cmd
, "\tTables too deep");
2045 command_print(cmd
, "%sAP # 0x%" PRIx64
, (depth
) ? "\t\t" : "", ap
->ap_num
);
2049 static int dap_info_mem_ap_header(int retval
, struct adiv5_ap
*ap
,
2050 target_addr_t dbgbase
, uint32_t apid
, int depth
, void *priv
)
2052 struct command_invocation
*cmd
= priv
;
2053 target_addr_t invalid_entry
;
2056 if (retval
!= ERROR_OK
) {
2057 command_print(cmd
, "\t\tCan't read MEM-AP, the corresponding core might be turned off");
2061 if (depth
> ROM_TABLE_MAX_DEPTH
) {
2062 command_print(cmd
, "\tTables too deep");
2067 snprintf(tabs
, sizeof(tabs
), "\t[L%02d] ", depth
);
2069 command_print(cmd
, "\t\tAP ID register 0x%8.8" PRIx32
, apid
);
2071 command_print(cmd
, "\t\tNo AP found at this AP#0x%" PRIx64
, ap
->ap_num
);
2075 command_print(cmd
, "\t\tType is %s", ap_type_to_description(apid
& AP_TYPE_MASK
));
2077 /* NOTE: a MEM-AP may have a single CoreSight component that's
2078 * not a ROM table ... or have no such components at all.
2080 const unsigned int class = (apid
& AP_REG_IDR_CLASS_MASK
) >> AP_REG_IDR_CLASS_SHIFT
;
2082 if (class == AP_REG_IDR_CLASS_MEM_AP
) {
2083 if (is_64bit_ap(ap
))
2084 invalid_entry
= 0xFFFFFFFFFFFFFFFFull
;
2086 invalid_entry
= 0xFFFFFFFFul
;
2088 command_print(cmd
, "%sMEM-AP BASE " TARGET_ADDR_FMT
, tabs
, dbgbase
);
2090 if (dbgbase
== invalid_entry
|| (dbgbase
& 0x3) == 0x2) {
2091 command_print(cmd
, "\t\tNo ROM table present");
2094 command_print(cmd
, "\t\tValid ROM table present");
2096 command_print(cmd
, "\t\tROM table in legacy format");
2103 static int dap_info_cs_component(int retval
, struct cs_component_vals
*v
, int depth
, void *priv
)
2105 struct command_invocation
*cmd
= priv
;
2107 if (depth
> ROM_TABLE_MAX_DEPTH
) {
2108 command_print(cmd
, "\tTables too deep");
2112 if (v
->mode
== CS_ACCESS_MEM_AP
)
2113 command_print(cmd
, "\t\tComponent base address " TARGET_ADDR_FMT
, v
->component_base
);
2115 if (retval
!= ERROR_OK
) {
2116 command_print(cmd
, "\t\tCan't read component, the corresponding core might be turned off");
2120 if (!is_valid_arm_cs_cidr(v
->cid
)) {
2121 command_print(cmd
, "\t\tInvalid CID 0x%08" PRIx32
, v
->cid
);
2122 return ERROR_OK
; /* Don't abort recursion */
2125 /* component may take multiple 4K pages */
2126 uint32_t size
= ARM_CS_PIDR_SIZE(v
->pid
);
2128 command_print(cmd
, "\t\tStart address " TARGET_ADDR_FMT
, v
->component_base
- 0x1000 * size
);
2130 command_print(cmd
, "\t\tPeripheral ID 0x%010" PRIx64
, v
->pid
);
2132 const unsigned int part_num
= ARM_CS_PIDR_PART(v
->pid
);
2133 unsigned int designer_id
= ARM_CS_PIDR_DESIGNER(v
->pid
);
2135 if (v
->pid
& ARM_CS_PIDR_JEDEC
) {
2137 command_print(cmd
, "\t\tDesigner is 0x%03x, %s",
2138 designer_id
, jep106_manufacturer(designer_id
));
2140 /* Legacy ASCII ID, clear invalid bits */
2141 designer_id
&= 0x7f;
2142 command_print(cmd
, "\t\tDesigner ASCII code 0x%02x, %s",
2143 designer_id
, designer_id
== 0x41 ? "ARM" : "<unknown>");
2146 const struct dap_part_nums
*partnum
= pidr_to_part_num(designer_id
, part_num
);
2147 command_print(cmd
, "\t\tPart is 0x%03x, %s %s", part_num
, partnum
->type
, partnum
->full
);
2149 const unsigned int class = ARM_CS_CIDR_CLASS(v
->cid
);
2150 command_print(cmd
, "\t\tComponent class is 0x%x, %s", class, class_description
[class]);
2152 if (class == ARM_CS_CLASS_0X1_ROM_TABLE
) {
2153 if (v
->devtype_memtype
& ARM_CS_C1_MEMTYPE_SYSMEM_MASK
)
2154 command_print(cmd
, "\t\tMEMTYPE system memory present on bus");
2156 command_print(cmd
, "\t\tMEMTYPE system memory not present: dedicated debug bus");
2160 if (class == ARM_CS_CLASS_0X9_CS_COMPONENT
) {
2161 dap_devtype_display(cmd
, v
->devtype_memtype
);
2163 /* REVISIT also show ARM_CS_C9_DEVID */
2165 if ((v
->devarch
& ARM_CS_C9_DEVARCH_PRESENT
) == 0)
2168 unsigned int architect_id
= ARM_CS_C9_DEVARCH_ARCHITECT(v
->devarch
);
2169 unsigned int revision
= ARM_CS_C9_DEVARCH_REVISION(v
->devarch
);
2170 command_print(cmd
, "\t\tDev Arch is 0x%08" PRIx32
", %s \"%s\" rev.%u", v
->devarch
,
2171 jep106_manufacturer(architect_id
), class0x9_devarch_description(v
->devarch
),
2174 if ((v
->devarch
& DEVARCH_ID_MASK
) == DEVARCH_ROM_C_0X9
) {
2175 command_print(cmd
, "\t\tType is ROM table");
2177 if (v
->devid
& ARM_CS_C9_DEVID_SYSMEM_MASK
)
2178 command_print(cmd
, "\t\tMEMTYPE system memory present on bus");
2180 command_print(cmd
, "\t\tMEMTYPE system memory not present: dedicated debug bus");
2185 /* Class other than 0x1 and 0x9 */
2189 static int dap_info_rom_table_entry(int retval
, int depth
,
2190 unsigned int offset
, uint64_t romentry
, void *priv
)
2192 struct command_invocation
*cmd
= priv
;
2196 snprintf(tabs
, sizeof(tabs
), "[L%02d] ", depth
);
2198 if (retval
!= ERROR_OK
) {
2199 command_print(cmd
, "\t%sROMTABLE[0x%x] Read error", tabs
, offset
);
2200 command_print(cmd
, "\t\tUnable to continue");
2201 command_print(cmd
, "\t%s\tStop parsing of ROM table", tabs
);
2205 command_print(cmd
, "\t%sROMTABLE[0x%x] = 0x%08" PRIx64
,
2206 tabs
, offset
, romentry
);
2208 if (romentry
== 0) {
2209 command_print(cmd
, "\t%s\tEnd of ROM table", tabs
);
2213 if (!(romentry
& ARM_CS_ROMENTRY_PRESENT
)) {
2214 command_print(cmd
, "\t\tComponent not present");
2221 int dap_info_command(struct command_invocation
*cmd
, struct adiv5_ap
*ap
)
2223 struct rtp_ops dap_info_ops
= {
2224 .ap_header
= dap_info_ap_header
,
2225 .mem_ap_header
= dap_info_mem_ap_header
,
2226 .cs_component
= dap_info_cs_component
,
2227 .rom_table_entry
= dap_info_rom_table_entry
,
2231 return rtp_ap(&dap_info_ops
, ap
, 0);
2234 /* Actions for dap_lookup_cs_component() */
2236 struct dap_lookup_data
{
2241 uint64_t component_base
;
2245 static int dap_lookup_cs_component_cs_component(int retval
,
2246 struct cs_component_vals
*v
, int depth
, void *priv
)
2248 struct dap_lookup_data
*lookup
= priv
;
2250 if (retval
!= ERROR_OK
)
2253 if (!is_valid_arm_cs_cidr(v
->cid
))
2256 const unsigned int class = ARM_CS_CIDR_CLASS(v
->cid
);
2257 if (class != ARM_CS_CLASS_0X9_CS_COMPONENT
)
2260 if ((v
->devtype_memtype
& ARM_CS_C9_DEVTYPE_MASK
) != lookup
->type
)
2264 /* search for next one */
2270 lookup
->component_base
= v
->component_base
;
2271 lookup
->ap_num
= v
->ap
->ap_num
;
2272 return CORESIGHT_COMPONENT_FOUND
;
2275 int dap_lookup_cs_component(struct adiv5_ap
*ap
, uint8_t type
,
2276 target_addr_t
*addr
, int32_t core_id
)
2278 struct dap_lookup_data lookup
= {
2282 struct rtp_ops dap_lookup_cs_component_ops
= {
2284 .mem_ap_header
= NULL
,
2285 .cs_component
= dap_lookup_cs_component_cs_component
,
2286 .rom_table_entry
= NULL
,
2290 int retval
= rtp_ap(&dap_lookup_cs_component_ops
, ap
, 0);
2291 if (retval
== CORESIGHT_COMPONENT_FOUND
) {
2292 if (lookup
.ap_num
!= ap
->ap_num
) {
2293 /* TODO: handle search from root ROM table */
2294 LOG_DEBUG("CS lookup ended in AP # 0x%" PRIx64
". Ignore it", lookup
.ap_num
);
2295 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2297 LOG_DEBUG("CS lookup found at 0x%" PRIx64
, lookup
.component_base
);
2298 *addr
= lookup
.component_base
;
2301 if (retval
!= ERROR_OK
) {
2302 LOG_DEBUG("CS lookup error %d", retval
);
2305 LOG_DEBUG("CS lookup not found");
2306 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2309 enum adiv5_cfg_param
{
2313 CFG_CTIBASE
, /* DEPRECATED */
2316 static const struct jim_nvp nvp_config_opts
[] = {
2317 { .name
= "-dap", .value
= CFG_DAP
},
2318 { .name
= "-ap-num", .value
= CFG_AP_NUM
},
2319 { .name
= "-baseaddr", .value
= CFG_BASEADDR
},
2320 { .name
= "-ctibase", .value
= CFG_CTIBASE
}, /* DEPRECATED */
2321 { .name
= NULL
, .value
= -1 }
2324 static int adiv5_jim_spot_configure(struct jim_getopt_info
*goi
,
2325 struct adiv5_dap
**dap_p
, uint64_t *ap_num_p
, uint32_t *base_p
)
2327 assert(dap_p
&& ap_num_p
);
2332 Jim_SetEmptyResult(goi
->interp
);
2335 int e
= jim_nvp_name2value_obj(goi
->interp
, nvp_config_opts
,
2338 return JIM_CONTINUE
;
2340 /* base_p can be NULL, then '-baseaddr' option is treated as unknown */
2341 if (!base_p
&& (n
->value
== CFG_BASEADDR
|| n
->value
== CFG_CTIBASE
))
2342 return JIM_CONTINUE
;
2344 e
= jim_getopt_obj(goi
, NULL
);
2350 if (goi
->isconfigure
) {
2352 struct adiv5_dap
*dap
;
2353 e
= jim_getopt_obj(goi
, &o_t
);
2356 dap
= dap_instance_by_jim_obj(goi
->interp
, o_t
);
2358 Jim_SetResultString(goi
->interp
, "DAP name invalid!", -1);
2361 if (*dap_p
&& *dap_p
!= dap
) {
2362 Jim_SetResultString(goi
->interp
,
2363 "DAP assignment cannot be changed!", -1);
2371 Jim_SetResultString(goi
->interp
, "DAP not configured", -1);
2374 Jim_SetResultString(goi
->interp
, adiv5_dap_name(*dap_p
), -1);
2379 if (goi
->isconfigure
) {
2380 /* jim_wide is a signed 64 bits int, ap_num is unsigned with max 52 bits */
2382 e
= jim_getopt_wide(goi
, &ap_num
);
2385 /* we still don't know dap->adi_version */
2386 if (ap_num
< 0 || (ap_num
> DP_APSEL_MAX
&& (ap_num
& 0xfff))) {
2387 Jim_SetResultString(goi
->interp
, "Invalid AP number!", -1);
2394 if (*ap_num_p
== DP_APSEL_INVALID
) {
2395 Jim_SetResultString(goi
->interp
, "AP number not configured", -1);
2398 Jim_SetResult(goi
->interp
, Jim_NewIntObj(goi
->interp
, *ap_num_p
));
2403 LOG_WARNING("DEPRECATED! use \'-baseaddr' not \'-ctibase\'");
2406 if (goi
->isconfigure
) {
2408 e
= jim_getopt_wide(goi
, &base
);
2411 *base_p
= (uint32_t)base
;
2415 Jim_SetResult(goi
->interp
, Jim_NewIntObj(goi
->interp
, *base_p
));
2423 Jim_WrongNumArgs(goi
->interp
, goi
->argc
, goi
->argv
, "NO PARAMS");
2427 int adiv5_jim_configure(struct target
*target
, struct jim_getopt_info
*goi
)
2429 struct adiv5_private_config
*pc
;
2432 pc
= (struct adiv5_private_config
*)target
->private_config
;
2434 pc
= calloc(1, sizeof(struct adiv5_private_config
));
2436 LOG_ERROR("Out of memory");
2439 pc
->ap_num
= DP_APSEL_INVALID
;
2440 target
->private_config
= pc
;
2443 target
->has_dap
= true;
2445 e
= adiv5_jim_spot_configure(goi
, &pc
->dap
, &pc
->ap_num
, NULL
);
2449 if (pc
->dap
&& !target
->dap_configured
) {
2450 if (target
->tap_configured
) {
2452 Jim_SetResultString(goi
->interp
,
2453 "-chain-position and -dap configparams are mutually exclusive!", -1);
2456 target
->tap
= pc
->dap
->tap
;
2457 target
->dap_configured
= true;
2463 int adiv5_verify_config(struct adiv5_private_config
*pc
)
2474 int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot
*cfg
,
2475 struct jim_getopt_info
*goi
)
2477 return adiv5_jim_spot_configure(goi
, &cfg
->dap
, &cfg
->ap_num
, &cfg
->base
);
2480 int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot
*p
)
2483 p
->ap_num
= DP_APSEL_INVALID
;
2488 COMMAND_HANDLER(handle_dap_info_command
)
2490 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2498 if (!strcmp(CMD_ARGV
[0], "root")) {
2499 if (!is_adiv6(dap
)) {
2500 command_print(CMD
, "Option \"root\" not allowed with ADIv5 DAP");
2501 return ERROR_COMMAND_ARGUMENT_INVALID
;
2503 int retval
= adiv6_dap_read_baseptr(CMD
, dap
, &apsel
);
2504 if (retval
!= ERROR_OK
) {
2505 command_print(CMD
, "Failed reading DAP baseptr");
2510 COMMAND_PARSE_NUMBER(u64
, CMD_ARGV
[0], apsel
);
2511 if (!is_ap_num_valid(dap
, apsel
)) {
2512 command_print(CMD
, "Invalid AP number");
2513 return ERROR_COMMAND_ARGUMENT_INVALID
;
2517 return ERROR_COMMAND_SYNTAX_ERROR
;
2520 struct adiv5_ap
*ap
= dap_get_ap(dap
, apsel
);
2522 command_print(CMD
, "Cannot get AP");
2526 int retval
= dap_info_command(CMD
, ap
);
2531 COMMAND_HANDLER(dap_baseaddr_command
)
2533 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2535 uint32_t baseaddr_lower
, baseaddr_upper
;
2536 struct adiv5_ap
*ap
;
2537 target_addr_t baseaddr
;
2547 COMMAND_PARSE_NUMBER(u64
, CMD_ARGV
[0], apsel
);
2548 if (!is_ap_num_valid(dap
, apsel
)) {
2549 command_print(CMD
, "Invalid AP number");
2550 return ERROR_COMMAND_ARGUMENT_INVALID
;
2554 return ERROR_COMMAND_SYNTAX_ERROR
;
2557 /* NOTE: assumes we're talking to a MEM-AP, which
2558 * has a base address. There are other kinds of AP,
2559 * though they're not common for now. This should
2560 * use the ID register to verify it's a MEM-AP.
2563 ap
= dap_get_ap(dap
, apsel
);
2565 command_print(CMD
, "Cannot get AP");
2569 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE(dap
), &baseaddr_lower
);
2571 if (retval
== ERROR_OK
&& ap
->cfg_reg
== MEM_AP_REG_CFG_INVALID
)
2572 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CFG(dap
), &ap
->cfg_reg
);
2574 if (retval
== ERROR_OK
&& (ap
->cfg_reg
== MEM_AP_REG_CFG_INVALID
|| is_64bit_ap(ap
))) {
2575 /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
2576 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE64(dap
), &baseaddr_upper
);
2579 if (retval
== ERROR_OK
)
2580 retval
= dap_run(dap
);
2582 if (retval
!= ERROR_OK
)
2585 if (is_64bit_ap(ap
)) {
2586 baseaddr
= (((target_addr_t
)baseaddr_upper
) << 32) | baseaddr_lower
;
2587 command_print(CMD
, "0x%016" PRIx64
, baseaddr
);
2589 command_print(CMD
, "0x%08" PRIx32
, baseaddr_lower
);
2594 COMMAND_HANDLER(dap_memaccess_command
)
2596 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2597 struct adiv5_ap
*ap
;
2598 uint32_t memaccess_tck
;
2602 ap
= dap_get_ap(dap
, dap
->apsel
);
2604 command_print(CMD
, "Cannot get AP");
2607 memaccess_tck
= ap
->memaccess_tck
;
2610 ap
= dap_get_config_ap(dap
, dap
->apsel
);
2612 command_print(CMD
, "Cannot get AP");
2615 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
2616 ap
->memaccess_tck
= memaccess_tck
;
2619 return ERROR_COMMAND_SYNTAX_ERROR
;
2624 command_print(CMD
, "memory bus access delay set to %" PRIu32
" tck",
2630 COMMAND_HANDLER(dap_apsel_command
)
2632 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2637 command_print(CMD
, "0x%" PRIx64
, dap
->apsel
);
2640 COMMAND_PARSE_NUMBER(u64
, CMD_ARGV
[0], apsel
);
2641 if (!is_ap_num_valid(dap
, apsel
)) {
2642 command_print(CMD
, "Invalid AP number");
2643 return ERROR_COMMAND_ARGUMENT_INVALID
;
2647 return ERROR_COMMAND_SYNTAX_ERROR
;
2654 COMMAND_HANDLER(dap_apcsw_command
)
2656 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2657 struct adiv5_ap
*ap
;
2658 uint32_t csw_val
, csw_mask
;
2662 ap
= dap_get_ap(dap
, dap
->apsel
);
2664 command_print(CMD
, "Cannot get AP");
2667 command_print(CMD
, "AP#0x%" PRIx64
" selected, csw 0x%8.8" PRIx32
,
2668 dap
->apsel
, ap
->csw_default
);
2671 if (strcmp(CMD_ARGV
[0], "default") == 0)
2672 csw_val
= CSW_AHB_DEFAULT
;
2674 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], csw_val
);
2676 if (csw_val
& (CSW_SIZE_MASK
| CSW_ADDRINC_MASK
)) {
2677 LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
2678 return ERROR_COMMAND_ARGUMENT_INVALID
;
2680 ap
= dap_get_config_ap(dap
, dap
->apsel
);
2682 command_print(CMD
, "Cannot get AP");
2685 ap
->csw_default
= csw_val
;
2688 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], csw_val
);
2689 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], csw_mask
);
2690 if (csw_mask
& (CSW_SIZE_MASK
| CSW_ADDRINC_MASK
)) {
2691 LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
2692 return ERROR_COMMAND_ARGUMENT_INVALID
;
2694 ap
= dap_get_config_ap(dap
, dap
->apsel
);
2696 command_print(CMD
, "Cannot get AP");
2699 ap
->csw_default
= (ap
->csw_default
& ~csw_mask
) | (csw_val
& csw_mask
);
2702 return ERROR_COMMAND_SYNTAX_ERROR
;
2711 COMMAND_HANDLER(dap_apid_command
)
2713 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2723 COMMAND_PARSE_NUMBER(u64
, CMD_ARGV
[0], apsel
);
2724 if (!is_ap_num_valid(dap
, apsel
)) {
2725 command_print(CMD
, "Invalid AP number");
2726 return ERROR_COMMAND_ARGUMENT_INVALID
;
2730 return ERROR_COMMAND_SYNTAX_ERROR
;
2733 struct adiv5_ap
*ap
= dap_get_ap(dap
, apsel
);
2735 command_print(CMD
, "Cannot get AP");
2738 retval
= dap_queue_ap_read(ap
, AP_REG_IDR(dap
), &apid
);
2739 if (retval
!= ERROR_OK
) {
2743 retval
= dap_run(dap
);
2745 if (retval
!= ERROR_OK
)
2748 command_print(CMD
, "0x%8.8" PRIx32
, apid
);
2753 COMMAND_HANDLER(dap_apreg_command
)
2755 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2757 uint32_t reg
, value
;
2760 if (CMD_ARGC
< 2 || CMD_ARGC
> 3)
2761 return ERROR_COMMAND_SYNTAX_ERROR
;
2763 COMMAND_PARSE_NUMBER(u64
, CMD_ARGV
[0], apsel
);
2764 if (!is_ap_num_valid(dap
, apsel
)) {
2765 command_print(CMD
, "Invalid AP number");
2766 return ERROR_COMMAND_ARGUMENT_INVALID
;
2769 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg
);
2770 if (is_adiv6(dap
)) {
2771 if (reg
>= 4096 || (reg
& 3)) {
2772 command_print(CMD
, "Invalid reg value (should be less than 4096 and 4 bytes aligned)");
2773 return ERROR_COMMAND_ARGUMENT_INVALID
;
2775 } else { /* ADI version 5 */
2776 if (reg
>= 256 || (reg
& 3)) {
2777 command_print(CMD
, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
2778 return ERROR_COMMAND_ARGUMENT_INVALID
;
2782 struct adiv5_ap
*ap
= dap_get_ap(dap
, apsel
);
2784 command_print(CMD
, "Cannot get AP");
2788 if (CMD_ARGC
== 3) {
2789 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
2790 /* see if user supplied register address is a match for the CSW or TAR register */
2791 if (reg
== MEM_AP_REG_CSW(dap
)) {
2792 ap
->csw_value
= 0; /* invalid, in case write fails */
2793 retval
= dap_queue_ap_write(ap
, reg
, value
);
2794 if (retval
== ERROR_OK
)
2795 ap
->csw_value
= value
;
2796 } else if (reg
== MEM_AP_REG_TAR(dap
)) {
2797 retval
= dap_queue_ap_write(ap
, reg
, value
);
2798 if (retval
== ERROR_OK
)
2799 ap
->tar_value
= (ap
->tar_value
& ~0xFFFFFFFFull
) | value
;
2801 /* To track independent writes to TAR and TAR64, two tar_valid flags */
2802 /* should be used. To keep it simple, tar_valid is only invalidated on a */
2803 /* write fail. This approach causes a later re-write of the TAR and TAR64 */
2804 /* if tar_valid is false. */
2805 ap
->tar_valid
= false;
2807 } else if (reg
== MEM_AP_REG_TAR64(dap
)) {
2808 retval
= dap_queue_ap_write(ap
, reg
, value
);
2809 if (retval
== ERROR_OK
)
2810 ap
->tar_value
= (ap
->tar_value
& 0xFFFFFFFFull
) | (((target_addr_t
)value
) << 32);
2812 /* See above comment for the MEM_AP_REG_TAR failed write case */
2813 ap
->tar_valid
= false;
2816 retval
= dap_queue_ap_write(ap
, reg
, value
);
2819 retval
= dap_queue_ap_read(ap
, reg
, &value
);
2821 if (retval
== ERROR_OK
)
2822 retval
= dap_run(dap
);
2826 if (retval
!= ERROR_OK
)
2830 command_print(CMD
, "0x%08" PRIx32
, value
);
2835 COMMAND_HANDLER(dap_dpreg_command
)
2837 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2838 uint32_t reg
, value
;
2841 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
2842 return ERROR_COMMAND_SYNTAX_ERROR
;
2844 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], reg
);
2845 if (reg
>= 256 || (reg
& 3)) {
2846 command_print(CMD
, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
2847 return ERROR_COMMAND_ARGUMENT_INVALID
;
2850 if (CMD_ARGC
== 2) {
2851 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
2852 retval
= dap_queue_dp_write(dap
, reg
, value
);
2854 retval
= dap_queue_dp_read(dap
, reg
, &value
);
2856 if (retval
== ERROR_OK
)
2857 retval
= dap_run(dap
);
2859 if (retval
!= ERROR_OK
)
2863 command_print(CMD
, "0x%08" PRIx32
, value
);
2868 COMMAND_HANDLER(dap_ti_be_32_quirks_command
)
2870 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2871 return CALL_COMMAND_HANDLER(handle_command_parse_bool
, &dap
->ti_be_32_quirks
,
2872 "TI BE-32 quirks mode");
2875 COMMAND_HANDLER(dap_nu_npcx_quirks_command
)
2877 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
2878 return CALL_COMMAND_HANDLER(handle_command_parse_bool
, &dap
->nu_npcx_quirks
,
2879 "Nuvoton NPCX quirks mode");
2882 const struct command_registration dap_instance_commands
[] = {
2885 .handler
= handle_dap_info_command
,
2886 .mode
= COMMAND_EXEC
,
2887 .help
= "display ROM table for specified MEM-AP (default currently selected AP) "
2888 "or the ADIv6 root ROM table",
2889 .usage
= "[ap_num | 'root']",
2893 .handler
= dap_apsel_command
,
2894 .mode
= COMMAND_ANY
,
2895 .help
= "Set the currently selected AP (default 0) "
2896 "and display the result",
2897 .usage
= "[ap_num]",
2901 .handler
= dap_apcsw_command
,
2902 .mode
= COMMAND_ANY
,
2903 .help
= "Set CSW default bits",
2904 .usage
= "[value [mask]]",
2909 .handler
= dap_apid_command
,
2910 .mode
= COMMAND_EXEC
,
2911 .help
= "return ID register from AP "
2912 "(default currently selected AP)",
2913 .usage
= "[ap_num]",
2917 .handler
= dap_apreg_command
,
2918 .mode
= COMMAND_EXEC
,
2919 .help
= "read/write a register from AP "
2920 "(reg is byte address of a word register, like 0 4 8...)",
2921 .usage
= "ap_num reg [value]",
2925 .handler
= dap_dpreg_command
,
2926 .mode
= COMMAND_EXEC
,
2927 .help
= "read/write a register from DP "
2928 "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)",
2929 .usage
= "reg [value]",
2933 .handler
= dap_baseaddr_command
,
2934 .mode
= COMMAND_EXEC
,
2935 .help
= "return debug base address from MEM-AP "
2936 "(default currently selected AP)",
2937 .usage
= "[ap_num]",
2940 .name
= "memaccess",
2941 .handler
= dap_memaccess_command
,
2942 .mode
= COMMAND_EXEC
,
2943 .help
= "set/get number of extra tck for MEM-AP memory "
2944 "bus access [0-255]",
2945 .usage
= "[cycles]",
2948 .name
= "ti_be_32_quirks",
2949 .handler
= dap_ti_be_32_quirks_command
,
2950 .mode
= COMMAND_CONFIG
,
2951 .help
= "set/get quirks mode for TI TMS450/TMS570 processors",
2952 .usage
= "[enable]",
2955 .name
= "nu_npcx_quirks",
2956 .handler
= dap_nu_npcx_quirks_command
,
2957 .mode
= COMMAND_CONFIG
,
2958 .help
= "set/get quirks mode for Nuvoton NPCX controllers",
2959 .usage
= "[enable]",
2961 COMMAND_REGISTRATION_DONE