1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifndef ARMV7M_COMMON_H
27 #define ARMV7M_COMMON_H
29 #include <target/arm_adi_v5.h>
30 #include <target/armv4_5.h>
32 /* define for enabling armv7 gdb workarounds */
34 #define ARMV7_GDB_HACKS
39 ARMV7M_MODE_THREAD
= 0,
40 ARMV7M_MODE_USER_THREAD
= 1,
41 ARMV7M_MODE_HANDLER
= 2,
45 extern char *armv7m_mode_strings
[];
49 ARMV7M_REGISTER_CORE_GP
,
50 ARMV7M_REGISTER_CORE_SP
,
51 ARMV7M_REGISTER_MEMMAP
54 char *armv7m_exception_string(int number
);
56 /* offsets into armv7m core register cache */
59 /* for convenience, the first set of indices match
60 * the Cortex-M3 DCRSR selectors
86 /* this next set of indices is arbitrary */
93 #define ARMV7M_COMMON_MAGIC 0x2A452A45
98 struct reg_cache
*core_cache
;
99 enum armv7m_mode core_mode
;
100 int exception_number
;
101 struct swjdp_common swjdp_info
;
103 /* Direct processor core register read and writes */
104 int (*load_core_reg_u32
)(struct target
*target
, enum armv7m_regtype type
, uint32_t num
, uint32_t *value
);
105 int (*store_core_reg_u32
)(struct target
*target
, enum armv7m_regtype type
, uint32_t num
, uint32_t value
);
106 /* register cache to processor synchronization */
107 int (*read_core_reg
)(struct target
*target
, unsigned num
);
108 int (*write_core_reg
)(struct target
*target
, unsigned num
);
110 int (*examine_debug_reason
)(struct target
*target
);
111 void (*post_debug_entry
)(struct target
*target
);
113 void (*pre_restore_context
)(struct target
*target
);
114 void (*post_restore_context
)(struct target
*target
);
117 static inline struct armv7m_common
*
118 target_to_armv7m(struct target
*target
)
120 return target
->arch_info
;
123 struct armv7m_algorithm
127 enum armv7m_mode core_mode
;
130 struct armv7m_core_reg
133 enum armv7m_regtype type
;
134 struct target
*target
;
135 struct armv7m_common
*armv7m_common
;
138 struct reg_cache
*armv7m_build_reg_cache(struct target
*target
);
139 enum armv7m_mode
armv7m_number_to_mode(int number
);
140 int armv7m_mode_to_number(enum armv7m_mode mode
);
142 int armv7m_arch_state(struct target
*target
);
143 int armv7m_get_gdb_reg_list(struct target
*target
,
144 struct reg
**reg_list
[], int *reg_list_size
);
146 int armv7m_init_arch_info(struct target
*target
, struct armv7m_common
*armv7m
);
148 int armv7m_run_algorithm(struct target
*target
,
149 int num_mem_params
, struct mem_param
*mem_params
,
150 int num_reg_params
, struct reg_param
*reg_params
,
151 uint32_t entry_point
, uint32_t exit_point
,
152 int timeout_ms
, void *arch_info
);
154 int armv7m_invalidate_core_regs(struct target
*target
);
156 int armv7m_restore_context(struct target
*target
);
158 int armv7m_checksum_memory(struct target
*target
,
159 uint32_t address
, uint32_t count
, uint32_t* checksum
);
160 int armv7m_blank_check_memory(struct target
*target
,
161 uint32_t address
, uint32_t count
, uint32_t* blank
);
163 extern const struct command_registration armv7m_command_handlers
[];
165 #endif /* ARMV7M_H */