src/target/armv7m.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2005 by Dominic Rath                                    *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  *                                                                         *
   7  *   Copyright (C) 2006 by Magnus Lundin                                   *
   8  *   lundin@mlu.mine.nu                                                    *
   9  *                                                                         *
  10  *   Copyright (C) 2008 by Spencer Oliver                                  *
  11  *   spen@spen-soft.co.uk                                                  *
  12  ***************************************************************************/
  13
  14 #ifndef OPENOCD_TARGET_ARMV7M_H
  15 #define OPENOCD_TARGET_ARMV7M_H
  16
  17 #include "arm.h"
  18 #include "armv7m_trace.h"
  19
  20 struct adiv5_ap;
  21
  22 extern const int armv7m_psp_reg_map[];
  23 extern const int armv7m_msp_reg_map[];
  24
  25 const char *armv7m_exception_string(int number);
  26
  27 /* Cortex-M DCRSR.REGSEL selectors */
  28 enum {
  29         ARMV7M_REGSEL_R0,
  30         ARMV7M_REGSEL_R1,
  31         ARMV7M_REGSEL_R2,
  32         ARMV7M_REGSEL_R3,
  33
  34         ARMV7M_REGSEL_R4,
  35         ARMV7M_REGSEL_R5,
  36         ARMV7M_REGSEL_R6,
  37         ARMV7M_REGSEL_R7,
  38
  39         ARMV7M_REGSEL_R8,
  40         ARMV7M_REGSEL_R9,
  41         ARMV7M_REGSEL_R10,
  42         ARMV7M_REGSEL_R11,
  43
  44         ARMV7M_REGSEL_R12,
  45         ARMV7M_REGSEL_R13,
  46         ARMV7M_REGSEL_R14,
  47         ARMV7M_REGSEL_PC = 15,
  48
  49         ARMV7M_REGSEL_XPSR = 16,
  50         ARMV7M_REGSEL_MSP,
  51         ARMV7M_REGSEL_PSP,
  52
  53         ARMV8M_REGSEL_MSP_NS = 0x18,
  54         ARMV8M_REGSEL_PSP_NS,
  55         ARMV8M_REGSEL_MSP_S,
  56         ARMV8M_REGSEL_PSP_S,
  57         ARMV8M_REGSEL_MSPLIM_S,
  58         ARMV8M_REGSEL_PSPLIM_S,
  59         ARMV8M_REGSEL_MSPLIM_NS,
  60         ARMV8M_REGSEL_PSPLIM_NS,
  61
  62         ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL = 0x14,
  63         ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S = 0x22,
  64         ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS = 0x23,
  65         ARMV7M_REGSEL_FPSCR = 0x21,
  66
  67         /* 32bit Floating-point registers */
  68         ARMV7M_REGSEL_S0 = 0x40,
  69         ARMV7M_REGSEL_S1,
  70         ARMV7M_REGSEL_S2,
  71         ARMV7M_REGSEL_S3,
  72         ARMV7M_REGSEL_S4,
  73         ARMV7M_REGSEL_S5,
  74         ARMV7M_REGSEL_S6,
  75         ARMV7M_REGSEL_S7,
  76         ARMV7M_REGSEL_S8,
  77         ARMV7M_REGSEL_S9,
  78         ARMV7M_REGSEL_S10,
  79         ARMV7M_REGSEL_S11,
  80         ARMV7M_REGSEL_S12,
  81         ARMV7M_REGSEL_S13,
  82         ARMV7M_REGSEL_S14,
  83         ARMV7M_REGSEL_S15,
  84         ARMV7M_REGSEL_S16,
  85         ARMV7M_REGSEL_S17,
  86         ARMV7M_REGSEL_S18,
  87         ARMV7M_REGSEL_S19,
  88         ARMV7M_REGSEL_S20,
  89         ARMV7M_REGSEL_S21,
  90         ARMV7M_REGSEL_S22,
  91         ARMV7M_REGSEL_S23,
  92         ARMV7M_REGSEL_S24,
  93         ARMV7M_REGSEL_S25,
  94         ARMV7M_REGSEL_S26,
  95         ARMV7M_REGSEL_S27,
  96         ARMV7M_REGSEL_S28,
  97         ARMV7M_REGSEL_S29,
  98         ARMV7M_REGSEL_S30,
  99         ARMV7M_REGSEL_S31,
 100 };
 101
 102 /* offsets into armv7m core register cache */
 103 enum {
 104         /* for convenience, the first set of indices match
 105          * the Cortex-M DCRSR.REGSEL selectors
 106          */
 107         ARMV7M_R0 = ARMV7M_REGSEL_R0,
 108         ARMV7M_R1 = ARMV7M_REGSEL_R1,
 109         ARMV7M_R2 = ARMV7M_REGSEL_R2,
 110         ARMV7M_R3 = ARMV7M_REGSEL_R3,
 111
 112         ARMV7M_R4 = ARMV7M_REGSEL_R4,
 113         ARMV7M_R5 = ARMV7M_REGSEL_R5,
 114         ARMV7M_R6 = ARMV7M_REGSEL_R6,
 115         ARMV7M_R7 = ARMV7M_REGSEL_R7,
 116
 117         ARMV7M_R8 = ARMV7M_REGSEL_R8,
 118         ARMV7M_R9 = ARMV7M_REGSEL_R9,
 119         ARMV7M_R10 = ARMV7M_REGSEL_R10,
 120         ARMV7M_R11 = ARMV7M_REGSEL_R11,
 121
 122         ARMV7M_R12 = ARMV7M_REGSEL_R12,
 123         ARMV7M_R13 = ARMV7M_REGSEL_R13,
 124         ARMV7M_R14 = ARMV7M_REGSEL_R14,
 125         ARMV7M_PC = ARMV7M_REGSEL_PC,
 126
 127         ARMV7M_XPSR = ARMV7M_REGSEL_XPSR,
 128         ARMV7M_MSP = ARMV7M_REGSEL_MSP,
 129         ARMV7M_PSP = ARMV7M_REGSEL_PSP,
 130
 131         /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
 132
 133         /* A block of container and contained registers follows:
 134          * THE ORDER IS IMPORTANT to the end of the block ! */
 135         /* working register for packing/unpacking special regs, hidden from gdb */
 136         ARMV7M_PMSK_BPRI_FLTMSK_CTRL,
 137
 138         /* WARNING: If you use armv7m_write_core_reg() on one of 4 following
 139          * special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
 140          * cache only and are not flushed to CPU HW register.
 141          * To trigger write to CPU HW register, add
 142          *              armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
 143          */
 144         ARMV7M_PRIMASK,
 145         ARMV7M_BASEPRI,
 146         ARMV7M_FAULTMASK,
 147         ARMV7M_CONTROL,
 148         /* The end of block of container and contained registers */
 149
 150         /* ARMv8-M specific registers */
 151         ARMV8M_MSP_NS,
 152         ARMV8M_PSP_NS,
 153         ARMV8M_MSP_S,
 154         ARMV8M_PSP_S,
 155         ARMV8M_MSPLIM_S,
 156         ARMV8M_PSPLIM_S,
 157         ARMV8M_MSPLIM_NS,
 158         ARMV8M_PSPLIM_NS,
 159
 160         /* A block of container and contained registers follows:
 161          * THE ORDER IS IMPORTANT to the end of the block ! */
 162         ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S,
 163         ARMV8M_PRIMASK_S,
 164         ARMV8M_BASEPRI_S,
 165         ARMV8M_FAULTMASK_S,
 166         ARMV8M_CONTROL_S,
 167         /* The end of block of container and contained registers */
 168
 169         /* A block of container and contained registers follows:
 170          * THE ORDER IS IMPORTANT to the end of the block ! */
 171         ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS,
 172         ARMV8M_PRIMASK_NS,
 173         ARMV8M_BASEPRI_NS,
 174         ARMV8M_FAULTMASK_NS,
 175         ARMV8M_CONTROL_NS,
 176         /* The end of block of container and contained registers */
 177
 178         /* 64bit Floating-point registers */
 179         ARMV7M_D0,
 180         ARMV7M_D1,
 181         ARMV7M_D2,
 182         ARMV7M_D3,
 183         ARMV7M_D4,
 184         ARMV7M_D5,
 185         ARMV7M_D6,
 186         ARMV7M_D7,
 187         ARMV7M_D8,
 188         ARMV7M_D9,
 189         ARMV7M_D10,
 190         ARMV7M_D11,
 191         ARMV7M_D12,
 192         ARMV7M_D13,
 193         ARMV7M_D14,
 194         ARMV7M_D15,
 195
 196         /* Floating-point status register */
 197         ARMV7M_FPSCR,
 198
 199         /* for convenience add registers' block delimiters */
 200         ARMV7M_LAST_REG,
 201         ARMV7M_CORE_FIRST_REG = ARMV7M_R0,
 202         ARMV7M_CORE_LAST_REG = ARMV7M_XPSR,
 203         ARMV7M_FPU_FIRST_REG = ARMV7M_D0,
 204         ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR,
 205         ARMV8M_FIRST_REG = ARMV8M_MSP_NS,
 206         ARMV8M_LAST_REG = ARMV8M_CONTROL_NS,
 207 };
 208
 209 enum {
 210         FP_NONE = 0,
 211         FPV4_SP,
 212         FPV5_SP,
 213         FPV5_DP,
 214         FPV5_MVE_I,
 215         FPV5_MVE_F,
 216 };
 217
 218 #define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1)
 219
 220 #define ARMV7M_COMMON_MAGIC 0x2A452A45U
 221
 222 struct armv7m_common {
 223         unsigned int common_magic;
 224
 225         struct arm arm;
 226
 227         int exception_number;
 228
 229         /* AP this processor is connected to in the DAP */
 230         struct adiv5_ap *debug_ap;
 231
 232         int fp_feature;
 233         uint32_t demcr;
 234
 235         /* hla_target uses a high level adapter that does not support all functions */
 236         bool is_hla_target;
 237
 238         struct armv7m_trace_config trace_config;
 239
 240         /* Direct processor core register read and writes */
 241         int (*load_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t *value);
 242         int (*store_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t value);
 243
 244         int (*examine_debug_reason)(struct target *target);
 245         int (*post_debug_entry)(struct target *target);
 246
 247         void (*pre_restore_context)(struct target *target);
 248 };
 249
 250 static inline bool is_armv7m(const struct armv7m_common *armv7m)
 251 {
 252         return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
 253 }
 254
 255 /**
 256  * @returns the pointer to the target specific struct
 257  * without matching a magic number.
 258  * Use in target specific service routines, where the correct
 259  * type of arch_info is certain.
 260  */
 261 static inline struct armv7m_common *
 262 target_to_armv7m(struct target *target)
 263 {
 264         return container_of(target->arch_info, struct armv7m_common, arm);
 265 }
 266
 267 /**
 268  * @returns the pointer to the target specific struct
 269  * or NULL if the magic number does not match.
 270  * Use in a flash driver or any place where mismatch of the arch_info
 271  * type can happen.
 272  */
 273 static inline struct armv7m_common *
 274 target_to_armv7m_safe(struct target *target)
 275 {
 276         if (!target)
 277                 return NULL;
 278
 279         if (!target->arch_info)
 280                 return NULL;
 281
 282         /* Check the parent type first to prevent peeking memory too far
 283          * from arch_info pointer */
 284         if (!is_arm(target_to_arm(target)))
 285                 return NULL;
 286
 287         struct armv7m_common *armv7m = target_to_armv7m(target);
 288         if (!is_armv7m(armv7m))
 289                 return NULL;
 290
 291         return armv7m;
 292 }
 293
 294 struct armv7m_algorithm {
 295         unsigned int common_magic;
 296
 297         enum arm_mode core_mode;
 298
 299         uint32_t context[ARMV7M_LAST_REG]; /* ARMV7M_NUM_REGS */
 300 };
 301
 302 struct reg_cache *armv7m_build_reg_cache(struct target *target);
 303 void armv7m_free_reg_cache(struct target *target);
 304
 305 enum armv7m_mode armv7m_number_to_mode(int number);
 306 int armv7m_mode_to_number(enum armv7m_mode mode);
 307
 308 int armv7m_arch_state(struct target *target);
 309 int armv7m_get_gdb_reg_list(struct target *target,
 310                 struct reg **reg_list[], int *reg_list_size,
 311                 enum target_register_class reg_class);
 312
 313 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m);
 314
 315 int armv7m_run_algorithm(struct target *target,
 316                 int num_mem_params, struct mem_param *mem_params,
 317                 int num_reg_params, struct reg_param *reg_params,
 318                 target_addr_t entry_point, target_addr_t exit_point,
 319                 unsigned int timeout_ms, void *arch_info);
 320
 321 int armv7m_start_algorithm(struct target *target,
 322                 int num_mem_params, struct mem_param *mem_params,
 323                 int num_reg_params, struct reg_param *reg_params,
 324                 target_addr_t entry_point, target_addr_t exit_point,
 325                 void *arch_info);
 326
 327 int armv7m_wait_algorithm(struct target *target,
 328                 int num_mem_params, struct mem_param *mem_params,
 329                 int num_reg_params, struct reg_param *reg_params,
 330                 target_addr_t exit_point, unsigned int timeout_ms,
 331                 void *arch_info);
 332
 333 int armv7m_invalidate_core_regs(struct target *target);
 334
 335 int armv7m_restore_context(struct target *target);
 336
 337 uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id);
 338
 339 bool armv7m_map_reg_packing(unsigned int arm_reg_id,
 340                 unsigned int *reg32_id, uint32_t *offset);
 341
 342 int armv7m_checksum_memory(struct target *target,
 343                 target_addr_t address, uint32_t count, uint32_t *checksum);
 344 int armv7m_blank_check_memory(struct target *target,
 345                 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
 346
 347 int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found);
 348
 349 extern const struct command_registration armv7m_command_handlers[];
 350
 351 #endif /* OPENOCD_TARGET_ARMV7M_H */