1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 /***************************************************************************
28 * This file implements support for the ARM Debug Interface v5 (ADI_V5) *
30 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A *
32 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A *
33 * Cortex-M3(tm) TRM, ARM DDI 0337C *
35 ***************************************************************************/
41 #include "replacements.h"
43 #include "arm_adi_v5.h"
46 #include "time_support.h"
52 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
53 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
54 * result checking until swjdp_end_transaction()
55 * This must be done before using or deallocating any return variables.
56 * swjdp->trans_mode == TRANS_MODE_ATOMIC
57 * All reads and writes to the AHB bus are checked for valid completion, and return values
58 * are immediatley available.
61 /***************************************************************************
63 * DPACC and APACC scanchain access through JTAG-DP *
65 ***************************************************************************/
67 /* Scan out and in from target ordered u8 buffers */
68 int adi_jtag_dp_scan(arm_jtag_t
*jtag_info
, u8 instr
, u8 reg_addr
, u8 RnW
, u8
*outvalue
, u8
*invalue
, u8
*ack
)
70 scan_field_t fields
[2];
73 jtag_add_end_state(TAP_IDLE
);
74 arm_jtag_set_instr(jtag_info
, instr
, NULL
);
76 fields
[0].tap
= jtag_info
->tap
;
77 fields
[0].num_bits
= 3;
78 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
79 fields
[0].out_value
= &out_addr_buf
;
81 fields
[0].in_value
= ack
;
84 fields
[0].in_handler
= NULL
;
87 fields
[1].tap
= jtag_info
->tap
;
88 fields
[1].num_bits
= 32;
89 fields
[1].out_value
= outvalue
;
91 fields
[1].in_value
= invalue
;
92 fields
[1].in_handler
= NULL
;
97 jtag_add_dr_scan(2, fields
, TAP_INVALID
);
102 /* Scan out and in from host ordered u32 variables */
103 int adi_jtag_dp_scan_u32(arm_jtag_t
*jtag_info
, u8 instr
, u8 reg_addr
, u8 RnW
, u32 outvalue
, u32
*invalue
, u8
*ack
)
105 scan_field_t fields
[2];
109 jtag_add_end_state(TAP_IDLE
);
110 arm_jtag_set_instr(jtag_info
, instr
, NULL
);
112 fields
[0].tap
= jtag_info
->tap
;
113 fields
[0].num_bits
= 3;
114 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
115 fields
[0].out_value
= &out_addr_buf
;
116 fields
[0].in_value
= ack
;
117 fields
[0].in_handler
= NULL
;
120 fields
[1].tap
= jtag_info
->tap
;
121 fields
[1].num_bits
= 32;
122 buf_set_u32(out_value_buf
, 0, 32, outvalue
);
123 fields
[1].out_value
= out_value_buf
;
124 fields
[1].in_value
= NULL
;
125 fields
[1].in_handler
= NULL
;
130 fields
[1].in_value
= tmp
;
131 jtag_add_dr_scan_now(2, fields
, TAP_INVALID
);
133 *invalue
=le_to_h_u32(tmp
);
137 jtag_add_dr_scan(2, fields
, TAP_INVALID
);
143 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
144 int scan_inout_check(swjdp_common_t
*swjdp
, u8 instr
, u8 reg_addr
, u8 RnW
, u8
*outvalue
, u8
*invalue
)
146 adi_jtag_dp_scan(swjdp
->jtag_info
, instr
, reg_addr
, RnW
, outvalue
, NULL
, NULL
);
147 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
149 adi_jtag_dp_scan(swjdp
->jtag_info
, SWJDP_IR_DPACC
, DP_RDBUFF
, DPAP_READ
, 0, invalue
, &swjdp
->ack
);
152 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
153 if ((instr
== SWJDP_IR_APACC
) && (swjdp
->trans_mode
== TRANS_MODE_ATOMIC
))
155 return swjdp_transaction_endcheck(swjdp
);
161 int scan_inout_check_u32(swjdp_common_t
*swjdp
, u8 instr
, u8 reg_addr
, u8 RnW
, u32 outvalue
, u32
*invalue
)
163 adi_jtag_dp_scan_u32(swjdp
->jtag_info
, instr
, reg_addr
, RnW
, outvalue
, NULL
, NULL
);
164 if ((RnW
==DPAP_READ
) && (invalue
!= NULL
))
166 adi_jtag_dp_scan_u32(swjdp
->jtag_info
, SWJDP_IR_DPACC
, DP_RDBUFF
, DPAP_READ
, 0, invalue
, &swjdp
->ack
);
169 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
170 if ((instr
== SWJDP_IR_APACC
) && (swjdp
->trans_mode
== TRANS_MODE_ATOMIC
))
172 return swjdp_transaction_endcheck(swjdp
);
178 int swjdp_transaction_endcheck(swjdp_common_t
*swjdp
)
183 /* too expensive to call keep_alive() here */
186 /* Danger!!!! BROKEN!!!! */
187 scan_inout_check_u32(swjdp
, SWJDP_IR_DPACC
, DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
188 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
189 R956 introduced the check on return value here and now Michael Schwingen reports
190 that this code no longer works....
192 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
194 if ((retval
=jtag_execute_queue())!=ERROR_OK
)
196 LOG_ERROR("BUG: Why does this fail the first time????");
198 /* Why??? second time it works??? */
201 scan_inout_check_u32(swjdp
, SWJDP_IR_DPACC
, DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
202 if ((retval
=jtag_execute_queue())!=ERROR_OK
)
205 swjdp
->ack
= swjdp
->ack
& 0x7;
209 long long then
=timeval_ms();
210 while (swjdp
->ack
!= 2)
214 if ((timeval_ms()-then
) > 1000)
216 LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
217 return ERROR_JTAG_DEVICE_ERROR
;
222 LOG_WARNING("Invalid ACK in SWJDP transaction");
223 return ERROR_JTAG_DEVICE_ERROR
;
226 scan_inout_check_u32(swjdp
, SWJDP_IR_DPACC
, DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
227 if ((retval
=jtag_execute_queue())!=ERROR_OK
)
229 swjdp
->ack
= swjdp
->ack
& 0x7;
233 /* common code path avoids fn to timeval_ms() */
236 /* Check for STICKYERR and STICKYORUN */
237 if (ctrlstat
& (SSTICKYORUN
| SSTICKYERR
))
239 LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat
);
240 /* Check power to debug regions */
241 if ((ctrlstat
& 0xf0000000) != 0xf0000000)
243 ahbap_debugport_init(swjdp
);
247 u32 mem_ap_csw
, mem_ap_tar
;
249 /* Print information about last AHBAP access */
250 LOG_ERROR("AHBAP Cached values: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp
->dp_select_value
, swjdp
->ap_csw_value
, swjdp
->ap_tar_value
);
251 if (ctrlstat
& SSTICKYORUN
)
252 LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
254 if (ctrlstat
& SSTICKYERR
)
255 LOG_ERROR("SWJ-DP STICKY ERROR");
257 /* Clear Sticky Error Bits */
258 scan_inout_check_u32(swjdp
, SWJDP_IR_DPACC
, DP_CTRL_STAT
, DPAP_WRITE
, swjdp
->dp_ctrl_stat
| SSTICKYORUN
| SSTICKYERR
, NULL
);
259 scan_inout_check_u32(swjdp
, SWJDP_IR_DPACC
, DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
260 if ((retval
=jtag_execute_queue())!=ERROR_OK
)
263 LOG_DEBUG("swjdp: status 0x%x", ctrlstat
);
265 dap_ap_read_reg_u32(swjdp
, AP_REG_CSW
, &mem_ap_csw
);
266 dap_ap_read_reg_u32(swjdp
, AP_REG_TAR
, &mem_ap_tar
);
267 if ((retval
=jtag_execute_queue())!=ERROR_OK
)
269 LOG_ERROR("Read MEM_AP_CSW 0x%x, MEM_AP_TAR 0x%x", mem_ap_csw
, mem_ap_tar
);
272 if ((retval
=jtag_execute_queue())!=ERROR_OK
)
274 return ERROR_JTAG_DEVICE_ERROR
;
280 /***************************************************************************
282 * DP and MEM-AP register access through APACC and DPACC *
284 ***************************************************************************/
286 int dap_dp_write_reg(swjdp_common_t
*swjdp
, u32 value
, u8 reg_addr
)
288 return scan_inout_check_u32(swjdp
, SWJDP_IR_DPACC
, reg_addr
, DPAP_WRITE
, value
, NULL
);
291 int dap_dp_read_reg(swjdp_common_t
*swjdp
, u32
*value
, u8 reg_addr
)
293 return scan_inout_check_u32(swjdp
, SWJDP_IR_DPACC
, reg_addr
, DPAP_READ
, 0, value
);
296 int dap_ap_select(swjdp_common_t
*swjdp
,u8 apsel
)
299 select
= (apsel
<<24) & 0xFF000000;
301 if (select
!= swjdp
->apsel
)
303 swjdp
->apsel
= select
;
304 /* Switchin AP invalidates cached values */
305 swjdp
->dp_select_value
= -1;
306 swjdp
->ap_csw_value
= -1;
307 swjdp
->ap_tar_value
= -1;
313 int dap_dp_bankselect(swjdp_common_t
*swjdp
,u32 ap_reg
)
316 select
= (ap_reg
& 0x000000F0);
318 if (select
!= swjdp
->dp_select_value
)
320 dap_dp_write_reg(swjdp
, select
| swjdp
->apsel
, DP_SELECT
);
321 swjdp
->dp_select_value
= select
;
327 int dap_ap_write_reg(swjdp_common_t
*swjdp
, u32 reg_addr
, u8
* out_value_buf
)
329 dap_dp_bankselect(swjdp
, reg_addr
);
330 scan_inout_check(swjdp
, SWJDP_IR_APACC
, reg_addr
, DPAP_WRITE
, out_value_buf
, NULL
);
335 int dap_ap_read_reg(swjdp_common_t
*swjdp
, u32 reg_addr
, u8
*in_value_buf
)
337 dap_dp_bankselect(swjdp
, reg_addr
);
338 scan_inout_check(swjdp
, SWJDP_IR_APACC
, reg_addr
, DPAP_READ
, 0, in_value_buf
);
342 int dap_ap_write_reg_u32(swjdp_common_t
*swjdp
, u32 reg_addr
, u32 value
)
346 buf_set_u32(out_value_buf
, 0, 32, value
);
347 dap_dp_bankselect(swjdp
, reg_addr
);
348 scan_inout_check(swjdp
, SWJDP_IR_APACC
, reg_addr
, DPAP_WRITE
, out_value_buf
, NULL
);
353 int dap_ap_read_reg_u32(swjdp_common_t
*swjdp
, u32 reg_addr
, u32
*value
)
355 dap_dp_bankselect(swjdp
, reg_addr
);
356 scan_inout_check_u32(swjdp
, SWJDP_IR_APACC
, reg_addr
, DPAP_READ
, 0, value
);
361 /***************************************************************************
363 * AHB-AP access to memory and system registers on AHB bus *
365 ***************************************************************************/
367 int dap_setup_accessport(swjdp_common_t
*swjdp
, u32 csw
, u32 tar
)
369 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
;
370 if (csw
!= swjdp
->ap_csw_value
)
372 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
373 dap_ap_write_reg_u32(swjdp
, AP_REG_CSW
, csw
);
374 swjdp
->ap_csw_value
= csw
;
376 if (tar
!= swjdp
->ap_tar_value
)
378 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
379 dap_ap_write_reg_u32(swjdp
, AP_REG_TAR
, tar
);
380 swjdp
->ap_tar_value
= tar
;
382 if (csw
& CSW_ADDRINC_MASK
)
384 /* Do not cache TAR value when autoincrementing */
385 swjdp
->ap_tar_value
= -1;
390 /*****************************************************************************
392 * mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
394 * Read a u32 value from memory or system register *
395 * Functionally equivalent to target_read_u32(target, address, u32 *value), *
396 * but with less overhead *
397 *****************************************************************************/
398 int mem_ap_read_u32(swjdp_common_t
*swjdp
, u32 address
, u32
*value
)
400 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
402 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, address
& 0xFFFFFFF0);
403 dap_ap_read_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC), value
);
408 int mem_ap_read_atomic_u32(swjdp_common_t
*swjdp
, u32 address
, u32
*value
)
410 mem_ap_read_u32(swjdp
, address
, value
);
412 return swjdp_transaction_endcheck(swjdp
);
415 /*****************************************************************************
417 * mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
419 * Write a u32 value to memory or memory mapped register *
421 *****************************************************************************/
422 int mem_ap_write_u32(swjdp_common_t
*swjdp
, u32 address
, u32 value
)
424 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
426 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, address
& 0xFFFFFFF0);
427 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC), value
);
432 int mem_ap_write_atomic_u32(swjdp_common_t
*swjdp
, u32 address
, u32 value
)
434 mem_ap_write_u32(swjdp
, address
, value
);
436 return swjdp_transaction_endcheck(swjdp
);
439 /*****************************************************************************
441 * mem_ap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
443 * Write a buffer in target order (little endian) *
445 *****************************************************************************/
446 int mem_ap_write_buf_u32(swjdp_common_t
*swjdp
, u8
*buffer
, int count
, u32 address
)
448 int wcount
, blocksize
, writecount
, errorcount
= 0, retval
= ERROR_OK
;
450 u8
* pBuffer
= buffer
;
452 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
457 /* if we have an unaligned access - reorder data */
460 for (writecount
= 0; writecount
< count
; writecount
++)
464 memcpy(&outvalue
, pBuffer
, sizeof(u32
));
466 for (i
= 0; i
< 4; i
++ )
468 *((u8
*)pBuffer
+ (adr
& 0x3)) = outvalue
;
472 pBuffer
+= sizeof(u32
);
478 /* Adjust to write blocks within 4K aligned boundaries */
479 blocksize
= (0x1000 - (0xFFF & address
)) >> 2;
480 if (wcount
< blocksize
)
483 /* handle unaligned data at 4k boundary */
487 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
489 for (writecount
= 0; writecount
< blocksize
; writecount
++)
491 dap_ap_write_reg(swjdp
, AP_REG_DRW
, buffer
+ 4 * writecount
);
494 if (swjdp_transaction_endcheck(swjdp
) == ERROR_OK
)
496 wcount
= wcount
- blocksize
;
497 address
= address
+ 4 * blocksize
;
498 buffer
= buffer
+ 4 * blocksize
;
507 LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address
, wcount
);
508 return ERROR_JTAG_DEVICE_ERROR
;
515 int mem_ap_write_buf_packed_u16(swjdp_common_t
*swjdp
, u8
*buffer
, int count
, u32 address
)
517 int retval
= ERROR_OK
;
518 int wcount
, blocksize
, writecount
, i
;
520 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
528 /* Adjust to read within 4K block boundaries */
529 blocksize
= (0x1000 - (0xFFF & address
)) >> 1;
531 if (wcount
< blocksize
)
534 /* handle unaligned data at 4k boundary */
538 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
539 writecount
= blocksize
;
543 nbytes
= MIN((writecount
<< 1), 4);
547 if (mem_ap_write_buf_u16(swjdp
, buffer
, nbytes
, address
) != ERROR_OK
)
549 LOG_WARNING("Block read error address 0x%x, count 0x%x", address
, count
);
550 return ERROR_JTAG_DEVICE_ERROR
;
553 address
+= nbytes
>> 1;
558 memcpy(&outvalue
, buffer
, sizeof(u32
));
560 for (i
= 0; i
< nbytes
; i
++ )
562 *((u8
*)buffer
+ (address
& 0x3)) = outvalue
;
567 memcpy(&outvalue
, buffer
, sizeof(u32
));
568 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
569 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
571 LOG_WARNING("Block read error address 0x%x, count 0x%x", address
, count
);
572 return ERROR_JTAG_DEVICE_ERROR
;
576 buffer
+= nbytes
>> 1;
577 writecount
-= nbytes
>> 1;
579 } while (writecount
);
586 int mem_ap_write_buf_u16(swjdp_common_t
*swjdp
, u8
*buffer
, int count
, u32 address
)
588 int retval
= ERROR_OK
;
591 return mem_ap_write_buf_packed_u16(swjdp
, buffer
, count
, address
);
593 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
597 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
599 memcpy(&svalue
, buffer
, sizeof(u16
));
600 u32 outvalue
= (u32
)svalue
<< 8 * (address
& 0x3);
601 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
602 retval
= swjdp_transaction_endcheck(swjdp
);
611 int mem_ap_write_buf_packed_u8(swjdp_common_t
*swjdp
, u8
*buffer
, int count
, u32 address
)
613 int retval
= ERROR_OK
;
614 int wcount
, blocksize
, writecount
, i
;
616 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
624 /* Adjust to read within 4K block boundaries */
625 blocksize
= (0x1000 - (0xFFF & address
));
627 if (wcount
< blocksize
)
630 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
631 writecount
= blocksize
;
635 nbytes
= MIN(writecount
, 4);
639 if (mem_ap_write_buf_u8(swjdp
, buffer
, nbytes
, address
) != ERROR_OK
)
641 LOG_WARNING("Block read error address 0x%x, count 0x%x", address
, count
);
642 return ERROR_JTAG_DEVICE_ERROR
;
650 memcpy(&outvalue
, buffer
, sizeof(u32
));
652 for (i
= 0; i
< nbytes
; i
++ )
654 *((u8
*)buffer
+ (address
& 0x3)) = outvalue
;
659 memcpy(&outvalue
, buffer
, sizeof(u32
));
660 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
661 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
663 LOG_WARNING("Block read error address 0x%x, count 0x%x", address
, count
);
664 return ERROR_JTAG_DEVICE_ERROR
;
669 writecount
-= nbytes
;
671 } while (writecount
);
678 int mem_ap_write_buf_u8(swjdp_common_t
*swjdp
, u8
*buffer
, int count
, u32 address
)
680 int retval
= ERROR_OK
;
683 return mem_ap_write_buf_packed_u8(swjdp
, buffer
, count
, address
);
685 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
689 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
690 u32 outvalue
= (u32
)*buffer
<< 8 * (address
& 0x3);
691 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
692 retval
= swjdp_transaction_endcheck(swjdp
);
701 /*********************************************************************************
703 * mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
705 * Read block fast in target order (little endian) into a buffer *
707 **********************************************************************************/
708 int mem_ap_read_buf_u32(swjdp_common_t
*swjdp
, u8
*buffer
, int count
, u32 address
)
710 int wcount
, blocksize
, readcount
, errorcount
= 0, retval
= ERROR_OK
;
712 u8
* pBuffer
= buffer
;
714 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
721 /* Adjust to read within 4K block boundaries */
722 blocksize
= (0x1000 - (0xFFF & address
)) >> 2;
723 if (wcount
< blocksize
)
726 /* handle unaligned data at 4k boundary */
730 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
732 /* Scan out first read */
733 adi_jtag_dp_scan(swjdp
->jtag_info
, SWJDP_IR_APACC
, AP_REG_DRW
, DPAP_READ
, 0, NULL
, NULL
);
734 for (readcount
= 0; readcount
< blocksize
- 1; readcount
++)
736 /* Scan out read instruction and scan in previous value */
737 adi_jtag_dp_scan(swjdp
->jtag_info
, SWJDP_IR_APACC
, AP_REG_DRW
, DPAP_READ
, 0, buffer
+ 4 * readcount
, &swjdp
->ack
);
740 /* Scan in last value */
741 adi_jtag_dp_scan(swjdp
->jtag_info
, SWJDP_IR_DPACC
, DP_RDBUFF
, DPAP_READ
, 0, buffer
+ 4 * readcount
, &swjdp
->ack
);
742 if (swjdp_transaction_endcheck(swjdp
) == ERROR_OK
)
744 wcount
= wcount
- blocksize
;
745 address
+= 4 * blocksize
;
746 buffer
+= 4 * blocksize
;
755 LOG_WARNING("Block read error address 0x%x, count 0x%x", address
, count
);
756 return ERROR_JTAG_DEVICE_ERROR
;
760 /* if we have an unaligned access - reorder data */
763 for (readcount
= 0; readcount
< count
; readcount
++)
767 memcpy(&data
, pBuffer
, sizeof(u32
));
769 for (i
= 0; i
< 4; i
++ )
771 *((u8
*)pBuffer
) = (data
>> 8 * (adr
& 0x3));
781 int mem_ap_read_buf_packed_u16(swjdp_common_t
*swjdp
, u8
*buffer
, int count
, u32 address
)
784 int retval
= ERROR_OK
;
785 int wcount
, blocksize
, readcount
, i
;
787 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
795 /* Adjust to read within 4K block boundaries */
796 blocksize
= (0x1000 - (0xFFF & address
)) >> 1;
797 if (wcount
< blocksize
)
800 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
802 /* handle unaligned data at 4k boundary */
805 readcount
= blocksize
;
809 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
810 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
812 LOG_WARNING("Block read error address 0x%x, count 0x%x", address
, count
);
813 return ERROR_JTAG_DEVICE_ERROR
;
816 nbytes
= MIN((readcount
<< 1), 4);
818 for (i
= 0; i
< nbytes
; i
++ )
820 *((u8
*)buffer
) = (invalue
>> 8 * (address
& 0x3));
825 readcount
-= (nbytes
>> 1);
833 int mem_ap_read_buf_u16(swjdp_common_t
*swjdp
, u8
*buffer
, int count
, u32 address
)
836 int retval
= ERROR_OK
;
839 return mem_ap_read_buf_packed_u16(swjdp
, buffer
, count
, address
);
841 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
845 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
846 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
847 retval
= swjdp_transaction_endcheck(swjdp
);
850 for (i
= 0; i
< 2; i
++ )
852 *((u8
*)buffer
) = (invalue
>> 8 * (address
& 0x3));
859 u16 svalue
= (invalue
>> 8 * (address
& 0x3));
860 memcpy(buffer
, &svalue
, sizeof(u16
));
870 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
871 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
873 * The solution is to arrange for a large out/in scan in this loop and
874 * and convert data afterwards.
876 int mem_ap_read_buf_packed_u8(swjdp_common_t
*swjdp
, u8
*buffer
, int count
, u32 address
)
879 int retval
= ERROR_OK
;
880 int wcount
, blocksize
, readcount
, i
;
882 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
890 /* Adjust to read within 4K block boundaries */
891 blocksize
= (0x1000 - (0xFFF & address
));
893 if (wcount
< blocksize
)
896 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
897 readcount
= blocksize
;
901 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
902 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
904 LOG_WARNING("Block read error address 0x%x, count 0x%x", address
, count
);
905 return ERROR_JTAG_DEVICE_ERROR
;
908 nbytes
= MIN(readcount
, 4);
910 for (i
= 0; i
< nbytes
; i
++ )
912 *((u8
*)buffer
) = (invalue
>> 8 * (address
& 0x3));
925 int mem_ap_read_buf_u8(swjdp_common_t
*swjdp
, u8
*buffer
, int count
, u32 address
)
928 int retval
= ERROR_OK
;
931 return mem_ap_read_buf_packed_u8(swjdp
, buffer
, count
, address
);
933 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
937 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
938 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
939 retval
= swjdp_transaction_endcheck(swjdp
);
940 *((u8
*)buffer
) = (invalue
>> 8 * (address
& 0x3));
949 int ahbap_debugport_init(swjdp_common_t
*swjdp
)
951 u32 idreg
, romaddr
, dummy
;
959 swjdp
->ap_csw_value
= -1;
960 swjdp
->ap_tar_value
= -1;
961 swjdp
->trans_mode
= TRANS_MODE_ATOMIC
;
962 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
963 dap_dp_write_reg(swjdp
, SSTICKYERR
, DP_CTRL_STAT
);
964 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
966 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
968 dap_dp_write_reg(swjdp
, swjdp
->dp_ctrl_stat
, DP_CTRL_STAT
);
969 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
970 if ((retval
=jtag_execute_queue())!=ERROR_OK
)
973 /* Check that we have debug power domains activated */
974 while (!(ctrlstat
& CDBGPWRUPACK
) && (cnt
++ < 10))
976 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
977 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
978 if ((retval
=jtag_execute_queue())!=ERROR_OK
)
983 while (!(ctrlstat
& CSYSPWRUPACK
) && (cnt
++ < 10))
985 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
986 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
987 if ((retval
=jtag_execute_queue())!=ERROR_OK
)
992 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
993 /* With debug power on we can activate OVERRUN checking */
994 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
995 dap_dp_write_reg(swjdp
, swjdp
->dp_ctrl_stat
, DP_CTRL_STAT
);
996 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
998 dap_ap_read_reg_u32(swjdp
, 0xFC, &idreg
);
999 dap_ap_read_reg_u32(swjdp
, 0xF8, &romaddr
);
1001 LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg
, romaddr
);
1007 char * class_description
[16] ={
1009 "ROM table","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved",
1010 "CoreSight component","Reserved","Peripheral Test Block","Reserved","DESS","Generic IP component","Non standard layout"};
1012 int dap_info_command(struct command_context_s
*cmd_ctx
, swjdp_common_t
*swjdp
, int apsel
)
1016 int romtable_present
= 0;
1020 apselold
= swjdp
->apsel
;
1021 dap_ap_select(swjdp
, apsel
);
1022 dap_ap_read_reg_u32(swjdp
, 0xF8, &dbgbase
);
1023 dap_ap_read_reg_u32(swjdp
, 0xFC, &apid
);
1024 swjdp_transaction_endcheck(swjdp
);
1025 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1026 mem_ap
= ((apid
&0x10000)&&((apid
&0x0F)!=0));
1027 command_print(cmd_ctx
, "ap identification register 0x%8.8x", apid
);
1033 command_print(cmd_ctx
, "\tType is jtag-ap");
1036 command_print(cmd_ctx
, "\tType is mem-ap AHB");
1039 command_print(cmd_ctx
, "\tType is mem-ap APB");
1042 command_print(cmd_ctx
, "\tUnknown AP-type");
1045 command_print(cmd_ctx
, "ap debugbase 0x%8.8x", dbgbase
);
1049 command_print(cmd_ctx
, "No AP found at this apsel 0x%x", apsel
);
1052 romtable_present
= ((mem_ap
)&&(dbgbase
!= 0xFFFFFFFF));
1053 if (romtable_present
)
1055 u32 cid0
,cid1
,cid2
,cid3
,memtype
,romentry
;
1057 /* bit 16 of apid indicates a memory access port */
1060 command_print(cmd_ctx
, "\tValid ROM table present");
1064 command_print(cmd_ctx
, "\tROM table in legacy format" );
1066 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1067 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000)|0xFF0, &cid0
);
1068 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000)|0xFF4, &cid1
);
1069 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000)|0xFF8, &cid2
);
1070 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000)|0xFFC, &cid3
);
1071 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000)|0xFCC, &memtype
);
1072 swjdp_transaction_endcheck(swjdp
);
1073 command_print(cmd_ctx
, "\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",cid3
,cid2
,cid1
,cid0
);
1076 command_print(cmd_ctx
, "\tMEMTYPE system memory present on bus");
1080 command_print(cmd_ctx
, "\tMEMTYPE system memory not present. Dedicated debug bus" );
1083 /* Now we read ROM table entries from dbgbase&0xFFFFF000)|0x000 until we get 0x00000000 */
1087 mem_ap_read_atomic_u32(swjdp
, (dbgbase
&0xFFFFF000)|entry_offset
, &romentry
);
1088 command_print(cmd_ctx
, "\tROMTABLE[0x%x] = 0x%x",entry_offset
,romentry
);
1091 u32 c_cid0
,c_cid1
,c_cid2
,c_cid3
,c_pid0
,c_pid1
,c_pid2
,c_pid3
,c_pid4
,component_start
;
1092 u32 component_base
= (u32
)((dbgbase
&0xFFFFF000)+(int)(romentry
&0xFFFFF000));
1093 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000)|0xFE0, &c_pid0
);
1094 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000)|0xFE4, &c_pid1
);
1095 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000)|0xFE8, &c_pid2
);
1096 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000)|0xFEC, &c_pid3
);
1097 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000)|0xFD0, &c_pid4
);
1098 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000)|0xFF0, &c_cid0
);
1099 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000)|0xFF4, &c_cid1
);
1100 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000)|0xFF8, &c_cid2
);
1101 mem_ap_read_atomic_u32(swjdp
, (component_base
&0xFFFFF000)|0xFFC, &c_cid3
);
1102 component_start
= component_base
- 0x1000*(c_pid4
>>4);
1103 command_print(cmd_ctx
, "\t\tComponent base address 0x%x, pid4 0x%x, start address 0x%x",component_base
,c_pid4
,component_start
);
1104 command_print(cmd_ctx
, "\t\tComponent cid1 0x%x, class is %s",c_cid1
,class_description
[(c_cid1
>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
1105 command_print(cmd_ctx
, "\t\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",c_cid3
,c_cid2
,c_cid1
,c_cid0
);
1106 command_print(cmd_ctx
, "\t\tPID3 0x%x, PID2 0x%x, PID1 0x%x, PID0, 0x%x",c_pid3
,c_pid2
,c_pid1
,c_pid0
);
1107 /* For CoreSight components, (c_cid1>>4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */
1112 command_print(cmd_ctx
, "\t\tComponent not present");
1114 command_print(cmd_ctx
, "\t\tEnd of ROM table");
1117 } while (romentry
>0);
1121 command_print(cmd_ctx
, "\tNo ROM table present");
1123 dap_ap_select(swjdp
, apselold
);