1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
19 * DaVinci family NAND controller support for OpenOCD.
21 * This driver uses hardware ECC (1-bit or 4-bit) unless
22 * the chip is accessed in "raw" mode.
31 #include <target/target.h>
34 HWECC1
, /* all controllers support 1-bit ECC */
35 HWECC4
, /* newer chips also have 4-bit ECC hardware */
36 HWECC4_INFIX
, /* avoid this layout, except maybe for boot code */
40 uint8_t chipsel
; /* chipselect 0..3 == CS2..CS5 */
43 /* Async EMIF controller base */
46 /* NAND chip addresses */
47 uint32_t data
; /* without CLE or ALE */
48 uint32_t cmd
; /* with CLE */
49 uint32_t addr
; /* with ALE */
51 /* write acceleration */
52 struct arm_nand_data io
;
54 /* page i/o for the relevant flavor of hardware ECC */
55 int (*read_page
)(struct nand_device
*nand
, uint32_t page
,
56 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
);
57 int (*write_page
)(struct nand_device
*nand
, uint32_t page
,
58 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
);
61 #define NANDFCR 0x60 /* flash control register */
62 #define NANDFSR 0x64 /* flash status register */
63 #define NANDFECC 0x70 /* 1-bit ECC data, CS0, 1st of 4 */
64 #define NAND4BITECCLOAD 0xbc /* 4-bit ECC, load saved values */
65 #define NAND4BITECC 0xc0 /* 4-bit ECC data, 1st of 4 */
66 #define NANDERRADDR 0xd0 /* 4-bit ECC err addr, 1st of 2 */
67 #define NANDERRVAL 0xd8 /* 4-bit ECC err value, 1st of 2 */
69 static int halted(struct target
*target
, const char *label
)
71 if (target
->state
== TARGET_HALTED
)
74 LOG_ERROR("Target must be halted to use NAND controller (%s)", label
);
78 static int davinci_init(struct nand_device
*nand
)
80 struct davinci_nand
*info
= nand
->controller_priv
;
81 struct target
*target
= nand
->target
;
84 if (!halted(target
, "init"))
85 return ERROR_NAND_OPERATION_FAILED
;
87 /* We require something else to have configured AEMIF to talk
88 * to NAND chip in this range (including timings and width).
90 target_read_u32(target
, info
->aemif
+ NANDFCR
, &nandfcr
);
91 if (!(nandfcr
& (1 << info
->chipsel
))) {
92 LOG_ERROR("chip address %08" PRIx32
" not NAND-enabled?", info
->data
);
93 return ERROR_NAND_OPERATION_FAILED
;
96 /* REVISIT verify: AxCR must be in 8-bit mode, since that's all we
97 * tested. 16 bit support should work too; but not with 4-bit ECC.
103 static int davinci_reset(struct nand_device
*nand
)
108 static int davinci_nand_ready(struct nand_device
*nand
, int timeout
)
110 struct davinci_nand
*info
= nand
->controller_priv
;
111 struct target
*target
= nand
->target
;
114 /* NOTE: return code is zero/error, else success; not ERROR_* */
116 if (!halted(target
, "ready"))
120 target_read_u32(target
, info
->aemif
+ NANDFSR
, &nandfsr
);
126 } while (timeout
-- > 0);
131 static int davinci_command(struct nand_device
*nand
, uint8_t command
)
133 struct davinci_nand
*info
= nand
->controller_priv
;
134 struct target
*target
= nand
->target
;
136 if (!halted(target
, "command"))
137 return ERROR_NAND_OPERATION_FAILED
;
139 target_write_u8(target
, info
->cmd
, command
);
143 static int davinci_address(struct nand_device
*nand
, uint8_t address
)
145 struct davinci_nand
*info
= nand
->controller_priv
;
146 struct target
*target
= nand
->target
;
148 if (!halted(target
, "address"))
149 return ERROR_NAND_OPERATION_FAILED
;
151 target_write_u8(target
, info
->addr
, address
);
155 static int davinci_write_data(struct nand_device
*nand
, uint16_t data
)
157 struct davinci_nand
*info
= nand
->controller_priv
;
158 struct target
*target
= nand
->target
;
160 if (!halted(target
, "write_data"))
161 return ERROR_NAND_OPERATION_FAILED
;
163 target_write_u8(target
, info
->data
, data
);
167 static int davinci_read_data(struct nand_device
*nand
, void *data
)
169 struct davinci_nand
*info
= nand
->controller_priv
;
170 struct target
*target
= nand
->target
;
172 if (!halted(target
, "read_data"))
173 return ERROR_NAND_OPERATION_FAILED
;
175 target_read_u8(target
, info
->data
, data
);
179 /* REVISIT a bit of native code should let block reads be MUCH faster */
181 static int davinci_read_block_data(struct nand_device
*nand
,
182 uint8_t *data
, int data_size
)
184 struct davinci_nand
*info
= nand
->controller_priv
;
185 struct target
*target
= nand
->target
;
186 uint32_t nfdata
= info
->data
;
189 if (!halted(target
, "read_block"))
190 return ERROR_NAND_OPERATION_FAILED
;
192 while (data_size
>= 4) {
193 target_read_u32(target
, nfdata
, &tmp
);
204 while (data_size
> 0) {
205 target_read_u8(target
, nfdata
, data
);
214 static int davinci_write_block_data(struct nand_device
*nand
,
215 uint8_t *data
, int data_size
)
217 struct davinci_nand
*info
= nand
->controller_priv
;
218 struct target
*target
= nand
->target
;
219 uint32_t nfdata
= info
->data
;
223 if (!halted(target
, "write_block"))
224 return ERROR_NAND_OPERATION_FAILED
;
226 /* try the fast way first */
227 status
= arm_nandwrite(&info
->io
, data
, data_size
);
228 if (status
!= ERROR_NAND_NO_BUFFER
)
231 /* else do it slowly */
232 while (data_size
>= 4) {
233 tmp
= le_to_h_u32(data
);
234 target_write_u32(target
, nfdata
, tmp
);
240 while (data_size
> 0) {
241 target_write_u8(target
, nfdata
, *data
);
250 static int davinci_write_page(struct nand_device
*nand
, uint32_t page
,
251 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
253 struct davinci_nand
*info
= nand
->controller_priv
;
254 uint8_t *ooballoc
= NULL
;
258 return ERROR_NAND_DEVICE_NOT_PROBED
;
259 if (!halted(nand
->target
, "write_page"))
260 return ERROR_NAND_OPERATION_FAILED
;
262 /* Always write both data and OOB ... we are not "raw" I/O! */
264 LOG_ERROR("Missing NAND data; try 'nand raw_access enable'");
265 return ERROR_NAND_OPERATION_FAILED
;
268 /* If we're not given OOB, write 0xff where we don't write ECC codes. */
269 switch (nand
->page_size
) {
280 return ERROR_NAND_OPERATION_FAILED
;
283 ooballoc
= malloc(oob_size
);
285 return ERROR_NAND_OPERATION_FAILED
;
287 memset(oob
, 0x0ff, oob_size
);
290 /* REVISIT avoid wasting SRAM: unless nand->use_raw is set,
291 * use 512 byte chunks. Read side support will often want
292 * to include oob_size ...
294 info
->io
.chunk_size
= nand
->page_size
;
296 status
= info
->write_page(nand
, page
, data
, data_size
, oob
, oob_size
);
301 static int davinci_read_page(struct nand_device
*nand
, uint32_t page
,
302 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
304 struct davinci_nand
*info
= nand
->controller_priv
;
307 return ERROR_NAND_DEVICE_NOT_PROBED
;
308 if (!halted(nand
->target
, "read_page"))
309 return ERROR_NAND_OPERATION_FAILED
;
311 return info
->read_page(nand
, page
, data
, data_size
, oob
, oob_size
);
314 static void davinci_write_pagecmd(struct nand_device
*nand
, uint8_t cmd
, uint32_t page
)
316 struct davinci_nand
*info
= nand
->controller_priv
;
317 struct target
*target
= nand
->target
;
318 int page3
= nand
->address_cycles
- (nand
->page_size
== 512);
320 /* write command ({page,otp}x{read,program} */
321 target_write_u8(target
, info
->cmd
, cmd
);
323 /* column address (beginning-of-page) */
324 target_write_u8(target
, info
->addr
, 0);
325 if (nand
->page_size
> 512)
326 target_write_u8(target
, info
->addr
, 0);
329 target_write_u8(target
, info
->addr
, page
);
330 target_write_u8(target
, info
->addr
, page
>> 8);
332 target_write_u8(target
, info
->addr
, page
>> 16);
334 target_write_u8(target
, info
->addr
, page
>> 24);
337 static int davinci_seek_column(struct nand_device
*nand
, uint16_t column
)
339 struct davinci_nand
*info
= nand
->controller_priv
;
340 struct target
*target
= nand
->target
;
342 /* Random read, we must have issued a page read already */
343 target_write_u8(target
, info
->cmd
, NAND_CMD_RNDOUT
);
345 target_write_u8(target
, info
->addr
, column
);
347 if (nand
->page_size
> 512) {
348 target_write_u8(target
, info
->addr
, column
>> 8);
349 target_write_u8(target
, info
->cmd
, NAND_CMD_RNDOUTSTART
);
352 if (!davinci_nand_ready(nand
, 100))
353 return ERROR_NAND_OPERATION_TIMEOUT
;
358 static int davinci_writepage_tail(struct nand_device
*nand
,
359 uint8_t *oob
, uint32_t oob_size
)
361 struct davinci_nand
*info
= nand
->controller_priv
;
362 struct target
*target
= nand
->target
;
366 davinci_write_block_data(nand
, oob
, oob_size
);
368 /* non-cachemode page program */
369 target_write_u8(target
, info
->cmd
, NAND_CMD_PAGEPROG
);
371 if (!davinci_nand_ready(nand
, 100))
372 return ERROR_NAND_OPERATION_TIMEOUT
;
374 if (nand_read_status(nand
, &status
) != ERROR_OK
) {
375 LOG_ERROR("couldn't read status");
376 return ERROR_NAND_OPERATION_FAILED
;
379 if (status
& NAND_STATUS_FAIL
) {
380 LOG_ERROR("write operation failed, status: 0x%02x", status
);
381 return ERROR_NAND_OPERATION_FAILED
;
388 * All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
390 static int davinci_write_page_ecc1(struct nand_device
*nand
, uint32_t page
,
391 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
394 struct davinci_nand
*info
= nand
->controller_priv
;
395 struct target
*target
= nand
->target
;
396 const uint32_t fcr_addr
= info
->aemif
+ NANDFCR
;
397 const uint32_t ecc1_addr
= info
->aemif
+ NANDFECC
+ (4 * info
->chipsel
);
400 /* Write contiguous ECC bytes starting at specified offset.
401 * NOTE: Linux reserves twice as many bytes as we need; and
402 * for 16-bit OOB, those extra bytes are discontiguous.
404 switch (nand
->page_size
) {
416 davinci_write_pagecmd(nand
, NAND_CMD_SEQIN
, page
);
418 /* scrub any old ECC state */
419 target_read_u32(target
, ecc1_addr
, &ecc1
);
421 target_read_u32(target
, fcr_addr
, &fcr
);
422 fcr
|= 1 << (8 + info
->chipsel
);
425 /* set "start csX 1bit ecc" bit */
426 target_write_u32(target
, fcr_addr
, fcr
);
428 /* write 512 bytes */
429 davinci_write_block_data(nand
, data
, 512);
433 /* read the ecc, pack to 3 bytes, and invert so the ecc
434 * in an erased block is correct
436 target_read_u32(target
, ecc1_addr
, &ecc1
);
437 ecc1
= (ecc1
& 0x0fff) | ((ecc1
& 0x0fff0000) >> 4);
440 /* save correct ECC code into oob data */
441 oob
[oob_offset
++] = (uint8_t)(ecc1
);
442 oob
[oob_offset
++] = (uint8_t)(ecc1
>> 8);
443 oob
[oob_offset
++] = (uint8_t)(ecc1
>> 16);
447 /* write OOB into spare area */
448 return davinci_writepage_tail(nand
, oob
, oob_size
);
452 * Preferred "new style" ECC layout for use with 4-bit ECC. This somewhat
453 * slows down large page reads done with error correction (since the OOB
454 * is read first, so its ECC data can be used incrementally), but the
455 * manufacturer bad block markers are safe. Contrast: old "infix" style.
457 static int davinci_write_page_ecc4(struct nand_device
*nand
, uint32_t page
,
458 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
460 static const uint8_t ecc512
[] = {
461 0, 1, 2, 3, 4, /* 5== mfr badblock */
462 6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15,
464 static const uint8_t ecc2048
[] = {
465 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
466 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
467 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
468 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
470 static const uint8_t ecc4096
[] = {
471 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
472 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
473 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
474 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
475 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
476 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
477 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
478 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
481 struct davinci_nand
*info
= nand
->controller_priv
;
483 struct target
*target
= nand
->target
;
484 const uint32_t fcr_addr
= info
->aemif
+ NANDFCR
;
485 const uint32_t ecc4_addr
= info
->aemif
+ NAND4BITECC
;
488 /* Use the same ECC layout Linux uses. For small page chips
489 * it's a bit cramped.
491 * NOTE: at this writing, 4KB pages have issues in Linux
492 * because they need more than 64 bytes of ECC data, which
493 * the standard ECC logic can't handle.
495 switch (nand
->page_size
) {
507 davinci_write_pagecmd(nand
, NAND_CMD_SEQIN
, page
);
509 /* scrub any old ECC state */
510 target_read_u32(target
, info
->aemif
+ NANDERRVAL
, &ecc4
);
512 target_read_u32(target
, fcr_addr
, &fcr
);
514 fcr
|= (1 << 12) | (info
->chipsel
<< 4);
517 uint32_t raw_ecc
[4], *p
;
520 /* start 4bit ecc on csX */
521 target_write_u32(target
, fcr_addr
, fcr
);
523 /* write 512 bytes */
524 davinci_write_block_data(nand
, data
, 512);
528 /* read the ecc, then save it into 10 bytes in the oob */
529 for (i
= 0; i
< 4; i
++) {
530 target_read_u32(target
, ecc4_addr
+ 4 * i
, &raw_ecc
[i
]);
531 raw_ecc
[i
] &= 0x03ff03ff;
533 for (i
= 0, p
= raw_ecc
; i
< 2; i
++, p
+= 2) {
534 oob
[*l
++] = p
[0] & 0xff;
535 oob
[*l
++] = ((p
[0] >> 8) & 0x03) | ((p
[0] >> 14) & 0xfc);
536 oob
[*l
++] = ((p
[0] >> 22) & 0x0f) | ((p
[1] << 4) & 0xf0);
537 oob
[*l
++] = ((p
[1] >> 4) & 0x3f) | ((p
[1] >> 10) & 0xc0);
538 oob
[*l
++] = (p
[1] >> 18) & 0xff;
543 /* write OOB into spare area */
544 return davinci_writepage_tail(nand
, oob
, oob_size
);
548 * "Infix" OOB ... like Linux ECC_HW_SYNDROME. Avoided because it trashes
549 * manufacturer bad block markers, except on small page chips. Once you
550 * write to a page using this scheme, you need specialized code to update
551 * it (code which ignores now-invalid bad block markers).
553 * This is needed *only* to support older firmware. Older ROM Boot Loaders
554 * need it to read their second stage loader (UBL) into SRAM, but from then
555 * on the whole system can use the cleaner non-infix layouts. Systems with
556 * older second stage loaders (ABL/U-Boot, etc) or other system software
557 * (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
559 static int davinci_write_page_ecc4infix(struct nand_device
*nand
, uint32_t page
,
560 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
562 struct davinci_nand
*info
= nand
->controller_priv
;
563 struct target
*target
= nand
->target
;
564 const uint32_t fcr_addr
= info
->aemif
+ NANDFCR
;
565 const uint32_t ecc4_addr
= info
->aemif
+ NAND4BITECC
;
568 davinci_write_pagecmd(nand
, NAND_CMD_SEQIN
, page
);
570 /* scrub any old ECC state */
571 target_read_u32(target
, info
->aemif
+ NANDERRVAL
, &ecc4
);
573 target_read_u32(target
, fcr_addr
, &fcr
);
575 fcr
|= (1 << 12) | (info
->chipsel
<< 4);
578 uint32_t raw_ecc
[4], *p
;
582 /* start 4bit ecc on csX */
583 target_write_u32(target
, fcr_addr
, fcr
);
585 /* write 512 bytes */
586 davinci_write_block_data(nand
, data
, 512);
591 for (i
= 0; i
< 4; i
++) {
592 target_read_u32(target
, ecc4_addr
+ 4 * i
, &raw_ecc
[i
]);
593 raw_ecc
[i
] &= 0x03ff03ff;
596 /* skip 6 bytes of prepad, then pack 10 packed ecc bytes */
597 for (i
= 0, l
= oob
+ 6, p
= raw_ecc
; i
< 2; i
++, p
+= 2) {
599 *l
++ = ((p
[0] >> 8) & 0x03) | ((p
[0] >> 14) & 0xfc);
600 *l
++ = ((p
[0] >> 22) & 0x0f) | ((p
[1] << 4) & 0xf0);
601 *l
++ = ((p
[1] >> 4) & 0x3f) | ((p
[1] >> 10) & 0xc0);
602 *l
++ = (p
[1] >> 18) & 0xff;
605 /* write this "out-of-band" data -- infix */
606 davinci_write_block_data(nand
, oob
, 16);
612 /* the last data and OOB writes included the spare area */
613 return davinci_writepage_tail(nand
, NULL
, 0);
616 static int davinci_read_page_ecc4infix(struct nand_device
*nand
, uint32_t page
,
617 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
620 int want_col
, at_col
;
623 davinci_write_pagecmd(nand
, NAND_CMD_READ0
, page
);
625 /* large page devices need a start command */
626 if (nand
->page_size
> 512)
627 davinci_command(nand
, NAND_CMD_READSTART
);
629 if (!davinci_nand_ready(nand
, 100))
630 return ERROR_NAND_OPERATION_TIMEOUT
;
632 /* NOTE: not bothering to compute and use ECC data for now */
636 while ((data
&& data_size
) || (oob
&& oob_size
)) {
638 if (data
&& data_size
) {
639 if (want_col
!= at_col
) {
640 /* Reads are slow, so seek past them when we can */
641 ret
= davinci_seek_column(nand
, want_col
);
646 /* read 512 bytes or data_size, whichever is smaller*/
647 read_size
= data_size
> 512 ? 512 : data_size
;
648 davinci_read_block_data(nand
, data
, read_size
);
650 data_size
-= read_size
;
655 if (oob
&& oob_size
) {
656 if (want_col
!= at_col
) {
657 ret
= davinci_seek_column(nand
, want_col
);
662 /* read this "out-of-band" data -- infix */
663 read_size
= oob_size
> 16 ? 16 : oob_size
;
664 davinci_read_block_data(nand
, oob
, read_size
);
666 oob_size
-= read_size
;
674 NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command
)
676 struct davinci_nand
*info
;
677 unsigned long chip
, aemif
;
684 * - nand chip address
687 * Plus someday, optionally, ALE and CLE masks.
690 return ERROR_COMMAND_SYNTAX_ERROR
;
692 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[2], chip
);
694 LOG_ERROR("Invalid NAND chip address %s", CMD_ARGV
[2]);
698 if (strcmp(CMD_ARGV
[3], "hwecc1") == 0)
700 else if (strcmp(CMD_ARGV
[3], "hwecc4") == 0)
702 else if (strcmp(CMD_ARGV
[3], "hwecc4_infix") == 0)
703 eccmode
= HWECC4_INFIX
;
705 LOG_ERROR("Invalid ecc mode %s", CMD_ARGV
[3]);
709 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[4], aemif
);
711 LOG_ERROR("Invalid AEMIF controller address %s", CMD_ARGV
[4]);
715 /* REVISIT what we'd *like* to do is look up valid ranges using
716 * target-specific declarations, and not even need to pass the
717 * AEMIF controller address.
719 if (aemif
== 0x01e00000 /* dm6446, dm357 */
720 || aemif
== 0x01e10000 /* dm335, dm355 */
721 || aemif
== 0x01d10000 /* dm365 */
723 if (chip
< 0x02000000 || chip
>= 0x0a000000) {
724 LOG_ERROR("NAND address %08lx out of range?", chip
);
727 chipsel
= (chip
- 0x02000000) >> 25;
729 LOG_ERROR("unrecognized AEMIF controller address %08lx", aemif
);
733 info
= calloc(1, sizeof *info
);
737 info
->eccmode
= eccmode
;
738 info
->chipsel
= chipsel
;
741 info
->cmd
= chip
| 0x10;
742 info
->addr
= chip
| 0x08;
744 nand
->controller_priv
= info
;
746 info
->io
.target
= nand
->target
;
747 info
->io
.data
= info
->data
;
748 info
->io
.op
= ARM_NAND_NONE
;
750 /* NOTE: for now we don't do any error correction on read.
751 * Nothing else in OpenOCD currently corrects read errors,
752 * and in any case it's *writing* that we care most about.
754 info
->read_page
= nand_read_page_raw
;
758 /* ECC_HW, 1-bit corrections, 3 bytes ECC per 512 data bytes */
759 info
->write_page
= davinci_write_page_ecc1
;
762 /* ECC_HW, 4-bit corrections, 10 bytes ECC per 512 data bytes */
763 info
->write_page
= davinci_write_page_ecc4
;
766 /* Same 4-bit ECC HW, with problematic page/ecc layout */
767 info
->read_page
= davinci_read_page_ecc4infix
;
768 info
->write_page
= davinci_write_page_ecc4infix
;
775 return ERROR_NAND_OPERATION_FAILED
;
778 struct nand_flash_controller davinci_nand_controller
= {
780 .usage
= "chip_addr hwecc_mode aemif_addr",
781 .nand_device_command
= davinci_nand_device_command
,
782 .init
= davinci_init
,
783 .reset
= davinci_reset
,
784 .command
= davinci_command
,
785 .address
= davinci_address
,
786 .write_data
= davinci_write_data
,
787 .read_data
= davinci_read_data
,
788 .write_page
= davinci_write_page
,
789 .read_page
= davinci_read_page
,
790 .write_block_data
= davinci_write_block_data
,
791 .read_block_data
= davinci_read_block_data
,
792 .nand_ready
= davinci_nand_ready
,