1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A
34 copy of the license is included in the section entitled ``GNU Free
35 Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
100 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
101 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
106 @section What is OpenOCD?
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board connect directly to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD supports only
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
153 USB-based, parallel port-based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
158 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
159 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
161 @b{Flash Programming:} Flash writing is supported for external
162 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
164 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
165 controllers (LPC3180, Orion, S3C24xx, more) is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{http://openocd.org/}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published regularly at:
179 @uref{http://openocd.org/doc/html/index.html}
181 PDF form is likewise published at:
183 @uref{http://openocd.org/doc/pdf/openocd.pdf}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
195 @section OpenOCD User's Mailing List
197 The OpenOCD User Mailing List provides the primary means of
198 communication between users:
200 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
204 Support can also be found on irc:
205 @uref{irc://irc.libera.chat/openocd}
208 @chapter OpenOCD Developer Resources
211 If you are interested in improving the state of OpenOCD's debugging and
212 testing support, new contributions will be welcome. Motivated developers
213 can produce new target, flash or interface drivers, improve the
214 documentation, as well as more conventional bug fixes and enhancements.
216 The resources in this chapter are available for developers wishing to explore
217 or expand the OpenOCD source code.
219 @section OpenOCD Git Repository
221 During the 0.3.x release cycle, OpenOCD switched from Subversion to
222 a Git repository hosted at SourceForge. The repository URL is:
224 @uref{git://git.code.sf.net/p/openocd/code}
228 @uref{http://git.code.sf.net/p/openocd/code}
230 You may prefer to use a mirror and the HTTP protocol:
232 @uref{http://repo.or.cz/r/openocd.git}
234 With standard Git tools, use @command{git clone} to initialize
235 a local repository, and @command{git pull} to update it.
236 There are also gitweb pages letting you browse the repository
237 with a web browser, or download arbitrary snapshots without
238 needing a Git client:
240 @uref{http://repo.or.cz/w/openocd.git}
242 The @file{README} file contains the instructions for building the project
243 from the repository or a snapshot.
245 Developers that want to contribute patches to the OpenOCD system are
246 @b{strongly} encouraged to work against mainline.
247 Patches created against older versions may require additional
248 work from their submitter in order to be updated for newer releases.
250 @section Doxygen Developer Manual
252 During the 0.2.x release cycle, the OpenOCD project began
253 providing a Doxygen reference manual. This document contains more
254 technical information about the software internals, development
255 processes, and similar documentation:
257 @uref{http://openocd.org/doc/doxygen/html/index.html}
259 This document is a work-in-progress, but contributions would be welcome
260 to fill in the gaps. All of the source files are provided in-tree,
261 listed in the Doxyfile configuration at the top of the source tree.
263 @section Gerrit Review System
265 All changes in the OpenOCD Git repository go through the web-based Gerrit
268 @uref{https://review.openocd.org/}
270 After a one-time registration and repository setup, anyone can push commits
271 from their local Git repository directly into Gerrit.
272 All users and developers are encouraged to review, test, discuss and vote
273 for changes in Gerrit. The feedback provides the basis for a maintainer to
274 eventually submit the change to the main Git repository.
276 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
277 Developer Manual, contains basic information about how to connect a
278 repository to Gerrit, prepare and push patches. Patch authors are expected to
279 maintain their changes while they're in Gerrit, respond to feedback and if
280 necessary rework and push improved versions of the change.
282 @section OpenOCD Developer Mailing List
284 The OpenOCD Developer Mailing List provides the primary means of
285 communication between developers:
287 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
289 @section OpenOCD Bug Tracker
291 The OpenOCD Bug Tracker is hosted on SourceForge:
293 @uref{http://bugs.openocd.org/}
296 @node Debug Adapter Hardware
297 @chapter Debug Adapter Hardware
305 Defined: @b{dongle}: A small device that plugs into a computer and serves as
306 an adapter .... [snip]
308 In the OpenOCD case, this generally refers to @b{a small adapter} that
309 attaches to your computer via USB or the parallel port.
312 @section Choosing a Dongle
314 There are several things you should keep in mind when choosing a dongle.
317 @item @b{Transport} Does it support the kind of communication that you need?
318 OpenOCD focuses mostly on JTAG. Your version may also support
319 other ways to communicate with target devices.
320 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
321 Does your dongle support it? You might need a level converter.
322 @item @b{Pinout} What pinout does your target board use?
323 Does your dongle support it? You may be able to use jumper
324 wires, or an "octopus" connector, to convert pinouts.
325 @item @b{Connection} Does your computer have the USB, parallel, or
326 Ethernet port needed?
327 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
328 RTCK support (also known as ``adaptive clocking'')?
331 @section USB FT2232 Based
333 There are many USB JTAG dongles on the market, many of them based
334 on a chip from ``Future Technology Devices International'' (FTDI)
335 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
336 See: @url{http://www.ftdichip.com} for more information.
337 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
338 chips started to become available in JTAG adapters. Around 2012, a new
339 variant appeared - FT232H - this is a single-channel version of FT2232H.
340 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
343 The FT2232 chips are flexible enough to support some other
344 transport options, such as SWD or the SPI variants used to
345 program some chips. They have two communications channels,
346 and one can be used for a UART adapter at the same time the
347 other one is used to provide a debug adapter.
349 Also, some development boards integrate an FT2232 chip to serve as
350 a built-in low-cost debug adapter and USB-to-serial solution.
354 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
356 @* See: @url{http://www.amontec.com/jtagkey.shtml}
358 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
360 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
362 @* See: @url{http://www.signalyzer.com}
363 @item @b{Stellaris Eval Boards}
364 @* See: @url{http://www.ti.com} - The Stellaris eval boards
365 bundle FT2232-based JTAG and SWD support, which can be used to debug
366 the Stellaris chips. Using separate JTAG adapters is optional.
367 These boards can also be used in a "pass through" mode as JTAG adapters
368 to other target boards, disabling the Stellaris chip.
369 @item @b{TI/Luminary ICDI}
370 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
371 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
372 Evaluation Kits. Like the non-detachable FT2232 support on the other
373 Stellaris eval boards, they can be used to debug other target boards.
374 @item @b{olimex-jtag}
375 @* See: @url{http://www.olimex.com}
376 @item @b{Flyswatter/Flyswatter2}
377 @* See: @url{http://www.tincantools.com}
378 @item @b{turtelizer2}
380 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
381 @url{http://www.ethernut.de}
383 @* Link: @url{http://www.hitex.com/index.php?id=383}
385 @* Link @url{http://www.hitex.com/stm32-stick}
386 @item @b{axm0432_jtag}
387 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
388 to be available anymore as of April 2012.
390 @* Link @url{http://www.hitex.com/index.php?id=cortino}
391 @item @b{dlp-usb1232h}
392 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
393 @item @b{digilent-hs1}
394 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
396 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
398 @item @b{JTAG-lock-pick Tiny 2}
399 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
402 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
406 @section USB-JTAG / Altera USB-Blaster compatibles
408 These devices also show up as FTDI devices, but are not
409 protocol-compatible with the FT2232 devices. They are, however,
410 protocol-compatible among themselves. USB-JTAG devices typically consist
411 of a FT245 followed by a CPLD that understands a particular protocol,
412 or emulates this protocol using some other hardware.
414 They may appear under different USB VID/PID depending on the particular
415 product. The driver can be configured to search for any VID/PID pair
416 (see the section on driver commands).
419 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
420 @* Link: @url{http://ixo-jtag.sourceforge.net/}
421 @item @b{Altera USB-Blaster}
422 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
425 @section USB J-Link based
426 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
427 an example of a microcontroller based JTAG adapter, it uses an
428 AT91SAM764 internally.
431 @item @b{SEGGER J-Link}
432 @* Link: @url{http://www.segger.com/jlink.html}
433 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
434 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
438 @section USB RLINK based
439 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
440 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
441 SWD and not JTAG, thus not supported.
444 @item @b{Raisonance RLink}
445 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
446 @item @b{STM32 Primer}
447 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
448 @item @b{STM32 Primer2}
449 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
452 @section USB ST-LINK based
453 STMicroelectronics has an adapter called @b{ST-LINK}.
454 They only work with STMicroelectronics chips, notably STM32 and STM8.
458 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
459 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
461 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
462 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
464 @* This is available standalone and as part of some kits.
465 @* Link: @url{http://www.st.com/stlink-v3}
468 For info the original ST-LINK enumerates using the mass storage usb class; however,
469 its implementation is completely broken. The result is this causes issues under Linux.
470 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
472 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
473 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
476 @section USB TI/Stellaris ICDI based
477 Texas Instruments has an adapter called @b{ICDI}.
478 It is not to be confused with the FTDI based adapters that were originally fitted to their
479 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
481 @section USB Nuvoton Nu-Link
482 Nuvoton has an adapter called @b{Nu-Link}.
483 It is available either as stand-alone dongle and embedded on development boards.
484 It supports SWD, serial port bridge and mass storage for firmware update.
485 Both Nu-Link v1 and v2 are supported.
487 @section USB CMSIS-DAP based
488 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
489 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
494 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
496 @item @b{USB - Presto}
497 @* Link: @url{http://tools.asix.net/prg_presto.htm}
499 @item @b{Versaloon-Link}
500 @* Link: @url{http://www.versaloon.com}
502 @item @b{ARM-JTAG-EW}
503 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
506 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
509 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
512 @* Link: @url{http://code.google.com/p/estick-jtag/}
514 @item @b{Keil ULINK v1}
515 @* Link: @url{http://www.keil.com/ulink1/}
517 @item @b{TI XDS110 Debug Probe}
518 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds110.html}
519 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html#xds110-support-utilities}
522 @section IBM PC Parallel Printer Port Based
524 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
525 and the Macraigor Wiggler. There are many clones and variations of
528 Note that parallel ports are becoming much less common, so if you
529 have the choice you should probably avoid these adapters in favor
534 @item @b{Wiggler} - There are many clones of this.
535 @* Link: @url{http://www.macraigor.com/wiggler.htm}
537 @item @b{DLC5} - From XILINX - There are many clones of this
538 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
539 produced, PDF schematics are easily found and it is easy to make.
541 @item @b{Amontec - JTAG Accelerator}
542 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
545 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
547 @item @b{Wiggler_ntrst_inverted}
548 @* Yet another variation - See the source code, src/jtag/parport.c
550 @item @b{old_amt_wiggler}
551 @* Unknown - probably not on the market today
554 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
557 @* Link: @url{http://www.amontec.com/chameleon.shtml}
563 @* ispDownload from Lattice Semiconductor
564 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
567 @* From STMicroelectronics;
568 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
576 @* An EP93xx based Linux machine using the GPIO pins directly.
579 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
581 @item @b{bcm2835gpio}
582 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
585 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
588 @* A Texas Instruments AM335x-based board (e.g. BeagleBone Black) using the GPIO pins of the expansion headers.
591 @* A JTAG driver acting as a client for the JTAG VPI server interface.
592 @* Link: @url{http://github.com/fjullien/jtag_vpi}
595 @* A driver for Cadence virtual Debug Interface to emulated or simulated targets.
596 It implements a client connecting to the vdebug server, which in turn communicates
597 with the emulated or simulated RTL model through a transactor. The current version
598 supports only JTAG as a transport, but other virtual transports, like DAP are planned.
601 @* A JTAG driver acting as a client for the SystemVerilog Direct Programming
602 Interface (DPI) for JTAG devices. DPI allows OpenOCD to connect to the JTAG
603 interface of a hardware model written in SystemVerilog, for example, on an
604 emulation model of target hardware.
606 @item @b{xlnx_pcie_xvc}
607 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
610 @* A bitbang JTAG driver using Linux GPIO through library libgpiod.
613 @* A bitbang JTAG driver using Linux legacy sysfs GPIO.
614 This is deprecated from Linux v5.3; prefer using @b{linuxgpiod}.
616 @item @b{esp_usb_jtag}
617 @* A JTAG driver to communicate with builtin debug modules of Espressif ESP32-C3 and ESP32-S3 chips using OpenOCD.
622 @chapter About Jim-Tcl
626 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
627 This programming language provides a simple and extensible
630 All commands presented in this Guide are extensions to Jim-Tcl.
631 You can use them as simple commands, without needing to learn
632 much of anything about Tcl.
633 Alternatively, you can write Tcl programs with them.
635 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
636 There is an active and responsive community, get on the mailing list
637 if you have any questions. Jim-Tcl maintainers also lurk on the
638 OpenOCD mailing list.
641 @item @b{Jim vs. Tcl}
642 @* Jim-Tcl is a stripped down version of the well known Tcl language,
643 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
644 fewer features. Jim-Tcl is several dozens of .C files and .H files and
645 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
646 4.2 MB .zip file containing 1540 files.
648 @item @b{Missing Features}
649 @* Our practice has been: Add/clone the real Tcl feature if/when
650 needed. We welcome Jim-Tcl improvements, not bloat. Also there
651 are a large number of optional Jim-Tcl features that are not
655 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
656 command interpreter today is a mixture of (newer)
657 Jim-Tcl commands, and the (older) original command interpreter.
660 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
661 can type a Tcl for() loop, set variables, etc.
662 Some of the commands documented in this guide are implemented
663 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
665 @item @b{Historical Note}
666 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
667 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
668 as a Git submodule, which greatly simplified upgrading Jim-Tcl
669 to benefit from new features and bugfixes in Jim-Tcl.
671 @item @b{Need a crash course in Tcl?}
672 @*@xref{Tcl Crash Course}.
677 @cindex command line options
679 @cindex directory search
681 Properly installing OpenOCD sets up your operating system to grant it access
682 to the debug adapters. On Linux, this usually involves installing a file
683 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
684 that works for many common adapters is shipped with OpenOCD in the
685 @file{contrib} directory. MS-Windows needs
686 complex and confusing driver configuration for every peripheral. Such issues
687 are unique to each operating system, and are not detailed in this User's Guide.
689 Then later you will invoke the OpenOCD server, with various options to
690 tell it how each debug session should work.
691 The @option{--help} option shows:
695 --help | -h display this help
696 --version | -v display OpenOCD version
697 --file | -f use configuration file <name>
698 --search | -s dir to search for config files and scripts
699 --debug | -d set debug level to 3
700 | -d<n> set debug level to <level>
701 --log_output | -l redirect log output to file <name>
702 --command | -c run <command>
705 If you don't give any @option{-f} or @option{-c} options,
706 OpenOCD tries to read the configuration file @file{openocd.cfg}.
707 To specify one or more different
708 configuration files, use @option{-f} options. For example:
711 openocd -f config1.cfg -f config2.cfg -f config3.cfg
714 Configuration files and scripts are searched for in
716 @item the current directory,
717 @item any search dir specified on the command line using the @option{-s} option,
718 @item any search dir specified using the @command{add_script_search_dir} command,
719 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
720 @item @file{%APPDATA%/OpenOCD} (only on Windows),
721 @item @file{$HOME/Library/Preferences/org.openocd} (only on Darwin),
722 @item @file{$XDG_CONFIG_HOME/openocd} (@env{$XDG_CONFIG_HOME} defaults to @file{$HOME/.config}),
723 @item @file{$HOME/.openocd},
724 @item the site wide script library @file{$pkgdatadir/site} and
725 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
727 The first found file with a matching file name will be used.
730 Don't try to use configuration script names or paths which
731 include the "#" character. That character begins Tcl comments.
734 @section Simple setup, no customization
736 In the best case, you can use two scripts from one of the script
737 libraries, hook up your JTAG adapter, and start the server ... and
738 your JTAG setup will just work "out of the box". Always try to
739 start by reusing those scripts, but assume you'll need more
740 customization even if this works. @xref{OpenOCD Project Setup}.
742 If you find a script for your JTAG adapter, and for your board or
743 target, you may be able to hook up your JTAG adapter then start
744 the server with some variation of one of the following:
747 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
748 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
751 You might also need to configure which reset signals are present,
752 using @option{-c 'reset_config trst_and_srst'} or something similar.
753 If all goes well you'll see output something like
756 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
757 For bug reports, read
758 http://openocd.org/doc/doxygen/bugs.html
759 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
760 (mfg: 0x23b, part: 0xba00, ver: 0x3)
763 Seeing that "tap/device found" message, and no warnings, means
764 the JTAG communication is working. That's a key milestone, but
765 you'll probably need more project-specific setup.
767 @section What OpenOCD does as it starts
769 OpenOCD starts by processing the configuration commands provided
770 on the command line or, if there were no @option{-c command} or
771 @option{-f file.cfg} options given, in @file{openocd.cfg}.
772 @xref{configurationstage,,Configuration Stage}.
773 At the end of the configuration stage it verifies the JTAG scan
774 chain defined using those commands; your configuration should
775 ensure that this always succeeds.
776 Normally, OpenOCD then starts running as a server.
777 Alternatively, commands may be used to terminate the configuration
778 stage early, perform work (such as updating some flash memory),
779 and then shut down without acting as a server.
781 Once OpenOCD starts running as a server, it waits for connections from
782 clients (Telnet, GDB, RPC) and processes the commands issued through
785 If you are having problems, you can enable internal debug messages via
786 the @option{-d} option.
788 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
789 @option{-c} command line switch.
791 To enable debug output (when reporting problems or working on OpenOCD
792 itself), use the @option{-d} command line switch. This sets the
793 @option{debug_level} to "3", outputting the most information,
794 including debug messages. The default setting is "2", outputting only
795 informational messages, warnings and errors. You can also change this
796 setting from within a telnet or gdb session using @command{debug_level<n>}
797 (@pxref{debuglevel,,debug_level}).
799 You can redirect all output from the server to a file using the
800 @option{-l <logfile>} switch.
802 Note! OpenOCD will launch the GDB & telnet server even if it can not
803 establish a connection with the target. In general, it is possible for
804 the JTAG controller to be unresponsive until the target is set up
805 correctly via e.g. GDB monitor commands in a GDB init script.
807 @node OpenOCD Project Setup
808 @chapter OpenOCD Project Setup
810 To use OpenOCD with your development projects, you need to do more than
811 just connect the JTAG adapter hardware (dongle) to your development board
812 and start the OpenOCD server.
813 You also need to configure your OpenOCD server so that it knows
814 about your adapter and board, and helps your work.
815 You may also want to connect OpenOCD to GDB, possibly
816 using Eclipse or some other GUI.
818 @section Hooking up the JTAG Adapter
820 Today's most common case is a dongle with a JTAG cable on one side
821 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
822 and a USB cable on the other.
823 Instead of USB, some dongles use Ethernet;
824 older ones may use a PC parallel port, or even a serial port.
827 @item @emph{Start with power to your target board turned off},
828 and nothing connected to your JTAG adapter.
829 If you're particularly paranoid, unplug power to the board.
830 It's important to have the ground signal properly set up,
831 unless you are using a JTAG adapter which provides
832 galvanic isolation between the target board and the
835 @item @emph{Be sure it's the right kind of JTAG connector.}
836 If your dongle has a 20-pin ARM connector, you need some kind
837 of adapter (or octopus, see below) to hook it up to
838 boards using 14-pin or 10-pin connectors ... or to 20-pin
839 connectors which don't use ARM's pinout.
841 In the same vein, make sure the voltage levels are compatible.
842 Not all JTAG adapters have the level shifters needed to work
843 with 1.2 Volt boards.
845 @item @emph{Be certain the cable is properly oriented} or you might
846 damage your board. In most cases there are only two possible
847 ways to connect the cable.
848 Connect the JTAG cable from your adapter to the board.
849 Be sure it's firmly connected.
851 In the best case, the connector is keyed to physically
852 prevent you from inserting it wrong.
853 This is most often done using a slot on the board's male connector
854 housing, which must match a key on the JTAG cable's female connector.
855 If there's no housing, then you must look carefully and
856 make sure pin 1 on the cable hooks up to pin 1 on the board.
857 Ribbon cables are frequently all grey except for a wire on one
858 edge, which is red. The red wire is pin 1.
860 Sometimes dongles provide cables where one end is an ``octopus'' of
861 color coded single-wire connectors, instead of a connector block.
862 These are great when converting from one JTAG pinout to another,
863 but are tedious to set up.
864 Use these with connector pinout diagrams to help you match up the
865 adapter signals to the right board pins.
867 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
868 A USB, parallel, or serial port connector will go to the host which
869 you are using to run OpenOCD.
870 For Ethernet, consult the documentation and your network administrator.
872 For USB-based JTAG adapters you have an easy sanity check at this point:
873 does the host operating system see the JTAG adapter? If you're running
874 Linux, try the @command{lsusb} command. If that host is an
875 MS-Windows host, you'll need to install a driver before OpenOCD works.
877 @item @emph{Connect the adapter's power supply, if needed.}
878 This step is primarily for non-USB adapters,
879 but sometimes USB adapters need extra power.
881 @item @emph{Power up the target board.}
882 Unless you just let the magic smoke escape,
883 you're now ready to set up the OpenOCD server
884 so you can use JTAG to work with that board.
888 Talk with the OpenOCD server using
889 telnet (@code{telnet localhost 4444} on many systems) or GDB.
890 @xref{GDB and OpenOCD}.
892 @section Project Directory
894 There are many ways you can configure OpenOCD and start it up.
896 A simple way to organize them all involves keeping a
897 single directory for your work with a given board.
898 When you start OpenOCD from that directory,
899 it searches there first for configuration files, scripts,
900 files accessed through semihosting,
901 and for code you upload to the target board.
902 It is also the natural place to write files,
903 such as log files and data you download from the board.
905 @section Configuration Basics
907 There are two basic ways of configuring OpenOCD, and
908 a variety of ways you can mix them.
909 Think of the difference as just being how you start the server:
912 @item Many @option{-f file} or @option{-c command} options on the command line
913 @item No options, but a @dfn{user config file}
914 in the current directory named @file{openocd.cfg}
917 Here is an example @file{openocd.cfg} file for a setup
918 using a Signalyzer FT2232-based JTAG adapter to talk to
919 a board with an Atmel AT91SAM7X256 microcontroller:
922 source [find interface/ftdi/signalyzer.cfg]
924 # GDB can also flash my flash!
925 gdb_memory_map enable
926 gdb_flash_program enable
928 source [find target/sam7x256.cfg]
931 Here is the command line equivalent of that configuration:
934 openocd -f interface/ftdi/signalyzer.cfg \
935 -c "gdb_memory_map enable" \
936 -c "gdb_flash_program enable" \
937 -f target/sam7x256.cfg
940 You could wrap such long command lines in shell scripts,
941 each supporting a different development task.
942 One might re-flash the board with a specific firmware version.
943 Another might set up a particular debugging or run-time environment.
946 At this writing (October 2009) the command line method has
947 problems with how it treats variables.
948 For example, after @option{-c "set VAR value"}, or doing the
949 same in a script, the variable @var{VAR} will have no value
950 that can be tested in a later script.
953 Here we will focus on the simpler solution: one user config
954 file, including basic configuration plus any TCL procedures
955 to simplify your work.
957 @section User Config Files
958 @cindex config file, user
959 @cindex user config file
960 @cindex config file, overview
962 A user configuration file ties together all the parts of a project
964 One of the following will match your situation best:
967 @item Ideally almost everything comes from configuration files
968 provided by someone else.
969 For example, OpenOCD distributes a @file{scripts} directory
970 (probably in @file{/usr/share/openocd/scripts} on Linux).
971 Board and tool vendors can provide these too, as can individual
972 user sites; the @option{-s} command line option lets you say
973 where to find these files. (@xref{Running}.)
974 The AT91SAM7X256 example above works this way.
976 Three main types of non-user configuration file each have their
977 own subdirectory in the @file{scripts} directory:
980 @item @b{interface} -- one for each different debug adapter;
981 @item @b{board} -- one for each different board
982 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
985 Best case: include just two files, and they handle everything else.
986 The first is an interface config file.
987 The second is board-specific, and it sets up the JTAG TAPs and
988 their GDB targets (by deferring to some @file{target.cfg} file),
989 declares all flash memory, and leaves you nothing to do except
993 source [find interface/olimex-jtag-tiny.cfg]
994 source [find board/csb337.cfg]
997 Boards with a single microcontroller often won't need more
998 than the target config file, as in the AT91SAM7X256 example.
999 That's because there is no external memory (flash, DDR RAM), and
1000 the board differences are encapsulated by application code.
1002 @item Maybe you don't know yet what your board looks like to JTAG.
1003 Once you know the @file{interface.cfg} file to use, you may
1004 need help from OpenOCD to discover what's on the board.
1005 Once you find the JTAG TAPs, you can just search for appropriate
1007 configuration files ... or write your own, from the bottom up.
1008 @xref{autoprobing,,Autoprobing}.
1010 @item You can often reuse some standard config files but
1011 need to write a few new ones, probably a @file{board.cfg} file.
1012 You will be using commands described later in this User's Guide,
1013 and working with the guidelines in the next chapter.
1015 For example, there may be configuration files for your JTAG adapter
1016 and target chip, but you need a new board-specific config file
1017 giving access to your particular flash chips.
1018 Or you might need to write another target chip configuration file
1019 for a new chip built around the Cortex-M3 core.
1022 When you write new configuration files, please submit
1023 them for inclusion in the next OpenOCD release.
1024 For example, a @file{board/newboard.cfg} file will help the
1025 next users of that board, and a @file{target/newcpu.cfg}
1026 will help support users of any board using that chip.
1030 You may need to write some C code.
1031 It may be as simple as supporting a new FT2232 or parport
1032 based adapter; a bit more involved, like a NAND or NOR flash
1033 controller driver; or a big piece of work like supporting
1034 a new chip architecture.
1037 Reuse the existing config files when you can.
1038 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1039 You may find a board configuration that's a good example to follow.
1041 When you write config files, separate the reusable parts
1042 (things every user of that interface, chip, or board needs)
1043 from ones specific to your environment and debugging approach.
1047 For example, a @code{gdb-attach} event handler that invokes
1048 the @command{reset init} command will interfere with debugging
1049 early boot code, which performs some of the same actions
1050 that the @code{reset-init} event handler does.
1053 Likewise, the @command{arm9 vector_catch} command (or
1054 @cindex vector_catch
1055 its siblings @command{xscale vector_catch}
1056 and @command{cortex_m vector_catch}) can be a time-saver
1057 during some debug sessions, but don't make everyone use that either.
1058 Keep those kinds of debugging aids in your user config file,
1059 along with messaging and tracing setup.
1060 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1063 You might need to override some defaults.
1064 For example, you might need to move, shrink, or back up the target's
1065 work area if your application needs much SRAM.
1068 TCP/IP port configuration is another example of something which
1069 is environment-specific, and should only appear in
1070 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1073 @section Project-Specific Utilities
1075 A few project-specific utility
1076 routines may well speed up your work.
1077 Write them, and keep them in your project's user config file.
1079 For example, if you are making a boot loader work on a
1080 board, it's nice to be able to debug the ``after it's
1081 loaded to RAM'' parts separately from the finicky early
1082 code which sets up the DDR RAM controller and clocks.
1083 A script like this one, or a more GDB-aware sibling,
1087 proc ramboot @{ @} @{
1088 # Reset, running the target's "reset-init" scripts
1089 # to initialize clocks and the DDR RAM controller.
1090 # Leave the CPU halted.
1093 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1094 load_image u-boot.bin 0x20000000
1101 Then once that code is working you will need to make it
1102 boot from NOR flash; a different utility would help.
1103 Alternatively, some developers write to flash using GDB.
1104 (You might use a similar script if you're working with a flash
1105 based microcontroller application instead of a boot loader.)
1108 proc newboot @{ @} @{
1109 # Reset, leaving the CPU halted. The "reset-init" event
1110 # proc gives faster access to the CPU and to NOR flash;
1111 # "reset halt" would be slower.
1114 # Write standard version of U-Boot into the first two
1115 # sectors of NOR flash ... the standard version should
1116 # do the same lowlevel init as "reset-init".
1117 flash protect 0 0 1 off
1118 flash erase_sector 0 0 1
1119 flash write_bank 0 u-boot.bin 0x0
1120 flash protect 0 0 1 on
1122 # Reboot from scratch using that new boot loader.
1127 You may need more complicated utility procedures when booting
1129 That often involves an extra bootloader stage,
1130 running from on-chip SRAM to perform DDR RAM setup so it can load
1131 the main bootloader code (which won't fit into that SRAM).
1133 Other helper scripts might be used to write production system images,
1134 involving considerably more than just a three stage bootloader.
1136 @section Target Software Changes
1138 Sometimes you may want to make some small changes to the software
1139 you're developing, to help make JTAG debugging work better.
1140 For example, in C or assembly language code you might
1141 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1142 handling issues like:
1146 @item @b{Watchdog Timers}...
1147 Watchdog timers are typically used to automatically reset systems if
1148 some application task doesn't periodically reset the timer. (The
1149 assumption is that the system has locked up if the task can't run.)
1150 When a JTAG debugger halts the system, that task won't be able to run
1151 and reset the timer ... potentially causing resets in the middle of
1152 your debug sessions.
1154 It's rarely a good idea to disable such watchdogs, since their usage
1155 needs to be debugged just like all other parts of your firmware.
1156 That might however be your only option.
1158 Look instead for chip-specific ways to stop the watchdog from counting
1159 while the system is in a debug halt state. It may be simplest to set
1160 that non-counting mode in your debugger startup scripts. You may however
1161 need a different approach when, for example, a motor could be physically
1162 damaged by firmware remaining inactive in a debug halt state. That might
1163 involve a type of firmware mode where that "non-counting" mode is disabled
1164 at the beginning then re-enabled at the end; a watchdog reset might fire
1165 and complicate the debug session, but hardware (or people) would be
1166 protected.@footnote{Note that many systems support a "monitor mode" debug
1167 that is a somewhat cleaner way to address such issues. You can think of
1168 it as only halting part of the system, maybe just one task,
1169 instead of the whole thing.
1170 At this writing, January 2010, OpenOCD based debugging does not support
1171 monitor mode debug, only "halt mode" debug.}
1173 @item @b{ARM Semihosting}...
1174 @cindex ARM semihosting
1175 When linked with a special runtime library provided with many
1176 toolchains@footnote{See chapter 8 "Semihosting" in
1177 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1178 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1179 The CodeSourcery EABI toolchain also includes a semihosting library.},
1180 your target code can use I/O facilities on the debug host. That library
1181 provides a small set of system calls which are handled by OpenOCD.
1182 It can let the debugger provide your system console and a file system,
1183 helping with early debugging or providing a more capable environment
1184 for sometimes-complex tasks like installing system firmware onto
1187 @item @b{ARM Wait-For-Interrupt}...
1188 Many ARM chips synchronize the JTAG clock using the core clock.
1189 Low power states which stop that core clock thus prevent JTAG access.
1190 Idle loops in tasking environments often enter those low power states
1191 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1193 You may want to @emph{disable that instruction} in source code,
1194 or otherwise prevent using that state,
1195 to ensure you can get JTAG access at any time.@footnote{As a more
1196 polite alternative, some processors have special debug-oriented
1197 registers which can be used to change various features including
1198 how the low power states are clocked while debugging.
1199 The STM32 DBGMCU_CR register is an example; at the cost of extra
1200 power consumption, JTAG can be used during low power states.}
1201 For example, the OpenOCD @command{halt} command may not
1202 work for an idle processor otherwise.
1204 @item @b{Delay after reset}...
1205 Not all chips have good support for debugger access
1206 right after reset; many LPC2xxx chips have issues here.
1207 Similarly, applications that reconfigure pins used for
1208 JTAG access as they start will also block debugger access.
1210 To work with boards like this, @emph{enable a short delay loop}
1211 the first thing after reset, before "real" startup activities.
1212 For example, one second's delay is usually more than enough
1213 time for a JTAG debugger to attach, so that
1214 early code execution can be debugged
1215 or firmware can be replaced.
1217 @item @b{Debug Communications Channel (DCC)}...
1218 Some processors include mechanisms to send messages over JTAG.
1219 Many ARM cores support these, as do some cores from other vendors.
1220 (OpenOCD may be able to use this DCC internally, speeding up some
1221 operations like writing to memory.)
1223 Your application may want to deliver various debugging messages
1224 over JTAG, by @emph{linking with a small library of code}
1225 provided with OpenOCD and using the utilities there to send
1226 various kinds of message.
1227 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1231 @section Target Hardware Setup
1233 Chip vendors often provide software development boards which
1234 are highly configurable, so that they can support all options
1235 that product boards may require. @emph{Make sure that any
1236 jumpers or switches match the system configuration you are
1239 Common issues include:
1243 @item @b{JTAG setup} ...
1244 Boards may support more than one JTAG configuration.
1245 Examples include jumpers controlling pullups versus pulldowns
1246 on the nTRST and/or nSRST signals, and choice of connectors
1247 (e.g. which of two headers on the base board,
1248 or one from a daughtercard).
1249 For some Texas Instruments boards, you may need to jumper the
1250 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1252 @item @b{Boot Modes} ...
1253 Complex chips often support multiple boot modes, controlled
1254 by external jumpers. Make sure this is set up correctly.
1255 For example many i.MX boards from NXP need to be jumpered
1256 to "ATX mode" to start booting using the on-chip ROM, when
1257 using second stage bootloader code stored in a NAND flash chip.
1259 Such explicit configuration is common, and not limited to
1260 booting from NAND. You might also need to set jumpers to
1261 start booting using code loaded from an MMC/SD card; external
1262 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1263 flash; some external host; or various other sources.
1266 @item @b{Memory Addressing} ...
1267 Boards which support multiple boot modes may also have jumpers
1268 to configure memory addressing. One board, for example, jumpers
1269 external chipselect 0 (used for booting) to address either
1270 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1271 or NAND flash. When it's jumpered to address NAND flash, that
1272 board must also be told to start booting from on-chip ROM.
1274 Your @file{board.cfg} file may also need to be told this jumper
1275 configuration, so that it can know whether to declare NOR flash
1276 using @command{flash bank} or instead declare NAND flash with
1277 @command{nand device}; and likewise which probe to perform in
1278 its @code{reset-init} handler.
1280 A closely related issue is bus width. Jumpers might need to
1281 distinguish between 8 bit or 16 bit bus access for the flash
1282 used to start booting.
1284 @item @b{Peripheral Access} ...
1285 Development boards generally provide access to every peripheral
1286 on the chip, sometimes in multiple modes (such as by providing
1287 multiple audio codec chips).
1288 This interacts with software
1289 configuration of pin multiplexing, where for example a
1290 given pin may be routed either to the MMC/SD controller
1291 or the GPIO controller. It also often interacts with
1292 configuration jumpers. One jumper may be used to route
1293 signals to an MMC/SD card slot or an expansion bus (which
1294 might in turn affect booting); others might control which
1295 audio or video codecs are used.
1299 Plus you should of course have @code{reset-init} event handlers
1300 which set up the hardware to match that jumper configuration.
1301 That includes in particular any oscillator or PLL used to clock
1302 the CPU, and any memory controllers needed to access external
1303 memory and peripherals. Without such handlers, you won't be
1304 able to access those resources without working target firmware
1305 which can do that setup ... this can be awkward when you're
1306 trying to debug that target firmware. Even if there's a ROM
1307 bootloader which handles a few issues, it rarely provides full
1308 access to all board-specific capabilities.
1311 @node Config File Guidelines
1312 @chapter Config File Guidelines
1314 This chapter is aimed at any user who needs to write a config file,
1315 including developers and integrators of OpenOCD and any user who
1316 needs to get a new board working smoothly.
1317 It provides guidelines for creating those files.
1319 You should find the following directories under
1320 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1321 them as-is where you can; or as models for new files.
1323 @item @file{interface} ...
1324 These are for debug adapters. Files that specify configuration to use
1325 specific JTAG, SWD and other adapters go here.
1326 @item @file{board} ...
1327 Think Circuit Board, PWA, PCB, they go by many names. Board files
1328 contain initialization items that are specific to a board.
1330 They reuse target configuration files, since the same
1331 microprocessor chips are used on many boards,
1332 but support for external parts varies widely. For
1333 example, the SDRAM initialization sequence for the board, or the type
1334 of external flash and what address it uses. Any initialization
1335 sequence to enable that external flash or SDRAM should be found in the
1336 board file. Boards may also contain multiple targets: two CPUs; or
1338 @item @file{target} ...
1339 Think chip. The ``target'' directory represents the JTAG TAPs
1341 which OpenOCD should control, not a board. Two common types of targets
1342 are ARM chips and FPGA or CPLD chips.
1343 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1344 the target config file defines all of them.
1345 @item @emph{more} ... browse for other library files which may be useful.
1346 For example, there are various generic and CPU-specific utilities.
1349 The @file{openocd.cfg} user config
1350 file may override features in any of the above files by
1351 setting variables before sourcing the target file, or by adding
1352 commands specific to their situation.
1354 @section Interface Config Files
1356 The user config file
1357 should be able to source one of these files with a command like this:
1360 source [find interface/FOOBAR.cfg]
1363 A preconfigured interface file should exist for every debug adapter
1364 in use today with OpenOCD.
1365 That said, perhaps some of these config files
1366 have only been used by the developer who created it.
1368 A separate chapter gives information about how to set these up.
1369 @xref{Debug Adapter Configuration}.
1370 Read the OpenOCD source code (and Developer's Guide)
1371 if you have a new kind of hardware interface
1372 and need to provide a driver for it.
1374 @deffn {Command} {find} 'filename'
1375 Prints full path to @var{filename} according to OpenOCD search rules.
1378 @deffn {Command} {ocd_find} 'filename'
1379 Prints full path to @var{filename} according to OpenOCD search rules. This
1380 is a low level function used by the @command{find}. Usually you want
1381 to use @command{find}, instead.
1384 @section Board Config Files
1385 @cindex config file, board
1386 @cindex board config file
1388 The user config file
1389 should be able to source one of these files with a command like this:
1392 source [find board/FOOBAR.cfg]
1395 The point of a board config file is to package everything
1396 about a given board that user config files need to know.
1397 In summary the board files should contain (if present)
1400 @item One or more @command{source [find target/...cfg]} statements
1401 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1402 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1403 @item Target @code{reset} handlers for SDRAM and I/O configuration
1404 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1405 @item All things that are not ``inside a chip''
1408 Generic things inside target chips belong in target config files,
1409 not board config files. So for example a @code{reset-init} event
1410 handler should know board-specific oscillator and PLL parameters,
1411 which it passes to target-specific utility code.
1413 The most complex task of a board config file is creating such a
1414 @code{reset-init} event handler.
1415 Define those handlers last, after you verify the rest of the board
1416 configuration works.
1418 @subsection Communication Between Config files
1420 In addition to target-specific utility code, another way that
1421 board and target config files communicate is by following a
1422 convention on how to use certain variables.
1424 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1425 Thus the rule we follow in OpenOCD is this: Variables that begin with
1426 a leading underscore are temporary in nature, and can be modified and
1427 used at will within a target configuration file.
1429 Complex board config files can do the things like this,
1430 for a board with three chips:
1433 # Chip #1: PXA270 for network side, big endian
1434 set CHIPNAME network
1436 source [find target/pxa270.cfg]
1437 # on return: _TARGETNAME = network.cpu
1438 # other commands can refer to the "network.cpu" target.
1439 $_TARGETNAME configure .... events for this CPU..
1441 # Chip #2: PXA270 for video side, little endian
1444 source [find target/pxa270.cfg]
1445 # on return: _TARGETNAME = video.cpu
1446 # other commands can refer to the "video.cpu" target.
1447 $_TARGETNAME configure .... events for this CPU..
1449 # Chip #3: Xilinx FPGA for glue logic
1452 source [find target/spartan3.cfg]
1455 That example is oversimplified because it doesn't show any flash memory,
1456 or the @code{reset-init} event handlers to initialize external DRAM
1457 or (assuming it needs it) load a configuration into the FPGA.
1458 Such features are usually needed for low-level work with many boards,
1459 where ``low level'' implies that the board initialization software may
1460 not be working. (That's a common reason to need JTAG tools. Another
1461 is to enable working with microcontroller-based systems, which often
1462 have no debugging support except a JTAG connector.)
1464 Target config files may also export utility functions to board and user
1465 config files. Such functions should use name prefixes, to help avoid
1468 Board files could also accept input variables from user config files.
1469 For example, there might be a @code{J4_JUMPER} setting used to identify
1470 what kind of flash memory a development board is using, or how to set
1471 up other clocks and peripherals.
1473 @subsection Variable Naming Convention
1474 @cindex variable names
1476 Most boards have only one instance of a chip.
1477 However, it should be easy to create a board with more than
1478 one such chip (as shown above).
1479 Accordingly, we encourage these conventions for naming
1480 variables associated with different @file{target.cfg} files,
1481 to promote consistency and
1482 so that board files can override target defaults.
1484 Inputs to target config files include:
1487 @item @code{CHIPNAME} ...
1488 This gives a name to the overall chip, and is used as part of
1489 tap identifier dotted names.
1490 While the default is normally provided by the chip manufacturer,
1491 board files may need to distinguish between instances of a chip.
1492 @item @code{ENDIAN} ...
1493 By default @option{little} - although chips may hard-wire @option{big}.
1494 Chips that can't change endianness don't need to use this variable.
1495 @item @code{CPUTAPID} ...
1496 When OpenOCD examines the JTAG chain, it can be told verify the
1497 chips against the JTAG IDCODE register.
1498 The target file will hold one or more defaults, but sometimes the
1499 chip in a board will use a different ID (perhaps a newer revision).
1502 Outputs from target config files include:
1505 @item @code{_TARGETNAME} ...
1506 By convention, this variable is created by the target configuration
1507 script. The board configuration file may make use of this variable to
1508 configure things like a ``reset init'' script, or other things
1509 specific to that board and that target.
1510 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1511 @code{_TARGETNAME1}, ... etc.
1514 @subsection The reset-init Event Handler
1515 @cindex event, reset-init
1516 @cindex reset-init handler
1518 Board config files run in the OpenOCD configuration stage;
1519 they can't use TAPs or targets, since they haven't been
1521 This means you can't write memory or access chip registers;
1522 you can't even verify that a flash chip is present.
1523 That's done later in event handlers, of which the target @code{reset-init}
1524 handler is one of the most important.
1526 Except on microcontrollers, the basic job of @code{reset-init} event
1527 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1528 Microcontrollers rarely use boot loaders; they run right out of their
1529 on-chip flash and SRAM memory. But they may want to use one of these
1530 handlers too, if just for developer convenience.
1533 Because this is so very board-specific, and chip-specific, no examples
1535 Instead, look at the board config files distributed with OpenOCD.
1536 If you have a boot loader, its source code will help; so will
1537 configuration files for other JTAG tools
1538 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1541 Some of this code could probably be shared between different boards.
1542 For example, setting up a DRAM controller often doesn't differ by
1543 much except the bus width (16 bits or 32?) and memory timings, so a
1544 reusable TCL procedure loaded by the @file{target.cfg} file might take
1545 those as parameters.
1546 Similarly with oscillator, PLL, and clock setup;
1547 and disabling the watchdog.
1548 Structure the code cleanly, and provide comments to help
1549 the next developer doing such work.
1550 (@emph{You might be that next person} trying to reuse init code!)
1552 The last thing normally done in a @code{reset-init} handler is probing
1553 whatever flash memory was configured. For most chips that needs to be
1554 done while the associated target is halted, either because JTAG memory
1555 access uses the CPU or to prevent conflicting CPU access.
1557 @subsection JTAG Clock Rate
1559 Before your @code{reset-init} handler has set up
1560 the PLLs and clocking, you may need to run with
1561 a low JTAG clock rate.
1562 @xref{jtagspeed,,JTAG Speed}.
1563 Then you'd increase that rate after your handler has
1564 made it possible to use the faster JTAG clock.
1565 When the initial low speed is board-specific, for example
1566 because it depends on a board-specific oscillator speed, then
1567 you should probably set it up in the board config file;
1568 if it's target-specific, it belongs in the target config file.
1570 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1571 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1572 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1573 Consult chip documentation to determine the peak JTAG clock rate,
1574 which might be less than that.
1577 On most ARMs, JTAG clock detection is coupled to the core clock, so
1578 software using a @option{wait for interrupt} operation blocks JTAG access.
1579 Adaptive clocking provides a partial workaround, but a more complete
1580 solution just avoids using that instruction with JTAG debuggers.
1583 If both the chip and the board support adaptive clocking,
1584 use the @command{jtag_rclk}
1585 command, in case your board is used with JTAG adapter which
1586 also supports it. Otherwise use @command{adapter speed}.
1587 Set the slow rate at the beginning of the reset sequence,
1588 and the faster rate as soon as the clocks are at full speed.
1590 @anchor{theinitboardprocedure}
1591 @subsection The init_board procedure
1592 @cindex init_board procedure
1594 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1595 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1596 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1597 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1598 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1599 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1600 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1601 Additionally ``linear'' board config file will most likely fail when target config file uses
1602 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1603 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1604 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1605 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1607 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1608 the original), allowing greater code reuse.
1611 ### board_file.cfg ###
1613 # source target file that does most of the config in init_targets
1614 source [find target/target.cfg]
1616 proc enable_fast_clock @{@} @{
1617 # enables fast on-board clock source
1618 # configures the chip to use it
1621 # initialize only board specifics - reset, clock, adapter frequency
1622 proc init_board @{@} @{
1623 reset_config trst_and_srst trst_pulls_srst
1625 $_TARGETNAME configure -event reset-start @{
1629 $_TARGETNAME configure -event reset-init @{
1636 @section Target Config Files
1637 @cindex config file, target
1638 @cindex target config file
1640 Board config files communicate with target config files using
1641 naming conventions as described above, and may source one or
1642 more target config files like this:
1645 source [find target/FOOBAR.cfg]
1648 The point of a target config file is to package everything
1649 about a given chip that board config files need to know.
1650 In summary the target files should contain
1654 @item Add TAPs to the scan chain
1655 @item Add CPU targets (includes GDB support)
1656 @item CPU/Chip/CPU-Core specific features
1660 As a rule of thumb, a target file sets up only one chip.
1661 For a microcontroller, that will often include a single TAP,
1662 which is a CPU needing a GDB target, and its on-chip flash.
1664 More complex chips may include multiple TAPs, and the target
1665 config file may need to define them all before OpenOCD
1666 can talk to the chip.
1667 For example, some phone chips have JTAG scan chains that include
1668 an ARM core for operating system use, a DSP,
1669 another ARM core embedded in an image processing engine,
1670 and other processing engines.
1672 @subsection Default Value Boiler Plate Code
1674 All target configuration files should start with code like this,
1675 letting board config files express environment-specific
1676 differences in how things should be set up.
1679 # Boards may override chip names, perhaps based on role,
1680 # but the default should match what the vendor uses
1681 if @{ [info exists CHIPNAME] @} @{
1682 set _CHIPNAME $CHIPNAME
1684 set _CHIPNAME sam7x256
1687 # ONLY use ENDIAN with targets that can change it.
1688 if @{ [info exists ENDIAN] @} @{
1694 # TAP identifiers may change as chips mature, for example with
1695 # new revision fields (the "3" here). Pick a good default; you
1696 # can pass several such identifiers to the "jtag newtap" command.
1697 if @{ [info exists CPUTAPID ] @} @{
1698 set _CPUTAPID $CPUTAPID
1700 set _CPUTAPID 0x3f0f0f0f
1703 @c but 0x3f0f0f0f is for an str73x part ...
1705 @emph{Remember:} Board config files may include multiple target
1706 config files, or the same target file multiple times
1707 (changing at least @code{CHIPNAME}).
1709 Likewise, the target configuration file should define
1710 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1711 use it later on when defining debug targets:
1714 set _TARGETNAME $_CHIPNAME.cpu
1715 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1718 @subsection Adding TAPs to the Scan Chain
1719 After the ``defaults'' are set up,
1720 add the TAPs on each chip to the JTAG scan chain.
1721 @xref{TAP Declaration}, and the naming convention
1724 In the simplest case the chip has only one TAP,
1725 probably for a CPU or FPGA.
1726 The config file for the Atmel AT91SAM7X256
1727 looks (in part) like this:
1730 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1733 A board with two such at91sam7 chips would be able
1734 to source such a config file twice, with different
1735 values for @code{CHIPNAME}, so
1736 it adds a different TAP each time.
1738 If there are nonzero @option{-expected-id} values,
1739 OpenOCD attempts to verify the actual tap id against those values.
1740 It will issue error messages if there is mismatch, which
1741 can help to pinpoint problems in OpenOCD configurations.
1744 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1745 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1746 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1747 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1748 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1751 There are more complex examples too, with chips that have
1752 multiple TAPs. Ones worth looking at include:
1755 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1756 plus a JRC to enable them
1757 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1758 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1759 is not currently used)
1762 @subsection Add CPU targets
1764 After adding a TAP for a CPU, you should set it up so that
1765 GDB and other commands can use it.
1766 @xref{CPU Configuration}.
1767 For the at91sam7 example above, the command can look like this;
1768 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1769 to little endian, and this chip doesn't support changing that.
1772 set _TARGETNAME $_CHIPNAME.cpu
1773 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1776 Work areas are small RAM areas associated with CPU targets.
1777 They are used by OpenOCD to speed up downloads,
1778 and to download small snippets of code to program flash chips.
1779 If the chip includes a form of ``on-chip-ram'' - and many do - define
1780 a work area if you can.
1781 Again using the at91sam7 as an example, this can look like:
1784 $_TARGETNAME configure -work-area-phys 0x00200000 \
1785 -work-area-size 0x4000 -work-area-backup 0
1788 @anchor{definecputargetsworkinginsmp}
1789 @subsection Define CPU targets working in SMP
1791 After setting targets, you can define a list of targets working in SMP.
1794 set _TARGETNAME_1 $_CHIPNAME.cpu1
1795 set _TARGETNAME_2 $_CHIPNAME.cpu2
1796 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1797 -coreid 0 -dbgbase $_DAP_DBG1
1798 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1799 -coreid 1 -dbgbase $_DAP_DBG2
1800 #define 2 targets working in smp.
1801 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1803 In the above example on cortex_a, 2 cpus are working in SMP.
1804 In SMP only one GDB instance is created and :
1806 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1807 @item halt command triggers the halt of all targets in the list.
1808 @item resume command triggers the write context and the restart of all targets in the list.
1809 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1810 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1811 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1814 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1815 command have been implemented.
1817 @item cortex_a smp on : enable SMP mode, behaviour is as described above.
1818 @item cortex_a smp off : disable SMP mode, the current target is the one
1819 displayed in the GDB session, only this target is now controlled by GDB
1820 session. This behaviour is useful during system boot up.
1821 @item cortex_a smp : display current SMP mode.
1822 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1829 #0 : coreid 0 is displayed to GDB ,
1830 #-> -1 : next resume triggers a real resume
1831 > cortex_a smp_gdb 1
1833 #0 :coreid 0 is displayed to GDB ,
1834 #->1 : next resume displays coreid 1 to GDB
1838 #1 :coreid 1 is displayed to GDB ,
1839 #->1 : next resume displays coreid 1 to GDB
1840 > cortex_a smp_gdb -1
1842 #1 :coreid 1 is displayed to GDB,
1843 #->-1 : next resume triggers a real resume
1847 @subsection Chip Reset Setup
1849 As a rule, you should put the @command{reset_config} command
1850 into the board file. Most things you think you know about a
1851 chip can be tweaked by the board.
1853 Some chips have specific ways the TRST and SRST signals are
1854 managed. In the unusual case that these are @emph{chip specific}
1855 and can never be changed by board wiring, they could go here.
1856 For example, some chips can't support JTAG debugging without
1859 Provide a @code{reset-assert} event handler if you can.
1860 Such a handler uses JTAG operations to reset the target,
1861 letting this target config be used in systems which don't
1862 provide the optional SRST signal, or on systems where you
1863 don't want to reset all targets at once.
1864 Such a handler might write to chip registers to force a reset,
1865 use a JRC to do that (preferable -- the target may be wedged!),
1866 or force a watchdog timer to trigger.
1867 (For Cortex-M targets, this is not necessary. The target
1868 driver knows how to use trigger an NVIC reset when SRST is
1871 Some chips need special attention during reset handling if
1872 they're going to be used with JTAG.
1873 An example might be needing to send some commands right
1874 after the target's TAP has been reset, providing a
1875 @code{reset-deassert-post} event handler that writes a chip
1876 register to report that JTAG debugging is being done.
1877 Another would be reconfiguring the watchdog so that it stops
1878 counting while the core is halted in the debugger.
1880 JTAG clocking constraints often change during reset, and in
1881 some cases target config files (rather than board config files)
1882 are the right places to handle some of those issues.
1883 For example, immediately after reset most chips run using a
1884 slower clock than they will use later.
1885 That means that after reset (and potentially, as OpenOCD
1886 first starts up) they must use a slower JTAG clock rate
1887 than they will use later.
1888 @xref{jtagspeed,,JTAG Speed}.
1890 @quotation Important
1891 When you are debugging code that runs right after chip
1892 reset, getting these issues right is critical.
1893 In particular, if you see intermittent failures when
1894 OpenOCD verifies the scan chain after reset,
1895 look at how you are setting up JTAG clocking.
1898 @anchor{theinittargetsprocedure}
1899 @subsection The init_targets procedure
1900 @cindex init_targets procedure
1902 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1903 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1904 procedure called @code{init_targets}, which will be executed when entering run stage
1905 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1906 Such procedure can be overridden by ``next level'' script (which sources the original).
1907 This concept facilitates code reuse when basic target config files provide generic configuration
1908 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1909 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1910 because sourcing them executes every initialization commands they provide.
1913 ### generic_file.cfg ###
1915 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1916 # basic initialization procedure ...
1919 proc init_targets @{@} @{
1920 # initializes generic chip with 4kB of flash and 1kB of RAM
1921 setup_my_chip MY_GENERIC_CHIP 4096 1024
1924 ### specific_file.cfg ###
1926 source [find target/generic_file.cfg]
1928 proc init_targets @{@} @{
1929 # initializes specific chip with 128kB of flash and 64kB of RAM
1930 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1934 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1935 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1937 For an example of this scheme see LPC2000 target config files.
1939 The @code{init_boards} procedure is a similar concept concerning board config files
1940 (@xref{theinitboardprocedure,,The init_board procedure}.)
1942 @anchor{theinittargeteventsprocedure}
1943 @subsection The init_target_events procedure
1944 @cindex init_target_events procedure
1946 A special procedure called @code{init_target_events} is run just after
1947 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1948 procedure}.) and before @code{init_board}
1949 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1950 to set up default target events for the targets that do not have those
1951 events already assigned.
1953 @subsection ARM Core Specific Hacks
1955 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1956 special high speed download features - enable it.
1958 If present, the MMU, the MPU and the CACHE should be disabled.
1960 Some ARM cores are equipped with trace support, which permits
1961 examination of the instruction and data bus activity. Trace
1962 activity is controlled through an ``Embedded Trace Module'' (ETM)
1963 on one of the core's scan chains. The ETM emits voluminous data
1964 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1965 If you are using an external trace port,
1966 configure it in your board config file.
1967 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1968 configure it in your target config file.
1971 etm config $_TARGETNAME 16 normal full etb
1972 etb config $_TARGETNAME $_CHIPNAME.etb
1975 @subsection Internal Flash Configuration
1977 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1979 @b{Never ever} in the ``target configuration file'' define any type of
1980 flash that is external to the chip. (For example a BOOT flash on
1981 Chip Select 0.) Such flash information goes in a board file - not
1982 the TARGET (chip) file.
1986 @item at91sam7x256 - has 256K flash YES enable it.
1987 @item str912 - has flash internal YES enable it.
1988 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1989 @item pxa270 - again - CS0 flash - it goes in the board file.
1992 @anchor{translatingconfigurationfiles}
1993 @section Translating Configuration Files
1995 If you have a configuration file for another hardware debugger
1996 or toolset (Abatron, BDI2000, BDI3000, CCS,
1997 Lauterbach, SEGGER, Macraigor, etc.), translating
1998 it into OpenOCD syntax is often quite straightforward. The most tricky
1999 part of creating a configuration script is oftentimes the reset init
2000 sequence where e.g. PLLs, DRAM and the like is set up.
2002 One trick that you can use when translating is to write small
2003 Tcl procedures to translate the syntax into OpenOCD syntax. This
2004 can avoid manual translation errors and make it easier to
2005 convert other scripts later on.
2007 Example of transforming quirky arguments to a simple search and
2011 # Lauterbach syntax(?)
2013 # Data.Set c15:0x042f %long 0x40000015
2015 # OpenOCD syntax when using procedure below.
2017 # setc15 0x01 0x00050078
2019 proc setc15 @{regs value@} @{
2022 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2024 arm mcr 15 [expr @{($regs >> 12) & 0x7@}] \
2025 [expr @{($regs >> 0) & 0xf@}] [expr @{($regs >> 4) & 0xf@}] \
2026 [expr @{($regs >> 8) & 0x7@}] $value
2032 @node Server Configuration
2033 @chapter Server Configuration
2034 @cindex initialization
2035 The commands here are commonly found in the openocd.cfg file and are
2036 used to specify what TCP/IP ports are used, and how GDB should be
2039 @anchor{configurationstage}
2040 @section Configuration Stage
2041 @cindex configuration stage
2042 @cindex config command
2044 When the OpenOCD server process starts up, it enters a
2045 @emph{configuration stage} which is the only time that
2046 certain commands, @emph{configuration commands}, may be issued.
2047 Normally, configuration commands are only available
2048 inside startup scripts.
2050 In this manual, the definition of a configuration command is
2051 presented as a @emph{Config Command}, not as a @emph{Command}
2052 which may be issued interactively.
2053 The runtime @command{help} command also highlights configuration
2054 commands, and those which may be issued at any time.
2056 Those configuration commands include declaration of TAPs,
2058 the interface used for JTAG communication,
2059 and other basic setup.
2060 The server must leave the configuration stage before it
2061 may access or activate TAPs.
2062 After it leaves this stage, configuration commands may no
2065 @deffn {Command} {command mode} [command_name]
2066 Returns the command modes allowed by a command: 'any', 'config', or
2067 'exec'. If no command is specified, returns the current command
2068 mode. Returns 'unknown' if an unknown command is given. Command can be
2069 multiple tokens. (command valid any time)
2071 In this document, the modes are described as stages, 'config' and
2072 'exec' mode correspond configuration stage and run stage. 'any' means
2073 the command can be executed in either
2074 stages. @xref{configurationstage,,Configuration Stage}, and
2075 @xref{enteringtherunstage,,Entering the Run Stage}.
2078 @anchor{enteringtherunstage}
2079 @section Entering the Run Stage
2081 The first thing OpenOCD does after leaving the configuration
2082 stage is to verify that it can talk to the scan chain
2083 (list of TAPs) which has been configured.
2084 It will warn if it doesn't find TAPs it expects to find,
2085 or finds TAPs that aren't supposed to be there.
2086 You should see no errors at this point.
2087 If you see errors, resolve them by correcting the
2088 commands you used to configure the server.
2089 Common errors include using an initial JTAG speed that's too
2090 fast, and not providing the right IDCODE values for the TAPs
2093 Once OpenOCD has entered the run stage, a number of commands
2095 A number of these relate to the debug targets you may have declared.
2096 For example, the @command{mww} command will not be available until
2097 a target has been successfully instantiated.
2098 If you want to use those commands, you may need to force
2099 entry to the run stage.
2101 @deffn {Config Command} {init}
2102 This command terminates the configuration stage and
2103 enters the run stage. This helps when you need to have
2104 the startup scripts manage tasks such as resetting the target,
2105 programming flash, etc. To reset the CPU upon startup, add "init" and
2106 "reset" at the end of the config script or at the end of the OpenOCD
2107 command line using the @option{-c} command line switch.
2109 If this command does not appear in any startup/configuration file
2110 OpenOCD executes the command for you after processing all
2111 configuration files and/or command line options.
2113 @b{NOTE:} This command normally occurs near the end of your
2114 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2115 targets ready. For example: If your openocd.cfg file needs to
2116 read/write memory on your target, @command{init} must occur before
2117 the memory read/write commands. This includes @command{nand probe}.
2119 @command{init} calls the following internal OpenOCD commands to initialize
2120 corresponding subsystems:
2121 @deffn {Config Command} {target init}
2122 @deffnx {Command} {transport init}
2123 @deffnx {Command} {dap init}
2124 @deffnx {Config Command} {flash init}
2125 @deffnx {Config Command} {nand init}
2126 @deffnx {Config Command} {pld init}
2127 @deffnx {Command} {tpiu init}
2130 At last, @command{init} executes all the commands that are specified in
2131 the TCL list @var{post_init_commands}. The commands are executed in the
2132 same order they occupy in the list. If one of the commands fails, then
2133 the error is propagated and OpenOCD fails too.
2135 lappend post_init_commands @{echo "OpenOCD successfully initialized."@}
2136 lappend post_init_commands @{echo "Have fun with OpenOCD !"@}
2140 @deffn {Config Command} {noinit}
2141 Prevent OpenOCD from implicit @command{init} call at the end of startup.
2142 Allows issuing configuration commands over telnet or Tcl connection.
2143 When you are done with configuration use @command{init} to enter
2147 @deffn {Overridable Procedure} {jtag_init}
2148 This is invoked at server startup to verify that it can talk
2149 to the scan chain (list of TAPs) which has been configured.
2151 The default implementation first tries @command{jtag arp_init},
2152 which uses only a lightweight JTAG reset before examining the
2154 If that fails, it tries again, using a harder reset
2155 from the overridable procedure @command{init_reset}.
2157 Implementations must have verified the JTAG scan chain before
2159 This is done by calling @command{jtag arp_init}
2160 (or @command{jtag arp_init-reset}).
2164 @section TCP/IP Ports
2169 The OpenOCD server accepts remote commands in several syntaxes.
2170 Each syntax uses a different TCP/IP port, which you may specify
2171 only during configuration (before those ports are opened).
2173 For reasons including security, you may wish to prevent remote
2174 access using one or more of these ports.
2175 In such cases, just specify the relevant port number as "disabled".
2176 If you disable all access through TCP/IP, you will need to
2177 use the command line @option{-pipe} option.
2180 @deffn {Config Command} {gdb_port} [number]
2182 Normally gdb listens to a TCP/IP port, but GDB can also
2183 communicate via pipes(stdin/out or named pipes). The name
2184 "gdb_port" stuck because it covers probably more than 90% of
2185 the normal use cases.
2187 No arguments reports GDB port. "pipe" means listen to stdin
2188 output to stdout, an integer is base port number, "disabled"
2189 disables the gdb server.
2191 When using "pipe", also use log_output to redirect the log
2192 output to a file so as not to flood the stdin/out pipes.
2194 Any other string is interpreted as named pipe to listen to.
2195 Output pipe is the same name as input pipe, but with 'o' appended,
2196 e.g. /var/gdb, /var/gdbo.
2198 The GDB port for the first target will be the base port, the
2199 second target will listen on gdb_port + 1, and so on.
2200 When not specified during the configuration stage,
2201 the port @var{number} defaults to 3333.
2202 When @var{number} is not a numeric value, incrementing it to compute
2203 the next port number does not work. In this case, specify the proper
2204 @var{number} for each target by using the option @code{-gdb-port} of the
2205 commands @command{target create} or @command{$target_name configure}.
2206 @xref{gdbportoverride,,option -gdb-port}.
2208 Note: when using "gdb_port pipe", increasing the default remote timeout in
2209 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2210 cause initialization to fail with "Unknown remote qXfer reply: OK".
2213 @deffn {Config Command} {tcl_port} [number]
2214 Specify or query the port used for a simplified RPC
2215 connection that can be used by clients to issue TCL commands and get the
2216 output from the Tcl engine.
2217 Intended as a machine interface.
2218 When not specified during the configuration stage,
2219 the port @var{number} defaults to 6666.
2220 When specified as "disabled", this service is not activated.
2223 @deffn {Config Command} {telnet_port} [number]
2224 Specify or query the
2225 port on which to listen for incoming telnet connections.
2226 This port is intended for interaction with one human through TCL commands.
2227 When not specified during the configuration stage,
2228 the port @var{number} defaults to 4444.
2229 When specified as "disabled", this service is not activated.
2232 @anchor{gdbconfiguration}
2233 @section GDB Configuration
2235 @cindex GDB configuration
2236 You can reconfigure some GDB behaviors if needed.
2237 The ones listed here are static and global.
2238 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2239 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2241 @anchor{gdbbreakpointoverride}
2242 @deffn {Command} {gdb_breakpoint_override} [@option{hard}|@option{soft}|@option{disable}]
2243 Force breakpoint type for gdb @command{break} commands.
2244 This option supports GDB GUIs which don't
2245 distinguish hard versus soft breakpoints, if the default OpenOCD and
2246 GDB behaviour is not sufficient. GDB normally uses hardware
2247 breakpoints if the memory map has been set up for flash regions.
2250 @anchor{gdbflashprogram}
2251 @deffn {Config Command} {gdb_flash_program} (@option{enable}|@option{disable})
2252 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2253 vFlash packet is received.
2254 The default behaviour is @option{enable}.
2257 @deffn {Config Command} {gdb_memory_map} (@option{enable}|@option{disable})
2258 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2259 requested. GDB will then know when to set hardware breakpoints, and program flash
2260 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2261 for flash programming to work.
2262 Default behaviour is @option{enable}.
2263 @xref{gdbflashprogram,,gdb_flash_program}.
2266 @deffn {Config Command} {gdb_report_data_abort} (@option{enable}|@option{disable})
2267 Specifies whether data aborts cause an error to be reported
2268 by GDB memory read packets.
2269 The default behaviour is @option{disable};
2270 use @option{enable} see these errors reported.
2273 @deffn {Config Command} {gdb_report_register_access_error} (@option{enable}|@option{disable})
2274 Specifies whether register accesses requested by GDB register read/write
2275 packets report errors or not.
2276 The default behaviour is @option{disable};
2277 use @option{enable} see these errors reported.
2280 @deffn {Config Command} {gdb_target_description} (@option{enable}|@option{disable})
2281 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2282 The default behaviour is @option{enable}.
2285 @deffn {Command} {gdb_save_tdesc}
2286 Saves the target description file to the local file system.
2288 The file name is @i{target_name}.xml.
2291 @anchor{eventpolling}
2292 @section Event Polling
2294 Hardware debuggers are parts of asynchronous systems,
2295 where significant events can happen at any time.
2296 The OpenOCD server needs to detect some of these events,
2297 so it can report them to through TCL command line
2300 Examples of such events include:
2303 @item One of the targets can stop running ... maybe it triggers
2304 a code breakpoint or data watchpoint, or halts itself.
2305 @item Messages may be sent over ``debug message'' channels ... many
2306 targets support such messages sent over JTAG,
2307 for receipt by the person debugging or tools.
2308 @item Loss of power ... some adapters can detect these events.
2309 @item Resets not issued through JTAG ... such reset sources
2310 can include button presses or other system hardware, sometimes
2311 including the target itself (perhaps through a watchdog).
2312 @item Debug instrumentation sometimes supports event triggering
2313 such as ``trace buffer full'' (so it can quickly be emptied)
2314 or other signals (to correlate with code behavior).
2317 None of those events are signaled through standard JTAG signals.
2318 However, most conventions for JTAG connectors include voltage
2319 level and system reset (SRST) signal detection.
2320 Some connectors also include instrumentation signals, which
2321 can imply events when those signals are inputs.
2323 In general, OpenOCD needs to periodically check for those events,
2324 either by looking at the status of signals on the JTAG connector
2325 or by sending synchronous ``tell me your status'' JTAG requests
2326 to the various active targets.
2327 There is a command to manage and monitor that polling,
2328 which is normally done in the background.
2330 @deffn {Command} {poll} [@option{on}|@option{off}]
2331 Poll the current target for its current state.
2332 (Also, @pxref{targetcurstate,,target curstate}.)
2333 If that target is in debug mode, architecture
2334 specific information about the current state is printed.
2335 An optional parameter
2336 allows background polling to be enabled and disabled.
2338 You could use this from the TCL command shell, or
2339 from GDB using @command{monitor poll} command.
2340 Leave background polling enabled while you're using GDB.
2343 background polling: on
2344 target state: halted
2345 target halted in ARM state due to debug-request, \
2346 current mode: Supervisor
2347 cpsr: 0x800000d3 pc: 0x11081bfc
2348 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2353 @node Debug Adapter Configuration
2354 @chapter Debug Adapter Configuration
2355 @cindex config file, interface
2356 @cindex interface config file
2358 Correctly installing OpenOCD includes making your operating system give
2359 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2360 are used to select which one is used, and to configure how it is used.
2363 Because OpenOCD started out with a focus purely on JTAG, you may find
2364 places where it wrongly presumes JTAG is the only transport protocol
2365 in use. Be aware that recent versions of OpenOCD are removing that
2366 limitation. JTAG remains more functional than most other transports.
2367 Other transports do not support boundary scan operations, or may be
2368 specific to a given chip vendor. Some might be usable only for
2369 programming flash memory, instead of also for debugging.
2372 Debug Adapters/Interfaces/Dongles are normally configured
2373 through commands in an interface configuration
2374 file which is sourced by your @file{openocd.cfg} file, or
2375 through a command line @option{-f interface/....cfg} option.
2378 source [find interface/olimex-jtag-tiny.cfg]
2382 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2383 A few cases are so simple that you only need to say what driver to use:
2387 adapter driver jlink
2390 Most adapters need a bit more configuration than that.
2393 @section Adapter Configuration
2395 The @command{adapter driver} command tells OpenOCD what type of debug adapter you are
2396 using. Depending on the type of adapter, you may need to use one or
2397 more additional commands to further identify or configure the adapter.
2399 @deffn {Config Command} {adapter driver} name
2400 Use the adapter driver @var{name} to connect to the
2404 @deffn {Command} {adapter list}
2405 List the debug adapter drivers that have been built into
2406 the running copy of OpenOCD.
2408 @deffn {Config Command} {adapter transports} transport_name+
2409 Specifies the transports supported by this debug adapter.
2410 The adapter driver builds-in similar knowledge; use this only
2411 when external configuration (such as jumpering) changes what
2412 the hardware can support.
2417 @deffn {Command} {adapter name}
2418 Returns the name of the debug adapter driver being used.
2421 @anchor{adapter_usb_location}
2422 @deffn {Config Command} {adapter usb location} [<bus>-<port>[.<port>]...]
2423 Displays or specifies the physical USB port of the adapter to use. The path
2424 roots at @var{bus} and walks down the physical ports, with each
2425 @var{port} option specifying a deeper level in the bus topology, the last
2426 @var{port} denoting where the target adapter is actually plugged.
2427 The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
2429 This command is only available if your libusb1 is at least version 1.0.16.
2432 @deffn {Config Command} {adapter serial} serial_string
2433 Specifies the @var{serial_string} of the adapter to use.
2434 If this command is not specified, serial strings are not checked.
2435 Only the following adapter drivers use the serial string from this command:
2436 aice (aice_usb), arm-jtag-ew, cmsis_dap, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus,
2437 openjtag, osbdm, presto, rlink, st-link, usb_blaster (ublast2), usbprog, vsllink, xds110.
2440 @section Interface Drivers
2442 Each of the interface drivers listed here must be explicitly
2443 enabled when OpenOCD is configured, in order to be made
2444 available at run time.
2446 @deffn {Interface Driver} {amt_jtagaccel}
2447 Amontec Chameleon in its JTAG Accelerator configuration,
2448 connected to a PC's EPP mode parallel port.
2449 This defines some driver-specific commands:
2451 @deffn {Config Command} {parport port} number
2452 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2453 the number of the @file{/dev/parport} device.
2456 @deffn {Config Command} {rtck} [@option{enable}|@option{disable}]
2457 Displays status of RTCK option.
2458 Optionally sets that option first.
2462 @deffn {Interface Driver} {arm-jtag-ew}
2463 Olimex ARM-JTAG-EW USB adapter
2464 This has one driver-specific command:
2466 @deffn {Command} {armjtagew_info}
2471 @deffn {Interface Driver} {at91rm9200}
2472 Supports bitbanged JTAG from the local system,
2473 presuming that system is an Atmel AT91rm9200
2474 and a specific set of GPIOs is used.
2475 @c command: at91rm9200_device NAME
2476 @c chooses among list of bit configs ... only one option
2479 @deffn {Interface Driver} {cmsis-dap}
2480 ARM CMSIS-DAP compliant based adapter v1 (USB HID based)
2483 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2484 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2485 the driver will attempt to auto detect the CMSIS-DAP device.
2486 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2488 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2492 @deffn {Config Command} {cmsis_dap_backend} [@option{auto}|@option{usb_bulk}|@option{hid}]
2493 Specifies how to communicate with the adapter:
2496 @item @option{hid} Use HID generic reports - CMSIS-DAP v1
2497 @item @option{usb_bulk} Use USB bulk - CMSIS-DAP v2
2498 @item @option{auto} First try USB bulk CMSIS-DAP v2, if not found try HID CMSIS-DAP v1.
2499 This is the default if @command{cmsis_dap_backend} is not specified.
2503 @deffn {Config Command} {cmsis_dap_usb interface} [number]
2504 Specifies the @var{number} of the USB interface to use in v2 mode (USB bulk).
2505 In most cases need not to be specified and interfaces are searched by
2506 interface string or for user class interface.
2509 @deffn {Command} {cmsis-dap info}
2510 Display various device information, like hardware version, firmware version, current bus status.
2513 @deffn {Command} {cmsis-dap cmd} number number ...
2514 Execute an arbitrary CMSIS-DAP command. Use for adapter testing or for handling
2515 of an adapter vendor specific command from a Tcl script.
2517 Take given numbers as bytes, assemble a CMSIS-DAP protocol command packet
2518 from them and send it to the adapter. The first 4 bytes of the adapter response
2520 See @url{https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__Commands__gr.html}
2524 @deffn {Interface Driver} {dummy}
2525 A dummy software-only driver for debugging.
2528 @deffn {Interface Driver} {ep93xx}
2529 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2532 @deffn {Interface Driver} {ftdi}
2533 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2534 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2536 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2537 bypassing intermediate libraries like libftdi.
2539 Support for new FTDI based adapters can be added completely through
2540 configuration files, without the need to patch and rebuild OpenOCD.
2542 The driver uses a signal abstraction to enable Tcl configuration files to
2543 define outputs for one or several FTDI GPIO. These outputs can then be
2544 controlled using the @command{ftdi set_signal} command. Special signal names
2545 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2546 will be used for their customary purpose. Inputs can be read using the
2547 @command{ftdi get_signal} command.
2549 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2550 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2551 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2552 required by the protocol, to tell the adapter to drive the data output onto
2553 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2555 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2556 be controlled differently. In order to support tristateable signals such as
2557 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2558 signal. The following output buffer configurations are supported:
2561 @item Push-pull with one FTDI output as (non-)inverted data line
2562 @item Open drain with one FTDI output as (non-)inverted output-enable
2563 @item Tristate with one FTDI output as (non-)inverted data line and another
2564 FTDI output as (non-)inverted output-enable
2565 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2566 switching data and direction as necessary
2569 These interfaces have several commands, used to configure the driver
2570 before initializing the JTAG scan chain:
2572 @deffn {Config Command} {ftdi vid_pid} [vid pid]+
2573 The vendor ID and product ID of the adapter. Up to eight
2574 [@var{vid}, @var{pid}] pairs may be given, e.g.
2576 ftdi vid_pid 0x0403 0xcff8 0x15ba 0x0003
2580 @deffn {Config Command} {ftdi device_desc} description
2581 Provides the USB device description (the @emph{iProduct string})
2582 of the adapter. If not specified, the device description is ignored
2583 during device selection.
2586 @deffn {Config Command} {ftdi channel} channel
2587 Selects the channel of the FTDI device to use for MPSSE operations. Most
2588 adapters use the default, channel 0, but there are exceptions.
2591 @deffn {Config Command} {ftdi layout_init} data direction
2592 Specifies the initial values of the FTDI GPIO data and direction registers.
2593 Each value is a 16-bit number corresponding to the concatenation of the high
2594 and low FTDI GPIO registers. The values should be selected based on the
2595 schematics of the adapter, such that all signals are set to safe levels with
2596 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2597 and initially asserted reset signals.
2600 @deffn {Command} {ftdi layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2601 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2602 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2603 register bitmasks to tell the driver the connection and type of the output
2604 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2605 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2606 used with inverting data inputs and @option{-data} with non-inverting inputs.
2607 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2608 not-output-enable) input to the output buffer is connected. The options
2609 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2610 with the method @command{ftdi get_signal}.
2612 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2613 simple open-collector transistor driver would be specified with @option{-oe}
2614 only. In that case the signal can only be set to drive low or to Hi-Z and the
2615 driver will complain if the signal is set to drive high. Which means that if
2616 it's a reset signal, @command{reset_config} must be specified as
2617 @option{srst_open_drain}, not @option{srst_push_pull}.
2619 A special case is provided when @option{-data} and @option{-oe} is set to the
2620 same bitmask. Then the FTDI pin is considered being connected straight to the
2621 target without any buffer. The FTDI pin is then switched between output and
2622 input as necessary to provide the full set of low, high and Hi-Z
2623 characteristics. In all other cases, the pins specified in a signal definition
2624 are always driven by the FTDI.
2626 If @option{-alias} or @option{-nalias} is used, the signal is created
2627 identical (or with data inverted) to an already specified signal
2631 @deffn {Command} {ftdi set_signal} name @option{0}|@option{1}|@option{z}
2632 Set a previously defined signal to the specified level.
2634 @item @option{0}, drive low
2635 @item @option{1}, drive high
2636 @item @option{z}, set to high-impedance
2640 @deffn {Command} {ftdi get_signal} name
2641 Get the value of a previously defined signal.
2644 @deffn {Command} {ftdi tdo_sample_edge} @option{rising}|@option{falling}
2645 Configure TCK edge at which the adapter samples the value of the TDO signal
2647 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2648 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2649 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2650 stability at higher JTAG clocks.
2652 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2653 @item @option{falling}, sample TDO on falling edge of TCK
2657 For example adapter definitions, see the configuration files shipped in the
2658 @file{interface/ftdi} directory.
2662 @deffn {Interface Driver} {ft232r}
2663 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2664 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2665 It currently doesn't support using CBUS pins as GPIO.
2667 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2674 @item DCD(10) - SRST
2677 User can change default pinout by supplying configuration
2678 commands with GPIO numbers or RS232 signal names.
2679 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2680 They differ from physical pin numbers.
2681 For details see actual FTDI chip datasheets.
2682 Every JTAG line must be configured to unique GPIO number
2683 different than any other JTAG line, even those lines
2684 that are sometimes not used like TRST or SRST.
2698 These interfaces have several commands, used to configure the driver
2699 before initializing the JTAG scan chain:
2701 @deffn {Config Command} {ft232r vid_pid} @var{vid} @var{pid}
2702 The vendor ID and product ID of the adapter. If not specified, default
2703 0x0403:0x6001 is used.
2706 @deffn {Config Command} {ft232r jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2707 Set four JTAG GPIO numbers at once.
2708 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2711 @deffn {Config Command} {ft232r tck_num} @var{tck}
2712 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2715 @deffn {Config Command} {ft232r tms_num} @var{tms}
2716 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2719 @deffn {Config Command} {ft232r tdi_num} @var{tdi}
2720 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2723 @deffn {Config Command} {ft232r tdo_num} @var{tdo}
2724 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2727 @deffn {Config Command} {ft232r trst_num} @var{trst}
2728 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2731 @deffn {Config Command} {ft232r srst_num} @var{srst}
2732 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2735 @deffn {Config Command} {ft232r restore_serial} @var{word}
2736 Restore serial port after JTAG. This USB bitmode control word
2737 (16-bit) will be sent before quit. Lower byte should
2738 set GPIO direction register to a "sane" state:
2739 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2740 byte is usually 0 to disable bitbang mode.
2741 When kernel driver reattaches, serial port should continue to work.
2742 Value 0xFFFF disables sending control word and serial port,
2743 then kernel driver will not reattach.
2744 If not specified, default 0xFFFF is used.
2749 @deffn {Interface Driver} {remote_bitbang}
2750 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2751 with a remote process and sends ASCII encoded bitbang requests to that process
2752 instead of directly driving JTAG.
2754 The remote_bitbang driver is useful for debugging software running on
2755 processors which are being simulated.
2757 @deffn {Config Command} {remote_bitbang port} number
2758 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2759 sockets instead of TCP.
2762 @deffn {Config Command} {remote_bitbang host} hostname
2763 Specifies the hostname of the remote process to connect to using TCP, or the
2764 name of the UNIX socket to use if remote_bitbang port is 0.
2767 For example, to connect remotely via TCP to the host foobar you might have
2771 adapter driver remote_bitbang
2772 remote_bitbang port 3335
2773 remote_bitbang host foobar
2776 To connect to another process running locally via UNIX sockets with socket
2780 adapter driver remote_bitbang
2781 remote_bitbang port 0
2782 remote_bitbang host mysocket
2786 @deffn {Interface Driver} {usb_blaster}
2787 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2788 for FTDI chips. These interfaces have several commands, used to
2789 configure the driver before initializing the JTAG scan chain:
2791 @deffn {Config Command} {usb_blaster vid_pid} vid pid
2792 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2793 default values are used.
2794 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2795 Altera USB-Blaster (default):
2797 usb_blaster vid_pid 0x09FB 0x6001
2799 The following VID/PID is for Kolja Waschk's USB JTAG:
2801 usb_blaster vid_pid 0x16C0 0x06AD
2805 @deffn {Command} {usb_blaster pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2806 Sets the state or function of the unused GPIO pins on USB-Blasters
2807 (pins 6 and 8 on the female JTAG header). These pins can be used as
2808 SRST and/or TRST provided the appropriate connections are made on the
2811 For example, to use pin 6 as SRST:
2813 usb_blaster pin pin6 s
2814 reset_config srst_only
2818 @deffn {Config Command} {usb_blaster lowlevel_driver} (@option{ftdi}|@option{ublast2})
2819 Chooses the low level access method for the adapter. If not specified,
2820 @option{ftdi} is selected unless it wasn't enabled during the
2821 configure stage. USB-Blaster II needs @option{ublast2}.
2824 @deffn {Config Command} {usb_blaster firmware} @var{path}
2825 This command specifies @var{path} to access USB-Blaster II firmware
2826 image. To be used with USB-Blaster II only.
2831 @deffn {Interface Driver} {gw16012}
2832 Gateworks GW16012 JTAG programmer.
2833 This has one driver-specific command:
2835 @deffn {Config Command} {parport port} [port_number]
2836 Display either the address of the I/O port
2837 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2838 If a parameter is provided, first switch to use that port.
2839 This is a write-once setting.
2843 @deffn {Interface Driver} {jlink}
2844 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2847 @quotation Compatibility Note
2848 SEGGER released many firmware versions for the many hardware versions they
2849 produced. OpenOCD was extensively tested and intended to run on all of them,
2850 but some combinations were reported as incompatible. As a general
2851 recommendation, it is advisable to use the latest firmware version
2852 available for each hardware version. However the current V8 is a moving
2853 target, and SEGGER firmware versions released after the OpenOCD was
2854 released may not be compatible. In such cases it is recommended to
2855 revert to the last known functional version. For 0.5.0, this is from
2856 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2857 version is from "May 3 2012 18:36:22", packed with 4.46f.
2860 @deffn {Command} {jlink hwstatus}
2861 Display various hardware related information, for example target voltage and pin
2864 @deffn {Command} {jlink freemem}
2865 Display free device internal memory.
2867 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2868 Set the JTAG command version to be used. Without argument, show the actual JTAG
2871 @deffn {Command} {jlink config}
2872 Display the device configuration.
2874 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2875 Set the target power state on JTAG-pin 19. Without argument, show the target
2878 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2879 Set the MAC address of the device. Without argument, show the MAC address.
2881 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2882 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2883 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2886 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2887 Set the USB address of the device. This will also change the USB Product ID
2888 (PID) of the device. Without argument, show the USB address.
2890 @deffn {Command} {jlink config reset}
2891 Reset the current configuration.
2893 @deffn {Command} {jlink config write}
2894 Write the current configuration to the internal persistent storage.
2896 @deffn {Command} {jlink emucom write} <channel> <data>
2897 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2900 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2901 the EMUCOM channel 0x10:
2903 > jlink emucom write 0x10 aa0b23
2906 @deffn {Command} {jlink emucom read} <channel> <length>
2907 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2910 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2912 > jlink emucom read 0x0 4
2916 @deffn {Config Command} {jlink usb} <@option{0} to @option{3}>
2917 Set the USB address of the interface, in case more than one adapter is connected
2918 to the host. If not specified, USB addresses are not considered. Device
2919 selection via USB address is not always unambiguous. It is recommended to use
2920 the serial number instead, if possible.
2922 As a configuration command, it can be used only before 'init'.
2926 @deffn {Interface Driver} {kitprog}
2927 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2928 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2929 families, but it is possible to use it with some other devices. If you are using
2930 this adapter with a PSoC or a PRoC, you may need to add
2931 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2932 configuration script.
2934 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2935 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2936 be used with this driver, and must either be used with the cmsis-dap driver or
2937 switched back to KitProg mode. See the Cypress KitProg User Guide for
2938 instructions on how to switch KitProg modes.
2942 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2944 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2945 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2946 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2947 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2948 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2949 SWD sequence must be sent after every target reset in order to re-establish
2950 communications with the target.
2951 @item Due in part to the limitation above, KitProg devices with firmware below
2952 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2953 communicate with PSoC 5LP devices. This is because, assuming debug is not
2954 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2955 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2956 could only be sent with an acquisition sequence.
2959 @deffn {Config Command} {kitprog_init_acquire_psoc}
2960 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2961 Please be aware that the acquisition sequence hard-resets the target.
2964 @deffn {Command} {kitprog acquire_psoc}
2965 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2966 outside of the target-specific configuration scripts since it hard-resets the
2967 target as a side-effect.
2968 This is necessary for "reset halt" on some PSoC 4 series devices.
2971 @deffn {Command} {kitprog info}
2972 Display various adapter information, such as the hardware version, firmware
2973 version, and target voltage.
2977 @deffn {Interface Driver} {parport}
2978 Supports PC parallel port bit-banging cables:
2979 Wigglers, PLD download cable, and more.
2980 These interfaces have several commands, used to configure the driver
2981 before initializing the JTAG scan chain:
2983 @deffn {Config Command} {parport cable} name
2984 Set the layout of the parallel port cable used to connect to the target.
2985 This is a write-once setting.
2986 Currently valid cable @var{name} values include:
2989 @item @b{altium} Altium Universal JTAG cable.
2990 @item @b{arm-jtag} Same as original wiggler except SRST and
2991 TRST connections reversed and TRST is also inverted.
2992 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2993 in configuration mode. This is only used to
2994 program the Chameleon itself, not a connected target.
2995 @item @b{dlc5} The Xilinx Parallel cable III.
2996 @item @b{flashlink} The ST Parallel cable.
2997 @item @b{lattice} Lattice ispDOWNLOAD Cable
2998 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
3000 Amontec's Chameleon Programmer. The new version available from
3001 the website uses the original Wiggler layout ('@var{wiggler}')
3002 @item @b{triton} The parallel port adapter found on the
3003 ``Karo Triton 1 Development Board''.
3004 This is also the layout used by the HollyGates design
3005 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
3006 @item @b{wiggler} The original Wiggler layout, also supported by
3007 several clones, such as the Olimex ARM-JTAG
3008 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
3009 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
3013 @deffn {Config Command} {parport port} [port_number]
3014 Display either the address of the I/O port
3015 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
3016 If a parameter is provided, first switch to use that port.
3017 This is a write-once setting.
3019 When using PPDEV to access the parallel port, use the number of the parallel port:
3020 @option{parport port 0} (the default). If @option{parport port 0x378} is specified
3021 you may encounter a problem.
3024 @deffn {Config Command} {parport toggling_time} [nanoseconds]
3025 Displays how many nanoseconds the hardware needs to toggle TCK;
3026 the parport driver uses this value to obey the
3027 @command{adapter speed} configuration.
3028 When the optional @var{nanoseconds} parameter is given,
3029 that setting is changed before displaying the current value.
3031 The default setting should work reasonably well on commodity PC hardware.
3032 However, you may want to calibrate for your specific hardware.
3034 To measure the toggling time with a logic analyzer or a digital storage
3035 oscilloscope, follow the procedure below:
3037 > parport toggling_time 1000
3040 This sets the maximum JTAG clock speed of the hardware, but
3041 the actual speed probably deviates from the requested 500 kHz.
3042 Now, measure the time between the two closest spaced TCK transitions.
3043 You can use @command{runtest 1000} or something similar to generate a
3044 large set of samples.
3045 Update the setting to match your measurement:
3047 > parport toggling_time <measured nanoseconds>
3049 Now the clock speed will be a better match for @command{adapter speed}
3050 command given in OpenOCD scripts and event handlers.
3052 You can do something similar with many digital multimeters, but note
3053 that you'll probably need to run the clock continuously for several
3054 seconds before it decides what clock rate to show. Adjust the
3055 toggling time up or down until the measured clock rate is a good
3056 match with the rate you specified in the @command{adapter speed} command;
3061 @deffn {Config Command} {parport write_on_exit} (@option{on}|@option{off})
3062 This will configure the parallel driver to write a known
3063 cable-specific value to the parallel interface on exiting OpenOCD.
3066 For example, the interface configuration file for a
3067 classic ``Wiggler'' cable on LPT2 might look something like this:
3070 adapter driver parport
3072 parport cable wiggler
3076 @deffn {Interface Driver} {presto}
3077 ASIX PRESTO USB JTAG programmer.
3080 @deffn {Interface Driver} {rlink}
3081 Raisonance RLink USB adapter
3084 @deffn {Interface Driver} {usbprog}
3085 usbprog is a freely programmable USB adapter.
3088 @deffn {Interface Driver} {vsllink}
3089 vsllink is part of Versaloon which is a versatile USB programmer.
3092 This defines quite a few driver-specific commands,
3093 which are not currently documented here.
3097 @anchor{hla_interface}
3098 @deffn {Interface Driver} {hla}
3099 This is a driver that supports multiple High Level Adapters.
3100 This type of adapter does not expose some of the lower level api's
3101 that OpenOCD would normally use to access the target.
3103 Currently supported adapters include the STMicroelectronics ST-LINK, TI ICDI
3104 and Nuvoton Nu-Link.
3105 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3106 versions of firmware where serial number is reset after first use. Suggest
3107 using ST firmware update utility to upgrade ST-LINK firmware even if current
3108 version reported is V2.J21.S4.
3110 @deffn {Config Command} {hla_device_desc} description
3111 Currently Not Supported.
3114 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi}|@option{nulink})
3115 Specifies the adapter layout to use.
3118 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3119 Pairs of vendor IDs and product IDs of the device.
3122 @deffn {Config Command} {hla_stlink_backend} (usb | tcp [port])
3123 @emph{ST-Link only:} Choose between 'exclusive' USB communication (the default backend) or
3124 'shared' mode using ST-Link TCP server (the default port is 7184).
3126 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3127 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3128 ST-LINK server software module}.
3131 @deffn {Command} {hla_command} command
3132 Execute a custom adapter-specific command. The @var{command} string is
3133 passed as is to the underlying adapter layout handler.
3137 @anchor{st_link_dap_interface}
3138 @deffn {Interface Driver} {st-link}
3139 This is a driver that supports STMicroelectronics adapters ST-LINK/V2
3140 (from firmware V2J24) and STLINK-V3, thanks to a new API that provides
3141 directly access the arm ADIv5 DAP.
3143 The new API provide access to multiple AP on the same DAP, but the
3144 maximum number of the AP port is limited by the specific firmware version
3145 (e.g. firmware V2J29 has 3 as maximum AP number, while V2J32 has 8).
3146 An error is returned for any AP number above the maximum allowed value.
3148 @emph{Note:} Either these same adapters and their older versions are
3149 also supported by @ref{hla_interface, the hla interface driver}.
3151 @deffn {Config Command} {st-link backend} (usb | tcp [port])
3152 Choose between 'exclusive' USB communication (the default backend) or
3153 'shared' mode using ST-Link TCP server (the default port is 7184).
3155 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3156 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3157 ST-LINK server software module}.
3159 @emph{Note:} ST-Link TCP server does not support the SWIM transport.
3162 @deffn {Config Command} {st-link vid_pid} [vid pid]+
3163 Pairs of vendor IDs and product IDs of the device.
3166 @deffn {Command} {st-link cmd} rx_n (tx_byte)+
3167 Sends an arbitrary command composed by the sequence of bytes @var{tx_byte}
3168 and receives @var{rx_n} bytes.
3170 For example, the command to read the target's supply voltage is one byte 0xf7 followed
3171 by 15 bytes zero. It returns 8 bytes, where the first 4 bytes represent the ADC sampling
3172 of the reference voltage 1.2V and the last 4 bytes represent the ADC sampling of half
3173 the target's supply voltage.
3175 > st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3176 0xf1 0x05 0x00 0x00 0x0b 0x08 0x00 0x00
3178 The result can be converted to Volts (ignoring the most significant bytes, always zero)
3180 > set a [st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
3181 > set n [expr @{[lindex $a 4] + 256 * [lindex $a 5]@}]
3182 > set d [expr @{[lindex $a 0] + 256 * [lindex $a 1]@}]
3183 > echo [expr @{2 * 1.2 * $n / $d@}]
3189 @deffn {Interface Driver} {opendous}
3190 opendous-jtag is a freely programmable USB adapter.
3193 @deffn {Interface Driver} {ulink}
3194 This is the Keil ULINK v1 JTAG debugger.
3197 @deffn {Interface Driver} {xds110}
3198 The XDS110 is included as the embedded debug probe on many Texas Instruments
3199 LaunchPad evaluation boards. The XDS110 is also available as a stand-alone USB
3200 debug probe with the added capability to supply power to the target board. The
3201 following commands are supported by the XDS110 driver:
3203 @deffn {Config Command} {xds110 supply} voltage_in_millivolts
3204 Available only on the XDS110 stand-alone probe. Sets the voltage level of the
3205 XDS110 power supply. A value of 0 leaves the supply off. Otherwise, the supply
3206 can be set to any value in the range 1800 to 3600 millivolts.
3209 @deffn {Command} {xds110 info}
3210 Displays information about the connected XDS110 debug probe (e.g. firmware
3215 @deffn {Interface Driver} {xlnx_pcie_xvc}
3216 This driver supports the Xilinx Virtual Cable (XVC) over PCI Express.
3217 It is commonly found in Xilinx based PCI Express designs. It allows debugging
3218 fabric based JTAG/SWD devices such as Cortex-M1/M3 microcontrollers. Access to this is
3219 exposed via extended capability registers in the PCI Express configuration space.
3221 For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG mode).
3223 @deffn {Config Command} {xlnx_pcie_xvc config} device
3224 Specifies the PCI Express device via parameter @var{device} to use.
3226 The correct value for @var{device} can be obtained by looking at the output
3227 of lscpi -D (first column) for the corresponding device.
3229 The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
3234 @deffn {Interface Driver} {bcm2835gpio}
3235 This SoC is present in Raspberry Pi which is a cheap single-board computer
3236 exposing some GPIOs on its expansion header.
3238 The driver accesses memory-mapped GPIO peripheral registers directly
3239 for maximum performance, but the only possible race condition is for
3240 the pins' modes/muxing (which is highly unlikely), so it should be
3241 able to coexist nicely with both sysfs bitbanging and various
3242 peripherals' kernel drivers. The driver restores the previous
3243 configuration on exit.
3245 GPIO numbers >= 32 can't be used for performance reasons.
3247 See @file{interface/raspberrypi-native.cfg} for a sample config and
3250 @deffn {Config Command} {bcm2835gpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3251 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
3252 Must be specified to enable JTAG transport. These pins can also be specified
3256 @deffn {Config Command} {bcm2835gpio tck_num} @var{tck}
3257 Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
3258 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3261 @deffn {Config Command} {bcm2835gpio tms_num} @var{tms}
3262 Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
3263 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3266 @deffn {Config Command} {bcm2835gpio tdo_num} @var{tdo}
3267 Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
3268 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3271 @deffn {Config Command} {bcm2835gpio tdi_num} @var{tdi}
3272 Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
3273 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3276 @deffn {Config Command} {bcm2835gpio swd_nums} @var{swclk} @var{swdio}
3277 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3278 specified to enable SWD transport. These pins can also be specified individually.
3281 @deffn {Config Command} {bcm2835gpio swclk_num} @var{swclk}
3282 Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
3283 specified using the configuration command @command{bcm2835gpio swd_nums}.
3286 @deffn {Config Command} {bcm2835gpio swdio_num} @var{swdio}
3287 Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
3288 specified using the configuration command @command{bcm2835gpio swd_nums}.
3291 @deffn {Config Command} {bcm2835gpio swdio_dir_num} @var{swdio} @var{dir}
3292 Set SWDIO direction control pin GPIO number. If specified, this pin can be used
3293 to control the direction of an external buffer on the SWDIO pin (set=output
3294 mode, clear=input mode). If not specified, this feature is disabled.
3297 @deffn {Config Command} {bcm2835gpio srst_num} @var{srst}
3298 Set SRST GPIO number. Must be specified to enable SRST.
3301 @deffn {Config Command} {bcm2835gpio trst_num} @var{trst}
3302 Set TRST GPIO number. Must be specified to enable TRST.
3305 @deffn {Config Command} {bcm2835gpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3306 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified,
3307 speed_coeff defaults to 113714, and speed_offset defaults to 28.
3310 @deffn {Config Command} {bcm2835gpio peripheral_base} @var{base}
3311 Set the peripheral base register address to access GPIOs. For the RPi1, use
3312 0x20000000. For RPi2 and RPi3, use 0x3F000000. For RPi4, use 0xFE000000. A full
3313 list can be found in the
3314 @uref{https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md, official guide}.
3319 @deffn {Interface Driver} {imx_gpio}
3320 i.MX SoC is present in many community boards. Wandboard is an example
3321 of the one which is most popular.
3323 This driver is mostly the same as bcm2835gpio.
3325 See @file{interface/imx-native.cfg} for a sample config and
3331 @deffn {Interface Driver} {am335xgpio} The AM335x SoC is present in BeagleBone
3332 Black and BeagleBone Green single-board computers which expose some of the GPIOs
3333 on the two expansion headers.
3335 For maximum performance the driver accesses memory-mapped GPIO peripheral
3336 registers directly. The memory mapping requires read and write permission to
3337 kernel memory; if /dev/gpiomem exists it will be used, otherwise /dev/mem will
3338 be used. The driver restores the GPIO state on exit.
3340 All four GPIO ports are available. GPIOs numbered 0 to 31 are mapped to GPIO port
3341 0, GPIO numbers 32 to 63 are mapped to GPIO port 1 and so on.
3343 See @file{interface/beaglebone-swd-native.cfg} for a sample configuration file.
3345 @deffn {Config Command} {am335xgpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3346 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
3347 Must be specified to enable JTAG transport. These pins can also be specified
3351 @deffn {Config Command} {am335xgpio tck_num} @var{tck}
3352 Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
3353 specified using the configuration command @command{am335xgpio jtag_nums}.
3356 @deffn {Config Command} {am335xgpio tms_num} @var{tms}
3357 Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
3358 specified using the configuration command @command{am335xgpio jtag_nums}.
3361 @deffn {Config Command} {am335xgpio tdo_num} @var{tdo}
3362 Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
3363 specified using the configuration command @command{am335xgpio jtag_nums}.
3366 @deffn {Config Command} {am335xgpio tdi_num} @var{tdi}
3367 Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
3368 specified using the configuration command @command{am335xgpio jtag_nums}.
3371 @deffn {Config Command} {am335xgpio swd_nums} @var{swclk} @var{swdio}
3372 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3373 specified to enable SWD transport. These pins can also be specified individually.
3376 @deffn {Config Command} {am335xgpio swclk_num} @var{swclk}
3377 Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
3378 specified using the configuration command @command{am335xgpio swd_nums}.
3381 @deffn {Config Command} {am335xgpio swdio_num} @var{swdio}
3382 Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
3383 specified using the configuration command @command{am335xgpio swd_nums}.
3386 @deffn {Config Command} {am335xgpio swdio_dir_num} @var{swdio_dir}
3387 Set SWDIO direction control pin GPIO number. If specified, this pin can be used
3388 to control the direction of an external buffer on the SWDIO pin. The direction
3389 control state can be set with the command @command{am335xgpio
3390 swdio_dir_output_state}. If not specified this feature is disabled.
3393 @deffn {Config Command} {am335xgpio swdio_dir_output_state} @var{output_state}
3394 Set the state required for an external SWDIO buffer to be an output. Valid
3395 values are @option{on} (default) and @option{off}.
3398 @deffn {Config Command} {am335xgpio srst_num} @var{srst}
3399 Set SRST GPIO number. Must be specified to enable SRST.
3402 @deffn {Config Command} {am335xgpio trst_num} @var{trst}
3403 Set TRST GPIO number. Must be specified to enable TRST.
3406 @deffn {Config Command} {am335xgpio led_num} @var{led}
3407 Set activity LED GPIO number. If not specified an activity LED is not enabled.
3410 @deffn {Config Command} {am335xgpio led_on_state} @var{on_state}
3411 Set required logic level for the LED to be on. Valid values are @option{on}
3412 (default) and @option{off}.
3415 @deffn {Config Command} {am335xgpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3416 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified
3417 speed_coeff defaults to 600000 and speed_offset defaults to 575.
3423 @deffn {Interface Driver} {linuxgpiod}
3424 Linux provides userspace access to GPIO through libgpiod since Linux kernel version v4.6.
3425 The driver emulates either JTAG or SWD transport through bitbanging.
3427 See @file{interface/dln-2-gpiod.cfg} for a sample config.
3429 @deffn {Config Command} {linuxgpiod gpiochip} @var{chip}
3430 Set the GPIO chip number for all GPIOs used by linuxgpiod. If GPIOs use
3431 different GPIO chips then the individual GPIO configuration commands (i.e., not
3432 @command{linuxgpiod jtag_nums} or @command{linuxgpiod swd_nums}) can be used to
3433 set chip numbers independently for each GPIO.
3436 @deffn {Config Command} {linuxgpiod jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3437 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order). Must
3438 be specified to enable JTAG transport. These pins can also be specified
3442 @deffn {Config Command} {linuxgpiod tck_num} [@var{chip}] @var{tck}
3443 Set TCK GPIO number, and optionally TCK chip number. Must be specified to enable
3444 JTAG transport. Can also be specified using the configuration command
3445 @command{linuxgpiod jtag_nums}.
3448 @deffn {Config Command} {linuxgpiod tms_num} [@var{chip}] @var{tms}
3449 Set TMS GPIO number, and optionally TMS chip number. Must be specified to enable
3450 JTAG transport. Can also be specified using the configuration command
3451 @command{linuxgpiod jtag_nums}.
3454 @deffn {Config Command} {linuxgpiod tdo_num} [@var{chip}] @var{tdo}
3455 Set TDO GPIO number, and optionally TDO chip number. Must be specified to enable
3456 JTAG transport. Can also be specified using the configuration command
3457 @command{linuxgpiod jtag_nums}.
3460 @deffn {Config Command} {linuxgpiod tdi_num} [@var{chip}] @var{tdi}
3461 Set TDI GPIO number, and optionally TDI chip number. Must be specified to enable
3462 JTAG transport. Can also be specified using the configuration command
3463 @command{linuxgpiod jtag_nums}.
3466 @deffn {Config Command} {linuxgpiod trst_num} [@var{chip}] @var{trst}
3467 Set TRST GPIO number, and optionally TRST chip number. Must be specified to
3471 @deffn {Config Command} {linuxgpiod swd_nums} @var{swclk} @var{swdio}
3472 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3473 specified to enable SWD transport. These pins can also be specified
3477 @deffn {Config Command} {linuxgpiod swclk_num} [@var{chip}] @var{swclk}
3478 Set SWCLK GPIO number, and optionally SWCLK chip number. Must be specified to
3479 enable SWD transport. Can also be specified using the configuration command
3480 @command{linuxgpiod swd_nums}.
3483 @deffn {Config Command} {linuxgpiod swdio_num} [@var{chip}] @var{swdio}
3484 Set SWDIO GPIO number, and optionally SWDIO chip number. Must be specified to
3485 enable SWD transport. Can also be specified using the configuration command
3486 @command{linuxgpiod swd_nums}.
3489 @deffn {Config Command} {linuxgpiod swdio_dir_num} [@var{chip}] @var{swdio_dir}
3490 Set SWDIO direction control GPIO number, and optionally SWDIO direction control
3491 chip number. If specified, this GPIO can be used to control the direction of an
3492 external buffer connected to the SWDIO GPIO (set=output mode, clear=input mode).
3495 @deffn {Config Command} {linuxgpiod srst_num} [@var{chip}] @var{srst}
3496 Set SRST GPIO number, and optionally SRST chip number. Must be specified to
3500 @deffn {Config Command} {linuxgpiod led_num} [@var{chip}] @var{led}
3501 Set activity LED GPIO number, and optionally activity LED chip number. If not
3502 specified an activity LED is not enabled.
3508 @deffn {Interface Driver} {sysfsgpio}
3509 Linux legacy userspace access to GPIO through sysfs is deprecated from Linux kernel version v5.3.
3510 Prefer using @b{linuxgpiod}, instead.
3512 See @file{interface/sysfsgpio-raspberrypi.cfg} for a sample config.
3516 @deffn {Interface Driver} {openjtag}
3517 OpenJTAG compatible USB adapter.
3518 This defines some driver-specific commands:
3520 @deffn {Config Command} {openjtag variant} variant
3521 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3522 Currently valid @var{variant} values include:
3525 @item @b{standard} Standard variant (default).
3526 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3527 (see @uref{http://www.cypress.com/?rID=82870}).
3531 @deffn {Config Command} {openjtag device_desc} string
3532 The USB device description string of the adapter.
3533 This value is only used with the standard variant.
3538 @deffn {Interface Driver} {vdebug}
3539 Cadence Virtual Debug Interface driver.
3541 @deffn {Config Command} {vdebug server} host:port
3542 Specifies the host and TCP port number where the vdebug server runs.
3545 @deffn {Config Command} {vdebug batching} value
3546 Specifies the batching method for the vdebug request. Possible values are
3548 1 or wr to batch write transactions together (default)
3549 2 or rw to batch both read and write transactions
3552 @deffn {Config Command} {vdebug polling} min max
3553 Takes two values, representing the polling interval in ms. Lower values mean faster
3554 debugger responsiveness, but lower emulation performance. The minimum should be
3555 around 10, maximum should not exceed 1000, which is the default gdb and keepalive
3559 @deffn {Config Command} {vdebug bfm_path} path clk_period
3560 Specifies the hierarchical path and input clk period of the vdebug BFM in the design.
3561 The hierarchical path uses Verilog notation top.inst.inst
3562 The clock period must include the unit, for instance 40ns.
3565 @deffn {Config Command} {vdebug mem_path} path base size
3566 Specifies the hierarchical path to the design memory instance for backdoor access.
3567 Up to 4 memories can be specified. The hierarchical path uses Verilog notation.
3568 The base specifies start address in the design address space, size its size in bytes.
3569 Both values can use hexadecimal notation with prefix 0x.
3573 @deffn {Interface Driver} {jtag_dpi}
3574 SystemVerilog Direct Programming Interface (DPI) compatible driver for
3575 JTAG devices in emulation. The driver acts as a client for the SystemVerilog
3576 DPI server interface.
3578 @deffn {Config Command} {jtag_dpi set_port} port
3579 Specifies the TCP/IP port number of the SystemVerilog DPI server interface.
3582 @deffn {Config Command} {jtag_dpi set_address} address
3583 Specifies the TCP/IP address of the SystemVerilog DPI server interface.
3588 @deffn {Interface Driver} {buspirate}
3590 This driver is for the Bus Pirate (see @url{http://dangerousprototypes.com/docs/Bus_Pirate}) and compatible devices.
3591 It uses a simple data protocol over a serial port connection.
3593 Most hardware development boards have a UART, a real serial port, or a virtual USB serial device, so this driver
3594 allows you to start building your own JTAG adapter without the complexity of a custom USB connection.
3596 @deffn {Config Command} {buspirate port} serial_port
3597 Specify the serial port's filename. For example:
3599 buspirate port /dev/ttyUSB0
3603 @deffn {Config Command} {buspirate speed} (normal|fast)
3604 Set the communication speed to 115k (normal) or 1M (fast). For example:
3606 buspirate speed normal
3610 @deffn {Config Command} {buspirate mode} (normal|open-drain)
3611 Set the Bus Pirate output mode.
3613 @item In normal mode (push/pull), do not enable the pull-ups, and do not connect I/O header pin VPU to JTAG VREF.
3614 @item In open drain mode, you will then need to enable the pull-ups.
3618 buspirate mode normal
3622 @deffn {Config Command} {buspirate pullup} (0|1)
3623 Whether to connect (1) or not (0) the I/O header pin VPU (JTAG VREF)
3624 to the pull-up/pull-down resistors on MOSI (JTAG TDI), CLK (JTAG TCK), MISO (JTAG TDO) and CS (JTAG TMS).
3631 @deffn {Config Command} {buspirate vreg} (0|1)
3632 Whether to enable (1) or disable (0) the built-in voltage regulator,
3633 which can be used to supply power to a test circuit through
3634 I/O header pins +3V3 and +5V. For example:
3640 @deffn {Command} {buspirate led} (0|1)
3641 Turns the Bus Pirate's LED on (1) or off (0). For example:
3649 @deffn {Interface Driver} {esp_usb_jtag}
3650 Espressif JTAG driver to communicate with ESP32-C3, ESP32-S3 chips and ESP USB Bridge board using OpenOCD.
3651 These chips have built-in JTAG circuitry and can be debugged without any additional hardware.
3652 Only an USB cable connected to the D+/D- pins is necessary.
3654 @deffn {Config Command} {espusbjtag tdo}
3655 Returns the current state of the TDO line
3658 @deffn {Config Command} {espusbjtag setio} setio
3659 Manually set the status of the output lines with the order of (tdi tms tck trst srst)
3661 espusbjtag setio 0 1 0 1 0
3665 @deffn {Config Command} {espusbjtag vid_pid} vid_pid
3666 Set vendor ID and product ID for the ESP usb jtag driver
3668 espusbjtag vid_pid 0x303a 0x1001
3672 @deffn {Config Command} {espusbjtag caps_descriptor} caps_descriptor
3673 Set the jtag descriptor to read capabilities of ESP usb jtag driver
3675 espusbjtag caps_descriptor 0x2000
3679 @deffn {Config Command} {espusbjtag chip_id} chip_id
3680 Set chip id to transfer to the ESP USB bridge board
3682 espusbjtag chip_id 1
3688 @section Transport Configuration
3690 As noted earlier, depending on the version of OpenOCD you use,
3691 and the debug adapter you are using,
3692 several transports may be available to
3693 communicate with debug targets (or perhaps to program flash memory).
3694 @deffn {Command} {transport list}
3695 displays the names of the transports supported by this
3699 @deffn {Command} {transport select} @option{transport_name}
3700 Select which of the supported transports to use in this OpenOCD session.
3702 When invoked with @option{transport_name}, attempts to select the named
3703 transport. The transport must be supported by the debug adapter
3704 hardware and by the version of OpenOCD you are using (including the
3707 If no transport has been selected and no @option{transport_name} is
3708 provided, @command{transport select} auto-selects the first transport
3709 supported by the debug adapter.
3711 @command{transport select} always returns the name of the session's selected
3715 @subsection JTAG Transport
3717 JTAG is the original transport supported by OpenOCD, and most
3718 of the OpenOCD commands support it.
3719 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3720 each of which must be explicitly declared.
3721 JTAG supports both debugging and boundary scan testing.
3722 Flash programming support is built on top of debug support.
3724 JTAG transport is selected with the command @command{transport select
3725 jtag}. Unless your adapter uses either @ref{hla_interface,the hla interface
3726 driver} (in which case the command is @command{transport select hla_jtag})
3727 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3728 the command is @command{transport select dapdirect_jtag}).
3730 @subsection SWD Transport
3732 @cindex Serial Wire Debug
3733 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3734 Debug Access Point (DAP, which must be explicitly declared.
3735 (SWD uses fewer signal wires than JTAG.)
3736 SWD is debug-oriented, and does not support boundary scan testing.
3737 Flash programming support is built on top of debug support.
3738 (Some processors support both JTAG and SWD.)
3740 SWD transport is selected with the command @command{transport select
3741 swd}. Unless your adapter uses either @ref{hla_interface,the hla interface
3742 driver} (in which case the command is @command{transport select hla_swd})
3743 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3744 the command is @command{transport select dapdirect_swd}).
3746 @deffn {Config Command} {swd newdap} ...
3747 Declares a single DAP which uses SWD transport.
3748 Parameters are currently the same as "jtag newtap" but this is
3752 @cindex SWD multi-drop
3753 The newer SWD devices (SW-DP v2 or SWJ-DP v2) support the multi-drop extension
3754 of SWD protocol: two or more devices can be connected to one SWD adapter.
3755 SWD transport works in multi-drop mode if @ref{dap_create,DAP} is configured
3756 with both @code{-dp-id} and @code{-instance-id} parameters regardless how many
3759 Not all adapters and adapter drivers support SWD multi-drop. Only the following
3760 adapter drivers are SWD multi-drop capable:
3761 cmsis_dap (use an adapter with CMSIS-DAP version 2.0), ftdi, all bitbang based.
3763 @subsection SPI Transport
3765 @cindex Serial Peripheral Interface
3766 The Serial Peripheral Interface (SPI) is a general purpose transport
3767 which uses four wire signaling. Some processors use it as part of a
3768 solution for flash programming.
3770 @anchor{swimtransport}
3771 @subsection SWIM Transport
3773 @cindex Single Wire Interface Module
3774 The Single Wire Interface Module (SWIM) is a low-pin-count debug protocol used
3775 by the STMicroelectronics MCU family STM8 and documented in the
3776 @uref{https://www.st.com/resource/en/user_manual/cd00173911.pdf, User Manual UM470}.
3778 SWIM does not support boundary scan testing nor multiple cores.
3780 The SWIM transport is selected with the command @command{transport select swim}.
3782 The concept of TAPs does not fit in the protocol since SWIM does not implement
3783 a scan chain. Nevertheless, the current SW model of OpenOCD requires defining a
3784 virtual SWIM TAP through the command @command{swim newtap basename tap_type}.
3785 The TAP definition must precede the target definition command
3786 @command{target create target_name stm8 -chain-position basename.tap_type}.
3790 JTAG clock setup is part of system setup.
3791 It @emph{does not belong with interface setup} since any interface
3792 only knows a few of the constraints for the JTAG clock speed.
3793 Sometimes the JTAG speed is
3794 changed during the target initialization process: (1) slow at
3795 reset, (2) program the CPU clocks, (3) run fast.
3796 Both the "slow" and "fast" clock rates are functions of the
3797 oscillators used, the chip, the board design, and sometimes
3798 power management software that may be active.
3800 The speed used during reset, and the scan chain verification which
3801 follows reset, can be adjusted using a @code{reset-start}
3802 target event handler.
3803 It can then be reconfigured to a faster speed by a
3804 @code{reset-init} target event handler after it reprograms those
3805 CPU clocks, or manually (if something else, such as a boot loader,
3806 sets up those clocks).
3807 @xref{targetevents,,Target Events}.
3808 When the initial low JTAG speed is a chip characteristic, perhaps
3809 because of a required oscillator speed, provide such a handler
3810 in the target config file.
3811 When that speed is a function of a board-specific characteristic
3812 such as which speed oscillator is used, it belongs in the board
3813 config file instead.
3814 In both cases it's safest to also set the initial JTAG clock rate
3815 to that same slow speed, so that OpenOCD never starts up using a
3816 clock speed that's faster than the scan chain can support.
3820 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3823 If your system supports adaptive clocking (RTCK), configuring
3824 JTAG to use that is probably the most robust approach.
3825 However, it introduces delays to synchronize clocks; so it
3826 may not be the fastest solution.
3828 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3829 instead of @command{adapter speed}, but only for (ARM) cores and boards
3830 which support adaptive clocking.
3832 @deffn {Command} {adapter speed} max_speed_kHz
3833 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3834 JTAG interfaces usually support a limited number of
3835 speeds. The speed actually used won't be faster
3836 than the speed specified.
3838 Chip data sheets generally include a top JTAG clock rate.
3839 The actual rate is often a function of a CPU core clock,
3840 and is normally less than that peak rate.
3841 For example, most ARM cores accept at most one sixth of the CPU clock.
3843 Speed 0 (khz) selects RTCK method.
3844 @xref{faqrtck,,FAQ RTCK}.
3845 If your system uses RTCK, you won't need to change the
3846 JTAG clocking after setup.
3847 Not all interfaces, boards, or targets support ``rtck''.
3848 If the interface device can not
3849 support it, an error is returned when you try to use RTCK.
3852 @defun jtag_rclk fallback_speed_kHz
3853 @cindex adaptive clocking
3855 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3856 If that fails (maybe the interface, board, or target doesn't
3857 support it), falls back to the specified frequency.
3859 # Fall back to 3mhz if RTCK is not supported
3864 @node Reset Configuration
3865 @chapter Reset Configuration
3866 @cindex Reset Configuration
3868 Every system configuration may require a different reset
3869 configuration. This can also be quite confusing.
3870 Resets also interact with @var{reset-init} event handlers,
3871 which do things like setting up clocks and DRAM, and
3872 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3873 They can also interact with JTAG routers.
3874 Please see the various board files for examples.
3877 To maintainers and integrators:
3878 Reset configuration touches several things at once.
3879 Normally the board configuration file
3880 should define it and assume that the JTAG adapter supports
3881 everything that's wired up to the board's JTAG connector.
3883 However, the target configuration file could also make note
3884 of something the silicon vendor has done inside the chip,
3885 which will be true for most (or all) boards using that chip.
3886 And when the JTAG adapter doesn't support everything, the
3887 user configuration file will need to override parts of
3888 the reset configuration provided by other files.
3891 @section Types of Reset
3893 There are many kinds of reset possible through JTAG, but
3894 they may not all work with a given board and adapter.
3895 That's part of why reset configuration can be error prone.
3899 @emph{System Reset} ... the @emph{SRST} hardware signal
3900 resets all chips connected to the JTAG adapter, such as processors,
3901 power management chips, and I/O controllers. Normally resets triggered
3902 with this signal behave exactly like pressing a RESET button.
3904 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3905 just the TAP controllers connected to the JTAG adapter.
3906 Such resets should not be visible to the rest of the system; resetting a
3907 device's TAP controller just puts that controller into a known state.
3909 @emph{Emulation Reset} ... many devices can be reset through JTAG
3910 commands. These resets are often distinguishable from system
3911 resets, either explicitly (a "reset reason" register says so)
3912 or implicitly (not all parts of the chip get reset).
3914 @emph{Other Resets} ... system-on-chip devices often support
3915 several other types of reset.
3916 You may need to arrange that a watchdog timer stops
3917 while debugging, preventing a watchdog reset.
3918 There may be individual module resets.
3921 In the best case, OpenOCD can hold SRST, then reset
3922 the TAPs via TRST and send commands through JTAG to halt the
3923 CPU at the reset vector before the 1st instruction is executed.
3924 Then when it finally releases the SRST signal, the system is
3925 halted under debugger control before any code has executed.
3926 This is the behavior required to support the @command{reset halt}
3927 and @command{reset init} commands; after @command{reset init} a
3928 board-specific script might do things like setting up DRAM.
3929 (@xref{resetcommand,,Reset Command}.)
3931 @anchor{srstandtrstissues}
3932 @section SRST and TRST Issues
3934 Because SRST and TRST are hardware signals, they can have a
3935 variety of system-specific constraints. Some of the most
3940 @item @emph{Signal not available} ... Some boards don't wire
3941 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3942 support such signals even if they are wired up.
3943 Use the @command{reset_config} @var{signals} options to say
3944 when either of those signals is not connected.
3945 When SRST is not available, your code might not be able to rely
3946 on controllers having been fully reset during code startup.
3947 Missing TRST is not a problem, since JTAG-level resets can
3948 be triggered using with TMS signaling.
3950 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3951 adapter will connect SRST to TRST, instead of keeping them separate.
3952 Use the @command{reset_config} @var{combination} options to say
3953 when those signals aren't properly independent.
3955 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3956 delay circuit, reset supervisor, or on-chip features can extend
3957 the effect of a JTAG adapter's reset for some time after the adapter
3958 stops issuing the reset. For example, there may be chip or board
3959 requirements that all reset pulses last for at least a
3960 certain amount of time; and reset buttons commonly have
3961 hardware debouncing.
3962 Use the @command{adapter srst delay} and @command{jtag_ntrst_delay}
3963 commands to say when extra delays are needed.
3965 @item @emph{Drive type} ... Reset lines often have a pullup
3966 resistor, letting the JTAG interface treat them as open-drain
3967 signals. But that's not a requirement, so the adapter may need
3968 to use push/pull output drivers.
3969 Also, with weak pullups it may be advisable to drive
3970 signals to both levels (push/pull) to minimize rise times.
3971 Use the @command{reset_config} @var{trst_type} and
3972 @var{srst_type} parameters to say how to drive reset signals.
3974 @item @emph{Special initialization} ... Targets sometimes need
3975 special JTAG initialization sequences to handle chip-specific
3976 issues (not limited to errata).
3977 For example, certain JTAG commands might need to be issued while
3978 the system as a whole is in a reset state (SRST active)
3979 but the JTAG scan chain is usable (TRST inactive).
3980 Many systems treat combined assertion of SRST and TRST as a
3981 trigger for a harder reset than SRST alone.
3982 Such custom reset handling is discussed later in this chapter.
3985 There can also be other issues.
3986 Some devices don't fully conform to the JTAG specifications.
3987 Trivial system-specific differences are common, such as
3988 SRST and TRST using slightly different names.
3989 There are also vendors who distribute key JTAG documentation for
3990 their chips only to developers who have signed a Non-Disclosure
3993 Sometimes there are chip-specific extensions like a requirement to use
3994 the normally-optional TRST signal (precluding use of JTAG adapters which
3995 don't pass TRST through), or needing extra steps to complete a TAP reset.
3997 In short, SRST and especially TRST handling may be very finicky,
3998 needing to cope with both architecture and board specific constraints.
4000 @section Commands for Handling Resets
4002 @deffn {Command} {adapter srst pulse_width} milliseconds
4003 Minimum amount of time (in milliseconds) OpenOCD should wait
4004 after asserting nSRST (active-low system reset) before
4005 allowing it to be deasserted.
4008 @deffn {Command} {adapter srst delay} milliseconds
4009 How long (in milliseconds) OpenOCD should wait after deasserting
4010 nSRST (active-low system reset) before starting new JTAG operations.
4011 When a board has a reset button connected to SRST line it will
4012 probably have hardware debouncing, implying you should use this.
4015 @deffn {Command} {jtag_ntrst_assert_width} milliseconds
4016 Minimum amount of time (in milliseconds) OpenOCD should wait
4017 after asserting nTRST (active-low JTAG TAP reset) before
4018 allowing it to be deasserted.
4021 @deffn {Command} {jtag_ntrst_delay} milliseconds
4022 How long (in milliseconds) OpenOCD should wait after deasserting
4023 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
4026 @anchor{reset_config}
4027 @deffn {Command} {reset_config} mode_flag ...
4028 This command displays or modifies the reset configuration
4029 of your combination of JTAG board and target in target
4030 configuration scripts.
4032 Information earlier in this section describes the kind of problems
4033 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
4034 As a rule this command belongs only in board config files,
4035 describing issues like @emph{board doesn't connect TRST};
4036 or in user config files, addressing limitations derived
4037 from a particular combination of interface and board.
4038 (An unlikely example would be using a TRST-only adapter
4039 with a board that only wires up SRST.)
4041 The @var{mode_flag} options can be specified in any order, but only one
4042 of each type -- @var{signals}, @var{combination}, @var{gates},
4043 @var{trst_type}, @var{srst_type} and @var{connect_type}
4044 -- may be specified at a time.
4045 If you don't provide a new value for a given type, its previous
4046 value (perhaps the default) is unchanged.
4047 For example, this means that you don't need to say anything at all about
4048 TRST just to declare that if the JTAG adapter should want to drive SRST,
4049 it must explicitly be driven high (@option{srst_push_pull}).
4053 @var{signals} can specify which of the reset signals are connected.
4054 For example, If the JTAG interface provides SRST, but the board doesn't
4055 connect that signal properly, then OpenOCD can't use it.
4056 Possible values are @option{none} (the default), @option{trst_only},
4057 @option{srst_only} and @option{trst_and_srst}.
4060 If your board provides SRST and/or TRST through the JTAG connector,
4061 you must declare that so those signals can be used.
4065 The @var{combination} is an optional value specifying broken reset
4066 signal implementations.
4067 The default behaviour if no option given is @option{separate},
4068 indicating everything behaves normally.
4069 @option{srst_pulls_trst} states that the
4070 test logic is reset together with the reset of the system (e.g. NXP
4071 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
4072 the system is reset together with the test logic (only hypothetical, I
4073 haven't seen hardware with such a bug, and can be worked around).
4074 @option{combined} implies both @option{srst_pulls_trst} and
4075 @option{trst_pulls_srst}.
4078 The @var{gates} tokens control flags that describe some cases where
4079 JTAG may be unavailable during reset.
4080 @option{srst_gates_jtag} (default)
4081 indicates that asserting SRST gates the
4082 JTAG clock. This means that no communication can happen on JTAG
4083 while SRST is asserted.
4084 Its converse is @option{srst_nogate}, indicating that JTAG commands
4085 can safely be issued while SRST is active.
4088 The @var{connect_type} tokens control flags that describe some cases where
4089 SRST is asserted while connecting to the target. @option{srst_nogate}
4090 is required to use this option.
4091 @option{connect_deassert_srst} (default)
4092 indicates that SRST will not be asserted while connecting to the target.
4093 Its converse is @option{connect_assert_srst}, indicating that SRST will
4094 be asserted before any target connection.
4095 Only some targets support this feature, STM32 and STR9 are examples.
4096 This feature is useful if you are unable to connect to your target due
4097 to incorrect options byte config or illegal program execution.
4100 The optional @var{trst_type} and @var{srst_type} parameters allow the
4101 driver mode of each reset line to be specified. These values only affect
4102 JTAG interfaces with support for different driver modes, like the Amontec
4103 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
4104 relevant signal (TRST or SRST) is not connected.
4108 Possible @var{trst_type} driver modes for the test reset signal (TRST)
4109 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
4110 Most boards connect this signal to a pulldown, so the JTAG TAPs
4111 never leave reset unless they are hooked up to a JTAG adapter.
4114 Possible @var{srst_type} driver modes for the system reset signal (SRST)
4115 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
4116 Most boards connect this signal to a pullup, and allow the
4117 signal to be pulled low by various events including system
4118 power-up and pressing a reset button.
4122 @section Custom Reset Handling
4125 OpenOCD has several ways to help support the various reset
4126 mechanisms provided by chip and board vendors.
4127 The commands shown in the previous section give standard parameters.
4128 There are also @emph{event handlers} associated with TAPs or Targets.
4129 Those handlers are Tcl procedures you can provide, which are invoked
4130 at particular points in the reset sequence.
4132 @emph{When SRST is not an option} you must set
4133 up a @code{reset-assert} event handler for your target.
4134 For example, some JTAG adapters don't include the SRST signal;
4135 and some boards have multiple targets, and you won't always
4136 want to reset everything at once.
4138 After configuring those mechanisms, you might still
4139 find your board doesn't start up or reset correctly.
4140 For example, maybe it needs a slightly different sequence
4141 of SRST and/or TRST manipulations, because of quirks that
4142 the @command{reset_config} mechanism doesn't address;
4143 or asserting both might trigger a stronger reset, which
4144 needs special attention.
4146 Experiment with lower level operations, such as
4147 @command{adapter assert}, @command{adapter deassert}
4148 and the @command{jtag arp_*} operations shown here,
4149 to find a sequence of operations that works.
4150 @xref{JTAG Commands}.
4151 When you find a working sequence, it can be used to override
4152 @command{jtag_init}, which fires during OpenOCD startup
4153 (@pxref{configurationstage,,Configuration Stage});
4154 or @command{init_reset}, which fires during reset processing.
4156 You might also want to provide some project-specific reset
4157 schemes. For example, on a multi-target board the standard
4158 @command{reset} command would reset all targets, but you
4159 may need the ability to reset only one target at time and
4160 thus want to avoid using the board-wide SRST signal.
4162 @deffn {Overridable Procedure} {init_reset} mode
4163 This is invoked near the beginning of the @command{reset} command,
4164 usually to provide as much of a cold (power-up) reset as practical.
4165 By default it is also invoked from @command{jtag_init} if
4166 the scan chain does not respond to pure JTAG operations.
4167 The @var{mode} parameter is the parameter given to the
4168 low level reset command (@option{halt},
4169 @option{init}, or @option{run}), @option{setup},
4170 or potentially some other value.
4172 The default implementation just invokes @command{jtag arp_init-reset}.
4173 Replacements will normally build on low level JTAG
4174 operations such as @command{adapter assert} and @command{adapter deassert}.
4175 Operations here must not address individual TAPs
4176 (or their associated targets)
4177 until the JTAG scan chain has first been verified to work.
4179 Implementations must have verified the JTAG scan chain before
4181 This is done by calling @command{jtag arp_init}
4182 (or @command{jtag arp_init-reset}).
4185 @deffn {Command} {jtag arp_init}
4186 This validates the scan chain using just the four
4187 standard JTAG signals (TMS, TCK, TDI, TDO).
4188 It starts by issuing a JTAG-only reset.
4189 Then it performs checks to verify that the scan chain configuration
4190 matches the TAPs it can observe.
4191 Those checks include checking IDCODE values for each active TAP,
4192 and verifying the length of their instruction registers using
4193 TAP @code{-ircapture} and @code{-irmask} values.
4194 If these tests all pass, TAP @code{setup} events are
4195 issued to all TAPs with handlers for that event.
4198 @deffn {Command} {jtag arp_init-reset}
4199 This uses TRST and SRST to try resetting
4200 everything on the JTAG scan chain
4201 (and anything else connected to SRST).
4202 It then invokes the logic of @command{jtag arp_init}.
4206 @node TAP Declaration
4207 @chapter TAP Declaration
4208 @cindex TAP declaration
4209 @cindex TAP configuration
4211 @emph{Test Access Ports} (TAPs) are the core of JTAG.
4212 TAPs serve many roles, including:
4215 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
4216 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
4217 Others do it indirectly, making a CPU do it.
4218 @item @b{Program Download} Using the same CPU support GDB uses,
4219 you can initialize a DRAM controller, download code to DRAM, and then
4220 start running that code.
4221 @item @b{Boundary Scan} Most chips support boundary scan, which
4222 helps test for board assembly problems like solder bridges
4223 and missing connections.
4226 OpenOCD must know about the active TAPs on your board(s).
4227 Setting up the TAPs is the core task of your configuration files.
4228 Once those TAPs are set up, you can pass their names to code
4229 which sets up CPUs and exports them as GDB targets,
4230 probes flash memory, performs low-level JTAG operations, and more.
4232 @section Scan Chains
4235 TAPs are part of a hardware @dfn{scan chain},
4236 which is a daisy chain of TAPs.
4237 They also need to be added to
4238 OpenOCD's software mirror of that hardware list,
4239 giving each member a name and associating other data with it.
4240 Simple scan chains, with a single TAP, are common in
4241 systems with a single microcontroller or microprocessor.
4242 More complex chips may have several TAPs internally.
4243 Very complex scan chains might have a dozen or more TAPs:
4244 several in one chip, more in the next, and connecting
4245 to other boards with their own chips and TAPs.
4247 You can display the list with the @command{scan_chain} command.
4248 (Don't confuse this with the list displayed by the @command{targets}
4249 command, presented in the next chapter.
4250 That only displays TAPs for CPUs which are configured as
4252 Here's what the scan chain might look like for a chip more than one TAP:
4255 TapName Enabled IdCode Expected IrLen IrCap IrMask
4256 -- ------------------ ------- ---------- ---------- ----- ----- ------
4257 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
4258 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
4259 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
4262 OpenOCD can detect some of that information, but not all
4263 of it. @xref{autoprobing,,Autoprobing}.
4264 Unfortunately, those TAPs can't always be autoconfigured,
4265 because not all devices provide good support for that.
4266 JTAG doesn't require supporting IDCODE instructions, and
4267 chips with JTAG routers may not link TAPs into the chain
4268 until they are told to do so.
4270 The configuration mechanism currently supported by OpenOCD
4271 requires explicit configuration of all TAP devices using
4272 @command{jtag newtap} commands, as detailed later in this chapter.
4273 A command like this would declare one tap and name it @code{chip1.cpu}:
4276 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
4279 Each target configuration file lists the TAPs provided
4281 Board configuration files combine all the targets on a board,
4283 Note that @emph{the order in which TAPs are declared is very important.}
4284 That declaration order must match the order in the JTAG scan chain,
4285 both inside a single chip and between them.
4286 @xref{faqtaporder,,FAQ TAP Order}.
4288 For example, the STMicroelectronics STR912 chip has
4289 three separate TAPs@footnote{See the ST
4290 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
4291 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
4292 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
4293 To configure those taps, @file{target/str912.cfg}
4294 includes commands something like this:
4297 jtag newtap str912 flash ... params ...
4298 jtag newtap str912 cpu ... params ...
4299 jtag newtap str912 bs ... params ...
4302 Actual config files typically use a variable such as @code{$_CHIPNAME}
4303 instead of literals like @option{str912}, to support more than one chip
4304 of each type. @xref{Config File Guidelines}.
4306 @deffn {Command} {jtag names}
4307 Returns the names of all current TAPs in the scan chain.
4308 Use @command{jtag cget} or @command{jtag tapisenabled}
4309 to examine attributes and state of each TAP.
4311 foreach t [jtag names] @{
4312 puts [format "TAP: %s\n" $t]
4317 @deffn {Command} {scan_chain}
4318 Displays the TAPs in the scan chain configuration,
4320 The set of TAPs listed by this command is fixed by
4321 exiting the OpenOCD configuration stage,
4322 but systems with a JTAG router can
4323 enable or disable TAPs dynamically.
4326 @c FIXME! "jtag cget" should be able to return all TAP
4327 @c attributes, like "$target_name cget" does for targets.
4329 @c Probably want "jtag eventlist", and a "tap-reset" event
4330 @c (on entry to RESET state).
4335 When TAP objects are declared with @command{jtag newtap},
4336 a @dfn{dotted.name} is created for the TAP, combining the
4337 name of a module (usually a chip) and a label for the TAP.
4338 For example: @code{xilinx.tap}, @code{str912.flash},
4339 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
4340 Many other commands use that dotted.name to manipulate or
4341 refer to the TAP. For example, CPU configuration uses the
4342 name, as does declaration of NAND or NOR flash banks.
4344 The components of a dotted name should follow ``C'' symbol
4345 name rules: start with an alphabetic character, then numbers
4346 and underscores are OK; while others (including dots!) are not.
4348 @section TAP Declaration Commands
4350 @deffn {Config Command} {jtag newtap} chipname tapname configparams...
4351 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
4352 and configured according to the various @var{configparams}.
4354 The @var{chipname} is a symbolic name for the chip.
4355 Conventionally target config files use @code{$_CHIPNAME},
4356 defaulting to the model name given by the chip vendor but
4359 @cindex TAP naming convention
4360 The @var{tapname} reflects the role of that TAP,
4361 and should follow this convention:
4364 @item @code{bs} -- For boundary scan if this is a separate TAP;
4365 @item @code{cpu} -- The main CPU of the chip, alternatively
4366 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
4367 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
4368 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
4369 @item @code{flash} -- If the chip has a flash TAP, like the str912;
4370 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
4371 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
4372 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
4374 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
4375 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
4376 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
4377 a JTAG TAP; that TAP should be named @code{sdma}.
4380 Every TAP requires at least the following @var{configparams}:
4383 @item @code{-irlen} @var{NUMBER}
4384 @*The length in bits of the
4385 instruction register, such as 4 or 5 bits.
4388 A TAP may also provide optional @var{configparams}:
4391 @item @code{-disable} (or @code{-enable})
4392 @*Use the @code{-disable} parameter to flag a TAP which is not
4393 linked into the scan chain after a reset using either TRST
4394 or the JTAG state machine's @sc{reset} state.
4395 You may use @code{-enable} to highlight the default state
4396 (the TAP is linked in).
4397 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
4398 @item @code{-expected-id} @var{NUMBER}
4399 @*A non-zero @var{number} represents a 32-bit IDCODE
4400 which you expect to find when the scan chain is examined.
4401 These codes are not required by all JTAG devices.
4402 @emph{Repeat the option} as many times as required if more than one
4403 ID code could appear (for example, multiple versions).
4404 Specify @var{number} as zero to suppress warnings about IDCODE
4405 values that were found but not included in the list.
4407 Provide this value if at all possible, since it lets OpenOCD
4408 tell when the scan chain it sees isn't right. These values
4409 are provided in vendors' chip documentation, usually a technical
4410 reference manual. Sometimes you may need to probe the JTAG
4411 hardware to find these values.
4412 @xref{autoprobing,,Autoprobing}.
4413 @item @code{-ignore-version}
4414 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
4415 option. When vendors put out multiple versions of a chip, or use the same
4416 JTAG-level ID for several largely-compatible chips, it may be more practical
4417 to ignore the version field than to update config files to handle all of
4418 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
4419 @item @code{-ignore-bypass}
4420 @*Specify this to ignore the 'bypass' bit of the idcode. Some vendor put
4421 an invalid idcode regarding this bit. Specify this to ignore this bit and
4422 to not consider this tap in bypass mode.
4423 @item @code{-ircapture} @var{NUMBER}
4424 @*The bit pattern loaded by the TAP into the JTAG shift register
4425 on entry to the @sc{ircapture} state, such as 0x01.
4426 JTAG requires the two LSBs of this value to be 01.
4427 By default, @code{-ircapture} and @code{-irmask} are set
4428 up to verify that two-bit value. You may provide
4429 additional bits if you know them, or indicate that
4430 a TAP doesn't conform to the JTAG specification.
4431 @item @code{-irmask} @var{NUMBER}
4432 @*A mask used with @code{-ircapture}
4433 to verify that instruction scans work correctly.
4434 Such scans are not used by OpenOCD except to verify that
4435 there seems to be no problems with JTAG scan chain operations.
4436 @item @code{-ignore-syspwrupack}
4437 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4438 register during initial examination and when checking the sticky error bit.
4439 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4440 devices do not set the ack bit until sometime later.
4444 @section Other TAP commands
4446 @deffn {Command} {jtag cget} dotted.name @option{-idcode}
4447 Get the value of the IDCODE found in hardware.
4450 @deffn {Command} {jtag cget} dotted.name @option{-event} event_name
4451 @deffnx {Command} {jtag configure} dotted.name @option{-event} event_name handler
4452 At this writing this TAP attribute
4453 mechanism is limited and used mostly for event handling.
4454 (It is not a direct analogue of the @code{cget}/@code{configure}
4455 mechanism for debugger targets.)
4456 See the next section for information about the available events.
4458 The @code{configure} subcommand assigns an event handler,
4459 a TCL string which is evaluated when the event is triggered.
4460 The @code{cget} subcommand returns that handler.
4467 OpenOCD includes two event mechanisms.
4468 The one presented here applies to all JTAG TAPs.
4469 The other applies to debugger targets,
4470 which are associated with certain TAPs.
4472 The TAP events currently defined are:
4475 @item @b{post-reset}
4476 @* The TAP has just completed a JTAG reset.
4477 The tap may still be in the JTAG @sc{reset} state.
4478 Handlers for these events might perform initialization sequences
4479 such as issuing TCK cycles, TMS sequences to ensure
4480 exit from the ARM SWD mode, and more.
4482 Because the scan chain has not yet been verified, handlers for these events
4483 @emph{should not issue commands which scan the JTAG IR or DR registers}
4484 of any particular target.
4485 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
4487 @* The scan chain has been reset and verified.
4488 This handler may enable TAPs as needed.
4489 @item @b{tap-disable}
4490 @* The TAP needs to be disabled. This handler should
4491 implement @command{jtag tapdisable}
4492 by issuing the relevant JTAG commands.
4493 @item @b{tap-enable}
4494 @* The TAP needs to be enabled. This handler should
4495 implement @command{jtag tapenable}
4496 by issuing the relevant JTAG commands.
4499 If you need some action after each JTAG reset which isn't actually
4500 specific to any TAP (since you can't yet trust the scan chain's
4501 contents to be accurate), you might:
4504 jtag configure CHIP.jrc -event post-reset @{
4505 echo "JTAG Reset done"
4506 ... non-scan jtag operations to be done after reset
4511 @anchor{enablinganddisablingtaps}
4512 @section Enabling and Disabling TAPs
4513 @cindex JTAG Route Controller
4516 In some systems, a @dfn{JTAG Route Controller} (JRC)
4517 is used to enable and/or disable specific JTAG TAPs.
4518 Many ARM-based chips from Texas Instruments include
4519 an ``ICEPick'' module, which is a JRC.
4520 Such chips include DaVinci and OMAP3 processors.
4522 A given TAP may not be visible until the JRC has been
4523 told to link it into the scan chain; and if the JRC
4524 has been told to unlink that TAP, it will no longer
4526 Such routers address problems that JTAG ``bypass mode''
4530 @item The scan chain can only go as fast as its slowest TAP.
4531 @item Having many TAPs slows instruction scans, since all
4532 TAPs receive new instructions.
4533 @item TAPs in the scan chain must be powered up, which wastes
4534 power and prevents debugging some power management mechanisms.
4537 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
4538 as implied by the existence of JTAG routers.
4539 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
4540 does include a kind of JTAG router functionality.
4542 @c (a) currently the event handlers don't seem to be able to
4543 @c fail in a way that could lead to no-change-of-state.
4545 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
4546 shown below, and is implemented using TAP event handlers.
4547 So for example, when defining a TAP for a CPU connected to
4548 a JTAG router, your @file{target.cfg} file
4549 should define TAP event handlers using
4550 code that looks something like this:
4553 jtag configure CHIP.cpu -event tap-enable @{
4554 ... jtag operations using CHIP.jrc
4556 jtag configure CHIP.cpu -event tap-disable @{
4557 ... jtag operations using CHIP.jrc
4561 Then you might want that CPU's TAP enabled almost all the time:
4564 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
4567 Note how that particular setup event handler declaration
4568 uses quotes to evaluate @code{$CHIP} when the event is configured.
4569 Using brackets @{ @} would cause it to be evaluated later,
4570 at runtime, when it might have a different value.
4572 @deffn {Command} {jtag tapdisable} dotted.name
4573 If necessary, disables the tap
4574 by sending it a @option{tap-disable} event.
4575 Returns the string "1" if the tap
4576 specified by @var{dotted.name} is enabled,
4577 and "0" if it is disabled.
4580 @deffn {Command} {jtag tapenable} dotted.name
4581 If necessary, enables the tap
4582 by sending it a @option{tap-enable} event.
4583 Returns the string "1" if the tap
4584 specified by @var{dotted.name} is enabled,
4585 and "0" if it is disabled.
4588 @deffn {Command} {jtag tapisenabled} dotted.name
4589 Returns the string "1" if the tap
4590 specified by @var{dotted.name} is enabled,
4591 and "0" if it is disabled.
4594 Humans will find the @command{scan_chain} command more helpful
4595 for querying the state of the JTAG taps.
4599 @anchor{autoprobing}
4600 @section Autoprobing
4602 @cindex JTAG autoprobe
4604 TAP configuration is the first thing that needs to be done
4605 after interface and reset configuration. Sometimes it's
4606 hard finding out what TAPs exist, or how they are identified.
4607 Vendor documentation is not always easy to find and use.
4609 To help you get past such problems, OpenOCD has a limited
4610 @emph{autoprobing} ability to look at the scan chain, doing
4611 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4612 To use this mechanism, start the OpenOCD server with only data
4613 that configures your JTAG interface, and arranges to come up
4614 with a slow clock (many devices don't support fast JTAG clocks
4615 right when they come out of reset).
4617 For example, your @file{openocd.cfg} file might have:
4620 source [find interface/olimex-arm-usb-tiny-h.cfg]
4621 reset_config trst_and_srst
4625 When you start the server without any TAPs configured, it will
4626 attempt to autoconfigure the TAPs. There are two parts to this:
4629 @item @emph{TAP discovery} ...
4630 After a JTAG reset (sometimes a system reset may be needed too),
4631 each TAP's data registers will hold the contents of either the
4632 IDCODE or BYPASS register.
4633 If JTAG communication is working, OpenOCD will see each TAP,
4634 and report what @option{-expected-id} to use with it.
4635 @item @emph{IR Length discovery} ...
4636 Unfortunately JTAG does not provide a reliable way to find out
4637 the value of the @option{-irlen} parameter to use with a TAP
4639 If OpenOCD can discover the length of a TAP's instruction
4640 register, it will report it.
4641 Otherwise you may need to consult vendor documentation, such
4642 as chip data sheets or BSDL files.
4645 In many cases your board will have a simple scan chain with just
4646 a single device. Here's what OpenOCD reported with one board
4647 that's a bit more complex:
4651 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4652 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4653 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4654 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4655 AUTO auto0.tap - use "... -irlen 4"
4656 AUTO auto1.tap - use "... -irlen 4"
4657 AUTO auto2.tap - use "... -irlen 6"
4658 no gdb ports allocated as no target has been specified
4661 Given that information, you should be able to either find some existing
4662 config files to use, or create your own. If you create your own, you
4663 would configure from the bottom up: first a @file{target.cfg} file
4664 with these TAPs, any targets associated with them, and any on-chip
4665 resources; then a @file{board.cfg} with off-chip resources, clocking,
4668 @anchor{dapdeclaration}
4669 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4670 @cindex DAP declaration
4672 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4673 no longer implicitly created together with the target. It must be
4674 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4675 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4676 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4678 The @command{dap} command group supports the following sub-commands:
4681 @deffn {Command} {dap create} dap_name @option{-chain-position} dotted.name configparams...
4682 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4683 @var{dotted.name}. This also creates a new command (@command{dap_name})
4684 which is used for various purposes including additional configuration.
4685 There can only be one DAP for each JTAG tap in the system.
4687 A DAP may also provide optional @var{configparams}:
4691 Specify that it's an ADIv5 DAP. This is the default if not specified.
4693 Specify that it's an ADIv6 DAP.
4694 @item @code{-ignore-syspwrupack}
4695 Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4696 register during initial examination and when checking the sticky error bit.
4697 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4698 devices do not set the ack bit until sometime later.
4700 @item @code{-dp-id} @var{number}
4701 @*Debug port identification number for SWD DPv2 multidrop.
4702 The @var{number} is written to bits 0..27 of DP TARGETSEL during DP selection.
4703 To find the id number of a single connected device read DP TARGETID:
4704 @code{device.dap dpreg 0x24}
4705 Use bits 0..27 of TARGETID.
4707 @item @code{-instance-id} @var{number}
4708 @*Instance identification number for SWD DPv2 multidrop.
4709 The @var{number} is written to bits 28..31 of DP TARGETSEL during DP selection.
4710 To find the instance number of a single connected device read DP DLPIDR:
4711 @code{device.dap dpreg 0x34}
4712 The instance number is in bits 28..31 of DLPIDR value.
4716 @deffn {Command} {dap names}
4717 This command returns a list of all registered DAP objects. It it useful mainly
4721 @deffn {Command} {dap info} [@var{num}|@option{root}]
4722 Displays the ROM table for MEM-AP @var{num},
4723 defaulting to the currently selected AP of the currently selected target.
4724 On ADIv5 DAP @var{num} is the numeric index of the AP.
4725 On ADIv6 DAP @var{num} is the base address of the AP.
4726 With ADIv6 only, @option{root} specifies the root ROM table.
4729 @deffn {Command} {dap init}
4730 Initialize all registered DAPs. This command is used internally
4731 during initialization. It can be issued at any time after the
4732 initialization, too.
4735 The following commands exist as subcommands of DAP instances:
4737 @deffn {Command} {$dap_name info} [@var{num}|@option{root}]
4738 Displays the ROM table for MEM-AP @var{num},
4739 defaulting to the currently selected AP.
4740 On ADIv5 DAP @var{num} is the numeric index of the AP.
4741 On ADIv6 DAP @var{num} is the base address of the AP.
4742 With ADIv6 only, @option{root} specifies the root ROM table.
4745 @deffn {Command} {$dap_name apid} [num]
4746 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4747 On ADIv5 DAP @var{num} is the numeric index of the AP.
4748 On ADIv6 DAP @var{num} is the base address of the AP.
4751 @anchor{DAP subcommand apreg}
4752 @deffn {Command} {$dap_name apreg} ap_num reg [value]
4753 Displays content of a register @var{reg} from AP @var{ap_num}
4754 or set a new value @var{value}.
4755 On ADIv5 DAP @var{ap_num} is the numeric index of the AP.
4756 On ADIv6 DAP @var{ap_num} is the base address of the AP.
4757 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4760 @deffn {Command} {$dap_name apsel} [num]
4761 Select AP @var{num}, defaulting to 0.
4762 On ADIv5 DAP @var{num} is the numeric index of the AP.
4763 On ADIv6 DAP @var{num} is the base address of the AP.
4766 @deffn {Command} {$dap_name dpreg} reg [value]
4767 Displays the content of DP register at address @var{reg}, or set it to a new
4770 In case of SWD, @var{reg} is a value in packed format
4771 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4772 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4774 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4775 background activity by OpenOCD while you are operating at such low-level.
4778 @deffn {Command} {$dap_name baseaddr} [num]
4779 Displays debug base address from MEM-AP @var{num},
4780 defaulting to the currently selected AP.
4781 On ADIv5 DAP @var{num} is the numeric index of the AP.
4782 On ADIv6 DAP @var{num} is the base address of the AP.
4785 @deffn {Command} {$dap_name memaccess} [value]
4786 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4787 memory bus access [0-255], giving additional time to respond to reads.
4788 If @var{value} is defined, first assigns that.
4791 @deffn {Command} {$dap_name apcsw} [value [mask]]
4792 Displays or changes CSW bit pattern for MEM-AP transfers.
4794 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4795 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4796 and the result is written to the real CSW register. All bits except dynamically
4797 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4798 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4801 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4802 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4805 kx.dap apcsw 0x2000000
4808 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4809 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4810 and leaves the rest of the pattern intact. It configures memory access through
4811 DCache on Cortex-M7.
4813 set CSW_HPROT3_CACHEABLE [expr @{1 << 27@}]
4814 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4817 Another example clears SPROT bit and leaves the rest of pattern intact:
4819 set CSW_SPROT [expr @{1 << 30@}]
4820 samv.dap apcsw 0 $CSW_SPROT
4823 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4824 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4826 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4827 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4828 example with a proper dap name:
4830 xxx.dap apcsw default
4834 @deffn {Config Command} {$dap_name ti_be_32_quirks} [@option{enable}]
4835 Set/get quirks mode for TI TMS450/TMS570 processors
4840 @node CPU Configuration
4841 @chapter CPU Configuration
4844 This chapter discusses how to set up GDB debug targets for CPUs.
4845 You can also access these targets without GDB
4846 (@pxref{Architecture and Core Commands},
4847 and @ref{targetstatehandling,,Target State handling}) and
4848 through various kinds of NAND and NOR flash commands.
4849 If you have multiple CPUs you can have multiple such targets.
4851 We'll start by looking at how to examine the targets you have,
4852 then look at how to add one more target and how to configure it.
4854 @section Target List
4855 @cindex target, current
4856 @cindex target, list
4858 All targets that have been set up are part of a list,
4859 where each member has a name.
4860 That name should normally be the same as the TAP name.
4861 You can display the list with the @command{targets}
4863 This display often has only one CPU; here's what it might
4864 look like with more than one:
4866 TargetName Type Endian TapName State
4867 -- ------------------ ---------- ------ ------------------ ------------
4868 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4869 1 MyTarget cortex_m little mychip.foo tap-disabled
4872 One member of that list is the @dfn{current target}, which
4873 is implicitly referenced by many commands.
4874 It's the one marked with a @code{*} near the target name.
4875 In particular, memory addresses often refer to the address
4876 space seen by that current target.
4877 Commands like @command{mdw} (memory display words)
4878 and @command{flash erase_address} (erase NOR flash blocks)
4879 are examples; and there are many more.
4881 Several commands let you examine the list of targets:
4883 @deffn {Command} {target current}
4884 Returns the name of the current target.
4887 @deffn {Command} {target names}
4888 Lists the names of all current targets in the list.
4890 foreach t [target names] @{
4891 puts [format "Target: %s\n" $t]
4896 @c yep, "target list" would have been better.
4897 @c plus maybe "target setdefault".
4899 @deffn {Command} {targets} [name]
4900 @emph{Note: the name of this command is plural. Other target
4901 command names are singular.}
4903 With no parameter, this command displays a table of all known
4904 targets in a user friendly form.
4906 With a parameter, this command sets the current target to
4907 the given target with the given @var{name}; this is
4908 only relevant on boards which have more than one target.
4911 @section Target CPU Types
4915 Each target has a @dfn{CPU type}, as shown in the output of
4916 the @command{targets} command. You need to specify that type
4917 when calling @command{target create}.
4918 The CPU type indicates more than just the instruction set.
4919 It also indicates how that instruction set is implemented,
4920 what kind of debug support it integrates,
4921 whether it has an MMU (and if so, what kind),
4922 what core-specific commands may be available
4923 (@pxref{Architecture and Core Commands}),
4926 It's easy to see what target types are supported,
4927 since there's a command to list them.
4929 @anchor{targettypes}
4930 @deffn {Command} {target types}
4931 Lists all supported target types.
4932 At this writing, the supported CPU types are:
4935 @item @code{aarch64} -- this is an ARMv8-A core with an MMU.
4936 @item @code{arm11} -- this is a generation of ARMv6 cores.
4937 @item @code{arm720t} -- this is an ARMv4 core with an MMU.
4938 @item @code{arm7tdmi} -- this is an ARMv4 core.
4939 @item @code{arm920t} -- this is an ARMv4 core with an MMU.
4940 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU.
4941 @item @code{arm946e} -- this is an ARMv5 core with an MMU.
4942 @item @code{arm966e} -- this is an ARMv5 core.
4943 @item @code{arm9tdmi} -- this is an ARMv4 core.
4944 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4945 (Support for this is preliminary and incomplete.)
4946 @item @code{avr32_ap7k} -- this an AVR32 core.
4947 @item @code{cortex_a} -- this is an ARMv7-A core with an MMU.
4948 @item @code{cortex_m} -- this is an ARMv7-M core, supporting only the
4949 compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
4950 @item @code{cortex_r4} -- this is an ARMv7-R core.
4951 @item @code{dragonite} -- resembles arm966e.
4952 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4953 (Support for this is still incomplete.)
4954 @item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
4955 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4956 The current implementation supports eSi-32xx cores.
4957 @item @code{esp32} -- this is an Espressif SoC with dual Xtensa cores.
4958 @item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core.
4959 @item @code{esp32s3} -- this is an Espressif SoC with dual Xtensa cores.
4960 @item @code{fa526} -- resembles arm920 (w/o Thumb).
4961 @item @code{feroceon} -- resembles arm926.
4962 @item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
4963 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4964 allowing access to physical memory addresses independently of CPU cores.
4965 @item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without
4966 a CPU, through which bus read and write cycles can be generated; it may be
4967 useful for working with non-CPU hardware behind an AP or during development of
4968 support for new CPUs.
4969 It's possible to connect a GDB client to this target (the GDB port has to be
4970 specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will
4971 be emulated to comply to GDB remote protocol.
4972 @item @code{mips_m4k} -- a MIPS core.
4973 @item @code{mips_mips64} -- a MIPS64 core.
4974 @item @code{nds32_v2} -- this is an Andes NDS32 v2 core (deprecated; would be removed in v0.13.0).
4975 @item @code{nds32_v3} -- this is an Andes NDS32 v3 core (deprecated; would be removed in v0.13.0).
4976 @item @code{nds32_v3m} -- this is an Andes NDS32 v3m core (deprecated; would be removed in v0.13.0).
4977 @item @code{or1k} -- this is an OpenRISC 1000 core.
4978 The current implementation supports three JTAG TAP cores:
4980 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag})
4981 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4982 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4984 And two debug interfaces cores:
4986 @item @code{Advanced debug interface}
4987 @*(See: @url{http://opencores.org/project@comma{}adv_debug_sys})
4988 @item @code{SoC Debug Interface}
4989 @*(See: @url{http://opencores.org/project@comma{}dbg_interface})
4991 @item @code{quark_d20xx} -- an Intel Quark D20xx core.
4992 @item @code{quark_x10xx} -- an Intel Quark X10xx core.
4993 @item @code{riscv} -- a RISC-V core.
4994 @item @code{stm8} -- implements an STM8 core.
4995 @item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
4996 @item @code{xscale} -- this is actually an architecture,
4997 not a CPU type. It is based on the ARMv5 architecture.
5001 To avoid being confused by the variety of ARM based cores, remember
5002 this key point: @emph{ARM is a technology licencing company}.
5003 (See: @url{http://www.arm.com}.)
5004 The CPU name used by OpenOCD will reflect the CPU design that was
5005 licensed, not a vendor brand which incorporates that design.
5006 Name prefixes like arm7, arm9, arm11, and cortex
5007 reflect design generations;
5008 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
5009 reflect an architecture version implemented by a CPU design.
5011 @anchor{targetconfiguration}
5012 @section Target Configuration
5014 Before creating a ``target'', you must have added its TAP to the scan chain.
5015 When you've added that TAP, you will have a @code{dotted.name}
5016 which is used to set up the CPU support.
5017 The chip-specific configuration file will normally configure its CPU(s)
5018 right after it adds all of the chip's TAPs to the scan chain.
5020 Although you can set up a target in one step, it's often clearer if you
5021 use shorter commands and do it in two steps: create it, then configure
5023 All operations on the target after it's created will use a new
5024 command, created as part of target creation.
5026 The two main things to configure after target creation are
5027 a work area, which usually has target-specific defaults even
5028 if the board setup code overrides them later;
5029 and event handlers (@pxref{targetevents,,Target Events}), which tend
5030 to be much more board-specific.
5031 The key steps you use might look something like this
5034 dap create mychip.dap -chain-position mychip.cpu
5035 target create MyTarget cortex_m -dap mychip.dap
5036 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
5037 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
5038 MyTarget configure -event reset-init @{ myboard_reinit @}
5041 You should specify a working area if you can; typically it uses some
5043 Such a working area can speed up many things, including bulk
5044 writes to target memory;
5045 flash operations like checking to see if memory needs to be erased;
5046 GDB memory checksumming;
5050 On more complex chips, the work area can become
5051 inaccessible when application code
5052 (such as an operating system)
5053 enables or disables the MMU.
5054 For example, the particular MMU context used to access the virtual
5055 address will probably matter ... and that context might not have
5056 easy access to other addresses needed.
5057 At this writing, OpenOCD doesn't have much MMU intelligence.
5060 It's often very useful to define a @code{reset-init} event handler.
5061 For systems that are normally used with a boot loader,
5062 common tasks include updating clocks and initializing memory
5064 That may be needed to let you write the boot loader into flash,
5065 in order to ``de-brick'' your board; or to load programs into
5066 external DDR memory without having run the boot loader.
5068 @deffn {Config Command} {target create} target_name type configparams...
5069 This command creates a GDB debug target that refers to a specific JTAG tap.
5070 It enters that target into a list, and creates a new
5071 command (@command{@var{target_name}}) which is used for various
5072 purposes including additional configuration.
5075 @item @var{target_name} ... is the name of the debug target.
5076 By convention this should be the same as the @emph{dotted.name}
5077 of the TAP associated with this target, which must be specified here
5078 using the @code{-chain-position @var{dotted.name}} configparam.
5080 This name is also used to create the target object command,
5081 referred to here as @command{$target_name},
5082 and in other places the target needs to be identified.
5083 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
5084 @item @var{configparams} ... all parameters accepted by
5085 @command{$target_name configure} are permitted.
5086 If the target is big-endian, set it here with @code{-endian big}.
5088 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
5089 @code{-dap @var{dap_name}} here.
5093 @deffn {Command} {$target_name configure} configparams...
5094 The options accepted by this command may also be
5095 specified as parameters to @command{target create}.
5096 Their values can later be queried one at a time by
5097 using the @command{$target_name cget} command.
5099 @emph{Warning:} changing some of these after setup is dangerous.
5100 For example, moving a target from one TAP to another;
5101 and changing its endianness.
5105 @item @code{-chain-position} @var{dotted.name} -- names the TAP
5106 used to access this target.
5108 @item @code{-dap} @var{dap_name} -- names the DAP used to access
5109 this target. @xref{dapdeclaration,,DAP declaration}, on how to
5110 create and manage DAP instances.
5112 @item @code{-endian} (@option{big}|@option{little}) -- specifies
5113 whether the CPU uses big or little endian conventions
5115 @item @code{-event} @var{event_name} @var{event_body} --
5116 @xref{targetevents,,Target Events}.
5117 Note that this updates a list of named event handlers.
5118 Calling this twice with two different event names assigns
5119 two different handlers, but calling it twice with the
5120 same event name assigns only one handler.
5122 Current target is temporarily overridden to the event issuing target
5123 before handler code starts and switched back after handler is done.
5125 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
5126 whether the work area gets backed up; by default,
5127 @emph{it is not backed up.}
5128 When possible, use a working_area that doesn't need to be backed up,
5129 since performing a backup slows down operations.
5130 For example, the beginning of an SRAM block is likely to
5131 be used by most build systems, but the end is often unused.
5133 @item @code{-work-area-size} @var{size} -- specify work are size,
5134 in bytes. The same size applies regardless of whether its physical
5135 or virtual address is being used.
5137 @item @code{-work-area-phys} @var{address} -- set the work area
5138 base @var{address} to be used when no MMU is active.
5140 @item @code{-work-area-virt} @var{address} -- set the work area
5141 base @var{address} to be used when an MMU is active.
5142 @emph{Do not specify a value for this except on targets with an MMU.}
5143 The value should normally correspond to a static mapping for the
5144 @code{-work-area-phys} address, set up by the current operating system.
5147 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
5148 @var{rtos_type} can be one of @option{auto}, @option{eCos},
5149 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
5150 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx},
5151 @option{RIOT}, @option{Zephyr}
5152 @xref{gdbrtossupport,,RTOS Support}.
5154 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
5155 scan and after a reset. A manual call to arp_examine is required to
5156 access the target for debugging.
5158 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target.
5159 On ADIv5 DAP @var{ap_number} is the numeric index of the DAP AP the target is connected to.
5160 On ADIv6 DAP @var{ap_number} is the base address of the DAP AP the target is connected to.
5161 Use this option with systems where multiple, independent cores are connected
5162 to separate access ports of the same DAP.
5164 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
5165 to the target. Currently, only the @code{aarch64} target makes use of this option,
5166 where it is a mandatory configuration for the target run control.
5167 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
5168 for instruction on how to declare and control a CTI instance.
5170 @anchor{gdbportoverride}
5171 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
5172 possible values of the parameter @var{number}, which are not only numeric values.
5173 Use this option to override, for this target only, the global parameter set with
5174 command @command{gdb_port}.
5175 @xref{gdb_port,,command gdb_port}.
5177 @item @code{-gdb-max-connections} @var{number} -- EXPERIMENTAL: set the maximum
5178 number of GDB connections that are allowed for the target. Default is 1.
5179 A negative value for @var{number} means unlimited connections.
5180 See @xref{gdbmeminspect,,Using GDB as a non-intrusive memory inspector}.
5184 @section Other $target_name Commands
5185 @cindex object command
5187 The Tcl/Tk language has the concept of object commands,
5188 and OpenOCD adopts that same model for targets.
5190 A good Tk example is a on screen button.
5191 Once a button is created a button
5192 has a name (a path in Tk terms) and that name is useable as a first
5193 class command. For example in Tk, one can create a button and later
5194 configure it like this:
5198 button .foobar -background red -command @{ foo @}
5200 .foobar configure -foreground blue
5202 set x [.foobar cget -background]
5204 puts [format "The button is %s" $x]
5207 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
5208 button, and its object commands are invoked the same way.
5211 str912.cpu mww 0x1234 0x42
5212 omap3530.cpu mww 0x5555 123
5215 The commands supported by OpenOCD target objects are:
5217 @deffn {Command} {$target_name arp_examine} @option{allow-defer}
5218 @deffnx {Command} {$target_name arp_halt}
5219 @deffnx {Command} {$target_name arp_poll}
5220 @deffnx {Command} {$target_name arp_reset}
5221 @deffnx {Command} {$target_name arp_waitstate}
5222 Internal OpenOCD scripts (most notably @file{startup.tcl})
5223 use these to deal with specific reset cases.
5224 They are not otherwise documented here.
5227 @deffn {Command} {$target_name set_reg} dict
5228 Set register values of the target.
5231 @item @var{dict} ... Tcl dictionary with pairs of register names and values.
5234 For example, the following command sets the value 0 to the program counter (pc)
5235 register and 0x1000 to the stack pointer (sp) register:
5238 set_reg @{pc 0 sp 0x1000@}
5242 @deffn {Command} {$target_name get_reg} [-force] list
5243 Get register values from the target and return them as Tcl dictionary with pairs
5244 of register names and values.
5245 If option "-force" is set, the register values are read directly from the
5246 target, bypassing any caching.
5249 @item @var{list} ... List of register names
5252 For example, the following command retrieves the values from the program
5253 counter (pc) and stack pointer (sp) register:
5260 @deffn {Command} {$target_name write_memory} address width data ['phys']
5261 This function provides an efficient way to write to the target memory from a Tcl
5265 @item @var{address} ... target memory address
5266 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
5267 @item @var{data} ... Tcl list with the elements to write
5268 @item ['phys'] ... treat the memory address as physical instead of virtual address
5271 For example, the following command writes two 32 bit words into the target
5272 memory at address 0x20000000:
5275 write_memory 0x20000000 32 @{0xdeadbeef 0x00230500@}
5279 @deffn {Command} {$target_name read_memory} address width count ['phys']
5280 This function provides an efficient way to read the target memory from a Tcl
5282 A Tcl list containing the requested memory elements is returned by this function.
5285 @item @var{address} ... target memory address
5286 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
5287 @item @var{count} ... number of elements to read
5288 @item ['phys'] ... treat the memory address as physical instead of virtual address
5291 For example, the following command reads two 32 bit words from the target
5292 memory at address 0x20000000:
5295 read_memory 0x20000000 32 2
5299 @deffn {Command} {$target_name cget} queryparm
5300 Each configuration parameter accepted by
5301 @command{$target_name configure}
5302 can be individually queried, to return its current value.
5303 The @var{queryparm} is a parameter name
5304 accepted by that command, such as @code{-work-area-phys}.
5305 There are a few special cases:
5308 @item @code{-event} @var{event_name} -- returns the handler for the
5309 event named @var{event_name}.
5310 This is a special case because setting a handler requires
5312 @item @code{-type} -- returns the target type.
5313 This is a special case because this is set using
5314 @command{target create} and can't be changed
5315 using @command{$target_name configure}.
5318 For example, if you wanted to summarize information about
5319 all the targets you might use something like this:
5322 foreach name [target names] @{
5323 set y [$name cget -endian]
5324 set z [$name cget -type]
5325 puts [format "Chip %d is %s, Endian: %s, type: %s" \
5331 @anchor{targetcurstate}
5332 @deffn {Command} {$target_name curstate}
5333 Displays the current target state:
5334 @code{debug-running},
5337 @code{running}, or @code{unknown}.
5338 (Also, @pxref{eventpolling,,Event Polling}.)
5341 @deffn {Command} {$target_name eventlist}
5342 Displays a table listing all event handlers
5343 currently associated with this target.
5344 @xref{targetevents,,Target Events}.
5347 @deffn {Command} {$target_name invoke-event} event_name
5348 Invokes the handler for the event named @var{event_name}.
5349 (This is primarily intended for use by OpenOCD framework
5350 code, for example by the reset code in @file{startup.tcl}.)
5353 @deffn {Command} {$target_name mdd} [phys] addr [count]
5354 @deffnx {Command} {$target_name mdw} [phys] addr [count]
5355 @deffnx {Command} {$target_name mdh} [phys] addr [count]
5356 @deffnx {Command} {$target_name mdb} [phys] addr [count]
5357 Display contents of address @var{addr}, as
5358 64-bit doublewords (@command{mdd}),
5359 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5360 or 8-bit bytes (@command{mdb}).
5361 When the current target has an MMU which is present and active,
5362 @var{addr} is interpreted as a virtual address.
5363 Otherwise, or if the optional @var{phys} flag is specified,
5364 @var{addr} is interpreted as a physical address.
5365 If @var{count} is specified, displays that many units.
5366 (If you want to process the data instead of displaying it,
5367 see the @code{read_memory} primitives.)
5370 @deffn {Command} {$target_name mwd} [phys] addr doubleword [count]
5371 @deffnx {Command} {$target_name mww} [phys] addr word [count]
5372 @deffnx {Command} {$target_name mwh} [phys] addr halfword [count]
5373 @deffnx {Command} {$target_name mwb} [phys] addr byte [count]
5374 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
5375 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
5376 at the specified address @var{addr}.
5377 When the current target has an MMU which is present and active,
5378 @var{addr} is interpreted as a virtual address.
5379 Otherwise, or if the optional @var{phys} flag is specified,
5380 @var{addr} is interpreted as a physical address.
5381 If @var{count} is specified, fills that many units of consecutive address.
5384 @anchor{targetevents}
5385 @section Target Events
5386 @cindex target events
5388 At various times, certain things can happen, or you want them to happen.
5391 @item What should happen when GDB connects? Should your target reset?
5392 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
5393 @item Is using SRST appropriate (and possible) on your system?
5394 Or instead of that, do you need to issue JTAG commands to trigger reset?
5395 SRST usually resets everything on the scan chain, which can be inappropriate.
5396 @item During reset, do you need to write to certain memory locations
5397 to set up system clocks or
5398 to reconfigure the SDRAM?
5399 How about configuring the watchdog timer, or other peripherals,
5400 to stop running while you hold the core stopped for debugging?
5403 All of the above items can be addressed by target event handlers.
5404 These are set up by @command{$target_name configure -event} or
5405 @command{target create ... -event}.
5407 The programmer's model matches the @code{-command} option used in Tcl/Tk
5408 buttons and events. The two examples below act the same, but one creates
5409 and invokes a small procedure while the other inlines it.
5412 proc my_init_proc @{ @} @{
5413 echo "Disabling watchdog..."
5414 mww 0xfffffd44 0x00008000
5416 mychip.cpu configure -event reset-init my_init_proc
5417 mychip.cpu configure -event reset-init @{
5418 echo "Disabling watchdog..."
5419 mww 0xfffffd44 0x00008000
5423 The following target events are defined:
5426 @item @b{debug-halted}
5427 @* The target has halted for debug reasons (i.e.: breakpoint)
5428 @item @b{debug-resumed}
5429 @* The target has resumed (i.e.: GDB said run)
5430 @item @b{early-halted}
5431 @* Occurs early in the halt process
5432 @item @b{examine-start}
5433 @* Before target examine is called.
5434 @item @b{examine-end}
5435 @* After target examine is called with no errors.
5436 @item @b{examine-fail}
5437 @* After target examine fails.
5438 @item @b{gdb-attach}
5439 @* When GDB connects. Issued before any GDB communication with the target
5440 starts. GDB expects the target is halted during attachment.
5441 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
5442 connect GDB to running target.
5443 The event can be also used to set up the target so it is possible to probe flash.
5444 Probing flash is necessary during GDB connect if you want to use
5445 @pxref{programmingusinggdb,,programming using GDB}.
5446 Another use of the flash memory map is for GDB to automatically choose
5447 hardware or software breakpoints depending on whether the breakpoint
5448 is in RAM or read only memory.
5449 Default is @code{halt}
5450 @item @b{gdb-detach}
5451 @* When GDB disconnects
5453 @* When the target has halted and GDB is not doing anything (see early halt)
5454 @item @b{gdb-flash-erase-start}
5455 @* Before the GDB flash process tries to erase the flash (default is
5457 @item @b{gdb-flash-erase-end}
5458 @* After the GDB flash process has finished erasing the flash
5459 @item @b{gdb-flash-write-start}
5460 @* Before GDB writes to the flash
5461 @item @b{gdb-flash-write-end}
5462 @* After GDB writes to the flash (default is @code{reset halt})
5464 @* Before the target steps, GDB is trying to start/resume the target
5466 @* The target has halted
5467 @item @b{reset-assert-pre}
5468 @* Issued as part of @command{reset} processing
5469 after @command{reset-start} was triggered
5470 but before either SRST alone is asserted on the scan chain,
5471 or @code{reset-assert} is triggered.
5472 @item @b{reset-assert}
5473 @* Issued as part of @command{reset} processing
5474 after @command{reset-assert-pre} was triggered.
5475 When such a handler is present, cores which support this event will use
5476 it instead of asserting SRST.
5477 This support is essential for debugging with JTAG interfaces which
5478 don't include an SRST line (JTAG doesn't require SRST), and for
5479 selective reset on scan chains that have multiple targets.
5480 @item @b{reset-assert-post}
5481 @* Issued as part of @command{reset} processing
5482 after @code{reset-assert} has been triggered.
5483 or the target asserted SRST on the entire scan chain.
5484 @item @b{reset-deassert-pre}
5485 @* Issued as part of @command{reset} processing
5486 after @code{reset-assert-post} has been triggered.
5487 @item @b{reset-deassert-post}
5488 @* Issued as part of @command{reset} processing
5489 after @code{reset-deassert-pre} has been triggered
5490 and (if the target is using it) after SRST has been
5491 released on the scan chain.
5493 @* Issued as the final step in @command{reset} processing.
5494 @item @b{reset-init}
5495 @* Used by @b{reset init} command for board-specific initialization.
5496 This event fires after @emph{reset-deassert-post}.
5498 This is where you would configure PLLs and clocking, set up DRAM so
5499 you can download programs that don't fit in on-chip SRAM, set up pin
5500 multiplexing, and so on.
5501 (You may be able to switch to a fast JTAG clock rate here, after
5502 the target clocks are fully set up.)
5503 @item @b{reset-start}
5504 @* Issued as the first step in @command{reset} processing
5505 before @command{reset-assert-pre} is called.
5507 This is the most robust place to use @command{jtag_rclk}
5508 or @command{adapter speed} to switch to a low JTAG clock rate,
5509 when reset disables PLLs needed to use a fast clock.
5510 @item @b{resume-start}
5511 @* Before any target is resumed
5512 @item @b{resume-end}
5513 @* After all targets have resumed
5515 @* Target has resumed
5516 @item @b{step-start}
5517 @* Before a target is single-stepped
5519 @* After single-step has completed
5520 @item @b{trace-config}
5521 @* After target hardware trace configuration was changed
5522 @item @b{semihosting-user-cmd-0x100}
5523 @* The target made a semihosting call with user-defined operation number 0x100
5524 @item @b{semihosting-user-cmd-0x101}
5525 @* The target made a semihosting call with user-defined operation number 0x101
5526 @item @b{semihosting-user-cmd-0x102}
5527 @* The target made a semihosting call with user-defined operation number 0x102
5528 @item @b{semihosting-user-cmd-0x103}
5529 @* The target made a semihosting call with user-defined operation number 0x103
5530 @item @b{semihosting-user-cmd-0x104}
5531 @* The target made a semihosting call with user-defined operation number 0x104
5532 @item @b{semihosting-user-cmd-0x105}
5533 @* The target made a semihosting call with user-defined operation number 0x105
5534 @item @b{semihosting-user-cmd-0x106}
5535 @* The target made a semihosting call with user-defined operation number 0x106
5536 @item @b{semihosting-user-cmd-0x107}
5537 @* The target made a semihosting call with user-defined operation number 0x107
5541 OpenOCD events are not supposed to be preempt by another event, but this
5542 is not enforced in current code. Only the target event @b{resumed} is
5543 executed with polling disabled; this avoids polling to trigger the event
5544 @b{halted}, reversing the logical order of execution of their handlers.
5545 Future versions of OpenOCD will prevent the event preemption and will
5546 disable the schedule of polling during the event execution. Do not rely
5547 on polling in any event handler; this means, don't expect the status of
5548 a core to change during the execution of the handler. The event handler
5549 will have to enable polling or use @command{$target_name arp_poll} to
5550 check if the core has changed status.
5553 @node Flash Commands
5554 @chapter Flash Commands
5556 OpenOCD has different commands for NOR and NAND flash;
5557 the ``flash'' command works with NOR flash, while
5558 the ``nand'' command works with NAND flash.
5559 This partially reflects different hardware technologies:
5560 NOR flash usually supports direct CPU instruction and data bus access,
5561 while data from a NAND flash must be copied to memory before it can be
5562 used. (SPI flash must also be copied to memory before use.)
5563 However, the documentation also uses ``flash'' as a generic term;
5564 for example, ``Put flash configuration in board-specific files''.
5568 @item Configure via the command @command{flash bank}
5569 @* Do this in a board-specific configuration file,
5570 passing parameters as needed by the driver.
5571 @item Operate on the flash via @command{flash subcommand}
5572 @* Often commands to manipulate the flash are typed by a human, or run
5573 via a script in some automated way. Common tasks include writing a
5574 boot loader, operating system, or other data.
5576 @* Flashing via GDB requires the flash be configured via ``flash
5577 bank'', and the GDB flash features be enabled.
5578 @xref{gdbconfiguration,,GDB Configuration}.
5581 Many CPUs have the ability to ``boot'' from the first flash bank.
5582 This means that misprogramming that bank can ``brick'' a system,
5583 so that it can't boot.
5584 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
5585 board by (re)installing working boot firmware.
5587 @anchor{norconfiguration}
5588 @section Flash Configuration Commands
5589 @cindex flash configuration
5591 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
5592 Configures a flash bank which provides persistent storage
5593 for addresses from @math{base} to @math{base + size - 1}.
5594 These banks will often be visible to GDB through the target's memory map.
5595 In some cases, configuring a flash bank will activate extra commands;
5596 see the driver-specific documentation.
5599 @item @var{name} ... may be used to reference the flash bank
5600 in other flash commands. A number is also available.
5601 @item @var{driver} ... identifies the controller driver
5602 associated with the flash bank being declared.
5603 This is usually @code{cfi} for external flash, or else
5604 the name of a microcontroller with embedded flash memory.
5605 @xref{flashdriverlist,,Flash Driver List}.
5606 @item @var{base} ... Base address of the flash chip.
5607 @item @var{size} ... Size of the chip, in bytes.
5608 For some drivers, this value is detected from the hardware.
5609 @item @var{chip_width} ... Width of the flash chip, in bytes;
5610 ignored for most microcontroller drivers.
5611 @item @var{bus_width} ... Width of the data bus used to access the
5612 chip, in bytes; ignored for most microcontroller drivers.
5613 @item @var{target} ... Names the target used to issue
5614 commands to the flash controller.
5615 @comment Actually, it's currently a controller-specific parameter...
5616 @item @var{driver_options} ... drivers may support, or require,
5617 additional parameters. See the driver-specific documentation
5618 for more information.
5621 This command is not available after OpenOCD initialization has completed.
5622 Use it in board specific configuration files, not interactively.
5626 @comment less confusing would be: "flash list" (like "nand list")
5627 @deffn {Command} {flash banks}
5628 Prints a one-line summary of each device that was
5629 declared using @command{flash bank}, numbered from zero.
5630 Note that this is the @emph{plural} form;
5631 the @emph{singular} form is a very different command.
5634 @deffn {Command} {flash list}
5635 Retrieves a list of associative arrays for each device that was
5636 declared using @command{flash bank}, numbered from zero.
5637 This returned list can be manipulated easily from within scripts.
5640 @deffn {Command} {flash probe} num
5641 Identify the flash, or validate the parameters of the configured flash. Operation
5642 depends on the flash type.
5643 The @var{num} parameter is a value shown by @command{flash banks}.
5644 Most flash commands will implicitly @emph{autoprobe} the bank;
5645 flash drivers can distinguish between probing and autoprobing,
5646 but most don't bother.
5649 @section Preparing a Target before Flash Programming
5651 The target device should be in well defined state before the flash programming
5654 @emph{Always issue} @command{reset init} before @ref{flashprogrammingcommands,,Flash Programming Commands}.
5655 Do not issue another @command{reset} or @command{reset halt} or @command{resume}
5656 until the programming session is finished.
5658 If you use @ref{programmingusinggdb,,Programming using GDB},
5659 the target is prepared automatically in the event gdb-flash-erase-start
5661 The jimtcl script @command{program} calls @command{reset init} explicitly.
5663 @section Erasing, Reading, Writing to Flash
5664 @cindex flash erasing
5665 @cindex flash reading
5666 @cindex flash writing
5667 @cindex flash programming
5668 @anchor{flashprogrammingcommands}
5670 One feature distinguishing NOR flash from NAND or serial flash technologies
5671 is that for read access, it acts exactly like any other addressable memory.
5672 This means you can use normal memory read commands like @command{mdw} or
5673 @command{dump_image} with it, with no special @command{flash} subcommands.
5674 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
5676 Write access works differently. Flash memory normally needs to be erased
5677 before it's written. Erasing a sector turns all of its bits to ones, and
5678 writing can turn ones into zeroes. This is why there are special commands
5679 for interactive erasing and writing, and why GDB needs to know which parts
5680 of the address space hold NOR flash memory.
5683 Most of these erase and write commands leverage the fact that NOR flash
5684 chips consume target address space. They implicitly refer to the current
5685 JTAG target, and map from an address in that target's address space
5686 back to a flash bank.
5687 @comment In May 2009, those mappings may fail if any bank associated
5688 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
5689 A few commands use abstract addressing based on bank and sector numbers,
5690 and don't depend on searching the current target and its address space.
5691 Avoid confusing the two command models.
5694 Some flash chips implement software protection against accidental writes,
5695 since such buggy writes could in some cases ``brick'' a system.
5696 For such systems, erasing and writing may require sector protection to be
5698 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
5699 and AT91SAM7 on-chip flash.
5700 @xref{flashprotect,,flash protect}.
5702 @deffn {Command} {flash erase_sector} num first last
5703 Erase sectors in bank @var{num}, starting at sector @var{first}
5704 up to and including @var{last}.
5705 Sector numbering starts at 0.
5706 Providing a @var{last} sector of @option{last}
5707 specifies "to the end of the flash bank".
5708 The @var{num} parameter is a value shown by @command{flash banks}.
5711 @deffn {Command} {flash erase_address} [@option{pad}] [@option{unlock}] address length
5712 Erase sectors starting at @var{address} for @var{length} bytes.
5713 Unless @option{pad} is specified, @math{address} must begin a
5714 flash sector, and @math{address + length - 1} must end a sector.
5715 Specifying @option{pad} erases extra data at the beginning and/or
5716 end of the specified region, as needed to erase only full sectors.
5717 The flash bank to use is inferred from the @var{address}, and
5718 the specified length must stay within that bank.
5719 As a special case, when @var{length} is zero and @var{address} is
5720 the start of the bank, the whole flash is erased.
5721 If @option{unlock} is specified, then the flash is unprotected
5722 before erase starts.
5725 @deffn {Command} {flash filld} address double-word length
5726 @deffnx {Command} {flash fillw} address word length
5727 @deffnx {Command} {flash fillh} address halfword length
5728 @deffnx {Command} {flash fillb} address byte length
5729 Fills flash memory with the specified @var{double-word} (64 bits), @var{word} (32 bits),
5730 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5731 starting at @var{address} and continuing
5732 for @var{length} units (word/halfword/byte).
5733 No erasure is done before writing; when needed, that must be done
5734 before issuing this command.
5735 Writes are done in blocks of up to 1024 bytes, and each write is
5736 verified by reading back the data and comparing it to what was written.
5737 The flash bank to use is inferred from the @var{address} of
5738 each block, and the specified length must stay within that bank.
5740 @comment no current checks for errors if fill blocks touch multiple banks!
5742 @deffn {Command} {flash mdw} addr [count]
5743 @deffnx {Command} {flash mdh} addr [count]
5744 @deffnx {Command} {flash mdb} addr [count]
5745 Display contents of address @var{addr}, as
5746 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5747 or 8-bit bytes (@command{mdb}).
5748 If @var{count} is specified, displays that many units.
5749 Reads from flash using the flash driver, therefore it enables reading
5750 from a bank not mapped in target address space.
5751 The flash bank to use is inferred from the @var{address} of
5752 each block, and the specified length must stay within that bank.
5755 @deffn {Command} {flash write_bank} num filename [offset]
5756 Write the binary @file{filename} to flash bank @var{num},
5757 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
5758 is omitted, start at the beginning of the flash bank.
5759 The @var{num} parameter is a value shown by @command{flash banks}.
5762 @deffn {Command} {flash read_bank} num filename [offset [length]]
5763 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
5764 and write the contents to the binary @file{filename}. If @var{offset} is
5765 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
5766 read the remaining bytes from the flash bank.
5767 The @var{num} parameter is a value shown by @command{flash banks}.
5770 @deffn {Command} {flash verify_bank} num filename [offset]
5771 Compare the contents of the binary file @var{filename} with the contents of the
5772 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
5773 start at the beginning of the flash bank. Fail if the contents do not match.
5774 The @var{num} parameter is a value shown by @command{flash banks}.
5777 @deffn {Command} {flash write_image} [erase] [unlock] filename [offset] [type]
5778 Write the image @file{filename} to the current target's flash bank(s).
5779 Only loadable sections from the image are written.
5780 A relocation @var{offset} may be specified, in which case it is added
5781 to the base address for each section in the image.
5782 The file [@var{type}] can be specified
5783 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
5784 @option{elf} (ELF file), @option{s19} (Motorola s19).
5785 @option{mem}, or @option{builder}.
5786 The relevant flash sectors will be erased prior to programming
5787 if the @option{erase} parameter is given. If @option{unlock} is
5788 provided, then the flash banks are unlocked before erase and
5789 program. The flash bank to use is inferred from the address of
5793 Be careful using the @option{erase} flag when the flash is holding
5794 data you want to preserve.
5795 Portions of the flash outside those described in the image's
5796 sections might be erased with no notice.
5799 When a section of the image being written does not fill out all the
5800 sectors it uses, the unwritten parts of those sectors are necessarily
5801 also erased, because sectors can't be partially erased.
5803 Data stored in sector "holes" between image sections are also affected.
5804 For example, "@command{flash write_image erase ...}" of an image with
5805 one byte at the beginning of a flash bank and one byte at the end
5806 erases the entire bank -- not just the two sectors being written.
5808 Also, when flash protection is important, you must re-apply it after
5809 it has been removed by the @option{unlock} flag.
5814 @deffn {Command} {flash verify_image} filename [offset] [type]
5815 Verify the image @file{filename} to the current target's flash bank(s).
5816 Parameters follow the description of 'flash write_image'.
5817 In contrast to the 'verify_image' command, for banks with specific
5818 verify method, that one is used instead of the usual target's read
5819 memory methods. This is necessary for flash banks not readable by
5820 ordinary memory reads.
5821 This command gives only an overall good/bad result for each bank, not
5822 addresses of individual failed bytes as it's intended only as quick
5823 check for successful programming.
5826 @section Other Flash commands
5827 @cindex flash protection
5829 @deffn {Command} {flash erase_check} num
5830 Check erase state of sectors in flash bank @var{num},
5831 and display that status.
5832 The @var{num} parameter is a value shown by @command{flash banks}.
5835 @deffn {Command} {flash info} num [sectors]
5836 Print info about flash bank @var{num}, a list of protection blocks
5837 and their status. Use @option{sectors} to show a list of sectors instead.
5839 The @var{num} parameter is a value shown by @command{flash banks}.
5840 This command will first query the hardware, it does not print cached
5841 and possibly stale information.
5844 @anchor{flashprotect}
5845 @deffn {Command} {flash protect} num first last (@option{on}|@option{off})
5846 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
5847 in flash bank @var{num}, starting at protection block @var{first}
5848 and continuing up to and including @var{last}.
5849 Providing a @var{last} block of @option{last}
5850 specifies "to the end of the flash bank".
5851 The @var{num} parameter is a value shown by @command{flash banks}.
5852 The protection block is usually identical to a flash sector.
5853 Some devices may utilize a protection block distinct from flash sector.
5854 See @command{flash info} for a list of protection blocks.
5857 @deffn {Command} {flash padded_value} num value
5858 Sets the default value used for padding any image sections, This should
5859 normally match the flash bank erased value. If not specified by this
5860 command or the flash driver then it defaults to 0xff.
5864 @deffn {Command} {program} filename [preverify] [verify] [reset] [exit] [offset]
5865 This is a helper script that simplifies using OpenOCD as a standalone
5866 programmer. The only required parameter is @option{filename}, the others are optional.
5867 @xref{Flash Programming}.
5870 @anchor{flashdriverlist}
5871 @section Flash Driver List
5872 As noted above, the @command{flash bank} command requires a driver name,
5873 and allows driver-specific options and behaviors.
5874 Some drivers also activate driver-specific commands.
5876 @deffn {Flash Driver} {virtual}
5877 This is a special driver that maps a previously defined bank to another
5878 address. All bank settings will be copied from the master physical bank.
5880 The @var{virtual} driver defines one mandatory parameters,
5883 @item @var{master_bank} The bank that this virtual address refers to.
5886 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5887 the flash bank defined at address 0x1fc00000. Any command executed on
5888 the virtual banks is actually performed on the physical banks.
5890 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5891 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5892 $_TARGETNAME $_FLASHNAME
5893 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5894 $_TARGETNAME $_FLASHNAME
5898 @subsection External Flash
5900 @deffn {Flash Driver} {cfi}
5901 @cindex Common Flash Interface
5903 The ``Common Flash Interface'' (CFI) is the main standard for
5904 external NOR flash chips, each of which connects to a
5905 specific external chip select on the CPU.
5906 Frequently the first such chip is used to boot the system.
5907 Your board's @code{reset-init} handler might need to
5908 configure additional chip selects using other commands (like: @command{mww} to
5909 configure a bus and its timings), or
5910 perhaps configure a GPIO pin that controls the ``write protect'' pin
5912 The CFI driver can use a target-specific working area to significantly
5915 The CFI driver can accept the following optional parameters, in any order:
5918 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
5919 like AM29LV010 and similar types.
5920 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
5921 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
5922 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
5923 swapped when writing data values (i.e. not CFI commands).
5926 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
5927 wide on a sixteen bit bus:
5930 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
5931 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
5934 To configure one bank of 32 MBytes
5935 built from two sixteen bit (two byte) wide parts wired in parallel
5936 to create a thirty-two bit (four byte) bus with doubled throughput:
5939 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
5942 @c "cfi part_id" disabled
5945 @deffn {Flash Driver} {jtagspi}
5946 @cindex Generic JTAG2SPI driver
5950 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
5951 SPI flash connected to them. To access this flash from the host, the device
5952 is first programmed with a special proxy bitstream that
5953 exposes the SPI flash on the device's JTAG interface. The flash can then be
5954 accessed through JTAG.
5956 Since signaling between JTAG and SPI is compatible, all that is required for
5957 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
5958 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
5959 a bitstream for several Xilinx FPGAs can be found in
5960 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
5961 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
5963 This flash bank driver requires a target on a JTAG tap and will access that
5964 tap directly. Since no support from the target is needed, the target can be a
5965 "testee" dummy. Since the target does not expose the flash memory
5966 mapping, target commands that would otherwise be expected to access the flash
5967 will not work. These include all @command{*_image} and
5968 @command{$target_name m*} commands as well as @command{program}. Equivalent
5969 functionality is available through the @command{flash write_bank},
5970 @command{flash read_bank}, and @command{flash verify_bank} commands.
5972 According to device size, 1- to 4-byte addresses are sent. However, some
5973 flash chips additionally have to be switched to 4-byte addresses by an extra
5977 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
5978 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
5979 @var{USER1} instruction.
5983 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
5984 set _XILINX_USER1 0x02
5985 flash bank $_FLASHNAME spi 0x0 0 0 0 \
5986 $_TARGETNAME $_XILINX_USER1
5989 @deffn Command {jtagspi set} bank_id name total_size page_size read_cmd unused pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
5990 Sets flash parameters: @var{name} human readable string, @var{total_size}
5991 size in bytes, @var{page_size} is write page size. @var{read_cmd} and @var{pprg_cmd}
5992 are commands for read and page program, respectively. @var{mass_erase_cmd},
5993 @var{sector_size} and @var{sector_erase_cmd} are optional.
5995 jtagspi set 0 w25q128 0x1000000 0x100 0x03 0 0x02 0xC7 0x10000 0xD8
5999 @deffn Command {jtagspi cmd} bank_id resp_num cmd_byte ...
6000 Sends command @var{cmd_byte} and at most 20 following bytes and reads
6001 @var{resp_num} bytes afterwards. E.g. for 'Enter 4-byte address mode'
6003 jtagspi cmd 0 0 0xB7
6007 @deffn Command {jtagspi always_4byte} bank_id [ on | off ]
6008 Some devices use 4-byte addresses for all commands except the legacy 0x03 read
6009 regardless of device size. This command controls the corresponding hack.
6013 @deffn {Flash Driver} {xcf}
6014 @cindex Xilinx Platform flash driver
6016 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
6017 It is (almost) regular NOR flash with erase sectors, program pages, etc. The
6018 only difference is special registers controlling its FPGA specific behavior.
6019 They must be properly configured for successful FPGA loading using
6020 additional @var{xcf} driver command:
6022 @deffn {Command} {xcf ccb} <bank_id>
6023 command accepts additional parameters:
6025 @item @var{external|internal} ... selects clock source.
6026 @item @var{serial|parallel} ... selects serial or parallel data bus mode.
6027 @item @var{slave|master} ... selects slave of master mode for flash device.
6028 @item @var{40|20} ... selects clock frequency in MHz for internal clock
6032 xcf ccb 0 external parallel slave 40
6034 All of them must be specified even if clock frequency is pointless
6035 in slave mode. If only bank id specified than command prints current
6036 CCB register value. Note: there is no need to write this register
6037 every time you erase/program data sectors because it stores in
6041 @deffn {Command} {xcf configure} <bank_id>
6042 Initiates FPGA loading procedure. Useful if your board has no "configure"
6049 Additional driver notes:
6051 @item Only single revision supported.
6052 @item Driver automatically detects need of bit reverse, but
6053 only "bin" (raw binary, do not confuse it with "bit") and "mcs"
6054 (Intel hex) file types supported.
6055 @item For additional info check xapp972.pdf and ug380.pdf.
6059 @deffn {Flash Driver} {lpcspifi}
6060 @cindex NXP SPI Flash Interface
6063 NXP's LPC43xx and LPC18xx families include a proprietary SPI
6064 Flash Interface (SPIFI) peripheral that can drive and provide
6065 memory mapped access to external SPI flash devices.
6067 The lpcspifi driver initializes this interface and provides
6068 program and erase functionality for these serial flash devices.
6069 Use of this driver @b{requires} a working area of at least 1kB
6070 to be configured on the target device; more than this will
6071 significantly reduce flash programming times.
6073 The setup command only requires the @var{base} parameter. All
6074 other parameters are ignored, and the flash size and layout
6075 are configured by the driver.
6078 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
6083 @deffn {Flash Driver} {stmsmi}
6084 @cindex STMicroelectronics Serial Memory Interface
6087 Some devices from STMicroelectronics (e.g. STR75x MCU family,
6088 SPEAr MPU family) include a proprietary
6089 ``Serial Memory Interface'' (SMI) controller able to drive external
6091 Depending on specific device and board configuration, up to 4 external
6092 flash devices can be connected.
6094 SMI makes the flash content directly accessible in the CPU address
6095 space; each external device is mapped in a memory bank.
6096 CPU can directly read data, execute code and boot from SMI banks.
6097 Normal OpenOCD commands like @command{mdw} can be used to display
6100 The setup command only requires the @var{base} parameter in order
6101 to identify the memory bank.
6102 All other parameters are ignored. Additional information, like
6103 flash size, are detected automatically.
6106 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
6111 @deffn {Flash Driver} {stmqspi}
6112 @cindex STMicroelectronics QuadSPI/OctoSPI Interface
6116 Some devices from STMicroelectronics include a proprietary ``QuadSPI Interface''
6117 (e.g. STM32F4, STM32F7, STM32L4) or ``OctoSPI Interface'' (e.g. STM32L4+)
6118 controller able to drive one or even two (dual mode) external SPI flash devices.
6119 The OctoSPI is a superset of QuadSPI, its presence is detected automatically.
6120 Currently only the regular command mode is supported, whereas the HyperFlash
6123 QuadSPI/OctoSPI makes the flash contents directly accessible in the CPU address
6124 space; in case of dual mode both devices must be of the same type and are
6125 mapped in the same memory bank (even and odd addresses interleaved).
6126 CPU can directly read data, execute code (but not boot) from QuadSPI bank.
6128 The 'flash bank' command only requires the @var{base} parameter and the extra
6129 parameter @var{io_base} in order to identify the memory bank. Both are fixed
6130 by hardware, see datasheet or RM. All other parameters are ignored.
6132 The controller must be initialized after each reset and properly configured
6133 for memory-mapped read operation for the particular flash chip(s), for the full
6134 list of available register settings cf. the controller's RM. This setup is quite
6135 board specific (that's why booting from this memory is not possible). The
6136 flash driver infers all parameters from current controller register values when
6137 'flash probe @var{bank_id}' is executed.
6139 Normal OpenOCD commands like @command{mdw} can be used to display the flash content,
6140 but only after proper controller initialization as described above. However,
6141 due to a silicon bug in some devices, attempting to access the very last word
6144 It is possible to use two (even different) flash chips alternatingly, if individual
6145 bank chip selects are available. For some package variants, this is not the case
6146 due to limited pin count. To switch from one to another, adjust FSEL bit accordingly
6147 and re-issue 'flash probe bank_id'. Note that the bank base address will @emph{not}
6148 change, so the address spaces of both devices will overlap. In dual flash mode
6149 both chips must be identical regarding size and most other properties.
6151 Block or sector protection internal to the flash chip is not handled by this
6152 driver at all, but can be dealt with manually by the 'cmd' command, see below.
6153 The sector protection via 'flash protect' command etc. is completely internal to
6154 openocd, intended only to prevent accidental erase or overwrite and it does not
6155 persist across openocd invocations.
6157 OpenOCD contains a hardcoded list of flash devices with their properties,
6158 these are auto-detected. If a device is not included in this list, SFDP discovery
6159 is attempted. If this fails or gives inappropriate results, manual setting is
6160 required (see 'set' command).
6163 flash bank $_FLASHNAME stmqspi 0x90000000 0 0 0 \
6164 $_TARGETNAME 0xA0001000
6165 flash bank $_FLASHNAME stmqspi 0x70000000 0 0 0 \
6166 $_TARGETNAME 0xA0001400
6169 There are three specific commands
6170 @deffn {Command} {stmqspi mass_erase} bank_id
6171 Clears sector protections and performs a mass erase. Works only if there is no
6172 chip specific write protection engaged.
6175 @deffn {Command} {stmqspi set} bank_id name total_size page_size read_cmd fread_cmd pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
6176 Set flash parameters: @var{name} human readable string, @var{total_size} size
6177 in bytes, @var{page_size} is write page size. @var{read_cmd}, @var{fread_cmd} and @var{pprg_cmd}
6178 are commands for reading and page programming. @var{fread_cmd} is used in DPI and QPI modes,
6179 @var{read_cmd} in normal SPI (single line) mode. @var{mass_erase_cmd}, @var{sector_size}
6180 and @var{sector_erase_cmd} are optional.
6182 This command is required if chip id is not hardcoded yet and e.g. for EEPROMs or FRAMs
6183 which don't support an id command.
6185 In dual mode parameters of both chips are set identically. The parameters refer to
6186 a single chip, so the whole bank gets twice the specified capacity etc.
6189 @deffn {Command} {stmqspi cmd} bank_id resp_num cmd_byte ...
6190 If @var{resp_num} is zero, sends command @var{cmd_byte} and following data
6191 bytes. In dual mode command byte is sent to @emph{both} chips but data bytes are
6192 sent @emph{alternatingly} to chip 1 and 2, first to flash 1, second to flash 2, etc.,
6193 i.e. the total number of bytes (including cmd_byte) must be odd.
6195 If @var{resp_num} is not zero, cmd and at most four following data bytes are
6196 sent, in dual mode @emph{simultaneously} to both chips. Then @var{resp_num} bytes
6197 are read interleaved from both chips starting with chip 1. In this case
6198 @var{resp_num} must be even.
6200 Note the hardware dictated subtle difference of those two cases in dual-flash mode.
6202 To check basic communication settings, issue
6204 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 1 0x05
6205 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 1 0x05
6207 for single flash mode or
6209 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 2 0x05
6210 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 2 0x05
6212 for dual flash mode. This should return the status register contents.
6214 In 8-line mode, @var{cmd_byte} is sent twice - first time as given, second time
6215 complemented. Additionally, in 8-line mode only, some commands (e.g. Read Status)
6216 need a dummy address, e.g.
6218 stmqspi cmd bank_id 1 0x05 0x00 0x00 0x00 0x00
6220 should return the status register contents.
6226 @deffn {Flash Driver} {mrvlqspi}
6227 This driver supports QSPI flash controller of Marvell's Wireless
6228 Microcontroller platform.
6230 The flash size is autodetected based on the table of known JEDEC IDs
6231 hardcoded in the OpenOCD sources.
6234 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
6239 @deffn {Flash Driver} {ath79}
6240 @cindex Atheros ath79 SPI driver
6242 Members of ATH79 SoC family from Atheros include a SPI interface with 3
6244 On reset a SPI flash connected to the first chip select (CS0) is made
6245 directly read-accessible in the CPU address space (up to 16MBytes)
6246 and is usually used to store the bootloader and operating system.
6247 Normal OpenOCD commands like @command{mdw} can be used to display
6248 the flash content while it is in memory-mapped mode (only the first
6249 4MBytes are accessible without additional configuration on reset).
6251 The setup command only requires the @var{base} parameter in order
6252 to identify the memory bank. The actual value for the base address
6253 is not otherwise used by the driver. However the mapping is passed
6254 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
6255 address should be the actual memory mapped base address. For unmapped
6256 chipselects (CS1 and CS2) care should be taken to use a base address
6257 that does not overlap with real memory regions.
6258 Additional information, like flash size, are detected automatically.
6259 An optional additional parameter sets the chipselect for the bank,
6260 with the default CS0.
6261 CS1 and CS2 require additional GPIO setup before they can be used
6262 since the alternate function must be enabled on the GPIO pin
6263 CS1/CS2 is routed to on the given SoC.
6266 flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME
6268 # When using multiple chipselects the base should be different
6269 # for each, otherwise the write_image command is not able to
6270 # distinguish the banks.
6271 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
6272 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
6273 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
6278 @deffn {Flash Driver} {fespi}
6279 @cindex Freedom E SPI
6282 SiFive's Freedom E SPI controller, used in HiFive and other boards.
6285 flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
6289 @subsection Internal Flash (Microcontrollers)
6291 @deffn {Flash Driver} {aduc702x}
6292 The ADUC702x analog microcontrollers from Analog Devices
6293 include internal flash and use ARM7TDMI cores.
6294 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
6295 The setup command only requires the @var{target} argument
6296 since all devices in this family have the same memory layout.
6299 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
6303 @deffn {Flash Driver} {ambiqmicro}
6306 All members of the Apollo microcontroller family from
6307 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
6308 The host connects over USB to an FTDI interface that communicates
6309 with the target using SWD.
6311 The @var{ambiqmicro} driver reads the Chip Information Register detect
6312 the device class of the MCU.
6313 The Flash and SRAM sizes directly follow device class, and are used
6314 to set up the flash banks.
6315 If this fails, the driver will use default values set to the minimum
6316 sizes of an Apollo chip.
6318 All Apollo chips have two flash banks of the same size.
6319 In all cases the first flash bank starts at location 0,
6320 and the second bank starts after the first.
6324 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
6325 # Flash bank 1 - same size as bank0, starts after bank 0.
6326 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
6330 Flash is programmed using custom entry points into the bootloader.
6331 This is the only way to program the flash as no flash control registers
6332 are available to the user.
6334 The @var{ambiqmicro} driver adds some additional commands:
6336 @deffn {Command} {ambiqmicro mass_erase} <bank>
6339 @deffn {Command} {ambiqmicro page_erase} <bank> <first> <last>
6342 @deffn {Command} {ambiqmicro program_otp} <bank> <offset> <count>
6343 Program OTP is a one time operation to create write protected flash.
6344 The user writes sectors to SRAM starting at 0x10000010.
6345 Program OTP will write these sectors from SRAM to flash, and write protect
6351 @deffn {Flash Driver} {at91samd}
6353 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
6354 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
6356 Do not use for ATSAM D51 and E5x: use @xref{atsame5}.
6358 The devices have one flash bank:
6361 flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
6364 @deffn {Command} {at91samd chip-erase}
6365 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6366 used to erase a chip back to its factory state and does not require the
6367 processor to be halted.
6370 @deffn {Command} {at91samd set-security}
6371 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
6372 to the Flash and can only be undone by using the chip-erase command which
6373 erases the Flash contents and turns off the security bit. Warning: at this
6374 time, openocd will not be able to communicate with a secured chip and it is
6375 therefore not possible to chip-erase it without using another tool.
6378 at91samd set-security enable
6382 @deffn {Command} {at91samd eeprom}
6383 Shows or sets the EEPROM emulation size configuration, stored in the User Row
6384 of the Flash. When setting, the EEPROM size must be specified in bytes and it
6385 must be one of the permitted sizes according to the datasheet. Settings are
6386 written immediately but only take effect on MCU reset. EEPROM emulation
6387 requires additional firmware support and the minimum EEPROM size may not be
6388 the same as the minimum that the hardware supports. Set the EEPROM size to 0
6389 in order to disable this feature.
6393 at91samd eeprom 1024
6397 @deffn {Command} {at91samd bootloader}
6398 Shows or sets the bootloader size configuration, stored in the User Row of the
6399 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6400 must be specified in bytes and it must be one of the permitted sizes according
6401 to the datasheet. Settings are written immediately but only take effect on
6402 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
6406 at91samd bootloader 16384
6410 @deffn {Command} {at91samd dsu_reset_deassert}
6411 This command releases internal reset held by DSU
6412 and prepares reset vector catch in case of reset halt.
6413 Command is used internally in event reset-deassert-post.
6416 @deffn {Command} {at91samd nvmuserrow}
6417 Writes or reads the entire 64 bit wide NVM user row register which is located at
6418 0x804000. This register includes various fuses lock-bits and factory calibration
6419 data. Reading the register is done by invoking this command without any
6420 arguments. Writing is possible by giving 1 or 2 hex values. The first argument
6421 is the register value to be written and the second one is an optional changemask.
6422 Every bit which value in changemask is 0 will stay unchanged. The lock- and
6423 reserved-bits are masked out and cannot be changed.
6427 >at91samd nvmuserrow
6428 NVMUSERROW: 0xFFFFFC5DD8E0C788
6429 # Write 0xFFFFFC5DD8E0C788 to user row
6430 >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
6431 # Write 0x12300 to user row but leave other bits and low
6433 >at91samd nvmuserrow 0x12345 0xFFF00
6440 @deffn {Flash Driver} {at91sam3}
6442 All members of the AT91SAM3 microcontroller family from
6443 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
6444 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
6445 that the driver was orginaly developed and tested using the
6446 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
6447 the family was cribbed from the data sheet. @emph{Note to future
6448 readers/updaters: Please remove this worrisome comment after other
6449 chips are confirmed.}
6451 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
6452 have one flash bank. In all cases the flash banks are at
6453 the following fixed locations:
6456 # Flash bank 0 - all chips
6457 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
6458 # Flash bank 1 - only 256K chips
6459 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
6462 Internally, the AT91SAM3 flash memory is organized as follows.
6463 Unlike the AT91SAM7 chips, these are not used as parameters
6464 to the @command{flash bank} command:
6467 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
6468 @item @emph{Bank Size:} 128K/64K Per flash bank
6469 @item @emph{Sectors:} 16 or 8 per bank
6470 @item @emph{SectorSize:} 8K Per Sector
6471 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
6474 The AT91SAM3 driver adds some additional commands:
6476 @deffn {Command} {at91sam3 gpnvm}
6477 @deffnx {Command} {at91sam3 gpnvm clear} number
6478 @deffnx {Command} {at91sam3 gpnvm set} number
6479 @deffnx {Command} {at91sam3 gpnvm show} [@option{all}|number]
6480 With no parameters, @command{show} or @command{show all},
6481 shows the status of all GPNVM bits.
6482 With @command{show} @var{number}, displays that bit.
6484 With @command{set} @var{number} or @command{clear} @var{number},
6485 modifies that GPNVM bit.
6488 @deffn {Command} {at91sam3 info}
6489 This command attempts to display information about the AT91SAM3
6490 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
6491 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
6492 document id: doc6430A] and decodes the values. @emph{Second} it reads the
6493 various clock configuration registers and attempts to display how it
6494 believes the chip is configured. By default, the SLOWCLK is assumed to
6495 be 32768 Hz, see the command @command{at91sam3 slowclk}.
6498 @deffn {Command} {at91sam3 slowclk} [value]
6499 This command shows/sets the slow clock frequency used in the
6500 @command{at91sam3 info} command calculations above.
6504 @deffn {Flash Driver} {at91sam4}
6506 All members of the AT91SAM4 microcontroller family from
6507 Atmel include internal flash and use ARM's Cortex-M4 core.
6508 This driver uses the same command names/syntax as @xref{at91sam3}.
6511 @deffn {Flash Driver} {at91sam4l}
6513 All members of the AT91SAM4L microcontroller family from
6514 Atmel include internal flash and use ARM's Cortex-M4 core.
6515 This driver uses the same command names/syntax as @xref{at91sam3}.
6517 The AT91SAM4L driver adds some additional commands:
6518 @deffn {Command} {at91sam4l smap_reset_deassert}
6519 This command releases internal reset held by SMAP
6520 and prepares reset vector catch in case of reset halt.
6521 Command is used internally in event reset-deassert-post.
6526 @deffn {Flash Driver} {atsame5}
6528 All members of the SAM E54, E53, E51 and D51 microcontroller
6529 families from Microchip (former Atmel) include internal flash
6530 and use ARM's Cortex-M4 core.
6532 The devices have two ECC flash banks with a swapping feature.
6533 This driver handles both banks together as it were one.
6534 Bank swapping is not supported yet.
6537 flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
6540 @deffn {Command} {atsame5 bootloader}
6541 Shows or sets the bootloader size configuration, stored in the User Page of the
6542 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6543 must be specified in bytes. The nearest bigger protection size is used.
6544 Settings are written immediately but only take effect on MCU reset.
6545 Setting the bootloader size to 0 disables bootloader protection.
6549 atsame5 bootloader 16384
6553 @deffn {Command} {atsame5 chip-erase}
6554 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6555 used to erase a chip back to its factory state and does not require the
6556 processor to be halted.
6559 @deffn {Command} {atsame5 dsu_reset_deassert}
6560 This command releases internal reset held by DSU
6561 and prepares reset vector catch in case of reset halt.
6562 Command is used internally in event reset-deassert-post.
6565 @deffn {Command} {atsame5 userpage}
6566 Writes or reads the first 64 bits of NVM User Page which is located at
6567 0x804000. This field includes various fuses.
6568 Reading is done by invoking this command without any arguments.
6569 Writing is possible by giving 1 or 2 hex values. The first argument
6570 is the value to be written and the second one is an optional bit mask
6571 (a zero bit in the mask means the bit stays unchanged).
6572 The reserved fields are always masked out and cannot be changed.
6577 USER PAGE: 0xAEECFF80FE9A9239
6579 >atsame5 userpage 0xAEECFF80FE9A9239
6580 # Write 2 to SEESBLK and 4 to SEEPSZ fields but leave other
6581 # bits unchanged (setup SmartEEPROM of virtual size 8192
6583 >atsame5 userpage 0x4200000000 0x7f00000000
6589 @deffn {Flash Driver} {atsamv}
6591 All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from
6592 Atmel include internal flash and use ARM's Cortex-M7 core.
6593 This driver uses the same command names/syntax as @xref{at91sam3}.
6596 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
6599 @deffn {Command} {atsamv gpnvm} [@option{show} [@option{all}|number]]
6600 @deffnx {Command} {atsamv gpnvm} (@option{clr}|@option{set}) number
6601 With no parameters, @option{show} or @option{show all},
6602 shows the status of all GPNVM bits.
6603 With @option{show} @var{number}, displays that bit.
6605 With @option{set} @var{number} or @option{clear} @var{number},
6606 modifies that GPNVM bit.
6611 @deffn {Flash Driver} {at91sam7}
6612 All members of the AT91SAM7 microcontroller family from Atmel include
6613 internal flash and use ARM7TDMI cores. The driver automatically
6614 recognizes a number of these chips using the chip identification
6615 register, and autoconfigures itself.
6618 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
6621 For chips which are not recognized by the controller driver, you must
6622 provide additional parameters in the following order:
6625 @item @var{chip_model} ... label used with @command{flash info}
6627 @item @var{sectors_per_bank}
6628 @item @var{pages_per_sector}
6629 @item @var{pages_size}
6630 @item @var{num_nvm_bits}
6631 @item @var{freq_khz} ... required if an external clock is provided,
6632 optional (but recommended) when the oscillator frequency is known
6635 It is recommended that you provide zeroes for all of those values
6636 except the clock frequency, so that everything except that frequency
6637 will be autoconfigured.
6638 Knowing the frequency helps ensure correct timings for flash access.
6640 The flash controller handles erases automatically on a page (128/256 byte)
6641 basis, so explicit erase commands are not necessary for flash programming.
6642 However, there is an ``EraseAll`` command that can erase an entire flash
6643 plane (of up to 256KB), and it will be used automatically when you issue
6644 @command{flash erase_sector} or @command{flash erase_address} commands.
6646 @deffn {Command} {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
6647 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
6648 bit for the processor. Each processor has a number of such bits,
6649 used for controlling features such as brownout detection (so they
6650 are not truly general purpose).
6652 This assumes that the first flash bank (number 0) is associated with
6653 the appropriate at91sam7 target.
6658 @deffn {Flash Driver} {avr}
6659 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
6660 @emph{The current implementation is incomplete.}
6661 @comment - defines mass_erase ... pointless given flash_erase_address
6664 @deffn {Flash Driver} {bluenrg-x}
6665 STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP/LPS Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
6666 The driver automatically recognizes these chips using
6667 the chip identification registers, and autoconfigures itself.
6670 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
6673 Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
6674 each single sector one by one.
6677 flash erase_sector 0 0 last # It will perform a mass erase
6680 Triggering a mass erase is also useful when users want to disable readout protection.
6683 @deffn {Flash Driver} {cc26xx}
6684 All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
6685 Instruments include internal flash. The cc26xx flash driver supports both the
6686 CC13xx and CC26xx family of devices. The driver automatically recognizes the
6687 specific version's flash parameters and autoconfigures itself. The flash bank
6688 starts at address 0.
6691 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
6695 @deffn {Flash Driver} {cc3220sf}
6696 The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
6697 Instruments includes 1MB of internal flash. The cc3220sf flash driver only
6698 supports the internal flash. The serial flash on SimpleLink boards is
6699 programmed via the bootloader over a UART connection. Security features of
6700 the CC3220SF may erase the internal flash during power on reset. Refer to
6701 documentation at @url{www.ti.com/cc3220sf} for details on security features
6702 and programming the serial flash.
6705 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
6709 @deffn {Flash Driver} {efm32}
6710 All members of the EFM32/EFR32 microcontroller family from Energy Micro (now Silicon Labs)
6711 include internal flash and use Arm Cortex-M3 or Cortex-M4 cores. The driver automatically
6712 recognizes a number of these chips using the chip identification register, and
6713 autoconfigures itself.
6715 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
6717 It supports writing to the user data page, as well as the portion of the lockbits page
6718 past 512 bytes on chips with larger page sizes. The latter is used by the SiLabs
6719 bootloader/AppLoader system for encryption keys. Setting protection on these pages is
6720 currently not supported.
6722 flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
6723 flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
6726 A special feature of efm32 controllers is that it is possible to completely disable the
6727 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
6728 this via the following command:
6732 The @var{num} parameter is a value shown by @command{flash banks}.
6733 Note that in order for this command to take effect, the target needs to be reset.
6734 @emph{The current implementation is incomplete. Unprotecting flash pages is not
6738 @deffn {Flash Driver} {esirisc}
6739 Members of the eSi-RISC family may optionally include internal flash programmed
6740 via the eSi-TSMC Flash interface. Additional parameters are required to
6741 configure the driver: @option{cfg_address} is the base address of the
6742 configuration register interface, @option{clock_hz} is the expected clock
6743 frequency, and @option{wait_states} is the number of configured read wait states.
6746 flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
6747 $_TARGETNAME cfg_address clock_hz wait_states
6750 @deffn {Command} {esirisc flash mass_erase} bank_id
6751 Erase all pages in data memory for the bank identified by @option{bank_id}.
6754 @deffn {Command} {esirisc flash ref_erase} bank_id
6755 Erase the reference cell for the bank identified by @option{bank_id}. @emph{This
6756 is an uncommon operation.}
6760 @deffn {Flash Driver} {fm3}
6761 All members of the FM3 microcontroller family from Fujitsu
6762 include internal flash and use ARM Cortex-M3 cores.
6763 The @var{fm3} driver uses the @var{target} parameter to select the
6764 correct bank config, it can currently be one of the following:
6765 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
6766 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
6769 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
6773 @deffn {Flash Driver} {fm4}
6774 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
6775 include internal flash and use ARM Cortex-M4 cores.
6776 The @var{fm4} driver uses a @var{family} parameter to select the
6777 correct bank config, it can currently be one of the following:
6778 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
6779 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
6780 with @code{x} treated as wildcard and otherwise case (and any trailing
6781 characters) ignored.
6784 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
6785 $_TARGETNAME S6E2CCAJ0A
6786 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
6787 $_TARGETNAME S6E2CCAJ0A
6789 @emph{The current implementation is incomplete. Protection is not supported,
6790 nor is Chip Erase (only Sector Erase is implemented).}
6793 @deffn {Flash Driver} {kinetis}
6795 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
6796 from NXP (former Freescale) include
6797 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
6798 recognizes flash size and a number of flash banks (1-4) using the chip
6799 identification register, and autoconfigures itself.
6800 Use kinetis_ke driver for KE0x and KEAx devices.
6802 The @var{kinetis} driver defines option:
6804 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
6808 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
6811 @deffn {Config Command} {kinetis create_banks}
6812 Configuration command enables automatic creation of additional flash banks
6813 based on real flash layout of device. Banks are created during device probe.
6814 Use 'flash probe 0' to force probe.
6817 @deffn {Command} {kinetis fcf_source} [protection|write]
6818 Select what source is used when writing to a Flash Configuration Field.
6819 @option{protection} mode builds FCF content from protection bits previously
6820 set by 'flash protect' command.
6821 This mode is default. MCU is protected from unwanted locking by immediate
6822 writing FCF after erase of relevant sector.
6823 @option{write} mode enables direct write to FCF.
6824 Protection cannot be set by 'flash protect' command. FCF is written along
6825 with the rest of a flash image.
6826 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
6829 @deffn {Command} {kinetis fopt} [num]
6830 Set value to write to FOPT byte of Flash Configuration Field.
6831 Used in kinetis 'fcf_source protection' mode only.
6834 @deffn {Command} {kinetis mdm check_security}
6835 Checks status of device security lock. Used internally in examine-end
6836 and examine-fail event.
6839 @deffn {Command} {kinetis mdm halt}
6840 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
6841 loop when connecting to an unsecured target.
6844 @deffn {Command} {kinetis mdm mass_erase}
6845 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
6846 back to its factory state, removing security. It does not require the processor
6847 to be halted, however the target will remain in a halted state after this
6851 @deffn {Command} {kinetis nvm_partition}
6852 For FlexNVM devices only (KxxDX and KxxFX).
6853 Command shows or sets data flash or EEPROM backup size in kilobytes,
6854 sets two EEPROM blocks sizes in bytes and enables/disables loading
6855 of EEPROM contents to FlexRAM during reset.
6857 For details see device reference manual, Flash Memory Module,
6858 Program Partition command.
6860 Setting is possible only once after mass_erase.
6861 Reset the device after partition setting.
6863 Show partition size:
6865 kinetis nvm_partition info
6868 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
6869 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
6871 kinetis nvm_partition dataflash 32 512 1536 on
6874 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
6875 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
6877 kinetis nvm_partition eebkp 16 1024 1024 off
6881 @deffn {Command} {kinetis mdm reset}
6882 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
6883 RESET pin, which can be used to reset other hardware on board.
6886 @deffn {Command} {kinetis disable_wdog}
6887 For Kx devices only (KLx has different COP watchdog, it is not supported).
6888 Command disables watchdog timer.
6892 @deffn {Flash Driver} {kinetis_ke}
6894 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
6895 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
6896 the KE0x sub-family using the chip identification register, and
6897 autoconfigures itself.
6898 Use kinetis (not kinetis_ke) driver for KE1x devices.
6901 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
6904 @deffn {Command} {kinetis_ke mdm check_security}
6905 Checks status of device security lock. Used internally in examine-end event.
6908 @deffn {Command} {kinetis_ke mdm mass_erase}
6909 Issues a complete Flash erase via the MDM-AP.
6910 This can be used to erase a chip back to its factory state.
6911 Command removes security lock from a device (use of SRST highly recommended).
6912 It does not require the processor to be halted.
6915 @deffn {Command} {kinetis_ke disable_wdog}
6916 Command disables watchdog timer.
6920 @deffn {Flash Driver} {lpc2000}
6921 This is the driver to support internal flash of all members of the
6922 LPC11(x)00 and LPC1300 microcontroller families and most members of
6923 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
6924 LPC8Nxx and NHS31xx microcontroller families from NXP.
6927 There are LPC2000 devices which are not supported by the @var{lpc2000}
6929 The LPC2888 is supported by the @var{lpc288x} driver.
6930 The LPC29xx family is supported by the @var{lpc2900} driver.
6933 The @var{lpc2000} driver defines two mandatory and two optional parameters,
6934 which must appear in the following order:
6937 @item @var{variant} ... required, may be
6938 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
6939 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
6940 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
6941 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
6943 @option{lpc800} (LPC8xx)
6944 @option{lpc1100} (LPC11(x)xx and LPC13xx)
6945 @option{lpc1500} (LPC15xx)
6946 @option{lpc54100} (LPC541xx)
6947 @option{lpc4000} (LPC40xx)
6948 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
6949 LPC8xx, LPC13xx, LPC17xx, LPC40xx, LPC8Nxx and NHS31xx
6950 @item @var{clock_kHz} ... the frequency, in kiloHertz,
6951 at which the core is running
6952 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
6953 telling the driver to calculate a valid checksum for the exception vector table.
6955 If you don't provide @option{calc_checksum} when you're writing the vector
6956 table, the boot ROM will almost certainly ignore your flash image.
6957 However, if you do provide it,
6958 with most tool chains @command{verify_image} will fail.
6960 @item @option{iap_entry} ... optional telling the driver to use a different
6961 ROM IAP entry point.
6964 LPC flashes don't require the chip and bus width to be specified.
6967 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
6968 lpc2000_v2 14765 calc_checksum
6971 @deffn {Command} {lpc2000 part_id} bank
6972 Displays the four byte part identifier associated with
6973 the specified flash @var{bank}.
6977 @deffn {Flash Driver} {lpc288x}
6978 The LPC2888 microcontroller from NXP needs slightly different flash
6979 support from its lpc2000 siblings.
6980 The @var{lpc288x} driver defines one mandatory parameter,
6981 the programming clock rate in Hz.
6982 LPC flashes don't require the chip and bus width to be specified.
6985 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
6989 @deffn {Flash Driver} {lpc2900}
6990 This driver supports the LPC29xx ARM968E based microcontroller family
6993 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
6994 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
6995 sector layout are auto-configured by the driver.
6996 The driver has one additional mandatory parameter: The CPU clock rate
6997 (in kHz) at the time the flash operations will take place. Most of the time this
6998 will not be the crystal frequency, but a higher PLL frequency. The
6999 @code{reset-init} event handler in the board script is usually the place where
7002 The driver rejects flashless devices (currently the LPC2930).
7004 The EEPROM in LPC2900 devices is not mapped directly into the address space.
7005 It must be handled much more like NAND flash memory, and will therefore be
7006 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
7008 Sector protection in terms of the LPC2900 is handled transparently. Every time a
7009 sector needs to be erased or programmed, it is automatically unprotected.
7010 What is shown as protection status in the @code{flash info} command, is
7011 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
7012 sector from ever being erased or programmed again. As this is an irreversible
7013 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
7014 and not by the standard @code{flash protect} command.
7016 Example for a 125 MHz clock frequency:
7018 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
7021 Some @code{lpc2900}-specific commands are defined. In the following command list,
7022 the @var{bank} parameter is the bank number as obtained by the
7023 @code{flash banks} command.
7025 @deffn {Command} {lpc2900 signature} bank
7026 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
7027 content. This is a hardware feature of the flash block, hence the calculation is
7028 very fast. You may use this to verify the content of a programmed device against
7033 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
7037 @deffn {Command} {lpc2900 read_custom} bank filename
7038 Reads the 912 bytes of customer information from the flash index sector, and
7039 saves it to a file in binary format.
7042 lpc2900 read_custom 0 /path_to/customer_info.bin
7046 The index sector of the flash is a @emph{write-only} sector. It cannot be
7047 erased! In order to guard against unintentional write access, all following
7048 commands need to be preceded by a successful call to the @code{password}
7051 @deffn {Command} {lpc2900 password} bank password
7052 You need to use this command right before each of the following commands:
7053 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
7054 @code{lpc2900 secure_jtag}.
7056 The password string is fixed to "I_know_what_I_am_doing".
7059 lpc2900 password 0 I_know_what_I_am_doing
7060 Potentially dangerous operation allowed in next command!
7064 @deffn {Command} {lpc2900 write_custom} bank filename type
7065 Writes the content of the file into the customer info space of the flash index
7066 sector. The filetype can be specified with the @var{type} field. Possible values
7067 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
7068 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
7069 contain a single section, and the contained data length must be exactly
7071 @quotation Attention
7072 This cannot be reverted! Be careful!
7076 lpc2900 write_custom 0 /path_to/customer_info.bin bin
7080 @deffn {Command} {lpc2900 secure_sector} bank first last
7081 Secures the sector range from @var{first} to @var{last} (including) against
7082 further program and erase operations. The sector security will be effective
7083 after the next power cycle.
7084 @quotation Attention
7085 This cannot be reverted! Be careful!
7087 Secured sectors appear as @emph{protected} in the @code{flash info} command.
7090 lpc2900 secure_sector 0 1 1
7092 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
7093 # 0: 0x00000000 (0x2000 8kB) not protected
7094 # 1: 0x00002000 (0x2000 8kB) protected
7095 # 2: 0x00004000 (0x2000 8kB) not protected
7099 @deffn {Command} {lpc2900 secure_jtag} bank
7100 Irreversibly disable the JTAG port. The new JTAG security setting will be
7101 effective after the next power cycle.
7102 @quotation Attention
7103 This cannot be reverted! Be careful!
7107 lpc2900 secure_jtag 0
7112 @deffn {Flash Driver} {mdr}
7113 This drivers handles the integrated NOR flash on Milandr Cortex-M
7114 based controllers. A known limitation is that the Info memory can't be
7115 read or verified as it's not memory mapped.
7118 flash bank <name> mdr <base> <size> \
7119 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
7123 @item @var{type} - 0 for main memory, 1 for info memory
7124 @item @var{page_count} - total number of pages
7125 @item @var{sec_count} - number of sector per page count
7130 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
7131 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
7132 0 0 $_TARGETNAME 1 1 4
7134 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
7135 0 0 $_TARGETNAME 0 32 4
7140 @deffn {Flash Driver} {msp432}
7141 All versions of the SimpleLink MSP432 microcontrollers from Texas
7142 Instruments include internal flash. The msp432 flash driver automatically
7143 recognizes the specific version's flash parameters and autoconfigures itself.
7144 Main program flash starts at address 0. The information flash region on
7145 MSP432P4 versions starts at address 0x200000.
7148 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
7151 @deffn {Command} {msp432 mass_erase} bank_id [main|all]
7152 Performs a complete erase of flash. By default, @command{mass_erase} will erase
7153 only the main program flash.
7155 On MSP432P4 versions, using @command{mass_erase all} will erase both the
7156 main program and information flash regions. To also erase the BSL in information
7157 flash, the user must first use the @command{bsl} command.
7160 @deffn {Command} {msp432 bsl} bank_id [unlock|lock]
7161 On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
7162 region in information flash so that flash commands can erase or write the BSL.
7163 Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
7165 To erase and program the BSL:
7168 flash erase_address 0x202000 0x2000
7169 flash write_image bsl.bin 0x202000
7175 @deffn {Flash Driver} {niietcm4}
7176 This drivers handles the integrated NOR flash on NIIET Cortex-M4
7177 based controllers. Flash size and sector layout are auto-configured by the driver.
7178 Main flash memory is called "Bootflash" and has main region and info region.
7179 Info region is NOT memory mapped by default,
7180 but it can replace first part of main region if needed.
7181 Full erase, single and block writes are supported for both main and info regions.
7182 There is additional not memory mapped flash called "Userflash", which
7183 also have division into regions: main and info.
7184 Purpose of userflash - to store system and user settings.
7185 Driver has special commands to perform operations with this memory.
7188 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
7191 Some niietcm4-specific commands are defined:
7193 @deffn {Command} {niietcm4 uflash_read_byte} bank ('main'|'info') address
7194 Read byte from main or info userflash region.
7197 @deffn {Command} {niietcm4 uflash_write_byte} bank ('main'|'info') address value
7198 Write byte to main or info userflash region.
7201 @deffn {Command} {niietcm4 uflash_full_erase} bank
7202 Erase all userflash including info region.
7205 @deffn {Command} {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
7206 Erase sectors of main or info userflash region, starting at sector first up to and including last.
7209 @deffn {Command} {niietcm4 uflash_protect_check} bank ('main'|'info')
7210 Check sectors protect.
7213 @deffn {Command} {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
7214 Protect sectors of main or info userflash region, starting at sector first up to and including last.
7217 @deffn {Command} {niietcm4 bflash_info_remap} bank ('on'|'off')
7218 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
7221 @deffn {Command} {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
7222 Configure external memory interface for boot.
7225 @deffn {Command} {niietcm4 service_mode_erase} bank
7226 Perform emergency erase of all flash (bootflash and userflash).
7229 @deffn {Command} {niietcm4 driver_info} bank
7230 Show information about flash driver.
7235 @deffn {Flash Driver} {npcx}
7236 All versions of the NPCX microcontroller families from Nuvoton include internal
7237 flash. The NPCX flash driver supports the NPCX family of devices. The driver
7238 automatically recognizes the specific version's flash parameters and
7239 autoconfigures itself. The flash bank starts at address 0x64000000.
7242 flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME
7246 @deffn {Flash Driver} {nrf5}
7247 All members of the nRF51 microcontroller families from Nordic Semiconductor
7248 include internal flash and use ARM Cortex-M0 core. nRF52 family powered
7249 by ARM Cortex-M4 or M4F core is supported too. nRF52832 is fully supported
7250 including BPROT flash protection scheme. nRF52833 and nRF52840 devices are
7251 supported with the exception of security extensions (flash access control list
7255 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
7258 Some nrf5-specific commands are defined:
7260 @deffn {Command} {nrf5 mass_erase}
7261 Erases the contents of the code memory and user information
7262 configuration registers as well. It must be noted that this command
7263 works only for chips that do not have factory pre-programmed region 0
7267 @deffn {Command} {nrf5 info}
7268 Decodes and shows information from FICR and UICR registers.
7273 @deffn {Flash Driver} {ocl}
7274 This driver is an implementation of the ``on chip flash loader''
7275 protocol proposed by Pavel Chromy.
7277 It is a minimalistic command-response protocol intended to be used
7278 over a DCC when communicating with an internal or external flash
7279 loader running from RAM. An example implementation for AT91SAM7x is
7280 available in @file{contrib/loaders/flash/at91sam7x/}.
7283 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
7287 @deffn {Flash Driver} {pic32mx}
7288 The PIC32MX microcontrollers are based on the MIPS 4K cores,
7289 and integrate flash memory.
7292 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
7293 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
7296 @comment numerous *disabled* commands are defined:
7297 @comment - chip_erase ... pointless given flash_erase_address
7298 @comment - lock, unlock ... pointless given protect on/off (yes?)
7299 @comment - pgm_word ... shouldn't bank be deduced from address??
7300 Some pic32mx-specific commands are defined:
7301 @deffn {Command} {pic32mx pgm_word} address value bank
7302 Programs the specified 32-bit @var{value} at the given @var{address}
7303 in the specified chip @var{bank}.
7305 @deffn {Command} {pic32mx unlock} bank
7306 Unlock and erase specified chip @var{bank}.
7307 This will remove any Code Protection.
7311 @deffn {Flash Driver} {psoc4}
7312 All members of the PSoC 41xx/42xx microcontroller family from Cypress
7313 include internal flash and use ARM Cortex-M0 cores.
7314 The driver automatically recognizes a number of these chips using
7315 the chip identification register, and autoconfigures itself.
7317 Note: Erased internal flash reads as 00.
7318 System ROM of PSoC 4 does not implement erase of a flash sector.
7321 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
7324 psoc4-specific commands
7325 @deffn {Command} {psoc4 flash_autoerase} num (on|off)
7326 Enables or disables autoerase mode for a flash bank.
7328 If flash_autoerase is off, use mass_erase before flash programming.
7329 Flash erase command fails if region to erase is not whole flash memory.
7331 If flash_autoerase is on, a sector is both erased and programmed in one
7332 system ROM call. Flash erase command is ignored.
7333 This mode is suitable for gdb load.
7335 The @var{num} parameter is a value shown by @command{flash banks}.
7338 @deffn {Command} {psoc4 mass_erase} num
7339 Erases the contents of the flash memory, protection and security lock.
7341 The @var{num} parameter is a value shown by @command{flash banks}.
7345 @deffn {Flash Driver} {psoc5lp}
7346 All members of the PSoC 5LP microcontroller family from Cypress
7347 include internal program flash and use ARM Cortex-M3 cores.
7348 The driver probes for a number of these chips and autoconfigures itself,
7349 apart from the base address.
7352 flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
7355 @b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
7356 @quotation Attention
7357 If flash operations are performed in ECC-disabled mode, they will also affect
7358 the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
7359 then also erase the corresponding 2k data bytes in the 0x48000000 area.
7360 Writing to the ECC data bytes in ECC-disabled mode is not implemented.
7363 Commands defined in the @var{psoc5lp} driver:
7365 @deffn {Command} {psoc5lp mass_erase}
7366 Erases all flash data and ECC/configuration bytes, all flash protection rows,
7367 and all row latches in all flash arrays on the device.
7371 @deffn {Flash Driver} {psoc5lp_eeprom}
7372 All members of the PSoC 5LP microcontroller family from Cypress
7373 include internal EEPROM and use ARM Cortex-M3 cores.
7374 The driver probes for a number of these chips and autoconfigures itself,
7375 apart from the base address.
7378 flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 \
7383 @deffn {Flash Driver} {psoc5lp_nvl}
7384 All members of the PSoC 5LP microcontroller family from Cypress
7385 include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
7386 The driver probes for a number of these chips and autoconfigures itself.
7389 flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
7392 PSoC 5LP chips have multiple NV Latches:
7395 @item Device Configuration NV Latch - 4 bytes
7396 @item Write Once (WO) NV Latch - 4 bytes
7399 @b{Note:} This driver only implements the Device Configuration NVL.
7401 The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
7402 @quotation Attention
7403 Switching ECC mode via write to Device Configuration NVL will require a reset
7404 after successful write.
7408 @deffn {Flash Driver} {psoc6}
7409 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
7410 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
7411 the same Flash/RAM/MMIO address space.
7413 Flash in PSoC6 is split into three regions:
7415 @item Main Flash - this is the main storage for user application.
7416 Total size varies among devices, sector size: 256 kBytes, row size:
7417 512 bytes. Supports erase operation on individual rows.
7418 @item Work Flash - intended to be used as storage for user data
7419 (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
7420 row size: 512 bytes.
7421 @item Supervisory Flash - special region which contains device-specific
7422 service data. This region does not support erase operation. Only few rows can
7423 be programmed by the user, most of the rows are read only. Programming
7424 operation will erase row automatically.
7427 All three flash regions are supported by the driver. Flash geometry is detected
7428 automatically by parsing data in SPCIF_GEOMETRY register.
7430 PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
7433 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 \
7435 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 \
7437 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 \
7439 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 \
7441 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 \
7443 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 \
7446 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 \
7448 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 \
7450 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 \
7452 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 \
7454 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 \
7456 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 \
7460 psoc6-specific commands
7461 @deffn {Command} {psoc6 reset_halt}
7462 Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
7463 When invoked for CM0+ target, it will set break point at application entry point
7464 and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
7465 reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
7466 instead of SYSRESETREQ to avoid unwanted reset of CM0+;
7469 @deffn {Command} {psoc6 mass_erase} num
7470 Erases the contents given flash bank. The @var{num} parameter is a value shown
7471 by @command{flash banks}.
7472 Note: only Main and Work flash regions support Erase operation.
7476 @deffn {Flash Driver} {rp2040}
7477 Supports RP2040 "Raspberry Pi Pico" microcontroller.
7478 RP2040 is a dual-core device with two CM0+ cores. Both cores share the same
7479 Flash/RAM/MMIO address space. Non-volatile storage is achieved with an
7480 external QSPI flash; a Boot ROM provides helper functions.
7483 flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME
7487 @deffn {Flash Driver} {sim3x}
7488 All members of the SiM3 microcontroller family from Silicon Laboratories
7489 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
7491 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
7492 If this fails, it will use the @var{size} parameter as the size of flash bank.
7495 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
7498 There are 2 commands defined in the @var{sim3x} driver:
7500 @deffn {Command} {sim3x mass_erase}
7501 Erases the complete flash. This is used to unlock the flash.
7502 And this command is only possible when using the SWD interface.
7505 @deffn {Command} {sim3x lock}
7506 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
7510 @deffn {Flash Driver} {stellaris}
7511 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
7512 families from Texas Instruments include internal flash. The driver
7513 automatically recognizes a number of these chips using the chip
7514 identification register, and autoconfigures itself.
7517 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
7520 @deffn {Command} {stellaris recover}
7521 Performs the @emph{Recovering a "Locked" Device} procedure to restore
7522 the flash and its associated nonvolatile registers to their factory
7523 default values (erased). This is the only way to remove flash
7524 protection or re-enable debugging if that capability has been
7527 Note that the final "power cycle the chip" step in this procedure
7528 must be performed by hand, since OpenOCD can't do it.
7530 if more than one Stellaris chip is connected, the procedure is
7531 applied to all of them.
7536 @deffn {Flash Driver} {stm32f1x}
7537 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
7538 from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller
7539 families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores.
7540 The driver also works with GD32VF103 powered by RISC-V core.
7541 The driver automatically recognizes a number of these chips using
7542 the chip identification register, and autoconfigures itself.
7545 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
7548 Note that some devices have been found that have a flash size register that contains
7549 an invalid value, to workaround this issue you can override the probed value used by
7553 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
7556 If you have a target with dual flash banks then define the second bank
7557 as per the following example.
7559 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
7562 Some stm32f1x-specific commands are defined:
7564 @deffn {Command} {stm32f1x lock} num
7565 Locks the entire stm32 device against reading.
7566 The @var{num} parameter is a value shown by @command{flash banks}.
7569 @deffn {Command} {stm32f1x unlock} num
7570 Unlocks the entire stm32 device for reading. This command will cause
7571 a mass erase of the entire stm32 device if previously locked.
7572 The @var{num} parameter is a value shown by @command{flash banks}.
7575 @deffn {Command} {stm32f1x mass_erase} num
7576 Mass erases the entire stm32 device.
7577 The @var{num} parameter is a value shown by @command{flash banks}.
7580 @deffn {Command} {stm32f1x options_read} num
7581 Reads and displays active stm32 option bytes loaded during POR
7582 or upon executing the @command{stm32f1x options_load} command.
7583 The @var{num} parameter is a value shown by @command{flash banks}.
7586 @deffn {Command} {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP}) (@option{USEROPT} user_data)
7587 Writes the stm32 option byte with the specified values.
7588 The @var{num} parameter is a value shown by @command{flash banks}.
7589 The @var{user_data} parameter is content of higher 16 bits of the option byte register (Data0 and Data1 as one 16bit number).
7592 @deffn {Command} {stm32f1x options_load} num
7593 Generates a special kind of reset to re-load the stm32 option bytes written
7594 by the @command{stm32f1x options_write} or @command{flash protect} commands
7595 without having to power cycle the target. Not applicable to stm32f1x devices.
7596 The @var{num} parameter is a value shown by @command{flash banks}.
7600 @deffn {Flash Driver} {stm32f2x}
7601 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
7602 include internal flash and use ARM Cortex-M3/M4/M7 cores.
7603 The driver automatically recognizes a number of these chips using
7604 the chip identification register, and autoconfigures itself.
7607 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
7610 If you use OTP (One-Time Programmable) memory define it as a second bank
7611 as per the following example.
7613 flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME
7616 @deffn {Command} {stm32f2x otp} num (@option{enable}|@option{disable}|@option{show})
7617 Enables or disables OTP write commands for bank @var{num}.
7618 The @var{num} parameter is a value shown by @command{flash banks}.
7621 Note that some devices have been found that have a flash size register that contains
7622 an invalid value, to workaround this issue you can override the probed value used by
7626 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
7629 Some stm32f2x-specific commands are defined:
7631 @deffn {Command} {stm32f2x lock} num
7632 Locks the entire stm32 device.
7633 The @var{num} parameter is a value shown by @command{flash banks}.
7636 @deffn {Command} {stm32f2x unlock} num
7637 Unlocks the entire stm32 device.
7638 The @var{num} parameter is a value shown by @command{flash banks}.
7641 @deffn {Command} {stm32f2x mass_erase} num
7642 Mass erases the entire stm32f2x device.
7643 The @var{num} parameter is a value shown by @command{flash banks}.
7646 @deffn {Command} {stm32f2x options_read} num
7647 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
7648 The @var{num} parameter is a value shown by @command{flash banks}.
7651 @deffn {Command} {stm32f2x options_write} num user_options boot_addr0 boot_addr1
7652 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
7653 Warning: The meaning of the various bits depends on the device, always check datasheet!
7654 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
7655 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
7656 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
7659 @deffn {Command} {stm32f2x optcr2_write} num optcr2
7660 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
7661 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
7665 @deffn {Flash Driver} {stm32h7x}
7666 All members of the STM32H7 microcontroller families from STMicroelectronics
7667 include internal flash and use ARM Cortex-M7 core.
7668 The driver automatically recognizes a number of these chips using
7669 the chip identification register, and autoconfigures itself.
7672 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
7675 Note that some devices have been found that have a flash size register that contains
7676 an invalid value, to workaround this issue you can override the probed value used by
7680 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
7683 Some stm32h7x-specific commands are defined:
7685 @deffn {Command} {stm32h7x lock} num
7686 Locks the entire stm32 device.
7687 The @var{num} parameter is a value shown by @command{flash banks}.
7690 @deffn {Command} {stm32h7x unlock} num
7691 Unlocks the entire stm32 device.
7692 The @var{num} parameter is a value shown by @command{flash banks}.
7695 @deffn {Command} {stm32h7x mass_erase} num
7696 Mass erases the entire stm32h7x device.
7697 The @var{num} parameter is a value shown by @command{flash banks}.
7700 @deffn {Command} {stm32h7x option_read} num reg_offset
7701 Reads an option byte register from the stm32h7x device.
7702 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7703 is the register offset of the option byte to read from the used bank registers' base.
7704 For example: in STM32H74x/H75x the bank 1 registers' base is 0x52002000 and 0x52002100 for bank 2.
7709 stm32h7x option_read 0 0x1c
7711 stm32h7x option_read 0 0x38
7713 stm32h7x option_read 1 0x38
7717 @deffn {Command} {stm32h7x option_write} num reg_offset value [reg_mask]
7718 Writes an option byte register of the stm32h7x device.
7719 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7720 is the register offset of the option byte to write from the used bank register base,
7721 and @var{reg_mask} is the mask to apply when writing the register (only bits with a '1'
7726 # swap bank 1 and bank 2 in dual bank devices
7727 # by setting SWAP_BANK_OPT bit in OPTSR_PRG
7728 stm32h7x option_write 0 0x20 0x8000000 0x8000000
7733 @deffn {Flash Driver} {stm32lx}
7734 All members of the STM32L0 and STM32L1 microcontroller families from STMicroelectronics
7735 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
7736 The driver automatically recognizes a number of these chips using
7737 the chip identification register, and autoconfigures itself.
7740 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
7743 Note that some devices have been found that have a flash size register that contains
7744 an invalid value, to workaround this issue you can override the probed value used by
7745 the flash driver. If you use 0 as the bank base address, it tells the
7746 driver to autodetect the bank location assuming you're configuring the
7750 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
7753 Some stm32lx-specific commands are defined:
7755 @deffn {Command} {stm32lx lock} num
7756 Locks the entire stm32 device.
7757 The @var{num} parameter is a value shown by @command{flash banks}.
7760 @deffn {Command} {stm32lx unlock} num
7761 Unlocks the entire stm32 device.
7762 The @var{num} parameter is a value shown by @command{flash banks}.
7765 @deffn {Command} {stm32lx mass_erase} num
7766 Mass erases the entire stm32lx device (all flash banks and EEPROM
7767 data). This is the only way to unlock a protected flash (unless RDP
7768 Level is 2 which can't be unlocked at all).
7769 The @var{num} parameter is a value shown by @command{flash banks}.
7773 @deffn {Flash Driver} {stm32l4x}
7774 All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL
7775 microcontroller families from STMicroelectronics include internal flash
7776 and use ARM Cortex-M0+, M4 and M33 cores.
7777 The driver automatically recognizes a number of these chips using
7778 the chip identification register, and autoconfigures itself.
7781 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
7784 If you use OTP (One-Time Programmable) memory define it as a second bank
7785 as per the following example.
7787 flash bank $_FLASHNAME stm32l4x 0x1FFF7000 0 0 0 $_TARGETNAME
7790 @deffn {Command} {stm32l4x otp} num (@option{enable}|@option{disable}|@option{show})
7791 Enables or disables OTP write commands for bank @var{num}.
7792 The @var{num} parameter is a value shown by @command{flash banks}.
7795 Note that some devices have been found that have a flash size register that contains
7796 an invalid value, to workaround this issue you can override the probed value used by
7797 the flash driver. However, specifying a wrong value might lead to a completely
7798 wrong flash layout, so this feature must be used carefully.
7801 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
7804 Some stm32l4x-specific commands are defined:
7806 @deffn {Command} {stm32l4x lock} num
7807 Locks the entire stm32 device.
7808 The @var{num} parameter is a value shown by @command{flash banks}.
7810 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
7813 @deffn {Command} {stm32l4x unlock} num
7814 Unlocks the entire stm32 device.
7815 The @var{num} parameter is a value shown by @command{flash banks}.
7817 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
7820 @deffn {Command} {stm32l4x mass_erase} num
7821 Mass erases the entire stm32l4x device.
7822 The @var{num} parameter is a value shown by @command{flash banks}.
7825 @deffn {Command} {stm32l4x option_read} num reg_offset
7826 Reads an option byte register from the stm32l4x device.
7827 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7828 is the register offset of the Option byte to read.
7830 For example to read the FLASH_OPTR register:
7832 stm32l4x option_read 0 0x20
7833 # Option Register (for STM32L4x): <0x40022020> = 0xffeff8aa
7834 # Option Register (for STM32WBx): <0x58004020> = ...
7835 # The correct flash base address will be used automatically
7838 The above example will read out the FLASH_OPTR register which contains the RDP
7839 option byte, Watchdog configuration, BOR level etc.
7842 @deffn {Command} {stm32l4x option_write} num reg_offset reg_mask
7843 Write an option byte register of the stm32l4x device.
7844 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7845 is the register offset of the Option byte to write, and @var{reg_mask} is the mask
7846 to apply when writing the register (only bits with a '1' will be touched).
7848 @emph{Note:} To apply the option bytes change immediately, use @command{stm32l4x option_load}.
7850 For example to write the WRP1AR option bytes:
7852 stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
7855 The above example will write the WRP1AR option register configuring the Write protection
7856 Area A for bank 1. The above example set WRP1AR_END=255, WRP1AR_START=0.
7857 This will effectively write protect all sectors in flash bank 1.
7860 @deffn {Command} {stm32l4x wrp_info} num [device_bank]
7861 List the protected areas using WRP.
7862 The @var{num} parameter is a value shown by @command{flash banks}.
7863 @var{device_bank} parameter is optional, possible values 'bank1' or 'bank2',
7864 if not specified, the command will display the whole flash protected areas.
7866 @b{Note:} @var{device_bank} is different from banks created using @code{flash bank}.
7867 Devices supported in this flash driver, can have main flash memory organized
7868 in single or dual-banks mode.
7869 Thus the usage of @var{device_bank} is meaningful only in dual-bank mode, to get
7870 write protected areas in a specific @var{device_bank}
7874 @deffn {Command} {stm32l4x option_load} num
7875 Forces a re-load of the option byte registers. Will cause a system reset of the device.
7876 The @var{num} parameter is a value shown by @command{flash banks}.
7879 @deffn Command {stm32l4x trustzone} num [@option{enable} | @option{disable}]
7880 Enables or disables Global TrustZone Security, using the TZEN option bit.
7881 If neither @option{enabled} nor @option{disable} are specified, the command will display
7882 the TrustZone status.
7883 @emph{Note:} This command works only with devices with TrustZone, eg. STM32L5.
7884 @emph{Note:} This command will perform an OBL_Launch after modifying the TZEN.
7888 @deffn {Flash Driver} {str7x}
7889 All members of the STR7 microcontroller family from STMicroelectronics
7890 include internal flash and use ARM7TDMI cores.
7891 The @var{str7x} driver defines one mandatory parameter, @var{variant},
7892 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
7895 flash bank $_FLASHNAME str7x \
7896 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
7899 @deffn {Command} {str7x disable_jtag} bank
7900 Activate the Debug/Readout protection mechanism
7901 for the specified flash bank.
7905 @deffn {Flash Driver} {str9x}
7906 Most members of the STR9 microcontroller family from STMicroelectronics
7907 include internal flash and use ARM966E cores.
7908 The str9 needs the flash controller to be configured using
7909 the @command{str9x flash_config} command prior to Flash programming.
7912 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
7913 str9x flash_config 0 4 2 0 0x80000
7916 @deffn {Command} {str9x flash_config} num bbsr nbbsr bbadr nbbadr
7917 Configures the str9 flash controller.
7918 The @var{num} parameter is a value shown by @command{flash banks}.
7921 @item @var{bbsr} - Boot Bank Size register
7922 @item @var{nbbsr} - Non Boot Bank Size register
7923 @item @var{bbadr} - Boot Bank Start Address register
7924 @item @var{nbbadr} - Boot Bank Start Address register
7930 @deffn {Flash Driver} {str9xpec}
7933 Only use this driver for locking/unlocking the device or configuring the option bytes.
7934 Use the standard str9 driver for programming.
7935 Before using the flash commands the turbo mode must be enabled using the
7936 @command{str9xpec enable_turbo} command.
7938 Here is some background info to help
7939 you better understand how this driver works. OpenOCD has two flash drivers for
7943 Standard driver @option{str9x} programmed via the str9 core. Normally used for
7944 flash programming as it is faster than the @option{str9xpec} driver.
7946 Direct programming @option{str9xpec} using the flash controller. This is an
7947 ISC compliant (IEEE 1532) tap connected in series with the str9 core. The str9
7948 core does not need to be running to program using this flash driver. Typical use
7949 for this driver is locking/unlocking the target and programming the option bytes.
7952 Before we run any commands using the @option{str9xpec} driver we must first disable
7953 the str9 core. This example assumes the @option{str9xpec} driver has been
7954 configured for flash bank 0.
7956 # assert srst, we do not want core running
7957 # while accessing str9xpec flash driver
7959 # turn off target polling
7962 str9xpec enable_turbo 0
7964 str9xpec options_read 0
7965 # re-enable str9 core
7966 str9xpec disable_turbo 0
7970 The above example will read the str9 option bytes.
7971 When performing a unlock remember that you will not be able to halt the str9 - it
7972 has been locked. Halting the core is not required for the @option{str9xpec} driver
7973 as mentioned above, just issue the commands above manually or from a telnet prompt.
7975 Several str9xpec-specific commands are defined:
7977 @deffn {Command} {str9xpec disable_turbo} num
7978 Restore the str9 into JTAG chain.
7981 @deffn {Command} {str9xpec enable_turbo} num
7982 Enable turbo mode, will simply remove the str9 from the chain and talk
7983 directly to the embedded flash controller.
7986 @deffn {Command} {str9xpec lock} num
7987 Lock str9 device. The str9 will only respond to an unlock command that will
7991 @deffn {Command} {str9xpec part_id} num
7992 Prints the part identifier for bank @var{num}.
7995 @deffn {Command} {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
7996 Configure str9 boot bank.
7999 @deffn {Command} {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
8000 Configure str9 lvd source.
8003 @deffn {Command} {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
8004 Configure str9 lvd threshold.
8007 @deffn {Command} {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
8008 Configure str9 lvd reset warning source.
8011 @deffn {Command} {str9xpec options_read} num
8012 Read str9 option bytes.
8015 @deffn {Command} {str9xpec options_write} num
8016 Write str9 option bytes.
8019 @deffn {Command} {str9xpec unlock} num
8025 @deffn {Flash Driver} {swm050}
8027 All members of the swm050 microcontroller family from Foshan Synwit Tech.
8030 flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
8033 One swm050-specific command is defined:
8035 @deffn {Command} {swm050 mass_erase} bank_id
8036 Erases the entire flash bank.
8042 @deffn {Flash Driver} {tms470}
8043 Most members of the TMS470 microcontroller family from Texas Instruments
8044 include internal flash and use ARM7TDMI cores.
8045 This driver doesn't require the chip and bus width to be specified.
8047 Some tms470-specific commands are defined:
8049 @deffn {Command} {tms470 flash_keyset} key0 key1 key2 key3
8050 Saves programming keys in a register, to enable flash erase and write commands.
8053 @deffn {Command} {tms470 osc_megahertz} clock_mhz
8054 Reports the clock speed, which is used to calculate timings.
8057 @deffn {Command} {tms470 plldis} (0|1)
8058 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
8063 @deffn {Flash Driver} {w600}
8064 W60x series Wi-Fi SoC from WinnerMicro
8065 are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside.
8066 The @var{w600} driver uses the @var{target} parameter to select the
8067 correct bank config.
8070 flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
8074 @deffn {Flash Driver} {xmc1xxx}
8075 All members of the XMC1xxx microcontroller family from Infineon.
8076 This driver does not require the chip and bus width to be specified.
8079 @deffn {Flash Driver} {xmc4xxx}
8080 All members of the XMC4xxx microcontroller family from Infineon.
8081 This driver does not require the chip and bus width to be specified.
8083 Some xmc4xxx-specific commands are defined:
8085 @deffn {Command} {xmc4xxx flash_password} bank_id passwd1 passwd2
8086 Saves flash protection passwords which are used to lock the user flash
8089 @deffn {Command} {xmc4xxx flash_unprotect} bank_id user_level[0-1]
8090 Removes Flash write protection from the selected user bank
8095 @section NAND Flash Commands
8098 Compared to NOR or SPI flash, NAND devices are inexpensive
8099 and high density. Today's NAND chips, and multi-chip modules,
8100 commonly hold multiple GigaBytes of data.
8102 NAND chips consist of a number of ``erase blocks'' of a given
8103 size (such as 128 KBytes), each of which is divided into a
8104 number of pages (of perhaps 512 or 2048 bytes each). Each
8105 page of a NAND flash has an ``out of band'' (OOB) area to hold
8106 Error Correcting Code (ECC) and other metadata, usually 16 bytes
8107 of OOB for every 512 bytes of page data.
8109 One key characteristic of NAND flash is that its error rate
8110 is higher than that of NOR flash. In normal operation, that
8111 ECC is used to correct and detect errors. However, NAND
8112 blocks can also wear out and become unusable; those blocks
8113 are then marked "bad". NAND chips are even shipped from the
8114 manufacturer with a few bad blocks. The highest density chips
8115 use a technology (MLC) that wears out more quickly, so ECC
8116 support is increasingly important as a way to detect blocks
8117 that have begun to fail, and help to preserve data integrity
8118 with techniques such as wear leveling.
8120 Software is used to manage the ECC. Some controllers don't
8121 support ECC directly; in those cases, software ECC is used.
8122 Other controllers speed up the ECC calculations with hardware.
8123 Single-bit error correction hardware is routine. Controllers
8124 geared for newer MLC chips may correct 4 or more errors for
8125 every 512 bytes of data.
8127 You will need to make sure that any data you write using
8128 OpenOCD includes the appropriate kind of ECC. For example,
8129 that may mean passing the @code{oob_softecc} flag when
8130 writing NAND data, or ensuring that the correct hardware
8133 The basic steps for using NAND devices include:
8135 @item Declare via the command @command{nand device}
8136 @* Do this in a board-specific configuration file,
8137 passing parameters as needed by the controller.
8138 @item Configure each device using @command{nand probe}.
8139 @* Do this only after the associated target is set up,
8140 such as in its reset-init script or in procures defined
8141 to access that device.
8142 @item Operate on the flash via @command{nand subcommand}
8143 @* Often commands to manipulate the flash are typed by a human, or run
8144 via a script in some automated way. Common task include writing a
8145 boot loader, operating system, or other data needed to initialize or
8149 @b{NOTE:} At the time this text was written, the largest NAND
8150 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
8151 This is because the variables used to hold offsets and lengths
8152 are only 32 bits wide.
8153 (Larger chips may work in some cases, unless an offset or length
8154 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
8155 Some larger devices will work, since they are actually multi-chip
8156 modules with two smaller chips and individual chipselect lines.
8158 @anchor{nandconfiguration}
8159 @subsection NAND Configuration Commands
8160 @cindex NAND configuration
8162 NAND chips must be declared in configuration scripts,
8163 plus some additional configuration that's done after
8164 OpenOCD has initialized.
8166 @deffn {Config Command} {nand device} name driver target [configparams...]
8167 Declares a NAND device, which can be read and written to
8168 after it has been configured through @command{nand probe}.
8169 In OpenOCD, devices are single chips; this is unlike some
8170 operating systems, which may manage multiple chips as if
8171 they were a single (larger) device.
8172 In some cases, configuring a device will activate extra
8173 commands; see the controller-specific documentation.
8175 @b{NOTE:} This command is not available after OpenOCD
8176 initialization has completed. Use it in board specific
8177 configuration files, not interactively.
8180 @item @var{name} ... may be used to reference the NAND bank
8181 in most other NAND commands. A number is also available.
8182 @item @var{driver} ... identifies the NAND controller driver
8183 associated with the NAND device being declared.
8184 @xref{nanddriverlist,,NAND Driver List}.
8185 @item @var{target} ... names the target used when issuing
8186 commands to the NAND controller.
8187 @comment Actually, it's currently a controller-specific parameter...
8188 @item @var{configparams} ... controllers may support, or require,
8189 additional parameters. See the controller-specific documentation
8190 for more information.
8194 @deffn {Command} {nand list}
8195 Prints a summary of each device declared
8196 using @command{nand device}, numbered from zero.
8197 Note that un-probed devices show no details.
8200 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
8201 blocksize: 131072, blocks: 8192
8202 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
8203 blocksize: 131072, blocks: 8192
8208 @deffn {Command} {nand probe} num
8209 Probes the specified device to determine key characteristics
8210 like its page and block sizes, and how many blocks it has.
8211 The @var{num} parameter is the value shown by @command{nand list}.
8212 You must (successfully) probe a device before you can use
8213 it with most other NAND commands.
8216 @subsection Erasing, Reading, Writing to NAND Flash
8218 @deffn {Command} {nand dump} num filename offset length [oob_option]
8219 @cindex NAND reading
8220 Reads binary data from the NAND device and writes it to the file,
8221 starting at the specified offset.
8222 The @var{num} parameter is the value shown by @command{nand list}.
8224 Use a complete path name for @var{filename}, so you don't depend
8225 on the directory used to start the OpenOCD server.
8227 The @var{offset} and @var{length} must be exact multiples of the
8228 device's page size. They describe a data region; the OOB data
8229 associated with each such page may also be accessed.
8231 @b{NOTE:} At the time this text was written, no error correction
8232 was done on the data that's read, unless raw access was disabled
8233 and the underlying NAND controller driver had a @code{read_page}
8234 method which handled that error correction.
8236 By default, only page data is saved to the specified file.
8237 Use an @var{oob_option} parameter to save OOB data:
8239 @item no oob_* parameter
8240 @*Output file holds only page data; OOB is discarded.
8241 @item @code{oob_raw}
8242 @*Output file interleaves page data and OOB data;
8243 the file will be longer than "length" by the size of the
8244 spare areas associated with each data page.
8245 Note that this kind of "raw" access is different from
8246 what's implied by @command{nand raw_access}, which just
8247 controls whether a hardware-aware access method is used.
8248 @item @code{oob_only}
8249 @*Output file has only raw OOB data, and will
8250 be smaller than "length" since it will contain only the
8251 spare areas associated with each data page.
8255 @deffn {Command} {nand erase} num [offset length]
8256 @cindex NAND erasing
8257 @cindex NAND programming
8258 Erases blocks on the specified NAND device, starting at the
8259 specified @var{offset} and continuing for @var{length} bytes.
8260 Both of those values must be exact multiples of the device's
8261 block size, and the region they specify must fit entirely in the chip.
8262 If those parameters are not specified,
8263 the whole NAND chip will be erased.
8264 The @var{num} parameter is the value shown by @command{nand list}.
8266 @b{NOTE:} This command will try to erase bad blocks, when told
8267 to do so, which will probably invalidate the manufacturer's bad
8269 For the remainder of the current server session, @command{nand info}
8270 will still report that the block ``is'' bad.
8273 @deffn {Command} {nand write} num filename offset [option...]
8274 @cindex NAND writing
8275 @cindex NAND programming
8276 Writes binary data from the file into the specified NAND device,
8277 starting at the specified offset. Those pages should already
8278 have been erased; you can't change zero bits to one bits.
8279 The @var{num} parameter is the value shown by @command{nand list}.
8281 Use a complete path name for @var{filename}, so you don't depend
8282 on the directory used to start the OpenOCD server.
8284 The @var{offset} must be an exact multiple of the device's page size.
8285 All data in the file will be written, assuming it doesn't run
8286 past the end of the device.
8287 Only full pages are written, and any extra space in the last
8288 page will be filled with 0xff bytes. (That includes OOB data,
8289 if that's being written.)
8291 @b{NOTE:} At the time this text was written, bad blocks are
8292 ignored. That is, this routine will not skip bad blocks,
8293 but will instead try to write them. This can cause problems.
8295 Provide at most one @var{option} parameter. With some
8296 NAND drivers, the meanings of these parameters may change
8297 if @command{nand raw_access} was used to disable hardware ECC.
8299 @item no oob_* parameter
8300 @*File has only page data, which is written.
8301 If raw access is in use, the OOB area will not be written.
8302 Otherwise, if the underlying NAND controller driver has
8303 a @code{write_page} routine, that routine may write the OOB
8304 with hardware-computed ECC data.
8305 @item @code{oob_only}
8306 @*File has only raw OOB data, which is written to the OOB area.
8307 Each page's data area stays untouched. @i{This can be a dangerous
8308 option}, since it can invalidate the ECC data.
8309 You may need to force raw access to use this mode.
8310 @item @code{oob_raw}
8311 @*File interleaves data and OOB data, both of which are written
8312 If raw access is enabled, the data is written first, then the
8314 Otherwise, if the underlying NAND controller driver has
8315 a @code{write_page} routine, that routine may modify the OOB
8316 before it's written, to include hardware-computed ECC data.
8317 @item @code{oob_softecc}
8318 @*File has only page data, which is written.
8319 The OOB area is filled with 0xff, except for a standard 1-bit
8320 software ECC code stored in conventional locations.
8321 You might need to force raw access to use this mode, to prevent
8322 the underlying driver from applying hardware ECC.
8323 @item @code{oob_softecc_kw}
8324 @*File has only page data, which is written.
8325 The OOB area is filled with 0xff, except for a 4-bit software ECC
8326 specific to the boot ROM in Marvell Kirkwood SoCs.
8327 You might need to force raw access to use this mode, to prevent
8328 the underlying driver from applying hardware ECC.
8332 @deffn {Command} {nand verify} num filename offset [option...]
8333 @cindex NAND verification
8334 @cindex NAND programming
8335 Verify the binary data in the file has been programmed to the
8336 specified NAND device, starting at the specified offset.
8337 The @var{num} parameter is the value shown by @command{nand list}.
8339 Use a complete path name for @var{filename}, so you don't depend
8340 on the directory used to start the OpenOCD server.
8342 The @var{offset} must be an exact multiple of the device's page size.
8343 All data in the file will be read and compared to the contents of the
8344 flash, assuming it doesn't run past the end of the device.
8345 As with @command{nand write}, only full pages are verified, so any extra
8346 space in the last page will be filled with 0xff bytes.
8348 The same @var{options} accepted by @command{nand write},
8349 and the file will be processed similarly to produce the buffers that
8350 can be compared against the contents produced from @command{nand dump}.
8352 @b{NOTE:} This will not work when the underlying NAND controller
8353 driver's @code{write_page} routine must update the OOB with a
8354 hardware-computed ECC before the data is written. This limitation may
8355 be removed in a future release.
8358 @subsection Other NAND commands
8359 @cindex NAND other commands
8361 @deffn {Command} {nand check_bad_blocks} num [offset length]
8362 Checks for manufacturer bad block markers on the specified NAND
8363 device. If no parameters are provided, checks the whole
8364 device; otherwise, starts at the specified @var{offset} and
8365 continues for @var{length} bytes.
8366 Both of those values must be exact multiples of the device's
8367 block size, and the region they specify must fit entirely in the chip.
8368 The @var{num} parameter is the value shown by @command{nand list}.
8370 @b{NOTE:} Before using this command you should force raw access
8371 with @command{nand raw_access enable} to ensure that the underlying
8372 driver will not try to apply hardware ECC.
8375 @deffn {Command} {nand info} num
8376 The @var{num} parameter is the value shown by @command{nand list}.
8377 This prints the one-line summary from "nand list", plus for
8378 devices which have been probed this also prints any known
8379 status for each block.
8382 @deffn {Command} {nand raw_access} num (@option{enable}|@option{disable})
8383 Sets or clears an flag affecting how page I/O is done.
8384 The @var{num} parameter is the value shown by @command{nand list}.
8386 This flag is cleared (disabled) by default, but changing that
8387 value won't affect all NAND devices. The key factor is whether
8388 the underlying driver provides @code{read_page} or @code{write_page}
8389 methods. If it doesn't provide those methods, the setting of
8390 this flag is irrelevant; all access is effectively ``raw''.
8392 When those methods exist, they are normally used when reading
8393 data (@command{nand dump} or reading bad block markers) or
8394 writing it (@command{nand write}). However, enabling
8395 raw access (setting the flag) prevents use of those methods,
8396 bypassing hardware ECC logic.
8397 @i{This can be a dangerous option}, since writing blocks
8398 with the wrong ECC data can cause them to be marked as bad.
8401 @anchor{nanddriverlist}
8402 @subsection NAND Driver List
8403 As noted above, the @command{nand device} command allows
8404 driver-specific options and behaviors.
8405 Some controllers also activate controller-specific commands.
8407 @deffn {NAND Driver} {at91sam9}
8408 This driver handles the NAND controllers found on AT91SAM9 family chips from
8409 Atmel. It takes two extra parameters: address of the NAND chip;
8410 address of the ECC controller.
8412 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
8414 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
8415 @code{read_page} methods are used to utilize the ECC hardware unless they are
8416 disabled by using the @command{nand raw_access} command. There are four
8417 additional commands that are needed to fully configure the AT91SAM9 NAND
8418 controller. Two are optional; most boards use the same wiring for ALE/CLE:
8419 @deffn {Config Command} {at91sam9 cle} num addr_line
8420 Configure the address line used for latching commands. The @var{num}
8421 parameter is the value shown by @command{nand list}.
8423 @deffn {Config Command} {at91sam9 ale} num addr_line
8424 Configure the address line used for latching addresses. The @var{num}
8425 parameter is the value shown by @command{nand list}.
8428 For the next two commands, it is assumed that the pins have already been
8429 properly configured for input or output.
8430 @deffn {Config Command} {at91sam9 rdy_busy} num pio_base_addr pin
8431 Configure the RDY/nBUSY input from the NAND device. The @var{num}
8432 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8433 is the base address of the PIO controller and @var{pin} is the pin number.
8435 @deffn {Config Command} {at91sam9 ce} num pio_base_addr pin
8436 Configure the chip enable input to the NAND device. The @var{num}
8437 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8438 is the base address of the PIO controller and @var{pin} is the pin number.
8442 @deffn {NAND Driver} {davinci}
8443 This driver handles the NAND controllers found on DaVinci family
8444 chips from Texas Instruments.
8445 It takes three extra parameters:
8446 address of the NAND chip;
8447 hardware ECC mode to use (@option{hwecc1},
8448 @option{hwecc4}, @option{hwecc4_infix});
8449 address of the AEMIF controller on this processor.
8451 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
8453 All DaVinci processors support the single-bit ECC hardware,
8454 and newer ones also support the four-bit ECC hardware.
8455 The @code{write_page} and @code{read_page} methods are used
8456 to implement those ECC modes, unless they are disabled using
8457 the @command{nand raw_access} command.
8460 @deffn {NAND Driver} {lpc3180}
8461 These controllers require an extra @command{nand device}
8462 parameter: the clock rate used by the controller.
8463 @deffn {Command} {lpc3180 select} num [mlc|slc]
8464 Configures use of the MLC or SLC controller mode.
8465 MLC implies use of hardware ECC.
8466 The @var{num} parameter is the value shown by @command{nand list}.
8469 At this writing, this driver includes @code{write_page}
8470 and @code{read_page} methods. Using @command{nand raw_access}
8471 to disable those methods will prevent use of hardware ECC
8472 in the MLC controller mode, but won't change SLC behavior.
8474 @comment current lpc3180 code won't issue 5-byte address cycles
8476 @deffn {NAND Driver} {mx3}
8477 This driver handles the NAND controller in i.MX31. The mxc driver
8478 should work for this chip as well.
8481 @deffn {NAND Driver} {mxc}
8482 This driver handles the NAND controller found in Freescale i.MX
8483 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
8484 The driver takes 3 extra arguments, chip (@option{mx27},
8485 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
8486 and optionally if bad block information should be swapped between
8487 main area and spare area (@option{biswap}), defaults to off.
8489 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
8491 @deffn {Command} {mxc biswap} bank_num [enable|disable]
8492 Turns on/off bad block information swapping from main area,
8493 without parameter query status.
8497 @deffn {NAND Driver} {orion}
8498 These controllers require an extra @command{nand device}
8499 parameter: the address of the controller.
8501 nand device orion 0xd8000000
8503 These controllers don't define any specialized commands.
8504 At this writing, their drivers don't include @code{write_page}
8505 or @code{read_page} methods, so @command{nand raw_access} won't
8506 change any behavior.
8509 @deffn {NAND Driver} {s3c2410}
8510 @deffnx {NAND Driver} {s3c2412}
8511 @deffnx {NAND Driver} {s3c2440}
8512 @deffnx {NAND Driver} {s3c2443}
8513 @deffnx {NAND Driver} {s3c6400}
8514 These S3C family controllers don't have any special
8515 @command{nand device} options, and don't define any
8516 specialized commands.
8517 At this writing, their drivers don't include @code{write_page}
8518 or @code{read_page} methods, so @command{nand raw_access} won't
8519 change any behavior.
8522 @node Flash Programming
8523 @chapter Flash Programming
8525 OpenOCD implements numerous ways to program the target flash, whether internal or external.
8526 Programming can be achieved by either using @ref{programmingusinggdb,,Programming using GDB},
8527 or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
8529 @*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage.
8530 OpenOCD will program/verify/reset the target and optionally shutdown.
8532 The script is executed as follows and by default the following actions will be performed.
8534 @item 'init' is executed.
8535 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
8536 @item @code{flash write_image} is called to erase and write any flash using the filename given.
8537 @item If the @option{preverify} parameter is given, the target is "verified" first and only flashed if this fails.
8538 @item @code{verify_image} is called if @option{verify} parameter is given.
8539 @item @code{reset run} is called if @option{reset} parameter is given.
8540 @item OpenOCD is shutdown if @option{exit} parameter is given.
8543 An example of usage is given below. @xref{program}.
8546 # program and verify using elf/hex/s19. verify and reset
8547 # are optional parameters
8548 openocd -f board/stm32f3discovery.cfg \
8549 -c "program filename.elf verify reset exit"
8551 # binary files need the flash address passing
8552 openocd -f board/stm32f3discovery.cfg \
8553 -c "program filename.bin exit 0x08000000"
8556 @node PLD/FPGA Commands
8557 @chapter PLD/FPGA Commands
8561 Programmable Logic Devices (PLDs) and the more flexible
8562 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
8563 OpenOCD can support programming them.
8564 Although PLDs are generally restrictive (cells are less functional, and
8565 there are no special purpose cells for memory or computational tasks),
8566 they share the same OpenOCD infrastructure.
8567 Accordingly, both are called PLDs here.
8569 @section PLD/FPGA Configuration and Commands
8571 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
8572 OpenOCD maintains a list of PLDs available for use in various commands.
8573 Also, each such PLD requires a driver.
8575 They are referenced by the number shown by the @command{pld devices} command,
8576 and new PLDs are defined by @command{pld device driver_name}.
8578 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
8579 Defines a new PLD device, supported by driver @var{driver_name},
8580 using the TAP named @var{tap_name}.
8581 The driver may make use of any @var{driver_options} to configure its
8585 @deffn {Command} {pld devices}
8586 Lists the PLDs and their numbers.
8589 @deffn {Command} {pld load} num filename
8590 Loads the file @file{filename} into the PLD identified by @var{num}.
8591 The file format must be inferred by the driver.
8594 @section PLD/FPGA Drivers, Options, and Commands
8596 Drivers may support PLD-specific options to the @command{pld device}
8597 definition command, and may also define commands usable only with
8598 that particular type of PLD.
8600 @deffn {FPGA Driver} {virtex2} [no_jstart]
8601 Virtex-II is a family of FPGAs sold by Xilinx.
8602 It supports the IEEE 1532 standard for In-System Configuration (ISC).
8604 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
8605 loading the bitstream. While required for Series2, Series3, and Series6, it
8606 breaks bitstream loading on Series7.
8608 @deffn {Command} {virtex2 read_stat} num
8609 Reads and displays the Virtex-II status register (STAT)
8614 @node General Commands
8615 @chapter General Commands
8618 The commands documented in this chapter here are common commands that
8619 you, as a human, may want to type and see the output of. Configuration type
8620 commands are documented elsewhere.
8624 @item @b{Source Of Commands}
8625 @* OpenOCD commands can occur in a configuration script (discussed
8626 elsewhere) or typed manually by a human or supplied programmatically,
8627 or via one of several TCP/IP Ports.
8629 @item @b{From the human}
8630 @* A human should interact with the telnet interface (default port: 4444)
8631 or via GDB (default port 3333).
8633 To issue commands from within a GDB session, use the @option{monitor}
8634 command, e.g. use @option{monitor poll} to issue the @option{poll}
8635 command. All output is relayed through the GDB session.
8637 @item @b{Machine Interface}
8638 The Tcl interface's intent is to be a machine interface. The default Tcl
8643 @section Server Commands
8645 @deffn {Command} {exit}
8646 Exits the current telnet session.
8649 @deffn {Command} {help} [string]
8650 With no parameters, prints help text for all commands.
8651 Otherwise, prints each helptext containing @var{string}.
8652 Not every command provides helptext.
8654 Configuration commands, and commands valid at any time, are
8655 explicitly noted in parenthesis.
8656 In most cases, no such restriction is listed; this indicates commands
8657 which are only available after the configuration stage has completed.
8660 @deffn {Command} {usage} [string]
8661 With no parameters, prints usage text for all commands. Otherwise,
8662 prints all usage text of which command, help text, and usage text
8663 containing @var{string}.
8664 Not every command provides helptext.
8667 @deffn {Command} {sleep} msec [@option{busy}]
8668 Wait for at least @var{msec} milliseconds before resuming.
8669 If @option{busy} is passed, busy-wait instead of sleeping.
8670 (This option is strongly discouraged.)
8671 Useful in connection with script files
8672 (@command{script} command and @command{target_name} configuration).
8675 @deffn {Command} {shutdown} [@option{error}]
8676 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
8677 other). If option @option{error} is used, OpenOCD will return a
8678 non-zero exit code to the parent process.
8680 If user types CTRL-C or kills OpenOCD, the command @command{shutdown}
8681 will be automatically executed to cause OpenOCD to exit.
8683 It is possible to specify, in the TCL list @var{pre_shutdown_commands} , a
8684 set of commands to be automatically executed before @command{shutdown} , e.g.:
8686 lappend pre_shutdown_commands @{echo "Goodbye, my friend ..."@}
8687 lappend pre_shutdown_commands @{echo "see you soon !"@}
8689 The commands in the list will be executed (in the same order they occupy
8690 in the list) before OpenOCD exits. If one of the commands in the list
8691 fails, then the remaining commands are not executed anymore while OpenOCD
8692 will proceed to quit.
8696 @deffn {Command} {debug_level} [n]
8697 @cindex message level
8698 Display debug level.
8699 If @var{n} (from 0..4) is provided, then set it to that level.
8700 This affects the kind of messages sent to the server log.
8701 Level 0 is error messages only;
8702 level 1 adds warnings;
8703 level 2 adds informational messages;
8704 level 3 adds debugging messages;
8705 and level 4 adds verbose low-level debug messages.
8706 The default is level 2, but that can be overridden on
8707 the command line along with the location of that log
8708 file (which is normally the server's standard output).
8712 @deffn {Command} {echo} [-n] message
8713 Logs a message at "user" priority.
8714 Option "-n" suppresses trailing newline.
8716 echo "Downloading kernel -- please wait"
8720 @deffn {Command} {log_output} [filename | "default"]
8721 Redirect logging to @var{filename} or set it back to default output;
8722 the default log output channel is stderr.
8725 @deffn {Command} {add_script_search_dir} [directory]
8726 Add @var{directory} to the file/script search path.
8729 @deffn {Config Command} {bindto} [@var{name}]
8730 Specify hostname or IPv4 address on which to listen for incoming
8731 TCP/IP connections. By default, OpenOCD will listen on the loopback
8732 interface only. If your network environment is safe, @code{bindto
8733 0.0.0.0} can be used to cover all available interfaces.
8736 @anchor{targetstatehandling}
8737 @section Target State handling
8740 @cindex target initialization
8742 In this section ``target'' refers to a CPU configured as
8743 shown earlier (@pxref{CPU Configuration}).
8744 These commands, like many, implicitly refer to
8745 a current target which is used to perform the
8746 various operations. The current target may be changed
8747 by using @command{targets} command with the name of the
8748 target which should become current.
8750 @deffn {Command} {reg} [(number|name) [(value|'force')]]
8751 Access a single register by @var{number} or by its @var{name}.
8752 The target must generally be halted before access to CPU core
8753 registers is allowed. Depending on the hardware, some other
8754 registers may be accessible while the target is running.
8756 @emph{With no arguments}:
8757 list all available registers for the current target,
8758 showing number, name, size, value, and cache status.
8759 For valid entries, a value is shown; valid entries
8760 which are also dirty (and will be written back later)
8761 are flagged as such.
8763 @emph{With number/name}: display that register's value.
8764 Use @var{force} argument to read directly from the target,
8765 bypassing any internal cache.
8767 @emph{With both number/name and value}: set register's value.
8768 Writes may be held in a writeback cache internal to OpenOCD,
8769 so that setting the value marks the register as dirty instead
8770 of immediately flushing that value. Resuming CPU execution
8771 (including by single stepping) or otherwise activating the
8772 relevant module will flush such values.
8774 Cores may have surprisingly many registers in their
8775 Debug and trace infrastructure:
8780 (0) r0 (/32): 0x0000D3C2 (dirty)
8781 (1) r1 (/32): 0xFD61F31C
8784 (164) ETM_contextid_comparator_mask (/32)
8789 @deffn {Command} {set_reg} dict
8790 Set register values of the target.
8793 @item @var{dict} ... Tcl dictionary with pairs of register names and values.
8796 For example, the following command sets the value 0 to the program counter (pc)
8797 register and 0x1000 to the stack pointer (sp) register:
8800 set_reg @{pc 0 sp 0x1000@}
8804 @deffn {Command} {get_reg} [-force] list
8805 Get register values from the target and return them as Tcl dictionary with pairs
8806 of register names and values.
8807 If option "-force" is set, the register values are read directly from the
8808 target, bypassing any caching.
8811 @item @var{list} ... List of register names
8814 For example, the following command retrieves the values from the program
8815 counter (pc) and stack pointer (sp) register:
8822 @deffn {Command} {write_memory} address width data ['phys']
8823 This function provides an efficient way to write to the target memory from a Tcl
8827 @item @var{address} ... target memory address
8828 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
8829 @item @var{data} ... Tcl list with the elements to write
8830 @item ['phys'] ... treat the memory address as physical instead of virtual address
8833 For example, the following command writes two 32 bit words into the target
8834 memory at address 0x20000000:
8837 write_memory 0x20000000 32 @{0xdeadbeef 0x00230500@}
8841 @deffn {Command} {read_memory} address width count ['phys']
8842 This function provides an efficient way to read the target memory from a Tcl
8844 A Tcl list containing the requested memory elements is returned by this function.
8847 @item @var{address} ... target memory address
8848 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
8849 @item @var{count} ... number of elements to read
8850 @item ['phys'] ... treat the memory address as physical instead of virtual address
8853 For example, the following command reads two 32 bit words from the target
8854 memory at address 0x20000000:
8857 read_memory 0x20000000 32 2
8861 @deffn {Command} {halt} [ms]
8862 @deffnx {Command} {wait_halt} [ms]
8863 The @command{halt} command first sends a halt request to the target,
8864 which @command{wait_halt} doesn't.
8865 Otherwise these behave the same: wait up to @var{ms} milliseconds,
8866 or 5 seconds if there is no parameter, for the target to halt
8867 (and enter debug mode).
8868 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
8871 On ARM cores, software using the @emph{wait for interrupt} operation
8872 often blocks the JTAG access needed by a @command{halt} command.
8873 This is because that operation also puts the core into a low
8874 power mode by gating the core clock;
8875 but the core clock is needed to detect JTAG clock transitions.
8877 One partial workaround uses adaptive clocking: when the core is
8878 interrupted the operation completes, then JTAG clocks are accepted
8879 at least until the interrupt handler completes.
8880 However, this workaround is often unusable since the processor, board,
8881 and JTAG adapter must all support adaptive JTAG clocking.
8882 Also, it can't work until an interrupt is issued.
8884 A more complete workaround is to not use that operation while you
8885 work with a JTAG debugger.
8886 Tasking environments generally have idle loops where the body is the
8887 @emph{wait for interrupt} operation.
8888 (On older cores, it is a coprocessor action;
8889 newer cores have a @option{wfi} instruction.)
8890 Such loops can just remove that operation, at the cost of higher
8891 power consumption (because the CPU is needlessly clocked).
8896 @deffn {Command} {resume} [address]
8897 Resume the target at its current code position,
8898 or the optional @var{address} if it is provided.
8899 OpenOCD will wait 5 seconds for the target to resume.
8902 @deffn {Command} {step} [address]
8903 Single-step the target at its current code position,
8904 or the optional @var{address} if it is provided.
8907 @anchor{resetcommand}
8908 @deffn {Command} {reset}
8909 @deffnx {Command} {reset run}
8910 @deffnx {Command} {reset halt}
8911 @deffnx {Command} {reset init}
8912 Perform as hard a reset as possible, using SRST if possible.
8913 @emph{All defined targets will be reset, and target
8914 events will fire during the reset sequence.}
8916 The optional parameter specifies what should
8917 happen after the reset.
8918 If there is no parameter, a @command{reset run} is executed.
8919 The other options will not work on all systems.
8920 @xref{Reset Configuration}.
8923 @item @b{run} Let the target run
8924 @item @b{halt} Immediately halt the target
8925 @item @b{init} Immediately halt the target, and execute the reset-init script
8929 @deffn {Command} {soft_reset_halt}
8930 Requesting target halt and executing a soft reset. This is often used
8931 when a target cannot be reset and halted. The target, after reset is
8932 released begins to execute code. OpenOCD attempts to stop the CPU and
8933 then sets the program counter back to the reset vector. Unfortunately
8934 the code that was executed may have left the hardware in an unknown
8938 @deffn {Command} {adapter assert} [signal [assert|deassert signal]]
8939 @deffnx {Command} {adapter deassert} [signal [assert|deassert signal]]
8940 Set values of reset signals.
8941 Without parameters returns current status of the signals.
8942 The @var{signal} parameter values may be
8943 @option{srst}, indicating that srst signal is to be asserted or deasserted,
8944 @option{trst}, indicating that trst signal is to be asserted or deasserted.
8946 The @command{reset_config} command should already have been used
8947 to configure how the board and the adapter treat these two
8948 signals, and to say if either signal is even present.
8949 @xref{Reset Configuration}.
8950 Trying to assert a signal that is not present triggers an error.
8951 If a signal is present on the adapter and not specified in the command,
8952 the signal will not be modified.
8955 TRST is specially handled.
8956 It actually signifies JTAG's @sc{reset} state.
8957 So if the board doesn't support the optional TRST signal,
8958 or it doesn't support it along with the specified SRST value,
8959 JTAG reset is triggered with TMS and TCK signals
8960 instead of the TRST signal.
8961 And no matter how that JTAG reset is triggered, once
8962 the scan chain enters @sc{reset} with TRST inactive,
8963 TAP @code{post-reset} events are delivered to all TAPs
8964 with handlers for that event.
8968 @anchor{memoryaccess}
8969 @section Memory access commands
8970 @cindex memory access
8972 These commands allow accesses of a specific size to the memory
8973 system. Often these are used to configure the current target in some
8974 special way. For example - one may need to write certain values to the
8975 SDRAM controller to enable SDRAM.
8978 @item Use the @command{targets} (plural) command
8979 to change the current target.
8980 @item In system level scripts these commands are deprecated.
8981 Please use their TARGET object siblings to avoid making assumptions
8982 about what TAP is the current target, or about MMU configuration.
8985 @deffn {Command} {mdd} [phys] addr [count]
8986 @deffnx {Command} {mdw} [phys] addr [count]
8987 @deffnx {Command} {mdh} [phys] addr [count]
8988 @deffnx {Command} {mdb} [phys] addr [count]
8989 Display contents of address @var{addr}, as
8990 64-bit doublewords (@command{mdd}),
8991 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
8992 or 8-bit bytes (@command{mdb}).
8993 When the current target has an MMU which is present and active,
8994 @var{addr} is interpreted as a virtual address.
8995 Otherwise, or if the optional @var{phys} flag is specified,
8996 @var{addr} is interpreted as a physical address.
8997 If @var{count} is specified, displays that many units.
8998 (If you want to process the data instead of displaying it,
8999 see the @code{read_memory} primitives.)
9002 @deffn {Command} {mwd} [phys] addr doubleword [count]
9003 @deffnx {Command} {mww} [phys] addr word [count]
9004 @deffnx {Command} {mwh} [phys] addr halfword [count]
9005 @deffnx {Command} {mwb} [phys] addr byte [count]
9006 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
9007 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
9008 at the specified address @var{addr}.
9009 When the current target has an MMU which is present and active,
9010 @var{addr} is interpreted as a virtual address.
9011 Otherwise, or if the optional @var{phys} flag is specified,
9012 @var{addr} is interpreted as a physical address.
9013 If @var{count} is specified, fills that many units of consecutive address.
9016 @anchor{imageaccess}
9017 @section Image loading commands
9018 @cindex image loading
9019 @cindex image dumping
9021 @deffn {Command} {dump_image} filename address size
9022 Dump @var{size} bytes of target memory starting at @var{address} to the
9023 binary file named @var{filename}.
9026 @deffn {Command} {fast_load}
9027 Loads an image stored in memory by @command{fast_load_image} to the
9028 current target. Must be preceded by fast_load_image.
9031 @deffn {Command} {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
9032 Normally you should be using @command{load_image} or GDB load. However, for
9033 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
9034 host), storing the image in memory and uploading the image to the target
9035 can be a way to upload e.g. multiple debug sessions when the binary does not change.
9036 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
9037 memory, i.e. does not affect target. This approach is also useful when profiling
9038 target programming performance as I/O and target programming can easily be profiled
9042 @deffn {Command} {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
9043 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
9044 The file format may optionally be specified
9045 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
9046 In addition the following arguments may be specified:
9047 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
9048 @var{max_length} - maximum number of bytes to load.
9050 proc load_image_bin @{fname foffset address length @} @{
9051 # Load data from fname filename at foffset offset to
9052 # target at address. Load at most length bytes.
9053 load_image $fname [expr @{$address - $foffset@}] bin \
9059 @deffn {Command} {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
9060 Displays image section sizes and addresses
9061 as if @var{filename} were loaded into target memory
9062 starting at @var{address} (defaults to zero).
9063 The file format may optionally be specified
9064 (@option{bin}, @option{ihex}, or @option{elf})
9067 @deffn {Command} {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
9068 Verify @var{filename} against target memory starting at @var{address}.
9069 The file format may optionally be specified
9070 (@option{bin}, @option{ihex}, or @option{elf})
9071 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
9074 @deffn {Command} {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
9075 Verify @var{filename} against target memory starting at @var{address}.
9076 The file format may optionally be specified
9077 (@option{bin}, @option{ihex}, or @option{elf})
9078 This perform a comparison using a CRC checksum only
9082 @section Breakpoint and Watchpoint commands
9086 CPUs often make debug modules accessible through JTAG, with
9087 hardware support for a handful of code breakpoints and data
9089 In addition, CPUs almost always support software breakpoints.
9091 @deffn {Command} {bp} [address len [@option{hw}]]
9092 With no parameters, lists all active breakpoints.
9093 Else sets a breakpoint on code execution starting
9094 at @var{address} for @var{length} bytes.
9095 This is a software breakpoint, unless @option{hw} is specified
9096 in which case it will be a hardware breakpoint.
9098 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
9099 for similar mechanisms that do not consume hardware breakpoints.)
9102 @deffn {Command} {rbp} @option{all} | address
9103 Remove the breakpoint at @var{address} or all breakpoints.
9106 @deffn {Command} {rwp} address
9107 Remove data watchpoint on @var{address}
9110 @deffn {Command} {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
9111 With no parameters, lists all active watchpoints.
9112 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
9113 The watch point is an "access" watchpoint unless
9114 the @option{r} or @option{w} parameter is provided,
9115 defining it as respectively a read or write watchpoint.
9116 If a @var{value} is provided, that value is used when determining if
9117 the watchpoint should trigger. The value may be first be masked
9118 using @var{mask} to mark ``don't care'' fields.
9122 @section Real Time Transfer (RTT)
9124 Real Time Transfer (RTT) is an interface specified by SEGGER based on basic
9125 memory reads and writes to transfer data bidirectionally between target and host.
9126 The specification is independent of the target architecture.
9127 Every target that supports so called "background memory access", which means
9128 that the target memory can be accessed by the debugger while the target is
9129 running, can be used.
9130 This interface is especially of interest for targets without
9131 Serial Wire Output (SWO), such as ARM Cortex-M0, or where semihosting is not
9132 applicable because of real-time constraints.
9135 The current implementation supports only single target devices.
9138 The data transfer between host and target device is organized through
9139 unidirectional up/down-channels for target-to-host and host-to-target
9140 communication, respectively.
9143 The current implementation does not respect channel buffer flags.
9144 They are used to determine what happens when writing to a full buffer, for
9148 Channels are exposed via raw TCP/IP connections. One or more RTT servers can be
9149 assigned to each channel to make them accessible to an unlimited number
9150 of TCP/IP connections.
9152 @deffn {Command} {rtt setup} address size ID
9153 Configure RTT for the currently selected target.
9154 Once RTT is started, OpenOCD searches for a control block with the
9155 identifier @var{ID} starting at the memory address @var{address} within the next
9159 @deffn {Command} {rtt start}
9161 If the control block location is not known, OpenOCD starts searching for it.
9164 @deffn {Command} {rtt stop}
9168 @deffn {Command} {rtt polling_interval} [interval]
9169 Display the polling interval.
9170 If @var{interval} is provided, set the polling interval.
9171 The polling interval determines (in milliseconds) how often the up-channels are
9172 checked for new data.
9175 @deffn {Command} {rtt channels}
9176 Display a list of all channels and their properties.
9179 @deffn {Command} {rtt channellist}
9180 Return a list of all channels and their properties as Tcl list.
9181 The list can be manipulated easily from within scripts.
9184 @deffn {Command} {rtt server start} port channel
9185 Start a TCP server on @var{port} for the channel @var{channel}.
9188 @deffn {Command} {rtt server stop} port
9189 Stop the TCP sever with port @var{port}.
9192 The following example shows how to setup RTT using the SEGGER RTT implementation
9193 on the target device.
9198 rtt setup 0x20000000 2048 "SEGGER RTT"
9201 rtt server start 9090 0
9204 In this example, OpenOCD searches the control block with the ID "SEGGER RTT"
9205 starting at 0x20000000 for 2048 bytes. The RTT channel 0 is exposed through the
9209 @section Misc Commands
9212 @deffn {Command} {profile} seconds filename [start end]
9213 Profiling samples the CPU's program counter as quickly as possible,
9214 which is useful for non-intrusive stochastic profiling.
9215 Saves up to 10000 samples in @file{filename} using ``gmon.out''
9216 format. Optional @option{start} and @option{end} parameters allow to
9217 limit the address range.
9220 @deffn {Command} {version}
9221 Displays a string identifying the version of this OpenOCD server.
9224 @deffn {Command} {virt2phys} virtual_address
9225 Requests the current target to map the specified @var{virtual_address}
9226 to its corresponding physical address, and displays the result.
9229 @deffn {Command} {add_help_text} 'command_name' 'help-string'
9230 Add or replace help text on the given @var{command_name}.
9233 @deffn {Command} {add_usage_text} 'command_name' 'help-string'
9234 Add or replace usage text on the given @var{command_name}.
9237 @node Architecture and Core Commands
9238 @chapter Architecture and Core Commands
9239 @cindex Architecture Specific Commands
9240 @cindex Core Specific Commands
9242 Most CPUs have specialized JTAG operations to support debugging.
9243 OpenOCD packages most such operations in its standard command framework.
9244 Some of those operations don't fit well in that framework, so they are
9245 exposed here as architecture or implementation (core) specific commands.
9247 @anchor{armhardwaretracing}
9248 @section ARM Hardware Tracing
9253 CPUs based on ARM cores may include standard tracing interfaces,
9254 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
9255 address and data bus trace records to a ``Trace Port''.
9259 Development-oriented boards will sometimes provide a high speed
9260 trace connector for collecting that data, when the particular CPU
9261 supports such an interface.
9262 (The standard connector is a 38-pin Mictor, with both JTAG
9263 and trace port support.)
9264 Those trace connectors are supported by higher end JTAG adapters
9265 and some logic analyzer modules; frequently those modules can
9266 buffer several megabytes of trace data.
9267 Configuring an ETM coupled to such an external trace port belongs
9268 in the board-specific configuration file.
9270 If the CPU doesn't provide an external interface, it probably
9271 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
9272 dedicated SRAM. 4KBytes is one common ETB size.
9273 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
9274 (target) configuration file, since it works the same on all boards.
9277 ETM support in OpenOCD doesn't seem to be widely used yet.
9280 ETM support may be buggy, and at least some @command{etm config}
9281 parameters should be detected by asking the ETM for them.
9283 ETM trigger events could also implement a kind of complex
9284 hardware breakpoint, much more powerful than the simple
9285 watchpoint hardware exported by EmbeddedICE modules.
9286 @emph{Such breakpoints can be triggered even when using the
9287 dummy trace port driver}.
9289 It seems like a GDB hookup should be possible,
9290 as well as tracing only during specific states
9291 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
9293 There should be GUI tools to manipulate saved trace data and help
9294 analyse it in conjunction with the source code.
9295 It's unclear how much of a common interface is shared
9296 with the current XScale trace support, or should be
9297 shared with eventual Nexus-style trace module support.
9299 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
9300 for ETM modules is available. The code should be able to
9301 work with some newer cores; but not all of them support
9302 this original style of JTAG access.
9305 @subsection ETM Configuration
9306 ETM setup is coupled with the trace port driver configuration.
9308 @deffn {Config Command} {etm config} target width mode clocking driver
9309 Declares the ETM associated with @var{target}, and associates it
9310 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
9312 Several of the parameters must reflect the trace port capabilities,
9313 which are a function of silicon capabilities (exposed later
9314 using @command{etm info}) and of what hardware is connected to
9315 that port (such as an external pod, or ETB).
9316 The @var{width} must be either 4, 8, or 16,
9317 except with ETMv3.0 and newer modules which may also
9318 support 1, 2, 24, 32, 48, and 64 bit widths.
9319 (With those versions, @command{etm info} also shows whether
9320 the selected port width and mode are supported.)
9322 The @var{mode} must be @option{normal}, @option{multiplexed},
9323 or @option{demultiplexed}.
9324 The @var{clocking} must be @option{half} or @option{full}.
9327 With ETMv3.0 and newer, the bits set with the @var{mode} and
9328 @var{clocking} parameters both control the mode.
9329 This modified mode does not map to the values supported by
9330 previous ETM modules, so this syntax is subject to change.
9334 You can see the ETM registers using the @command{reg} command.
9335 Not all possible registers are present in every ETM.
9336 Most of the registers are write-only, and are used to configure
9337 what CPU activities are traced.
9341 @deffn {Command} {etm info}
9342 Displays information about the current target's ETM.
9343 This includes resource counts from the @code{ETM_CONFIG} register,
9344 as well as silicon capabilities (except on rather old modules).
9345 from the @code{ETM_SYS_CONFIG} register.
9348 @deffn {Command} {etm status}
9349 Displays status of the current target's ETM and trace port driver:
9350 is the ETM idle, or is it collecting data?
9351 Did trace data overflow?
9355 @deffn {Command} {etm tracemode} [type context_id_bits cycle_accurate branch_output]
9356 Displays what data that ETM will collect.
9357 If arguments are provided, first configures that data.
9358 When the configuration changes, tracing is stopped
9359 and any buffered trace data is invalidated.
9362 @item @var{type} ... describing how data accesses are traced,
9363 when they pass any ViewData filtering that was set up.
9365 @option{none} (save nothing),
9366 @option{data} (save data),
9367 @option{address} (save addresses),
9368 @option{all} (save data and addresses)
9369 @item @var{context_id_bits} ... 0, 8, 16, or 32
9370 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
9371 cycle-accurate instruction tracing.
9372 Before ETMv3, enabling this causes much extra data to be recorded.
9373 @item @var{branch_output} ... @option{enable} or @option{disable}.
9374 Disable this unless you need to try reconstructing the instruction
9375 trace stream without an image of the code.
9379 @deffn {Command} {etm trigger_debug} (@option{enable}|@option{disable})
9380 Displays whether ETM triggering debug entry (like a breakpoint) is
9381 enabled or disabled, after optionally modifying that configuration.
9382 The default behaviour is @option{disable}.
9383 Any change takes effect after the next @command{etm start}.
9385 By using script commands to configure ETM registers, you can make the
9386 processor enter debug state automatically when certain conditions,
9387 more complex than supported by the breakpoint hardware, happen.
9390 @subsection ETM Trace Operation
9392 After setting up the ETM, you can use it to collect data.
9393 That data can be exported to files for later analysis.
9394 It can also be parsed with OpenOCD, for basic sanity checking.
9396 To configure what is being traced, you will need to write
9397 various trace registers using @command{reg ETM_*} commands.
9398 For the definitions of these registers, read ARM publication
9399 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
9400 Be aware that most of the relevant registers are write-only,
9401 and that ETM resources are limited. There are only a handful
9402 of address comparators, data comparators, counters, and so on.
9404 Examples of scenarios you might arrange to trace include:
9407 @item Code flow within a function, @emph{excluding} subroutines
9408 it calls. Use address range comparators to enable tracing
9409 for instruction access within that function's body.
9410 @item Code flow within a function, @emph{including} subroutines
9411 it calls. Use the sequencer and address comparators to activate
9412 tracing on an ``entered function'' state, then deactivate it by
9413 exiting that state when the function's exit code is invoked.
9414 @item Code flow starting at the fifth invocation of a function,
9415 combining one of the above models with a counter.
9416 @item CPU data accesses to the registers for a particular device,
9417 using address range comparators and the ViewData logic.
9418 @item Such data accesses only during IRQ handling, combining the above
9419 model with sequencer triggers which on entry and exit to the IRQ handler.
9420 @item @emph{... more}
9423 At this writing, September 2009, there are no Tcl utility
9424 procedures to help set up any common tracing scenarios.
9426 @deffn {Command} {etm analyze}
9427 Reads trace data into memory, if it wasn't already present.
9428 Decodes and prints the data that was collected.
9431 @deffn {Command} {etm dump} filename
9432 Stores the captured trace data in @file{filename}.
9435 @deffn {Command} {etm image} filename [base_address] [type]
9436 Opens an image file.
9439 @deffn {Command} {etm load} filename
9440 Loads captured trace data from @file{filename}.
9443 @deffn {Command} {etm start}
9444 Starts trace data collection.
9447 @deffn {Command} {etm stop}
9448 Stops trace data collection.
9451 @anchor{traceportdrivers}
9452 @subsection Trace Port Drivers
9454 To use an ETM trace port it must be associated with a driver.
9456 @deffn {Trace Port Driver} {dummy}
9457 Use the @option{dummy} driver if you are configuring an ETM that's
9458 not connected to anything (on-chip ETB or off-chip trace connector).
9459 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
9460 any trace data collection.}
9461 @deffn {Config Command} {etm_dummy config} target
9462 Associates the ETM for @var{target} with a dummy driver.
9466 @deffn {Trace Port Driver} {etb}
9467 Use the @option{etb} driver if you are configuring an ETM
9468 to use on-chip ETB memory.
9469 @deffn {Config Command} {etb config} target etb_tap
9470 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
9471 You can see the ETB registers using the @command{reg} command.
9473 @deffn {Command} {etb trigger_percent} [percent]
9474 This displays, or optionally changes, ETB behavior after the
9475 ETM's configured @emph{trigger} event fires.
9476 It controls how much more trace data is saved after the (single)
9477 trace trigger becomes active.
9480 @item The default corresponds to @emph{trace around} usage,
9481 recording 50 percent data before the event and the rest
9483 @item The minimum value of @var{percent} is 2 percent,
9484 recording almost exclusively data before the trigger.
9485 Such extreme @emph{trace before} usage can help figure out
9486 what caused that event to happen.
9487 @item The maximum value of @var{percent} is 100 percent,
9488 recording data almost exclusively after the event.
9489 This extreme @emph{trace after} usage might help sort out
9490 how the event caused trouble.
9492 @c REVISIT allow "break" too -- enter debug mode.
9497 @anchor{armcrosstrigger}
9498 @section ARM Cross-Trigger Interface
9501 The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
9502 that connects event sources like tracing components or CPU cores with each
9503 other through a common trigger matrix (CTM). For ARMv8 architecture, a
9504 CTI is mandatory for core run control and each core has an individual
9505 CTI instance attached to it. OpenOCD has limited support for CTI using
9506 the @emph{cti} group of commands.
9508 @deffn {Command} {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-baseaddr} base_address
9509 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
9511 On ADIv5 DAP @var{apn} is the numeric index of the DAP AP the CTI is connected to.
9512 On ADIv6 DAP @var{apn} is the base address of the DAP AP the CTI is connected to.
9513 The @var{base_address} must match the base address of the CTI
9514 on the respective MEM-AP. All arguments are mandatory. This creates a
9515 new command @command{$cti_name} which is used for various purposes
9516 including additional configuration.
9519 @deffn {Command} {$cti_name enable} @option{on|off}
9520 Enable (@option{on}) or disable (@option{off}) the CTI.
9523 @deffn {Command} {$cti_name dump}
9524 Displays a register dump of the CTI.
9527 @deffn {Command} {$cti_name write} @var{reg_name} @var{value}
9528 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
9531 @deffn {Command} {$cti_name read} @var{reg_name}
9532 Print the value read from the CTI register with the symbolic name @var{reg_name}.
9535 @deffn {Command} {$cti_name ack} @var{event}
9536 Acknowledge a CTI @var{event}.
9539 @deffn {Command} {$cti_name channel} @var{channel_number} @var{operation}
9540 Perform a specific channel operation, the possible operations are:
9541 gate, ungate, set, clear and pulse
9544 @deffn {Command} {$cti_name testmode} @option{on|off}
9545 Enable (@option{on}) or disable (@option{off}) the integration test mode
9549 @deffn {Command} {cti names}
9550 Prints a list of names of all CTI objects created. This command is mainly
9551 useful in TCL scripting.
9554 @section Generic ARM
9557 These commands should be available on all ARM processors.
9558 They are available in addition to other core-specific
9559 commands that may be available.
9561 @deffn {Command} {arm core_state} [@option{arm}|@option{thumb}]
9562 Displays the core_state, optionally changing it to process
9563 either @option{arm} or @option{thumb} instructions.
9564 The target may later be resumed in the currently set core_state.
9565 (Processors may also support the Jazelle state, but
9566 that is not currently supported in OpenOCD.)
9569 @deffn {Command} {arm disassemble} address [count [@option{thumb}]]
9571 Disassembles @var{count} instructions starting at @var{address}.
9572 If @var{count} is not specified, a single instruction is disassembled.
9573 If @option{thumb} is specified, or the low bit of the address is set,
9574 Thumb2 (mixed 16/32-bit) instructions are used;
9575 else ARM (32-bit) instructions are used.
9576 (Processors may also support the Jazelle state, but
9577 those instructions are not currently understood by OpenOCD.)
9579 Note that all Thumb instructions are Thumb2 instructions,
9580 so older processors (without Thumb2 support) will still
9581 see correct disassembly of Thumb code.
9582 Also, ThumbEE opcodes are the same as Thumb2,
9583 with a handful of exceptions.
9584 ThumbEE disassembly currently has no explicit support.
9587 @deffn {Command} {arm mcr} pX op1 CRn CRm op2 value
9588 Write @var{value} to a coprocessor @var{pX} register
9589 passing parameters @var{CRn},
9590 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9591 and using the MCR instruction.
9592 (Parameter sequence matches the ARM instruction, but omits
9596 @deffn {Command} {arm mrc} pX coproc op1 CRn CRm op2
9597 Read a coprocessor @var{pX} register passing parameters @var{CRn},
9598 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9599 and the MRC instruction.
9600 Returns the result so it can be manipulated by Jim scripts.
9601 (Parameter sequence matches the ARM instruction, but omits
9605 @deffn {Command} {arm reg}
9606 Display a table of all banked core registers, fetching the current value from every
9607 core mode if necessary.
9610 @deffn {Command} {arm semihosting} [@option{enable}|@option{disable}]
9611 @cindex ARM semihosting
9612 Display status of semihosting, after optionally changing that status.
9614 Semihosting allows for code executing on an ARM target to use the
9615 I/O facilities on the host computer i.e. the system where OpenOCD
9616 is running. The target application must be linked against a library
9617 implementing the ARM semihosting convention that forwards operation
9618 requests by using a special SVC instruction that is trapped at the
9619 Supervisor Call vector by OpenOCD.
9622 @deffn {Command} {arm semihosting_redirect} (@option{disable} | @option{tcp} <port>
9623 [@option{debug}|@option{stdio}|@option{all})
9624 @cindex ARM semihosting
9625 Redirect semihosting messages to a specified TCP port.
9627 This command redirects debug (READC, WRITEC and WRITE0) and stdio (READ, WRITE)
9628 semihosting operations to the specified TCP port.
9629 The command allows to select which type of operations to redirect (debug, stdio, all (default)).
9630 Note: for stdio operations, only I/O from/to ':tt' file descriptors are redirected.
9633 @deffn {Command} {arm semihosting_cmdline} [@option{enable}|@option{disable}]
9634 @cindex ARM semihosting
9635 Set the command line to be passed to the debugger.
9638 arm semihosting_cmdline argv0 argv1 argv2 ...
9641 This option lets one set the command line arguments to be passed to
9642 the program. The first argument (argv0) is the program name in a
9643 standard C environment (argv[0]). Depending on the program (not much
9644 programs look at argv[0]), argv0 is ignored and can be any string.
9647 @deffn {Command} {arm semihosting_fileio} [@option{enable}|@option{disable}]
9648 @cindex ARM semihosting
9649 Display status of semihosting fileio, after optionally changing that
9652 Enabling this option forwards semihosting I/O to GDB process using the
9653 File-I/O remote protocol extension. This is especially useful for
9654 interacting with remote files or displaying console messages in the
9658 @deffn {Command} {arm semihosting_resexit} [@option{enable}|@option{disable}]
9659 @cindex ARM semihosting
9660 Enable resumable SEMIHOSTING_SYS_EXIT.
9662 When SEMIHOSTING_SYS_EXIT is called outside a debug session,
9663 things are simple, the openocd process calls exit() and passes
9664 the value returned by the target.
9666 When SEMIHOSTING_SYS_EXIT is called during a debug session,
9667 by default execution returns to the debugger, leaving the
9668 debugger in a HALT state, similar to the state entered when
9669 encountering a break.
9671 In some use cases, it is useful to have SEMIHOSTING_SYS_EXIT
9672 return normally, as any semihosting call, and do not break
9674 The standard allows this to happen, but the condition
9675 to trigger it is a bit obscure ("by performing an RDI_Execute
9676 request or equivalent").
9678 To make the SEMIHOSTING_SYS_EXIT call return normally, enable
9679 this option (default: disabled).
9682 @deffn {Command} {arm semihosting_read_user_param}
9683 @cindex ARM semihosting
9684 Read parameter of the semihosting call from the target. Usable in
9685 semihosting-user-cmd-0x10* event handlers, returning a string.
9687 When the target makes semihosting call with operation number from range 0x100-
9688 0x107, an optional string parameter can be passed to the server. This parameter
9689 is valid during the run of the event handlers and is accessible with this
9693 @deffn {Command} {arm semihosting_basedir} [dir]
9694 @cindex ARM semihosting
9695 Set the base directory for semihosting I/O, either an absolute path or a path relative to OpenOCD working directory.
9696 Use "." for the current directory.
9699 @section ARMv4 and ARMv5 Architecture
9703 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
9704 and introduced core parts of the instruction set in use today.
9705 That includes the Thumb instruction set, introduced in the ARMv4T
9708 @subsection ARM7 and ARM9 specific commands
9712 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
9713 ARM9TDMI, ARM920T or ARM926EJ-S.
9714 They are available in addition to the ARM commands,
9715 and any other core-specific commands that may be available.
9717 @deffn {Command} {arm7_9 dbgrq} [@option{enable}|@option{disable}]
9718 Displays the value of the flag controlling use of the
9719 EmbeddedIce DBGRQ signal to force entry into debug mode,
9720 instead of breakpoints.
9721 If a boolean parameter is provided, first assigns that flag.
9724 safe for all but ARM7TDMI-S cores (like NXP LPC).
9725 This feature is enabled by default on most ARM9 cores,
9726 including ARM9TDMI, ARM920T, and ARM926EJ-S.
9729 @deffn {Command} {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
9731 Displays the value of the flag controlling use of the debug communications
9732 channel (DCC) to write larger (>128 byte) amounts of memory.
9733 If a boolean parameter is provided, first assigns that flag.
9735 DCC downloads offer a huge speed increase, but might be
9736 unsafe, especially with targets running at very low speeds. This command was introduced
9737 with OpenOCD rev. 60, and requires a few bytes of working area.
9740 @deffn {Command} {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
9741 Displays the value of the flag controlling use of memory writes and reads
9742 that don't check completion of the operation.
9743 If a boolean parameter is provided, first assigns that flag.
9745 This provides a huge speed increase, especially with USB JTAG
9746 cables (FT2232), but might be unsafe if used with targets running at very low
9747 speeds, like the 32kHz startup clock of an AT91RM9200.
9750 @subsection ARM9 specific commands
9753 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
9755 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
9757 @c 9-june-2009: tried this on arm920t, it didn't work.
9758 @c no-params always lists nothing caught, and that's how it acts.
9759 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
9760 @c versions have different rules about when they commit writes.
9762 @anchor{arm9vectorcatch}
9763 @deffn {Command} {arm9 vector_catch} [@option{all}|@option{none}|list]
9764 @cindex vector_catch
9765 Vector Catch hardware provides a sort of dedicated breakpoint
9766 for hardware events such as reset, interrupt, and abort.
9767 You can use this to conserve normal breakpoint resources,
9768 so long as you're not concerned with code that branches directly
9769 to those hardware vectors.
9771 This always finishes by listing the current configuration.
9772 If parameters are provided, it first reconfigures the
9773 vector catch hardware to intercept
9774 @option{all} of the hardware vectors,
9775 @option{none} of them,
9776 or a list with one or more of the following:
9777 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
9778 @option{irq} @option{fiq}.
9781 @subsection ARM920T specific commands
9784 These commands are available to ARM920T based CPUs,
9785 which are implementations of the ARMv4T architecture
9786 built using the ARM9TDMI integer core.
9787 They are available in addition to the ARM, ARM7/ARM9,
9790 @deffn {Command} {arm920t cache_info}
9791 Print information about the caches found. This allows to see whether your target
9792 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
9795 @deffn {Command} {arm920t cp15} regnum [value]
9796 Display cp15 register @var{regnum};
9797 else if a @var{value} is provided, that value is written to that register.
9798 This uses "physical access" and the register number is as
9799 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
9800 (Not all registers can be written.)
9803 @deffn {Command} {arm920t read_cache} filename
9804 Dump the content of ICache and DCache to a file named @file{filename}.
9807 @deffn {Command} {arm920t read_mmu} filename
9808 Dump the content of the ITLB and DTLB to a file named @file{filename}.
9811 @subsection ARM926ej-s specific commands
9814 These commands are available to ARM926ej-s based CPUs,
9815 which are implementations of the ARMv5TEJ architecture
9816 based on the ARM9EJ-S integer core.
9817 They are available in addition to the ARM, ARM7/ARM9,
9820 The Feroceon cores also support these commands, although
9821 they are not built from ARM926ej-s designs.
9823 @deffn {Command} {arm926ejs cache_info}
9824 Print information about the caches found.
9827 @subsection ARM966E specific commands
9830 These commands are available to ARM966 based CPUs,
9831 which are implementations of the ARMv5TE architecture.
9832 They are available in addition to the ARM, ARM7/ARM9,
9835 @deffn {Command} {arm966e cp15} regnum [value]
9836 Display cp15 register @var{regnum};
9837 else if a @var{value} is provided, that value is written to that register.
9838 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
9840 There is no current control over bits 31..30 from that table,
9841 as required for BIST support.
9844 @subsection XScale specific commands
9847 Some notes about the debug implementation on the XScale CPUs:
9849 The XScale CPU provides a special debug-only mini-instruction cache
9850 (mini-IC) in which exception vectors and target-resident debug handler
9851 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
9852 must point vector 0 (the reset vector) to the entry of the debug
9853 handler. However, this means that the complete first cacheline in the
9854 mini-IC is marked valid, which makes the CPU fetch all exception
9855 handlers from the mini-IC, ignoring the code in RAM.
9857 To address this situation, OpenOCD provides the @code{xscale
9858 vector_table} command, which allows the user to explicitly write
9859 individual entries to either the high or low vector table stored in
9862 It is recommended to place a pc-relative indirect branch in the vector
9863 table, and put the branch destination somewhere in memory. Doing so
9864 makes sure the code in the vector table stays constant regardless of
9865 code layout in memory:
9868 ldr pc,[pc,#0x100-8]
9869 ldr pc,[pc,#0x100-8]
9870 ldr pc,[pc,#0x100-8]
9871 ldr pc,[pc,#0x100-8]
9872 ldr pc,[pc,#0x100-8]
9873 ldr pc,[pc,#0x100-8]
9874 ldr pc,[pc,#0x100-8]
9875 ldr pc,[pc,#0x100-8]
9877 .long real_reset_vector
9878 .long real_ui_handler
9879 .long real_swi_handler
9881 .long real_data_abort
9882 .long 0 /* unused */
9883 .long real_irq_handler
9884 .long real_fiq_handler
9887 Alternatively, you may choose to keep some or all of the mini-IC
9888 vector table entries synced with those written to memory by your
9889 system software. The mini-IC can not be modified while the processor
9890 is executing, but for each vector table entry not previously defined
9891 using the @code{xscale vector_table} command, OpenOCD will copy the
9892 value from memory to the mini-IC every time execution resumes from a
9893 halt. This is done for both high and low vector tables (although the
9894 table not in use may not be mapped to valid memory, and in this case
9895 that copy operation will silently fail). This means that you will
9896 need to briefly halt execution at some strategic point during system
9897 start-up; e.g., after the software has initialized the vector table,
9898 but before exceptions are enabled. A breakpoint can be used to
9899 accomplish this once the appropriate location in the start-up code has
9900 been identified. A watchpoint over the vector table region is helpful
9901 in finding the location if you're not sure. Note that the same
9902 situation exists any time the vector table is modified by the system
9905 The debug handler must be placed somewhere in the address space using
9906 the @code{xscale debug_handler} command. The allowed locations for the
9907 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
9908 0xfffff800). The default value is 0xfe000800.
9910 XScale has resources to support two hardware breakpoints and two
9911 watchpoints. However, the following restrictions on watchpoint
9912 functionality apply: (1) the value and mask arguments to the @code{wp}
9913 command are not supported, (2) the watchpoint length must be a
9914 power of two and not less than four, and can not be greater than the
9915 watchpoint address, and (3) a watchpoint with a length greater than
9916 four consumes all the watchpoint hardware resources. This means that
9917 at any one time, you can have enabled either two watchpoints with a
9918 length of four, or one watchpoint with a length greater than four.
9920 These commands are available to XScale based CPUs,
9921 which are implementations of the ARMv5TE architecture.
9923 @deffn {Command} {xscale analyze_trace}
9924 Displays the contents of the trace buffer.
9927 @deffn {Command} {xscale cache_clean_address} address
9928 Changes the address used when cleaning the data cache.
9931 @deffn {Command} {xscale cache_info}
9932 Displays information about the CPU caches.
9935 @deffn {Command} {xscale cp15} regnum [value]
9936 Display cp15 register @var{regnum};
9937 else if a @var{value} is provided, that value is written to that register.
9940 @deffn {Command} {xscale debug_handler} target address
9941 Changes the address used for the specified target's debug handler.
9944 @deffn {Command} {xscale dcache} [@option{enable}|@option{disable}]
9945 Enables or disable the CPU's data cache.
9948 @deffn {Command} {xscale dump_trace} filename
9949 Dumps the raw contents of the trace buffer to @file{filename}.
9952 @deffn {Command} {xscale icache} [@option{enable}|@option{disable}]
9953 Enables or disable the CPU's instruction cache.
9956 @deffn {Command} {xscale mmu} [@option{enable}|@option{disable}]
9957 Enables or disable the CPU's memory management unit.
9960 @deffn {Command} {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
9961 Displays the trace buffer status, after optionally
9962 enabling or disabling the trace buffer
9963 and modifying how it is emptied.
9966 @deffn {Command} {xscale trace_image} filename [offset [type]]
9967 Opens a trace image from @file{filename}, optionally rebasing
9968 its segment addresses by @var{offset}.
9969 The image @var{type} may be one of
9970 @option{bin} (binary), @option{ihex} (Intel hex),
9971 @option{elf} (ELF file), @option{s19} (Motorola s19),
9972 @option{mem}, or @option{builder}.
9975 @anchor{xscalevectorcatch}
9976 @deffn {Command} {xscale vector_catch} [mask]
9977 @cindex vector_catch
9978 Display a bitmask showing the hardware vectors to catch.
9979 If the optional parameter is provided, first set the bitmask to that value.
9981 The mask bits correspond with bit 16..23 in the DCSR:
9984 0x02 Trap Undefined Instructions
9985 0x04 Trap Software Interrupt
9986 0x08 Trap Prefetch Abort
9987 0x10 Trap Data Abort
9994 @deffn {Command} {xscale vector_table} [(@option{low}|@option{high}) index value]
9995 @cindex vector_table
9997 Set an entry in the mini-IC vector table. There are two tables: one for
9998 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
9999 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
10000 points to the debug handler entry and can not be overwritten.
10001 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
10003 Without arguments, the current settings are displayed.
10007 @section ARMv6 Architecture
10010 @subsection ARM11 specific commands
10013 @deffn {Command} {arm11 memwrite burst} [@option{enable}|@option{disable}]
10014 Displays the value of the memwrite burst-enable flag,
10015 which is enabled by default.
10016 If a boolean parameter is provided, first assigns that flag.
10017 Burst writes are only used for memory writes larger than 1 word.
10018 They improve performance by assuming that the CPU has read each data
10019 word over JTAG and completed its write before the next word arrives,
10020 instead of polling for a status flag to verify that completion.
10021 This is usually safe, because JTAG runs much slower than the CPU.
10024 @deffn {Command} {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
10025 Displays the value of the memwrite error_fatal flag,
10026 which is enabled by default.
10027 If a boolean parameter is provided, first assigns that flag.
10028 When set, certain memory write errors cause earlier transfer termination.
10031 @deffn {Command} {arm11 step_irq_enable} [@option{enable}|@option{disable}]
10032 Displays the value of the flag controlling whether
10033 IRQs are enabled during single stepping;
10034 they are disabled by default.
10035 If a boolean parameter is provided, first assigns that.
10038 @deffn {Command} {arm11 vcr} [value]
10039 @cindex vector_catch
10040 Displays the value of the @emph{Vector Catch Register (VCR)},
10041 coprocessor 14 register 7.
10042 If @var{value} is defined, first assigns that.
10044 Vector Catch hardware provides dedicated breakpoints
10045 for certain hardware events.
10046 The specific bit values are core-specific (as in fact is using
10047 coprocessor 14 register 7 itself) but all current ARM11
10048 cores @emph{except the ARM1176} use the same six bits.
10051 @section ARMv7 and ARMv8 Architecture
10055 @subsection ARMv7-A specific commands
10058 @deffn {Command} {cortex_a cache_info}
10059 display information about target caches
10062 @deffn {Command} {cortex_a dacrfixup} [@option{on}|@option{off}]
10063 Work around issues with software breakpoints when the program text is
10064 mapped read-only by the operating system. This option sets the CP15 DACR
10065 to "all-manager" to bypass MMU permission checks on memory access.
10069 @deffn {Command} {cortex_a dbginit}
10070 Initialize core debug
10071 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
10074 @deffn {Command} {cortex_a smp} [on|off]
10075 Display/set the current SMP mode
10078 @deffn {Command} {cortex_a smp_gdb} [core_id]
10079 Display/set the current core displayed in GDB
10082 @deffn {Command} {cortex_a maskisr} [@option{on}|@option{off}]
10083 Selects whether interrupts will be processed when single stepping
10086 @deffn {Command} {cache_config l2x} [base way]
10087 configure l2x cache
10090 @deffn {Command} {cortex_a mmu dump} [@option{0}|@option{1}|@option{addr} address [@option{num_entries}]]
10091 Dump the MMU translation table from TTB0 or TTB1 register, or from physical
10092 memory location @var{address}. When dumping the table from @var{address}, print at most
10093 @var{num_entries} page table entries. @var{num_entries} is optional, if omitted, the maximum
10094 possible (4096) entries are printed.
10097 @subsection ARMv7-R specific commands
10100 @deffn {Command} {cortex_r4 dbginit}
10101 Initialize core debug
10102 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
10105 @deffn {Command} {cortex_r4 maskisr} [@option{on}|@option{off}]
10106 Selects whether interrupts will be processed when single stepping
10110 @subsection ARM CoreSight TPIU and SWO specific commands
10116 ARM CoreSight provides several modules to generate debugging
10117 information internally (ITM, DWT and ETM). Their output is directed
10118 through TPIU or SWO modules to be captured externally either on an SWO pin (this
10119 configuration is called SWV) or on a synchronous parallel trace port.
10121 ARM CoreSight provides independent HW blocks named TPIU and SWO each with its
10122 own functionality. Embedded in Cortex-M3 and M4, ARM provides an optional HW
10123 block that includes both TPIU and SWO functionalities and is again named TPIU,
10124 which causes quite some confusion.
10125 The registers map of all the TPIU and SWO implementations allows using a single
10126 driver that detects at runtime the features available.
10128 The @command{tpiu} is used for either TPIU or SWO.
10129 A convenient alias @command{swo} is available to help distinguish, in scripts,
10130 the commands for SWO from the commands for TPIU.
10132 @deffn {Command} {swo} ...
10133 Alias of @command{tpiu ...}. Can be used in scripts to distinguish the commands
10134 for SWO from the commands for TPIU.
10137 @deffn {Command} {tpiu create} tpiu_name configparams...
10138 Creates a TPIU or a SWO object. The two commands are equivalent.
10139 Add the object in a list and add new commands (@command{@var{tpiu_name}})
10140 which are used for various purposes including additional configuration.
10143 @item @var{tpiu_name} -- the name of the TPIU or SWO object.
10144 This name is also used to create the object's command, referred to here
10145 as @command{$tpiu_name}, and in other places where the TPIU or SWO needs to be identified.
10146 @item @var{configparams} -- all parameters accepted by @command{$tpiu_name configure} are permitted.
10148 You @emph{must} set here the AP and MEM_AP base_address through @code{-dap @var{dap_name}},
10149 @code{-ap-num @var{ap_number}} and @code{-baseaddr @var{base_address}}.
10153 @deffn {Command} {tpiu names}
10154 Lists all the TPIU or SWO objects created so far. The two commands are equivalent.
10157 @deffn {Command} {tpiu init}
10158 Initialize all registered TPIU and SWO. The two commands are equivalent.
10159 These commands are used internally during initialization. They can be issued
10160 at any time after the initialization, too.
10163 @deffn {Command} {$tpiu_name cget} queryparm
10164 Each configuration parameter accepted by @command{$tpiu_name configure} can be
10165 individually queried, to return its current value.
10166 The @var{queryparm} is a parameter name accepted by that command, such as @code{-dap}.
10169 @deffn {Command} {$tpiu_name configure} configparams...
10170 The options accepted by this command may also be specified as parameters
10171 to @command{tpiu create}. Their values can later be queried one at a time by
10172 using the @command{$tpiu_name cget} command.
10175 @item @code{-dap} @var{dap_name} -- names the DAP used to access this
10176 TPIU. @xref{dapdeclaration,,DAP declaration}, on how to create and manage DAP instances.
10178 @item @code{-ap-num} @var{ap_number} -- sets DAP access port for TPIU.
10179 On ADIv5 DAP @var{ap_number} is the numeric index of the DAP AP the TPIU is connected to.
10180 On ADIv6 DAP @var{ap_number} is the base address of the DAP AP the TPIU is connected to.
10182 @item @code{-baseaddr} @var{base_address} -- sets the TPIU @var{base_address} where
10183 to access the TPIU in the DAP AP memory space.
10185 @item @code{-protocol} (@option{sync}|@option{uart}|@option{manchester}) -- sets the
10186 protocol used for trace data:
10188 @item @option{sync} -- synchronous parallel trace output mode, using @var{port_width}
10189 data bits (default);
10190 @item @option{uart} -- use asynchronous SWO mode with NRZ (same as regular UART 8N1) coding;
10191 @item @option{manchester} -- use asynchronous SWO mode with Manchester coding.
10194 @item @code{-event} @var{event_name} @var{event_body} -- assigns an event handler,
10195 a TCL string which is evaluated when the event is triggered. The events
10196 @code{pre-enable}, @code{post-enable}, @code{pre-disable} and @code{post-disable}
10197 are defined for TPIU/SWO.
10198 A typical use case for the event @code{pre-enable} is to enable the trace clock
10201 @item @code{-output} (@option{external}|@option{:}@var{port}|@var{filename}|@option{-}) -- specifies
10202 the destination of the trace data:
10204 @item @option{external} -- configure TPIU/SWO to let user capture trace
10205 output externally, either with an additional UART or with a logic analyzer (default);
10206 @item @option{-} -- configure TPIU/SWO and debug adapter to gather trace data
10207 and forward it to @command{tcl_trace} command;
10208 @item @option{:}@var{port} -- configure TPIU/SWO and debug adapter to gather
10209 trace data, open a TCP server at port @var{port} and send the trace data to
10210 each connected client;
10211 @item @var{filename} -- configure TPIU/SWO and debug adapter to
10212 gather trace data and append it to @var{filename}, which can be
10213 either a regular file or a named pipe.
10216 @item @code{-traceclk} @var{TRACECLKIN_freq} -- mandatory parameter.
10217 Specifies the frequency in Hz of the trace clock. For the TPIU embedded in
10218 Cortex-M3 or M4, this is usually the same frequency as HCLK. For protocol
10219 @option{sync} this is twice the frequency of the pin data rate.
10221 @item @code{-pin-freq} @var{trace_freq} -- specifies the expected data rate
10222 in Hz of the SWO pin. Parameter used only on protocols @option{uart} and
10223 @option{manchester}. Can be omitted to let the adapter driver select the
10224 maximum supported rate automatically.
10226 @item @code{-port-width} @var{port_width} -- sets to @var{port_width} the width
10227 of the synchronous parallel port used for trace output. Parameter used only on
10228 protocol @option{sync}. If not specified, default value is @var{1}.
10230 @item @code{-formatter} (@option{0}|@option{1}) -- specifies if the formatter
10231 should be enabled. Parameter used only on protocol @option{sync}. If not specified,
10232 default value is @var{0}.
10236 @deffn {Command} {$tpiu_name enable}
10237 Uses the parameters specified by the previous @command{$tpiu_name configure}
10238 to configure and enable the TPIU or the SWO.
10239 If required, the adapter is also configured and enabled to receive the trace
10241 This command can be used before @command{init}, but it will take effect only
10242 after the @command{init}.
10245 @deffn {Command} {$tpiu_name disable}
10246 Disable the TPIU or the SWO, terminating the receiving of the trace data.
10253 @item STM32L152 board is programmed with an application that configures
10254 PLL to provide core clock with 24MHz frequency; to use ITM output it's
10257 #include <libopencm3/cm3/itm.h>
10262 (the most obvious way is to use the first stimulus port for printf,
10263 for that this ITM_STIM8 assignment can be used inside _write(); to make it
10264 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
10265 ITM_STIM_FIFOREADY));});
10266 @item An FT2232H UART is connected to the SWO pin of the board;
10267 @item Commands to configure UART for 12MHz baud rate:
10269 $ setserial /dev/ttyUSB1 spd_cust divisor 5
10270 $ stty -F /dev/ttyUSB1 38400
10272 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
10273 baud with our custom divisor to get 12MHz)
10274 @item @code{itmdump -f /dev/ttyUSB1 -d1}
10275 @item OpenOCD invocation line:
10277 openocd -f interface/stlink.cfg \
10278 -c "transport select hla_swd" \
10279 -f target/stm32l1.cfg \
10280 -c "stm32l1.tpiu configure -protocol uart" \
10281 -c "stm32l1.tpiu configure -traceclk 24000000 -pin-freq 12000000" \
10282 -c "stm32l1.tpiu enable"
10286 @subsection ARMv7-M specific commands
10293 @deffn {Command} {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
10294 Enable or disable trace output for ITM stimulus @var{port} (counting
10295 from 0). Port 0 is enabled on target creation automatically.
10298 @deffn {Command} {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
10299 Enable or disable trace output for all ITM stimulus ports.
10302 @subsection Cortex-M specific commands
10305 @deffn {Command} {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}|@option{steponly})
10306 Control masking (disabling) interrupts during target step/resume.
10308 The @option{auto} option handles interrupts during stepping in a way that they
10309 get served but don't disturb the program flow. The step command first allows
10310 pending interrupt handlers to execute, then disables interrupts and steps over
10311 the next instruction where the core was halted. After the step interrupts
10312 are enabled again. If the interrupt handlers don't complete within 500ms,
10313 the step command leaves with the core running.
10315 The @option{steponly} option disables interrupts during single-stepping but
10316 enables them during normal execution. This can be used as a partial workaround
10317 for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with
10318 FPU (AT611) Software Developer Errata Notice" from ARM for further details.
10320 Note that a free hardware (FPB) breakpoint is required for the @option{auto}
10321 option. If no breakpoint is available at the time of the step, then the step
10322 is taken with interrupts enabled, i.e. the same way the @option{off} option
10325 Default is @option{auto}.
10328 @deffn {Command} {cortex_m vector_catch} [@option{all}|@option{none}|list]
10329 @cindex vector_catch
10330 Vector Catch hardware provides dedicated breakpoints
10331 for certain hardware events.
10333 Parameters request interception of
10334 @option{all} of these hardware event vectors,
10335 @option{none} of them,
10336 or one or more of the following:
10337 @option{hard_err} for a HardFault exception;
10338 @option{mm_err} for a MemManage exception;
10339 @option{bus_err} for a BusFault exception;
10341 @option{state_err},
10342 @option{chk_err}, or
10343 @option{nocp_err} for various UsageFault exceptions; or
10345 If NVIC setup code does not enable them,
10346 MemManage, BusFault, and UsageFault exceptions
10347 are mapped to HardFault.
10348 UsageFault checks for
10349 divide-by-zero and unaligned access
10350 must also be explicitly enabled.
10352 This finishes by listing the current vector catch configuration.
10355 @deffn {Command} {cortex_m reset_config} (@option{sysresetreq}|@option{vectreset})
10356 Control reset handling if hardware srst is not fitted
10357 @xref{reset_config,,reset_config}.
10360 @item @option{sysresetreq} use AIRCR SYSRESETREQ to reset system.
10361 @item @option{vectreset} use AIRCR VECTRESET to reset system (default).
10364 Using @option{vectreset} is a safe option for Cortex-M3, M4 and M7 cores.
10365 This however has the disadvantage of only resetting the core, all peripherals
10366 are unaffected. A solution would be to use a @code{reset-init} event handler
10367 to manually reset the peripherals.
10368 @xref{targetevents,,Target Events}.
10370 Cortex-M0, M0+ and M1 do not support @option{vectreset}, use @option{sysresetreq}
10374 @subsection ARMv8-A specific commands
10378 @deffn {Command} {aarch64 cache_info}
10379 Display information about target caches
10382 @deffn {Command} {aarch64 dbginit}
10383 This command enables debugging by clearing the OS Lock and sticky power-down and reset
10384 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
10385 target code relies on. In a configuration file, the command would typically be called from a
10386 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
10387 However, normally it is not necessary to use the command at all.
10390 @deffn {Command} {aarch64 disassemble} address [count]
10391 @cindex disassemble
10392 Disassembles @var{count} instructions starting at @var{address}.
10393 If @var{count} is not specified, a single instruction is disassembled.
10396 @deffn {Command} {aarch64 smp} [on|off]
10397 Display, enable or disable SMP handling mode. The state of SMP handling influences the way targets in an SMP group
10398 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
10399 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
10400 group. With SMP handling disabled, all targets need to be treated individually.
10403 @deffn {Command} {aarch64 maskisr} [@option{on}|@option{off}]
10404 Selects whether interrupts will be processed when single stepping. The default configuration is
10408 @deffn {Command} {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+
10409 Cause @command{$target_name} to halt when an exception is taken. Any combination of
10410 Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target
10411 @command{$target_name} will halt before taking the exception. In order to resume
10412 the target, the exception catch must be disabled again with @command{$target_name catch_exc off}.
10413 Issuing the command without options prints the current configuration.
10416 @section EnSilica eSi-RISC Architecture
10418 eSi-RISC is a highly configurable microprocessor architecture for embedded systems
10419 provided by EnSilica. (See: @url{http://www.ensilica.com/risc-ip/}.)
10421 @subsection eSi-RISC Configuration
10423 @deffn {Command} {esirisc cache_arch} (@option{harvard}|@option{von_neumann})
10424 Configure the caching architecture. Targets with the @code{UNIFIED_ADDRESS_SPACE}
10425 option disabled employ a Harvard architecture. By default, @option{von_neumann} is assumed.
10428 @deffn {Command} {esirisc hwdc} (@option{all}|@option{none}|mask ...)
10429 Configure hardware debug control. The HWDC register controls which exceptions return
10430 control back to the debugger. Possible masks are @option{all}, @option{none},
10431 @option{reset}, @option{interrupt}, @option{syscall}, @option{error}, and @option{debug}.
10432 By default, @option{reset}, @option{error}, and @option{debug} are enabled.
10435 @subsection eSi-RISC Operation
10437 @deffn {Command} {esirisc flush_caches}
10438 Flush instruction and data caches. This command requires that the target is halted
10439 when the command is issued and configured with an instruction or data cache.
10442 @subsection eSi-Trace Configuration
10444 eSi-RISC targets may be configured with support for instruction tracing. Trace
10445 data may be written to an in-memory buffer or FIFO. If a FIFO is configured, DMA
10446 is typically employed to move trace data off-device using a high-speed
10447 peripheral (eg. SPI). Collected trace data is encoded in one of three different
10448 formats. At a minimum, @command{esirisc trace buffer} or @command{esirisc trace
10449 fifo} must be issued along with @command{esirisc trace format} before trace data
10452 OpenOCD provides rudimentary analysis of collected trace data. If more detail is
10453 needed, collected trace data can be dumped to a file and processed by external
10457 OpenOCD is unable to process trace data sent to a FIFO. A potential workaround
10458 for this issue is to configure DMA to copy trace data to an in-memory buffer,
10459 which can then be passed to the @command{esirisc trace analyze} and
10460 @command{esirisc trace dump} commands.
10462 It is possible to corrupt trace data when using a FIFO if the peripheral
10463 responsible for draining data from the FIFO is not fast enough. This can be
10464 managed by enabling flow control, however this can impact timing-sensitive
10465 software operation on the CPU.
10468 @deffn {Command} {esirisc trace buffer} address size [@option{wrap}]
10469 Configure trace buffer using the provided address and size. If the @option{wrap}
10470 option is specified, trace collection will continue once the end of the buffer
10471 is reached. By default, wrap is disabled.
10474 @deffn {Command} {esirisc trace fifo} address
10475 Configure trace FIFO using the provided address.
10478 @deffn {Command} {esirisc trace flow_control} (@option{enable}|@option{disable})
10479 Enable or disable stalling the CPU to collect trace data. By default, flow
10480 control is disabled.
10483 @deffn {Command} {esirisc trace format} (@option{full}|@option{branch}|@option{icache}) pc_bits
10484 Configure trace format and number of PC bits to be captured. @option{pc_bits}
10485 must be within 1 and 31 as the LSB is not collected. If external tooling is used
10486 to analyze collected trace data, these values must match.
10488 Supported trace formats:
10490 @item @option{full} capture full trace data, allowing execution history and
10491 timing to be determined.
10492 @item @option{branch} capture taken branch instructions and branch target
10494 @item @option{icache} capture instruction cache misses.
10498 @deffn {Command} {esirisc trace trigger start} (@option{condition}) [start_data start_mask]
10499 Configure trigger start condition using the provided start data and mask. A
10500 brief description of each condition is provided below; for more detail on how
10501 these values are used, see the eSi-RISC Architecture Manual.
10503 Supported conditions:
10505 @item @option{none} manual tracing (see @command{esirisc trace start}).
10506 @item @option{pc} start tracing if the PC matches start data and mask.
10507 @item @option{load} start tracing if the effective address of a load
10508 instruction matches start data and mask.
10509 @item @option{store} start tracing if the effective address of a store
10510 instruction matches start data and mask.
10511 @item @option{exception} start tracing if the EID of an exception matches start
10513 @item @option{eret} start tracing when an @code{ERET} instruction is executed.
10514 @item @option{wait} start tracing when a @code{WAIT} instruction is executed.
10515 @item @option{stop} start tracing when a @code{STOP} instruction is executed.
10516 @item @option{high} start tracing when an external signal is a logical high.
10517 @item @option{low} start tracing when an external signal is a logical low.
10521 @deffn {Command} {esirisc trace trigger stop} (@option{condition}) [stop_data stop_mask]
10522 Configure trigger stop condition using the provided stop data and mask. A brief
10523 description of each condition is provided below; for more detail on how these
10524 values are used, see the eSi-RISC Architecture Manual.
10526 Supported conditions:
10528 @item @option{none} manual tracing (see @command{esirisc trace stop}).
10529 @item @option{pc} stop tracing if the PC matches stop data and mask.
10530 @item @option{load} stop tracing if the effective address of a load
10531 instruction matches stop data and mask.
10532 @item @option{store} stop tracing if the effective address of a store
10533 instruction matches stop data and mask.
10534 @item @option{exception} stop tracing if the EID of an exception matches stop
10536 @item @option{eret} stop tracing when an @code{ERET} instruction is executed.
10537 @item @option{wait} stop tracing when a @code{WAIT} instruction is executed.
10538 @item @option{stop} stop tracing when a @code{STOP} instruction is executed.
10542 @deffn {Command} {esirisc trace trigger delay} (@option{trigger}) [cycles]
10543 Configure trigger start/stop delay in clock cycles.
10545 Supported triggers:
10547 @item @option{none} no delay to start or stop collection.
10548 @item @option{start} delay @option{cycles} after trigger to start collection.
10549 @item @option{stop} delay @option{cycles} after trigger to stop collection.
10550 @item @option{both} delay @option{cycles} after both triggers to start or stop
10555 @subsection eSi-Trace Operation
10557 @deffn {Command} {esirisc trace init}
10558 Initialize trace collection. This command must be called any time the
10559 configuration changes. If a trace buffer has been configured, the contents will
10560 be overwritten when trace collection starts.
10563 @deffn {Command} {esirisc trace info}
10564 Display trace configuration.
10567 @deffn {Command} {esirisc trace status}
10568 Display trace collection status.
10571 @deffn {Command} {esirisc trace start}
10572 Start manual trace collection.
10575 @deffn {Command} {esirisc trace stop}
10576 Stop manual trace collection.
10579 @deffn {Command} {esirisc trace analyze} [address size]
10580 Analyze collected trace data. This command may only be used if a trace buffer
10581 has been configured. If a trace FIFO has been configured, trace data must be
10582 copied to an in-memory buffer identified by the @option{address} and
10583 @option{size} options using DMA.
10586 @deffn {Command} {esirisc trace dump} [address size] @file{filename}
10587 Dump collected trace data to file. This command may only be used if a trace
10588 buffer has been configured. If a trace FIFO has been configured, trace data must
10589 be copied to an in-memory buffer identified by the @option{address} and
10590 @option{size} options using DMA.
10593 @section Intel Architecture
10595 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
10596 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
10597 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
10598 software debug and the CLTAP is used for SoC level operations.
10599 Useful docs are here: https://communities.intel.com/community/makers/documentation
10601 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
10602 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
10603 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
10606 @subsection x86 32-bit specific commands
10607 The three main address spaces for x86 are memory, I/O and configuration space.
10608 These commands allow a user to read and write to the 64Kbyte I/O address space.
10610 @deffn {Command} {x86_32 idw} address
10611 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
10614 @deffn {Command} {x86_32 idh} address
10615 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
10618 @deffn {Command} {x86_32 idb} address
10619 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
10622 @deffn {Command} {x86_32 iww} address
10623 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
10626 @deffn {Command} {x86_32 iwh} address
10627 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
10630 @deffn {Command} {x86_32 iwb} address
10631 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
10634 @section OpenRISC Architecture
10636 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
10637 configured with any of the TAP / Debug Unit available.
10639 @subsection TAP and Debug Unit selection commands
10640 @deffn {Command} {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
10641 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
10643 @deffn {Command} {du_select} (@option{adv}|@option{mohor}) [option]
10644 Select between the Advanced Debug Interface and the classic one.
10646 An option can be passed as a second argument to the debug unit.
10648 When using the Advanced Debug Interface, option = 1 means the RTL core is
10649 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
10650 between bytes while doing read or write bursts.
10653 @subsection Registers commands
10654 @deffn {Command} {addreg} [name] [address] [feature] [reg_group]
10655 Add a new register in the cpu register list. This register will be
10656 included in the generated target descriptor file.
10658 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
10660 @strong{[reg_group]} can be anything. The default register list defines "system",
10661 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
10662 and "timer" groups.
10666 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
10671 @section RISC-V Architecture
10673 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
10674 debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
10675 harts. (It's possible to increase this limit to 1024 by changing
10676 RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
10677 Debug Specification, but there is also support for legacy targets that
10678 implement version 0.11.
10680 @subsection RISC-V Terminology
10682 A @emph{hart} is a hardware thread. A hart may share resources (eg. FPU) with
10683 another hart, or may be a separate core. RISC-V treats those the same, and
10684 OpenOCD exposes each hart as a separate core.
10686 @subsection Vector Registers
10688 For harts that implement the vector extension, OpenOCD provides access to the
10689 relevant CSRs, as well as the vector registers (v0-v31). The size of each
10690 vector register is dependent on the value of vlenb. RISC-V allows each vector
10691 register to be divided into selected-width elements, and this division can be
10692 changed at run-time. Because OpenOCD cannot update register definitions at
10693 run-time, it exposes each vector register to gdb as a union of fields of
10694 vectors so that users can easily access individual bytes, shorts, words,
10695 longs, and quads inside each vector register. It is left to gdb or
10696 higher-level debuggers to present this data in a more intuitive format.
10698 In the XML register description, the vector registers (when vlenb=16) look as
10702 <feature name="org.gnu.gdb.riscv.vector">
10703 <vector id="bytes" type="uint8" count="16"/>
10704 <vector id="shorts" type="uint16" count="8"/>
10705 <vector id="words" type="uint32" count="4"/>
10706 <vector id="longs" type="uint64" count="2"/>
10707 <vector id="quads" type="uint128" count="1"/>
10708 <union id="riscv_vector">
10709 <field name="b" type="bytes"/>
10710 <field name="s" type="shorts"/>
10711 <field name="w" type="words"/>
10712 <field name="l" type="longs"/>
10713 <field name="q" type="quads"/>
10715 <reg name="v0" bitsize="128" regnum="4162" save-restore="no"
10716 type="riscv_vector" group="vector"/>
10718 <reg name="v31" bitsize="128" regnum="4193" save-restore="no"
10719 type="riscv_vector" group="vector"/>
10723 @subsection RISC-V Debug Configuration Commands
10725 @deffn {Config Command} {riscv expose_csrs} n[-m|=name] [...]
10726 Configure which CSRs to expose in addition to the standard ones. The CSRs to expose
10727 can be specified as individual register numbers or register ranges (inclusive). For the
10728 individually listed CSRs, a human-readable name can optionally be set using the @code{n=name}
10729 syntax, which will get @code{csr_} prepended to it. If no name is provided, the register will be
10730 named @code{csr<n>}.
10732 By default OpenOCD attempts to expose only CSRs that are mentioned in a spec,
10733 and then only if the corresponding extension appears to be implemented. This
10734 command can be used if OpenOCD gets this wrong, or if the target implements custom
10738 # Expose a single RISC-V CSR number 128 under the name "csr128":
10739 $_TARGETNAME expose_csrs 128
10741 # Expose multiple RISC-V CSRs 128..132 under names "csr128" through "csr132":
10742 $_TARGETNAME expose_csrs 128-132
10744 # Expose a single RISC-V CSR number 1996 under custom name "csr_myregister":
10745 $_TARGETNAME expose_csrs 1996=myregister
10749 @deffn {Config Command} {riscv expose_custom} n[-m|=name] [...]
10750 The RISC-V Debug Specification allows targets to expose custom registers
10751 through abstract commands. (See Section 3.5.1.1 in that document.) This command
10752 configures individual registers or register ranges (inclusive) that shall be exposed.
10753 Number 0 indicates the first custom register, whose abstract command number is 0xc000.
10754 For individually listed registers, a human-readable name can be optionally provided
10755 using the @code{n=name} syntax, which will get @code{custom_} prepended to it. If no
10756 name is provided, the register will be named @code{custom<n>}.
10759 # Expose one RISC-V custom register with number 0xc010 (0xc000 + 16)
10760 # under the name "custom16":
10761 $_TARGETNAME expose_custom 16
10763 # Expose a range of RISC-V custom registers with numbers 0xc010 .. 0xc018
10764 # (0xc000+16 .. 0xc000+24) under the names "custom16" through "custom24":
10765 $_TARGETNAME expose_custom 16-24
10767 # Expose one RISC-V custom register with number 0xc020 (0xc000 + 32) under
10768 # user-defined name "custom_myregister":
10769 $_TARGETNAME expose_custom 32=myregister
10773 @deffn {Command} {riscv set_command_timeout_sec} [seconds]
10774 Set the wall-clock timeout (in seconds) for individual commands. The default
10775 should work fine for all but the slowest targets (eg. simulators).
10778 @deffn {Command} {riscv set_reset_timeout_sec} [seconds]
10779 Set the maximum time to wait for a hart to come out of reset after reset is
10783 @deffn {Command} {riscv set_scratch_ram} none|[address]
10784 Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'.
10785 This is used to access 64-bit floating point registers on 32-bit targets.
10788 @deffn Command {riscv set_mem_access} method1 [method2] [method3]
10789 Specify which RISC-V memory access method(s) shall be used, and in which order
10790 of priority. At least one method must be specified.
10792 Available methods are:
10794 @item @code{progbuf} - Use RISC-V Debug Program Buffer to access memory.
10795 @item @code{sysbus} - Access memory via RISC-V Debug System Bus interface.
10796 @item @code{abstract} - Access memory via RISC-V Debug abstract commands.
10799 By default, all memory access methods are enabled in the following order:
10800 @code{progbuf sysbus abstract}.
10802 This command can be used to change the memory access methods if the default
10803 behavior is not suitable for a particular target.
10806 @deffn {Command} {riscv set_enable_virtual} on|off
10807 When on, memory accesses are performed on physical or virtual memory depending
10808 on the current system configuration. When off (default), all memory accessses are performed
10809 on physical memory.
10812 @deffn {Command} {riscv set_enable_virt2phys} on|off
10813 When on (default), memory accesses are performed on physical or virtual memory
10814 depending on the current satp configuration. When off, all memory accessses are
10815 performed on physical memory.
10818 @deffn {Command} {riscv resume_order} normal|reversed
10819 Some software assumes all harts are executing nearly continuously. Such
10820 software may be sensitive to the order that harts are resumed in. On harts
10821 that don't support hasel, this option allows the user to choose the order the
10822 harts are resumed in. If you are using this option, it's probably masking a
10823 race condition problem in your code.
10825 Normal order is from lowest hart index to highest. This is the default
10826 behavior. Reversed order is from highest hart index to lowest.
10829 @deffn {Command} {riscv set_ir} (@option{idcode}|@option{dtmcs}|@option{dmi}) [value]
10830 Set the IR value for the specified JTAG register. This is useful, for
10831 example, when using the existing JTAG interface on a Xilinx FPGA by
10832 way of BSCANE2 primitives that only permit a limited selection of IR
10835 When utilizing version 0.11 of the RISC-V Debug Specification,
10836 @option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL
10837 and DBUS registers, respectively.
10840 @deffn {Command} {riscv use_bscan_tunnel} value
10841 Enable or disable use of a BSCAN tunnel to reach DM. Supply the width of
10842 the DM transport TAP's instruction register to enable. Supply a value of 0 to disable.
10845 @deffn {Command} {riscv set_ebreakm} on|off
10846 Control dcsr.ebreakm. When on (default), M-mode ebreak instructions trap to
10847 OpenOCD. When off, they generate a breakpoint exception handled internally.
10850 @deffn {Command} {riscv set_ebreaks} on|off
10851 Control dcsr.ebreaks. When on (default), S-mode ebreak instructions trap to
10852 OpenOCD. When off, they generate a breakpoint exception handled internally.
10855 @deffn {Command} {riscv set_ebreaku} on|off
10856 Control dcsr.ebreaku. When on (default), U-mode ebreak instructions trap to
10857 OpenOCD. When off, they generate a breakpoint exception handled internally.
10860 @subsection RISC-V Authentication Commands
10862 The following commands can be used to authenticate to a RISC-V system. Eg. a
10863 trivial challenge-response protocol could be implemented as follows in a
10864 configuration file, immediately following @command{init}:
10866 set challenge [riscv authdata_read]
10867 riscv authdata_write [expr @{$challenge + 1@}]
10870 @deffn {Command} {riscv authdata_read}
10871 Return the 32-bit value read from authdata.
10874 @deffn {Command} {riscv authdata_write} value
10875 Write the 32-bit value to authdata.
10878 @subsection RISC-V DMI Commands
10880 The following commands allow direct access to the Debug Module Interface, which
10881 can be used to interact with custom debug features.
10883 @deffn {Command} {riscv dmi_read} address
10884 Perform a 32-bit DMI read at address, returning the value.
10887 @deffn {Command} {riscv dmi_write} address value
10888 Perform a 32-bit DMI write of value at address.
10891 @section ARC Architecture
10894 Synopsys DesignWare ARC Processors are a family of 32-bit CPUs that SoC
10895 designers can optimize for a wide range of uses, from deeply embedded to
10896 high-performance host applications in a variety of market segments. See more
10897 at: @url{http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx}.
10898 OpenOCD currently supports ARC EM processors.
10899 There is a set ARC-specific OpenOCD commands that allow low-level
10900 access to the core and provide necessary support for ARC extensibility and
10901 configurability capabilities. ARC processors has much more configuration
10902 capabilities than most of the other processors and in addition there is an
10903 extension interface that allows SoC designers to add custom registers and
10904 instructions. For the OpenOCD that mostly means that set of core and AUX
10905 registers in target will vary and is not fixed for a particular processor
10906 model. To enable extensibility several TCL commands are provided that allow to
10907 describe those optional registers in OpenOCD configuration files. Moreover
10908 those commands allow for a dynamic target features discovery.
10911 @subsection General ARC commands
10913 @deffn {Config Command} {arc add-reg} configparams
10915 Add a new register to processor target. By default newly created register is
10916 marked as not existing. @var{configparams} must have following required
10921 @item @code{-name} name
10922 @*Name of a register.
10924 @item @code{-num} number
10925 @*Architectural register number: core register number or AUX register number.
10927 @item @code{-feature} XML_feature
10928 @*Name of GDB XML target description feature.
10932 @var{configparams} may have following optional arguments:
10936 @item @code{-gdbnum} number
10937 @*GDB register number. It is recommended to not assign GDB register number
10938 manually, because there would be a risk that two register will have same
10939 number. When register GDB number is not set with this option, then register
10940 will get a previous register number + 1. This option is required only for those
10941 registers that must be at particular address expected by GDB.
10944 @*This option specifies that register is a core registers. If not - this is an
10945 AUX register. AUX registers and core registers reside in different address
10949 @*This options specifies that register is a BCR register. BCR means Build
10950 Configuration Registers - this is a special type of AUX registers that are read
10951 only and non-volatile, that is - they never change their value. Therefore OpenOCD
10952 never invalidates values of those registers in internal caches. Because BCR is a
10953 type of AUX registers, this option cannot be used with @code{-core}.
10955 @item @code{-type} type_name
10956 @*Name of type of this register. This can be either one of the basic GDB types,
10957 or a custom types described with @command{arc add-reg-type-[flags|struct]}.
10960 @* If specified then this is a "general" register. General registers are always
10961 read by OpenOCD on context save (when core has just been halted) and is always
10962 transferred to GDB client in a response to g-packet. Contrary to this,
10963 non-general registers are read and sent to GDB client on-demand. In general it
10964 is not recommended to apply this option to custom registers.
10970 @deffn {Config Command} {arc add-reg-type-flags} -name name flags...
10971 Adds new register type of ``flags'' class. ``Flags'' types can contain only
10972 one-bit fields. Each flag definition looks like @code{-flag name bit-position}.
10975 @anchor{add-reg-type-struct}
10976 @deffn {Config Command} {arc add-reg-type-struct} -name name structs...
10977 Adds new register type of ``struct'' class. ``Struct'' types can contain either
10978 bit-fields or fields of other types, however at the moment only bit fields are
10979 supported. Structure bit field definition looks like @code{-bitfield name
10983 @deffn {Command} {arc get-reg-field} reg-name field-name
10984 Returns value of bit-field in a register. Register must be ``struct'' register
10985 type, @xref{add-reg-type-struct}. command definition.
10988 @deffn {Command} {arc set-reg-exists} reg-names...
10989 Specify that some register exists. Any amount of names can be passed
10990 as an argument for a single command invocation.
10993 @subsection ARC JTAG commands
10995 @deffn {Command} {arc jtag set-aux-reg} regnum value
10996 This command writes value to AUX register via its number. This command access
10997 register in target directly via JTAG, bypassing any OpenOCD internal caches,
10998 therefore it is unsafe to use if that register can be operated by other means.
11002 @deffn {Command} {arc jtag set-core-reg} regnum value
11003 This command is similar to @command{arc jtag set-aux-reg} but is for core
11007 @deffn {Command} {arc jtag get-aux-reg} regnum
11008 This command returns the value storded in AUX register via its number. This commands access
11009 register in target directly via JTAG, bypassing any OpenOCD internal caches,
11010 therefore it is unsafe to use if that register can be operated by other means.
11014 @deffn {Command} {arc jtag get-core-reg} regnum
11015 This command is similar to @command{arc jtag get-aux-reg} but is for core
11019 @section STM8 Architecture
11020 @uref{http://st.com/stm8/, STM8} is a 8-bit microcontroller platform from
11021 STMicroelectronics, based on a proprietary 8-bit core architecture.
11023 OpenOCD supports debugging STM8 through the STMicroelectronics debug
11024 protocol SWIM, @pxref{swimtransport,,SWIM}.
11026 @section Xtensa Architecture
11027 Xtensa processors are based on a modular, highly flexible 32-bit RISC architecture
11028 that can easily scale from a tiny, cache-less controller or task engine to a high-performance
11029 SIMD/VLIW DSP provided by Cadence.
11030 @url{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip/tensilica-xtensa-controllers-and-extensible-processors.html}.
11032 OpenOCD supports generic Xtensa processors implementation which can be customized by
11033 simply providing vendor-specific core configuration which controls every configurable
11034 Xtensa architecture option, e.g. number of address registers, exceptions, reduced
11035 size instructions support, memory banks configuration etc. Also OpenOCD supports SMP
11036 configurations for Xtensa processors with any number of cores and allows to configure
11037 their debug signals interconnection (so-called "break/stall networks") which control how
11038 debug signals are distributed among cores. Xtensa "break networks" are compatible with
11039 ARM's Cross Trigger Interface (CTI). For debugging code on Xtensa chips OpenOCD
11040 uses JTAG protocol. Currently OpenOCD implements several Epsressif Xtensa-based chips of
11041 @uref{https://www.espressif.com/en/products/socs, ESP32 family}.
11043 @subsection General Xtensa Commands
11045 @deffn {Command} {xtensa set_permissive} (0|1)
11046 By default accessing memory beyond defined regions is forbidden. This commnd controls memory access address check.
11047 When set to (1), skips access controls and address range check before read/write memory.
11050 @deffn {Command} {xtensa maskisr} (on|off)
11051 Selects whether interrupts will be disabled during stepping over single instruction. The default configuration is (off).
11054 @deffn {Command} {xtensa smpbreak} [none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]
11055 Configures debug signals connection ("break network") for currently selected core.
11057 @item @code{none} - Core's "break/stall network" is disconnected. Core is not affected by any debug
11058 signal from other cores.
11059 @item @code{breakinout} - Core's "break network" is fully connected (break inputs and outputs are enabled).
11060 Core will receive debug break signals from other cores and send such signals to them. For example when another core
11061 is stopped due to breakpoint hit this core will be stopped too and vice versa.
11062 @item @code{runstall} - Core's "stall network" is fully connected (stall inputs and outputs are enabled).
11063 This feature is not well implemented and tested yet.
11064 @item @code{BreakIn} - Core's "break-in" signal is enabled.
11065 Core will receive debug break signals from other cores. For example when another core is
11066 stopped due to breakpoint hit this core will be stopped too.
11067 @item @code{BreakOut} - Core's "break-out" signal is enabled.
11068 Core will send debug break signal to other cores. For example when this core is
11069 stopped due to breakpoint hit other cores with enabled break-in signals will be stopped too.
11070 @item @code{RunStallIn} - Core's "runstall-in" signal is enabled.
11071 This feature is not well implemented and tested yet.
11072 @item @code{DebugModeOut} - Core's "debugmode-out" signal is enabled.
11073 This feature is not well implemented and tested yet.
11077 @deffn {Command} {xtensa perfmon_enable} <counter_id> <select> [mask] [kernelcnt] [tracelevel]
11078 Enable and start performance counter.
11080 @item @code{counter_id} - Counter ID (0-1).
11081 @item @code{select} - Selects performance metric to be counted by the counter,
11082 e.g. 0 - CPU cycles, 2 - retired instructions.
11083 @item @code{mask} - Selects input subsets to be counted (counter will
11084 increment only once even if more than one condition corresponding to a mask bit occurs).
11085 @item @code{kernelcnt} - 0 - count events with "CINTLEVEL <= tracelevel",
11086 1 - count events with "CINTLEVEL > tracelevel".
11087 @item @code{tracelevel} - Compares this value to "CINTLEVEL" when deciding
11092 @deffn {Command} {xtensa perfmon_dump} (counter_id)
11093 Dump performance counter value. If no argument specified, dumps all counters.
11096 @deffn {Command} {xtensa tracestart} [pc <pcval>/[<maskbitcount>]] [after <n> [ins|words]]
11097 Set up and start a HW trace. Optionally set PC address range to trigger tracing stop when reached during program execution.
11098 This command also allows to specify the amount of data to capture after stop trigger activation.
11100 @item @code{pcval} - PC value which will trigger trace data collection stop.
11101 @item @code{maskbitcount} - PC value mask.
11102 @item @code{n} - Maximum number of instructions/words to capture after trace stop trigger.
11106 @deffn {Command} {xtensa tracestop}
11107 Stop current trace as started by the tracestart command.
11110 @deffn {Command} {xtensa tracedump} <outfile>
11111 Dump trace memory to a file.
11114 @anchor{softwaredebugmessagesandtracing}
11115 @section Software Debug Messages and Tracing
11116 @cindex Linux-ARM DCC support
11120 OpenOCD can process certain requests from target software, when
11121 the target uses appropriate libraries.
11122 The most powerful mechanism is semihosting, but there is also
11123 a lighter weight mechanism using only the DCC channel.
11125 Currently @command{target_request debugmsgs}
11126 is supported only for @option{arm7_9} and @option{cortex_m} cores.
11127 These messages are received as part of target polling, so
11128 you need to have @command{poll on} active to receive them.
11129 They are intrusive in that they will affect program execution
11130 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
11132 See @file{libdcc} in the contrib dir for more details.
11133 In addition to sending strings, characters, and
11134 arrays of various size integers from the target,
11135 @file{libdcc} also exports a software trace point mechanism.
11136 The target being debugged may
11137 issue trace messages which include a 24-bit @dfn{trace point} number.
11138 Trace point support includes two distinct mechanisms,
11139 each supported by a command:
11142 @item @emph{History} ... A circular buffer of trace points
11143 can be set up, and then displayed at any time.
11144 This tracks where code has been, which can be invaluable in
11145 finding out how some fault was triggered.
11147 The buffer may overflow, since it collects records continuously.
11148 It may be useful to use some of the 24 bits to represent a
11149 particular event, and other bits to hold data.
11151 @item @emph{Counting} ... An array of counters can be set up,
11152 and then displayed at any time.
11153 This can help establish code coverage and identify hot spots.
11155 The array of counters is directly indexed by the trace point
11156 number, so trace points with higher numbers are not counted.
11159 Linux-ARM kernels have a ``Kernel low-level debugging
11160 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
11161 depends on CONFIG_DEBUG_LL) which uses this mechanism to
11162 deliver messages before a serial console can be activated.
11163 This is not the same format used by @file{libdcc}.
11164 Other software, such as the U-Boot boot loader, sometimes
11165 does the same thing.
11167 @deffn {Command} {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
11168 Displays current handling of target DCC message requests.
11169 These messages may be sent to the debugger while the target is running.
11170 The optional @option{enable} and @option{charmsg} parameters
11171 both enable the messages, while @option{disable} disables them.
11173 With @option{charmsg} the DCC words each contain one character,
11174 as used by Linux with CONFIG_DEBUG_ICEDCC;
11175 otherwise the libdcc format is used.
11178 @deffn {Command} {trace history} [@option{clear}|count]
11179 With no parameter, displays all the trace points that have triggered
11180 in the order they triggered.
11181 With the parameter @option{clear}, erases all current trace history records.
11182 With a @var{count} parameter, allocates space for that many
11186 @deffn {Command} {trace point} [@option{clear}|identifier]
11187 With no parameter, displays all trace point identifiers and how many times
11188 they have been triggered.
11189 With the parameter @option{clear}, erases all current trace point counters.
11190 With a numeric @var{identifier} parameter, creates a new a trace point counter
11191 and associates it with that identifier.
11193 @emph{Important:} The identifier and the trace point number
11194 are not related except by this command.
11195 These trace point numbers always start at zero (from server startup,
11196 or after @command{trace point clear}) and count up from there.
11200 @node JTAG Commands
11201 @chapter JTAG Commands
11202 @cindex JTAG Commands
11203 Most general purpose JTAG commands have been presented earlier.
11204 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
11205 Lower level JTAG commands, as presented here,
11206 may be needed to work with targets which require special
11207 attention during operations such as reset or initialization.
11209 To use these commands you will need to understand some
11210 of the basics of JTAG, including:
11213 @item A JTAG scan chain consists of a sequence of individual TAP
11214 devices such as a CPUs.
11215 @item Control operations involve moving each TAP through the same
11216 standard state machine (in parallel)
11217 using their shared TMS and clock signals.
11218 @item Data transfer involves shifting data through the chain of
11219 instruction or data registers of each TAP, writing new register values
11220 while the reading previous ones.
11221 @item Data register sizes are a function of the instruction active in
11222 a given TAP, while instruction register sizes are fixed for each TAP.
11223 All TAPs support a BYPASS instruction with a single bit data register.
11224 @item The way OpenOCD differentiates between TAP devices is by
11225 shifting different instructions into (and out of) their instruction
11229 @section Low Level JTAG Commands
11231 These commands are used by developers who need to access
11232 JTAG instruction or data registers, possibly controlling
11233 the order of TAP state transitions.
11234 If you're not debugging OpenOCD internals, or bringing up a
11235 new JTAG adapter or a new type of TAP device (like a CPU or
11236 JTAG router), you probably won't need to use these commands.
11237 In a debug session that doesn't use JTAG for its transport protocol,
11238 these commands are not available.
11240 @deffn {Command} {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
11241 Loads the data register of @var{tap} with a series of bit fields
11242 that specify the entire register.
11243 Each field is @var{numbits} bits long with
11244 a numeric @var{value} (hexadecimal encouraged).
11245 The return value holds the original value of each
11248 For example, a 38 bit number might be specified as one
11249 field of 32 bits then one of 6 bits.
11250 @emph{For portability, never pass fields which are more
11251 than 32 bits long. Many OpenOCD implementations do not
11252 support 64-bit (or larger) integer values.}
11254 All TAPs other than @var{tap} must be in BYPASS mode.
11255 The single bit in their data registers does not matter.
11257 When @var{tap_state} is specified, the JTAG state machine is left
11259 For example @sc{drpause} might be specified, so that more
11260 instructions can be issued before re-entering the @sc{run/idle} state.
11261 If the end state is not specified, the @sc{run/idle} state is entered.
11264 OpenOCD does not record information about data register lengths,
11265 so @emph{it is important that you get the bit field lengths right}.
11266 Remember that different JTAG instructions refer to different
11267 data registers, which may have different lengths.
11268 Moreover, those lengths may not be fixed;
11269 the SCAN_N instruction can change the length of
11270 the register accessed by the INTEST instruction
11271 (by connecting a different scan chain).
11275 @deffn {Command} {flush_count}
11276 Returns the number of times the JTAG queue has been flushed.
11277 This may be used for performance tuning.
11279 For example, flushing a queue over USB involves a
11280 minimum latency, often several milliseconds, which does
11281 not change with the amount of data which is written.
11282 You may be able to identify performance problems by finding
11283 tasks which waste bandwidth by flushing small transfers too often,
11284 instead of batching them into larger operations.
11287 @deffn {Command} {irscan} [tap instruction]+ [@option{-endstate} tap_state]
11288 For each @var{tap} listed, loads the instruction register
11289 with its associated numeric @var{instruction}.
11290 (The number of bits in that instruction may be displayed
11291 using the @command{scan_chain} command.)
11292 For other TAPs, a BYPASS instruction is loaded.
11294 When @var{tap_state} is specified, the JTAG state machine is left
11296 For example @sc{irpause} might be specified, so the data register
11297 can be loaded before re-entering the @sc{run/idle} state.
11298 If the end state is not specified, the @sc{run/idle} state is entered.
11301 OpenOCD currently supports only a single field for instruction
11302 register values, unlike data register values.
11303 For TAPs where the instruction register length is more than 32 bits,
11304 portable scripts currently must issue only BYPASS instructions.
11308 @deffn {Command} {pathmove} start_state [next_state ...]
11309 Start by moving to @var{start_state}, which
11310 must be one of the @emph{stable} states.
11311 Unless it is the only state given, this will often be the
11312 current state, so that no TCK transitions are needed.
11313 Then, in a series of single state transitions
11314 (conforming to the JTAG state machine) shift to
11315 each @var{next_state} in sequence, one per TCK cycle.
11316 The final state must also be stable.
11319 @deffn {Command} {runtest} @var{num_cycles}
11320 Move to the @sc{run/idle} state, and execute at least
11321 @var{num_cycles} of the JTAG clock (TCK).
11322 Instructions often need some time
11323 to execute before they take effect.
11326 @c tms_sequence (short|long)
11327 @c ... temporary, debug-only, other than USBprog bug workaround...
11329 @deffn {Command} {verify_ircapture} (@option{enable}|@option{disable})
11330 Verify values captured during @sc{ircapture} and returned
11331 during IR scans. Default is enabled, but this can be
11332 overridden by @command{verify_jtag}.
11333 This flag is ignored when validating JTAG chain configuration.
11336 @deffn {Command} {verify_jtag} (@option{enable}|@option{disable})
11337 Enables verification of DR and IR scans, to help detect
11338 programming errors. For IR scans, @command{verify_ircapture}
11339 must also be enabled.
11340 Default is enabled.
11343 @section TAP state names
11344 @cindex TAP state names
11346 The @var{tap_state} names used by OpenOCD in the @command{drscan},
11347 @command{irscan}, and @command{pathmove} commands are the same
11348 as those used in SVF boundary scan documents, except that
11349 SVF uses @sc{idle} instead of @sc{run/idle}.
11352 @item @b{RESET} ... @emph{stable} (with TMS high);
11353 acts as if TRST were pulsed
11354 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
11356 @item @b{DRCAPTURE}
11357 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
11358 through the data register
11360 @item @b{DRPAUSE} ... @emph{stable}; data register ready
11361 for update or more shifting
11365 @item @b{IRCAPTURE}
11366 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
11367 through the instruction register
11369 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
11370 for update or more shifting
11375 Note that only six of those states are fully ``stable'' in the
11376 face of TMS fixed (low except for @sc{reset})
11377 and a free-running JTAG clock. For all the
11378 others, the next TCK transition changes to a new state.
11381 @item From @sc{drshift} and @sc{irshift}, clock transitions will
11382 produce side effects by changing register contents. The values
11383 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
11384 may not be as expected.
11385 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
11386 choices after @command{drscan} or @command{irscan} commands,
11387 since they are free of JTAG side effects.
11388 @item @sc{run/idle} may have side effects that appear at non-JTAG
11389 levels, such as advancing the ARM9E-S instruction pipeline.
11390 Consult the documentation for the TAP(s) you are working with.
11393 @node Boundary Scan Commands
11394 @chapter Boundary Scan Commands
11396 One of the original purposes of JTAG was to support
11397 boundary scan based hardware testing.
11398 Although its primary focus is to support On-Chip Debugging,
11399 OpenOCD also includes some boundary scan commands.
11401 @section SVF: Serial Vector Format
11402 @cindex Serial Vector Format
11405 The Serial Vector Format, better known as @dfn{SVF}, is a
11406 way to represent JTAG test patterns in text files.
11407 In a debug session using JTAG for its transport protocol,
11408 OpenOCD supports running such test files.
11410 @deffn {Command} {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{[-]quiet}] @
11411 [@option{[-]nil}] [@option{[-]progress}] [@option{[-]ignore_error}]
11412 This issues a JTAG reset (Test-Logic-Reset) and then
11413 runs the SVF script from @file{filename}.
11415 Arguments can be specified in any order; the optional dash doesn't
11416 affect their semantics.
11420 @item @option{-tap @var{tapname}} ignore IR and DR headers and footers
11421 specified by the SVF file with HIR, TIR, HDR and TDR commands;
11422 instead, calculate them automatically according to the current JTAG
11423 chain configuration, targeting @var{tapname};
11424 @item @option{[-]quiet} do not log every command before execution;
11425 @item @option{[-]nil} ``dry run'', i.e., do not perform any operations
11426 on the real interface;
11427 @item @option{[-]progress} enable progress indication;
11428 @item @option{[-]ignore_error} continue execution despite TDO check
11433 @section XSVF: Xilinx Serial Vector Format
11434 @cindex Xilinx Serial Vector Format
11437 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
11438 binary representation of SVF which is optimized for use with
11440 In a debug session using JTAG for its transport protocol,
11441 OpenOCD supports running such test files.
11443 @quotation Important
11444 Not all XSVF commands are supported.
11447 @deffn {Command} {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
11448 This issues a JTAG reset (Test-Logic-Reset) and then
11449 runs the XSVF script from @file{filename}.
11450 When a @var{tapname} is specified, the commands are directed at
11452 When @option{virt2} is specified, the @sc{xruntest} command counts
11453 are interpreted as TCK cycles instead of microseconds.
11454 Unless the @option{quiet} option is specified,
11455 messages are logged for comments and some retries.
11458 The OpenOCD sources also include two utility scripts
11459 for working with XSVF; they are not currently installed
11460 after building the software.
11461 You may find them useful:
11464 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
11465 syntax understood by the @command{xsvf} command; see notes below.
11466 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
11467 understands the OpenOCD extensions.
11470 The input format accepts a handful of non-standard extensions.
11471 These include three opcodes corresponding to SVF extensions
11472 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
11473 two opcodes supporting a more accurate translation of SVF
11474 (XTRST, XWAITSTATE).
11475 If @emph{xsvfdump} shows a file is using those opcodes, it
11476 probably will not be usable with other XSVF tools.
11479 @section IPDBG: JTAG-Host server
11480 @cindex IPDBG JTAG-Host server
11483 IPDBG is a set of tools to debug IP-Cores. It comprises, among others, a logic analyzer and an arbitrary
11484 waveform generator. These are synthesize-able hardware descriptions of
11485 logic circuits in addition to software for control, visualization and further analysis.
11486 In a session using JTAG for its transport protocol, OpenOCD supports the function
11487 of a JTAG-Host. The JTAG-Host is needed to connect the circuit over JTAG to the
11488 control-software. For more details see @url{http://ipdbg.org}.
11490 @deffn {Command} {ipdbg} [@option{-start|-stop}] @option{-tap @var{tapname}} @option{-hub @var{ir_value} [@var{dr_length}]} [@option{-port @var{number}}] [@option{-tool @var{number}}] [@option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]}]
11491 Starts or stops a IPDBG JTAG-Host server. Arguments can be specified in any order.
11495 @item @option{-start|-stop} starts or stops a IPDBG JTAG-Host server (default: start).
11496 @item @option{-tap @var{tapname}} targeting the TAP @var{tapname}.
11497 @item @option{-hub @var{ir_value}} states that the JTAG hub is
11498 reachable with dr-scans while the JTAG instruction register has the value @var{ir_value}.
11499 @item @option{-port @var{number}} tcp port number where the JTAG-Host is listening.
11500 @item @option{-tool @var{number}} number of the tool/feature. These corresponds to the ports "data_(up/down)_(0..6)" at the JtagHub.
11501 @item @option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]} On some devices, the user data-register is only reachable if there is a
11502 specific value in a second dr. This second dr is called vir (virtual ir). With this parameter given, the IPDBG satisfies this condition prior an
11503 access to the IPDBG-Hub. The value shifted into the vir is given by the first parameter @var{vir_value} (default: 0x11). The second
11504 parameter @var{length} is the length of the vir data register (default: 5). With the @var{instr_code} (default: 0x00e) parameter the ir value to
11505 shift data through vir can be configured.
11511 ipdbg -start -tap xc6s.tap -hub 0x02 -port 4242 -tool 4
11513 Starts a server listening on tcp-port 4242 which connects to tool 4.
11514 The connection is through the TAP of a Xilinx Spartan 6 on USER1 instruction (tested with a papillion pro board).
11517 ipdbg -start -tap 10m50.tap -hub 0x00C -vir -port 60000 -tool 1
11519 Starts a server listening on tcp-port 60000 which connects to tool 1 (data_up_1/data_down_1).
11520 The connection is through the TAP of a Intel MAX10 virtual jtag component (sld_instance_index is 0; sld_ir_width is smaller than 5).
11522 @node Utility Commands
11523 @chapter Utility Commands
11524 @cindex Utility Commands
11526 @section RAM testing
11527 @cindex RAM testing
11529 There is often a need to stress-test random access memory (RAM) for
11530 errors. OpenOCD comes with a Tcl implementation of well-known memory
11531 testing procedures allowing the detection of all sorts of issues with
11532 electrical wiring, defective chips, PCB layout and other common
11535 To use them, you usually need to initialise your RAM controller first;
11536 consult your SoC's documentation to get the recommended list of
11537 register operations and translate them to the corresponding
11538 @command{mww}/@command{mwb} commands.
11540 Load the memory testing functions with
11543 source [find tools/memtest.tcl]
11546 to get access to the following facilities:
11548 @deffn {Command} {memTestDataBus} address
11549 Test the data bus wiring in a memory region by performing a walking
11550 1's test at a fixed address within that region.
11553 @deffn {Command} {memTestAddressBus} baseaddress size
11554 Perform a walking 1's test on the relevant bits of the address and
11555 check for aliasing. This test will find single-bit address failures
11556 such as stuck-high, stuck-low, and shorted pins.
11559 @deffn {Command} {memTestDevice} baseaddress size
11560 Test the integrity of a physical memory device by performing an
11561 increment/decrement test over the entire region. In the process every
11562 storage bit in the device is tested as zero and as one.
11565 @deffn {Command} {runAllMemTests} baseaddress size
11566 Run all of the above tests over a specified memory region.
11569 @section Firmware recovery helpers
11570 @cindex Firmware recovery
11572 OpenOCD includes an easy-to-use script to facilitate mass-market
11573 devices recovery with JTAG.
11575 For quickstart instructions run:
11577 openocd -f tools/firmware-recovery.tcl -c firmware_help
11580 @node GDB and OpenOCD
11581 @chapter GDB and OpenOCD
11583 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
11584 to debug remote targets.
11585 Setting up GDB to work with OpenOCD can involve several components:
11588 @item The OpenOCD server support for GDB may need to be configured.
11589 @xref{gdbconfiguration,,GDB Configuration}.
11590 @item GDB's support for OpenOCD may need configuration,
11591 as shown in this chapter.
11592 @item If you have a GUI environment like Eclipse,
11593 that also will probably need to be configured.
11596 Of course, the version of GDB you use will need to be one which has
11597 been built to know about the target CPU you're using. It's probably
11598 part of the tool chain you're using. For example, if you are doing
11599 cross-development for ARM on an x86 PC, instead of using the native
11600 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
11601 if that's the tool chain used to compile your code.
11603 @section Connecting to GDB
11604 @cindex Connecting to GDB
11605 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
11606 instance GDB 6.3 has a known bug that produces bogus memory access
11607 errors, which has since been fixed; see
11608 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
11610 OpenOCD can communicate with GDB in two ways:
11614 A socket (TCP/IP) connection is typically started as follows:
11616 target extended-remote localhost:3333
11618 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
11620 The extended remote protocol is a super-set of the remote protocol and should
11621 be the preferred choice. More details are available in GDB documentation
11622 @url{https://sourceware.org/gdb/onlinedocs/gdb/Connecting.html}
11624 To speed-up typing, any GDB command can be abbreviated, including the extended
11625 remote command above that becomes:
11630 @b{Note:} If any backward compatibility issue requires using the old remote
11631 protocol in place of the extended remote one, the former protocol is still
11632 available through the command:
11634 target remote localhost:3333
11638 A pipe connection is typically started as follows:
11640 target extended-remote | \
11641 openocd -c "gdb_port pipe; log_output openocd.log"
11643 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
11644 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
11645 session. log_output sends the log output to a file to ensure that the pipe is
11646 not saturated when using higher debug level outputs.
11649 To list the available OpenOCD commands type @command{monitor help} on the
11652 @section Sample GDB session startup
11654 With the remote protocol, GDB sessions start a little differently
11655 than they do when you're debugging locally.
11656 Here's an example showing how to start a debug session with a
11658 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
11659 Most programs would be written into flash (address 0) and run from there.
11662 $ arm-none-eabi-gdb example.elf
11663 (gdb) target extended-remote localhost:3333
11664 Remote debugging using localhost:3333
11666 (gdb) monitor reset halt
11669 Loading section .vectors, size 0x100 lma 0x20000000
11670 Loading section .text, size 0x5a0 lma 0x20000100
11671 Loading section .data, size 0x18 lma 0x200006a0
11672 Start address 0x2000061c, load size 1720
11673 Transfer rate: 22 KB/sec, 573 bytes/write.
11679 You could then interrupt the GDB session to make the program break,
11680 type @command{where} to show the stack, @command{list} to show the
11681 code around the program counter, @command{step} through code,
11682 set breakpoints or watchpoints, and so on.
11684 @section Configuring GDB for OpenOCD
11686 OpenOCD supports the gdb @option{qSupported} packet, this enables information
11687 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
11688 packet size and the device's memory map.
11689 You do not need to configure the packet size by hand,
11690 and the relevant parts of the memory map should be automatically
11691 set up when you declare (NOR) flash banks.
11693 However, there are other things which GDB can't currently query.
11694 You may need to set those up by hand.
11695 As OpenOCD starts up, you will often see a line reporting
11699 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
11702 You can pass that information to GDB with these commands:
11705 set remote hardware-breakpoint-limit 6
11706 set remote hardware-watchpoint-limit 4
11709 With that particular hardware (Cortex-M3) the hardware breakpoints
11710 only work for code running from flash memory. Most other ARM systems
11711 do not have such restrictions.
11713 Rather than typing such commands interactively, you may prefer to
11714 save them in a file and have GDB execute them as it starts, perhaps
11715 using a @file{.gdbinit} in your project directory or starting GDB
11716 using @command{gdb -x filename}.
11718 @section Programming using GDB
11719 @cindex Programming using GDB
11720 @anchor{programmingusinggdb}
11722 By default the target memory map is sent to GDB. This can be disabled by
11723 the following OpenOCD configuration option:
11725 gdb_memory_map disable
11727 For this to function correctly a valid flash configuration must also be set
11728 in OpenOCD. For faster performance you should also configure a valid
11731 Informing GDB of the memory map of the target will enable GDB to protect any
11732 flash areas of the target and use hardware breakpoints by default. This means
11733 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
11734 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
11736 To view the configured memory map in GDB, use the GDB command @option{info mem}.
11737 All other unassigned addresses within GDB are treated as RAM.
11739 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
11740 This can be changed to the old behaviour by using the following GDB command
11742 set mem inaccessible-by-default off
11745 If @command{gdb_flash_program enable} is also used, GDB will be able to
11746 program any flash memory using the vFlash interface.
11748 GDB will look at the target memory map when a load command is given, if any
11749 areas to be programmed lie within the target flash area the vFlash packets
11752 If the target needs configuring before GDB programming, set target
11753 event gdb-flash-erase-start:
11755 $_TARGETNAME configure -event gdb-flash-erase-start BODY
11757 @xref{targetevents,,Target Events}, for other GDB programming related events.
11759 To verify any flash programming the GDB command @option{compare-sections}
11762 @section Using GDB as a non-intrusive memory inspector
11763 @cindex Using GDB as a non-intrusive memory inspector
11764 @anchor{gdbmeminspect}
11766 If your project controls more than a blinking LED, let's say a heavy industrial
11767 robot or an experimental nuclear reactor, stopping the controlling process
11768 just because you want to attach GDB is not a good option.
11770 OpenOCD does not support GDB non-stop mode (might be implemented in the future).
11771 Though there is a possible setup where the target does not get stopped
11772 and GDB treats it as it were running.
11773 If the target supports background access to memory while it is running,
11774 you can use GDB in this mode to inspect memory (mainly global variables)
11775 without any intrusion of the target process.
11777 Remove default setting of gdb-attach event. @xref{targetevents,,Target Events}.
11778 Place following command after target configuration:
11780 $_TARGETNAME configure -event gdb-attach @{@}
11783 If any of installed flash banks does not support probe on running target,
11784 switch off gdb_memory_map:
11786 gdb_memory_map disable
11789 Ensure GDB is configured without interrupt-on-connect.
11790 Some GDB versions set it by default, some does not.
11792 set remote interrupt-on-connect off
11795 If you switched gdb_memory_map off, you may want to setup GDB memory map
11796 manually or issue @command{set mem inaccessible-by-default off}
11798 Now you can issue GDB command @command{target extended-remote ...} and inspect memory
11799 of a running target. Do not use GDB commands @command{continue},
11800 @command{step} or @command{next} as they synchronize GDB with your target
11801 and GDB would require stopping the target to get the prompt back.
11803 Do not use this mode under an IDE like Eclipse as it caches values of
11804 previously shown variables.
11806 It's also possible to connect more than one GDB to the same target by the
11807 target's configuration option @code{-gdb-max-connections}. This allows, for
11808 example, one GDB to run a script that continuously polls a set of variables
11809 while other GDB can be used interactively. Be extremely careful in this case,
11810 because the two GDB can easily get out-of-sync.
11812 @section RTOS Support
11813 @cindex RTOS Support
11814 @anchor{gdbrtossupport}
11816 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
11817 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
11819 @xref{Threads, Debugging Programs with Multiple Threads,
11820 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
11823 @* An example setup is below:
11826 $_TARGETNAME configure -rtos auto
11829 This will attempt to auto detect the RTOS within your application.
11831 Currently supported rtos's include:
11833 @item @option{eCos}
11834 @item @option{ThreadX}
11835 @item @option{FreeRTOS}
11836 @item @option{linux}
11837 @item @option{ChibiOS}
11838 @item @option{embKernel}
11840 @item @option{uCOS-III}
11841 @item @option{nuttx}
11842 @item @option{RIOT}
11843 @item @option{hwthread} (This is not an actual RTOS. @xref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.)
11844 @item @option{Zephyr}
11847 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
11848 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
11852 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
11853 @item ThreadX symbols
11854 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
11855 @item FreeRTOS symbols
11857 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
11858 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
11859 uxCurrentNumberOfTasks, uxTopUsedPriority.
11861 @item linux symbols
11863 @item ChibiOS symbols
11864 rlist, ch_debug, chSysInit.
11865 @item embKernel symbols
11866 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
11867 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
11869 _mqx_kernel_data, MQX_init_struct.
11870 @item uC/OS-III symbols
11871 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty.
11872 @item nuttx symbols
11873 g_readytorun, g_tasklisttable.
11876 sched_threads, sched_num_threads, sched_active_pid, max_threads,
11879 @item Zephyr symbols
11880 _kernel, _kernel_openocd_offsets, _kernel_openocd_size_t_size
11883 For most RTOS supported the above symbols will be exported by default. However for
11884 some, eg. FreeRTOS, uC/OS-III and Zephyr, extra steps must be taken.
11886 Zephyr must be compiled with the DEBUG_THREAD_INFO option. This will generate some symbols
11887 with information needed in order to build the list of threads.
11889 FreeRTOS and uC/OS-III RTOSes may require additional OpenOCD-specific file to be linked
11890 along with the project:
11894 contrib/rtos-helpers/FreeRTOS-openocd.c
11896 contrib/rtos-helpers/uCOS-III-openocd.c
11899 @anchor{usingopenocdsmpwithgdb}
11900 @section Using OpenOCD SMP with GDB
11904 OpenOCD includes a pseudo RTOS called @emph{hwthread} that presents CPU cores
11905 ("hardware threads") in an SMP system as threads to GDB. With this extension,
11906 GDB can be used to inspect the state of an SMP system in a natural way.
11907 After halting the system, using the GDB command @command{info threads} will
11908 list the context of each active CPU core in the system. GDB's @command{thread}
11909 command can be used to switch the view to a different CPU core.
11910 The @command{step} and @command{stepi} commands can be used to step a specific core
11911 while other cores are free-running or remain halted, depending on the
11912 scheduler-locking mode configured in GDB.
11914 @node Tcl Scripting API
11915 @chapter Tcl Scripting API
11916 @cindex Tcl Scripting API
11917 @cindex Tcl scripts
11920 Tcl commands are stateless; e.g. the @command{telnet} command has
11921 a concept of currently active target, the Tcl API proc's take this sort
11922 of state information as an argument to each proc.
11924 There are three main types of return values: single value, name value
11925 pair list and lists.
11927 Name value pair. The proc 'foo' below returns a name/value pair
11931 > set foo(me) Duane
11932 > set foo(you) Oyvind
11933 > set foo(mouse) Micky
11934 > set foo(duck) Donald
11946 me Duane you Oyvind mouse Micky duck Donald
11949 Thus, to get the names of the associative array is easy:
11952 foreach { name value } [set foo] {
11953 puts "Name: $name, Value: $value"
11957 Lists returned should be relatively small. Otherwise, a range
11958 should be passed in to the proc in question.
11960 @section Internal low-level Commands
11962 By "low-level", we mean commands that a human would typically not
11966 @item @b{flash banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
11968 Return information about the flash banks
11970 @item @b{capture} <@var{command}>
11972 Run <@var{command}> and return full log output that was produced during
11973 its execution. Example:
11976 > capture "reset init"
11981 OpenOCD commands can consist of two words, e.g. "flash banks". The
11982 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
11983 called "flash_banks".
11985 @section Tcl RPC server
11988 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
11989 commands and receive the results.
11991 To access it, your application needs to connect to a configured TCP port
11992 (see @command{tcl_port}). Then it can pass any string to the
11993 interpreter terminating it with @code{0x1a} and wait for the return
11994 value (it will be terminated with @code{0x1a} as well). This can be
11995 repeated as many times as desired without reopening the connection.
11997 It is not needed anymore to prefix the OpenOCD commands with
11998 @code{ocd_} to get the results back. But sometimes you might need the
11999 @command{capture} command.
12001 See @file{contrib/rpc_examples/} for specific client implementations.
12003 @section Tcl RPC server notifications
12004 @cindex RPC Notifications
12006 Notifications are sent asynchronously to other commands being executed over
12007 the RPC server, so the port must be polled continuously.
12009 Target event, state and reset notifications are emitted as Tcl associative arrays
12010 in the following format.
12013 type target_event event [event-name]
12014 type target_state state [state-name]
12015 type target_reset mode [reset-mode]
12018 @deffn {Command} {tcl_notifications} [on/off]
12019 Toggle output of target notifications to the current Tcl RPC server.
12020 Only available from the Tcl RPC server.
12025 @section Tcl RPC server trace output
12026 @cindex RPC trace output
12028 Trace data is sent asynchronously to other commands being executed over
12029 the RPC server, so the port must be polled continuously.
12031 Target trace data is emitted as a Tcl associative array in the following format.
12034 type target_trace data [trace-data-hex-encoded]
12037 @deffn {Command} {tcl_trace} [on/off]
12038 Toggle output of target trace data to the current Tcl RPC server.
12039 Only available from the Tcl RPC server.
12042 See an example application here:
12043 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
12052 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
12054 @cindex adaptive clocking
12057 In digital circuit design it is often referred to as ``clock
12058 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
12059 operating at some speed, your CPU target is operating at another.
12060 The two clocks are not synchronised, they are ``asynchronous''
12062 In order for the two to work together they must be synchronised
12063 well enough to work; JTAG can't go ten times faster than the CPU,
12064 for example. There are 2 basic options:
12067 Use a special "adaptive clocking" circuit to change the JTAG
12068 clock rate to match what the CPU currently supports.
12070 The JTAG clock must be fixed at some speed that's enough slower than
12071 the CPU clock that all TMS and TDI transitions can be detected.
12074 @b{Does this really matter?} For some chips and some situations, this
12075 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
12076 the CPU has no difficulty keeping up with JTAG.
12077 Startup sequences are often problematic though, as are other
12078 situations where the CPU clock rate changes (perhaps to save
12081 For example, Atmel AT91SAM chips start operation from reset with
12082 a 32kHz system clock. Boot firmware may activate the main oscillator
12083 and PLL before switching to a faster clock (perhaps that 500 MHz
12085 If you're using JTAG to debug that startup sequence, you must slow
12086 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
12087 JTAG can use a faster clock.
12089 Consider also debugging a 500MHz ARM926 hand held battery powered
12090 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
12091 clock, between keystrokes unless it has work to do. When would
12092 that 5 MHz JTAG clock be usable?
12094 @b{Solution #1 - A special circuit}
12096 In order to make use of this,
12097 your CPU, board, and JTAG adapter must all support the RTCK
12098 feature. Not all of them support this; keep reading!
12100 The RTCK ("Return TCK") signal in some ARM chips is used to help with
12101 this problem. ARM has a good description of the problem described at
12102 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
12103 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
12104 work? / how does adaptive clocking work?''.
12106 The nice thing about adaptive clocking is that ``battery powered hand
12107 held device example'' - the adaptiveness works perfectly all the
12108 time. One can set a break point or halt the system in the deep power
12109 down code, slow step out until the system speeds up.
12111 Note that adaptive clocking may also need to work at the board level,
12112 when a board-level scan chain has multiple chips.
12113 Parallel clock voting schemes are good way to implement this,
12114 both within and between chips, and can easily be implemented
12116 It's not difficult to have logic fan a module's input TCK signal out
12117 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
12118 back with the right polarity before changing the output RTCK signal.
12119 Texas Instruments makes some clock voting logic available
12120 for free (with no support) in VHDL form; see
12121 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
12123 @b{Solution #2 - Always works - but may be slower}
12125 Often this is a perfectly acceptable solution.
12127 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
12128 the target clock speed. But what that ``magic division'' is varies
12129 depending on the chips on your board.
12130 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
12131 ARM11 cores use an 8:1 division.
12132 @b{Xilinx rule of thumb} is 1/12 the clock speed.
12134 Note: most full speed FT2232 based JTAG adapters are limited to a
12135 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
12136 often support faster clock rates (and adaptive clocking).
12138 You can still debug the 'low power' situations - you just need to
12139 either use a fixed and very slow JTAG clock rate ... or else
12140 manually adjust the clock speed at every step. (Adjusting is painful
12141 and tedious, and is not always practical.)
12143 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
12144 have a special debug mode in your application that does a ``high power
12145 sleep''. If you are careful - 98% of your problems can be debugged
12148 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
12149 operation in your idle loops even if you don't otherwise change the CPU
12151 That operation gates the CPU clock, and thus the JTAG clock; which
12152 prevents JTAG access. One consequence is not being able to @command{halt}
12153 cores which are executing that @emph{wait for interrupt} operation.
12155 To set the JTAG frequency use the command:
12158 # Example: 1.234MHz
12163 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
12165 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
12166 around Windows filenames.
12179 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
12181 Make sure you have Cygwin installed, or at least a version of OpenOCD that
12182 claims to come with all the necessary DLLs. When using Cygwin, try launching
12183 OpenOCD from the Cygwin shell.
12185 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a front-end like Insight or
12186 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
12187 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
12189 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
12190 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
12191 software breakpoints consume one of the two available hardware breakpoints.
12193 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
12195 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
12196 clock at the time you're programming the flash. If you've specified the crystal's
12197 frequency, make sure the PLL is disabled. If you've specified the full core speed
12198 (e.g. 60MHz), make sure the PLL is enabled.
12200 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
12201 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
12202 out while waiting for end of scan, rtck was disabled".
12204 Make sure your PC's parallel port operates in EPP mode. You might have to try several
12205 settings in your PC BIOS (ECP, EPP, and different versions of those).
12207 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
12208 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
12209 memory read caused data abort".
12211 The errors are non-fatal, and are the result of GDB trying to trace stack frames
12212 beyond the last valid frame. It might be possible to prevent this by setting up
12213 a proper "initial" stack frame, if you happen to know what exactly has to
12214 be done, feel free to add this here.
12216 @b{Simple:} In your startup code - push 8 registers of zeros onto the
12217 stack before calling main(). What GDB is doing is ``climbing'' the run
12218 time stack by reading various values on the stack using the standard
12219 call frame for the target. GDB keeps going - until one of 2 things
12220 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
12221 stackframes have been processed. By pushing zeros on the stack, GDB
12224 @b{Debugging Interrupt Service Routines} - In your ISR before you call
12225 your C code, do the same - artificially push some zeros onto the stack,
12226 remember to pop them off when the ISR is done.
12228 @b{Also note:} If you have a multi-threaded operating system, they
12229 often do not @b{in the interest of saving memory} waste these few
12233 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
12234 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
12236 This warning doesn't indicate any serious problem, as long as you don't want to
12237 debug your core right out of reset. Your .cfg file specified @option{reset_config
12238 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
12239 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
12240 independently. With this setup, it's not possible to halt the core right out of
12241 reset, everything else should work fine.
12243 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
12244 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
12245 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
12246 quit with an error message. Is there a stability issue with OpenOCD?
12248 No, this is not a stability issue concerning OpenOCD. Most users have solved
12249 this issue by simply using a self-powered USB hub, which they connect their
12250 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
12251 supply stable enough for the Amontec JTAGkey to be operated.
12253 @b{Laptops running on battery have this problem too...}
12255 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
12256 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
12257 What does that mean and what might be the reason for this?
12259 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
12260 has closed the connection to OpenOCD. This might be a GDB issue.
12262 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
12263 are described, there is a parameter for specifying the clock frequency
12264 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
12265 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
12266 specified in kilohertz. However, I do have a quartz crystal of a
12267 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
12268 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
12271 No. The clock frequency specified here must be given as an integral number.
12272 However, this clock frequency is used by the In-Application-Programming (IAP)
12273 routines of the LPC2000 family only, which seems to be very tolerant concerning
12274 the given clock frequency, so a slight difference between the specified clock
12275 frequency and the actual clock frequency will not cause any trouble.
12277 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
12279 Well, yes and no. Commands can be given in arbitrary order, yet the
12280 devices listed for the JTAG scan chain must be given in the right
12281 order (jtag newdevice), with the device closest to the TDO-Pin being
12282 listed first. In general, whenever objects of the same type exist
12283 which require an index number, then these objects must be given in the
12284 right order (jtag newtap, targets and flash banks - a target
12285 references a jtag newtap and a flash bank references a target).
12287 You can use the ``scan_chain'' command to verify and display the tap order.
12289 Also, some commands can't execute until after @command{init} has been
12290 processed. Such commands include @command{nand probe} and everything
12291 else that needs to write to controller registers, perhaps for setting
12292 up DRAM and loading it with code.
12294 @anchor{faqtaporder}
12295 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
12298 Yes; whenever you have more than one, you must declare them in
12299 the same order used by the hardware.
12301 Many newer devices have multiple JTAG TAPs. For example:
12302 STMicroelectronics STM32 chips have two TAPs, a ``boundary scan TAP'' and
12303 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
12304 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
12305 connected to the boundary scan TAP, which then connects to the
12306 Cortex-M3 TAP, which then connects to the TDO pin.
12308 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
12309 (2) The boundary scan TAP. If your board includes an additional JTAG
12310 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
12311 place it before or after the STM32 chip in the chain. For example:
12314 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
12315 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
12316 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
12317 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
12318 @item Xilinx TDO Pin -> OpenOCD TDO (input)
12321 The ``jtag device'' commands would thus be in the order shown below. Note:
12324 @item jtag newtap Xilinx tap -irlen ...
12325 @item jtag newtap stm32 cpu -irlen ...
12326 @item jtag newtap stm32 bs -irlen ...
12327 @item # Create the debug target and say where it is
12328 @item target create stm32.cpu -chain-position stm32.cpu ...
12332 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
12333 log file, I can see these error messages: Error: arm7_9_common.c:561
12334 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
12340 @node Tcl Crash Course
12341 @chapter Tcl Crash Course
12344 Not everyone knows Tcl - this is not intended to be a replacement for
12345 learning Tcl, the intent of this chapter is to give you some idea of
12346 how the Tcl scripts work.
12348 This chapter is written with two audiences in mind. (1) OpenOCD users
12349 who need to understand a bit more of how Jim-Tcl works so they can do
12350 something useful, and (2) those that want to add a new command to
12353 @section Tcl Rule #1
12354 There is a famous joke, it goes like this:
12356 @item Rule #1: The wife is always correct
12357 @item Rule #2: If you think otherwise, See Rule #1
12360 The Tcl equal is this:
12363 @item Rule #1: Everything is a string
12364 @item Rule #2: If you think otherwise, See Rule #1
12367 As in the famous joke, the consequences of Rule #1 are profound. Once
12368 you understand Rule #1, you will understand Tcl.
12370 @section Tcl Rule #1b
12371 There is a second pair of rules.
12373 @item Rule #1: Control flow does not exist. Only commands
12374 @* For example: the classic FOR loop or IF statement is not a control
12375 flow item, they are commands, there is no such thing as control flow
12377 @item Rule #2: If you think otherwise, See Rule #1
12378 @* Actually what happens is this: There are commands that by
12379 convention, act like control flow key words in other languages. One of
12380 those commands is the word ``for'', another command is ``if''.
12383 @section Per Rule #1 - All Results are strings
12384 Every Tcl command results in a string. The word ``result'' is used
12385 deliberately. No result is just an empty string. Remember: @i{Rule #1 -
12386 Everything is a string}
12388 @section Tcl Quoting Operators
12389 In life of a Tcl script, there are two important periods of time, the
12390 difference is subtle.
12393 @item Evaluation Time
12396 The two key items here are how ``quoted things'' work in Tcl. Tcl has
12397 three primary quoting constructs, the [square-brackets] the
12398 @{curly-braces@} and ``double-quotes''
12400 By now you should know $VARIABLES always start with a $DOLLAR
12401 sign. BTW: To set a variable, you actually use the command ``set'', as
12402 in ``set VARNAME VALUE'' much like the ancient BASIC language ``let x
12403 = 1'' statement, but without the equal sign.
12406 @item @b{[square-brackets]}
12407 @* @b{[square-brackets]} are command substitutions. It operates much
12408 like Unix Shell `back-ticks`. The result of a [square-bracket]
12409 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
12410 string}. These two statements are roughly identical:
12414 echo "The Date is: $X"
12417 puts "The Date is: $X"
12419 @item @b{``double-quoted-things''}
12420 @* @b{``double-quoted-things''} are just simply quoted
12421 text. $VARIABLES and [square-brackets] are expanded in place - the
12422 result however is exactly 1 string. @i{Remember Rule #1 - Everything
12426 puts "It is now \"[date]\", $x is in 1 hour"
12428 @item @b{@{Curly-Braces@}}
12429 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
12430 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
12431 'single-quote' operators in BASH shell scripts, with the added
12432 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
12433 nested 3 times@}@}@} NOTE: [date] is a bad example;
12434 at this writing, Jim/OpenOCD does not have a date command.
12437 @section Consequences of Rule 1/2/3/4
12439 The consequences of Rule 1 are profound.
12441 @subsection Tokenisation & Execution.
12443 Of course, whitespace, blank lines and #comment lines are handled in
12446 As a script is parsed, each (multi) line in the script file is
12447 tokenised and according to the quoting rules. After tokenisation, that
12448 line is immediately executed.
12450 Multi line statements end with one or more ``still-open''
12451 @{curly-braces@} which - eventually - closes a few lines later.
12453 @subsection Command Execution
12455 Remember earlier: There are no ``control flow''
12456 statements in Tcl. Instead there are COMMANDS that simply act like
12457 control flow operators.
12459 Commands are executed like this:
12462 @item Parse the next line into (argc) and (argv[]).
12463 @item Look up (argv[0]) in a table and call its function.
12464 @item Repeat until End Of File.
12467 It sort of works like this:
12470 ReadAndParse( &argc, &argv );
12472 cmdPtr = LookupCommand( argv[0] );
12474 (*cmdPtr->Execute)( argc, argv );
12478 When the command ``proc'' is parsed (which creates a procedure
12479 function) it gets 3 parameters on the command line. @b{1} the name of
12480 the proc (function), @b{2} the list of parameters, and @b{3} the body
12481 of the function. Note the choice of words: LIST and BODY. The PROC
12482 command stores these items in a table somewhere so it can be found by
12483 ``LookupCommand()''
12485 @subsection The FOR command
12487 The most interesting command to look at is the FOR command. In Tcl,
12488 the FOR command is normally implemented in C. Remember, FOR is a
12489 command just like any other command.
12491 When the ascii text containing the FOR command is parsed, the parser
12492 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
12496 @item The ascii text 'for'
12497 @item The start text
12498 @item The test expression
12499 @item The next text
12500 @item The body text
12503 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
12504 Remember @i{Rule #1 - Everything is a string.} The key point is this:
12505 Often many of those parameters are in @{curly-braces@} - thus the
12506 variables inside are not expanded or replaced until later.
12508 Remember that every Tcl command looks like the classic ``main( argc,
12509 argv )'' function in C. In JimTCL - they actually look like this:
12513 MyCommand( Jim_Interp *interp,
12515 Jim_Obj * const *argvs );
12518 Real Tcl is nearly identical. Although the newer versions have
12519 introduced a byte-code parser and interpreter, but at the core, it
12520 still operates in the same basic way.
12522 @subsection FOR command implementation
12524 To understand Tcl it is perhaps most helpful to see the FOR
12525 command. Remember, it is a COMMAND not a control flow structure.
12527 In Tcl there are two underlying C helper functions.
12529 Remember Rule #1 - You are a string.
12531 The @b{first} helper parses and executes commands found in an ascii
12532 string. Commands can be separated by semicolons, or newlines. While
12533 parsing, variables are expanded via the quoting rules.
12535 The @b{second} helper evaluates an ascii string as a numerical
12536 expression and returns a value.
12538 Here is an example of how the @b{FOR} command could be
12539 implemented. The pseudo code below does not show error handling.
12541 void Execute_AsciiString( void *interp, const char *string );
12543 int Evaluate_AsciiExpression( void *interp, const char *string );
12546 MyForCommand( void *interp,
12551 SetResult( interp, "WRONG number of parameters");
12555 // argv[0] = the ascii string just like C
12557 // Execute the start statement.
12558 Execute_AsciiString( interp, argv[1] );
12560 // Top of loop test
12562 i = Evaluate_AsciiExpression(interp, argv[2]);
12566 // Execute the body
12567 Execute_AsciiString( interp, argv[3] );
12569 // Execute the LOOP part
12570 Execute_AsciiString( interp, argv[4] );
12574 SetResult( interp, "" );
12579 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
12580 in the same basic way.
12582 @section OpenOCD Tcl Usage
12584 @subsection source and find commands
12585 @b{Where:} In many configuration files
12586 @* Example: @b{ source [find FILENAME] }
12587 @*Remember the parsing rules
12589 @item The @command{find} command is in square brackets,
12590 and is executed with the parameter FILENAME. It should find and return
12591 the full path to a file with that name; it uses an internal search path.
12592 The RESULT is a string, which is substituted into the command line in
12593 place of the bracketed @command{find} command.
12594 (Don't try to use a FILENAME which includes the "#" character.
12595 That character begins Tcl comments.)
12596 @item The @command{source} command is executed with the resulting filename;
12597 it reads a file and executes as a script.
12599 @subsection format command
12600 @b{Where:} Generally occurs in numerous places.
12601 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
12607 puts [format "The answer: %d" [expr @{$x * $y@}]]
12610 @item The SET command creates 2 variables, X and Y.
12611 @item The double [nested] EXPR command performs math
12612 @* The EXPR command produces numerical result as a string.
12613 @* Refer to Rule #1
12614 @item The format command is executed, producing a single string
12615 @* Refer to Rule #1.
12616 @item The PUTS command outputs the text.
12618 @subsection Body or Inlined Text
12619 @b{Where:} Various TARGET scripts.
12622 proc someproc @{@} @{
12623 ... multiple lines of stuff ...
12625 $_TARGETNAME configure -event FOO someproc
12626 #2 Good - no variables
12627 $_TARGETNAME configure -event foo "this ; that;"
12628 #3 Good Curly Braces
12629 $_TARGETNAME configure -event FOO @{
12630 puts "Time: [date]"
12632 #4 DANGER DANGER DANGER
12633 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
12636 @item The $_TARGETNAME is an OpenOCD variable convention.
12637 @*@b{$_TARGETNAME} represents the last target created, the value changes
12638 each time a new target is created. Remember the parsing rules. When
12639 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
12640 the name of the target which happens to be a TARGET (object)
12642 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
12643 @*There are 4 examples:
12645 @item The TCLBODY is a simple string that happens to be a proc name
12646 @item The TCLBODY is several simple commands separated by semicolons
12647 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
12648 @item The TCLBODY is a string with variables that get expanded.
12651 In the end, when the target event FOO occurs the TCLBODY is
12652 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
12653 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
12655 Remember the parsing rules. In case #3, @{curly-braces@} mean the
12656 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
12657 and the text is evaluated. In case #4, they are replaced before the
12658 ``Target Object Command'' is executed. This occurs at the same time
12659 $_TARGETNAME is replaced. In case #4 the date will never
12660 change. @{BTW: [date] is a bad example; at this writing,
12661 Jim/OpenOCD does not have a date command@}
12663 @subsection Global Variables
12664 @b{Where:} You might discover this when writing your own procs @* In
12665 simple terms: Inside a PROC, if you need to access a global variable
12666 you must say so. See also ``upvar''. Example:
12668 proc myproc @{ @} @{
12669 set y 0 #Local variable Y
12670 global x #Global variable X
12671 puts [format "X=%d, Y=%d" $x $y]
12674 @section Other Tcl Hacks
12675 @b{Dynamic variable creation}
12677 # Dynamically create a bunch of variables.
12678 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr @{$x + 1@}]@} @{
12680 set vn [format "BIT%d" $x]
12684 set $vn [expr @{1 << $x@}]
12687 @b{Dynamic proc/command creation}
12689 # One "X" function - 5 uart functions.
12690 foreach who @{A B C D E@}
12691 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
12696 @appendix The GNU Free Documentation License.
12699 @node OpenOCD Concept Index
12700 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
12701 @comment case issue with ``Index.html'' and ``index.html''
12702 @comment Occurs when creating ``--html --no-split'' output
12703 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
12704 @unnumbered OpenOCD Concept Index
12708 @node Command and Driver Index
12709 @unnumbered Command and Driver Index