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ADIv5: remove ATOMIC/COMPOSITE interface mode
[openocd.git] / src / target / arm_adi_v5.c
blob819dd290fd83990c231adb769c4fb396dfbc659a
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
17 * *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
22 * *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
28
29 /**
30 * @file
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
36 *
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
45 *
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
56 */
57
58 /*
59 * Relevant specifications from ARM include:
60 *
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
63 *
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
66 */
67
68 #ifdef HAVE_CONFIG_H
69 #include "config.h"
70 #endif
71
72 #include "arm_adi_v5.h"
73 #include <helper/time_support.h>
74
75
76 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
77
78 /*
79 uint32_t tar_block_size(uint32_t address)
80 Return the largest block starting at address that does not cross a tar block size alignment boundary
81 */
82 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
83 {
84 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
85 }
86
87 /***************************************************************************
88 * *
89 * DPACC and APACC scanchain access through JTAG-DP *
90 * *
91 ***************************************************************************/
92
93 /**
94 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
95 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
96 * discusses operations which access these registers.
97 *
98 * Note that only one scan is performed. If RnW is set, a separate scan
99 * will be needed to collect the data which was read; the "invalue" collects
100 * the posted result of a preceding operation, not the current one.
101 *
102 * @param swjdp the DAP
103 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
104 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
105 * SELECT register has more addressing bits.
106 * @param RnW false iff outvalue will be written to the DP or AP
107 * @param outvalue points to a 32-bit (little-endian) integer
108 * @param invalue NULL, or points to a 32-bit (little-endian) integer
109 * @param ack points to where the three bit JTAG_ACK_* code will be stored
110 */
111 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
112 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
113 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
114 {
115 struct arm_jtag *jtag_info = swjdp->jtag_info;
116 struct scan_field fields[2];
117 uint8_t out_addr_buf;
118
119 jtag_set_end_state(TAP_IDLE);
120 arm_jtag_set_instr(jtag_info, instr, NULL);
121
122 /* Add specified number of tck clocks before accessing memory bus */
123
124 /* REVISIT these TCK cycles should be *AFTER* updating APACC, since
125 * they provide more time for the (MEM) AP to complete the read ...
126 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
127 */
128 if ((instr == JTAG_DP_APACC)
129 && ((reg_addr == AP_REG_DRW)
130 || ((reg_addr & 0xF0) == AP_REG_BD0))
131 && (swjdp->memaccess_tck != 0))
132 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
133
134 /* Scan out a read or write operation using some DP or AP register.
135 * For APACC access with any sticky error flag set, this is discarded.
136 */
137 fields[0].tap = jtag_info->tap;
138 fields[0].num_bits = 3;
139 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
140 fields[0].out_value = &out_addr_buf;
141 fields[0].in_value = ack;
142
143 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
144 * complete; data we write is discarded, data we read is unpredictable.
145 * When overrun detect is active, STICKYORUN is set.
146 */
147
148 fields[1].tap = jtag_info->tap;
149 fields[1].num_bits = 32;
150 fields[1].out_value = outvalue;
151 fields[1].in_value = invalue;
152
153 jtag_add_dr_scan(2, fields, jtag_get_end_state());
154
155 return jtag_get_error();
156 }
157
158 /**
159 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
160 * This is exactly like adi_jtag_dp_scan(), except that endianness
161 * conversions are performed (so the types of invalue and outvalue
162 * must be different).
163 */
164 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
165 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
166 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
167 {
168 uint8_t out_value_buf[4];
169 int retval;
170
171 buf_set_u32(out_value_buf, 0, 32, outvalue);
172
173 retval = adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW,
174 out_value_buf, (uint8_t *)invalue, ack);
175 if (retval != ERROR_OK)
176 return retval;
177
178 if (invalue)
179 jtag_add_callback(arm_le_to_h_u32,
180 (jtag_callback_data_t) invalue);
181
182 return retval;
183 }
184
185 /**
186 * Utility to write AP registers.
187 */
188 static inline int ap_write_check(struct swjdp_common *dap,
189 uint8_t reg_addr, uint8_t *outvalue)
190 {
191 return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
192 outvalue, NULL, NULL);
193 }
194
195 static int scan_inout_check_u32(struct swjdp_common *swjdp,
196 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
197 uint32_t outvalue, uint32_t *invalue)
198 {
199 int retval;
200
201 /* Issue the read or write */
202 retval = adi_jtag_dp_scan_u32(swjdp, instr, reg_addr,
203 RnW, outvalue, NULL, NULL);
204 if (retval != ERROR_OK)
205 return retval;
206
207 /* For reads, collect posted value; RDBUFF has no other effect.
208 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
209 */
210 if ((RnW == DPAP_READ) && (invalue != NULL))
211 retval = adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
212 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
213 return retval;
214 }
215
216 int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
217 {
218 int retval;
219 uint32_t ctrlstat;
220
221 /* too expensive to call keep_alive() here */
222
223 #if 0
224 /* Danger!!!! BROKEN!!!! */
225 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
226 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
227 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
228 R956 introduced the check on return value here and now Michael Schwingen reports
229 that this code no longer works....
230
231 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
232 */
233 if ((retval = jtag_execute_queue()) != ERROR_OK)
234 {
235 LOG_ERROR("BUG: Why does this fail the first time????");
236 }
237 /* Why??? second time it works??? */
238 #endif
239
240 /* Post CTRL/STAT read; discard any previous posted read value
241 * but collect its ACK status.
242 */
243 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
244 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
245 if ((retval = jtag_execute_queue()) != ERROR_OK)
246 return retval;
247
248 swjdp->ack = swjdp->ack & 0x7;
249
250 /* common code path avoids calling timeval_ms() */
251 if (swjdp->ack != JTAG_ACK_OK_FAULT)
252 {
253 long long then = timeval_ms();
254
255 while (swjdp->ack != JTAG_ACK_OK_FAULT)
256 {
257 if (swjdp->ack == JTAG_ACK_WAIT)
258 {
259 if ((timeval_ms()-then) > 1000)
260 {
261 /* NOTE: this would be a good spot
262 * to use JTAG_DP_ABORT.
263 */
264 LOG_WARNING("Timeout (1000ms) waiting "
265 "for ACK=OK/FAULT "
266 "in JTAG-DP transaction");
267 return ERROR_JTAG_DEVICE_ERROR;
268 }
269 }
270 else
271 {
272 LOG_WARNING("Invalid ACK %#x "
273 "in JTAG-DP transaction",
274 swjdp->ack);
275 return ERROR_JTAG_DEVICE_ERROR;
276 }
277
278 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
279 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
280 if ((retval = jtag_execute_queue()) != ERROR_OK)
281 return retval;
282 swjdp->ack = swjdp->ack & 0x7;
283 }
284 }
285
286 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
287
288 /* Check for STICKYERR and STICKYORUN */
289 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
290 {
291 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
292 /* Check power to debug regions */
293 if ((ctrlstat & 0xf0000000) != 0xf0000000)
294 ahbap_debugport_init(swjdp);
295 else
296 {
297 uint32_t mem_ap_csw, mem_ap_tar;
298
299 /* Maybe print information about last intended
300 * MEM-AP access; but not if autoincrementing.
301 * *Real* CSW and TAR values are always shown.
302 */
303 if (swjdp->ap_tar_value != (uint32_t) -1)
304 LOG_DEBUG("MEM-AP Cached values: "
305 "ap_bank 0x%" PRIx32
306 ", ap_csw 0x%" PRIx32
307 ", ap_tar 0x%" PRIx32,
308 swjdp->ap_bank_value,
309 swjdp->ap_csw_value,
310 swjdp->ap_tar_value);
311
312 if (ctrlstat & SSTICKYORUN)
313 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
314 "memaccess, or reduce jtag speed");
315
316 if (ctrlstat & SSTICKYERR)
317 LOG_ERROR("JTAG-DP STICKY ERROR");
318
319 /* Clear Sticky Error Bits */
320 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
321 DP_CTRL_STAT, DPAP_WRITE,
322 swjdp->dp_ctrl_stat | SSTICKYORUN
323 | SSTICKYERR, NULL);
324 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
325 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
326 if ((retval = jtag_execute_queue()) != ERROR_OK)
327 return retval;
328
329 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
330
331 dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
332 dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
333 if ((retval = jtag_execute_queue()) != ERROR_OK)
334 return retval;
335 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
336 PRIx32, mem_ap_csw, mem_ap_tar);
337
338 }
339 if ((retval = jtag_execute_queue()) != ERROR_OK)
340 return retval;
341 return ERROR_JTAG_DEVICE_ERROR;
342 }
343
344 return ERROR_OK;
345 }
346
347 /***************************************************************************
348 * *
349 * DP and MEM-AP register access through APACC and DPACC *
350 * *
351 ***************************************************************************/
352
353 static int dap_dp_write_reg(struct swjdp_common *swjdp,
354 uint32_t value, uint8_t reg_addr)
355 {
356 return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
357 reg_addr, DPAP_WRITE, value, NULL);
358 }
359
360 static int dap_dp_read_reg(struct swjdp_common *swjdp,
361 uint32_t *value, uint8_t reg_addr)
362 {
363 return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
364 reg_addr, DPAP_READ, 0, value);
365 }
366
367 /**
368 * Select one of the APs connected to the specified DAP. The
369 * selection is implicitly used with future AP transactions.
370 * This is a NOP if the specified AP is already selected.
371 *
372 * @param swjdp The DAP
373 * @param apsel Number of the AP to (implicitly) use with further
374 * transactions. This normally identifies a MEM-AP.
375 */
376 void dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
377 {
378 uint32_t select = (apsel << 24) & 0xFF000000;
379
380 if (select != swjdp->apsel)
381 {
382 swjdp->apsel = select;
383 /* Switching AP invalidates cached values.
384 * Values MUST BE UPDATED BEFORE AP ACCESS.
385 */
386 swjdp->ap_bank_value = -1;
387 swjdp->ap_csw_value = -1;
388 swjdp->ap_tar_value = -1;
389 }
390 }
391
392 /** Select the AP register bank matching bits 7:4 of ap_reg. */
393 static int dap_ap_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
394 {
395 uint32_t select = (ap_reg & 0x000000F0);
396
397 if (select != swjdp->ap_bank_value)
398 {
399 swjdp->ap_bank_value = select;
400 select |= swjdp->apsel;
401 return dap_dp_write_reg(swjdp, select, DP_SELECT);
402 } else
403 return ERROR_OK;
404 }
405
406 static int dap_ap_write_reg(struct swjdp_common *swjdp,
407 uint32_t reg_addr, uint8_t *out_value_buf)
408 {
409 int retval;
410
411 retval = dap_ap_bankselect(swjdp, reg_addr);
412 if (retval != ERROR_OK)
413 return retval;
414
415 return ap_write_check(swjdp, reg_addr, out_value_buf);
416 }
417
418 /**
419 * Asynchronous (queued) AP register write.
420 *
421 * @param swjdp The DAP whose currently selected AP will be written.
422 * @param reg_addr Eight bit AP register address.
423 * @param value Word to be written at reg_addr
424 *
425 * @return ERROR_OK if the transaction was properly queued, else a fault code.
426 */
427 int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
428 uint32_t reg_addr, uint32_t value)
429 {
430 uint8_t out_value_buf[4];
431
432 buf_set_u32(out_value_buf, 0, 32, value);
433 return dap_ap_write_reg(swjdp,
434 reg_addr, out_value_buf);
435 }
436
437 /**
438 * Asynchronous (queued) AP register eread.
439 *
440 * @param swjdp The DAP whose currently selected AP will be read.
441 * @param reg_addr Eight bit AP register address.
442 * @param value Points to where the 32-bit (little-endian) word will be stored.
443 *
444 * @return ERROR_OK if the transaction was properly queued, else a fault code.
445 */
446 int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
447 uint32_t reg_addr, uint32_t *value)
448 {
449 int retval;
450
451 retval = dap_ap_bankselect(swjdp, reg_addr);
452 if (retval != ERROR_OK)
453 return retval;
454
455 return scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
456 DPAP_READ, 0, value);
457 }
458
459 /**
460 * Queue transactions setting up transfer parameters for the
461 * currently selected MEM-AP.
462 *
463 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
464 * initiate data reads or writes using memory or peripheral addresses.
465 * If the CSW is configured for it, the TAR may be automatically
466 * incremented after each transfer.
467 *
468 * @todo Rename to reflect it being specifically a MEM-AP function.
469 *
470 * @param swjdp The DAP connected to the MEM-AP.
471 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
472 * matches the cached value, the register is not changed.
473 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
474 * matches the cached address, the register is not changed.
475 *
476 * @return ERROR_OK if the transaction was properly queued, else a fault code.
477 */
478 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
479 {
480 int retval;
481
482 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
483 if (csw != swjdp->ap_csw_value)
484 {
485 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
486 retval = dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
487 if (retval != ERROR_OK)
488 return retval;
489 swjdp->ap_csw_value = csw;
490 }
491 if (tar != swjdp->ap_tar_value)
492 {
493 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
494 retval = dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
495 if (retval != ERROR_OK)
496 return retval;
497 swjdp->ap_tar_value = tar;
498 }
499 /* Disable TAR cache when autoincrementing */
500 if (csw & CSW_ADDRINC_MASK)
501 swjdp->ap_tar_value = -1;
502 return ERROR_OK;
503 }
504
505 /**
506 * Asynchronous (queued) read of a word from memory or a system register.
507 *
508 * @param swjdp The DAP connected to the MEM-AP performing the read.
509 * @param address Address of the 32-bit word to read; it must be
510 * readable by the currently selected MEM-AP.
511 * @param value points to where the word will be stored when the
512 * transaction queue is flushed (assuming no errors).
513 *
514 * @return ERROR_OK for success. Otherwise a fault code.
515 */
516 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address,
517 uint32_t *value)
518 {
519 int retval;
520
521 /* Use banked addressing (REG_BDx) to avoid some link traffic
522 * (updating TAR) when reading several consecutive addresses.
523 */
524 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
525 address & 0xFFFFFFF0);
526 if (retval != ERROR_OK)
527 return retval;
528
529 return dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
530 }
531
532 /**
533 * Synchronous read of a word from memory or a system register.
534 * As a side effect, this flushes any queued transactions.
535 *
536 * @param swjdp The DAP connected to the MEM-AP performing the read.
537 * @param address Address of the 32-bit word to read; it must be
538 * readable by the currently selected MEM-AP.
539 * @param value points to where the result will be stored.
540 *
541 * @return ERROR_OK for success; *value holds the result.
542 * Otherwise a fault code.
543 */
544 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
545 uint32_t *value)
546 {
547 int retval;
548
549 retval = mem_ap_read_u32(swjdp, address, value);
550 if (retval != ERROR_OK)
551 return retval;
552
553 return jtagdp_transaction_endcheck(swjdp);
554 }
555
556 /**
557 * Asynchronous (queued) write of a word to memory or a system register.
558 *
559 * @param swjdp The DAP connected to the MEM-AP.
560 * @param address Address to be written; it must be writable by
561 * the currently selected MEM-AP.
562 * @param value Word that will be written to the address when transaction
563 * queue is flushed (assuming no errors).
564 *
565 * @return ERROR_OK for success. Otherwise a fault code.
566 */
567 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address,
568 uint32_t value)
569 {
570 int retval;
571
572 /* Use banked addressing (REG_BDx) to avoid some link traffic
573 * (updating TAR) when writing several consecutive addresses.
574 */
575 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
576 address & 0xFFFFFFF0);
577 if (retval != ERROR_OK)
578 return retval;
579
580 return dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC),
581 value);
582 }
583
584 /**
585 * Synchronous write of a word to memory or a system register.
586 * As a side effect, this flushes any queued transactions.
587 *
588 * @param swjdp The DAP connected to the MEM-AP.
589 * @param address Address to be written; it must be writable by
590 * the currently selected MEM-AP.
591 * @param value Word that will be written.
592 *
593 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
594 */
595 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
596 uint32_t value)
597 {
598 int retval = mem_ap_write_u32(swjdp, address, value);
599
600 if (retval != ERROR_OK)
601 return retval;
602
603 return jtagdp_transaction_endcheck(swjdp);
604 }
605
606 /*****************************************************************************
607 * *
608 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
609 * *
610 * Write a buffer in target order (little endian) *
611 * *
612 *****************************************************************************/
613 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
614 {
615 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
616 uint32_t adr = address;
617 uint8_t* pBuffer = buffer;
618
619 count >>= 2;
620 wcount = count;
621
622 /* if we have an unaligned access - reorder data */
623 if (adr & 0x3u)
624 {
625 for (writecount = 0; writecount < count; writecount++)
626 {
627 int i;
628 uint32_t outvalue;
629 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
630
631 for (i = 0; i < 4; i++)
632 {
633 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
634 outvalue >>= 8;
635 adr++;
636 }
637 pBuffer += sizeof(uint32_t);
638 }
639 }
640
641 while (wcount > 0)
642 {
643 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
644 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
645 if (wcount < blocksize)
646 blocksize = wcount;
647
648 /* handle unaligned data at 4k boundary */
649 if (blocksize == 0)
650 blocksize = 1;
651
652 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
653
654 for (writecount = 0; writecount < blocksize; writecount++)
655 {
656 dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
657 }
658
659 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
660 {
661 wcount = wcount - blocksize;
662 address = address + 4 * blocksize;
663 buffer = buffer + 4 * blocksize;
664 }
665 else
666 {
667 errorcount++;
668 }
669
670 if (errorcount > 1)
671 {
672 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
673 return ERROR_JTAG_DEVICE_ERROR;
674 }
675 }
676
677 return retval;
678 }
679
680 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
681 uint8_t *buffer, int count, uint32_t address)
682 {
683 int retval = ERROR_OK;
684 int wcount, blocksize, writecount, i;
685
686 wcount = count >> 1;
687
688 while (wcount > 0)
689 {
690 int nbytes;
691
692 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
693 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
694
695 if (wcount < blocksize)
696 blocksize = wcount;
697
698 /* handle unaligned data at 4k boundary */
699 if (blocksize == 0)
700 blocksize = 1;
701
702 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
703 writecount = blocksize;
704
705 do
706 {
707 nbytes = MIN((writecount << 1), 4);
708
709 if (nbytes < 4)
710 {
711 if (mem_ap_write_buf_u16(swjdp, buffer,
712 nbytes, address) != ERROR_OK)
713 {
714 LOG_WARNING("Block write error address "
715 "0x%" PRIx32 ", count 0x%x",
716 address, count);
717 return ERROR_JTAG_DEVICE_ERROR;
718 }
719
720 address += nbytes >> 1;
721 }
722 else
723 {
724 uint32_t outvalue;
725 memcpy(&outvalue, buffer, sizeof(uint32_t));
726
727 for (i = 0; i < nbytes; i++)
728 {
729 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
730 outvalue >>= 8;
731 address++;
732 }
733
734 memcpy(&outvalue, buffer, sizeof(uint32_t));
735 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
736 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
737 {
738 LOG_WARNING("Block write error address "
739 "0x%" PRIx32 ", count 0x%x",
740 address, count);
741 return ERROR_JTAG_DEVICE_ERROR;
742 }
743 }
744
745 buffer += nbytes >> 1;
746 writecount -= nbytes >> 1;
747
748 } while (writecount);
749 wcount -= blocksize;
750 }
751
752 return retval;
753 }
754
755 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
756 {
757 int retval = ERROR_OK;
758
759 if (count >= 4)
760 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
761
762 while (count > 0)
763 {
764 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
765 uint16_t svalue;
766 memcpy(&svalue, buffer, sizeof(uint16_t));
767 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
768 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
769 retval = jtagdp_transaction_endcheck(swjdp);
770 count -= 2;
771 address += 2;
772 buffer += 2;
773 }
774
775 return retval;
776 }
777
778 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
779 uint8_t *buffer, int count, uint32_t address)
780 {
781 int retval = ERROR_OK;
782 int wcount, blocksize, writecount, i;
783
784 wcount = count;
785
786 while (wcount > 0)
787 {
788 int nbytes;
789
790 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
791 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
792
793 if (wcount < blocksize)
794 blocksize = wcount;
795
796 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
797 writecount = blocksize;
798
799 do
800 {
801 nbytes = MIN(writecount, 4);
802
803 if (nbytes < 4)
804 {
805 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
806 {
807 LOG_WARNING("Block write error address "
808 "0x%" PRIx32 ", count 0x%x",
809 address, count);
810 return ERROR_JTAG_DEVICE_ERROR;
811 }
812
813 address += nbytes;
814 }
815 else
816 {
817 uint32_t outvalue;
818 memcpy(&outvalue, buffer, sizeof(uint32_t));
819
820 for (i = 0; i < nbytes; i++)
821 {
822 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
823 outvalue >>= 8;
824 address++;
825 }
826
827 memcpy(&outvalue, buffer, sizeof(uint32_t));
828 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
829 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
830 {
831 LOG_WARNING("Block write error address "
832 "0x%" PRIx32 ", count 0x%x",
833 address, count);
834 return ERROR_JTAG_DEVICE_ERROR;
835 }
836 }
837
838 buffer += nbytes;
839 writecount -= nbytes;
840
841 } while (writecount);
842 wcount -= blocksize;
843 }
844
845 return retval;
846 }
847
848 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
849 {
850 int retval = ERROR_OK;
851
852 if (count >= 4)
853 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
854
855 while (count > 0)
856 {
857 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
858 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
859 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
860 retval = jtagdp_transaction_endcheck(swjdp);
861 count--;
862 address++;
863 buffer++;
864 }
865
866 return retval;
867 }
868
869 /*********************************************************************************
870 * *
871 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
872 * *
873 * Read block fast in target order (little endian) into a buffer *
874 * *
875 **********************************************************************************/
876 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
877 {
878 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
879 uint32_t adr = address;
880 uint8_t* pBuffer = buffer;
881
882 count >>= 2;
883 wcount = count;
884
885 while (wcount > 0)
886 {
887 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
888 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
889 if (wcount < blocksize)
890 blocksize = wcount;
891
892 /* handle unaligned data at 4k boundary */
893 if (blocksize == 0)
894 blocksize = 1;
895
896 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
897
898 /* Scan out first read */
899 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
900 DPAP_READ, 0, NULL, NULL);
901 for (readcount = 0; readcount < blocksize - 1; readcount++)
902 {
903 /* Scan out next read; scan in posted value for the
904 * previous one. Assumes read is acked "OK/FAULT",
905 * and CTRL_STAT says that meant "OK".
906 */
907 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
908 DPAP_READ, 0, buffer + 4 * readcount,
909 &swjdp->ack);
910 }
911
912 /* Scan in last posted value; RDBUFF has no other effect,
913 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
914 */
915 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
916 DPAP_READ, 0, buffer + 4 * readcount,
917 &swjdp->ack);
918 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
919 {
920 wcount = wcount - blocksize;
921 address += 4 * blocksize;
922 buffer += 4 * blocksize;
923 }
924 else
925 {
926 errorcount++;
927 }
928
929 if (errorcount > 1)
930 {
931 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
932 return ERROR_JTAG_DEVICE_ERROR;
933 }
934 }
935
936 /* if we have an unaligned access - reorder data */
937 if (adr & 0x3u)
938 {
939 for (readcount = 0; readcount < count; readcount++)
940 {
941 int i;
942 uint32_t data;
943 memcpy(&data, pBuffer, sizeof(uint32_t));
944
945 for (i = 0; i < 4; i++)
946 {
947 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
948 pBuffer++;
949 adr++;
950 }
951 }
952 }
953
954 return retval;
955 }
956
957 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
958 uint8_t *buffer, int count, uint32_t address)
959 {
960 uint32_t invalue;
961 int retval = ERROR_OK;
962 int wcount, blocksize, readcount, i;
963
964 wcount = count >> 1;
965
966 while (wcount > 0)
967 {
968 int nbytes;
969
970 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
971 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
972 if (wcount < blocksize)
973 blocksize = wcount;
974
975 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
976
977 /* handle unaligned data at 4k boundary */
978 if (blocksize == 0)
979 blocksize = 1;
980 readcount = blocksize;
981
982 do
983 {
984 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
985 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
986 {
987 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
988 return ERROR_JTAG_DEVICE_ERROR;
989 }
990
991 nbytes = MIN((readcount << 1), 4);
992
993 for (i = 0; i < nbytes; i++)
994 {
995 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
996 buffer++;
997 address++;
998 }
999
1000 readcount -= (nbytes >> 1);
1001 } while (readcount);
1002 wcount -= blocksize;
1003 }
1004
1005 return retval;
1006 }
1007
1008 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
1009 {
1010 uint32_t invalue, i;
1011 int retval = ERROR_OK;
1012
1013 if (count >= 4)
1014 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
1015
1016 while (count > 0)
1017 {
1018 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
1019 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1020 retval = jtagdp_transaction_endcheck(swjdp);
1021 if (address & 0x1)
1022 {
1023 for (i = 0; i < 2; i++)
1024 {
1025 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1026 buffer++;
1027 address++;
1028 }
1029 }
1030 else
1031 {
1032 uint16_t svalue = (invalue >> 8 * (address & 0x3));
1033 memcpy(buffer, &svalue, sizeof(uint16_t));
1034 address += 2;
1035 buffer += 2;
1036 }
1037 count -= 2;
1038 }
1039
1040 return retval;
1041 }
1042
1043 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
1044 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
1045 *
1046 * The solution is to arrange for a large out/in scan in this loop and
1047 * and convert data afterwards.
1048 */
1049 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
1050 uint8_t *buffer, int count, uint32_t address)
1051 {
1052 uint32_t invalue;
1053 int retval = ERROR_OK;
1054 int wcount, blocksize, readcount, i;
1055
1056 wcount = count;
1057
1058 while (wcount > 0)
1059 {
1060 int nbytes;
1061
1062 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1063 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1064
1065 if (wcount < blocksize)
1066 blocksize = wcount;
1067
1068 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1069 readcount = blocksize;
1070
1071 do
1072 {
1073 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1074 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
1075 {
1076 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1077 return ERROR_JTAG_DEVICE_ERROR;
1078 }
1079
1080 nbytes = MIN(readcount, 4);
1081
1082 for (i = 0; i < nbytes; i++)
1083 {
1084 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1085 buffer++;
1086 address++;
1087 }
1088
1089 readcount -= nbytes;
1090 } while (readcount);
1091 wcount -= blocksize;
1092 }
1093
1094 return retval;
1095 }
1096
1097 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
1098 {
1099 uint32_t invalue;
1100 int retval = ERROR_OK;
1101
1102 if (count >= 4)
1103 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1104
1105 while (count > 0)
1106 {
1107 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1108 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1109 retval = jtagdp_transaction_endcheck(swjdp);
1110 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1111 count--;
1112 address++;
1113 buffer++;
1114 }
1115
1116 return retval;
1117 }
1118
1119 /**
1120 * Initialize a DAP. This sets up the power domains, prepares the DP
1121 * for further use, and arranges to use AP #0 for all AP operations
1122 * until dap_ap-select() changes that policy.
1123 *
1124 * @param swjdp The DAP being initialized.
1125 *
1126 * @todo Rename this. We also need an initialization scheme which account
1127 * for SWD transports not just JTAG; that will need to address differences
1128 * in layering. (JTAG is useful without any debug target; but not SWD.)
1129 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1130 */
1131 int ahbap_debugport_init(struct swjdp_common *swjdp)
1132 {
1133 uint32_t idreg, romaddr, dummy;
1134 uint32_t ctrlstat;
1135 int cnt = 0;
1136 int retval;
1137
1138 LOG_DEBUG(" ");
1139
1140 /* Default MEM-AP setup.
1141 *
1142 * REVISIT AP #0 may be an inappropriate default for this.
1143 * Should we probe, or take a hint from the caller?
1144 * Presumably we can ignore the possibility of multiple APs.
1145 */
1146 swjdp->apsel = !0;
1147 dap_ap_select(swjdp, 0);
1148
1149 /* DP initialization */
1150 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1151 dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1152 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1153
1154 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1155
1156 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1157 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1158 if ((retval = jtag_execute_queue()) != ERROR_OK)
1159 return retval;
1160
1161 /* Check that we have debug power domains activated */
1162 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1163 {
1164 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1165 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1166 if ((retval = jtag_execute_queue()) != ERROR_OK)
1167 return retval;
1168 alive_sleep(10);
1169 }
1170
1171 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1172 {
1173 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1174 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1175 if ((retval = jtag_execute_queue()) != ERROR_OK)
1176 return retval;
1177 alive_sleep(10);
1178 }
1179
1180 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1181 /* With debug power on we can activate OVERRUN checking */
1182 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1183 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1184 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1185
1186 /*
1187 * REVISIT this isn't actually *initializing* anything in an AP,
1188 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1189 * Should it? If the ROM address is valid, is this the right
1190 * place to scan the table and do any topology detection?
1191 */
1192 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1193 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1194
1195 LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1196 ", Debug ROM Address 0x%" PRIx32,
1197 swjdp->apsel, idreg, romaddr);
1198
1199 return ERROR_OK;
1200 }
1201
1202 /* CID interpretation -- see ARM IHI 0029B section 3
1203 * and ARM IHI 0031A table 13-3.
1204 */
1205 static const char *class_description[16] ={
1206 "Reserved", "ROM table", "Reserved", "Reserved",
1207 "Reserved", "Reserved", "Reserved", "Reserved",
1208 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1209 "Reserved", "OptimoDE DESS",
1210 "Generic IP component", "PrimeCell or System component"
1211 };
1212
1213 static bool
1214 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1215 {
1216 return cid3 == 0xb1 && cid2 == 0x05
1217 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1218 }
1219
1220 int dap_info_command(struct command_context *cmd_ctx,
1221 struct swjdp_common *swjdp, int apsel)
1222 {
1223
1224 uint32_t dbgbase, apid;
1225 int romtable_present = 0;
1226 uint8_t mem_ap;
1227 uint32_t apselold;
1228
1229 /* AP address is in bits 31:24 of DP_SELECT */
1230 if (apsel >= 256)
1231 return ERROR_INVALID_ARGUMENTS;
1232
1233 apselold = swjdp->apsel;
1234 dap_ap_select(swjdp, apsel);
1235 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1236 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1237 jtagdp_transaction_endcheck(swjdp);
1238 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1239 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1240 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1241 if (apid)
1242 {
1243 switch (apid&0x0F)
1244 {
1245 case 0:
1246 command_print(cmd_ctx, "\tType is JTAG-AP");
1247 break;
1248 case 1:
1249 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1250 break;
1251 case 2:
1252 command_print(cmd_ctx, "\tType is MEM-AP APB");
1253 break;
1254 default:
1255 command_print(cmd_ctx, "\tUnknown AP type");
1256 break;
1257 }
1258
1259 /* NOTE: a MEM-AP may have a single CoreSight component that's
1260 * not a ROM table ... or have no such components at all.
1261 */
1262 if (mem_ap)
1263 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1264 dbgbase);
1265 }
1266 else
1267 {
1268 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1269 }
1270
1271 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1272 if (romtable_present)
1273 {
1274 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1275 uint16_t entry_offset;
1276
1277 /* bit 16 of apid indicates a memory access port */
1278 if (dbgbase & 0x02)
1279 command_print(cmd_ctx, "\tValid ROM table present");
1280 else
1281 command_print(cmd_ctx, "\tROM table in legacy format");
1282
1283 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1284 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1285 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1286 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1287 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1288 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1289 jtagdp_transaction_endcheck(swjdp);
1290 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1291 command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1292 ", CID2 0x%2.2" PRIx32
1293 ", CID1 0x%2.2" PRIx32
1294 ", CID0 0x%2.2" PRIx32,
1295 cid3, cid2, cid1, cid0);
1296 if (memtype & 0x01)
1297 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1298 else
1299 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1300 "Dedicated debug bus.");
1301
1302 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1303 entry_offset = 0;
1304 do
1305 {
1306 mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1307 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1308 if (romentry&0x01)
1309 {
1310 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1311 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1312 uint32_t component_start, component_base;
1313 unsigned part_num;
1314 char *type, *full;
1315
1316 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1317 + (int)(romentry & 0xFFFFF000));
1318 mem_ap_read_atomic_u32(swjdp,
1319 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1320 mem_ap_read_atomic_u32(swjdp,
1321 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1322 mem_ap_read_atomic_u32(swjdp,
1323 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1324 mem_ap_read_atomic_u32(swjdp,
1325 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1326 mem_ap_read_atomic_u32(swjdp,
1327 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1328 mem_ap_read_atomic_u32(swjdp,
1329 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1330 mem_ap_read_atomic_u32(swjdp,
1331 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1332 mem_ap_read_atomic_u32(swjdp,
1333 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1334 mem_ap_read_atomic_u32(swjdp,
1335 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1336 component_start = component_base - 0x1000*(c_pid4 >> 4);
1337
1338 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1339 ", start address 0x%" PRIx32,
1340 component_base, component_start);
1341 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1342 (int) (c_cid1 >> 4) & 0xf,
1343 /* See ARM IHI 0029B Table 3-3 */
1344 class_description[(c_cid1 >> 4) & 0xf]);
1345
1346 /* CoreSight component? */
1347 if (((c_cid1 >> 4) & 0x0f) == 9) {
1348 uint32_t devtype;
1349 unsigned minor;
1350 char *major = "Reserved", *subtype = "Reserved";
1351
1352 mem_ap_read_atomic_u32(swjdp,
1353 (component_base & 0xfffff000) | 0xfcc,
1354 &devtype);
1355 minor = (devtype >> 4) & 0x0f;
1356 switch (devtype & 0x0f) {
1357 case 0:
1358 major = "Miscellaneous";
1359 switch (minor) {
1360 case 0:
1361 subtype = "other";
1362 break;
1363 case 4:
1364 subtype = "Validation component";
1365 break;
1366 }
1367 break;
1368 case 1:
1369 major = "Trace Sink";
1370 switch (minor) {
1371 case 0:
1372 subtype = "other";
1373 break;
1374 case 1:
1375 subtype = "Port";
1376 break;
1377 case 2:
1378 subtype = "Buffer";
1379 break;
1380 }
1381 break;
1382 case 2:
1383 major = "Trace Link";
1384 switch (minor) {
1385 case 0:
1386 subtype = "other";
1387 break;
1388 case 1:
1389 subtype = "Funnel, router";
1390 break;
1391 case 2:
1392 subtype = "Filter";
1393 break;
1394 case 3:
1395 subtype = "FIFO, buffer";
1396 break;
1397 }
1398 break;
1399 case 3:
1400 major = "Trace Source";
1401 switch (minor) {
1402 case 0:
1403 subtype = "other";
1404 break;
1405 case 1:
1406 subtype = "Processor";
1407 break;
1408 case 2:
1409 subtype = "DSP";
1410 break;
1411 case 3:
1412 subtype = "Engine/Coprocessor";
1413 break;
1414 case 4:
1415 subtype = "Bus";
1416 break;
1417 }
1418 break;
1419 case 4:
1420 major = "Debug Control";
1421 switch (minor) {
1422 case 0:
1423 subtype = "other";
1424 break;
1425 case 1:
1426 subtype = "Trigger Matrix";
1427 break;
1428 case 2:
1429 subtype = "Debug Auth";
1430 break;
1431 }
1432 break;
1433 case 5:
1434 major = "Debug Logic";
1435 switch (minor) {
1436 case 0:
1437 subtype = "other";
1438 break;
1439 case 1:
1440 subtype = "Processor";
1441 break;
1442 case 2:
1443 subtype = "DSP";
1444 break;
1445 case 3:
1446 subtype = "Engine/Coprocessor";
1447 break;
1448 }
1449 break;
1450 }
1451 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1452 (unsigned) (devtype & 0xff),
1453 major, subtype);
1454 /* REVISIT also show 0xfc8 DevId */
1455 }
1456
1457 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1458 command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1459 ", CID2 0x%2.2" PRIx32
1460 ", CID1 0x%2.2" PRIx32
1461 ", CID0 0x%2.2" PRIx32,
1462 c_cid3, c_cid2, c_cid1, c_cid0);
1463 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1464 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1465 (int) c_pid4,
1466 (int) c_pid3, (int) c_pid2,
1467 (int) c_pid1, (int) c_pid0);
1468
1469 /* Part number interpretations are from Cortex
1470 * core specs, the CoreSight components TRM
1471 * (ARM DDI 0314H), and ETM specs; also from
1472 * chip observation (e.g. TI SDTI).
1473 */
1474 part_num = c_pid0 & 0xff;
1475 part_num |= (c_pid1 & 0x0f) << 8;
1476 switch (part_num) {
1477 case 0x000:
1478 type = "Cortex-M3 NVIC";
1479 full = "(Interrupt Controller)";
1480 break;
1481 case 0x001:
1482 type = "Cortex-M3 ITM";
1483 full = "(Instrumentation Trace Module)";
1484 break;
1485 case 0x002:
1486 type = "Cortex-M3 DWT";
1487 full = "(Data Watchpoint and Trace)";
1488 break;
1489 case 0x003:
1490 type = "Cortex-M3 FBP";
1491 full = "(Flash Patch and Breakpoint)";
1492 break;
1493 case 0x00d:
1494 type = "CoreSight ETM11";
1495 full = "(Embedded Trace)";
1496 break;
1497 // case 0x113: what?
1498 case 0x120: /* from OMAP3 memmap */
1499 type = "TI SDTI";
1500 full = "(System Debug Trace Interface)";
1501 break;
1502 case 0x343: /* from OMAP3 memmap */
1503 type = "TI DAPCTL";
1504 full = "";
1505 break;
1506 case 0x4e0:
1507 type = "Cortex-M3 ETM";
1508 full = "(Embedded Trace)";
1509 break;
1510 case 0x906:
1511 type = "Coresight CTI";
1512 full = "(Cross Trigger)";
1513 break;
1514 case 0x907:
1515 type = "Coresight ETB";
1516 full = "(Trace Buffer)";
1517 break;
1518 case 0x908:
1519 type = "Coresight CSTF";
1520 full = "(Trace Funnel)";
1521 break;
1522 case 0x910:
1523 type = "CoreSight ETM9";
1524 full = "(Embedded Trace)";
1525 break;
1526 case 0x912:
1527 type = "Coresight TPIU";
1528 full = "(Trace Port Interface Unit)";
1529 break;
1530 case 0x921:
1531 type = "Cortex-A8 ETM";
1532 full = "(Embedded Trace)";
1533 break;
1534 case 0x922:
1535 type = "Cortex-A8 CTI";
1536 full = "(Cross Trigger)";
1537 break;
1538 case 0x923:
1539 type = "Cortex-M3 TPIU";
1540 full = "(Trace Port Interface Unit)";
1541 break;
1542 case 0xc08:
1543 type = "Cortex-A8 Debug";
1544 full = "(Debug Unit)";
1545 break;
1546 default:
1547 type = "-*- unrecognized -*-";
1548 full = "";
1549 break;
1550 }
1551 command_print(cmd_ctx, "\t\tPart is %s %s",
1552 type, full);
1553 }
1554 else
1555 {
1556 if (romentry)
1557 command_print(cmd_ctx, "\t\tComponent not present");
1558 else
1559 command_print(cmd_ctx, "\t\tEnd of ROM table");
1560 }
1561 entry_offset += 4;
1562 } while (romentry > 0);
1563 }
1564 else
1565 {
1566 command_print(cmd_ctx, "\tNo ROM table present");
1567 }
1568 dap_ap_select(swjdp, apselold);
1569
1570 return ERROR_OK;
1571 }
1572
1573 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1574 {
1575 uint32_t apsel, apselsave, baseaddr;
1576 int retval;
1577
1578 apselsave = swjdp->apsel;
1579 switch (CMD_ARGC) {
1580 case 0:
1581 apsel = swjdp->apsel;
1582 break;
1583 case 1:
1584 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1585 /* AP address is in bits 31:24 of DP_SELECT */
1586 if (apsel >= 256)
1587 return ERROR_INVALID_ARGUMENTS;
1588 break;
1589 default:
1590 return ERROR_COMMAND_SYNTAX_ERROR;
1591 }
1592
1593 if (apselsave != apsel)
1594 dap_ap_select(swjdp, apsel);
1595
1596 /* NOTE: assumes we're talking to a MEM-AP, which
1597 * has a base address. There are other kinds of AP,
1598 * though they're not common for now. This should
1599 * use the ID register to verify it's a MEM-AP.
1600 */
1601 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1602 retval = jtagdp_transaction_endcheck(swjdp);
1603 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1604
1605 if (apselsave != apsel)
1606 dap_ap_select(swjdp, apselsave);
1607
1608 return retval;
1609 }
1610
1611 DAP_COMMAND_HANDLER(dap_memaccess_command)
1612 {
1613 uint32_t memaccess_tck;
1614
1615 switch (CMD_ARGC) {
1616 case 0:
1617 memaccess_tck = swjdp->memaccess_tck;
1618 break;
1619 case 1:
1620 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1621 break;
1622 default:
1623 return ERROR_COMMAND_SYNTAX_ERROR;
1624 }
1625 swjdp->memaccess_tck = memaccess_tck;
1626
1627 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1628 swjdp->memaccess_tck);
1629
1630 return ERROR_OK;
1631 }
1632
1633 DAP_COMMAND_HANDLER(dap_apsel_command)
1634 {
1635 uint32_t apsel, apid;
1636 int retval;
1637
1638 switch (CMD_ARGC) {
1639 case 0:
1640 apsel = 0;
1641 break;
1642 case 1:
1643 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1644 /* AP address is in bits 31:24 of DP_SELECT */
1645 if (apsel >= 256)
1646 return ERROR_INVALID_ARGUMENTS;
1647 break;
1648 default:
1649 return ERROR_COMMAND_SYNTAX_ERROR;
1650 }
1651
1652 dap_ap_select(swjdp, apsel);
1653 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1654 retval = jtagdp_transaction_endcheck(swjdp);
1655 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1656 apsel, apid);
1657
1658 return retval;
1659 }
1660
1661 DAP_COMMAND_HANDLER(dap_apid_command)
1662 {
1663 uint32_t apsel, apselsave, apid;
1664 int retval;
1665
1666 apselsave = swjdp->apsel;
1667 switch (CMD_ARGC) {
1668 case 0:
1669 apsel = swjdp->apsel;
1670 break;
1671 case 1:
1672 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1673 /* AP address is in bits 31:24 of DP_SELECT */
1674 if (apsel >= 256)
1675 return ERROR_INVALID_ARGUMENTS;
1676 break;
1677 default:
1678 return ERROR_COMMAND_SYNTAX_ERROR;
1679 }
1680
1681 if (apselsave != apsel)
1682 dap_ap_select(swjdp, apsel);
1683
1684 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1685 retval = jtagdp_transaction_endcheck(swjdp);
1686 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1687 if (apselsave != apsel)
1688 dap_ap_select(swjdp, apselsave);
1689
1690 return retval;
1691 }
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