1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2013 Synapse Product Development *
5 * Andrey Smirnov <andrew.smironv@gmail.com> *
6 * Angus Gratton <gus@projectgus.com> *
7 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
8 ***************************************************************************/
15 #include <helper/binarybuffer.h>
16 #include <target/algorithm.h>
17 #include <target/armv7m.h>
18 #include <helper/types.h>
19 #include <helper/time_support.h>
21 /* Both those values are constant across the current spectrum ofr nRF5 devices */
22 #define WATCHDOG_REFRESH_REGISTER 0x40010600
23 #define WATCHDOG_REFRESH_VALUE 0x6e524635
26 NRF5_FLASH_BASE
= 0x00000000,
29 enum nrf5_ficr_registers
{
30 NRF5_FICR_BASE
= 0x10000000, /* Factory Information Configuration Registers */
32 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
34 NRF5_FICR_CODEPAGESIZE
= NRF5_FICR_REG(0x010),
35 NRF5_FICR_CODESIZE
= NRF5_FICR_REG(0x014),
37 NRF51_FICR_CLENR0
= NRF5_FICR_REG(0x028),
38 NRF51_FICR_PPFC
= NRF5_FICR_REG(0x02C),
39 NRF51_FICR_NUMRAMBLOCK
= NRF5_FICR_REG(0x034),
40 NRF51_FICR_SIZERAMBLOCK0
= NRF5_FICR_REG(0x038),
41 NRF51_FICR_SIZERAMBLOCK1
= NRF5_FICR_REG(0x03C),
42 NRF51_FICR_SIZERAMBLOCK2
= NRF5_FICR_REG(0x040),
43 NRF51_FICR_SIZERAMBLOCK3
= NRF5_FICR_REG(0x044),
45 NRF5_FICR_CONFIGID
= NRF5_FICR_REG(0x05C),
46 NRF5_FICR_DEVICEID0
= NRF5_FICR_REG(0x060),
47 NRF5_FICR_DEVICEID1
= NRF5_FICR_REG(0x064),
48 NRF5_FICR_ER0
= NRF5_FICR_REG(0x080),
49 NRF5_FICR_ER1
= NRF5_FICR_REG(0x084),
50 NRF5_FICR_ER2
= NRF5_FICR_REG(0x088),
51 NRF5_FICR_ER3
= NRF5_FICR_REG(0x08C),
52 NRF5_FICR_IR0
= NRF5_FICR_REG(0x090),
53 NRF5_FICR_IR1
= NRF5_FICR_REG(0x094),
54 NRF5_FICR_IR2
= NRF5_FICR_REG(0x098),
55 NRF5_FICR_IR3
= NRF5_FICR_REG(0x09C),
56 NRF5_FICR_DEVICEADDRTYPE
= NRF5_FICR_REG(0x0A0),
57 NRF5_FICR_DEVICEADDR0
= NRF5_FICR_REG(0x0A4),
58 NRF5_FICR_DEVICEADDR1
= NRF5_FICR_REG(0x0A8),
60 NRF51_FICR_OVERRIDEN
= NRF5_FICR_REG(0x0AC),
61 NRF51_FICR_NRF_1MBIT0
= NRF5_FICR_REG(0x0B0),
62 NRF51_FICR_NRF_1MBIT1
= NRF5_FICR_REG(0x0B4),
63 NRF51_FICR_NRF_1MBIT2
= NRF5_FICR_REG(0x0B8),
64 NRF51_FICR_NRF_1MBIT3
= NRF5_FICR_REG(0x0BC),
65 NRF51_FICR_NRF_1MBIT4
= NRF5_FICR_REG(0x0C0),
66 NRF51_FICR_BLE_1MBIT0
= NRF5_FICR_REG(0x0EC),
67 NRF51_FICR_BLE_1MBIT1
= NRF5_FICR_REG(0x0F0),
68 NRF51_FICR_BLE_1MBIT2
= NRF5_FICR_REG(0x0F4),
69 NRF51_FICR_BLE_1MBIT3
= NRF5_FICR_REG(0x0F8),
70 NRF51_FICR_BLE_1MBIT4
= NRF5_FICR_REG(0x0FC),
72 /* Following registers are available on nRF52 and on nRF51 since rev 3 */
73 NRF5_FICR_INFO_PART
= NRF5_FICR_REG(0x100),
74 NRF5_FICR_INFO_VARIANT
= NRF5_FICR_REG(0x104),
75 NRF5_FICR_INFO_PACKAGE
= NRF5_FICR_REG(0x108),
76 NRF5_FICR_INFO_RAM
= NRF5_FICR_REG(0x10C),
77 NRF5_FICR_INFO_FLASH
= NRF5_FICR_REG(0x110),
80 enum nrf5_uicr_registers
{
81 NRF5_UICR_BASE
= 0x10001000, /* User Information
82 * Configuration Registers */
84 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
86 NRF51_UICR_CLENR0
= NRF5_UICR_REG(0x000),
87 NRF51_UICR_RBPCONF
= NRF5_UICR_REG(0x004),
88 NRF51_UICR_XTALFREQ
= NRF5_UICR_REG(0x008),
89 NRF51_UICR_FWID
= NRF5_UICR_REG(0x010),
92 enum nrf5_nvmc_registers
{
93 NRF5_NVMC_BASE
= 0x4001E000, /* Non-Volatile Memory
94 * Controller Registers */
96 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
98 NRF5_NVMC_READY
= NRF5_NVMC_REG(0x400),
99 NRF5_NVMC_CONFIG
= NRF5_NVMC_REG(0x504),
100 NRF5_NVMC_ERASEPAGE
= NRF5_NVMC_REG(0x508),
101 NRF5_NVMC_ERASEALL
= NRF5_NVMC_REG(0x50C),
102 NRF5_NVMC_ERASEUICR
= NRF5_NVMC_REG(0x514),
104 NRF5_BPROT_BASE
= 0x40000000,
107 enum nrf5_nvmc_config_bits
{
108 NRF5_NVMC_CONFIG_REN
= 0x00,
109 NRF5_NVMC_CONFIG_WEN
= 0x01,
110 NRF5_NVMC_CONFIG_EEN
= 0x02,
114 struct nrf52_ficr_info
{
123 NRF5_FEATURE_SERIES_51
= 1 << 0,
124 NRF5_FEATURE_SERIES_52
= 1 << 1,
125 NRF5_FEATURE_BPROT
= 1 << 2,
126 NRF5_FEATURE_ACL_PROT
= 1 << 3,
129 struct nrf5_device_spec
{
133 const char *build_code
;
134 unsigned int flash_size_kb
;
135 enum nrf5_features features
;
139 unsigned int refcount
;
142 struct nrf5_info
*chip
;
145 struct target
*target
;
147 /* chip identification stored in nrf5_probe() for use in nrf5_info() */
148 bool ficr_info_valid
;
149 struct nrf52_ficr_info ficr_info
;
150 const struct nrf5_device_spec
*spec
;
152 enum nrf5_features features
;
153 unsigned int flash_size_kb
;
154 unsigned int ram_size_kb
;
157 #define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
162 .build_code = bcode, \
163 .flash_size_kb = (fsize), \
164 .features = NRF5_FEATURE_SERIES_51, \
167 #define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize, features) \
172 .build_code = bcode, \
173 .flash_size_kb = (fsize), \
174 .features = features, \
177 /* The known devices table below is derived from the "nRF5x series
178 * compatibility matrix" documents, which can be found in the "DocLib" of
181 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51422_ic_revision_overview
182 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51822_ic_revision_overview
183 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51824_ic_revision_overview
184 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52810/latest/COMP/nrf52810/nRF52810_ic_revision_overview
185 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52832/latest/COMP/nrf52832/ic_revision_overview
186 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52840/latest/COMP/nrf52840/nRF52840_ic_revision_overview
188 * Up to date with Matrix v2.0, plus some additional HWIDs.
190 * The additional HWIDs apply where the build code in the matrix is
191 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
192 * for x==0, x!=0 means different (unspecified) HWIDs.
194 static const struct nrf5_device_spec nrf5_known_devices_table
[] = {
195 /* nRF51822 Devices (IC rev 1). */
196 NRF51_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
197 NRF51_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
198 NRF51_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
199 NRF51_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
200 NRF51_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
202 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
203 with built-in jlink seem to use engineering samples not listed
204 in the nRF51 Series Compatibility Matrix V1.0. */
205 NRF51_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
207 /* nRF51822 Devices (IC rev 2). */
208 NRF51_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
209 NRF51_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
210 NRF51_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
211 NRF51_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
212 NRF51_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
213 NRF51_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
214 NRF51_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
215 NRF51_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
216 NRF51_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
218 /* nRF51822 Devices (IC rev 3). */
219 NRF51_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
220 NRF51_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
221 NRF51_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
222 NRF51_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
223 NRF51_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
224 NRF51_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
225 NRF51_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
226 NRF51_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
227 NRF51_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
229 /* nRF51422 Devices (IC rev 1). */
230 NRF51_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
231 NRF51_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
232 NRF51_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
234 /* nRF51422 Devices (IC rev 2). */
235 NRF51_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
236 NRF51_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
237 NRF51_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
238 NRF51_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
240 /* nRF51422 Devices (IC rev 3). */
241 NRF51_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
242 NRF51_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
243 NRF51_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
244 NRF51_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
245 NRF51_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
246 NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
247 NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
249 /* The driver fully autodetects nRF52 series devices by FICR INFO,
250 * no need for nRF52xxx HWIDs in this table */
252 /* nRF52810 Devices */
253 NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0", 192, NRF5_FEATURE_SERIES_52
| NRF5_FEATURE_BPROT
),
254 NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0", 192, NRF5_FEATURE_SERIES_52
| NRF5_FEATURE_BPROT
),
256 /* nRF52832 Devices */
257 NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512, NRF5_FEATURE_SERIES_52
| NRF5_FEATURE_BPROT
),
258 NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512, NRF5_FEATURE_SERIES_52
| NRF5_FEATURE_BPROT
),
259 NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0", 512, NRF5_FEATURE_SERIES_52
| NRF5_FEATURE_BPROT
),
261 /* nRF52840 Devices */
262 NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0", 1024, NRF5_FEATURE_SERIES_52
| NRF5_FEATURE_ACL_PROT
),
266 struct nrf5_device_package
{
271 /* Newer devices have FICR INFO.PACKAGE.
272 * This table converts its value to two character code */
273 static const struct nrf5_device_package nrf5_packages_table
[] = {
280 const struct flash_driver nrf5_flash
, nrf51_flash
;
282 static bool nrf5_bank_is_probed(const struct flash_bank
*bank
)
284 struct nrf5_bank
*nbank
= bank
->driver_priv
;
288 return nbank
->probed
;
290 static int nrf5_probe(struct flash_bank
*bank
);
292 static int nrf5_get_probed_chip_if_halted(struct flash_bank
*bank
, struct nrf5_info
**chip
)
294 if (bank
->target
->state
!= TARGET_HALTED
) {
295 LOG_ERROR("Target not halted");
296 return ERROR_TARGET_NOT_HALTED
;
299 struct nrf5_bank
*nbank
= bank
->driver_priv
;
302 if (nrf5_bank_is_probed(bank
))
305 return nrf5_probe(bank
);
308 static int nrf5_wait_for_nvmc(struct nrf5_info
*chip
)
312 int timeout_ms
= 340;
313 int64_t ts_start
= timeval_ms();
316 res
= target_read_u32(chip
->target
, NRF5_NVMC_READY
, &ready
);
317 if (res
!= ERROR_OK
) {
318 LOG_ERROR("Error waiting NVMC_READY: generic flash write/erase error (check protection etc...)");
322 if (ready
== 0x00000001)
327 } while ((timeval_ms()-ts_start
) < timeout_ms
);
329 LOG_DEBUG("Timed out waiting for NVMC_READY");
330 return ERROR_FLASH_BUSY
;
333 static int nrf5_nvmc_erase_enable(struct nrf5_info
*chip
)
336 res
= target_write_u32(chip
->target
,
338 NRF5_NVMC_CONFIG_EEN
);
340 if (res
!= ERROR_OK
) {
341 LOG_ERROR("Failed to enable erase operation");
346 According to NVMC examples in Nordic SDK busy status must be
347 checked after writing to NVMC_CONFIG
349 res
= nrf5_wait_for_nvmc(chip
);
351 LOG_ERROR("Erase enable did not complete");
356 static int nrf5_nvmc_write_enable(struct nrf5_info
*chip
)
359 res
= target_write_u32(chip
->target
,
361 NRF5_NVMC_CONFIG_WEN
);
363 if (res
!= ERROR_OK
) {
364 LOG_ERROR("Failed to enable write operation");
369 According to NVMC examples in Nordic SDK busy status must be
370 checked after writing to NVMC_CONFIG
372 res
= nrf5_wait_for_nvmc(chip
);
374 LOG_ERROR("Write enable did not complete");
379 static int nrf5_nvmc_read_only(struct nrf5_info
*chip
)
382 res
= target_write_u32(chip
->target
,
384 NRF5_NVMC_CONFIG_REN
);
386 if (res
!= ERROR_OK
) {
387 LOG_ERROR("Failed to enable read-only operation");
391 According to NVMC examples in Nordic SDK busy status must be
392 checked after writing to NVMC_CONFIG
394 res
= nrf5_wait_for_nvmc(chip
);
396 LOG_ERROR("Read only enable did not complete");
401 static int nrf5_nvmc_generic_erase(struct nrf5_info
*chip
,
402 uint32_t erase_register
, uint32_t erase_value
)
406 res
= nrf5_nvmc_erase_enable(chip
);
410 res
= target_write_u32(chip
->target
,
416 res
= nrf5_wait_for_nvmc(chip
);
420 return nrf5_nvmc_read_only(chip
);
423 nrf5_nvmc_read_only(chip
);
425 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32
" val: 0x%08"PRIx32
,
426 erase_register
, erase_value
);
430 static int nrf5_protect_check_clenr0(struct flash_bank
*bank
)
434 struct nrf5_bank
*nbank
= bank
->driver_priv
;
435 struct nrf5_info
*chip
= nbank
->chip
;
439 res
= target_read_u32(chip
->target
, NRF51_FICR_CLENR0
,
441 if (res
!= ERROR_OK
) {
442 LOG_ERROR("Couldn't read code region 0 size[FICR]");
446 if (clenr0
== 0xFFFFFFFF) {
447 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
449 if (res
!= ERROR_OK
) {
450 LOG_ERROR("Couldn't read code region 0 size[UICR]");
455 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++)
456 bank
->sectors
[i
].is_protected
=
457 clenr0
!= 0xFFFFFFFF && bank
->sectors
[i
].offset
< clenr0
;
462 static int nrf5_protect_check_bprot(struct flash_bank
*bank
)
464 struct nrf5_bank
*nbank
= bank
->driver_priv
;
465 struct nrf5_info
*chip
= nbank
->chip
;
469 static uint32_t nrf5_bprot_offsets
[4] = { 0x600, 0x604, 0x610, 0x614 };
470 uint32_t bprot_reg
= 0;
473 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
474 unsigned int bit
= i
% 32;
476 unsigned int n_reg
= i
/ 32;
477 if (n_reg
>= ARRAY_SIZE(nrf5_bprot_offsets
))
480 res
= target_read_u32(chip
->target
, NRF5_BPROT_BASE
+ nrf5_bprot_offsets
[n_reg
], &bprot_reg
);
484 bank
->sectors
[i
].is_protected
= (bprot_reg
& (1 << bit
)) ? 1 : 0;
489 static int nrf5_protect_check(struct flash_bank
*bank
)
491 /* UICR cannot be write protected so just return early */
492 if (bank
->base
== NRF5_UICR_BASE
)
495 struct nrf5_bank
*nbank
= bank
->driver_priv
;
496 struct nrf5_info
*chip
= nbank
->chip
;
500 if (chip
->features
& NRF5_FEATURE_BPROT
)
501 return nrf5_protect_check_bprot(bank
);
503 if (chip
->features
& NRF5_FEATURE_SERIES_51
)
504 return nrf5_protect_check_clenr0(bank
);
506 LOG_WARNING("Flash protection of this nRF device is not supported");
507 return ERROR_FLASH_OPER_UNSUPPORTED
;
510 static int nrf5_protect_clenr0(struct flash_bank
*bank
, int set
, unsigned int first
,
514 uint32_t clenr0
, ppfc
;
515 struct nrf5_bank
*nbank
= bank
->driver_priv
;
516 struct nrf5_info
*chip
= nbank
->chip
;
519 LOG_ERROR("Code region 0 must start at the beginning of the bank");
523 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
525 if (res
!= ERROR_OK
) {
526 LOG_ERROR("Couldn't read PPFC register");
530 if ((ppfc
& 0xFF) == 0x00) {
531 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
535 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
537 if (res
!= ERROR_OK
) {
538 LOG_ERROR("Couldn't read code region 0 size from UICR");
542 if (!set
|| clenr0
!= 0xFFFFFFFF) {
543 LOG_ERROR("You need to perform chip erase before changing the protection settings");
547 res
= nrf5_nvmc_write_enable(chip
);
551 clenr0
= bank
->sectors
[last
].offset
+ bank
->sectors
[last
].size
;
552 res
= target_write_u32(chip
->target
, NRF51_UICR_CLENR0
, clenr0
);
554 int res2
= nrf5_wait_for_nvmc(chip
);
560 LOG_INFO("A reset or power cycle is required for the new protection settings to take effect.");
562 LOG_ERROR("Couldn't write code region 0 size to UICR");
565 nrf5_nvmc_read_only(chip
);
570 static int nrf5_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
574 struct nrf5_info
*chip
;
576 /* UICR cannot be write protected so just bail out early */
577 if (bank
->base
== NRF5_UICR_BASE
) {
578 LOG_ERROR("UICR page does not support protection");
579 return ERROR_FLASH_OPER_UNSUPPORTED
;
582 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
586 if (chip
->features
& NRF5_FEATURE_SERIES_51
)
587 return nrf5_protect_clenr0(bank
, set
, first
, last
);
589 LOG_ERROR("Flash protection setting is not supported on this nRF5 device");
590 return ERROR_FLASH_OPER_UNSUPPORTED
;
593 static bool nrf5_info_variant_to_str(uint32_t variant
, char *bf
)
597 h_u32_to_be(b
, variant
);
598 if (isalnum(b
[0]) && isalnum(b
[1]) && isalnum(b
[2]) && isalnum(b
[3])) {
608 static const char *nrf5_decode_info_package(uint32_t package
)
610 for (size_t i
= 0; i
< ARRAY_SIZE(nrf5_packages_table
); i
++) {
611 if (nrf5_packages_table
[i
].package
== package
)
612 return nrf5_packages_table
[i
].code
;
617 static int get_nrf5_chip_type_str(const struct nrf5_info
*chip
, char *buf
, unsigned int buf_size
)
621 res
= snprintf(buf
, buf_size
, "nRF%s-%s(build code: %s)",
622 chip
->spec
->part
, chip
->spec
->variant
, chip
->spec
->build_code
);
623 } else if (chip
->ficr_info_valid
) {
625 nrf5_info_variant_to_str(chip
->ficr_info
.variant
, variant
);
626 res
= snprintf(buf
, buf_size
, "nRF%" PRIx32
"-%s%.2s(build code: %s)",
627 chip
->ficr_info
.part
,
628 nrf5_decode_info_package(chip
->ficr_info
.package
),
629 variant
, &variant
[2]);
631 res
= snprintf(buf
, buf_size
, "nRF51xxx (HWID 0x%04" PRIx16
")", chip
->hwid
);
635 if (res
<= 0 || (unsigned int)res
>= buf_size
) {
636 LOG_ERROR("BUG: buffer problem in %s", __func__
);
642 static int nrf5_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
644 struct nrf5_bank
*nbank
= bank
->driver_priv
;
645 struct nrf5_info
*chip
= nbank
->chip
;
647 char chip_type_str
[256];
648 if (get_nrf5_chip_type_str(chip
, chip_type_str
, sizeof(chip_type_str
)) != ERROR_OK
)
651 command_print_sameline(cmd
, "%s %ukB Flash, %ukB RAM",
652 chip_type_str
, chip
->flash_size_kb
, chip
->ram_size_kb
);
656 static int nrf5_read_ficr_info(struct nrf5_info
*chip
)
659 struct target
*target
= chip
->target
;
661 chip
->ficr_info_valid
= false;
663 res
= target_read_u32(target
, NRF5_FICR_INFO_PART
, &chip
->ficr_info
.part
);
664 if (res
!= ERROR_OK
) {
665 LOG_DEBUG("Couldn't read FICR INFO.PART register");
669 uint32_t series
= chip
->ficr_info
.part
& 0xfffff000;
672 chip
->features
= NRF5_FEATURE_SERIES_51
;
676 chip
->features
= NRF5_FEATURE_SERIES_52
;
678 switch (chip
->ficr_info
.part
) {
681 chip
->features
|= NRF5_FEATURE_BPROT
;
685 chip
->features
|= NRF5_FEATURE_ACL_PROT
;
691 LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
692 PRIx32
, chip
->ficr_info
.part
);
693 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
696 /* Now we know the device has FICR INFO filled by something relevant:
697 * Although it is not documented, the tested nRF51 rev 3 devices
698 * have FICR INFO.PART, RAM and FLASH of the same format as nRF52.
699 * VARIANT and PACKAGE coding is unknown for a nRF51 device.
700 * nRF52 devices have FICR INFO documented and always filled. */
702 res
= target_read_u32(target
, NRF5_FICR_INFO_VARIANT
, &chip
->ficr_info
.variant
);
706 res
= target_read_u32(target
, NRF5_FICR_INFO_PACKAGE
, &chip
->ficr_info
.package
);
710 res
= target_read_u32(target
, NRF5_FICR_INFO_RAM
, &chip
->ficr_info
.ram
);
714 res
= target_read_u32(target
, NRF5_FICR_INFO_FLASH
, &chip
->ficr_info
.flash
);
718 chip
->ficr_info_valid
= true;
722 static int nrf5_get_ram_size(struct target
*target
, uint32_t *ram_size
)
728 uint32_t numramblock
;
729 res
= target_read_u32(target
, NRF51_FICR_NUMRAMBLOCK
, &numramblock
);
730 if (res
!= ERROR_OK
) {
731 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
735 if (numramblock
< 1 || numramblock
> 4) {
736 LOG_DEBUG("FICR NUMRAMBLOCK strange value %" PRIx32
, numramblock
);
737 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
740 for (unsigned int i
= 0; i
< numramblock
; i
++) {
741 uint32_t sizeramblock
;
742 res
= target_read_u32(target
, NRF51_FICR_SIZERAMBLOCK0
+ sizeof(uint32_t)*i
, &sizeramblock
);
743 if (res
!= ERROR_OK
) {
744 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
747 if (sizeramblock
< 1024 || sizeramblock
> 65536)
748 LOG_DEBUG("FICR SIZERAMBLOCK strange value %" PRIx32
, sizeramblock
);
750 *ram_size
+= sizeramblock
;
755 static int nrf5_probe(struct flash_bank
*bank
)
758 struct nrf5_bank
*nbank
= bank
->driver_priv
;
759 struct nrf5_info
*chip
= nbank
->chip
;
760 struct target
*target
= chip
->target
;
763 res
= target_read_u32(target
, NRF5_FICR_CONFIGID
, &configid
);
764 if (res
!= ERROR_OK
) {
765 LOG_ERROR("Couldn't read CONFIGID register");
769 /* HWID is stored in the lower two bytes of the CONFIGID register */
770 chip
->hwid
= configid
& 0xFFFF;
772 /* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
773 chip
->features
= NRF5_FEATURE_SERIES_51
;
775 /* Don't bail out on error for the case that some old engineering
776 * sample has FICR INFO registers unreadable. We can proceed anyway. */
777 (void)nrf5_read_ficr_info(chip
);
780 for (size_t i
= 0; i
< ARRAY_SIZE(nrf5_known_devices_table
); i
++) {
781 if (chip
->hwid
== nrf5_known_devices_table
[i
].hwid
) {
782 chip
->spec
= &nrf5_known_devices_table
[i
];
783 chip
->features
= chip
->spec
->features
;
788 if (chip
->spec
&& chip
->ficr_info_valid
) {
789 /* check if HWID table gives the same part as FICR INFO */
790 if (chip
->ficr_info
.part
!= strtoul(chip
->spec
->part
, NULL
, 16))
791 LOG_WARNING("HWID 0x%04" PRIx32
" mismatch: FICR INFO.PART %"
792 PRIx32
, chip
->hwid
, chip
->ficr_info
.part
);
795 if (chip
->ficr_info_valid
) {
796 chip
->ram_size_kb
= chip
->ficr_info
.ram
;
799 nrf5_get_ram_size(target
, &ram_size
);
800 chip
->ram_size_kb
= ram_size
/ 1024;
803 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
804 uint32_t flash_page_size
;
805 res
= target_read_u32(chip
->target
, NRF5_FICR_CODEPAGESIZE
,
807 if (res
!= ERROR_OK
) {
808 LOG_ERROR("Couldn't read code page size");
812 /* Note the register name is misleading,
813 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
814 uint32_t num_sectors
;
815 res
= target_read_u32(chip
->target
, NRF5_FICR_CODESIZE
, &num_sectors
);
816 if (res
!= ERROR_OK
) {
817 LOG_ERROR("Couldn't read code memory size");
821 chip
->flash_size_kb
= num_sectors
* flash_page_size
/ 1024;
823 if (!chip
->bank
[0].probed
&& !chip
->bank
[1].probed
) {
824 char chip_type_str
[256];
825 if (get_nrf5_chip_type_str(chip
, chip_type_str
, sizeof(chip_type_str
)) != ERROR_OK
)
827 const bool device_is_unknown
= (!chip
->spec
&& !chip
->ficr_info_valid
);
828 LOG_INFO("%s%s %ukB Flash, %ukB RAM",
829 device_is_unknown
? "Unknown device: " : "",
837 if (bank
->base
== NRF5_FLASH_BASE
) {
839 if (chip
->spec
&& chip
->flash_size_kb
!= chip
->spec
->flash_size_kb
)
840 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
841 if (chip
->ficr_info_valid
&& chip
->flash_size_kb
!= chip
->ficr_info
.flash
)
842 LOG_WARNING("Chip's reported Flash capacity does not match FICR INFO.FLASH");
844 bank
->num_sectors
= num_sectors
;
845 bank
->size
= num_sectors
* flash_page_size
;
847 bank
->sectors
= alloc_block_array(0, flash_page_size
, num_sectors
);
851 chip
->bank
[0].probed
= true;
854 bank
->num_sectors
= 1;
855 bank
->size
= flash_page_size
;
857 bank
->sectors
= alloc_block_array(0, flash_page_size
, num_sectors
);
861 bank
->sectors
[0].is_protected
= 0;
863 chip
->bank
[1].probed
= true;
869 static int nrf5_auto_probe(struct flash_bank
*bank
)
871 if (nrf5_bank_is_probed(bank
))
874 return nrf5_probe(bank
);
877 static int nrf5_erase_all(struct nrf5_info
*chip
)
879 LOG_DEBUG("Erasing all non-volatile memory");
880 return nrf5_nvmc_generic_erase(chip
,
885 static int nrf5_erase_page(struct flash_bank
*bank
,
886 struct nrf5_info
*chip
,
887 struct flash_sector
*sector
)
891 LOG_DEBUG("Erasing page at 0x%"PRIx32
, sector
->offset
);
893 if (bank
->base
== NRF5_UICR_BASE
) {
894 if (chip
->features
& NRF5_FEATURE_SERIES_51
) {
896 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
898 if (res
!= ERROR_OK
) {
899 LOG_ERROR("Couldn't read PPFC register");
903 if ((ppfc
& 0xFF) == 0xFF) {
904 /* We can't erase the UICR. Double-check to
905 see if it's already erased before complaining. */
906 default_flash_blank_check(bank
);
907 if (sector
->is_erased
== 1)
910 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
915 res
= nrf5_nvmc_generic_erase(chip
,
921 res
= nrf5_nvmc_generic_erase(chip
,
929 /* Start a low level flash write for the specified region */
930 static int nrf5_ll_flash_write(struct nrf5_info
*chip
, uint32_t address
, const uint8_t *buffer
, uint32_t bytes
)
932 struct target
*target
= chip
->target
;
933 uint32_t buffer_size
= 8192;
934 struct working_area
*write_algorithm
;
935 struct working_area
*source
;
936 struct reg_param reg_params
[6];
937 struct armv7m_algorithm armv7m_info
;
938 int retval
= ERROR_OK
;
940 static const uint8_t nrf5_flash_write_code
[] = {
941 #include "../../../contrib/loaders/flash/nrf5/nrf5.inc"
944 LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32
" bytes=0x%"PRIx32
, address
, bytes
);
945 assert(bytes
% 4 == 0);
947 /* allocate working area with flash programming code */
948 if (target_alloc_working_area(target
, sizeof(nrf5_flash_write_code
),
949 &write_algorithm
) != ERROR_OK
) {
950 LOG_WARNING("no working area available, falling back to slow memory writes");
952 for (; bytes
> 0; bytes
-= 4) {
953 retval
= target_write_memory(target
, address
, 4, 1, buffer
);
954 if (retval
!= ERROR_OK
)
957 retval
= nrf5_wait_for_nvmc(chip
);
958 if (retval
!= ERROR_OK
)
968 retval
= target_write_buffer(target
, write_algorithm
->address
,
969 sizeof(nrf5_flash_write_code
),
970 nrf5_flash_write_code
);
971 if (retval
!= ERROR_OK
)
975 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
) {
977 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
978 if (buffer_size
<= 256) {
979 /* free working area, write algorithm already allocated */
980 target_free_working_area(target
, write_algorithm
);
982 LOG_WARNING("No large enough working area available, can't do block memory writes");
983 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
987 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
988 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
990 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* byte count */
991 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer start */
992 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer end */
993 init_reg_param(®_params
[3], "r3", 32, PARAM_IN_OUT
); /* target address */
994 init_reg_param(®_params
[4], "r6", 32, PARAM_OUT
); /* watchdog refresh value */
995 init_reg_param(®_params
[5], "r7", 32, PARAM_OUT
); /* watchdog refresh register address */
997 buf_set_u32(reg_params
[0].value
, 0, 32, bytes
);
998 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
999 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
+ source
->size
);
1000 buf_set_u32(reg_params
[3].value
, 0, 32, address
);
1001 buf_set_u32(reg_params
[4].value
, 0, 32, WATCHDOG_REFRESH_VALUE
);
1002 buf_set_u32(reg_params
[5].value
, 0, 32, WATCHDOG_REFRESH_REGISTER
);
1004 retval
= target_run_flash_async_algorithm(target
, buffer
, bytes
/4, 4,
1006 ARRAY_SIZE(reg_params
), reg_params
,
1007 source
->address
, source
->size
,
1008 write_algorithm
->address
, write_algorithm
->address
+ sizeof(nrf5_flash_write_code
) - 2,
1011 target_free_working_area(target
, source
);
1012 target_free_working_area(target
, write_algorithm
);
1014 destroy_reg_param(®_params
[0]);
1015 destroy_reg_param(®_params
[1]);
1016 destroy_reg_param(®_params
[2]);
1017 destroy_reg_param(®_params
[3]);
1018 destroy_reg_param(®_params
[4]);
1019 destroy_reg_param(®_params
[5]);
1024 static int nrf5_write(struct flash_bank
*bank
, const uint8_t *buffer
,
1025 uint32_t offset
, uint32_t count
)
1027 struct nrf5_info
*chip
;
1029 int res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
1030 if (res
!= ERROR_OK
)
1033 assert(offset
% 4 == 0);
1034 assert(count
% 4 == 0);
1036 /* UICR CLENR0 based protection used on nRF51 is somewhat clumsy:
1037 * RM reads: Code running from code region 1 will not be able to write
1039 * Unfortunately the flash loader running from RAM can write to both
1040 * code regions without any hint the protection is violated.
1042 * Update protection state and check if any flash sector to be written
1044 if (chip
->features
& NRF5_FEATURE_SERIES_51
) {
1046 res
= nrf5_protect_check_clenr0(bank
);
1047 if (res
!= ERROR_OK
)
1050 for (unsigned int sector
= 0; sector
< bank
->num_sectors
; sector
++) {
1051 struct flash_sector
*bs
= &bank
->sectors
[sector
];
1053 /* Start offset in or before this sector? */
1054 /* End offset in or behind this sector? */
1055 if ((offset
< (bs
->offset
+ bs
->size
))
1056 && ((offset
+ count
- 1) >= bs
->offset
)
1057 && bs
->is_protected
== 1) {
1058 LOG_ERROR("Write refused, sector %d is protected", sector
);
1059 return ERROR_FLASH_PROTECTED
;
1064 res
= nrf5_nvmc_write_enable(chip
);
1065 if (res
!= ERROR_OK
)
1068 res
= nrf5_ll_flash_write(chip
, bank
->base
+ offset
, buffer
, count
);
1069 if (res
!= ERROR_OK
)
1072 return nrf5_nvmc_read_only(chip
);
1075 nrf5_nvmc_read_only(chip
);
1076 LOG_ERROR("Failed to write to nrf5 flash");
1080 static int nrf5_erase(struct flash_bank
*bank
, unsigned int first
,
1084 struct nrf5_info
*chip
;
1086 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
1087 if (res
!= ERROR_OK
)
1090 /* UICR CLENR0 based protection used on nRF51 prevents erase
1091 * absolutely silently. NVMC has no flag to indicate the protection
1094 * Update protection state and check if any flash sector to be erased
1096 if (chip
->features
& NRF5_FEATURE_SERIES_51
) {
1098 res
= nrf5_protect_check_clenr0(bank
);
1099 if (res
!= ERROR_OK
)
1103 /* For each sector to be erased */
1104 for (unsigned int s
= first
; s
<= last
&& res
== ERROR_OK
; s
++) {
1106 if (chip
->features
& NRF5_FEATURE_SERIES_51
1107 && bank
->sectors
[s
].is_protected
== 1) {
1108 LOG_ERROR("Flash sector %d is protected", s
);
1109 return ERROR_FLASH_PROTECTED
;
1112 res
= nrf5_erase_page(bank
, chip
, &bank
->sectors
[s
]);
1113 if (res
!= ERROR_OK
) {
1114 LOG_ERROR("Error erasing sector %d", s
);
1122 static void nrf5_free_driver_priv(struct flash_bank
*bank
)
1124 struct nrf5_bank
*nbank
= bank
->driver_priv
;
1125 struct nrf5_info
*chip
= nbank
->chip
;
1130 if (chip
->refcount
== 0) {
1132 bank
->driver_priv
= NULL
;
1136 static struct nrf5_info
*nrf5_get_chip(struct target
*target
)
1138 struct flash_bank
*bank_iter
;
1140 /* iterate over nrf5 banks of same target */
1141 for (bank_iter
= flash_bank_list(); bank_iter
; bank_iter
= bank_iter
->next
) {
1142 if (bank_iter
->driver
!= &nrf5_flash
&& bank_iter
->driver
!= &nrf51_flash
)
1145 if (bank_iter
->target
!= target
)
1148 struct nrf5_bank
*nbank
= bank_iter
->driver_priv
;
1158 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command
)
1160 struct nrf5_info
*chip
;
1161 struct nrf5_bank
*nbank
= NULL
;
1163 switch (bank
->base
) {
1164 case NRF5_FLASH_BASE
:
1165 case NRF5_UICR_BASE
:
1168 LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT
, bank
->base
);
1172 chip
= nrf5_get_chip(bank
->target
);
1174 /* Create a new chip */
1175 chip
= calloc(1, sizeof(*chip
));
1179 chip
->target
= bank
->target
;
1182 switch (bank
->base
) {
1183 case NRF5_FLASH_BASE
:
1184 nbank
= &chip
->bank
[0];
1186 case NRF5_UICR_BASE
:
1187 nbank
= &chip
->bank
[1];
1194 nbank
->probed
= false;
1195 bank
->driver_priv
= nbank
;
1196 bank
->write_start_alignment
= bank
->write_end_alignment
= 4;
1201 COMMAND_HANDLER(nrf5_handle_mass_erase_command
)
1204 struct flash_bank
*bank
= NULL
;
1205 struct target
*target
= get_current_target(CMD_CTX
);
1207 res
= get_flash_bank_by_addr(target
, NRF5_FLASH_BASE
, true, &bank
);
1208 if (res
!= ERROR_OK
)
1213 struct nrf5_info
*chip
;
1215 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
1216 if (res
!= ERROR_OK
)
1219 if (chip
->features
& NRF5_FEATURE_SERIES_51
) {
1221 res
= target_read_u32(target
, NRF51_FICR_PPFC
,
1223 if (res
!= ERROR_OK
) {
1224 LOG_ERROR("Couldn't read PPFC register");
1228 if ((ppfc
& 0xFF) == 0x00) {
1229 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1230 "mass erase command won't work.");
1235 res
= nrf5_erase_all(chip
);
1236 if (res
== ERROR_OK
) {
1237 LOG_INFO("Mass erase completed.");
1238 if (chip
->features
& NRF5_FEATURE_SERIES_51
)
1239 LOG_INFO("A reset or power cycle is required if the flash was protected before.");
1242 LOG_ERROR("Failed to erase the chip");
1248 COMMAND_HANDLER(nrf5_handle_info_command
)
1251 struct flash_bank
*bank
= NULL
;
1252 struct target
*target
= get_current_target(CMD_CTX
);
1254 res
= get_flash_bank_by_addr(target
, NRF5_FLASH_BASE
, true, &bank
);
1255 if (res
!= ERROR_OK
)
1260 struct nrf5_info
*chip
;
1262 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
1263 if (res
!= ERROR_OK
)
1267 const uint32_t address
;
1270 { .address
= NRF5_FICR_CODEPAGESIZE
},
1271 { .address
= NRF5_FICR_CODESIZE
},
1272 { .address
= NRF51_FICR_CLENR0
},
1273 { .address
= NRF51_FICR_PPFC
},
1274 { .address
= NRF51_FICR_NUMRAMBLOCK
},
1275 { .address
= NRF51_FICR_SIZERAMBLOCK0
},
1276 { .address
= NRF51_FICR_SIZERAMBLOCK1
},
1277 { .address
= NRF51_FICR_SIZERAMBLOCK2
},
1278 { .address
= NRF51_FICR_SIZERAMBLOCK3
},
1279 { .address
= NRF5_FICR_CONFIGID
},
1280 { .address
= NRF5_FICR_DEVICEID0
},
1281 { .address
= NRF5_FICR_DEVICEID1
},
1282 { .address
= NRF5_FICR_ER0
},
1283 { .address
= NRF5_FICR_ER1
},
1284 { .address
= NRF5_FICR_ER2
},
1285 { .address
= NRF5_FICR_ER3
},
1286 { .address
= NRF5_FICR_IR0
},
1287 { .address
= NRF5_FICR_IR1
},
1288 { .address
= NRF5_FICR_IR2
},
1289 { .address
= NRF5_FICR_IR3
},
1290 { .address
= NRF5_FICR_DEVICEADDRTYPE
},
1291 { .address
= NRF5_FICR_DEVICEADDR0
},
1292 { .address
= NRF5_FICR_DEVICEADDR1
},
1293 { .address
= NRF51_FICR_OVERRIDEN
},
1294 { .address
= NRF51_FICR_NRF_1MBIT0
},
1295 { .address
= NRF51_FICR_NRF_1MBIT1
},
1296 { .address
= NRF51_FICR_NRF_1MBIT2
},
1297 { .address
= NRF51_FICR_NRF_1MBIT3
},
1298 { .address
= NRF51_FICR_NRF_1MBIT4
},
1299 { .address
= NRF51_FICR_BLE_1MBIT0
},
1300 { .address
= NRF51_FICR_BLE_1MBIT1
},
1301 { .address
= NRF51_FICR_BLE_1MBIT2
},
1302 { .address
= NRF51_FICR_BLE_1MBIT3
},
1303 { .address
= NRF51_FICR_BLE_1MBIT4
},
1305 { .address
= NRF51_UICR_CLENR0
, },
1306 { .address
= NRF51_UICR_RBPCONF
},
1307 { .address
= NRF51_UICR_XTALFREQ
},
1308 { .address
= NRF51_UICR_FWID
},
1311 for (size_t i
= 0; i
< ARRAY_SIZE(ficr
); i
++) {
1312 res
= target_read_u32(chip
->target
, ficr
[i
].address
,
1314 if (res
!= ERROR_OK
) {
1315 LOG_ERROR("Couldn't read %" PRIx32
, ficr
[i
].address
);
1320 for (size_t i
= 0; i
< ARRAY_SIZE(uicr
); i
++) {
1321 res
= target_read_u32(chip
->target
, uicr
[i
].address
,
1323 if (res
!= ERROR_OK
) {
1324 LOG_ERROR("Couldn't read %" PRIx32
, uicr
[i
].address
);
1330 "\n[factory information control block]\n\n"
1331 "code page size: %"PRIu32
"B\n"
1332 "code memory size: %"PRIu32
"kB\n"
1333 "code region 0 size: %"PRIu32
"kB\n"
1334 "pre-programmed code: %s\n"
1335 "number of ram blocks: %"PRIu32
"\n"
1336 "ram block 0 size: %"PRIu32
"B\n"
1337 "ram block 1 size: %"PRIu32
"B\n"
1338 "ram block 2 size: %"PRIu32
"B\n"
1339 "ram block 3 size: %"PRIu32
"B\n"
1340 "config id: %" PRIx32
"\n"
1341 "device id: 0x%"PRIx32
"%08"PRIx32
"\n"
1342 "encryption root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1343 "identity root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1344 "device address type: 0x%"PRIx32
"\n"
1345 "device address: 0x%"PRIx32
"%08"PRIx32
"\n"
1346 "override enable: %"PRIx32
"\n"
1347 "NRF_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1348 "BLE_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1349 "\n[user information control block]\n\n"
1350 "code region 0 size: %"PRIu32
"kB\n"
1351 "read back protection configuration: %"PRIx32
"\n"
1352 "reset value for XTALFREQ: %"PRIx32
"\n"
1353 "firmware id: 0x%04"PRIx32
,
1355 (ficr
[1].value
* ficr
[0].value
) / 1024,
1356 (ficr
[2].value
== 0xFFFFFFFF) ? 0 : ficr
[2].value
/ 1024,
1357 ((ficr
[3].value
& 0xFF) == 0x00) ? "present" : "not present",
1360 (ficr
[6].value
== 0xFFFFFFFF) ? 0 : ficr
[6].value
,
1361 (ficr
[7].value
== 0xFFFFFFFF) ? 0 : ficr
[7].value
,
1362 (ficr
[8].value
== 0xFFFFFFFF) ? 0 : ficr
[8].value
,
1364 ficr
[10].value
, ficr
[11].value
,
1365 ficr
[12].value
, ficr
[13].value
, ficr
[14].value
, ficr
[15].value
,
1366 ficr
[16].value
, ficr
[17].value
, ficr
[18].value
, ficr
[19].value
,
1368 ficr
[21].value
, ficr
[22].value
,
1370 ficr
[24].value
, ficr
[25].value
, ficr
[26].value
, ficr
[27].value
, ficr
[28].value
,
1371 ficr
[29].value
, ficr
[30].value
, ficr
[31].value
, ficr
[32].value
, ficr
[33].value
,
1372 (uicr
[0].value
== 0xFFFFFFFF) ? 0 : uicr
[0].value
/ 1024,
1373 uicr
[1].value
& 0xFFFF,
1374 uicr
[2].value
& 0xFF,
1375 uicr
[3].value
& 0xFFFF);
1380 static const struct command_registration nrf5_exec_command_handlers
[] = {
1382 .name
= "mass_erase",
1383 .handler
= nrf5_handle_mass_erase_command
,
1384 .mode
= COMMAND_EXEC
,
1385 .help
= "Erase all flash contents of the chip.",
1390 .handler
= nrf5_handle_info_command
,
1391 .mode
= COMMAND_EXEC
,
1392 .help
= "Show FICR and UICR info.",
1395 COMMAND_REGISTRATION_DONE
1398 static const struct command_registration nrf5_command_handlers
[] = {
1401 .mode
= COMMAND_ANY
,
1402 .help
= "nrf5 flash command group",
1404 .chain
= nrf5_exec_command_handlers
,
1408 .mode
= COMMAND_ANY
,
1409 .help
= "nrf51 flash command group",
1411 .chain
= nrf5_exec_command_handlers
,
1413 COMMAND_REGISTRATION_DONE
1416 const struct flash_driver nrf5_flash
= {
1418 .commands
= nrf5_command_handlers
,
1419 .flash_bank_command
= nrf5_flash_bank_command
,
1421 .erase
= nrf5_erase
,
1422 .protect
= nrf5_protect
,
1423 .write
= nrf5_write
,
1424 .read
= default_flash_read
,
1425 .probe
= nrf5_probe
,
1426 .auto_probe
= nrf5_auto_probe
,
1427 .erase_check
= default_flash_blank_check
,
1428 .protect_check
= nrf5_protect_check
,
1429 .free_driver_priv
= nrf5_free_driver_priv
,
1432 /* We need to retain the flash-driver name as well as the commands
1433 * for backwards compatibility */
1434 const struct flash_driver nrf51_flash
= {
1436 .commands
= nrf5_command_handlers
,
1437 .flash_bank_command
= nrf5_flash_bank_command
,
1439 .erase
= nrf5_erase
,
1440 .protect
= nrf5_protect
,
1441 .write
= nrf5_write
,
1442 .read
= default_flash_read
,
1443 .probe
= nrf5_probe
,
1444 .auto_probe
= nrf5_auto_probe
,
1445 .erase_check
= default_flash_blank_check
,
1446 .protect_check
= nrf5_protect_check
,
1447 .free_driver_priv
= nrf5_free_driver_priv
,