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rtos/hwthread: derive threadid from SMP index
[openocd.git] / src / flash / nor / nrf5.c
blob5cb552aa94c5c7cc2047367e30f0147398a5683f
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2013 Synapse Product Development *
5 * Andrey Smirnov <andrew.smironv@gmail.com> *
6 * Angus Gratton <gus@projectgus.com> *
7 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
8 ***************************************************************************/
9
10 #ifdef HAVE_CONFIG_H
11 #include "config.h"
12 #endif
13
14 #include "imp.h"
15 #include <helper/binarybuffer.h>
16 #include <target/algorithm.h>
17 #include <target/armv7m.h>
18 #include <helper/types.h>
19 #include <helper/time_support.h>
20 #include <helper/bits.h>
21
22 /* The refresh code is constant across the current spectrum of nRF5 devices */
23 #define WATCHDOG_REFRESH_VALUE 0x6e524635
24
25 enum {
26 NRF5_FLASH_BASE = 0x00000000,
27 };
28
29 enum nrf5_ficr_registers {
30 NRF51_52_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
31
32 #define NRF5_FICR_REG(offset) (NRF51_52_FICR_BASE + (offset))
33
34 NRF51_FICR_CLENR0 = NRF5_FICR_REG(0x028),
35 NRF51_FICR_PPFC = NRF5_FICR_REG(0x02C),
36 NRF51_FICR_NUMRAMBLOCK = NRF5_FICR_REG(0x034),
37 NRF51_FICR_SIZERAMBLOCK0 = NRF5_FICR_REG(0x038),
38 NRF51_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
39 NRF51_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
40 NRF51_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
41 };
42
43 enum nrf5_uicr_registers {
44 NRF51_52_UICR_BASE = 0x10001000, /* User Information
45 * Configuration Registers */
46
47 #define NRF5_UICR_REG(offset) (NRF51_52_UICR_BASE + (offset))
48
49 NRF51_UICR_CLENR0 = NRF5_UICR_REG(0x000),
50 };
51
52 enum nrf5_nvmc_registers {
53 NRF5_NVMC_READY = 0x400,
54 NRF5_NVMC_CONFIG = 0x504,
55 NRF5_NVMC_ERASEPAGE = 0x508,
56 NRF5_NVMC_ERASEALL = 0x50C,
57 NRF5_NVMC_ERASEUICR = 0x514,
58
59 NRF5_BPROT_BASE = 0x40000000,
60 };
61
62 enum nrf5_nvmc_config_bits {
63 NRF5_NVMC_CONFIG_REN = 0x00,
64 NRF5_NVMC_CONFIG_WEN = 0x01,
65 NRF5_NVMC_CONFIG_EEN = 0x02,
66
67 };
68
69 struct nrf52_ficr_info {
70 uint32_t part;
71 uint32_t variant;
72 uint32_t package;
73 uint32_t ram;
74 uint32_t flash;
75 };
76
77 enum nrf5_features {
78 NRF5_FEATURE_SERIES_51 = BIT(0),
79 NRF5_FEATURE_SERIES_52 = BIT(1),
80 NRF5_FEATURE_BPROT = BIT(2),
81 NRF5_FEATURE_ACL_PROT = BIT(3),
82 NRF5_FEATURE_SERIES_53 = BIT(4),
83 NRF5_FEATURE_SERIES_91 = BIT(5),
84 NRF5_FEATURE_ERASE_BY_FLASH_WR = BIT(6),
85 };
86
87 struct nrf5_device_spec {
88 uint16_t hwid;
89 const char *part;
90 const char *variant;
91 const char *build_code;
92 unsigned int flash_size_kb;
93 enum nrf5_features features;
94 };
95
96 /* FICR registers offsets */
97 struct nrf5_ficr_map {
98 uint32_t codepagesize;
99 uint32_t codesize;
100 uint32_t configid;
101 uint32_t info_part;
102 uint32_t info_variant;
103 uint32_t info_package;
104 uint32_t info_ram;
105 uint32_t info_flash;
106 };
107
108 /* Map of device */
109 struct nrf5_map {
110 uint32_t flash_base;
111 uint32_t ficr_base;
112 uint32_t uicr_base;
113 uint32_t nvmc_base;
114
115 uint32_t watchdog_refresh_addr;
116 };
117
118 struct nrf5_info {
119 unsigned int refcount;
120 bool chip_probed;
121
122 struct nrf5_bank {
123 struct nrf5_info *chip;
124 bool probed;
125 } bank[2];
126
127 struct target *target;
128
129 /* chip identification stored in nrf5_probe_chip()
130 * for use in nrf5_info() and nrf5_setup_bank() */
131 bool ficr_info_valid;
132 struct nrf52_ficr_info ficr_info;
133 const struct nrf5_device_spec *spec;
134 uint16_t hwid;
135 enum nrf5_features features;
136 uint32_t flash_page_size;
137 uint32_t flash_num_sectors;
138 unsigned int ram_size_kb;
139
140 const struct nrf5_map *map;
141 const struct nrf5_ficr_map *ficr_offsets;
142 };
143
144 #define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
145 { \
146 .hwid = (id), \
147 .part = pt, \
148 .variant = var, \
149 .build_code = bcode, \
150 .flash_size_kb = (fsize), \
151 .features = NRF5_FEATURE_SERIES_51, \
152 }
153
154 /*
155 * The table maps known HWIDs to the part numbers, variant
156 * build code and some other info. For nRF51 rev 1 and 2 devices
157 * this is the only way how to get the part number and variant.
158 *
159 * All tested nRF51 rev 3 devices have FICR INFO fields
160 * but the fields are not documented in RM so we keep HWIDs in
161 * this table.
162 *
163 * nRF52 and newer devices have FICR INFO documented, the autodetection
164 * can rely on it and HWIDs table is not used.
165 *
166 * The known devices table below is derived from the "nRF5x series
167 * compatibility matrix" documents.
168 *
169 * Up to date with Matrix v2.0, plus some additional HWIDs.
170 *
171 * The additional HWIDs apply where the build code in the matrix is
172 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
173 * for x==0, x!=0 means different (unspecified) HWIDs.
174 */
175 static const struct nrf5_device_spec nrf5_known_devices_table[] = {
176 /* nRF51822 Devices (IC rev 1). */
177 NRF51_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
178 NRF51_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
179 NRF51_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
180 NRF51_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
181 NRF51_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
182
183 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
184 with built-in jlink seem to use engineering samples not listed
185 in the nRF51 Series Compatibility Matrix V1.0. */
186 NRF51_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
187
188 /* nRF51822 Devices (IC rev 2). */
189 NRF51_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
190 NRF51_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
191 NRF51_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
192 NRF51_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
193 NRF51_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
194 NRF51_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
195 NRF51_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
196 NRF51_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
197 NRF51_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
198
199 /* nRF51822 Devices (IC rev 3). */
200 NRF51_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
201 NRF51_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
202 NRF51_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
203 NRF51_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
204 NRF51_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
205 NRF51_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
206 NRF51_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
207 NRF51_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
208 NRF51_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
209
210 /* nRF51422 Devices (IC rev 1). */
211 NRF51_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
212 NRF51_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
213 NRF51_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
214
215 /* nRF51422 Devices (IC rev 2). */
216 NRF51_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
217 NRF51_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
218 NRF51_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
219 NRF51_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
220
221 /* nRF51422 Devices (IC rev 3). */
222 NRF51_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
223 NRF51_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
224 NRF51_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
225 NRF51_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
226 NRF51_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
227 NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
228 NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
229
230 /* The driver fully autodetects nRF52 series devices by FICR INFO,
231 * no need for nRF52xxx HWIDs in this table */
232 };
233
234 struct nrf5_device_package {
235 uint32_t package;
236 const char *code;
237 };
238
239 /* Newer devices have FICR INFO.PACKAGE.
240 * This table converts its value to two character code */
241 static const struct nrf5_device_package nrf52_packages_table[] = {
242 { 0x2000, "QF" },
243 { 0x2001, "CH" },
244 { 0x2002, "CI" },
245 { 0x2003, "QC" },
246 { 0x2004, "QI/CA" }, /* differs nRF52805, 810, 811: CA, nRF52833, 840: QI */
247 { 0x2005, "CK" },
248 { 0x2007, "QD" },
249 { 0x2008, "CJ" },
250 { 0x2009, "CF" },
251 };
252
253 static const struct nrf5_ficr_map nrf51_52_ficr_offsets = {
254 .codepagesize = 0x10,
255 .codesize = 0x14,
256
257 /* CONFIGID is documented on nRF51 series only.
258 * On nRF52 is present but not documented */
259 .configid = 0x5c,
260
261 /* Following registers are available on nRF52 and on nRF51 since rev 3 */
262 .info_part = 0x100,
263 .info_variant = 0x104,
264 .info_package = 0x108,
265 .info_ram = 0x10c,
266 .info_flash = 0x110,
267 };
268
269 static const struct nrf5_map nrf51_52_map = {
270 .flash_base = NRF5_FLASH_BASE,
271 .ficr_base = NRF51_52_FICR_BASE,
272 .uicr_base = NRF51_52_UICR_BASE,
273 .nvmc_base = 0x4001E000,
274
275 .watchdog_refresh_addr = 0x40010600,
276 };
277
278
279 /* Third generation devices (nRF53, nRF91) */
280
281 static const struct nrf5_ficr_map nrf53_91_ficr_offsets = {
282 .codepagesize = 0x220,
283 .codesize = 0x224,
284 .configid = 0x200,
285 .info_part = 0x20c,
286 .info_variant = 0x210,
287 .info_package = 0x214,
288 .info_ram = 0x218,
289 .info_flash = 0x21c,
290 };
291
292 /* Since nRF9160 Product Specification v2.1 there is
293 * a new UICR field SIPINFO, which should be preferred.
294 * The original INFO fields describe just a part of the chip
295 * (PARTNO=9120 at nRF9161)
296 */
297 static const struct nrf5_ficr_map nrf91new_ficr_offsets = {
298 .codepagesize = 0x220,
299 .codesize = 0x224,
300 .configid = 0x200,
301 .info_part = 0x140, /* SIPINFO.PARTNO */
302 .info_variant = 0x148, /* SIPINFO.VARIANT */
303 .info_package = 0x214,
304 .info_ram = 0x218,
305 .info_flash = 0x21c,
306 };
307
308 enum {
309 NRF53APP_91_FICR_BASE = 0x00FF0000,
310 NRF53APP_91_UICR_BASE = 0x00FF8000,
311 NRF53NET_FLASH_BASE = 0x01000000,
312 NRF53NET_FICR_BASE = 0x01FF0000,
313 NRF53NET_UICR_BASE = 0x01FF8000,
314 };
315
316 static const struct nrf5_map nrf53app_91_map = {
317 .flash_base = NRF5_FLASH_BASE,
318 .ficr_base = NRF53APP_91_FICR_BASE,
319 .uicr_base = NRF53APP_91_UICR_BASE,
320 .nvmc_base = 0x50039000,
321
322 .watchdog_refresh_addr = 0x50018600,
323 };
324
325 /* nRF53 duality:
326 * SoC consists of two Cortex-M33 cores:
327 * - application core with security extensions
328 * - network core
329 * Each core has its own RAM, flash, FICR and UICR
330 * The flash driver probes and handles flash and UICR of one core
331 * independently of those dedicated to the other core.
332 */
333 static const struct nrf5_map nrf53net_map = {
334 .flash_base = NRF53NET_FLASH_BASE,
335 .ficr_base = NRF53NET_FICR_BASE,
336 .uicr_base = NRF53NET_UICR_BASE,
337 .nvmc_base = 0x41080000,
338
339 .watchdog_refresh_addr = 0x41080000,
340 };
341
342
343 const struct flash_driver nrf5_flash, nrf51_flash;
344
345 static bool nrf5_bank_is_probed(const struct flash_bank *bank)
346 {
347 struct nrf5_bank *nbank = bank->driver_priv;
348 return nbank->probed;
349 }
350
351 static bool nrf5_chip_is_probed(const struct flash_bank *bank)
352 {
353 struct nrf5_bank *nbank = bank->driver_priv;
354 struct nrf5_info *chip = nbank->chip;
355 return chip->chip_probed;
356 }
357
358 static bool nrf5_bank_is_uicr(const struct nrf5_bank *nbank)
359 {
360 struct nrf5_info *chip = nbank->chip;
361 return nbank == &chip->bank[1];
362 }
363
364 static int nrf5_nvmc_read_u32(struct nrf5_info *chip, uint32_t reg_offset, uint32_t *value)
365 {
366 return target_read_u32(chip->target, chip->map->nvmc_base + reg_offset, value);
367 }
368
369 static int nrf5_nvmc_write_u32(struct nrf5_info *chip, uint32_t reg_offset, uint32_t value)
370 {
371 return target_write_u32(chip->target, chip->map->nvmc_base + reg_offset, value);
372 }
373
374 static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
375 {
376 uint32_t ready;
377 int res;
378 int timeout_ms = 340;
379 int64_t ts_start = timeval_ms();
380
381 do {
382 res = nrf5_nvmc_read_u32(chip, NRF5_NVMC_READY, &ready);
383 if (res == ERROR_WAIT) {
384 /* The adapter does not handle SWD WAIT properly,
385 * add some delay to reduce number of error messages */
386 alive_sleep(10);
387 continue;
388 }
389 if (res != ERROR_OK) {
390 LOG_ERROR("Error waiting NVMC_READY: generic flash write/erase error (check protection etc...)");
391 return res;
392 }
393
394 if (ready == 0x00000001)
395 return ERROR_OK;
396
397 keep_alive();
398
399 } while ((timeval_ms()-ts_start) < timeout_ms);
400
401 LOG_DEBUG("Timed out waiting for NVMC_READY");
402 return ERROR_FLASH_BUSY;
403 }
404
405 static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
406 {
407 int res;
408 res = nrf5_nvmc_write_u32(chip,
409 NRF5_NVMC_CONFIG,
410 NRF5_NVMC_CONFIG_EEN);
411
412 if (res != ERROR_OK) {
413 LOG_ERROR("Failed to enable erase operation");
414 return res;
415 }
416
417 /*
418 According to NVMC examples in Nordic SDK busy status must be
419 checked after writing to NVMC_CONFIG
420 */
421 res = nrf5_wait_for_nvmc(chip);
422 if (res != ERROR_OK)
423 LOG_ERROR("Erase enable did not complete");
424
425 return res;
426 }
427
428 static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
429 {
430 int res;
431 res = nrf5_nvmc_write_u32(chip,
432 NRF5_NVMC_CONFIG,
433 NRF5_NVMC_CONFIG_WEN);
434
435 if (res != ERROR_OK) {
436 LOG_ERROR("Failed to enable write operation");
437 return res;
438 }
439
440 /*
441 According to NVMC examples in Nordic SDK busy status must be
442 checked after writing to NVMC_CONFIG
443 */
444 res = nrf5_wait_for_nvmc(chip);
445 if (res != ERROR_OK)
446 LOG_ERROR("Write enable did not complete");
447
448 return res;
449 }
450
451 static int nrf5_nvmc_read_only(struct nrf5_info *chip)
452 {
453 int res;
454 res = nrf5_nvmc_write_u32(chip,
455 NRF5_NVMC_CONFIG,
456 NRF5_NVMC_CONFIG_REN);
457
458 if (res != ERROR_OK) {
459 LOG_ERROR("Failed to disable write/erase operation");
460 return res;
461 }
462 /*
463 According to NVMC examples in Nordic SDK busy status must be
464 checked after writing to NVMC_CONFIG
465 */
466 res = nrf5_wait_for_nvmc(chip);
467 if (res != ERROR_OK)
468 LOG_ERROR("Read only enable did not complete");
469
470 return res;
471 }
472
473 /* nRF51 series only */
474 static int nrf51_protect_check_clenr0(struct flash_bank *bank)
475 {
476 int res;
477 uint32_t clenr0;
478
479 struct nrf5_bank *nbank = bank->driver_priv;
480 struct nrf5_info *chip = nbank->chip;
481
482 res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
483 &clenr0);
484 if (res != ERROR_OK) {
485 LOG_ERROR("Couldn't read code region 0 size[FICR]");
486 return res;
487 }
488
489 if (clenr0 == 0xFFFFFFFF) {
490 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
491 &clenr0);
492 if (res != ERROR_OK) {
493 LOG_ERROR("Couldn't read code region 0 size[UICR]");
494 return res;
495 }
496 }
497
498 for (unsigned int i = 0; i < bank->num_sectors; i++)
499 bank->sectors[i].is_protected =
500 clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
501
502 return ERROR_OK;
503 }
504
505 /* nRF52 series only */
506 static int nrf52_protect_check_bprot(struct flash_bank *bank)
507 {
508 struct nrf5_bank *nbank = bank->driver_priv;
509 struct nrf5_info *chip = nbank->chip;
510
511 static uint32_t nrf5_bprot_offsets[4] = { 0x600, 0x604, 0x610, 0x614 };
512 uint32_t bprot_reg = 0;
513 int res;
514
515 for (unsigned int i = 0; i < bank->num_sectors; i++) {
516 unsigned int bit = i % 32;
517 if (bit == 0) {
518 unsigned int n_reg = i / 32;
519 if (n_reg >= ARRAY_SIZE(nrf5_bprot_offsets))
520 break;
521
522 res = target_read_u32(chip->target, NRF5_BPROT_BASE + nrf5_bprot_offsets[n_reg], &bprot_reg);
523 if (res != ERROR_OK)
524 return res;
525 }
526 bank->sectors[i].is_protected = (bprot_reg & (1 << bit)) ? 1 : 0;
527 }
528 return ERROR_OK;
529 }
530
531 static int nrf5_protect_check(struct flash_bank *bank)
532 {
533 struct nrf5_bank *nbank = bank->driver_priv;
534 struct nrf5_info *chip = nbank->chip;
535
536 /* UICR cannot be write protected so just return early */
537 if (nrf5_bank_is_uicr(nbank))
538 return ERROR_OK;
539
540 if (chip->features & NRF5_FEATURE_BPROT)
541 return nrf52_protect_check_bprot(bank);
542
543 if (chip->features & NRF5_FEATURE_SERIES_51)
544 return nrf51_protect_check_clenr0(bank);
545
546 LOG_WARNING("Flash protection of this nRF device is not supported");
547 return ERROR_FLASH_OPER_UNSUPPORTED;
548 }
549
550 /* nRF51 series only */
551 static int nrf51_protect_clenr0(struct flash_bank *bank, int set, unsigned int first,
552 unsigned int last)
553 {
554 int res;
555 uint32_t clenr0, ppfc;
556
557 struct nrf5_bank *nbank = bank->driver_priv;
558 struct nrf5_info *chip = nbank->chip;
559
560 if (first != 0) {
561 LOG_ERROR("Code region 0 must start at the beginning of the bank");
562 return ERROR_FAIL;
563 }
564
565 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
566 &ppfc);
567 if (res != ERROR_OK) {
568 LOG_ERROR("Couldn't read PPFC register");
569 return res;
570 }
571
572 if ((ppfc & 0xFF) == 0x00) {
573 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
574 return ERROR_FAIL;
575 }
576
577 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
578 &clenr0);
579 if (res != ERROR_OK) {
580 LOG_ERROR("Couldn't read code region 0 size from UICR");
581 return res;
582 }
583
584 if (!set || clenr0 != 0xFFFFFFFF) {
585 LOG_ERROR("You need to perform chip erase before changing the protection settings");
586 return ERROR_FAIL;
587 }
588
589 res = nrf5_nvmc_write_enable(chip);
590 if (res != ERROR_OK)
591 goto error;
592
593 clenr0 = bank->sectors[last].offset + bank->sectors[last].size;
594 res = target_write_u32(chip->target, NRF51_UICR_CLENR0, clenr0);
595
596 int res2 = nrf5_wait_for_nvmc(chip);
597
598 if (res == ERROR_OK)
599 res = res2;
600
601 if (res == ERROR_OK)
602 LOG_INFO("A reset or power cycle is required for the new protection settings to take effect.");
603 else
604 LOG_ERROR("Couldn't write code region 0 size to UICR");
605
606 error:
607 nrf5_nvmc_read_only(chip);
608
609 return res;
610 }
611
612 static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
613 unsigned int last)
614 {
615 struct nrf5_bank *nbank = bank->driver_priv;
616 struct nrf5_info *chip = nbank->chip;
617
618 /* UICR cannot be write protected so just bail out early */
619 if (nrf5_bank_is_uicr(nbank)) {
620 LOG_ERROR("UICR page does not support protection");
621 return ERROR_FLASH_OPER_UNSUPPORTED;
622 }
623
624 if (bank->target->state != TARGET_HALTED) {
625 LOG_ERROR("Target not halted");
626 return ERROR_TARGET_NOT_HALTED;
627 }
628
629 if (chip->features & NRF5_FEATURE_SERIES_51)
630 return nrf51_protect_clenr0(bank, set, first, last);
631
632 LOG_ERROR("Flash protection setting is not supported on this nRF5 device");
633 return ERROR_FLASH_OPER_UNSUPPORTED;
634 }
635
636 static bool nrf5_info_variant_to_str(uint32_t variant, char *bf, bool swap)
637 {
638 uint8_t b[4];
639
640 if (swap)
641 h_u32_to_le(b, variant);
642 else
643 h_u32_to_be(b, variant);
644
645 if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) &&
646 (isalnum(b[3]) || b[3] == 0)) {
647 memcpy(bf, b, 4);
648 bf[4] = 0;
649 return true;
650 }
651
652 strcpy(bf, "xxxx");
653 return false;
654 }
655
656 static const char *nrf5_decode_info_package(uint32_t package)
657 {
658 for (size_t i = 0; i < ARRAY_SIZE(nrf52_packages_table); i++) {
659 if (nrf52_packages_table[i].package == package)
660 return nrf52_packages_table[i].code;
661 }
662 return "xx";
663 }
664
665 static int nrf5_get_chip_type_str(const struct nrf5_info *chip, char *buf, unsigned int buf_size)
666 {
667 int res;
668 if (chip->spec) {
669 res = snprintf(buf, buf_size, "nRF%s-%s(build code: %s)",
670 chip->spec->part, chip->spec->variant, chip->spec->build_code);
671 } else if (chip->ficr_info_valid) {
672 char variant[5];
673
674 nrf5_info_variant_to_str(chip->ficr_info.variant, variant,
675 chip->features & NRF5_FEATURE_SERIES_91);
676
677 if (chip->features & (NRF5_FEATURE_SERIES_53 | NRF5_FEATURE_SERIES_91)) {
678 res = snprintf(buf, buf_size, "nRF%" PRIx32 "-%s",
679 chip->ficr_info.part, variant);
680 } else {
681 res = snprintf(buf, buf_size, "nRF%" PRIx32 "-%s%.2s(build code: %s)",
682 chip->ficr_info.part,
683 nrf5_decode_info_package(chip->ficr_info.package),
684 variant, &variant[2]);
685 }
686 } else {
687 res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%04" PRIx16 ")", chip->hwid);
688 }
689
690 /* safety: */
691 if (res <= 0 || (unsigned int)res >= buf_size) {
692 LOG_ERROR("BUG: buffer problem in %s", __func__);
693 return ERROR_FAIL;
694 }
695 return ERROR_OK;
696 }
697
698 static int nrf5_info(struct flash_bank *bank, struct command_invocation *cmd)
699 {
700 struct nrf5_bank *nbank = bank->driver_priv;
701 struct nrf5_info *chip = nbank->chip;
702
703 char chip_type_str[256];
704 if (nrf5_get_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
705 return ERROR_FAIL;
706
707 unsigned int flash_size_kb = chip->flash_num_sectors * chip->flash_page_size / 1024;
708 command_print_sameline(cmd, "%s %ukB Flash, %ukB RAM",
709 chip_type_str, flash_size_kb, chip->ram_size_kb);
710 return ERROR_OK;
711 }
712
713 static int nrf5_read_ficr_info_part(struct nrf5_info *chip, const struct nrf5_map *map,
714 const struct nrf5_ficr_map *ficr_offsets)
715 {
716 struct target *target = chip->target;
717 uint32_t ficr_base = map->ficr_base;
718
719 int res = target_read_u32(target, ficr_base + ficr_offsets->info_part, &chip->ficr_info.part);
720 if (res != ERROR_OK)
721 LOG_DEBUG("Couldn't read FICR INFO.PART register");
722
723 return res;
724 }
725
726 static int nrf51_52_partno_check(struct nrf5_info *chip)
727 {
728
729 uint32_t series = chip->ficr_info.part & 0xfffff000;
730 switch (series) {
731 case 0x51000:
732 chip->features = NRF5_FEATURE_SERIES_51;
733 return ERROR_OK;
734
735 case 0x52000:
736 chip->features = NRF5_FEATURE_SERIES_52;
737
738 switch (chip->ficr_info.part) {
739 case 0x52805:
740 case 0x52810:
741 case 0x52811:
742 case 0x52832:
743 chip->features |= NRF5_FEATURE_BPROT;
744 break;
745
746 case 0x52820:
747 case 0x52833:
748 case 0x52840:
749 chip->features |= NRF5_FEATURE_ACL_PROT;
750 break;
751 }
752 return ERROR_OK;
753
754 default:
755 LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
756 PRIx32, chip->ficr_info.part);
757 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
758 }
759 }
760
761 static int nrf53_91_partno_check(struct nrf5_info *chip)
762 {
763 uint32_t series = chip->ficr_info.part & 0xffffff00;
764 switch (series) {
765 case 0x5300:
766 chip->features = NRF5_FEATURE_SERIES_53 | NRF5_FEATURE_ERASE_BY_FLASH_WR;
767 return ERROR_OK;
768
769 case 0x9100:
770 chip->features = NRF5_FEATURE_SERIES_91 | NRF5_FEATURE_ERASE_BY_FLASH_WR;
771 return ERROR_OK;
772
773 default:
774 LOG_DEBUG("Invalid FICR INFO PART value 0x%08"
775 PRIx32, chip->ficr_info.part);
776 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
777 }
778 }
779
780 static int nrf5_read_ficr_more_info(struct nrf5_info *chip)
781 {
782 int res;
783 struct target *target = chip->target;
784 const struct nrf5_ficr_map *ficr_offsets = chip->ficr_offsets;
785 uint32_t ficr_base = chip->map->ficr_base;
786
787 res = target_read_u32(target, ficr_base + ficr_offsets->info_variant, &chip->ficr_info.variant);
788 if (res != ERROR_OK)
789 return res;
790
791 res = target_read_u32(target, ficr_base + ficr_offsets->info_package, &chip->ficr_info.package);
792 if (res != ERROR_OK)
793 return res;
794
795 res = target_read_u32(target, ficr_base + ficr_offsets->info_ram, &chip->ficr_info.ram);
796 if (res != ERROR_OK)
797 return res;
798
799 res = target_read_u32(target, ficr_base + ficr_offsets->info_flash, &chip->ficr_info.flash);
800 return res;
801 }
802
803 /* nRF51 series only */
804 static int nrf51_get_ram_size(struct target *target, uint32_t *ram_size)
805 {
806 int res;
807
808 *ram_size = 0;
809
810 uint32_t numramblock;
811 res = target_read_u32(target, NRF51_FICR_NUMRAMBLOCK, &numramblock);
812 if (res != ERROR_OK) {
813 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
814 return res;
815 }
816
817 if (numramblock < 1 || numramblock > 4) {
818 LOG_DEBUG("FICR NUMRAMBLOCK strange value %" PRIx32, numramblock);
819 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
820 }
821
822 for (unsigned int i = 0; i < numramblock; i++) {
823 uint32_t sizeramblock;
824 res = target_read_u32(target, NRF51_FICR_SIZERAMBLOCK0 + sizeof(uint32_t)*i, &sizeramblock);
825 if (res != ERROR_OK) {
826 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
827 return res;
828 }
829 if (sizeramblock < 1024 || sizeramblock > 65536)
830 LOG_DEBUG("FICR SIZERAMBLOCK strange value %" PRIx32, sizeramblock);
831 else
832 *ram_size += sizeramblock;
833 }
834 return res;
835 }
836
837 static int nrf5_probe_chip(struct flash_bank *bank)
838 {
839 int res = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
840
841 struct nrf5_bank *nbank = bank->driver_priv;
842 struct nrf5_info *chip = nbank->chip;
843 struct target *target = chip->target;
844
845 chip->spec = NULL;
846 chip->ficr_info_valid = false;
847
848 /* First try to detect nRF53/91 */
849 switch (bank->base) {
850 case NRF5_FLASH_BASE:
851 case NRF53APP_91_UICR_BASE:
852 res = nrf5_read_ficr_info_part(chip, &nrf53app_91_map, &nrf91new_ficr_offsets);
853 if (res == ERROR_OK) {
854 res = nrf53_91_partno_check(chip);
855 if (res == ERROR_OK) {
856 chip->map = &nrf53app_91_map;
857 chip->ficr_offsets = &nrf91new_ficr_offsets;
858 break;
859 }
860 }
861
862 res = nrf5_read_ficr_info_part(chip, &nrf53app_91_map, &nrf53_91_ficr_offsets);
863 if (res != ERROR_OK)
864 break;
865
866 res = nrf53_91_partno_check(chip);
867 if (res != ERROR_OK)
868 break;
869
870 chip->map = &nrf53app_91_map;
871 chip->ficr_offsets = &nrf53_91_ficr_offsets;
872 break;
873
874 case NRF53NET_FLASH_BASE:
875 case NRF53NET_UICR_BASE:
876 res = nrf5_read_ficr_info_part(chip, &nrf53net_map, &nrf53_91_ficr_offsets);
877 if (res != ERROR_OK)
878 break;
879
880 res = nrf53_91_partno_check(chip);
881 if (res != ERROR_OK)
882 break;
883
884 chip->map = &nrf53net_map;
885 chip->ficr_offsets = &nrf53_91_ficr_offsets;
886 break;
887
888 default:
889 break;
890 }
891
892 /* If nRF53/91 is not detected, try nRF51/52 */
893 if (res != ERROR_OK) {
894 /* Guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
895 chip->features = NRF5_FEATURE_SERIES_51;
896 chip->map = &nrf51_52_map;
897 chip->ficr_offsets = &nrf51_52_ficr_offsets;
898
899 /* Don't bail out on error for the case that some old engineering
900 * sample has FICR INFO registers unreadable. We can proceed anyway. */
901 res = nrf5_read_ficr_info_part(chip, chip->map, chip->ficr_offsets);
902 if (res == ERROR_OK)
903 res = nrf51_52_partno_check(chip);
904 }
905
906 if (res == ERROR_OK) {
907 /* Now we know the device has FICR INFO filled by something relevant:
908 * Although it is not documented, the tested nRF51 rev 3 devices
909 * have FICR INFO.PART, RAM and FLASH of the same format as nRF52.
910 * VARIANT and PACKAGE coding is unknown for a nRF51 device.
911 * nRF52 devices have FICR INFO documented and always filled. */
912 res = nrf5_read_ficr_more_info(chip);
913 if (res == ERROR_OK) {
914 chip->ficr_info_valid = true;
915 } else if (chip->features & NRF5_FEATURE_SERIES_51) {
916 LOG_DEBUG("Couldn't read some of FICR INFO registers");
917 } else {
918 LOG_ERROR("Couldn't read some of FICR INFO registers");
919 return res;
920 }
921 }
922
923 const struct nrf5_ficr_map *ficr_offsets = chip->ficr_offsets;
924 uint32_t ficr_base = chip->map->ficr_base;
925 uint32_t configid = 0;
926 res = target_read_u32(target, ficr_base + ficr_offsets->configid, &configid);
927 if (res != ERROR_OK) {
928 if (chip->features & NRF5_FEATURE_SERIES_51) {
929 LOG_ERROR("Couldn't read FICR CONFIGID register");
930 return res;
931 }
932
933 LOG_DEBUG("Couldn't read FICR CONFIGID register, using FICR INFO");
934 }
935
936 /* HWID is stored in the lower two bytes of the CONFIGID register */
937 chip->hwid = configid & 0xFFFF;
938
939 for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
940 if (chip->hwid == nrf5_known_devices_table[i].hwid) {
941 chip->spec = &nrf5_known_devices_table[i];
942 chip->features = chip->spec->features;
943 break;
944 }
945 }
946
947 if (chip->spec && chip->ficr_info_valid) {
948 /* check if HWID table gives the same part as FICR INFO */
949 if (chip->ficr_info.part != strtoul(chip->spec->part, NULL, 16))
950 LOG_WARNING("HWID 0x%04" PRIx32 " mismatch: FICR INFO.PART %"
951 PRIx32, chip->hwid, chip->ficr_info.part);
952 }
953
954 if (chip->ficr_info_valid) {
955 chip->ram_size_kb = chip->ficr_info.ram;
956 } else if (chip->features & NRF5_FEATURE_SERIES_51) {
957 uint32_t ram_size;
958 nrf51_get_ram_size(target, &ram_size);
959 chip->ram_size_kb = ram_size / 1024;
960 } else {
961 chip->ram_size_kb = 0;
962 }
963
964 /* The value stored in FICR CODEPAGESIZE is the number of bytes in one page of FLASH. */
965 res = target_read_u32(chip->target, ficr_base + ficr_offsets->codepagesize,
966 &chip->flash_page_size);
967 if (res != ERROR_OK) {
968 LOG_ERROR("Couldn't read code page size");
969 return res;
970 }
971
972 /* Note the register name is misleading,
973 * FICR CODESIZE is the number of pages in flash memory, not the number of bytes! */
974 res = target_read_u32(chip->target, ficr_base + ficr_offsets->codesize,
975 &chip->flash_num_sectors);
976 if (res != ERROR_OK) {
977 LOG_ERROR("Couldn't read code memory size");
978 return res;
979 }
980
981 char chip_type_str[256];
982 if (nrf5_get_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
983 return ERROR_FAIL;
984
985 unsigned int flash_size_kb = chip->flash_num_sectors * chip->flash_page_size / 1024;
986 const bool device_is_unknown = (!chip->spec && !chip->ficr_info_valid);
987 LOG_INFO("%s%s %ukB Flash, %ukB RAM",
988 device_is_unknown ? "Unknown device: " : "",
989 chip_type_str,
990 flash_size_kb,
991 chip->ram_size_kb);
992
993 chip->chip_probed = true;
994 return ERROR_OK;
995 }
996
997 static int nrf5_setup_bank(struct flash_bank *bank)
998 {
999 struct nrf5_bank *nbank = bank->driver_priv;
1000 struct nrf5_info *chip = nbank->chip;
1001
1002 if (bank->base == chip->map->flash_base) {
1003 unsigned int flash_size_kb = chip->flash_num_sectors * chip->flash_page_size / 1024;
1004 /* Sanity check */
1005 if (chip->spec && flash_size_kb != chip->spec->flash_size_kb)
1006 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
1007 if (chip->ficr_info_valid && flash_size_kb != chip->ficr_info.flash)
1008 LOG_WARNING("Chip's reported Flash capacity does not match FICR INFO.FLASH");
1009
1010 bank->num_sectors = chip->flash_num_sectors;
1011 bank->size = chip->flash_num_sectors * chip->flash_page_size;
1012
1013 bank->sectors = alloc_block_array(0, chip->flash_page_size, bank->num_sectors);
1014 if (!bank->sectors)
1015 return ERROR_FAIL;
1016
1017 chip->bank[0].probed = true;
1018
1019 } else if (bank->base == chip->map->uicr_base) {
1020 /* UICR bank */
1021 bank->num_sectors = 1;
1022 bank->size = chip->flash_page_size;
1023
1024 bank->sectors = alloc_block_array(0, chip->flash_page_size, bank->num_sectors);
1025 if (!bank->sectors)
1026 return ERROR_FAIL;
1027
1028 bank->sectors[0].is_protected = 0;
1029
1030 chip->bank[1].probed = true;
1031 } else {
1032 LOG_ERROR("Invalid nRF bank address " TARGET_ADDR_FMT, bank->base);
1033 return ERROR_FLASH_BANK_INVALID;
1034 }
1035
1036 return ERROR_OK;
1037 }
1038
1039 static int nrf5_probe(struct flash_bank *bank)
1040 {
1041 /* probe always reads actual info from the device */
1042 int res = nrf5_probe_chip(bank);
1043 if (res != ERROR_OK)
1044 return res;
1045
1046 return nrf5_setup_bank(bank);
1047 }
1048
1049 static int nrf5_auto_probe(struct flash_bank *bank)
1050 {
1051 if (nrf5_bank_is_probed(bank))
1052 return ERROR_OK;
1053
1054 if (!nrf5_chip_is_probed(bank)) {
1055 int res = nrf5_probe_chip(bank);
1056 if (res != ERROR_OK)
1057 return res;
1058 }
1059
1060 return nrf5_setup_bank(bank);
1061 }
1062
1063
1064 static int nrf5_erase_page(struct flash_bank *bank,
1065 struct nrf5_info *chip,
1066 struct flash_sector *sector)
1067 {
1068 int res;
1069
1070 LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
1071
1072 if (bank->base == chip->map->uicr_base) {
1073 if (chip->features & NRF5_FEATURE_SERIES_51) {
1074 uint32_t ppfc;
1075 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
1076 &ppfc);
1077 if (res != ERROR_OK) {
1078 LOG_ERROR("Couldn't read PPFC register");
1079 return res;
1080 }
1081
1082 if ((ppfc & 0xFF) == 0xFF) {
1083 /* We can't erase the UICR. Double-check to
1084 see if it's already erased before complaining. */
1085 default_flash_blank_check(bank);
1086 if (sector->is_erased == 1)
1087 return ERROR_OK;
1088
1089 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
1090 return ERROR_FAIL;
1091 }
1092 }
1093
1094 res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_ERASEUICR, 0x00000001);
1095
1096 } else if (chip->features & NRF5_FEATURE_ERASE_BY_FLASH_WR) {
1097 res = target_write_u32(chip->target, bank->base + sector->offset, 0xffffffff);
1098 /* nRF9160 errata [2] NVMC: CPU code execution from RAM halted during
1099 * flash page erase operation
1100 * https://infocenter.nordicsemi.com/index.jsp?topic=%2Ferrata_nRF9160_Rev1%2FERR%2FnRF9160%2FRev1%2Flatest%2Fanomaly_160_2.html
1101 * affects also erasing by debugger MEM-AP write:
1102 *
1103 * Write to a flash address stalls the bus for 87 ms until
1104 * page erase finishes! This makes problems if the adapter does not
1105 * handle SWD WAIT properly or does not wait long enough.
1106 * Using a target algo would not help, AP gets unresponsive too.
1107 * Neither sending AP ABORT helps, the next AP access stalls again.
1108 * Simply wait long enough before accessing AP again...
1109 *
1110 * The same errata was observed in nRF9161
1111 */
1112 if (chip->features & NRF5_FEATURE_SERIES_91)
1113 alive_sleep(90);
1114
1115 } else {
1116 res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_ERASEPAGE, sector->offset);
1117 }
1118
1119 if (res != ERROR_OK) {
1120 /* caller logs the error */
1121 return res;
1122 }
1123
1124 res = nrf5_wait_for_nvmc(chip);
1125 return res;
1126 }
1127
1128 /* Start a low level flash write for the specified region */
1129 static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const uint8_t *buffer, uint32_t bytes)
1130 {
1131 struct target *target = chip->target;
1132 uint32_t buffer_size = 8192;
1133 struct working_area *write_algorithm;
1134 struct working_area *source;
1135 struct reg_param reg_params[6];
1136 struct armv7m_algorithm armv7m_info;
1137 int retval = ERROR_OK;
1138
1139 static const uint8_t nrf5_flash_write_code[] = {
1140 #include "../../../contrib/loaders/flash/nrf5/nrf5.inc"
1141 };
1142
1143 LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32" bytes=0x%"PRIx32, address, bytes);
1144 assert(bytes % 4 == 0);
1145
1146 /* allocate working area with flash programming code */
1147 if (target_alloc_working_area(target, sizeof(nrf5_flash_write_code),
1148 &write_algorithm) != ERROR_OK) {
1149 LOG_WARNING("no working area available, falling back to slow memory writes");
1150
1151 for (; bytes > 0; bytes -= 4) {
1152 retval = target_write_memory(target, address, 4, 1, buffer);
1153 if (retval != ERROR_OK)
1154 return retval;
1155
1156 retval = nrf5_wait_for_nvmc(chip);
1157 if (retval != ERROR_OK)
1158 return retval;
1159
1160 address += 4;
1161 buffer += 4;
1162 }
1163
1164 return ERROR_OK;
1165 }
1166
1167 retval = target_write_buffer(target, write_algorithm->address,
1168 sizeof(nrf5_flash_write_code),
1169 nrf5_flash_write_code);
1170 if (retval != ERROR_OK)
1171 return retval;
1172
1173 /* memory buffer */
1174 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
1175 buffer_size /= 2;
1176 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
1177 if (buffer_size <= 256) {
1178 /* free working area, write algorithm already allocated */
1179 target_free_working_area(target, write_algorithm);
1180
1181 LOG_WARNING("No large enough working area available, can't do block memory writes");
1182 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1183 }
1184 }
1185
1186 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1187 armv7m_info.core_mode = ARM_MODE_THREAD;
1188
1189 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
1190 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer start */
1191 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer end */
1192 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
1193 init_reg_param(&reg_params[4], "r6", 32, PARAM_OUT); /* watchdog refresh value */
1194 init_reg_param(&reg_params[5], "r7", 32, PARAM_OUT); /* watchdog refresh register address */
1195
1196 buf_set_u32(reg_params[0].value, 0, 32, bytes);
1197 buf_set_u32(reg_params[1].value, 0, 32, source->address);
1198 buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
1199 buf_set_u32(reg_params[3].value, 0, 32, address);
1200 buf_set_u32(reg_params[4].value, 0, 32, WATCHDOG_REFRESH_VALUE);
1201 buf_set_u32(reg_params[5].value, 0, 32, chip->map->watchdog_refresh_addr);
1202
1203 retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
1204 0, NULL,
1205 ARRAY_SIZE(reg_params), reg_params,
1206 source->address, source->size,
1207 write_algorithm->address, write_algorithm->address + sizeof(nrf5_flash_write_code) - 2,
1208 &armv7m_info);
1209
1210 target_free_working_area(target, source);
1211 target_free_working_area(target, write_algorithm);
1212
1213 destroy_reg_param(&reg_params[0]);
1214 destroy_reg_param(&reg_params[1]);
1215 destroy_reg_param(&reg_params[2]);
1216 destroy_reg_param(&reg_params[3]);
1217 destroy_reg_param(&reg_params[4]);
1218 destroy_reg_param(&reg_params[5]);
1219
1220 return retval;
1221 }
1222
1223 static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer,
1224 uint32_t offset, uint32_t count)
1225 {
1226 int res;
1227
1228 if (bank->target->state != TARGET_HALTED) {
1229 LOG_ERROR("Target not halted");
1230 return ERROR_TARGET_NOT_HALTED;
1231 }
1232
1233 struct nrf5_bank *nbank = bank->driver_priv;
1234 struct nrf5_info *chip = nbank->chip;
1235
1236 assert(offset % 4 == 0);
1237 assert(count % 4 == 0);
1238
1239 /* UICR CLENR0 based protection used on nRF51 is somewhat clumsy:
1240 * RM reads: Code running from code region 1 will not be able to write
1241 * to code region 0.
1242 * Unfortunately the flash loader running from RAM can write to both
1243 * code regions without any hint the protection is violated.
1244 *
1245 * Update protection state and check if any flash sector to be written
1246 * is protected. */
1247 if (chip->features & NRF5_FEATURE_SERIES_51) {
1248
1249 res = nrf51_protect_check_clenr0(bank);
1250 if (res != ERROR_OK)
1251 return res;
1252
1253 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
1254 struct flash_sector *bs = &bank->sectors[sector];
1255
1256 /* Start offset in or before this sector? */
1257 /* End offset in or behind this sector? */
1258 if ((offset < (bs->offset + bs->size))
1259 && ((offset + count - 1) >= bs->offset)
1260 && bs->is_protected == 1) {
1261 LOG_ERROR("Write refused, sector %d is protected", sector);
1262 return ERROR_FLASH_PROTECTED;
1263 }
1264 }
1265 }
1266
1267 res = nrf5_nvmc_write_enable(chip);
1268 if (res != ERROR_OK)
1269 goto error;
1270
1271 res = nrf5_ll_flash_write(chip, bank->base + offset, buffer, count);
1272 if (res != ERROR_OK)
1273 goto error;
1274
1275 return nrf5_nvmc_read_only(chip);
1276
1277 error:
1278 nrf5_nvmc_read_only(chip);
1279 LOG_ERROR("Failed to write to nrf5 flash");
1280 return res;
1281 }
1282
1283 static int nrf5_erase(struct flash_bank *bank, unsigned int first,
1284 unsigned int last)
1285 {
1286 int res;
1287
1288 if (bank->target->state != TARGET_HALTED) {
1289 LOG_ERROR("Target not halted");
1290 return ERROR_TARGET_NOT_HALTED;
1291 }
1292
1293 struct nrf5_bank *nbank = bank->driver_priv;
1294 struct nrf5_info *chip = nbank->chip;
1295
1296 /* UICR CLENR0 based protection used on nRF51 prevents erase
1297 * absolutely silently. NVMC has no flag to indicate the protection
1298 * was violated.
1299 *
1300 * Update protection state and check if any flash sector to be erased
1301 * is protected. */
1302 if (chip->features & NRF5_FEATURE_SERIES_51) {
1303
1304 res = nrf51_protect_check_clenr0(bank);
1305 if (res != ERROR_OK)
1306 return res;
1307 }
1308
1309 res = nrf5_nvmc_erase_enable(chip);
1310 if (res != ERROR_OK)
1311 goto error;
1312
1313 /* For each sector to be erased */
1314 for (unsigned int s = first; s <= last; s++) {
1315
1316 if (chip->features & NRF5_FEATURE_SERIES_51
1317 && bank->sectors[s].is_protected == 1) {
1318 LOG_ERROR("Flash sector %d is protected", s);
1319 res = ERROR_FLASH_PROTECTED;
1320 break;
1321 }
1322
1323 res = nrf5_erase_page(bank, chip, &bank->sectors[s]);
1324 if (res != ERROR_OK) {
1325 LOG_ERROR("Error erasing sector %d", s);
1326 return res;
1327 }
1328 }
1329
1330 error:
1331 nrf5_nvmc_read_only(chip);
1332 return res;
1333 }
1334
1335 static void nrf5_free_driver_priv(struct flash_bank *bank)
1336 {
1337 struct nrf5_bank *nbank = bank->driver_priv;
1338 struct nrf5_info *chip = nbank->chip;
1339 if (!chip)
1340 return;
1341
1342 chip->refcount--;
1343 if (chip->refcount == 0) {
1344 free(chip);
1345 bank->driver_priv = NULL;
1346 }
1347 }
1348
1349 static struct nrf5_info *nrf5_get_chip(struct target *target)
1350 {
1351 struct flash_bank *bank_iter;
1352
1353 /* iterate over nrf5 banks of same target */
1354 for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
1355 if (bank_iter->driver != &nrf5_flash && bank_iter->driver != &nrf51_flash)
1356 continue;
1357
1358 if (bank_iter->target != target)
1359 continue;
1360
1361 struct nrf5_bank *nbank = bank_iter->driver_priv;
1362 if (!nbank)
1363 continue;
1364
1365 if (nbank->chip)
1366 return nbank->chip;
1367 }
1368 return NULL;
1369 }
1370
1371 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
1372 {
1373 struct nrf5_info *chip;
1374 struct nrf5_bank *nbank = NULL;
1375
1376 if (bank->driver == &nrf51_flash)
1377 LOG_WARNING("Flash driver 'nrf51' is deprecated! Use 'nrf5' instead.");
1378
1379 switch (bank->base) {
1380 case NRF5_FLASH_BASE:
1381 case NRF53NET_FLASH_BASE:
1382 case NRF51_52_UICR_BASE:
1383 case NRF53APP_91_UICR_BASE:
1384 case NRF53NET_UICR_BASE:
1385 break;
1386 default:
1387 LOG_ERROR("Invalid nRF bank address " TARGET_ADDR_FMT, bank->base);
1388 return ERROR_FLASH_BANK_INVALID;
1389 }
1390
1391 chip = nrf5_get_chip(bank->target);
1392 if (!chip) {
1393 /* Create a new chip */
1394 chip = calloc(1, sizeof(*chip));
1395 if (!chip)
1396 return ERROR_FAIL;
1397
1398 chip->target = bank->target;
1399 }
1400
1401 switch (bank->base) {
1402 case NRF5_FLASH_BASE:
1403 case NRF53NET_FLASH_BASE:
1404 nbank = &chip->bank[0];
1405 break;
1406 case NRF51_52_UICR_BASE:
1407 case NRF53APP_91_UICR_BASE:
1408 case NRF53NET_UICR_BASE:
1409 nbank = &chip->bank[1];
1410 break;
1411 }
1412 assert(nbank);
1413
1414 chip->refcount++;
1415 nbank->chip = chip;
1416 nbank->probed = false;
1417 bank->driver_priv = nbank;
1418 bank->write_start_alignment = bank->write_end_alignment = 4;
1419
1420 return ERROR_OK;
1421 }
1422
1423 COMMAND_HANDLER(nrf5_handle_mass_erase_command)
1424 {
1425 int res;
1426 struct flash_bank *bank = NULL;
1427 struct target *target = get_current_target(CMD_CTX);
1428
1429 res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1430 if (res != ERROR_OK)
1431 return res;
1432
1433 if (target->state != TARGET_HALTED) {
1434 LOG_ERROR("Target not halted");
1435 return ERROR_TARGET_NOT_HALTED;
1436 }
1437
1438 struct nrf5_bank *nbank = bank->driver_priv;
1439 struct nrf5_info *chip = nbank->chip;
1440
1441 if (chip->features & NRF5_FEATURE_SERIES_51) {
1442 uint32_t ppfc;
1443 res = target_read_u32(target, NRF51_FICR_PPFC,
1444 &ppfc);
1445 if (res != ERROR_OK) {
1446 LOG_ERROR("Couldn't read PPFC register");
1447 return res;
1448 }
1449
1450 if ((ppfc & 0xFF) == 0x00) {
1451 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1452 "mass erase command won't work.");
1453 return ERROR_FAIL;
1454 }
1455 }
1456
1457 res = nrf5_nvmc_erase_enable(chip);
1458 if (res != ERROR_OK)
1459 goto error;
1460
1461 res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_ERASEALL, 0x00000001);
1462 if (res != ERROR_OK) {
1463 LOG_ERROR("Mass erase failed");
1464 goto error;
1465 }
1466
1467 res = nrf5_wait_for_nvmc(chip);
1468 if (res != ERROR_OK)
1469 LOG_ERROR("Mass erase did not complete");
1470
1471 error:
1472 nrf5_nvmc_read_only(chip);
1473
1474 if (res == ERROR_OK) {
1475 LOG_INFO("Mass erase completed.");
1476 if (chip->features & NRF5_FEATURE_SERIES_51)
1477 LOG_INFO("A reset or power cycle is required if the flash was protected before.");
1478 }
1479
1480 return res;
1481 }
1482
1483
1484 static const struct command_registration nrf5_exec_command_handlers[] = {
1485 {
1486 .name = "mass_erase",
1487 .handler = nrf5_handle_mass_erase_command,
1488 .mode = COMMAND_EXEC,
1489 .help = "Erase all flash contents of the chip.",
1490 .usage = "",
1491 },
1492 COMMAND_REGISTRATION_DONE
1493 };
1494
1495 static const struct command_registration nrf5_command_handlers[] = {
1496 {
1497 .name = "nrf5",
1498 .mode = COMMAND_ANY,
1499 .help = "nrf5 flash command group",
1500 .usage = "",
1501 .chain = nrf5_exec_command_handlers,
1502 },
1503 {
1504 .name = "nrf51",
1505 .mode = COMMAND_ANY,
1506 .help = "nrf51 flash command group",
1507 .usage = "",
1508 .chain = nrf5_exec_command_handlers,
1509 },
1510 COMMAND_REGISTRATION_DONE
1511 };
1512
1513 const struct flash_driver nrf5_flash = {
1514 .name = "nrf5",
1515 .commands = nrf5_command_handlers,
1516 .flash_bank_command = nrf5_flash_bank_command,
1517 .info = nrf5_info,
1518 .erase = nrf5_erase,
1519 .protect = nrf5_protect,
1520 .write = nrf5_write,
1521 .read = default_flash_read,
1522 .probe = nrf5_probe,
1523 .auto_probe = nrf5_auto_probe,
1524 .erase_check = default_flash_blank_check,
1525 .protect_check = nrf5_protect_check,
1526 .free_driver_priv = nrf5_free_driver_priv,
1527 };
1528
1529 /* We need to retain the flash-driver name as well as the commands
1530 * for backwards compatibility */
1531 const struct flash_driver nrf51_flash = {
1532 .name = "nrf51",
1533 .commands = nrf5_command_handlers,
1534 .flash_bank_command = nrf5_flash_bank_command,
1535 .info = nrf5_info,
1536 .erase = nrf5_erase,
1537 .protect = nrf5_protect,
1538 .write = nrf5_write,
1539 .read = default_flash_read,
1540 .probe = nrf5_probe,
1541 .auto_probe = nrf5_auto_probe,
1542 .erase_check = default_flash_blank_check,
1543 .protect_check = nrf5_protect_check,
1544 .free_driver_priv = nrf5_free_driver_priv,
1545 };
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