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flash/nor/nrf5, target/nrf51: deprecate nrf51 flash driver
[openocd.git] / src / flash / nor / nrf5.c
blob18efae5c6d90587011e8c859879206eb54e09d02
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2013 Synapse Product Development *
5 * Andrey Smirnov <andrew.smironv@gmail.com> *
6 * Angus Gratton <gus@projectgus.com> *
7 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
8 ***************************************************************************/
9
10 #ifdef HAVE_CONFIG_H
11 #include "config.h"
12 #endif
13
14 #include "imp.h"
15 #include <helper/binarybuffer.h>
16 #include <target/algorithm.h>
17 #include <target/armv7m.h>
18 #include <helper/types.h>
19 #include <helper/time_support.h>
20
21 /* Both those values are constant across the current spectrum ofr nRF5 devices */
22 #define WATCHDOG_REFRESH_REGISTER 0x40010600
23 #define WATCHDOG_REFRESH_VALUE 0x6e524635
24
25 enum {
26 NRF5_FLASH_BASE = 0x00000000,
27 };
28
29 enum nrf5_ficr_registers {
30 NRF5_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
31
32 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
33
34 NRF5_FICR_CODEPAGESIZE = NRF5_FICR_REG(0x010),
35 NRF5_FICR_CODESIZE = NRF5_FICR_REG(0x014),
36
37 NRF51_FICR_CLENR0 = NRF5_FICR_REG(0x028),
38 NRF51_FICR_PPFC = NRF5_FICR_REG(0x02C),
39 NRF51_FICR_NUMRAMBLOCK = NRF5_FICR_REG(0x034),
40 NRF51_FICR_SIZERAMBLOCK0 = NRF5_FICR_REG(0x038),
41 NRF51_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
42 NRF51_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
43 NRF51_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
44
45 /* CONFIGID is documented on nRF51 series only.
46 * On nRF52 is present but not documented */
47 NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
48
49 NRF5_FICR_DEVICEID0 = NRF5_FICR_REG(0x060),
50 NRF5_FICR_DEVICEID1 = NRF5_FICR_REG(0x064),
51 NRF5_FICR_ER0 = NRF5_FICR_REG(0x080),
52 NRF5_FICR_ER1 = NRF5_FICR_REG(0x084),
53 NRF5_FICR_ER2 = NRF5_FICR_REG(0x088),
54 NRF5_FICR_ER3 = NRF5_FICR_REG(0x08C),
55 NRF5_FICR_IR0 = NRF5_FICR_REG(0x090),
56 NRF5_FICR_IR1 = NRF5_FICR_REG(0x094),
57 NRF5_FICR_IR2 = NRF5_FICR_REG(0x098),
58 NRF5_FICR_IR3 = NRF5_FICR_REG(0x09C),
59 NRF5_FICR_DEVICEADDRTYPE = NRF5_FICR_REG(0x0A0),
60 NRF5_FICR_DEVICEADDR0 = NRF5_FICR_REG(0x0A4),
61 NRF5_FICR_DEVICEADDR1 = NRF5_FICR_REG(0x0A8),
62
63 NRF51_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC),
64 NRF51_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0),
65 NRF51_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4),
66 NRF51_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8),
67 NRF51_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC),
68 NRF51_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0),
69 NRF51_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC),
70 NRF51_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0),
71 NRF51_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4),
72 NRF51_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8),
73 NRF51_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC),
74
75 /* Following registers are available on nRF52 and on nRF51 since rev 3 */
76 NRF5_FICR_INFO_PART = NRF5_FICR_REG(0x100),
77 NRF5_FICR_INFO_VARIANT = NRF5_FICR_REG(0x104),
78 NRF5_FICR_INFO_PACKAGE = NRF5_FICR_REG(0x108),
79 NRF5_FICR_INFO_RAM = NRF5_FICR_REG(0x10C),
80 NRF5_FICR_INFO_FLASH = NRF5_FICR_REG(0x110),
81 };
82
83 enum nrf5_uicr_registers {
84 NRF5_UICR_BASE = 0x10001000, /* User Information
85 * Configuration Registers */
86
87 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
88
89 NRF51_UICR_CLENR0 = NRF5_UICR_REG(0x000),
90 NRF51_UICR_RBPCONF = NRF5_UICR_REG(0x004),
91 NRF51_UICR_XTALFREQ = NRF5_UICR_REG(0x008),
92 NRF51_UICR_FWID = NRF5_UICR_REG(0x010),
93 };
94
95 enum nrf5_nvmc_registers {
96 NRF5_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
97 * Controller Registers */
98
99 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
100
101 NRF5_NVMC_READY = NRF5_NVMC_REG(0x400),
102 NRF5_NVMC_CONFIG = NRF5_NVMC_REG(0x504),
103 NRF5_NVMC_ERASEPAGE = NRF5_NVMC_REG(0x508),
104 NRF5_NVMC_ERASEALL = NRF5_NVMC_REG(0x50C),
105 NRF5_NVMC_ERASEUICR = NRF5_NVMC_REG(0x514),
106
107 NRF5_BPROT_BASE = 0x40000000,
108 };
109
110 enum nrf5_nvmc_config_bits {
111 NRF5_NVMC_CONFIG_REN = 0x00,
112 NRF5_NVMC_CONFIG_WEN = 0x01,
113 NRF5_NVMC_CONFIG_EEN = 0x02,
114
115 };
116
117 struct nrf52_ficr_info {
118 uint32_t part;
119 uint32_t variant;
120 uint32_t package;
121 uint32_t ram;
122 uint32_t flash;
123 };
124
125 enum nrf5_features {
126 NRF5_FEATURE_SERIES_51 = 1 << 0,
127 NRF5_FEATURE_SERIES_52 = 1 << 1,
128 NRF5_FEATURE_BPROT = 1 << 2,
129 NRF5_FEATURE_ACL_PROT = 1 << 3,
130 };
131
132 struct nrf5_device_spec {
133 uint16_t hwid;
134 const char *part;
135 const char *variant;
136 const char *build_code;
137 unsigned int flash_size_kb;
138 enum nrf5_features features;
139 };
140
141 struct nrf5_info {
142 unsigned int refcount;
143
144 struct nrf5_bank {
145 struct nrf5_info *chip;
146 bool probed;
147 } bank[2];
148 struct target *target;
149
150 /* chip identification stored in nrf5_probe() for use in nrf5_info() */
151 bool ficr_info_valid;
152 struct nrf52_ficr_info ficr_info;
153 const struct nrf5_device_spec *spec;
154 uint16_t hwid;
155 enum nrf5_features features;
156 unsigned int flash_size_kb;
157 unsigned int ram_size_kb;
158 };
159
160 #define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
161 { \
162 .hwid = (id), \
163 .part = pt, \
164 .variant = var, \
165 .build_code = bcode, \
166 .flash_size_kb = (fsize), \
167 .features = NRF5_FEATURE_SERIES_51, \
168 }
169
170 /*
171 * The table maps known HWIDs to the part numbers, variant
172 * build code and some other info. For nRF51 rev 1 and 2 devices
173 * this is the only way how to get the part number and variant.
174 *
175 * All tested nRF51 rev 3 devices have FICR INFO fields
176 * but the fields are not documented in RM so we keep HWIDs in
177 * this table.
178 *
179 * nRF52 and newer devices have FICR INFO documented, the autodetection
180 * can rely on it and HWIDs table is not used.
181 *
182 * The known devices table below is derived from the "nRF5x series
183 * compatibility matrix" documents.
184 *
185 * Up to date with Matrix v2.0, plus some additional HWIDs.
186 *
187 * The additional HWIDs apply where the build code in the matrix is
188 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
189 * for x==0, x!=0 means different (unspecified) HWIDs.
190 */
191 static const struct nrf5_device_spec nrf5_known_devices_table[] = {
192 /* nRF51822 Devices (IC rev 1). */
193 NRF51_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
194 NRF51_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
195 NRF51_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
196 NRF51_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
197 NRF51_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
198
199 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
200 with built-in jlink seem to use engineering samples not listed
201 in the nRF51 Series Compatibility Matrix V1.0. */
202 NRF51_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
203
204 /* nRF51822 Devices (IC rev 2). */
205 NRF51_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
206 NRF51_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
207 NRF51_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
208 NRF51_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
209 NRF51_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
210 NRF51_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
211 NRF51_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
212 NRF51_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
213 NRF51_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
214
215 /* nRF51822 Devices (IC rev 3). */
216 NRF51_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
217 NRF51_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
218 NRF51_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
219 NRF51_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
220 NRF51_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
221 NRF51_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
222 NRF51_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
223 NRF51_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
224 NRF51_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
225
226 /* nRF51422 Devices (IC rev 1). */
227 NRF51_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
228 NRF51_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
229 NRF51_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
230
231 /* nRF51422 Devices (IC rev 2). */
232 NRF51_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
233 NRF51_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
234 NRF51_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
235 NRF51_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
236
237 /* nRF51422 Devices (IC rev 3). */
238 NRF51_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
239 NRF51_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
240 NRF51_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
241 NRF51_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
242 NRF51_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
243 NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
244 NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
245
246 /* The driver fully autodetects nRF52 series devices by FICR INFO,
247 * no need for nRF52xxx HWIDs in this table */
248 };
249
250 struct nrf5_device_package {
251 uint32_t package;
252 const char *code;
253 };
254
255 /* Newer devices have FICR INFO.PACKAGE.
256 * This table converts its value to two character code */
257 static const struct nrf5_device_package nrf5_packages_table[] = {
258 { 0x2000, "QF" },
259 { 0x2001, "CH" },
260 { 0x2002, "CI" },
261 { 0x2005, "CK" },
262 };
263
264 const struct flash_driver nrf5_flash, nrf51_flash;
265
266 static bool nrf5_bank_is_probed(const struct flash_bank *bank)
267 {
268 struct nrf5_bank *nbank = bank->driver_priv;
269
270 assert(nbank);
271
272 return nbank->probed;
273 }
274 static int nrf5_probe(struct flash_bank *bank);
275
276 static int nrf5_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf5_info **chip)
277 {
278 if (bank->target->state != TARGET_HALTED) {
279 LOG_ERROR("Target not halted");
280 return ERROR_TARGET_NOT_HALTED;
281 }
282
283 struct nrf5_bank *nbank = bank->driver_priv;
284 *chip = nbank->chip;
285
286 if (nrf5_bank_is_probed(bank))
287 return ERROR_OK;
288
289 return nrf5_probe(bank);
290 }
291
292 static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
293 {
294 uint32_t ready;
295 int res;
296 int timeout_ms = 340;
297 int64_t ts_start = timeval_ms();
298
299 do {
300 res = target_read_u32(chip->target, NRF5_NVMC_READY, &ready);
301 if (res != ERROR_OK) {
302 LOG_ERROR("Error waiting NVMC_READY: generic flash write/erase error (check protection etc...)");
303 return res;
304 }
305
306 if (ready == 0x00000001)
307 return ERROR_OK;
308
309 keep_alive();
310
311 } while ((timeval_ms()-ts_start) < timeout_ms);
312
313 LOG_DEBUG("Timed out waiting for NVMC_READY");
314 return ERROR_FLASH_BUSY;
315 }
316
317 static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
318 {
319 int res;
320 res = target_write_u32(chip->target,
321 NRF5_NVMC_CONFIG,
322 NRF5_NVMC_CONFIG_EEN);
323
324 if (res != ERROR_OK) {
325 LOG_ERROR("Failed to enable erase operation");
326 return res;
327 }
328
329 /*
330 According to NVMC examples in Nordic SDK busy status must be
331 checked after writing to NVMC_CONFIG
332 */
333 res = nrf5_wait_for_nvmc(chip);
334 if (res != ERROR_OK)
335 LOG_ERROR("Erase enable did not complete");
336
337 return res;
338 }
339
340 static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
341 {
342 int res;
343 res = target_write_u32(chip->target,
344 NRF5_NVMC_CONFIG,
345 NRF5_NVMC_CONFIG_WEN);
346
347 if (res != ERROR_OK) {
348 LOG_ERROR("Failed to enable write operation");
349 return res;
350 }
351
352 /*
353 According to NVMC examples in Nordic SDK busy status must be
354 checked after writing to NVMC_CONFIG
355 */
356 res = nrf5_wait_for_nvmc(chip);
357 if (res != ERROR_OK)
358 LOG_ERROR("Write enable did not complete");
359
360 return res;
361 }
362
363 static int nrf5_nvmc_read_only(struct nrf5_info *chip)
364 {
365 int res;
366 res = target_write_u32(chip->target,
367 NRF5_NVMC_CONFIG,
368 NRF5_NVMC_CONFIG_REN);
369
370 if (res != ERROR_OK) {
371 LOG_ERROR("Failed to enable read-only operation");
372 return res;
373 }
374 /*
375 According to NVMC examples in Nordic SDK busy status must be
376 checked after writing to NVMC_CONFIG
377 */
378 res = nrf5_wait_for_nvmc(chip);
379 if (res != ERROR_OK)
380 LOG_ERROR("Read only enable did not complete");
381
382 return res;
383 }
384
385 static int nrf5_nvmc_generic_erase(struct nrf5_info *chip,
386 uint32_t erase_register, uint32_t erase_value)
387 {
388 int res;
389
390 res = nrf5_nvmc_erase_enable(chip);
391 if (res != ERROR_OK)
392 goto error;
393
394 res = target_write_u32(chip->target,
395 erase_register,
396 erase_value);
397 if (res != ERROR_OK)
398 goto set_read_only;
399
400 res = nrf5_wait_for_nvmc(chip);
401 if (res != ERROR_OK)
402 goto set_read_only;
403
404 return nrf5_nvmc_read_only(chip);
405
406 set_read_only:
407 nrf5_nvmc_read_only(chip);
408 error:
409 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
410 erase_register, erase_value);
411 return ERROR_FAIL;
412 }
413
414 static int nrf5_protect_check_clenr0(struct flash_bank *bank)
415 {
416 int res;
417 uint32_t clenr0;
418 struct nrf5_bank *nbank = bank->driver_priv;
419 struct nrf5_info *chip = nbank->chip;
420
421 assert(chip);
422
423 res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
424 &clenr0);
425 if (res != ERROR_OK) {
426 LOG_ERROR("Couldn't read code region 0 size[FICR]");
427 return res;
428 }
429
430 if (clenr0 == 0xFFFFFFFF) {
431 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
432 &clenr0);
433 if (res != ERROR_OK) {
434 LOG_ERROR("Couldn't read code region 0 size[UICR]");
435 return res;
436 }
437 }
438
439 for (unsigned int i = 0; i < bank->num_sectors; i++)
440 bank->sectors[i].is_protected =
441 clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
442
443 return ERROR_OK;
444 }
445
446 static int nrf5_protect_check_bprot(struct flash_bank *bank)
447 {
448 struct nrf5_bank *nbank = bank->driver_priv;
449 struct nrf5_info *chip = nbank->chip;
450
451 assert(chip);
452
453 static uint32_t nrf5_bprot_offsets[4] = { 0x600, 0x604, 0x610, 0x614 };
454 uint32_t bprot_reg = 0;
455 int res;
456
457 for (unsigned int i = 0; i < bank->num_sectors; i++) {
458 unsigned int bit = i % 32;
459 if (bit == 0) {
460 unsigned int n_reg = i / 32;
461 if (n_reg >= ARRAY_SIZE(nrf5_bprot_offsets))
462 break;
463
464 res = target_read_u32(chip->target, NRF5_BPROT_BASE + nrf5_bprot_offsets[n_reg], &bprot_reg);
465 if (res != ERROR_OK)
466 return res;
467 }
468 bank->sectors[i].is_protected = (bprot_reg & (1 << bit)) ? 1 : 0;
469 }
470 return ERROR_OK;
471 }
472
473 static int nrf5_protect_check(struct flash_bank *bank)
474 {
475 /* UICR cannot be write protected so just return early */
476 if (bank->base == NRF5_UICR_BASE)
477 return ERROR_OK;
478
479 struct nrf5_bank *nbank = bank->driver_priv;
480 struct nrf5_info *chip = nbank->chip;
481
482 assert(chip);
483
484 if (chip->features & NRF5_FEATURE_BPROT)
485 return nrf5_protect_check_bprot(bank);
486
487 if (chip->features & NRF5_FEATURE_SERIES_51)
488 return nrf5_protect_check_clenr0(bank);
489
490 LOG_WARNING("Flash protection of this nRF device is not supported");
491 return ERROR_FLASH_OPER_UNSUPPORTED;
492 }
493
494 static int nrf5_protect_clenr0(struct flash_bank *bank, int set, unsigned int first,
495 unsigned int last)
496 {
497 int res;
498 uint32_t clenr0, ppfc;
499 struct nrf5_bank *nbank = bank->driver_priv;
500 struct nrf5_info *chip = nbank->chip;
501
502 if (first != 0) {
503 LOG_ERROR("Code region 0 must start at the beginning of the bank");
504 return ERROR_FAIL;
505 }
506
507 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
508 &ppfc);
509 if (res != ERROR_OK) {
510 LOG_ERROR("Couldn't read PPFC register");
511 return res;
512 }
513
514 if ((ppfc & 0xFF) == 0x00) {
515 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
516 return ERROR_FAIL;
517 }
518
519 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
520 &clenr0);
521 if (res != ERROR_OK) {
522 LOG_ERROR("Couldn't read code region 0 size from UICR");
523 return res;
524 }
525
526 if (!set || clenr0 != 0xFFFFFFFF) {
527 LOG_ERROR("You need to perform chip erase before changing the protection settings");
528 return ERROR_FAIL;
529 }
530
531 res = nrf5_nvmc_write_enable(chip);
532 if (res != ERROR_OK)
533 goto error;
534
535 clenr0 = bank->sectors[last].offset + bank->sectors[last].size;
536 res = target_write_u32(chip->target, NRF51_UICR_CLENR0, clenr0);
537
538 int res2 = nrf5_wait_for_nvmc(chip);
539
540 if (res == ERROR_OK)
541 res = res2;
542
543 if (res == ERROR_OK)
544 LOG_INFO("A reset or power cycle is required for the new protection settings to take effect.");
545 else
546 LOG_ERROR("Couldn't write code region 0 size to UICR");
547
548 error:
549 nrf5_nvmc_read_only(chip);
550
551 return res;
552 }
553
554 static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
555 unsigned int last)
556 {
557 int res;
558 struct nrf5_info *chip;
559
560 /* UICR cannot be write protected so just bail out early */
561 if (bank->base == NRF5_UICR_BASE) {
562 LOG_ERROR("UICR page does not support protection");
563 return ERROR_FLASH_OPER_UNSUPPORTED;
564 }
565
566 res = nrf5_get_probed_chip_if_halted(bank, &chip);
567 if (res != ERROR_OK)
568 return res;
569
570 if (chip->features & NRF5_FEATURE_SERIES_51)
571 return nrf5_protect_clenr0(bank, set, first, last);
572
573 LOG_ERROR("Flash protection setting is not supported on this nRF5 device");
574 return ERROR_FLASH_OPER_UNSUPPORTED;
575 }
576
577 static bool nrf5_info_variant_to_str(uint32_t variant, char *bf)
578 {
579 uint8_t b[4];
580
581 h_u32_to_be(b, variant);
582 if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) && isalnum(b[3])) {
583 memcpy(bf, b, 4);
584 bf[4] = 0;
585 return true;
586 }
587
588 strcpy(bf, "xxxx");
589 return false;
590 }
591
592 static const char *nrf5_decode_info_package(uint32_t package)
593 {
594 for (size_t i = 0; i < ARRAY_SIZE(nrf5_packages_table); i++) {
595 if (nrf5_packages_table[i].package == package)
596 return nrf5_packages_table[i].code;
597 }
598 return "xx";
599 }
600
601 static int get_nrf5_chip_type_str(const struct nrf5_info *chip, char *buf, unsigned int buf_size)
602 {
603 int res;
604 if (chip->spec) {
605 res = snprintf(buf, buf_size, "nRF%s-%s(build code: %s)",
606 chip->spec->part, chip->spec->variant, chip->spec->build_code);
607 } else if (chip->ficr_info_valid) {
608 char variant[5];
609 nrf5_info_variant_to_str(chip->ficr_info.variant, variant);
610 res = snprintf(buf, buf_size, "nRF%" PRIx32 "-%s%.2s(build code: %s)",
611 chip->ficr_info.part,
612 nrf5_decode_info_package(chip->ficr_info.package),
613 variant, &variant[2]);
614 } else {
615 res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%04" PRIx16 ")", chip->hwid);
616 }
617
618 /* safety: */
619 if (res <= 0 || (unsigned int)res >= buf_size) {
620 LOG_ERROR("BUG: buffer problem in %s", __func__);
621 return ERROR_FAIL;
622 }
623 return ERROR_OK;
624 }
625
626 static int nrf5_info(struct flash_bank *bank, struct command_invocation *cmd)
627 {
628 struct nrf5_bank *nbank = bank->driver_priv;
629 struct nrf5_info *chip = nbank->chip;
630
631 char chip_type_str[256];
632 if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
633 return ERROR_FAIL;
634
635 command_print_sameline(cmd, "%s %ukB Flash, %ukB RAM",
636 chip_type_str, chip->flash_size_kb, chip->ram_size_kb);
637 return ERROR_OK;
638 }
639
640 static int nrf5_read_ficr_info(struct nrf5_info *chip)
641 {
642 int res;
643 struct target *target = chip->target;
644
645 chip->ficr_info_valid = false;
646
647 res = target_read_u32(target, NRF5_FICR_INFO_PART, &chip->ficr_info.part);
648 if (res != ERROR_OK) {
649 LOG_DEBUG("Couldn't read FICR INFO.PART register");
650 return res;
651 }
652
653 uint32_t series = chip->ficr_info.part & 0xfffff000;
654 switch (series) {
655 case 0x51000:
656 chip->features = NRF5_FEATURE_SERIES_51;
657 break;
658
659 case 0x52000:
660 chip->features = NRF5_FEATURE_SERIES_52;
661
662 switch (chip->ficr_info.part) {
663 case 0x52810:
664 case 0x52832:
665 chip->features |= NRF5_FEATURE_BPROT;
666 break;
667
668 case 0x52840:
669 chip->features |= NRF5_FEATURE_ACL_PROT;
670 break;
671 }
672 break;
673
674 default:
675 LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
676 PRIx32, chip->ficr_info.part);
677 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
678 }
679
680 /* Now we know the device has FICR INFO filled by something relevant:
681 * Although it is not documented, the tested nRF51 rev 3 devices
682 * have FICR INFO.PART, RAM and FLASH of the same format as nRF52.
683 * VARIANT and PACKAGE coding is unknown for a nRF51 device.
684 * nRF52 devices have FICR INFO documented and always filled. */
685
686 res = target_read_u32(target, NRF5_FICR_INFO_VARIANT, &chip->ficr_info.variant);
687 if (res != ERROR_OK)
688 return res;
689
690 res = target_read_u32(target, NRF5_FICR_INFO_PACKAGE, &chip->ficr_info.package);
691 if (res != ERROR_OK)
692 return res;
693
694 res = target_read_u32(target, NRF5_FICR_INFO_RAM, &chip->ficr_info.ram);
695 if (res != ERROR_OK)
696 return res;
697
698 res = target_read_u32(target, NRF5_FICR_INFO_FLASH, &chip->ficr_info.flash);
699 if (res != ERROR_OK)
700 return res;
701
702 chip->ficr_info_valid = true;
703 return ERROR_OK;
704 }
705
706 static int nrf5_get_ram_size(struct target *target, uint32_t *ram_size)
707 {
708 int res;
709
710 *ram_size = 0;
711
712 uint32_t numramblock;
713 res = target_read_u32(target, NRF51_FICR_NUMRAMBLOCK, &numramblock);
714 if (res != ERROR_OK) {
715 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
716 return res;
717 }
718
719 if (numramblock < 1 || numramblock > 4) {
720 LOG_DEBUG("FICR NUMRAMBLOCK strange value %" PRIx32, numramblock);
721 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
722 }
723
724 for (unsigned int i = 0; i < numramblock; i++) {
725 uint32_t sizeramblock;
726 res = target_read_u32(target, NRF51_FICR_SIZERAMBLOCK0 + sizeof(uint32_t)*i, &sizeramblock);
727 if (res != ERROR_OK) {
728 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
729 return res;
730 }
731 if (sizeramblock < 1024 || sizeramblock > 65536)
732 LOG_DEBUG("FICR SIZERAMBLOCK strange value %" PRIx32, sizeramblock);
733 else
734 *ram_size += sizeramblock;
735 }
736 return res;
737 }
738
739 static int nrf5_probe(struct flash_bank *bank)
740 {
741 int res;
742 struct nrf5_bank *nbank = bank->driver_priv;
743 struct nrf5_info *chip = nbank->chip;
744 struct target *target = chip->target;
745
746 uint32_t configid;
747 res = target_read_u32(target, NRF5_FICR_CONFIGID, &configid);
748 if (res != ERROR_OK) {
749 LOG_ERROR("Couldn't read CONFIGID register");
750 return res;
751 }
752
753 /* HWID is stored in the lower two bytes of the CONFIGID register */
754 chip->hwid = configid & 0xFFFF;
755
756 /* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
757 chip->features = NRF5_FEATURE_SERIES_51;
758
759 /* Don't bail out on error for the case that some old engineering
760 * sample has FICR INFO registers unreadable. We can proceed anyway. */
761 (void)nrf5_read_ficr_info(chip);
762
763 chip->spec = NULL;
764 for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
765 if (chip->hwid == nrf5_known_devices_table[i].hwid) {
766 chip->spec = &nrf5_known_devices_table[i];
767 chip->features = chip->spec->features;
768 break;
769 }
770 }
771
772 if (chip->spec && chip->ficr_info_valid) {
773 /* check if HWID table gives the same part as FICR INFO */
774 if (chip->ficr_info.part != strtoul(chip->spec->part, NULL, 16))
775 LOG_WARNING("HWID 0x%04" PRIx32 " mismatch: FICR INFO.PART %"
776 PRIx32, chip->hwid, chip->ficr_info.part);
777 }
778
779 if (chip->ficr_info_valid) {
780 chip->ram_size_kb = chip->ficr_info.ram;
781 } else {
782 uint32_t ram_size;
783 nrf5_get_ram_size(target, &ram_size);
784 chip->ram_size_kb = ram_size / 1024;
785 }
786
787 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
788 uint32_t flash_page_size;
789 res = target_read_u32(chip->target, NRF5_FICR_CODEPAGESIZE,
790 &flash_page_size);
791 if (res != ERROR_OK) {
792 LOG_ERROR("Couldn't read code page size");
793 return res;
794 }
795
796 /* Note the register name is misleading,
797 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
798 uint32_t num_sectors;
799 res = target_read_u32(chip->target, NRF5_FICR_CODESIZE, &num_sectors);
800 if (res != ERROR_OK) {
801 LOG_ERROR("Couldn't read code memory size");
802 return res;
803 }
804
805 chip->flash_size_kb = num_sectors * flash_page_size / 1024;
806
807 if (!chip->bank[0].probed && !chip->bank[1].probed) {
808 char chip_type_str[256];
809 if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
810 return ERROR_FAIL;
811 const bool device_is_unknown = (!chip->spec && !chip->ficr_info_valid);
812 LOG_INFO("%s%s %ukB Flash, %ukB RAM",
813 device_is_unknown ? "Unknown device: " : "",
814 chip_type_str,
815 chip->flash_size_kb,
816 chip->ram_size_kb);
817 }
818
819 free(bank->sectors);
820
821 if (bank->base == NRF5_FLASH_BASE) {
822 /* Sanity check */
823 if (chip->spec && chip->flash_size_kb != chip->spec->flash_size_kb)
824 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
825 if (chip->ficr_info_valid && chip->flash_size_kb != chip->ficr_info.flash)
826 LOG_WARNING("Chip's reported Flash capacity does not match FICR INFO.FLASH");
827
828 bank->num_sectors = num_sectors;
829 bank->size = num_sectors * flash_page_size;
830
831 bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
832 if (!bank->sectors)
833 return ERROR_FAIL;
834
835 chip->bank[0].probed = true;
836
837 } else {
838 bank->num_sectors = 1;
839 bank->size = flash_page_size;
840
841 bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
842 if (!bank->sectors)
843 return ERROR_FAIL;
844
845 bank->sectors[0].is_protected = 0;
846
847 chip->bank[1].probed = true;
848 }
849
850 return ERROR_OK;
851 }
852
853 static int nrf5_auto_probe(struct flash_bank *bank)
854 {
855 if (nrf5_bank_is_probed(bank))
856 return ERROR_OK;
857
858 return nrf5_probe(bank);
859 }
860
861 static int nrf5_erase_all(struct nrf5_info *chip)
862 {
863 LOG_DEBUG("Erasing all non-volatile memory");
864 return nrf5_nvmc_generic_erase(chip,
865 NRF5_NVMC_ERASEALL,
866 0x00000001);
867 }
868
869 static int nrf5_erase_page(struct flash_bank *bank,
870 struct nrf5_info *chip,
871 struct flash_sector *sector)
872 {
873 int res;
874
875 LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
876
877 if (bank->base == NRF5_UICR_BASE) {
878 if (chip->features & NRF5_FEATURE_SERIES_51) {
879 uint32_t ppfc;
880 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
881 &ppfc);
882 if (res != ERROR_OK) {
883 LOG_ERROR("Couldn't read PPFC register");
884 return res;
885 }
886
887 if ((ppfc & 0xFF) == 0xFF) {
888 /* We can't erase the UICR. Double-check to
889 see if it's already erased before complaining. */
890 default_flash_blank_check(bank);
891 if (sector->is_erased == 1)
892 return ERROR_OK;
893
894 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
895 return ERROR_FAIL;
896 }
897 }
898
899 res = nrf5_nvmc_generic_erase(chip,
900 NRF5_NVMC_ERASEUICR,
901 0x00000001);
902
903
904 } else {
905 res = nrf5_nvmc_generic_erase(chip,
906 NRF5_NVMC_ERASEPAGE,
907 sector->offset);
908 }
909
910 return res;
911 }
912
913 /* Start a low level flash write for the specified region */
914 static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const uint8_t *buffer, uint32_t bytes)
915 {
916 struct target *target = chip->target;
917 uint32_t buffer_size = 8192;
918 struct working_area *write_algorithm;
919 struct working_area *source;
920 struct reg_param reg_params[6];
921 struct armv7m_algorithm armv7m_info;
922 int retval = ERROR_OK;
923
924 static const uint8_t nrf5_flash_write_code[] = {
925 #include "../../../contrib/loaders/flash/nrf5/nrf5.inc"
926 };
927
928 LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32" bytes=0x%"PRIx32, address, bytes);
929 assert(bytes % 4 == 0);
930
931 /* allocate working area with flash programming code */
932 if (target_alloc_working_area(target, sizeof(nrf5_flash_write_code),
933 &write_algorithm) != ERROR_OK) {
934 LOG_WARNING("no working area available, falling back to slow memory writes");
935
936 for (; bytes > 0; bytes -= 4) {
937 retval = target_write_memory(target, address, 4, 1, buffer);
938 if (retval != ERROR_OK)
939 return retval;
940
941 retval = nrf5_wait_for_nvmc(chip);
942 if (retval != ERROR_OK)
943 return retval;
944
945 address += 4;
946 buffer += 4;
947 }
948
949 return ERROR_OK;
950 }
951
952 retval = target_write_buffer(target, write_algorithm->address,
953 sizeof(nrf5_flash_write_code),
954 nrf5_flash_write_code);
955 if (retval != ERROR_OK)
956 return retval;
957
958 /* memory buffer */
959 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
960 buffer_size /= 2;
961 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
962 if (buffer_size <= 256) {
963 /* free working area, write algorithm already allocated */
964 target_free_working_area(target, write_algorithm);
965
966 LOG_WARNING("No large enough working area available, can't do block memory writes");
967 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
968 }
969 }
970
971 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
972 armv7m_info.core_mode = ARM_MODE_THREAD;
973
974 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
975 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer start */
976 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer end */
977 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
978 init_reg_param(&reg_params[4], "r6", 32, PARAM_OUT); /* watchdog refresh value */
979 init_reg_param(&reg_params[5], "r7", 32, PARAM_OUT); /* watchdog refresh register address */
980
981 buf_set_u32(reg_params[0].value, 0, 32, bytes);
982 buf_set_u32(reg_params[1].value, 0, 32, source->address);
983 buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
984 buf_set_u32(reg_params[3].value, 0, 32, address);
985 buf_set_u32(reg_params[4].value, 0, 32, WATCHDOG_REFRESH_VALUE);
986 buf_set_u32(reg_params[5].value, 0, 32, WATCHDOG_REFRESH_REGISTER);
987
988 retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
989 0, NULL,
990 ARRAY_SIZE(reg_params), reg_params,
991 source->address, source->size,
992 write_algorithm->address, write_algorithm->address + sizeof(nrf5_flash_write_code) - 2,
993 &armv7m_info);
994
995 target_free_working_area(target, source);
996 target_free_working_area(target, write_algorithm);
997
998 destroy_reg_param(&reg_params[0]);
999 destroy_reg_param(&reg_params[1]);
1000 destroy_reg_param(&reg_params[2]);
1001 destroy_reg_param(&reg_params[3]);
1002 destroy_reg_param(&reg_params[4]);
1003 destroy_reg_param(&reg_params[5]);
1004
1005 return retval;
1006 }
1007
1008 static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer,
1009 uint32_t offset, uint32_t count)
1010 {
1011 struct nrf5_info *chip;
1012
1013 int res = nrf5_get_probed_chip_if_halted(bank, &chip);
1014 if (res != ERROR_OK)
1015 return res;
1016
1017 assert(offset % 4 == 0);
1018 assert(count % 4 == 0);
1019
1020 /* UICR CLENR0 based protection used on nRF51 is somewhat clumsy:
1021 * RM reads: Code running from code region 1 will not be able to write
1022 * to code region 0.
1023 * Unfortunately the flash loader running from RAM can write to both
1024 * code regions without any hint the protection is violated.
1025 *
1026 * Update protection state and check if any flash sector to be written
1027 * is protected. */
1028 if (chip->features & NRF5_FEATURE_SERIES_51) {
1029
1030 res = nrf5_protect_check_clenr0(bank);
1031 if (res != ERROR_OK)
1032 return res;
1033
1034 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
1035 struct flash_sector *bs = &bank->sectors[sector];
1036
1037 /* Start offset in or before this sector? */
1038 /* End offset in or behind this sector? */
1039 if ((offset < (bs->offset + bs->size))
1040 && ((offset + count - 1) >= bs->offset)
1041 && bs->is_protected == 1) {
1042 LOG_ERROR("Write refused, sector %d is protected", sector);
1043 return ERROR_FLASH_PROTECTED;
1044 }
1045 }
1046 }
1047
1048 res = nrf5_nvmc_write_enable(chip);
1049 if (res != ERROR_OK)
1050 goto error;
1051
1052 res = nrf5_ll_flash_write(chip, bank->base + offset, buffer, count);
1053 if (res != ERROR_OK)
1054 goto error;
1055
1056 return nrf5_nvmc_read_only(chip);
1057
1058 error:
1059 nrf5_nvmc_read_only(chip);
1060 LOG_ERROR("Failed to write to nrf5 flash");
1061 return res;
1062 }
1063
1064 static int nrf5_erase(struct flash_bank *bank, unsigned int first,
1065 unsigned int last)
1066 {
1067 int res;
1068 struct nrf5_info *chip;
1069
1070 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1071 if (res != ERROR_OK)
1072 return res;
1073
1074 /* UICR CLENR0 based protection used on nRF51 prevents erase
1075 * absolutely silently. NVMC has no flag to indicate the protection
1076 * was violated.
1077 *
1078 * Update protection state and check if any flash sector to be erased
1079 * is protected. */
1080 if (chip->features & NRF5_FEATURE_SERIES_51) {
1081
1082 res = nrf5_protect_check_clenr0(bank);
1083 if (res != ERROR_OK)
1084 return res;
1085 }
1086
1087 /* For each sector to be erased */
1088 for (unsigned int s = first; s <= last && res == ERROR_OK; s++) {
1089
1090 if (chip->features & NRF5_FEATURE_SERIES_51
1091 && bank->sectors[s].is_protected == 1) {
1092 LOG_ERROR("Flash sector %d is protected", s);
1093 return ERROR_FLASH_PROTECTED;
1094 }
1095
1096 res = nrf5_erase_page(bank, chip, &bank->sectors[s]);
1097 if (res != ERROR_OK) {
1098 LOG_ERROR("Error erasing sector %d", s);
1099 return res;
1100 }
1101 }
1102
1103 return ERROR_OK;
1104 }
1105
1106 static void nrf5_free_driver_priv(struct flash_bank *bank)
1107 {
1108 struct nrf5_bank *nbank = bank->driver_priv;
1109 struct nrf5_info *chip = nbank->chip;
1110 if (!chip)
1111 return;
1112
1113 chip->refcount--;
1114 if (chip->refcount == 0) {
1115 free(chip);
1116 bank->driver_priv = NULL;
1117 }
1118 }
1119
1120 static struct nrf5_info *nrf5_get_chip(struct target *target)
1121 {
1122 struct flash_bank *bank_iter;
1123
1124 /* iterate over nrf5 banks of same target */
1125 for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
1126 if (bank_iter->driver != &nrf5_flash && bank_iter->driver != &nrf51_flash)
1127 continue;
1128
1129 if (bank_iter->target != target)
1130 continue;
1131
1132 struct nrf5_bank *nbank = bank_iter->driver_priv;
1133 if (!nbank)
1134 continue;
1135
1136 if (nbank->chip)
1137 return nbank->chip;
1138 }
1139 return NULL;
1140 }
1141
1142 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
1143 {
1144 struct nrf5_info *chip;
1145 struct nrf5_bank *nbank = NULL;
1146
1147 if (bank->driver == &nrf51_flash)
1148 LOG_WARNING("Flash driver 'nrf51' is deprecated! Use 'nrf5' instead.");
1149
1150 switch (bank->base) {
1151 case NRF5_FLASH_BASE:
1152 case NRF5_UICR_BASE:
1153 break;
1154 default:
1155 LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
1156 return ERROR_FAIL;
1157 }
1158
1159 chip = nrf5_get_chip(bank->target);
1160 if (!chip) {
1161 /* Create a new chip */
1162 chip = calloc(1, sizeof(*chip));
1163 if (!chip)
1164 return ERROR_FAIL;
1165
1166 chip->target = bank->target;
1167 }
1168
1169 switch (bank->base) {
1170 case NRF5_FLASH_BASE:
1171 nbank = &chip->bank[0];
1172 break;
1173 case NRF5_UICR_BASE:
1174 nbank = &chip->bank[1];
1175 break;
1176 }
1177 assert(nbank);
1178
1179 chip->refcount++;
1180 nbank->chip = chip;
1181 nbank->probed = false;
1182 bank->driver_priv = nbank;
1183 bank->write_start_alignment = bank->write_end_alignment = 4;
1184
1185 return ERROR_OK;
1186 }
1187
1188 COMMAND_HANDLER(nrf5_handle_mass_erase_command)
1189 {
1190 int res;
1191 struct flash_bank *bank = NULL;
1192 struct target *target = get_current_target(CMD_CTX);
1193
1194 res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1195 if (res != ERROR_OK)
1196 return res;
1197
1198 assert(bank);
1199
1200 struct nrf5_info *chip;
1201
1202 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1203 if (res != ERROR_OK)
1204 return res;
1205
1206 if (chip->features & NRF5_FEATURE_SERIES_51) {
1207 uint32_t ppfc;
1208 res = target_read_u32(target, NRF51_FICR_PPFC,
1209 &ppfc);
1210 if (res != ERROR_OK) {
1211 LOG_ERROR("Couldn't read PPFC register");
1212 return res;
1213 }
1214
1215 if ((ppfc & 0xFF) == 0x00) {
1216 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1217 "mass erase command won't work.");
1218 return ERROR_FAIL;
1219 }
1220 }
1221
1222 res = nrf5_erase_all(chip);
1223 if (res == ERROR_OK) {
1224 LOG_INFO("Mass erase completed.");
1225 if (chip->features & NRF5_FEATURE_SERIES_51)
1226 LOG_INFO("A reset or power cycle is required if the flash was protected before.");
1227
1228 } else {
1229 LOG_ERROR("Failed to erase the chip");
1230 }
1231
1232 return res;
1233 }
1234
1235 COMMAND_HANDLER(nrf5_handle_info_command)
1236 {
1237 int res;
1238 struct flash_bank *bank = NULL;
1239 struct target *target = get_current_target(CMD_CTX);
1240
1241 res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1242 if (res != ERROR_OK)
1243 return res;
1244
1245 assert(bank);
1246
1247 struct nrf5_info *chip;
1248
1249 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1250 if (res != ERROR_OK)
1251 return res;
1252
1253 static struct {
1254 const uint32_t address;
1255 uint32_t value;
1256 } ficr[] = {
1257 { .address = NRF5_FICR_CODEPAGESIZE },
1258 { .address = NRF5_FICR_CODESIZE },
1259 { .address = NRF51_FICR_CLENR0 },
1260 { .address = NRF51_FICR_PPFC },
1261 { .address = NRF51_FICR_NUMRAMBLOCK },
1262 { .address = NRF51_FICR_SIZERAMBLOCK0 },
1263 { .address = NRF51_FICR_SIZERAMBLOCK1 },
1264 { .address = NRF51_FICR_SIZERAMBLOCK2 },
1265 { .address = NRF51_FICR_SIZERAMBLOCK3 },
1266 { .address = NRF5_FICR_CONFIGID },
1267 { .address = NRF5_FICR_DEVICEID0 },
1268 { .address = NRF5_FICR_DEVICEID1 },
1269 { .address = NRF5_FICR_ER0 },
1270 { .address = NRF5_FICR_ER1 },
1271 { .address = NRF5_FICR_ER2 },
1272 { .address = NRF5_FICR_ER3 },
1273 { .address = NRF5_FICR_IR0 },
1274 { .address = NRF5_FICR_IR1 },
1275 { .address = NRF5_FICR_IR2 },
1276 { .address = NRF5_FICR_IR3 },
1277 { .address = NRF5_FICR_DEVICEADDRTYPE },
1278 { .address = NRF5_FICR_DEVICEADDR0 },
1279 { .address = NRF5_FICR_DEVICEADDR1 },
1280 { .address = NRF51_FICR_OVERRIDEN },
1281 { .address = NRF51_FICR_NRF_1MBIT0 },
1282 { .address = NRF51_FICR_NRF_1MBIT1 },
1283 { .address = NRF51_FICR_NRF_1MBIT2 },
1284 { .address = NRF51_FICR_NRF_1MBIT3 },
1285 { .address = NRF51_FICR_NRF_1MBIT4 },
1286 { .address = NRF51_FICR_BLE_1MBIT0 },
1287 { .address = NRF51_FICR_BLE_1MBIT1 },
1288 { .address = NRF51_FICR_BLE_1MBIT2 },
1289 { .address = NRF51_FICR_BLE_1MBIT3 },
1290 { .address = NRF51_FICR_BLE_1MBIT4 },
1291 }, uicr[] = {
1292 { .address = NRF51_UICR_CLENR0, },
1293 { .address = NRF51_UICR_RBPCONF },
1294 { .address = NRF51_UICR_XTALFREQ },
1295 { .address = NRF51_UICR_FWID },
1296 };
1297
1298 for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
1299 res = target_read_u32(chip->target, ficr[i].address,
1300 &ficr[i].value);
1301 if (res != ERROR_OK) {
1302 LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
1303 return res;
1304 }
1305 }
1306
1307 for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
1308 res = target_read_u32(chip->target, uicr[i].address,
1309 &uicr[i].value);
1310 if (res != ERROR_OK) {
1311 LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
1312 return res;
1313 }
1314 }
1315
1316 command_print(CMD,
1317 "\n[factory information control block]\n\n"
1318 "code page size: %"PRIu32"B\n"
1319 "code memory size: %"PRIu32"kB\n"
1320 "code region 0 size: %"PRIu32"kB\n"
1321 "pre-programmed code: %s\n"
1322 "number of ram blocks: %"PRIu32"\n"
1323 "ram block 0 size: %"PRIu32"B\n"
1324 "ram block 1 size: %"PRIu32"B\n"
1325 "ram block 2 size: %"PRIu32"B\n"
1326 "ram block 3 size: %"PRIu32 "B\n"
1327 "config id: %" PRIx32 "\n"
1328 "device id: 0x%"PRIx32"%08"PRIx32"\n"
1329 "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1330 "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1331 "device address type: 0x%"PRIx32"\n"
1332 "device address: 0x%"PRIx32"%08"PRIx32"\n"
1333 "override enable: %"PRIx32"\n"
1334 "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1335 "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1336 "\n[user information control block]\n\n"
1337 "code region 0 size: %"PRIu32"kB\n"
1338 "read back protection configuration: %"PRIx32"\n"
1339 "reset value for XTALFREQ: %"PRIx32"\n"
1340 "firmware id: 0x%04"PRIx32,
1341 ficr[0].value,
1342 (ficr[1].value * ficr[0].value) / 1024,
1343 (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1344 ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
1345 ficr[4].value,
1346 ficr[5].value,
1347 (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1348 (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1349 (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1350 ficr[9].value,
1351 ficr[10].value, ficr[11].value,
1352 ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1353 ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1354 ficr[20].value,
1355 ficr[21].value, ficr[22].value,
1356 ficr[23].value,
1357 ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1358 ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1359 (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1360 uicr[1].value & 0xFFFF,
1361 uicr[2].value & 0xFF,
1362 uicr[3].value & 0xFFFF);
1363
1364 return ERROR_OK;
1365 }
1366
1367 static const struct command_registration nrf5_exec_command_handlers[] = {
1368 {
1369 .name = "mass_erase",
1370 .handler = nrf5_handle_mass_erase_command,
1371 .mode = COMMAND_EXEC,
1372 .help = "Erase all flash contents of the chip.",
1373 .usage = "",
1374 },
1375 {
1376 .name = "info",
1377 .handler = nrf5_handle_info_command,
1378 .mode = COMMAND_EXEC,
1379 .help = "Show FICR and UICR info.",
1380 .usage = "",
1381 },
1382 COMMAND_REGISTRATION_DONE
1383 };
1384
1385 static const struct command_registration nrf5_command_handlers[] = {
1386 {
1387 .name = "nrf5",
1388 .mode = COMMAND_ANY,
1389 .help = "nrf5 flash command group",
1390 .usage = "",
1391 .chain = nrf5_exec_command_handlers,
1392 },
1393 {
1394 .name = "nrf51",
1395 .mode = COMMAND_ANY,
1396 .help = "nrf51 flash command group",
1397 .usage = "",
1398 .chain = nrf5_exec_command_handlers,
1399 },
1400 COMMAND_REGISTRATION_DONE
1401 };
1402
1403 const struct flash_driver nrf5_flash = {
1404 .name = "nrf5",
1405 .commands = nrf5_command_handlers,
1406 .flash_bank_command = nrf5_flash_bank_command,
1407 .info = nrf5_info,
1408 .erase = nrf5_erase,
1409 .protect = nrf5_protect,
1410 .write = nrf5_write,
1411 .read = default_flash_read,
1412 .probe = nrf5_probe,
1413 .auto_probe = nrf5_auto_probe,
1414 .erase_check = default_flash_blank_check,
1415 .protect_check = nrf5_protect_check,
1416 .free_driver_priv = nrf5_free_driver_priv,
1417 };
1418
1419 /* We need to retain the flash-driver name as well as the commands
1420 * for backwards compatibility */
1421 const struct flash_driver nrf51_flash = {
1422 .name = "nrf51",
1423 .commands = nrf5_command_handlers,
1424 .flash_bank_command = nrf5_flash_bank_command,
1425 .info = nrf5_info,
1426 .erase = nrf5_erase,
1427 .protect = nrf5_protect,
1428 .write = nrf5_write,
1429 .read = default_flash_read,
1430 .probe = nrf5_probe,
1431 .auto_probe = nrf5_auto_probe,
1432 .erase_check = default_flash_blank_check,
1433 .protect_check = nrf5_protect_check,
1434 .free_driver_priv = nrf5_free_driver_priv,
1435 };
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