2 # Freescale i.MX6UltraLite series: 6UL 6ULL 6ULZ
5 if { [info exists CHIPNAME] } {
6 set _CHIPNAME $CHIPNAME
11 # CoreSight Debug Access Port
12 if { [info exists DAP_TAPID] } {
13 set _DAP_TAPID $DAP_TAPID
15 set _DAP_TAPID 0x4ba00477
18 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
19 -expected-id $_DAP_TAPID
22 jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
24 # System JTAG Controller
25 set _SJC_TAPID_6UL 0x0891d01d
26 set _SJC_TAPID_6ULL 0x0891e01d
27 set _SJC_TAPID_6ULZ 0x1891e01d
29 # Allow external override of the first SJC TAPID
30 if { [info exists SJC_TAPID] } {
31 set _SJC_TAPID $SJC_TAPID
33 set _SJC_TAPID $_SJC_TAPID_6UL
36 jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
38 -expected-id $_SJC_TAPID \
39 -expected-id $_SJC_TAPID_6ULL \
40 -expected-id $_SJC_TAPID_6ULZ \
43 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
46 target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
48 # Cortex-A7 single core
49 set _TARGETNAME $_CHIPNAME.cpu
50 target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x82130000