1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # Freescale i.MX6UltraLite series: 6UL 6ULL 6ULZ
7 if { [info exists CHIPNAME] } {
8 set _CHIPNAME $CHIPNAME
13 # CoreSight Debug Access Port
14 if { [info exists DAP_TAPID] } {
15 set _DAP_TAPID $DAP_TAPID
17 set _DAP_TAPID 0x4ba00477
20 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
21 -expected-id $_DAP_TAPID
24 jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
26 # System JTAG Controller
27 set _SJC_TAPID_6UL 0x0891d01d
28 set _SJC_TAPID_6ULL 0x0891e01d
29 set _SJC_TAPID_6ULZ 0x1891e01d
31 # Allow external override of the first SJC TAPID
32 if { [info exists SJC_TAPID] } {
33 set _SJC_TAPID $SJC_TAPID
35 set _SJC_TAPID $_SJC_TAPID_6UL
38 jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
40 -expected-id $_SJC_TAPID \
41 -expected-id $_SJC_TAPID_6ULL \
42 -expected-id $_SJC_TAPID_6ULZ \
45 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
48 target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
50 # Cortex-A7 single core
51 set _TARGETNAME $_CHIPNAME.cpu
52 target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x82130000