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flash/nor/stm32l4x: Minor code cleanups
[openocd.git] / src / flash / nor / stm32l4x.c
blobabbb75b466b6a52968fa3a6988fda8f1706a78e6
1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
4 * *
5 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
6 * tarek.bouchkati@gmail.com *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
21
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "imp.h"
27 #include <helper/binarybuffer.h>
28 #include <target/algorithm.h>
29 #include <target/armv7m.h>
30 #include "bits.h"
31
32 /* STM32L4xxx series for reference.
33 *
34 * RM0351 (STM32L4x5/STM32L4x6)
35 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
36 *
37 * RM0394 (STM32L43x/44x/45x/46x)
38 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
39 *
40 * RM0432 (STM32L4R/4Sxx)
41 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
42 *
43 * STM32L476RG Datasheet (for erase timing)
44 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
45 *
46 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
47 * an option byte is available to map all sectors to the first bank.
48 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
49 * handlers do!
50 *
51 * RM0394 devices have a single bank only.
52 *
53 * RM0432 devices have single and dual bank operating modes.
54 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
55 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
56 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
57 *
58 * Bank mode is controlled by two different bits in option bytes register.
59 * - for STM32L4R/Sxx
60 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
61 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
62 * - for STM32L4P5/Q5x
63 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
64 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
65 *
66 */
67
68 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
69
70 #define FLASH_ERASE_TIMEOUT 250
71
72 /* Flash registers offsets */
73 #define STM32_FLASH_ACR 0x00
74 #define STM32_FLASH_KEYR 0x08
75 #define STM32_FLASH_OPTKEYR 0x0c
76 #define STM32_FLASH_SR 0x10
77 #define STM32_FLASH_CR 0x14
78 #define STM32_FLASH_OPTR 0x20
79 #define STM32_FLASH_WRP1AR 0x2c
80 #define STM32_FLASH_WRP1BR 0x30
81 #define STM32_FLASH_WRP2AR 0x4c
82 #define STM32_FLASH_WRP2BR 0x50
83
84 /* FLASH_CR register bits */
85 #define FLASH_PG (1 << 0)
86 #define FLASH_PER (1 << 1)
87 #define FLASH_MER1 (1 << 2)
88 #define FLASH_PAGE_SHIFT 3
89 #define FLASH_CR_BKER (1 << 11)
90 #define FLASH_MER2 (1 << 15)
91 #define FLASH_STRT (1 << 16)
92 #define FLASH_OPTSTRT (1 << 17)
93 #define FLASH_EOPIE (1 << 24)
94 #define FLASH_ERRIE (1 << 25)
95 #define FLASH_OBLLAUNCH (1 << 27)
96 #define FLASH_OPTLOCK (1 << 30)
97 #define FLASH_LOCK (1 << 31)
98
99 /* FLASH_SR register bits */
100 #define FLASH_BSY (1 << 16)
101 /* Fast programming not used => related errors not used*/
102 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
103 #define FLASH_SIZERR (1 << 6) /* Size error */
104 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
105 #define FLASH_WRPERR (1 << 4) /* Write protection error */
106 #define FLASH_PROGERR (1 << 3) /* Programming error */
107 #define FLASH_OPERR (1 << 1) /* Operation error */
108 #define FLASH_EOP (1 << 0) /* End of operation */
109 #define FLASH_ERROR (FLASH_PGSERR | FLASH_SIZERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_PROGERR | FLASH_OPERR)
110
111 /* register unlock keys */
112 #define KEY1 0x45670123
113 #define KEY2 0xCDEF89AB
114
115 /* option register unlock key */
116 #define OPTKEY1 0x08192A3B
117 #define OPTKEY2 0x4C5D6E7F
118
119 #define RDP_LEVEL_0 0xAA
120 #define RDP_LEVEL_1 0xBB
121 #define RDP_LEVEL_2 0xCC
122
123
124 /* other registers */
125 #define DBGMCU_IDCODE 0xE0042000
126
127
128 struct stm32l4_rev {
129 const uint16_t rev;
130 const char *str;
131 };
132
133 struct stm32l4_part_info {
134 uint16_t id;
135 const char *device_str;
136 const struct stm32l4_rev *revs;
137 const size_t num_revs;
138 const uint16_t max_flash_size_kb;
139 const bool has_dual_bank;
140 const uint32_t flash_regs_base;
141 const uint32_t fsize_addr;
142 };
143
144 struct stm32l4_flash_bank {
145 bool probed;
146 uint32_t idcode;
147 int bank1_sectors;
148 bool dual_bank_mode;
149 int hole_sectors;
150 const struct stm32l4_part_info *part_info;
151 };
152
153 static const struct stm32l4_rev stm32_415_revs[] = {
154 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
155 };
156
157 static const struct stm32l4_rev stm32_435_revs[] = {
158 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
159 };
160
161 static const struct stm32l4_rev stm32_461_revs[] = {
162 { 0x1000, "A" }, { 0x2000, "B" },
163 };
164
165 static const struct stm32l4_rev stm32_462_revs[] = {
166 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
167 };
168
169 static const struct stm32l4_rev stm32_464_revs[] = {
170 { 0x1000, "A" },
171 };
172
173 static const struct stm32l4_rev stm32_470_revs[] = {
174 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
175 };
176
177 static const struct stm32l4_rev stm32_471_revs[] = {
178 { 0x1000, "1" },
179 };
180
181 static const struct stm32l4_rev stm32_495_revs[] = {
182 { 0x2001, "2.1" },
183 };
184
185 static const struct stm32l4_part_info stm32l4_parts[] = {
186 {
187 .id = 0x415,
188 .revs = stm32_415_revs,
189 .num_revs = ARRAY_SIZE(stm32_415_revs),
190 .device_str = "STM32L47/L48xx",
191 .max_flash_size_kb = 1024,
192 .has_dual_bank = true,
193 .flash_regs_base = 0x40022000,
194 .fsize_addr = 0x1FFF75E0,
195 },
196 {
197 .id = 0x435,
198 .revs = stm32_435_revs,
199 .num_revs = ARRAY_SIZE(stm32_435_revs),
200 .device_str = "STM32L43/L44xx",
201 .max_flash_size_kb = 256,
202 .has_dual_bank = false,
203 .flash_regs_base = 0x40022000,
204 .fsize_addr = 0x1FFF75E0,
205 },
206 {
207 .id = 0x461,
208 .revs = stm32_461_revs,
209 .num_revs = ARRAY_SIZE(stm32_461_revs),
210 .device_str = "STM32L49/L4Axx",
211 .max_flash_size_kb = 1024,
212 .has_dual_bank = true,
213 .flash_regs_base = 0x40022000,
214 .fsize_addr = 0x1FFF75E0,
215 },
216 {
217 .id = 0x462,
218 .revs = stm32_462_revs,
219 .num_revs = ARRAY_SIZE(stm32_462_revs),
220 .device_str = "STM32L45/L46xx",
221 .max_flash_size_kb = 512,
222 .has_dual_bank = false,
223 .flash_regs_base = 0x40022000,
224 .fsize_addr = 0x1FFF75E0,
225 },
226 {
227 .id = 0x464,
228 .revs = stm32_464_revs,
229 .num_revs = ARRAY_SIZE(stm32_464_revs),
230 .device_str = "STM32L41/L42xx",
231 .max_flash_size_kb = 128,
232 .has_dual_bank = false,
233 .flash_regs_base = 0x40022000,
234 .fsize_addr = 0x1FFF75E0,
235 },
236 {
237 .id = 0x470,
238 .revs = stm32_470_revs,
239 .num_revs = ARRAY_SIZE(stm32_470_revs),
240 .device_str = "STM32L4R/L4Sxx",
241 .max_flash_size_kb = 2048,
242 .has_dual_bank = true,
243 .flash_regs_base = 0x40022000,
244 .fsize_addr = 0x1FFF75E0,
245 },
246 {
247 .id = 0x471,
248 .revs = stm32_471_revs,
249 .num_revs = ARRAY_SIZE(stm32_471_revs),
250 .device_str = "STM32L4P5/L4Q5x",
251 .max_flash_size_kb = 1024,
252 .has_dual_bank = true,
253 .flash_regs_base = 0x40022000,
254 .fsize_addr = 0x1FFF75E0,
255 },
256 {
257 .id = 0x495,
258 .revs = stm32_495_revs,
259 .num_revs = ARRAY_SIZE(stm32_495_revs),
260 .device_str = "STM32WB5x",
261 .max_flash_size_kb = 1024,
262 .has_dual_bank = false,
263 .flash_regs_base = 0x58004000,
264 .fsize_addr = 0x1FFF75E0,
265 },
266 };
267
268 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
269 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
270 {
271 struct stm32l4_flash_bank *stm32l4_info;
272
273 if (CMD_ARGC < 6)
274 return ERROR_COMMAND_SYNTAX_ERROR;
275
276 stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
277 if (!stm32l4_info)
278 return ERROR_FAIL; /* Checkme: What better error to use?*/
279 bank->driver_priv = stm32l4_info;
280
281 /* The flash write must be aligned to a double word (8-bytes) boundary.
282 * Ask the flash infrastructure to ensure required alignment */
283 bank->write_start_alignment = bank->write_end_alignment = 8;
284
285 stm32l4_info->probed = false;
286
287 return ERROR_OK;
288 }
289
290 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
291 {
292 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
293 return stm32l4_info->part_info->flash_regs_base + reg_offset;
294 }
295
296 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
297 {
298 return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
299 }
300
301 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
302 {
303 return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
304 }
305
306 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
307 {
308 uint32_t status;
309 int retval = ERROR_OK;
310
311 /* wait for busy to clear */
312 for (;;) {
313 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_SR, &status);
314 if (retval != ERROR_OK)
315 return retval;
316 LOG_DEBUG("status: 0x%" PRIx32 "", status);
317 if ((status & FLASH_BSY) == 0)
318 break;
319 if (timeout-- <= 0) {
320 LOG_ERROR("timed out waiting for flash");
321 return ERROR_FAIL;
322 }
323 alive_sleep(1);
324 }
325
326
327 if (status & FLASH_WRPERR) {
328 LOG_ERROR("stm32x device protected");
329 retval = ERROR_FAIL;
330 }
331
332 /* Clear but report errors */
333 if (status & FLASH_ERROR) {
334 if (retval == ERROR_OK)
335 retval = ERROR_FAIL;
336 /* If this operation fails, we ignore it and report the original
337 * retval
338 */
339 stm32l4_write_flash_reg(bank, STM32_FLASH_SR, status & FLASH_ERROR);
340 }
341
342 return retval;
343 }
344
345 static int stm32l4_unlock_reg(struct flash_bank *bank)
346 {
347 uint32_t ctrl;
348
349 /* first check if not already unlocked
350 * otherwise writing on STM32_FLASH_KEYR will fail
351 */
352 int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
353 if (retval != ERROR_OK)
354 return retval;
355
356 if ((ctrl & FLASH_LOCK) == 0)
357 return ERROR_OK;
358
359 /* unlock flash registers */
360 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY1);
361 if (retval != ERROR_OK)
362 return retval;
363
364 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY2);
365 if (retval != ERROR_OK)
366 return retval;
367
368 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
369 if (retval != ERROR_OK)
370 return retval;
371
372 if (ctrl & FLASH_LOCK) {
373 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
374 return ERROR_TARGET_FAILURE;
375 }
376
377 return ERROR_OK;
378 }
379
380 static int stm32l4_unlock_option_reg(struct flash_bank *bank)
381 {
382 uint32_t ctrl;
383
384 int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
385 if (retval != ERROR_OK)
386 return retval;
387
388 if ((ctrl & FLASH_OPTLOCK) == 0)
389 return ERROR_OK;
390
391 /* unlock option registers */
392 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY1);
393 if (retval != ERROR_OK)
394 return retval;
395
396 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY2);
397 if (retval != ERROR_OK)
398 return retval;
399
400 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
401 if (retval != ERROR_OK)
402 return retval;
403
404 if (ctrl & FLASH_OPTLOCK) {
405 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
406 return ERROR_TARGET_FAILURE;
407 }
408
409 return ERROR_OK;
410 }
411
412 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
413 {
414 uint32_t optiondata;
415 int retval, retval2;
416
417 retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
418 if (retval != ERROR_OK)
419 return retval;
420
421 retval = stm32l4_unlock_reg(bank);
422 if (retval != ERROR_OK)
423 goto err_lock;
424
425 retval = stm32l4_unlock_option_reg(bank);
426 if (retval != ERROR_OK)
427 goto err_lock;
428
429 optiondata = (optiondata & ~mask) | (value & mask);
430
431 retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
432 if (retval != ERROR_OK)
433 goto err_lock;
434
435 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OPTSTRT);
436 if (retval != ERROR_OK)
437 goto err_lock;
438
439 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
440
441 err_lock:
442 retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK | FLASH_OPTLOCK);
443
444 if (retval != ERROR_OK)
445 return retval;
446
447 return retval2;
448 }
449
450 static int stm32l4_protect_check(struct flash_bank *bank)
451 {
452 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
453
454 uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
455 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1AR, &wrp1ar);
456 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1BR, &wrp1br);
457 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
458 stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
459
460 const uint8_t wrp1a_start = wrp1ar & 0xFF;
461 const uint8_t wrp1a_end = (wrp1ar >> 16) & 0xFF;
462 const uint8_t wrp1b_start = wrp1br & 0xFF;
463 const uint8_t wrp1b_end = (wrp1br >> 16) & 0xFF;
464 const uint8_t wrp2a_start = wrp2ar & 0xFF;
465 const uint8_t wrp2a_end = (wrp2ar >> 16) & 0xFF;
466 const uint8_t wrp2b_start = wrp2br & 0xFF;
467 const uint8_t wrp2b_end = (wrp2br >> 16) & 0xFF;
468
469 for (int i = 0; i < bank->num_sectors; i++) {
470 if (i < stm32l4_info->bank1_sectors) {
471 if (((i >= wrp1a_start) &&
472 (i <= wrp1a_end)) ||
473 ((i >= wrp1b_start) &&
474 (i <= wrp1b_end)))
475 bank->sectors[i].is_protected = 1;
476 else
477 bank->sectors[i].is_protected = 0;
478 } else {
479 uint8_t snb;
480 snb = i - stm32l4_info->bank1_sectors;
481 if (((snb >= wrp2a_start) &&
482 (snb <= wrp2a_end)) ||
483 ((snb >= wrp2b_start) &&
484 (snb <= wrp2b_end)))
485 bank->sectors[i].is_protected = 1;
486 else
487 bank->sectors[i].is_protected = 0;
488 }
489 }
490 return ERROR_OK;
491 }
492
493 static int stm32l4_erase(struct flash_bank *bank, int first, int last)
494 {
495 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
496 int i;
497 int retval, retval2;
498
499 assert(first < bank->num_sectors);
500 assert(last < bank->num_sectors);
501
502 if (bank->target->state != TARGET_HALTED) {
503 LOG_ERROR("Target not halted");
504 return ERROR_TARGET_NOT_HALTED;
505 }
506
507 retval = stm32l4_unlock_reg(bank);
508 if (retval != ERROR_OK)
509 goto err_lock;
510
511 /*
512 Sector Erase
513 To erase a sector, follow the procedure below:
514 1. Check that no Flash memory operation is ongoing by
515 checking the BSY bit in the FLASH_SR register
516 2. Set the PER bit and select the page and bank
517 you wish to erase in the FLASH_CR register
518 3. Set the STRT bit in the FLASH_CR register
519 4. Wait for the BSY bit to be cleared
520 */
521
522 for (i = first; i <= last; i++) {
523 uint32_t erase_flags;
524 erase_flags = FLASH_PER | FLASH_STRT;
525
526 if (i >= stm32l4_info->bank1_sectors) {
527 uint8_t snb;
528 snb = i - stm32l4_info->bank1_sectors;
529 erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
530 } else
531 erase_flags |= i << FLASH_PAGE_SHIFT;
532 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, erase_flags);
533 if (retval != ERROR_OK)
534 break;
535
536 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
537 if (retval != ERROR_OK)
538 break;
539
540 bank->sectors[i].is_erased = 1;
541 }
542
543 err_lock:
544 retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
545
546 if (retval != ERROR_OK)
547 return retval;
548
549 return retval2;
550 }
551
552 static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
553 {
554 struct target *target = bank->target;
555 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
556
557 if (target->state != TARGET_HALTED) {
558 LOG_ERROR("Target not halted");
559 return ERROR_TARGET_NOT_HALTED;
560 }
561
562 int ret = ERROR_OK;
563 /* Bank 2 */
564 uint32_t reg_value = 0xFF; /* Default to bank un-protected */
565 if (last >= stm32l4_info->bank1_sectors) {
566 if (set == 1) {
567 uint8_t begin = first > stm32l4_info->bank1_sectors ? first : 0x00;
568 reg_value = ((last & 0xFF) << 16) | begin;
569 }
570
571 ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
572 }
573 /* Bank 1 */
574 reg_value = 0xFF; /* Default to bank un-protected */
575 if (first < stm32l4_info->bank1_sectors) {
576 if (set == 1) {
577 uint8_t end = last >= stm32l4_info->bank1_sectors ? 0xFF : last;
578 reg_value = (end << 16) | (first & 0xFF);
579 }
580
581 ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
582 }
583
584 return ret;
585 }
586
587 /* Count is in double-words */
588 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
589 uint32_t offset, uint32_t count)
590 {
591 struct target *target = bank->target;
592 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
593 uint32_t buffer_size = 16384;
594 struct working_area *write_algorithm;
595 struct working_area *source;
596 uint32_t address = bank->base + offset;
597 struct reg_param reg_params[5];
598 struct armv7m_algorithm armv7m_info;
599 int retval = ERROR_OK;
600
601 static const uint8_t stm32l4_flash_write_code[] = {
602 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
603 };
604
605 if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
606 &write_algorithm) != ERROR_OK) {
607 LOG_WARNING("no working area available, can't do block memory writes");
608 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
609 }
610
611 retval = target_write_buffer(target, write_algorithm->address,
612 sizeof(stm32l4_flash_write_code),
613 stm32l4_flash_write_code);
614 if (retval != ERROR_OK) {
615 target_free_working_area(target, write_algorithm);
616 return retval;
617 }
618
619 /* memory buffer */
620 while (target_alloc_working_area_try(target, buffer_size, &source) !=
621 ERROR_OK) {
622 buffer_size /= 2;
623 if (buffer_size <= 256) {
624 /* we already allocated the writing code, but failed to get a
625 * buffer, free the algorithm */
626 target_free_working_area(target, write_algorithm);
627
628 LOG_WARNING("large enough working area not available, can't do block memory writes");
629 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
630 }
631 }
632
633 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
634 armv7m_info.core_mode = ARM_MODE_THREAD;
635
636 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
637 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
638 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
639 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (double word-64bit) */
640 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* flash regs base */
641
642 buf_set_u32(reg_params[0].value, 0, 32, source->address);
643 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
644 buf_set_u32(reg_params[2].value, 0, 32, address);
645 buf_set_u32(reg_params[3].value, 0, 32, count);
646 buf_set_u32(reg_params[4].value, 0, 32, stm32l4_info->part_info->flash_regs_base);
647
648 retval = target_run_flash_async_algorithm(target, buffer, count, 8,
649 0, NULL,
650 5, reg_params,
651 source->address, source->size,
652 write_algorithm->address, 0,
653 &armv7m_info);
654
655 if (retval == ERROR_FLASH_OPERATION_FAILED) {
656 LOG_ERROR("error executing stm32l4 flash write algorithm");
657
658 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
659
660 if (error & FLASH_WRPERR)
661 LOG_ERROR("flash memory write protected");
662
663 if (error != 0) {
664 LOG_ERROR("flash write failed = %08" PRIx32, error);
665 /* Clear but report errors */
666 stm32l4_write_flash_reg(bank, STM32_FLASH_SR, error);
667 retval = ERROR_FAIL;
668 }
669 }
670
671 target_free_working_area(target, source);
672 target_free_working_area(target, write_algorithm);
673
674 destroy_reg_param(&reg_params[0]);
675 destroy_reg_param(&reg_params[1]);
676 destroy_reg_param(&reg_params[2]);
677 destroy_reg_param(&reg_params[3]);
678 destroy_reg_param(&reg_params[4]);
679
680 return retval;
681 }
682
683 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
684 uint32_t offset, uint32_t count)
685 {
686 int retval, retval2;
687
688 if (bank->target->state != TARGET_HALTED) {
689 LOG_ERROR("Target not halted");
690 return ERROR_TARGET_NOT_HALTED;
691 }
692
693 /* The flash write must be aligned to a double word (8-bytes) boundary.
694 * The flash infrastructure ensures it, do just a security check */
695 assert(offset % 8 == 0);
696 assert(count % 8 == 0);
697
698 retval = stm32l4_unlock_reg(bank);
699 if (retval != ERROR_OK)
700 goto err_lock;
701
702 retval = stm32l4_write_block(bank, buffer, offset, count / 8);
703
704 err_lock:
705 retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
706
707 if (retval != ERROR_OK) {
708 LOG_ERROR("block write failed");
709 return retval;
710 }
711 return retval2;
712 }
713
714 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
715 {
716 int retval = target_read_u32(bank->target, DBGMCU_IDCODE, id);
717 if (retval != ERROR_OK)
718 return retval;
719
720 return retval;
721 }
722
723 static int stm32l4_probe(struct flash_bank *bank)
724 {
725 struct target *target = bank->target;
726 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
727 const struct stm32l4_part_info *part_info;
728 uint16_t flash_size_in_kb = 0xffff;
729 uint32_t device_id;
730 uint32_t options;
731
732 stm32l4_info->probed = false;
733
734 /* read stm32 device id register */
735 int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
736 if (retval != ERROR_OK)
737 return retval;
738
739 device_id = stm32l4_info->idcode & 0xFFF;
740
741 for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
742 if (device_id == stm32l4_parts[n].id)
743 stm32l4_info->part_info = &stm32l4_parts[n];
744 }
745
746 if (!stm32l4_info->part_info) {
747 LOG_WARNING("Cannot identify target as an STM32 L4 or WB family device.");
748 return ERROR_FAIL;
749 }
750
751 part_info = stm32l4_info->part_info;
752
753 char device_info[1024];
754 retval = bank->driver->info(bank, device_info, sizeof(device_info));
755 if (retval != ERROR_OK)
756 return retval;
757
758 LOG_INFO("device idcode = 0x%08" PRIx32 " (%s)", stm32l4_info->idcode, device_info);
759
760 /* get flash size from target. */
761 retval = target_read_u16(target, part_info->fsize_addr, &flash_size_in_kb);
762
763 /* failed reading flash size or flash size invalid (early silicon),
764 * default to max target family */
765 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0
766 || flash_size_in_kb > part_info->max_flash_size_kb) {
767 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
768 part_info->max_flash_size_kb);
769 flash_size_in_kb = part_info->max_flash_size_kb;
770 }
771
772 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
773
774 /* did we assign a flash size? */
775 assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
776
777 /* read flash option register */
778 retval = stm32l4_read_flash_reg(bank, STM32_FLASH_OPTR, &options);
779 if (retval != ERROR_OK)
780 return retval;
781
782 stm32l4_info->bank1_sectors = 0;
783 stm32l4_info->hole_sectors = 0;
784
785 int num_pages = 0;
786 int page_size = 0;
787
788 stm32l4_info->dual_bank_mode = false;
789
790 switch (device_id) {
791 case 0x415:
792 case 0x461:
793 /* if flash size is max (1M) the device is always dual bank
794 * 0x415: has variants with 512K
795 * 0x461: has variants with 512 and 256
796 * for these variants:
797 * if DUAL_BANK = 0 -> single bank
798 * else -> dual bank without gap
799 * note: the page size is invariant
800 */
801 page_size = 2048;
802 num_pages = flash_size_in_kb / 2;
803 stm32l4_info->bank1_sectors = num_pages;
804
805 /* check DUAL_BANK bit[21] if the flash is less than 1M */
806 if (flash_size_in_kb == 1024 || (options & BIT(21))) {
807 stm32l4_info->dual_bank_mode = true;
808 stm32l4_info->bank1_sectors = num_pages / 2;
809 }
810 break;
811 case 0x435:
812 case 0x462:
813 case 0x464:
814 /* single bank flash */
815 page_size = 2048;
816 num_pages = flash_size_in_kb / 2;
817 stm32l4_info->bank1_sectors = num_pages;
818 break;
819 case 0x470:
820 case 0x471:
821 /* STM32L4R/S can be single/dual bank:
822 * if size = 2M check DBANK bit(22)
823 * if size = 1M check DB1M bit(21)
824 * STM32L4P/Q can be single/dual bank
825 * if size = 1M check DBANK bit(22)
826 * if size = 512K check DB512K bit(21)
827 * in single bank configuration the page size is 8K
828 * else (dual bank) the page size is 4K without gap between banks
829 */
830 page_size = 8192;
831 num_pages = flash_size_in_kb / 8;
832 stm32l4_info->bank1_sectors = num_pages;
833 const bool use_dbank_bit = flash_size_in_kb == part_info->max_flash_size_kb;
834 if ((use_dbank_bit && (options & BIT(22))) ||
835 (!use_dbank_bit && (options & BIT(21)))) {
836 stm32l4_info->dual_bank_mode = true;
837 page_size = 4096;
838 num_pages = flash_size_in_kb / 4;
839 stm32l4_info->bank1_sectors = num_pages / 2;
840 }
841 break;
842 case 0x495:
843 /* single bank flash */
844 page_size = 4096;
845 num_pages = flash_size_in_kb / 4;
846 stm32l4_info->bank1_sectors = num_pages;
847 break;
848 default:
849 LOG_ERROR("unsupported device");
850 return ERROR_FAIL;
851 }
852
853 LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
854
855 const int gap_size = stm32l4_info->hole_sectors * page_size;
856
857 if (stm32l4_info->dual_bank_mode & gap_size) {
858 LOG_INFO("gap detected starting from %0x08" PRIx32 " to %0x08" PRIx32,
859 0x8000000 + stm32l4_info->bank1_sectors * page_size,
860 0x8000000 + stm32l4_info->bank1_sectors * page_size + gap_size);
861 }
862
863 if (bank->sectors) {
864 free(bank->sectors);
865 bank->sectors = NULL;
866 }
867
868 bank->size = flash_size_in_kb * 1024 + gap_size;
869 bank->base = 0x08000000;
870 bank->num_sectors = num_pages;
871 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
872 if (bank->sectors == NULL) {
873 LOG_ERROR("failed to allocate bank sectors");
874 return ERROR_FAIL;
875 }
876
877 for (int i = 0; i < bank->num_sectors; i++) {
878 bank->sectors[i].offset = i * page_size;
879 /* in dual bank configuration, if there is a gap between banks
880 * we fix up the sector offset to consider this gap */
881 if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
882 bank->sectors[i].offset += gap_size;
883 bank->sectors[i].size = page_size;
884 bank->sectors[i].is_erased = -1;
885 bank->sectors[i].is_protected = 1;
886 }
887
888 stm32l4_info->probed = true;
889 return ERROR_OK;
890 }
891
892 static int stm32l4_auto_probe(struct flash_bank *bank)
893 {
894 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
895 if (stm32l4_info->probed)
896 return ERROR_OK;
897
898 return stm32l4_probe(bank);
899 }
900
901 static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
902 {
903 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
904 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
905
906 if (part_info) {
907 const char *rev_str = NULL;
908 uint16_t rev_id = stm32l4_info->idcode >> 16;
909 for (unsigned int i = 0; i < part_info->num_revs; i++) {
910 if (rev_id == part_info->revs[i].rev) {
911 rev_str = part_info->revs[i].str;
912
913 if (rev_str != NULL) {
914 snprintf(buf, buf_size, "%s - Rev: %s",
915 part_info->device_str, rev_str);
916 return ERROR_OK;
917 }
918 }
919 }
920
921 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)",
922 part_info->device_str, rev_id);
923 return ERROR_OK;
924 } else {
925 snprintf(buf, buf_size, "Cannot identify target as an STM32 L4 or WB device");
926 return ERROR_FAIL;
927 }
928
929 return ERROR_OK;
930 }
931
932 static int stm32l4_mass_erase(struct flash_bank *bank)
933 {
934 int retval, retval2;
935 struct target *target = bank->target;
936 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
937
938 uint32_t action = FLASH_MER1;
939
940 if (stm32l4_info->part_info->has_dual_bank)
941 action |= FLASH_MER2;
942
943 if (target->state != TARGET_HALTED) {
944 LOG_ERROR("Target not halted");
945 return ERROR_TARGET_NOT_HALTED;
946 }
947
948 retval = stm32l4_unlock_reg(bank);
949 if (retval != ERROR_OK)
950 goto err_lock;
951
952 /* mass erase flash memory */
953 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
954 if (retval != ERROR_OK)
955 goto err_lock;
956
957 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action);
958 if (retval != ERROR_OK)
959 goto err_lock;
960
961 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action | FLASH_STRT);
962 if (retval != ERROR_OK)
963 goto err_lock;
964
965 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
966
967 err_lock:
968 retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
969
970 if (retval != ERROR_OK)
971 return retval;
972
973 return retval2;
974 }
975
976 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
977 {
978 if (CMD_ARGC < 1) {
979 command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
980 return ERROR_COMMAND_SYNTAX_ERROR;
981 }
982
983 struct flash_bank *bank;
984 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
985 if (ERROR_OK != retval)
986 return retval;
987
988 retval = stm32l4_mass_erase(bank);
989 if (retval == ERROR_OK) {
990 /* set all sectors as erased */
991 for (int i = 0; i < bank->num_sectors; i++)
992 bank->sectors[i].is_erased = 1;
993
994 command_print(CMD, "stm32l4x mass erase complete");
995 } else {
996 command_print(CMD, "stm32l4x mass erase failed");
997 }
998
999 return retval;
1000 }
1001
1002 COMMAND_HANDLER(stm32l4_handle_option_read_command)
1003 {
1004 if (CMD_ARGC < 2) {
1005 command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
1006 return ERROR_COMMAND_SYNTAX_ERROR;
1007 }
1008
1009 struct flash_bank *bank;
1010 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1011 if (ERROR_OK != retval)
1012 return retval;
1013
1014 uint32_t reg_offset, reg_addr;
1015 uint32_t value = 0;
1016
1017 reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
1018 reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
1019
1020 retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
1021 if (ERROR_OK != retval)
1022 return retval;
1023
1024 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
1025
1026 return retval;
1027 }
1028
1029 COMMAND_HANDLER(stm32l4_handle_option_write_command)
1030 {
1031 if (CMD_ARGC < 3) {
1032 command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
1033 return ERROR_COMMAND_SYNTAX_ERROR;
1034 }
1035
1036 struct flash_bank *bank;
1037 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1038 if (ERROR_OK != retval)
1039 return retval;
1040
1041 uint32_t reg_offset;
1042 uint32_t value = 0;
1043 uint32_t mask = 0xFFFFFFFF;
1044
1045 reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
1046 value = strtoul(CMD_ARGV[2], NULL, 16);
1047 if (CMD_ARGC > 3)
1048 mask = strtoul(CMD_ARGV[3], NULL, 16);
1049
1050 command_print(CMD, "%s Option written.\n"
1051 "INFO: a reset or power cycle is required "
1052 "for the new settings to take effect.", bank->driver->name);
1053
1054 retval = stm32l4_write_option(bank, reg_offset, value, mask);
1055 return retval;
1056 }
1057
1058 COMMAND_HANDLER(stm32l4_handle_option_load_command)
1059 {
1060 if (CMD_ARGC < 1)
1061 return ERROR_COMMAND_SYNTAX_ERROR;
1062
1063 struct flash_bank *bank;
1064 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1065 if (ERROR_OK != retval)
1066 return retval;
1067
1068 retval = stm32l4_unlock_reg(bank);
1069 if (ERROR_OK != retval)
1070 return retval;
1071
1072 retval = stm32l4_unlock_option_reg(bank);
1073 if (ERROR_OK != retval)
1074 return retval;
1075
1076 /* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
1077 retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OBLLAUNCH);
1078
1079 command_print(CMD, "stm32l4x option load (POR) completed.");
1080 return retval;
1081 }
1082
1083 COMMAND_HANDLER(stm32l4_handle_lock_command)
1084 {
1085 struct target *target = NULL;
1086
1087 if (CMD_ARGC < 1)
1088 return ERROR_COMMAND_SYNTAX_ERROR;
1089
1090 struct flash_bank *bank;
1091 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1092 if (ERROR_OK != retval)
1093 return retval;
1094
1095 target = bank->target;
1096
1097 if (target->state != TARGET_HALTED) {
1098 LOG_ERROR("Target not halted");
1099 return ERROR_TARGET_NOT_HALTED;
1100 }
1101
1102 /* set readout protection level 1 by erasing the RDP option byte */
1103 if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
1104 command_print(CMD, "%s failed to lock device", bank->driver->name);
1105 return ERROR_OK;
1106 }
1107
1108 return ERROR_OK;
1109 }
1110
1111 COMMAND_HANDLER(stm32l4_handle_unlock_command)
1112 {
1113 struct target *target = NULL;
1114
1115 if (CMD_ARGC < 1)
1116 return ERROR_COMMAND_SYNTAX_ERROR;
1117
1118 struct flash_bank *bank;
1119 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1120 if (ERROR_OK != retval)
1121 return retval;
1122
1123 target = bank->target;
1124
1125 if (target->state != TARGET_HALTED) {
1126 LOG_ERROR("Target not halted");
1127 return ERROR_TARGET_NOT_HALTED;
1128 }
1129
1130 if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
1131 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1132 return ERROR_OK;
1133 }
1134
1135 return ERROR_OK;
1136 }
1137
1138 static const struct command_registration stm32l4_exec_command_handlers[] = {
1139 {
1140 .name = "lock",
1141 .handler = stm32l4_handle_lock_command,
1142 .mode = COMMAND_EXEC,
1143 .usage = "bank_id",
1144 .help = "Lock entire flash device.",
1145 },
1146 {
1147 .name = "unlock",
1148 .handler = stm32l4_handle_unlock_command,
1149 .mode = COMMAND_EXEC,
1150 .usage = "bank_id",
1151 .help = "Unlock entire protected flash device.",
1152 },
1153 {
1154 .name = "mass_erase",
1155 .handler = stm32l4_handle_mass_erase_command,
1156 .mode = COMMAND_EXEC,
1157 .usage = "bank_id",
1158 .help = "Erase entire flash device.",
1159 },
1160 {
1161 .name = "option_read",
1162 .handler = stm32l4_handle_option_read_command,
1163 .mode = COMMAND_EXEC,
1164 .usage = "bank_id reg_offset",
1165 .help = "Read & Display device option bytes.",
1166 },
1167 {
1168 .name = "option_write",
1169 .handler = stm32l4_handle_option_write_command,
1170 .mode = COMMAND_EXEC,
1171 .usage = "bank_id reg_offset value mask",
1172 .help = "Write device option bit fields with provided value.",
1173 },
1174 {
1175 .name = "option_load",
1176 .handler = stm32l4_handle_option_load_command,
1177 .mode = COMMAND_EXEC,
1178 .usage = "bank_id",
1179 .help = "Force re-load of device options (will cause device reset).",
1180 },
1181 COMMAND_REGISTRATION_DONE
1182 };
1183
1184 static const struct command_registration stm32l4_command_handlers[] = {
1185 {
1186 .name = "stm32l4x",
1187 .mode = COMMAND_ANY,
1188 .help = "stm32l4x flash command group",
1189 .usage = "",
1190 .chain = stm32l4_exec_command_handlers,
1191 },
1192 COMMAND_REGISTRATION_DONE
1193 };
1194
1195 const struct flash_driver stm32l4x_flash = {
1196 .name = "stm32l4x",
1197 .commands = stm32l4_command_handlers,
1198 .flash_bank_command = stm32l4_flash_bank_command,
1199 .erase = stm32l4_erase,
1200 .protect = stm32l4_protect,
1201 .write = stm32l4_write,
1202 .read = default_flash_read,
1203 .probe = stm32l4_probe,
1204 .auto_probe = stm32l4_auto_probe,
1205 .erase_check = default_flash_blank_check,
1206 .protect_check = stm32l4_protect_check,
1207 .info = get_stm32l4_info,
1208 .free_driver_priv = default_flash_free_driver_priv,
1209 };
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