1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2015 by Uwe Bonnes *
5 * bon@elektron.ikp.physik.tu-darmstadt.de *
7 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
8 * tarek.bouchkati@gmail.com *
9 ***************************************************************************/
16 #include <helper/align.h>
17 #include <helper/binarybuffer.h>
18 #include <helper/bits.h>
19 #include <target/algorithm.h>
20 #include <target/arm_adi_v5.h>
21 #include <target/cortex_m.h>
24 /* STM32L4xxx series for reference.
26 * RM0351 (STM32L4x5/STM32L4x6)
27 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
29 * RM0394 (STM32L43x/44x/45x/46x)
30 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
32 * RM0432 (STM32L4R/4Sxx)
33 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
35 * STM32L476RG Datasheet (for erase timing)
36 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
38 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
39 * an option byte is available to map all sectors to the first bank.
40 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
43 * RM0394 devices have a single bank only.
45 * RM0432 devices have single and dual bank operating modes.
46 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
47 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
48 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
50 * Bank mode is controlled by two different bits in option bytes register.
52 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
53 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
55 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
56 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
59 /* STM32WBxxx series for reference.
61 * RM0493 (STM32WBA52x)
62 * http://www.st.com/resource/en/reference_manual/dm00821869.pdf
64 * RM0434 (STM32WB55/WB35x)
65 * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
67 * RM0471 (STM32WB50/WB30x)
68 * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
71 * http://www.st.com/resource/en/reference_manual/dm00649196.pdf
74 * http://www.st.com/resource/en/reference_manual/dm00689203.pdf
77 /* STM32WLxxx series for reference.
80 * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
83 * http://www.st.com/resource/en/reference_manual/dm00451556.pdf
86 /* STM32C0xxx series for reference.
89 * http://www.st.com/resource/en/reference_manual/dm00781702.pdf
92 /* STM32G0xxx series for reference.
95 * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
98 * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
101 /* STM32G4xxx series for reference.
103 * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
104 * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
106 * Cat. 2 devices have single bank only, page size is 2kByte.
108 * Cat. 3 devices have single and dual bank operating modes,
109 * Page size is 2kByte (dual mode) or 4kByte (single mode).
111 * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
112 * Both banks are treated as a single OpenOCD bank.
114 * Cat. 4 devices have single bank only, page size is 2kByte.
117 /* STM32L5xxx series for reference.
119 * RM0428 (STM32L552xx/STM32L562xx)
120 * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
123 /* STM32U5xxx series for reference.
126 * http://www.st.com/resource/en/reference_manual/dm00477635.pdf
129 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
131 #define FLASH_ERASE_TIMEOUT 250
132 #define FLASH_WRITE_TIMEOUT 50
135 /* relevant STM32L4 flags ****************************************************/
137 /* this flag indicates if the device flash is with dual bank architecture */
138 #define F_HAS_DUAL_BANK BIT(0)
139 /* this flags is used for dual bank devices only, it indicates if the
140 * 4 WRPxx are usable if the device is configured in single-bank mode */
141 #define F_USE_ALL_WRPXX BIT(1)
142 /* this flag indicates if the device embeds a TrustZone security feature */
143 #define F_HAS_TZ BIT(2)
144 /* this flag indicates if the device has the same flash registers as STM32L5 */
145 #define F_HAS_L5_FLASH_REGS BIT(3)
146 /* this flag indicates that programming should be done in quad-word
147 * the default programming word size is double-word */
148 #define F_QUAD_WORD_PROG BIT(4)
149 /* end of STM32L4 flags ******************************************************/
152 enum stm32l4_flash_reg_index
{
153 STM32_FLASH_ACR_INDEX
,
154 STM32_FLASH_KEYR_INDEX
,
155 STM32_FLASH_OPTKEYR_INDEX
,
156 STM32_FLASH_SR_INDEX
,
157 STM32_FLASH_CR_INDEX
,
158 /* for some devices like STM32WL5x, the CPU2 have a dedicated C2CR register w/o LOCKs,
159 * so it uses the C2CR for flash operations and CR for checking locks and locking */
160 STM32_FLASH_CR_WLK_INDEX
, /* FLASH_CR_WITH_LOCK */
161 STM32_FLASH_OPTR_INDEX
,
162 STM32_FLASH_WRP1AR_INDEX
,
163 STM32_FLASH_WRP1BR_INDEX
,
164 STM32_FLASH_WRP2AR_INDEX
,
165 STM32_FLASH_WRP2BR_INDEX
,
166 STM32_FLASH_REG_INDEX_NUM
,
171 RDP_LEVEL_0_5
= 0x55, /* for devices with TrustZone enabled */
176 static const uint32_t stm32l4_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
177 [STM32_FLASH_ACR_INDEX
] = 0x000,
178 [STM32_FLASH_KEYR_INDEX
] = 0x008,
179 [STM32_FLASH_OPTKEYR_INDEX
] = 0x00C,
180 [STM32_FLASH_SR_INDEX
] = 0x010,
181 [STM32_FLASH_CR_INDEX
] = 0x014,
182 [STM32_FLASH_OPTR_INDEX
] = 0x020,
183 [STM32_FLASH_WRP1AR_INDEX
] = 0x02C,
184 [STM32_FLASH_WRP1BR_INDEX
] = 0x030,
185 [STM32_FLASH_WRP2AR_INDEX
] = 0x04C,
186 [STM32_FLASH_WRP2BR_INDEX
] = 0x050,
189 static const uint32_t stm32wl_cpu2_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
190 [STM32_FLASH_ACR_INDEX
] = 0x000,
191 [STM32_FLASH_KEYR_INDEX
] = 0x008,
192 [STM32_FLASH_OPTKEYR_INDEX
] = 0x010,
193 [STM32_FLASH_SR_INDEX
] = 0x060,
194 [STM32_FLASH_CR_INDEX
] = 0x064,
195 [STM32_FLASH_CR_WLK_INDEX
] = 0x014,
196 [STM32_FLASH_OPTR_INDEX
] = 0x020,
197 [STM32_FLASH_WRP1AR_INDEX
] = 0x02C,
198 [STM32_FLASH_WRP1BR_INDEX
] = 0x030,
201 static const uint32_t stm32l5_ns_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
202 [STM32_FLASH_ACR_INDEX
] = 0x000,
203 [STM32_FLASH_KEYR_INDEX
] = 0x008, /* NSKEYR */
204 [STM32_FLASH_OPTKEYR_INDEX
] = 0x010,
205 [STM32_FLASH_SR_INDEX
] = 0x020, /* NSSR */
206 [STM32_FLASH_CR_INDEX
] = 0x028, /* NSCR */
207 [STM32_FLASH_OPTR_INDEX
] = 0x040,
208 [STM32_FLASH_WRP1AR_INDEX
] = 0x058,
209 [STM32_FLASH_WRP1BR_INDEX
] = 0x05C,
210 [STM32_FLASH_WRP2AR_INDEX
] = 0x068,
211 [STM32_FLASH_WRP2BR_INDEX
] = 0x06C,
214 static const uint32_t stm32l5_s_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
215 [STM32_FLASH_ACR_INDEX
] = 0x000,
216 [STM32_FLASH_KEYR_INDEX
] = 0x00C, /* SECKEYR */
217 [STM32_FLASH_OPTKEYR_INDEX
] = 0x010,
218 [STM32_FLASH_SR_INDEX
] = 0x024, /* SECSR */
219 [STM32_FLASH_CR_INDEX
] = 0x02C, /* SECCR */
220 [STM32_FLASH_OPTR_INDEX
] = 0x040,
221 [STM32_FLASH_WRP1AR_INDEX
] = 0x058,
222 [STM32_FLASH_WRP1BR_INDEX
] = 0x05C,
223 [STM32_FLASH_WRP2AR_INDEX
] = 0x068,
224 [STM32_FLASH_WRP2BR_INDEX
] = 0x06C,
232 struct stm32l4_part_info
{
234 const char *device_str
;
235 const struct stm32l4_rev
*revs
;
236 const size_t num_revs
;
237 const uint16_t max_flash_size_kb
;
238 const uint32_t flags
; /* one bit per feature, see STM32L4 flags: macros F_XXX */
239 const uint32_t flash_regs_base
;
240 const uint32_t fsize_addr
;
241 const uint32_t otp_base
;
242 const uint32_t otp_size
;
245 struct stm32l4_flash_bank
{
248 unsigned int bank1_sectors
;
251 uint32_t user_bank_size
;
253 uint32_t cr_bker_mask
;
254 uint32_t sr_bsy_mask
;
255 uint32_t wrpxxr_mask
;
256 const struct stm32l4_part_info
*part_info
;
257 uint32_t flash_regs_base
;
258 const uint32_t *flash_regs
;
260 enum stm32l4_rdp rdp
;
272 enum stm32l4_flash_reg_index reg_idx
;
280 /* human readable list of families this drivers supports (sorted alphabetically) */
281 static const char *device_families
= "STM32C0/G0/G4/L4/L4+/L5/U5/WB/WL";
283 static const struct stm32l4_rev stm32l47_l48xx_revs
[] = {
284 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
287 static const struct stm32l4_rev stm32l43_l44xx_revs
[] = {
288 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
292 static const struct stm32l4_rev stm32c01xx_revs
[] = {
293 { 0x1000, "A" }, { 0x1001, "Z" },
296 static const struct stm32l4_rev stm32c03xx_revs
[] = {
297 { 0x1000, "A" }, { 0x1001, "Z" },
300 static const struct stm32l4_rev stm32g05_g06xx_revs
[] = {
304 static const struct stm32l4_rev stm32_g07_g08xx_revs
[] = {
305 { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
308 static const struct stm32l4_rev stm32l49_l4axx_revs
[] = {
309 { 0x1000, "A" }, { 0x2000, "B" },
312 static const struct stm32l4_rev stm32l45_l46xx_revs
[] = {
313 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
316 static const struct stm32l4_rev stm32l41_l42xx_revs
[] = {
317 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
320 static const struct stm32l4_rev stm32g03_g04xx_revs
[] = {
321 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
324 static const struct stm32l4_rev stm32g0b_g0cxx_revs
[] = {
328 static const struct stm32l4_rev stm32g43_g44xx_revs
[] = {
329 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
332 static const struct stm32l4_rev stm32g47_g48xx_revs
[] = {
333 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
336 static const struct stm32l4_rev stm32l4r_l4sxx_revs
[] = {
337 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
341 static const struct stm32l4_rev stm32l4p_l4qxx_revs
[] = {
345 static const struct stm32l4_rev stm32l55_l56xx_revs
[] = {
346 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
349 static const struct stm32l4_rev stm32g49_g4axx_revs
[] = {
353 static const struct stm32l4_rev stm32u53_u54xx_revs
[] = {
354 { 0x1000, "A" }, { 0x1001, "Z" },
357 static const struct stm32l4_rev stm32u57_u58xx_revs
[] = {
358 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" },
359 { 0x2001, "X" }, { 0x3000, "C" }, { 0x3001, "W" },
362 static const struct stm32l4_rev stm32u59_u5axx_revs
[] = {
366 static const struct stm32l4_rev stm32wba5x_revs
[] = {
370 static const struct stm32l4_rev stm32wb1xx_revs
[] = {
371 { 0x1000, "A" }, { 0x2000, "B" },
374 static const struct stm32l4_rev stm32wb5xx_revs
[] = {
378 static const struct stm32l4_rev stm32wb3xx_revs
[] = {
382 static const struct stm32l4_rev stm32wle_wl5xx_revs
[] = {
386 static const struct stm32l4_part_info stm32l4_parts
[] = {
388 .id
= DEVID_STM32L47_L48XX
,
389 .revs
= stm32l47_l48xx_revs
,
390 .num_revs
= ARRAY_SIZE(stm32l47_l48xx_revs
),
391 .device_str
= "STM32L47/L48xx",
392 .max_flash_size_kb
= 1024,
393 .flags
= F_HAS_DUAL_BANK
,
394 .flash_regs_base
= 0x40022000,
395 .fsize_addr
= 0x1FFF75E0,
396 .otp_base
= 0x1FFF7000,
400 .id
= DEVID_STM32L43_L44XX
,
401 .revs
= stm32l43_l44xx_revs
,
402 .num_revs
= ARRAY_SIZE(stm32l43_l44xx_revs
),
403 .device_str
= "STM32L43/L44xx",
404 .max_flash_size_kb
= 256,
406 .flash_regs_base
= 0x40022000,
407 .fsize_addr
= 0x1FFF75E0,
408 .otp_base
= 0x1FFF7000,
412 .id
= DEVID_STM32C01XX
,
413 .revs
= stm32c01xx_revs
,
414 .num_revs
= ARRAY_SIZE(stm32c01xx_revs
),
415 .device_str
= "STM32C01xx",
416 .max_flash_size_kb
= 32,
418 .flash_regs_base
= 0x40022000,
419 .fsize_addr
= 0x1FFF75A0,
420 .otp_base
= 0x1FFF7000,
424 .id
= DEVID_STM32C03XX
,
425 .revs
= stm32c03xx_revs
,
426 .num_revs
= ARRAY_SIZE(stm32c03xx_revs
),
427 .device_str
= "STM32C03xx",
428 .max_flash_size_kb
= 32,
430 .flash_regs_base
= 0x40022000,
431 .fsize_addr
= 0x1FFF75A0,
432 .otp_base
= 0x1FFF7000,
436 .id
= DEVID_STM32U53_U54XX
,
437 .revs
= stm32u53_u54xx_revs
,
438 .num_revs
= ARRAY_SIZE(stm32u53_u54xx_revs
),
439 .device_str
= "STM32U535/U545",
440 .max_flash_size_kb
= 512,
441 .flags
= F_HAS_DUAL_BANK
| F_QUAD_WORD_PROG
| F_HAS_TZ
| F_HAS_L5_FLASH_REGS
,
442 .flash_regs_base
= 0x40022000,
443 .fsize_addr
= 0x0BFA07A0,
444 .otp_base
= 0x0BFA0000,
448 .id
= DEVID_STM32G05_G06XX
,
449 .revs
= stm32g05_g06xx_revs
,
450 .num_revs
= ARRAY_SIZE(stm32g05_g06xx_revs
),
451 .device_str
= "STM32G05/G06xx",
452 .max_flash_size_kb
= 64,
454 .flash_regs_base
= 0x40022000,
455 .fsize_addr
= 0x1FFF75E0,
456 .otp_base
= 0x1FFF7000,
460 .id
= DEVID_STM32G07_G08XX
,
461 .revs
= stm32_g07_g08xx_revs
,
462 .num_revs
= ARRAY_SIZE(stm32_g07_g08xx_revs
),
463 .device_str
= "STM32G07/G08xx",
464 .max_flash_size_kb
= 128,
466 .flash_regs_base
= 0x40022000,
467 .fsize_addr
= 0x1FFF75E0,
468 .otp_base
= 0x1FFF7000,
472 .id
= DEVID_STM32L49_L4AXX
,
473 .revs
= stm32l49_l4axx_revs
,
474 .num_revs
= ARRAY_SIZE(stm32l49_l4axx_revs
),
475 .device_str
= "STM32L49/L4Axx",
476 .max_flash_size_kb
= 1024,
477 .flags
= F_HAS_DUAL_BANK
,
478 .flash_regs_base
= 0x40022000,
479 .fsize_addr
= 0x1FFF75E0,
480 .otp_base
= 0x1FFF7000,
484 .id
= DEVID_STM32L45_L46XX
,
485 .revs
= stm32l45_l46xx_revs
,
486 .num_revs
= ARRAY_SIZE(stm32l45_l46xx_revs
),
487 .device_str
= "STM32L45/L46xx",
488 .max_flash_size_kb
= 512,
490 .flash_regs_base
= 0x40022000,
491 .fsize_addr
= 0x1FFF75E0,
492 .otp_base
= 0x1FFF7000,
496 .id
= DEVID_STM32L41_L42XX
,
497 .revs
= stm32l41_l42xx_revs
,
498 .num_revs
= ARRAY_SIZE(stm32l41_l42xx_revs
),
499 .device_str
= "STM32L41/L42xx",
500 .max_flash_size_kb
= 128,
502 .flash_regs_base
= 0x40022000,
503 .fsize_addr
= 0x1FFF75E0,
504 .otp_base
= 0x1FFF7000,
508 .id
= DEVID_STM32G03_G04XX
,
509 .revs
= stm32g03_g04xx_revs
,
510 .num_revs
= ARRAY_SIZE(stm32g03_g04xx_revs
),
511 .device_str
= "STM32G03x/G04xx",
512 .max_flash_size_kb
= 64,
514 .flash_regs_base
= 0x40022000,
515 .fsize_addr
= 0x1FFF75E0,
516 .otp_base
= 0x1FFF7000,
520 .id
= DEVID_STM32G0B_G0CXX
,
521 .revs
= stm32g0b_g0cxx_revs
,
522 .num_revs
= ARRAY_SIZE(stm32g0b_g0cxx_revs
),
523 .device_str
= "STM32G0B/G0Cx",
524 .max_flash_size_kb
= 512,
525 .flags
= F_HAS_DUAL_BANK
,
526 .flash_regs_base
= 0x40022000,
527 .fsize_addr
= 0x1FFF75E0,
528 .otp_base
= 0x1FFF7000,
532 .id
= DEVID_STM32G43_G44XX
,
533 .revs
= stm32g43_g44xx_revs
,
534 .num_revs
= ARRAY_SIZE(stm32g43_g44xx_revs
),
535 .device_str
= "STM32G43/G44xx",
536 .max_flash_size_kb
= 128,
538 .flash_regs_base
= 0x40022000,
539 .fsize_addr
= 0x1FFF75E0,
540 .otp_base
= 0x1FFF7000,
544 .id
= DEVID_STM32G47_G48XX
,
545 .revs
= stm32g47_g48xx_revs
,
546 .num_revs
= ARRAY_SIZE(stm32g47_g48xx_revs
),
547 .device_str
= "STM32G47/G48xx",
548 .max_flash_size_kb
= 512,
549 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
550 .flash_regs_base
= 0x40022000,
551 .fsize_addr
= 0x1FFF75E0,
552 .otp_base
= 0x1FFF7000,
556 .id
= DEVID_STM32L4R_L4SXX
,
557 .revs
= stm32l4r_l4sxx_revs
,
558 .num_revs
= ARRAY_SIZE(stm32l4r_l4sxx_revs
),
559 .device_str
= "STM32L4R/L4Sxx",
560 .max_flash_size_kb
= 2048,
561 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
562 .flash_regs_base
= 0x40022000,
563 .fsize_addr
= 0x1FFF75E0,
564 .otp_base
= 0x1FFF7000,
568 .id
= DEVID_STM32L4P_L4QXX
,
569 .revs
= stm32l4p_l4qxx_revs
,
570 .num_revs
= ARRAY_SIZE(stm32l4p_l4qxx_revs
),
571 .device_str
= "STM32L4P/L4Qxx",
572 .max_flash_size_kb
= 1024,
573 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
574 .flash_regs_base
= 0x40022000,
575 .fsize_addr
= 0x1FFF75E0,
576 .otp_base
= 0x1FFF7000,
580 .id
= DEVID_STM32L55_L56XX
,
581 .revs
= stm32l55_l56xx_revs
,
582 .num_revs
= ARRAY_SIZE(stm32l55_l56xx_revs
),
583 .device_str
= "STM32L55/L56xx",
584 .max_flash_size_kb
= 512,
585 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
| F_HAS_TZ
| F_HAS_L5_FLASH_REGS
,
586 .flash_regs_base
= 0x40022000,
587 .fsize_addr
= 0x0BFA05E0,
588 .otp_base
= 0x0BFA0000,
592 .id
= DEVID_STM32G49_G4AXX
,
593 .revs
= stm32g49_g4axx_revs
,
594 .num_revs
= ARRAY_SIZE(stm32g49_g4axx_revs
),
595 .device_str
= "STM32G49/G4Axx",
596 .max_flash_size_kb
= 512,
598 .flash_regs_base
= 0x40022000,
599 .fsize_addr
= 0x1FFF75E0,
600 .otp_base
= 0x1FFF7000,
604 .id
= DEVID_STM32U59_U5AXX
,
605 .revs
= stm32u59_u5axx_revs
,
606 .num_revs
= ARRAY_SIZE(stm32u59_u5axx_revs
),
607 .device_str
= "STM32U59/U5Axx",
608 .max_flash_size_kb
= 4096,
609 .flags
= F_HAS_DUAL_BANK
| F_QUAD_WORD_PROG
| F_HAS_TZ
| F_HAS_L5_FLASH_REGS
,
610 .flash_regs_base
= 0x40022000,
611 .fsize_addr
= 0x0BFA07A0,
612 .otp_base
= 0x0BFA0000,
616 .id
= DEVID_STM32U57_U58XX
,
617 .revs
= stm32u57_u58xx_revs
,
618 .num_revs
= ARRAY_SIZE(stm32u57_u58xx_revs
),
619 .device_str
= "STM32U57/U58xx",
620 .max_flash_size_kb
= 2048,
621 .flags
= F_HAS_DUAL_BANK
| F_QUAD_WORD_PROG
| F_HAS_TZ
| F_HAS_L5_FLASH_REGS
,
622 .flash_regs_base
= 0x40022000,
623 .fsize_addr
= 0x0BFA07A0,
624 .otp_base
= 0x0BFA0000,
628 .id
= DEVID_STM32WBA5X
,
629 .revs
= stm32wba5x_revs
,
630 .num_revs
= ARRAY_SIZE(stm32wba5x_revs
),
631 .device_str
= "STM32WBA5x",
632 .max_flash_size_kb
= 1024,
633 .flags
= F_QUAD_WORD_PROG
| F_HAS_TZ
| F_HAS_L5_FLASH_REGS
,
634 .flash_regs_base
= 0x40022000,
635 .fsize_addr
= 0x0FF907A0,
636 .otp_base
= 0x0FF90000,
640 .id
= DEVID_STM32WB1XX
,
641 .revs
= stm32wb1xx_revs
,
642 .num_revs
= ARRAY_SIZE(stm32wb1xx_revs
),
643 .device_str
= "STM32WB1x",
644 .max_flash_size_kb
= 320,
646 .flash_regs_base
= 0x58004000,
647 .fsize_addr
= 0x1FFF75E0,
648 .otp_base
= 0x1FFF7000,
652 .id
= DEVID_STM32WB5XX
,
653 .revs
= stm32wb5xx_revs
,
654 .num_revs
= ARRAY_SIZE(stm32wb5xx_revs
),
655 .device_str
= "STM32WB5x",
656 .max_flash_size_kb
= 1024,
658 .flash_regs_base
= 0x58004000,
659 .fsize_addr
= 0x1FFF75E0,
660 .otp_base
= 0x1FFF7000,
664 .id
= DEVID_STM32WB3XX
,
665 .revs
= stm32wb3xx_revs
,
666 .num_revs
= ARRAY_SIZE(stm32wb3xx_revs
),
667 .device_str
= "STM32WB3x",
668 .max_flash_size_kb
= 512,
670 .flash_regs_base
= 0x58004000,
671 .fsize_addr
= 0x1FFF75E0,
672 .otp_base
= 0x1FFF7000,
676 .id
= DEVID_STM32WLE_WL5XX
,
677 .revs
= stm32wle_wl5xx_revs
,
678 .num_revs
= ARRAY_SIZE(stm32wle_wl5xx_revs
),
679 .device_str
= "STM32WLE/WL5x",
680 .max_flash_size_kb
= 256,
682 .flash_regs_base
= 0x58004000,
683 .fsize_addr
= 0x1FFF75E0,
684 .otp_base
= 0x1FFF7000,
689 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
690 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command
)
692 struct stm32l4_flash_bank
*stm32l4_info
;
695 return ERROR_COMMAND_SYNTAX_ERROR
;
697 /* fix-up bank base address: 0 is used for normal flash memory */
699 bank
->base
= STM32_FLASH_BANK_BASE
;
701 stm32l4_info
= calloc(1, sizeof(struct stm32l4_flash_bank
));
703 return ERROR_FAIL
; /* Checkme: What better error to use?*/
704 bank
->driver_priv
= stm32l4_info
;
706 stm32l4_info
->probed
= false;
707 stm32l4_info
->otp_enabled
= false;
708 stm32l4_info
->user_bank_size
= bank
->size
;
713 /* bitmap helper extension */
719 static void bitmap_to_ranges(unsigned long *bitmap
, unsigned int nbits
,
720 struct range
*ranges
, unsigned int *ranges_count
) {
722 bool last_bit
= 0, cur_bit
;
723 for (unsigned int i
= 0; i
< nbits
; i
++) {
724 cur_bit
= test_bit(i
, bitmap
);
726 if (cur_bit
&& !last_bit
) {
728 ranges
[*ranges_count
- 1].start
= i
;
729 ranges
[*ranges_count
- 1].end
= i
;
730 } else if (cur_bit
&& last_bit
) {
731 /* update (increment) the end this range */
732 ranges
[*ranges_count
- 1].end
= i
;
739 static inline int range_print_one(struct range
*range
, char *str
)
741 if (range
->start
== range
->end
)
742 return sprintf(str
, "[%d]", range
->start
);
744 return sprintf(str
, "[%d,%d]", range
->start
, range
->end
);
747 static char *range_print_alloc(struct range
*ranges
, unsigned int ranges_count
)
749 /* each range will be printed like the following: [start,end]
750 * start and end, both are unsigned int, an unsigned int takes 10 characters max
751 * plus 3 characters for '[', ',' and ']'
752 * thus means each range can take maximum 23 character
753 * after each range we add a ' ' as separator and finally we need the '\0'
754 * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
755 char *str
= calloc(1, ranges_count
* (24 * sizeof(char)) + 1);
758 for (unsigned int i
= 0; i
< ranges_count
; i
++) {
759 ptr
+= range_print_one(&(ranges
[i
]), ptr
);
761 if (i
< ranges_count
- 1)
768 /* end of bitmap helper extension */
770 static inline bool stm32l4_is_otp(struct flash_bank
*bank
)
772 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
773 return bank
->base
== stm32l4_info
->part_info
->otp_base
;
776 static int stm32l4_otp_enable(struct flash_bank
*bank
, bool enable
)
778 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
780 if (!stm32l4_is_otp(bank
))
783 char *op_str
= enable
? "enabled" : "disabled";
785 LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
787 stm32l4_info
->otp_enabled
== enable
? "already " : "",
790 stm32l4_info
->otp_enabled
= enable
;
795 static inline bool stm32l4_otp_is_enabled(struct flash_bank
*bank
)
797 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
798 return stm32l4_info
->otp_enabled
;
801 static void stm32l4_sync_rdp_tzen(struct flash_bank
*bank
)
803 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
807 if (stm32l4_info
->part_info
->flags
& F_HAS_TZ
)
808 tzen
= (stm32l4_info
->optr
& FLASH_TZEN
) != 0;
810 uint32_t rdp
= stm32l4_info
->optr
& FLASH_RDP_MASK
;
812 /* for devices without TrustZone:
813 * RDP level 0 and 2 values are to 0xAA and 0xCC
814 * Any other value corresponds to RDP level 1
815 * for devices with TrusZone:
816 * RDP level 0 and 2 values are 0xAA and 0xCC
817 * RDP level 0.5 value is 0x55 only if TZEN = 1
818 * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
821 if (rdp
!= RDP_LEVEL_0
&& rdp
!= RDP_LEVEL_2
) {
822 if (!tzen
|| (tzen
&& rdp
!= RDP_LEVEL_0_5
))
826 stm32l4_info
->tzen
= tzen
;
827 stm32l4_info
->rdp
= rdp
;
830 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
)
832 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
833 return stm32l4_info
->flash_regs_base
+ reg_offset
;
836 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank
*bank
,
837 enum stm32l4_flash_reg_index reg_index
)
839 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
840 return stm32l4_get_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
]);
843 static inline int stm32l4_read_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t *value
)
845 return target_read_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
848 static inline int stm32l4_read_flash_reg_by_index(struct flash_bank
*bank
,
849 enum stm32l4_flash_reg_index reg_index
, uint32_t *value
)
851 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
852 return stm32l4_read_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
], value
);
855 static inline int stm32l4_write_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t value
)
857 return target_write_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
860 static inline int stm32l4_write_flash_reg_by_index(struct flash_bank
*bank
,
861 enum stm32l4_flash_reg_index reg_index
, uint32_t value
)
863 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
864 return stm32l4_write_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
], value
);
867 static int stm32l4_wait_status_busy(struct flash_bank
*bank
, int timeout
)
869 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
871 int retval
= ERROR_OK
;
873 /* wait for busy to clear */
875 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, &status
);
876 if (retval
!= ERROR_OK
)
878 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
879 if ((status
& stm32l4_info
->sr_bsy_mask
) == 0)
881 if (timeout
-- <= 0) {
882 LOG_ERROR("timed out waiting for flash");
888 if (status
& FLASH_WRPERR
) {
889 LOG_ERROR("stm32x device protected");
893 /* Clear but report errors */
894 if (status
& FLASH_ERROR
) {
895 if (retval
== ERROR_OK
)
897 /* If this operation fails, we ignore it and report the original
900 stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, status
& FLASH_ERROR
);
906 /** set all FLASH_SECBB registers to the same value */
907 static int stm32l4_set_secbb(struct flash_bank
*bank
, uint32_t value
)
909 /* This function should be used only with device with TrustZone, do just a security check */
910 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
911 assert(stm32l4_info
->part_info
->flags
& F_HAS_TZ
);
913 /* based on RM0438 Rev6 for STM32L5x devices:
914 * to modify a page block-based security attribution, it is recommended to
915 * 1- check that no flash operation is ongoing on the related page
916 * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
917 * this step is not need in case of JTAG direct access
919 int retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
920 if (retval
!= ERROR_OK
)
923 /* write SECBBxRy registers */
924 LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value
);
926 const uint8_t secbb_regs
[] = {
927 FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
928 FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
932 unsigned int num_secbb_regs
= ARRAY_SIZE(secbb_regs
);
934 /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
935 * then consider only the first half of secbb_regs
937 if (!stm32l4_info
->dual_bank_mode
)
940 for (unsigned int i
= 0; i
< num_secbb_regs
; i
++) {
941 retval
= stm32l4_write_flash_reg(bank
, secbb_regs
[i
], value
);
942 if (retval
!= ERROR_OK
)
949 static inline int stm32l4_get_flash_cr_with_lock_index(struct flash_bank
*bank
)
951 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
952 return (stm32l4_info
->flash_regs
[STM32_FLASH_CR_WLK_INDEX
]) ?
953 STM32_FLASH_CR_WLK_INDEX
: STM32_FLASH_CR_INDEX
;
956 static int stm32l4_unlock_reg(struct flash_bank
*bank
)
958 const uint32_t flash_cr_index
= stm32l4_get_flash_cr_with_lock_index(bank
);
961 /* first check if not already unlocked
962 * otherwise writing on STM32_FLASH_KEYR will fail
964 int retval
= stm32l4_read_flash_reg_by_index(bank
, flash_cr_index
, &ctrl
);
965 if (retval
!= ERROR_OK
)
968 if ((ctrl
& FLASH_LOCK
) == 0)
971 /* unlock flash registers */
972 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_KEYR_INDEX
, KEY1
);
973 if (retval
!= ERROR_OK
)
976 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_KEYR_INDEX
, KEY2
);
977 if (retval
!= ERROR_OK
)
980 retval
= stm32l4_read_flash_reg_by_index(bank
, flash_cr_index
, &ctrl
);
981 if (retval
!= ERROR_OK
)
984 if (ctrl
& FLASH_LOCK
) {
985 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
986 return ERROR_TARGET_FAILURE
;
992 static int stm32l4_unlock_option_reg(struct flash_bank
*bank
)
994 const uint32_t flash_cr_index
= stm32l4_get_flash_cr_with_lock_index(bank
);
997 int retval
= stm32l4_read_flash_reg_by_index(bank
, flash_cr_index
, &ctrl
);
998 if (retval
!= ERROR_OK
)
1001 if ((ctrl
& FLASH_OPTLOCK
) == 0)
1004 /* unlock option registers */
1005 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_OPTKEYR_INDEX
, OPTKEY1
);
1006 if (retval
!= ERROR_OK
)
1009 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_OPTKEYR_INDEX
, OPTKEY2
);
1010 if (retval
!= ERROR_OK
)
1013 retval
= stm32l4_read_flash_reg_by_index(bank
, flash_cr_index
, &ctrl
);
1014 if (retval
!= ERROR_OK
)
1017 if (ctrl
& FLASH_OPTLOCK
) {
1018 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
1019 return ERROR_TARGET_FAILURE
;
1025 static int stm32l4_perform_obl_launch(struct flash_bank
*bank
)
1027 int retval
, retval2
;
1029 retval
= stm32l4_unlock_reg(bank
);
1030 if (retval
!= ERROR_OK
)
1033 retval
= stm32l4_unlock_option_reg(bank
);
1034 if (retval
!= ERROR_OK
)
1037 /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
1038 * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
1039 * "Note: If the read protection is set while the debugger is still
1040 * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
1043 /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */
1044 /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful,
1045 * then just ignore the returned value */
1046 stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_OBL_LAUNCH
);
1048 /* Need to re-probe after change */
1049 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1050 stm32l4_info
->probed
= false;
1053 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
),
1054 FLASH_LOCK
| FLASH_OPTLOCK
);
1056 if (retval
!= ERROR_OK
)
1062 static int stm32l4_write_option(struct flash_bank
*bank
, uint32_t reg_offset
,
1063 uint32_t value
, uint32_t mask
)
1065 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1066 uint32_t optiondata
;
1067 int retval
, retval2
;
1069 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &optiondata
);
1070 if (retval
!= ERROR_OK
)
1073 /* for STM32L5 and similar devices, use always non-secure
1074 * registers for option bytes programming */
1075 const uint32_t *saved_flash_regs
= stm32l4_info
->flash_regs
;
1076 if (stm32l4_info
->part_info
->flags
& F_HAS_L5_FLASH_REGS
)
1077 stm32l4_info
->flash_regs
= stm32l5_ns_flash_regs
;
1079 retval
= stm32l4_unlock_reg(bank
);
1080 if (retval
!= ERROR_OK
)
1083 retval
= stm32l4_unlock_option_reg(bank
);
1084 if (retval
!= ERROR_OK
)
1087 optiondata
= (optiondata
& ~mask
) | (value
& mask
);
1089 retval
= stm32l4_write_flash_reg(bank
, reg_offset
, optiondata
);
1090 if (retval
!= ERROR_OK
)
1093 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_OPTSTRT
);
1094 if (retval
!= ERROR_OK
)
1097 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1100 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
),
1101 FLASH_LOCK
| FLASH_OPTLOCK
);
1102 stm32l4_info
->flash_regs
= saved_flash_regs
;
1104 if (retval
!= ERROR_OK
)
1110 static int stm32l4_get_one_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
,
1111 enum stm32l4_flash_reg_index reg_idx
, int offset
)
1113 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1116 wrpxy
->reg_idx
= reg_idx
;
1117 wrpxy
->offset
= offset
;
1119 ret
= stm32l4_read_flash_reg_by_index(bank
, wrpxy
->reg_idx
, &wrpxy
->value
);
1120 if (ret
!= ERROR_OK
)
1123 wrpxy
->first
= (wrpxy
->value
& stm32l4_info
->wrpxxr_mask
) + wrpxy
->offset
;
1124 wrpxy
->last
= ((wrpxy
->value
>> 16) & stm32l4_info
->wrpxxr_mask
) + wrpxy
->offset
;
1125 wrpxy
->used
= wrpxy
->first
<= wrpxy
->last
;
1130 static int stm32l4_get_all_wrpxy(struct flash_bank
*bank
, enum stm32_bank_id dev_bank_id
,
1131 struct stm32l4_wrp
*wrpxy
, unsigned int *n_wrp
)
1133 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1138 /* for single bank devices there is 2 WRP regions.
1139 * for dual bank devices there is 2 WRP regions per bank,
1140 * if configured as single bank only 2 WRP are usable
1141 * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
1142 * note: this should be revised, if a device will have the SWAP banks option
1145 int wrp2y_sectors_offset
= -1; /* -1 : unused */
1147 /* if bank_id is BANK1 or ALL_BANKS */
1148 if (dev_bank_id
!= STM32_BANK2
) {
1149 /* get FLASH_WRP1AR */
1150 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP1AR_INDEX
, 0);
1151 if (ret
!= ERROR_OK
)
1155 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP1BR_INDEX
, 0);
1156 if (ret
!= ERROR_OK
)
1159 /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
1160 if ((stm32l4_info
->part_info
->flags
& F_USE_ALL_WRPXX
) && !stm32l4_info
->dual_bank_mode
)
1161 wrp2y_sectors_offset
= 0;
1164 /* if bank_id is BANK2 or ALL_BANKS */
1165 if (dev_bank_id
!= STM32_BANK1
&& stm32l4_info
->dual_bank_mode
)
1166 wrp2y_sectors_offset
= stm32l4_info
->bank1_sectors
;
1168 if (wrp2y_sectors_offset
>= 0) {
1170 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP2AR_INDEX
, wrp2y_sectors_offset
);
1171 if (ret
!= ERROR_OK
)
1175 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP2BR_INDEX
, wrp2y_sectors_offset
);
1176 if (ret
!= ERROR_OK
)
1183 static int stm32l4_write_one_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
)
1185 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1187 int wrp_start
= wrpxy
->first
- wrpxy
->offset
;
1188 int wrp_end
= wrpxy
->last
- wrpxy
->offset
;
1190 uint32_t wrp_value
= (wrp_start
& stm32l4_info
->wrpxxr_mask
) | ((wrp_end
& stm32l4_info
->wrpxxr_mask
) << 16);
1192 return stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[wrpxy
->reg_idx
], wrp_value
, 0xffffffff);
1195 static int stm32l4_write_all_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
, unsigned int n_wrp
)
1199 for (unsigned int i
= 0; i
< n_wrp
; i
++) {
1200 ret
= stm32l4_write_one_wrpxy(bank
, &wrpxy
[i
]);
1201 if (ret
!= ERROR_OK
)
1208 static int stm32l4_protect_check(struct flash_bank
*bank
)
1211 struct stm32l4_wrp wrpxy
[4];
1213 int ret
= stm32l4_get_all_wrpxy(bank
, STM32_ALL_BANKS
, wrpxy
, &n_wrp
);
1214 if (ret
!= ERROR_OK
)
1217 /* initialize all sectors as unprotected */
1218 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++)
1219 bank
->sectors
[i
].is_protected
= 0;
1221 /* now check WRPxy and mark the protected sectors */
1222 for (unsigned int i
= 0; i
< n_wrp
; i
++) {
1223 if (wrpxy
[i
].used
) {
1224 for (int s
= wrpxy
[i
].first
; s
<= wrpxy
[i
].last
; s
++)
1225 bank
->sectors
[s
].is_protected
= 1;
1232 static int stm32l4_erase(struct flash_bank
*bank
, unsigned int first
,
1235 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1236 int retval
, retval2
;
1238 assert((first
<= last
) && (last
< bank
->num_sectors
));
1240 if (stm32l4_is_otp(bank
)) {
1241 LOG_ERROR("cannot erase OTP memory");
1242 return ERROR_FLASH_OPER_UNSUPPORTED
;
1245 if (bank
->target
->state
!= TARGET_HALTED
) {
1246 LOG_ERROR("Target not halted");
1247 return ERROR_TARGET_NOT_HALTED
;
1250 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1251 /* set all FLASH pages as secure */
1252 retval
= stm32l4_set_secbb(bank
, FLASH_SECBB_SECURE
);
1253 if (retval
!= ERROR_OK
) {
1254 /* restore all FLASH pages as non-secure */
1255 stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
); /* ignore the return value */
1260 retval
= stm32l4_unlock_reg(bank
);
1261 if (retval
!= ERROR_OK
)
1266 To erase a sector, follow the procedure below:
1267 1. Check that no Flash memory operation is ongoing by
1268 checking the BSY bit in the FLASH_SR register
1269 2. Set the PER bit and select the page and bank
1270 you wish to erase in the FLASH_CR register
1271 3. Set the STRT bit in the FLASH_CR register
1272 4. Wait for the BSY bit to be cleared
1275 for (unsigned int i
= first
; i
<= last
; i
++) {
1276 uint32_t erase_flags
;
1277 erase_flags
= FLASH_PER
| FLASH_STRT
;
1279 if (i
>= stm32l4_info
->bank1_sectors
) {
1281 snb
= i
- stm32l4_info
->bank1_sectors
;
1282 erase_flags
|= snb
<< FLASH_PAGE_SHIFT
| stm32l4_info
->cr_bker_mask
;
1284 erase_flags
|= i
<< FLASH_PAGE_SHIFT
;
1285 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, erase_flags
);
1286 if (retval
!= ERROR_OK
)
1289 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1290 if (retval
!= ERROR_OK
)
1295 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
), FLASH_LOCK
);
1297 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1298 /* restore all FLASH pages as non-secure */
1299 int retval3
= stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
);
1300 if (retval3
!= ERROR_OK
)
1304 if (retval
!= ERROR_OK
)
1310 static int stm32l4_protect_same_bank(struct flash_bank
*bank
, enum stm32_bank_id bank_id
, int set
,
1311 unsigned int first
, unsigned int last
)
1315 /* check if the desired protection is already configured */
1316 for (i
= first
; i
<= last
; i
++) {
1317 if (bank
->sectors
[i
].is_protected
!= set
)
1319 else if (i
== last
) {
1320 LOG_INFO("The specified sectors are already %s", set
? "protected" : "unprotected");
1325 /* all sectors from first to last (or part of them) could have different
1326 * protection other than the requested */
1328 struct stm32l4_wrp wrpxy
[4];
1330 int ret
= stm32l4_get_all_wrpxy(bank
, bank_id
, wrpxy
, &n_wrp
);
1331 if (ret
!= ERROR_OK
)
1334 /* use bitmap and range helpers to optimize the WRP usage */
1335 DECLARE_BITMAP(pages
, bank
->num_sectors
);
1336 bitmap_zero(pages
, bank
->num_sectors
);
1338 for (i
= 0; i
< n_wrp
; i
++) {
1339 if (wrpxy
[i
].used
) {
1340 for (int p
= wrpxy
[i
].first
; p
<= wrpxy
[i
].last
; p
++)
1345 /* we have at most 'n_wrp' WRP areas
1346 * add one range if the user is trying to protect a fifth range */
1347 struct range ranges
[n_wrp
+ 1];
1348 unsigned int ranges_count
= 0;
1350 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
1352 /* pretty-print the currently protected ranges */
1353 if (ranges_count
> 0) {
1354 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
1355 LOG_DEBUG("current protected areas: %s", ranges_str
);
1358 LOG_DEBUG("current protected areas: none");
1360 if (set
) { /* flash protect */
1361 for (i
= first
; i
<= last
; i
++)
1363 } else { /* flash unprotect */
1364 for (i
= first
; i
<= last
; i
++)
1365 clear_bit(i
, pages
);
1368 /* check the ranges_count after the user request */
1369 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
1371 /* pretty-print the requested areas for protection */
1372 if (ranges_count
> 0) {
1373 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
1374 LOG_DEBUG("requested areas for protection: %s", ranges_str
);
1377 LOG_DEBUG("requested areas for protection: none");
1379 if (ranges_count
> n_wrp
) {
1380 LOG_ERROR("cannot set the requested protection "
1381 "(only %u write protection areas are available)" , n_wrp
);
1385 /* re-init all WRPxy as disabled (first > last)*/
1386 for (i
= 0; i
< n_wrp
; i
++) {
1387 wrpxy
[i
].first
= wrpxy
[i
].offset
+ 1;
1388 wrpxy
[i
].last
= wrpxy
[i
].offset
;
1391 /* then configure WRPxy areas */
1392 for (i
= 0; i
< ranges_count
; i
++) {
1393 wrpxy
[i
].first
= ranges
[i
].start
;
1394 wrpxy
[i
].last
= ranges
[i
].end
;
1397 /* finally write WRPxy registers */
1398 return stm32l4_write_all_wrpxy(bank
, wrpxy
, n_wrp
);
1401 static int stm32l4_protect(struct flash_bank
*bank
, int set
, unsigned int first
, unsigned int last
)
1403 struct target
*target
= bank
->target
;
1404 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1406 if (stm32l4_is_otp(bank
)) {
1407 LOG_ERROR("cannot protect/unprotect OTP memory");
1408 return ERROR_FLASH_OPER_UNSUPPORTED
;
1411 if (target
->state
!= TARGET_HALTED
) {
1412 LOG_ERROR("Target not halted");
1413 return ERROR_TARGET_NOT_HALTED
;
1416 /* refresh the sectors' protection */
1417 int ret
= stm32l4_protect_check(bank
);
1418 if (ret
!= ERROR_OK
)
1421 /* the requested sectors could be located into bank1 and/or bank2 */
1422 if (last
< stm32l4_info
->bank1_sectors
) {
1423 return stm32l4_protect_same_bank(bank
, STM32_BANK1
, set
, first
, last
);
1424 } else if (first
>= stm32l4_info
->bank1_sectors
) {
1425 return stm32l4_protect_same_bank(bank
, STM32_BANK2
, set
, first
, last
);
1427 ret
= stm32l4_protect_same_bank(bank
, STM32_BANK1
, set
, first
, stm32l4_info
->bank1_sectors
- 1);
1428 if (ret
!= ERROR_OK
)
1431 return stm32l4_protect_same_bank(bank
, STM32_BANK2
, set
, stm32l4_info
->bank1_sectors
, last
);
1435 /* count is the size divided by stm32l4_info->data_width */
1436 static int stm32l4_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
1437 uint32_t offset
, uint32_t count
)
1439 struct target
*target
= bank
->target
;
1440 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1441 struct working_area
*write_algorithm
;
1442 struct working_area
*source
;
1443 uint32_t address
= bank
->base
+ offset
;
1444 struct reg_param reg_params
[5];
1445 struct armv7m_algorithm armv7m_info
;
1446 int retval
= ERROR_OK
;
1448 static const uint8_t stm32l4_flash_write_code
[] = {
1449 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1452 if (target_alloc_working_area(target
, sizeof(stm32l4_flash_write_code
),
1453 &write_algorithm
) != ERROR_OK
) {
1454 LOG_WARNING("no working area available, can't do block memory writes");
1455 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1458 retval
= target_write_buffer(target
, write_algorithm
->address
,
1459 sizeof(stm32l4_flash_write_code
),
1460 stm32l4_flash_write_code
);
1461 if (retval
!= ERROR_OK
) {
1462 target_free_working_area(target
, write_algorithm
);
1466 /* data_width should be multiple of double-word */
1467 assert(stm32l4_info
->data_width
% 8 == 0);
1468 const size_t extra_size
= sizeof(struct stm32l4_work_area
);
1469 uint32_t buffer_size
= target_get_working_area_avail(target
) - extra_size
;
1470 /* buffer_size should be multiple of stm32l4_info->data_width */
1471 buffer_size
&= ~(stm32l4_info
->data_width
- 1);
1473 if (buffer_size
< 256) {
1474 LOG_WARNING("large enough working area not available, can't do block memory writes");
1475 target_free_working_area(target
, write_algorithm
);
1476 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1477 } else if (buffer_size
> 16384) {
1478 /* probably won't benefit from more than 16k ... */
1479 buffer_size
= 16384;
1482 if (target_alloc_working_area_try(target
, buffer_size
+ extra_size
, &source
) != ERROR_OK
) {
1483 LOG_ERROR("allocating working area failed");
1484 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1487 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
1488 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
1490 /* contrib/loaders/flash/stm32/stm32l4x.c:write() arguments */
1491 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* stm32l4_work_area ptr , status (out) */
1492 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
1493 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
1494 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count (of stm32l4_info->data_width) */
1496 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1497 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
1498 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
1499 buf_set_u32(reg_params
[3].value
, 0, 32, count
);
1501 /* write algo stack pointer */
1502 init_reg_param(®_params
[4], "sp", 32, PARAM_OUT
);
1503 buf_set_u32(reg_params
[4].value
, 0, 32, source
->address
+
1504 offsetof(struct stm32l4_work_area
, stack
) + LDR_STACK_SIZE
);
1506 struct stm32l4_loader_params loader_extra_params
;
1508 target_buffer_set_u32(target
, (uint8_t *) &loader_extra_params
.flash_sr_addr
,
1509 stm32l4_get_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
));
1510 target_buffer_set_u32(target
, (uint8_t *) &loader_extra_params
.flash_cr_addr
,
1511 stm32l4_get_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
));
1512 target_buffer_set_u32(target
, (uint8_t *) &loader_extra_params
.flash_word_size
,
1513 stm32l4_info
->data_width
);
1514 target_buffer_set_u32(target
, (uint8_t *) &loader_extra_params
.flash_sr_bsy_mask
,
1515 stm32l4_info
->sr_bsy_mask
);
1517 retval
= target_write_buffer(target
, source
->address
, sizeof(loader_extra_params
),
1518 (uint8_t *) &loader_extra_params
);
1519 if (retval
!= ERROR_OK
)
1522 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, stm32l4_info
->data_width
,
1524 ARRAY_SIZE(reg_params
), reg_params
,
1525 source
->address
+ offsetof(struct stm32l4_work_area
, fifo
),
1526 source
->size
- offsetof(struct stm32l4_work_area
, fifo
),
1527 write_algorithm
->address
, 0,
1530 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
1531 LOG_ERROR("error executing stm32l4 flash write algorithm");
1534 stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, &error
);
1535 error
&= FLASH_ERROR
;
1537 if (error
& FLASH_WRPERR
)
1538 LOG_ERROR("flash memory write protected");
1541 LOG_ERROR("flash write failed = %08" PRIx32
, error
);
1542 /* Clear but report errors */
1543 stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, error
);
1544 retval
= ERROR_FAIL
;
1548 target_free_working_area(target
, source
);
1549 target_free_working_area(target
, write_algorithm
);
1551 destroy_reg_param(®_params
[0]);
1552 destroy_reg_param(®_params
[1]);
1553 destroy_reg_param(®_params
[2]);
1554 destroy_reg_param(®_params
[3]);
1555 destroy_reg_param(®_params
[4]);
1560 /* count is the size divided by stm32l4_info->data_width */
1561 static int stm32l4_write_block_without_loader(struct flash_bank
*bank
, const uint8_t *buffer
,
1562 uint32_t offset
, uint32_t count
)
1564 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1565 struct target
*target
= bank
->target
;
1566 uint32_t address
= bank
->base
+ offset
;
1567 int retval
= ERROR_OK
;
1569 /* wait for BSY bit */
1570 retval
= stm32l4_wait_status_busy(bank
, FLASH_WRITE_TIMEOUT
);
1571 if (retval
!= ERROR_OK
)
1574 /* set PG in FLASH_CR */
1575 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_PG
);
1576 if (retval
!= ERROR_OK
)
1580 /* write directly to flash memory */
1581 const uint8_t *src
= buffer
;
1582 const uint32_t data_width_in_words
= stm32l4_info
->data_width
/ 4;
1584 retval
= target_write_memory(target
, address
, 4, data_width_in_words
, src
);
1585 if (retval
!= ERROR_OK
)
1588 /* wait for BSY bit */
1589 retval
= stm32l4_wait_status_busy(bank
, FLASH_WRITE_TIMEOUT
);
1590 if (retval
!= ERROR_OK
)
1593 src
+= stm32l4_info
->data_width
;
1594 address
+= stm32l4_info
->data_width
;
1597 /* reset PG in FLASH_CR */
1598 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, 0);
1599 if (retval
!= ERROR_OK
)
1605 static int stm32l4_write(struct flash_bank
*bank
, const uint8_t *buffer
,
1606 uint32_t offset
, uint32_t count
)
1608 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1609 int retval
= ERROR_OK
, retval2
;
1611 if (stm32l4_is_otp(bank
) && !stm32l4_otp_is_enabled(bank
)) {
1612 LOG_ERROR("OTP memory is disabled for write commands");
1616 if (bank
->target
->state
!= TARGET_HALTED
) {
1617 LOG_ERROR("Target not halted");
1618 return ERROR_TARGET_NOT_HALTED
;
1621 /* ensure that stm32l4_info->data_width is 'at least' a multiple of dword */
1622 assert(stm32l4_info
->data_width
% 8 == 0);
1624 /* The flash write must be aligned to the 'stm32l4_info->data_width' boundary.
1625 * The flash infrastructure ensures it, do just a security check */
1626 assert(offset
% stm32l4_info
->data_width
== 0);
1627 assert(count
% stm32l4_info
->data_width
== 0);
1629 /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1630 * data to be written does not go into a gap:
1631 * suppose buffer is fully contained in bank from sector 0 to sector
1632 * num->sectors - 1 and sectors are ordered according to offset
1634 struct flash_sector
*head
= &bank
->sectors
[0];
1635 struct flash_sector
*tail
= &bank
->sectors
[bank
->num_sectors
- 1];
1637 while ((head
< tail
) && (offset
>= (head
+ 1)->offset
)) {
1638 /* buffer does not intersect head nor gap behind head */
1642 while ((head
< tail
) && (offset
+ count
<= (tail
- 1)->offset
+ (tail
- 1)->size
)) {
1643 /* buffer does not intersect tail nor gap before tail */
1647 LOG_DEBUG("data: 0x%08" PRIx32
" - 0x%08" PRIx32
", sectors: 0x%08" PRIx32
" - 0x%08" PRIx32
,
1648 offset
, offset
+ count
- 1, head
->offset
, tail
->offset
+ tail
->size
- 1);
1650 /* Now check that there is no gap from head to tail, this should work
1651 * even for multiple or non-symmetric gaps
1653 while (head
< tail
) {
1654 if (head
->offset
+ head
->size
!= (head
+ 1)->offset
) {
1655 LOG_ERROR("write into gap from " TARGET_ADDR_FMT
" to " TARGET_ADDR_FMT
,
1656 bank
->base
+ head
->offset
+ head
->size
,
1657 bank
->base
+ (head
+ 1)->offset
- 1);
1658 retval
= ERROR_FLASH_DST_OUT_OF_BANK
;
1663 if (retval
!= ERROR_OK
)
1666 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1667 /* set all FLASH pages as secure */
1668 retval
= stm32l4_set_secbb(bank
, FLASH_SECBB_SECURE
);
1669 if (retval
!= ERROR_OK
) {
1670 /* restore all FLASH pages as non-secure */
1671 stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
); /* ignore the return value */
1676 retval
= stm32l4_unlock_reg(bank
);
1677 if (retval
!= ERROR_OK
)
1681 /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
1682 * the debug is possible only in non-secure state.
1683 * Thus means the flashloader will run in non-secure mode,
1684 * and the workarea need to be in non-secure RAM */
1685 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0_5
))
1686 LOG_WARNING("RDP = 0x55, the work-area should be in non-secure RAM (check SAU partitioning)");
1688 /* first try to write using the loader, for better performance */
1689 retval
= stm32l4_write_block(bank
, buffer
, offset
,
1690 count
/ stm32l4_info
->data_width
);
1692 /* if resources are not available write without a loader */
1693 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
1694 LOG_WARNING("falling back to programming without a flash loader (slower)");
1695 retval
= stm32l4_write_block_without_loader(bank
, buffer
, offset
,
1696 count
/ stm32l4_info
->data_width
);
1700 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
), FLASH_LOCK
);
1702 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1703 /* restore all FLASH pages as non-secure */
1704 int retval3
= stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
);
1705 if (retval3
!= ERROR_OK
)
1709 if (retval
!= ERROR_OK
) {
1710 LOG_ERROR("block write failed");
1716 static int stm32l4_read_idcode(struct flash_bank
*bank
, uint32_t *id
)
1718 int retval
= ERROR_OK
;
1719 struct target
*target
= bank
->target
;
1721 /* try reading possible IDCODE registers, in the following order */
1722 uint32_t dbgmcu_idcode
[] = {DBGMCU_IDCODE_L4_G4
, DBGMCU_IDCODE_G0
, DBGMCU_IDCODE_L5
};
1724 for (unsigned int i
= 0; i
< ARRAY_SIZE(dbgmcu_idcode
); i
++) {
1725 retval
= target_read_u32(target
, dbgmcu_idcode
[i
], id
);
1726 if ((retval
== ERROR_OK
) && ((*id
& 0xfff) != 0) && ((*id
& 0xfff) != 0xfff))
1730 /* Workaround for STM32WL5x devices:
1731 * DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
1732 * to solve this read the UID64 (IEEE 64-bit unique device ID register) */
1734 struct armv7m_common
*armv7m
= target_to_armv7m_safe(target
);
1736 LOG_ERROR("Flash requires Cortex-M target");
1737 return ERROR_TARGET_INVALID
;
1740 /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
1741 * Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */
1742 if (cortex_m_get_impl_part(target
) == CORTEX_M0P_PARTNO
&&
1743 armv7m
->debug_ap
&& armv7m
->debug_ap
->ap_num
== 1) {
1746 /* UID64 is contains
1747 * - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
1748 * - Bits 31:08 : STID (company ID) = 0x0080E1
1749 * - Bits 07:00 : DEVID (device ID) = 0x15
1751 * read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
1753 retval
= target_read_u32(target
, UID64_IDS
, &uid64_ids
);
1754 if (retval
== ERROR_OK
&& uid64_ids
== UID64_IDS_STM32WL
) {
1755 /* force the DEV_ID to DEVID_STM32WLE_WL5XX and the REV_ID to unknown */
1756 *id
= DEVID_STM32WLE_WL5XX
;
1761 LOG_ERROR("can't get the device id");
1762 return (retval
== ERROR_OK
) ? ERROR_FAIL
: retval
;
1765 static const char *get_stm32l4_rev_str(struct flash_bank
*bank
)
1767 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1768 const struct stm32l4_part_info
*part_info
= stm32l4_info
->part_info
;
1771 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
1772 for (unsigned int i
= 0; i
< part_info
->num_revs
; i
++) {
1773 if (rev_id
== part_info
->revs
[i
].rev
)
1774 return part_info
->revs
[i
].str
;
1779 static const char *get_stm32l4_bank_type_str(struct flash_bank
*bank
)
1781 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1782 assert(stm32l4_info
->part_info
);
1783 return stm32l4_is_otp(bank
) ? "OTP" :
1784 stm32l4_info
->dual_bank_mode
? "Flash dual" :
1788 static int stm32l4_probe(struct flash_bank
*bank
)
1790 struct target
*target
= bank
->target
;
1791 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1792 const struct stm32l4_part_info
*part_info
;
1793 uint16_t flash_size_kb
= 0xffff;
1795 if (!target_was_examined(target
)) {
1796 LOG_ERROR("Target not examined yet");
1797 return ERROR_TARGET_NOT_EXAMINED
;
1800 struct armv7m_common
*armv7m
= target_to_armv7m_safe(target
);
1802 LOG_ERROR("Flash requires Cortex-M target");
1803 return ERROR_TARGET_INVALID
;
1806 stm32l4_info
->probed
= false;
1808 /* read stm32 device id registers */
1809 int retval
= stm32l4_read_idcode(bank
, &stm32l4_info
->idcode
);
1810 if (retval
!= ERROR_OK
)
1813 const uint32_t device_id
= stm32l4_info
->idcode
& 0xFFF;
1815 for (unsigned int n
= 0; n
< ARRAY_SIZE(stm32l4_parts
); n
++) {
1816 if (device_id
== stm32l4_parts
[n
].id
) {
1817 stm32l4_info
->part_info
= &stm32l4_parts
[n
];
1822 if (!stm32l4_info
->part_info
) {
1823 LOG_WARNING("Cannot identify target as an %s family device.", device_families
);
1827 part_info
= stm32l4_info
->part_info
;
1828 const char *rev_str
= get_stm32l4_rev_str(bank
);
1829 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
1831 LOG_INFO("device idcode = 0x%08" PRIx32
" (%s - Rev %s : 0x%04x)",
1832 stm32l4_info
->idcode
, part_info
->device_str
, rev_str
, rev_id
);
1834 stm32l4_info
->flash_regs_base
= stm32l4_info
->part_info
->flash_regs_base
;
1835 stm32l4_info
->data_width
= (part_info
->flags
& F_QUAD_WORD_PROG
) ? 16 : 8;
1836 stm32l4_info
->cr_bker_mask
= FLASH_BKER
;
1837 stm32l4_info
->sr_bsy_mask
= FLASH_BSY
;
1839 /* Set flash write alignment boundaries.
1840 * Ask the flash infrastructure to ensure required alignment */
1841 bank
->write_start_alignment
= stm32l4_info
->data_width
;
1842 bank
->write_end_alignment
= stm32l4_info
->data_width
;
1844 /* Initialize the flash registers layout */
1845 if (part_info
->flags
& F_HAS_L5_FLASH_REGS
)
1846 stm32l4_info
->flash_regs
= stm32l5_ns_flash_regs
;
1848 stm32l4_info
->flash_regs
= stm32l4_flash_regs
;
1850 /* read flash option register */
1851 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_OPTR_INDEX
, &stm32l4_info
->optr
);
1852 if (retval
!= ERROR_OK
)
1855 stm32l4_sync_rdp_tzen(bank
);
1857 /* for devices with TrustZone, use flash secure registers when TZEN=1 and RDP is LEVEL_0 */
1858 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1859 if (part_info
->flags
& F_HAS_L5_FLASH_REGS
) {
1860 stm32l4_info
->flash_regs_base
|= STM32L5_REGS_SEC_OFFSET
;
1861 stm32l4_info
->flash_regs
= stm32l5_s_flash_regs
;
1863 LOG_ERROR("BUG: device supported incomplete");
1864 return ERROR_NOT_IMPLEMENTED
;
1868 if (part_info
->flags
& F_HAS_TZ
)
1869 LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1871 stm32l4_info
->tzen
? "enabled" : "disabled");
1873 LOG_INFO("RDP level %s (0x%02X)",
1874 stm32l4_info
->rdp
== RDP_LEVEL_0
? "0" : stm32l4_info
->rdp
== RDP_LEVEL_0_5
? "0.5" : "1",
1877 if (stm32l4_is_otp(bank
)) {
1878 bank
->size
= part_info
->otp_size
;
1880 LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT
, bank
->size
, bank
->base
);
1882 /* OTP memory is considered as one sector */
1883 free(bank
->sectors
);
1884 bank
->num_sectors
= 1;
1885 bank
->sectors
= alloc_block_array(0, part_info
->otp_size
, 1);
1887 if (!bank
->sectors
) {
1888 LOG_ERROR("failed to allocate bank sectors");
1892 stm32l4_info
->probed
= true;
1894 } else if (bank
->base
!= STM32_FLASH_BANK_BASE
&& bank
->base
!= STM32_FLASH_S_BANK_BASE
) {
1895 LOG_ERROR("invalid bank base address");
1899 /* get flash size from target. */
1900 retval
= target_read_u16(target
, part_info
->fsize_addr
, &flash_size_kb
);
1902 /* failed reading flash size or flash size invalid (early silicon),
1903 * default to max target family */
1904 if (retval
!= ERROR_OK
|| flash_size_kb
== 0xffff || flash_size_kb
== 0
1905 || flash_size_kb
> part_info
->max_flash_size_kb
) {
1906 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
1907 part_info
->max_flash_size_kb
);
1908 flash_size_kb
= part_info
->max_flash_size_kb
;
1911 /* if the user sets the size manually then ignore the probed value
1912 * this allows us to work around devices that have a invalid flash size register value */
1913 if (stm32l4_info
->user_bank_size
) {
1914 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
1915 flash_size_kb
= stm32l4_info
->user_bank_size
/ 1024;
1918 LOG_INFO("flash size = %d KiB", flash_size_kb
);
1920 /* did we assign a flash size? */
1921 assert((flash_size_kb
!= 0xffff) && flash_size_kb
);
1923 const bool is_max_flash_size
= flash_size_kb
== stm32l4_info
->part_info
->max_flash_size_kb
;
1925 stm32l4_info
->bank1_sectors
= 0;
1926 stm32l4_info
->hole_sectors
= 0;
1929 int page_size_kb
= 0;
1931 stm32l4_info
->dual_bank_mode
= false;
1933 switch (device_id
) {
1934 case DEVID_STM32L47_L48XX
:
1935 case DEVID_STM32L49_L4AXX
:
1936 /* if flash size is max (1M) the device is always dual bank
1937 * STM32L47/L48xx: has variants with 512K
1938 * STM32L49/L4Axx: has variants with 512 and 256
1939 * for these variants:
1940 * if DUAL_BANK = 0 -> single bank
1941 * else -> dual bank without gap
1942 * note: the page size is invariant
1945 num_pages
= flash_size_kb
/ page_size_kb
;
1946 stm32l4_info
->bank1_sectors
= num_pages
;
1948 /* check DUAL_BANK option bit if the flash is less than 1M */
1949 if (is_max_flash_size
|| (stm32l4_info
->optr
& FLASH_L4_DUAL_BANK
)) {
1950 stm32l4_info
->dual_bank_mode
= true;
1951 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1954 case DEVID_STM32L43_L44XX
:
1955 case DEVID_STM32C01XX
:
1956 case DEVID_STM32C03XX
:
1957 case DEVID_STM32G05_G06XX
:
1958 case DEVID_STM32G07_G08XX
:
1959 case DEVID_STM32L45_L46XX
:
1960 case DEVID_STM32L41_L42XX
:
1961 case DEVID_STM32G03_G04XX
:
1962 case DEVID_STM32G43_G44XX
:
1963 case DEVID_STM32G49_G4AXX
:
1964 case DEVID_STM32WB1XX
:
1965 /* single bank flash */
1967 num_pages
= flash_size_kb
/ page_size_kb
;
1968 stm32l4_info
->bank1_sectors
= num_pages
;
1970 case DEVID_STM32G0B_G0CXX
:
1971 /* single/dual bank depending on DUAL_BANK option bit */
1973 num_pages
= flash_size_kb
/ page_size_kb
;
1974 stm32l4_info
->bank1_sectors
= num_pages
;
1975 stm32l4_info
->cr_bker_mask
= FLASH_BKER_G0
;
1977 /* check DUAL_BANK bit */
1978 if (stm32l4_info
->optr
& FLASH_G0_DUAL_BANK
) {
1979 stm32l4_info
->sr_bsy_mask
= FLASH_BSY
| FLASH_BSY2
;
1980 stm32l4_info
->dual_bank_mode
= true;
1981 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1984 case DEVID_STM32G47_G48XX
:
1985 /* STM32G47/8 can be single/dual bank:
1986 * if DUAL_BANK = 0 -> single bank
1987 * else -> dual bank WITH gap
1990 num_pages
= flash_size_kb
/ page_size_kb
;
1991 stm32l4_info
->bank1_sectors
= num_pages
;
1992 if (stm32l4_info
->optr
& FLASH_G4_DUAL_BANK
) {
1993 stm32l4_info
->dual_bank_mode
= true;
1995 num_pages
= flash_size_kb
/ page_size_kb
;
1996 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1998 /* for devices with trimmed flash, there is a gap between both banks */
1999 stm32l4_info
->hole_sectors
=
2000 (part_info
->max_flash_size_kb
- flash_size_kb
) / (2 * page_size_kb
);
2003 case DEVID_STM32L4R_L4SXX
:
2004 case DEVID_STM32L4P_L4QXX
:
2005 /* STM32L4R/S can be single/dual bank:
2006 * if size = 2M check DBANK bit
2007 * if size = 1M check DB1M bit
2008 * STM32L4P/Q can be single/dual bank
2009 * if size = 1M check DBANK bit
2010 * if size = 512K check DB512K bit (same as DB1M bit)
2013 num_pages
= flash_size_kb
/ page_size_kb
;
2014 stm32l4_info
->bank1_sectors
= num_pages
;
2015 if ((is_max_flash_size
&& (stm32l4_info
->optr
& FLASH_L4R_DBANK
)) ||
2016 (!is_max_flash_size
&& (stm32l4_info
->optr
& FLASH_LRR_DB1M
))) {
2017 stm32l4_info
->dual_bank_mode
= true;
2019 num_pages
= flash_size_kb
/ page_size_kb
;
2020 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
2023 case DEVID_STM32L55_L56XX
:
2024 /* STM32L55/L56xx can be single/dual bank:
2025 * if size = 512K check DBANK bit
2026 * if size = 256K check DB256K bit
2028 * default page size is 4kb, if DBANK = 1, the page size is 2kb.
2031 page_size_kb
= (stm32l4_info
->optr
& FLASH_L5_DBANK
) ? 2 : 4;
2032 num_pages
= flash_size_kb
/ page_size_kb
;
2033 stm32l4_info
->bank1_sectors
= num_pages
;
2035 if ((is_max_flash_size
&& (stm32l4_info
->optr
& FLASH_L5_DBANK
)) ||
2036 (!is_max_flash_size
&& (stm32l4_info
->optr
& FLASH_L5_DB256
))) {
2037 stm32l4_info
->dual_bank_mode
= true;
2038 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
2041 case DEVID_STM32U53_U54XX
:
2042 case DEVID_STM32U57_U58XX
:
2043 case DEVID_STM32U59_U5AXX
:
2044 /* according to RM0456 Rev 4, Chapter 7.3.1 and 7.9.13
2045 * U53x/U54x have 512K max flash size:
2046 * 512K variants are always in DUAL BANK mode
2047 * 256K and 128K variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2048 * U57x/U58x have 2M max flash size:
2049 * 2M variants are always in DUAL BANK mode
2050 * 1M variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2051 * U59x/U5Ax have 4M max flash size:
2052 * 4M variants are always in DUAL BANK mode
2053 * 2M variants can be in DUAL BANK mode if FLASH_OPTR:DUALBANK is set
2054 * Note: flash banks are always contiguous
2058 num_pages
= flash_size_kb
/ page_size_kb
;
2059 stm32l4_info
->bank1_sectors
= num_pages
;
2060 if (is_max_flash_size
|| (stm32l4_info
->optr
& FLASH_U5_DUALBANK
)) {
2061 stm32l4_info
->dual_bank_mode
= true;
2062 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
2065 case DEVID_STM32WBA5X
:
2066 /* single bank flash */
2068 num_pages
= flash_size_kb
/ page_size_kb
;
2069 stm32l4_info
->bank1_sectors
= num_pages
;
2071 case DEVID_STM32WB5XX
:
2072 case DEVID_STM32WB3XX
:
2073 /* single bank flash */
2075 num_pages
= flash_size_kb
/ page_size_kb
;
2076 stm32l4_info
->bank1_sectors
= num_pages
;
2078 case DEVID_STM32WLE_WL5XX
:
2079 /* single bank flash */
2081 num_pages
= flash_size_kb
/ page_size_kb
;
2082 stm32l4_info
->bank1_sectors
= num_pages
;
2084 /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
2085 * Using HLA adapters armv7m->debug_ap is null, and checking ap_num triggers a segfault */
2086 if (armv7m
->debug_ap
&& armv7m
->debug_ap
->ap_num
== 1)
2087 stm32l4_info
->flash_regs
= stm32wl_cpu2_flash_regs
;
2090 LOG_ERROR("unsupported device");
2094 /* ensure that at least there is 1 flash sector / page */
2095 if (num_pages
== 0) {
2096 if (stm32l4_info
->user_bank_size
)
2097 LOG_ERROR("The specified flash size is less than page size");
2099 LOG_ERROR("Flash pages count cannot be zero");
2103 LOG_INFO("flash mode : %s-bank", stm32l4_info
->dual_bank_mode
? "dual" : "single");
2105 const int gap_size_kb
= stm32l4_info
->hole_sectors
* page_size_kb
;
2107 if (gap_size_kb
!= 0) {
2108 LOG_INFO("gap detected from 0x%08x to 0x%08x",
2109 STM32_FLASH_BANK_BASE
+ stm32l4_info
->bank1_sectors
2110 * page_size_kb
* 1024,
2111 STM32_FLASH_BANK_BASE
+ (stm32l4_info
->bank1_sectors
2112 * page_size_kb
+ gap_size_kb
) * 1024 - 1);
2115 /* number of significant bits in WRPxxR differs per device,
2116 * always right adjusted, on some devices non-implemented
2117 * bits read as '0', on others as '1' ...
2118 * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
2121 /* use *max_flash_size* instead of actual size as the trimmed versions
2122 * certainly use the same number of bits
2124 uint32_t max_pages
= stm32l4_info
->part_info
->max_flash_size_kb
/ page_size_kb
;
2126 /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
2127 stm32l4_info
->wrpxxr_mask
= ((max_pages
>> (stm32l4_info
->dual_bank_mode
? 1 : 0)) - 1);
2128 assert((stm32l4_info
->wrpxxr_mask
& 0xFFFF0000) == 0);
2129 LOG_DEBUG("WRPxxR mask 0x%04" PRIx16
, (uint16_t)stm32l4_info
->wrpxxr_mask
);
2131 free(bank
->sectors
);
2133 bank
->size
= (flash_size_kb
+ gap_size_kb
) * 1024;
2134 bank
->num_sectors
= num_pages
;
2135 bank
->sectors
= malloc(sizeof(struct flash_sector
) * bank
->num_sectors
);
2136 if (!bank
->sectors
) {
2137 LOG_ERROR("failed to allocate bank sectors");
2141 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
2142 bank
->sectors
[i
].offset
= i
* page_size_kb
* 1024;
2143 /* in dual bank configuration, if there is a gap between banks
2144 * we fix up the sector offset to consider this gap */
2145 if (i
>= stm32l4_info
->bank1_sectors
&& stm32l4_info
->hole_sectors
)
2146 bank
->sectors
[i
].offset
+= gap_size_kb
* 1024;
2147 bank
->sectors
[i
].size
= page_size_kb
* 1024;
2148 bank
->sectors
[i
].is_erased
= -1;
2149 bank
->sectors
[i
].is_protected
= 1;
2152 stm32l4_info
->probed
= true;
2156 static int stm32l4_auto_probe(struct flash_bank
*bank
)
2158 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2159 if (stm32l4_info
->probed
) {
2162 /* save flash_regs_base */
2163 uint32_t saved_flash_regs_base
= stm32l4_info
->flash_regs_base
;
2165 /* for devices with TrustZone, use NS flash registers to read OPTR */
2166 if (stm32l4_info
->part_info
->flags
& F_HAS_L5_FLASH_REGS
)
2167 stm32l4_info
->flash_regs_base
&= ~STM32L5_REGS_SEC_OFFSET
;
2169 /* read flash option register and re-probe if optr value is changed */
2170 int retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_OPTR_INDEX
, &optr_cur
);
2172 /* restore saved flash_regs_base */
2173 stm32l4_info
->flash_regs_base
= saved_flash_regs_base
;
2175 if (retval
!= ERROR_OK
)
2178 if (stm32l4_info
->optr
== optr_cur
)
2182 return stm32l4_probe(bank
);
2185 static int get_stm32l4_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
2187 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2188 const struct stm32l4_part_info
*part_info
= stm32l4_info
->part_info
;
2191 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
2192 command_print_sameline(cmd
, "%s - Rev %s : 0x%04x", part_info
->device_str
,
2193 get_stm32l4_rev_str(bank
), rev_id
);
2194 if (stm32l4_info
->probed
)
2195 command_print_sameline(cmd
, " - %s-bank", get_stm32l4_bank_type_str(bank
));
2197 command_print_sameline(cmd
, "Cannot identify target as an %s device", device_families
);
2203 static int stm32l4_mass_erase(struct flash_bank
*bank
)
2205 int retval
, retval2
;
2206 struct target
*target
= bank
->target
;
2207 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2209 if (stm32l4_is_otp(bank
)) {
2210 LOG_ERROR("cannot erase OTP memory");
2211 return ERROR_FLASH_OPER_UNSUPPORTED
;
2214 uint32_t action
= FLASH_MER1
;
2216 if (stm32l4_info
->part_info
->flags
& F_HAS_DUAL_BANK
)
2217 action
|= FLASH_MER2
;
2219 if (target
->state
!= TARGET_HALTED
) {
2220 LOG_ERROR("Target not halted");
2221 return ERROR_TARGET_NOT_HALTED
;
2224 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
2225 /* set all FLASH pages as secure */
2226 retval
= stm32l4_set_secbb(bank
, FLASH_SECBB_SECURE
);
2227 if (retval
!= ERROR_OK
) {
2228 /* restore all FLASH pages as non-secure */
2229 stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
); /* ignore the return value */
2234 retval
= stm32l4_unlock_reg(bank
);
2235 if (retval
!= ERROR_OK
)
2238 /* mass erase flash memory */
2239 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
/ 10);
2240 if (retval
!= ERROR_OK
)
2243 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, action
);
2244 if (retval
!= ERROR_OK
)
2247 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, action
| FLASH_STRT
);
2248 if (retval
!= ERROR_OK
)
2251 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
2254 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
), FLASH_LOCK
);
2256 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
2257 /* restore all FLASH pages as non-secure */
2258 int retval3
= stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
);
2259 if (retval3
!= ERROR_OK
)
2263 if (retval
!= ERROR_OK
)
2269 COMMAND_HANDLER(stm32l4_handle_mass_erase_command
)
2272 return ERROR_COMMAND_SYNTAX_ERROR
;
2274 struct flash_bank
*bank
;
2275 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2276 if (retval
!= ERROR_OK
)
2279 retval
= stm32l4_mass_erase(bank
);
2280 if (retval
== ERROR_OK
)
2281 command_print(CMD
, "stm32l4x mass erase complete");
2283 command_print(CMD
, "stm32l4x mass erase failed");
2288 COMMAND_HANDLER(stm32l4_handle_option_read_command
)
2291 return ERROR_COMMAND_SYNTAX_ERROR
;
2293 struct flash_bank
*bank
;
2294 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2295 if (retval
!= ERROR_OK
)
2298 uint32_t reg_offset
, reg_addr
;
2301 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg_offset
);
2302 reg_addr
= stm32l4_get_flash_reg(bank
, reg_offset
);
2304 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &value
);
2305 if (retval
!= ERROR_OK
)
2308 command_print(CMD
, "Option Register: <0x%" PRIx32
"> = 0x%" PRIx32
"", reg_addr
, value
);
2313 COMMAND_HANDLER(stm32l4_handle_option_write_command
)
2315 if (CMD_ARGC
!= 3 && CMD_ARGC
!= 4)
2316 return ERROR_COMMAND_SYNTAX_ERROR
;
2318 struct flash_bank
*bank
;
2319 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2320 if (retval
!= ERROR_OK
)
2323 uint32_t reg_offset
;
2325 uint32_t mask
= 0xFFFFFFFF;
2327 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg_offset
);
2328 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
2331 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[3], mask
);
2333 command_print(CMD
, "%s Option written.\n"
2334 "INFO: a reset or power cycle is required "
2335 "for the new settings to take effect.", bank
->driver
->name
);
2337 retval
= stm32l4_write_option(bank
, reg_offset
, value
, mask
);
2341 COMMAND_HANDLER(stm32l4_handle_trustzone_command
)
2343 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
2344 return ERROR_COMMAND_SYNTAX_ERROR
;
2346 struct flash_bank
*bank
;
2347 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2348 if (retval
!= ERROR_OK
)
2351 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2352 if (!(stm32l4_info
->part_info
->flags
& F_HAS_TZ
)) {
2353 LOG_ERROR("This device does not have a TrustZone");
2357 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_OPTR_INDEX
, &stm32l4_info
->optr
);
2358 if (retval
!= ERROR_OK
)
2361 stm32l4_sync_rdp_tzen(bank
);
2363 if (CMD_ARGC
== 1) {
2364 /* only display the TZEN value */
2365 LOG_INFO("Global TrustZone Security is %s", stm32l4_info
->tzen
? "enabled" : "disabled");
2370 COMMAND_PARSE_ENABLE(CMD_ARGV
[1], new_tzen
);
2372 if (new_tzen
== stm32l4_info
->tzen
) {
2373 LOG_INFO("The requested TZEN is already programmed");
2378 if (stm32l4_info
->rdp
!= RDP_LEVEL_0
) {
2379 LOG_ERROR("TZEN can be set only when RDP level is 0");
2382 retval
= stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2383 FLASH_TZEN
, FLASH_TZEN
);
2385 /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is
2386 * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */
2387 if (stm32l4_info
->rdp
!= RDP_LEVEL_1
&& stm32l4_info
->rdp
!= RDP_LEVEL_0_5
) {
2388 LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0");
2392 retval
= stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2393 RDP_LEVEL_0
, FLASH_RDP_MASK
| FLASH_TZEN
);
2396 if (retval
!= ERROR_OK
)
2399 return stm32l4_perform_obl_launch(bank
);
2402 COMMAND_HANDLER(stm32l4_handle_option_load_command
)
2405 return ERROR_COMMAND_SYNTAX_ERROR
;
2407 struct flash_bank
*bank
;
2408 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2409 if (retval
!= ERROR_OK
)
2412 retval
= stm32l4_perform_obl_launch(bank
);
2413 if (retval
!= ERROR_OK
) {
2414 command_print(CMD
, "stm32l4x option load failed");
2419 command_print(CMD
, "stm32l4x option load completed. Power-on reset might be required");
2424 COMMAND_HANDLER(stm32l4_handle_lock_command
)
2426 struct target
*target
= NULL
;
2429 return ERROR_COMMAND_SYNTAX_ERROR
;
2431 struct flash_bank
*bank
;
2432 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2433 if (retval
!= ERROR_OK
)
2436 if (stm32l4_is_otp(bank
)) {
2437 LOG_ERROR("cannot lock/unlock OTP memory");
2438 return ERROR_FLASH_OPER_UNSUPPORTED
;
2441 target
= bank
->target
;
2443 if (target
->state
!= TARGET_HALTED
) {
2444 LOG_ERROR("Target not halted");
2445 return ERROR_TARGET_NOT_HALTED
;
2448 /* set readout protection level 1 by erasing the RDP option byte */
2449 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2450 if (stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2451 RDP_LEVEL_1
, FLASH_RDP_MASK
) != ERROR_OK
) {
2452 command_print(CMD
, "%s failed to lock device", bank
->driver
->name
);
2459 COMMAND_HANDLER(stm32l4_handle_unlock_command
)
2461 struct target
*target
= NULL
;
2464 return ERROR_COMMAND_SYNTAX_ERROR
;
2466 struct flash_bank
*bank
;
2467 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2468 if (retval
!= ERROR_OK
)
2471 if (stm32l4_is_otp(bank
)) {
2472 LOG_ERROR("cannot lock/unlock OTP memory");
2473 return ERROR_FLASH_OPER_UNSUPPORTED
;
2476 target
= bank
->target
;
2478 if (target
->state
!= TARGET_HALTED
) {
2479 LOG_ERROR("Target not halted");
2480 return ERROR_TARGET_NOT_HALTED
;
2483 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2484 if (stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2485 RDP_LEVEL_0
, FLASH_RDP_MASK
) != ERROR_OK
) {
2486 command_print(CMD
, "%s failed to unlock device", bank
->driver
->name
);
2493 COMMAND_HANDLER(stm32l4_handle_wrp_info_command
)
2495 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
2496 return ERROR_COMMAND_SYNTAX_ERROR
;
2498 struct flash_bank
*bank
;
2499 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2500 if (retval
!= ERROR_OK
)
2503 if (stm32l4_is_otp(bank
)) {
2504 LOG_ERROR("OTP memory does not have write protection areas");
2505 return ERROR_FLASH_OPER_UNSUPPORTED
;
2508 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2509 enum stm32_bank_id dev_bank_id
= STM32_ALL_BANKS
;
2510 if (CMD_ARGC
== 2) {
2511 if (strcmp(CMD_ARGV
[1], "bank1") == 0)
2512 dev_bank_id
= STM32_BANK1
;
2513 else if (strcmp(CMD_ARGV
[1], "bank2") == 0)
2514 dev_bank_id
= STM32_BANK2
;
2516 return ERROR_COMMAND_ARGUMENT_INVALID
;
2519 if (dev_bank_id
== STM32_BANK2
) {
2520 if (!(stm32l4_info
->part_info
->flags
& F_HAS_DUAL_BANK
)) {
2521 LOG_ERROR("this device has no second bank");
2523 } else if (!stm32l4_info
->dual_bank_mode
) {
2524 LOG_ERROR("this device is configured in single bank mode");
2530 unsigned int n_wrp
, i
;
2531 struct stm32l4_wrp wrpxy
[4];
2533 ret
= stm32l4_get_all_wrpxy(bank
, dev_bank_id
, wrpxy
, &n_wrp
);
2534 if (ret
!= ERROR_OK
)
2537 /* use bitmap and range helpers to better describe protected areas */
2538 DECLARE_BITMAP(pages
, bank
->num_sectors
);
2539 bitmap_zero(pages
, bank
->num_sectors
);
2541 for (i
= 0; i
< n_wrp
; i
++) {
2542 if (wrpxy
[i
].used
) {
2543 for (int p
= wrpxy
[i
].first
; p
<= wrpxy
[i
].last
; p
++)
2548 /* we have at most 'n_wrp' WRP areas */
2549 struct range ranges
[n_wrp
];
2550 unsigned int ranges_count
= 0;
2552 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
2554 if (ranges_count
> 0) {
2555 /* pretty-print the protected ranges */
2556 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
2557 command_print(CMD
, "protected areas: %s", ranges_str
);
2560 command_print(CMD
, "no protected areas");
2565 COMMAND_HANDLER(stm32l4_handle_otp_command
)
2568 return ERROR_COMMAND_SYNTAX_ERROR
;
2570 struct flash_bank
*bank
;
2571 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2572 if (retval
!= ERROR_OK
)
2575 if (!stm32l4_is_otp(bank
)) {
2576 command_print(CMD
, "the specified bank is not an OTP memory");
2579 if (strcmp(CMD_ARGV
[1], "enable") == 0)
2580 stm32l4_otp_enable(bank
, true);
2581 else if (strcmp(CMD_ARGV
[1], "disable") == 0)
2582 stm32l4_otp_enable(bank
, false);
2583 else if (strcmp(CMD_ARGV
[1], "show") == 0)
2584 command_print(CMD
, "OTP memory bank #%d is %s for write commands.",
2585 bank
->bank_number
, stm32l4_otp_is_enabled(bank
) ? "enabled" : "disabled");
2587 return ERROR_COMMAND_SYNTAX_ERROR
;
2592 static const struct command_registration stm32l4_exec_command_handlers
[] = {
2595 .handler
= stm32l4_handle_lock_command
,
2596 .mode
= COMMAND_EXEC
,
2598 .help
= "Lock entire flash device.",
2602 .handler
= stm32l4_handle_unlock_command
,
2603 .mode
= COMMAND_EXEC
,
2605 .help
= "Unlock entire protected flash device.",
2608 .name
= "mass_erase",
2609 .handler
= stm32l4_handle_mass_erase_command
,
2610 .mode
= COMMAND_EXEC
,
2612 .help
= "Erase entire flash device.",
2615 .name
= "option_read",
2616 .handler
= stm32l4_handle_option_read_command
,
2617 .mode
= COMMAND_EXEC
,
2618 .usage
= "bank_id reg_offset",
2619 .help
= "Read & Display device option bytes.",
2622 .name
= "option_write",
2623 .handler
= stm32l4_handle_option_write_command
,
2624 .mode
= COMMAND_EXEC
,
2625 .usage
= "bank_id reg_offset value mask",
2626 .help
= "Write device option bit fields with provided value.",
2629 .name
= "trustzone",
2630 .handler
= stm32l4_handle_trustzone_command
,
2631 .mode
= COMMAND_EXEC
,
2632 .usage
= "<bank_id> [enable|disable]",
2633 .help
= "Configure TrustZone security",
2637 .handler
= stm32l4_handle_wrp_info_command
,
2638 .mode
= COMMAND_EXEC
,
2639 .usage
= "bank_id [bank1|bank2]",
2640 .help
= "list the protected areas using WRP",
2643 .name
= "option_load",
2644 .handler
= stm32l4_handle_option_load_command
,
2645 .mode
= COMMAND_EXEC
,
2647 .help
= "Force re-load of device options (will cause device reset).",
2651 .handler
= stm32l4_handle_otp_command
,
2652 .mode
= COMMAND_EXEC
,
2653 .usage
= "<bank_id> <enable|disable|show>",
2654 .help
= "OTP (One Time Programmable) memory write enable/disable",
2656 COMMAND_REGISTRATION_DONE
2659 static const struct command_registration stm32l4_command_handlers
[] = {
2662 .mode
= COMMAND_ANY
,
2663 .help
= "stm32l4x flash command group",
2665 .chain
= stm32l4_exec_command_handlers
,
2667 COMMAND_REGISTRATION_DONE
2670 const struct flash_driver stm32l4x_flash
= {
2672 .commands
= stm32l4_command_handlers
,
2673 .flash_bank_command
= stm32l4_flash_bank_command
,
2674 .erase
= stm32l4_erase
,
2675 .protect
= stm32l4_protect
,
2676 .write
= stm32l4_write
,
2677 .read
= default_flash_read
,
2678 .probe
= stm32l4_probe
,
2679 .auto_probe
= stm32l4_auto_probe
,
2680 .erase_check
= default_flash_blank_check
,
2681 .protect_check
= stm32l4_protect_check
,
2682 .info
= get_stm32l4_info
,
2683 .free_driver_priv
= default_flash_free_driver_priv
,