| blob | 9730417ee3ebd9562f9062f29242e66cce22d7c5 |
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
29 /* We can't use enum machine_mode inside a generator file because it
30 hasn't been created yet; we shouldn't be using any code that
31 needs the real definition though, so this ought to be safe. */
32 #ifdef GENERATOR_FILE
33 #define MACHMODE int
34 #else
36 #define MACHMODE enum machine_mode
37 #endif
41 /* The architecture define. */
44 /* Target CPU builtins. */
45 #define TARGET_CPU_CPP_BUILTINS() \
46 do \
47 { \
48 /* Define __arm__ even when in thumb mode, for \
52 if (TARGET_THUMB) \
54 if (TARGET_THUMB2) \
56 \
57 if (TARGET_BIG_END) \
58 { \
60 if (TARGET_THUMB) \
62 if (TARGET_LITTLE_WORDS) \
64 } \
65 else \
66 { \
68 if (TARGET_THUMB) \
70 } \
71 \
72 if (TARGET_SOFT_FLOAT) \
74 \
75 if (TARGET_VFP) \
77 \
78 if (TARGET_NEON) \
80 \
81 /* Add a define for interworking. \
83 if (arm_cpp_interwork) \
85 \
88 \
89 builtin_define (arm_arch_name); \
90 if (arm_arch_cirrus) \
92 if (arm_arch_xscale) \
94 if (arm_arch_iwmmxt) \
96 if (TARGET_AAPCS_BASED) \
97 { \
98 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
100 else if (arm_pcs_default == ARM_PCS_AAPCS) \
103 } \
104 } while (0)
106 /* The various ARM cores. */
107 enum processor_type
108 {
109 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
110 IDENT,
112 #undef ARM_CORE
113 /* Used to indicate that no processor has been specified. */
114 arm_none
115 };
117 enum target_cpus
118 {
119 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
120 TARGET_CPU_##IDENT,
122 #undef ARM_CORE
123 TARGET_CPU_generic
124 };
126 /* The processor for which instructions should be scheduled. */
129 enum arm_sync_generator_tag
130 {
131 arm_sync_generator_omn,
132 arm_sync_generator_omrn
133 };
135 /* Wrapper to pass around a polymorphic pointer to a sync instruction
136 generator and. */
137 struct arm_sync_generator
138 {
140 union
141 {
145 };
148 {
151 }
152 arm_cc;
156 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
161 /* The label of the current constant pool. */
163 /* Set to 1 when a return insn is output, this means that the epilogue
164 is not needed. */
166 /* Callback to output language specific object attributes. */
168 \f
169 /* Just in case configure has failed to define anything. */
170 #ifndef TARGET_CPU_DEFAULT
171 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
172 #endif
175 #undef CPP_SPEC
177 %{msoft-float:%{mhard-float: \
178 %e-msoft-float and -mhard_float may not be used together}} \
179 %{mbig-endian:%{mlittle-endian: \
180 %e-mbig-endian and -mlittle-endian may not be used together}}"
182 #ifndef CC1_SPEC
184 #endif
186 /* This macro defines names of additional specifications to put in the specs
187 that can be used in various specifications like CC1_SPEC. Its definition
188 is an initializer with a subgrouping for each command option.
190 Each subgrouping contains a string constant, that defines the
191 specification name, and a string constant that used by the GCC driver
192 program.
194 Do not define this macro if it does not need to do anything. */
195 #define EXTRA_SPECS \
197 SUBTARGET_EXTRA_SPECS
199 #ifndef SUBTARGET_EXTRA_SPECS
200 #define SUBTARGET_EXTRA_SPECS
201 #endif
203 #ifndef SUBTARGET_CPP_SPEC
205 #endif
206 \f
207 /* Run-time Target Specification. */
208 #ifndef TARGET_VERSION
210 #endif
212 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
213 /* Use hardware floating point instructions. */
214 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
215 /* Use hardware floating point calling convention. */
216 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
217 #define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA)
218 #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
219 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
220 #define TARGET_IWMMXT (arm_arch_iwmmxt)
221 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
222 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
223 #define TARGET_ARM (! TARGET_THUMB)
225 #define TARGET_BACKTRACE (leaf_function_p () \
226 ? TARGET_TPCS_LEAF_FRAME \
227 : TARGET_TPCS_FRAME)
228 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
229 #define TARGET_AAPCS_BASED \
230 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
232 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
233 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
235 /* Only 16-bit thumb code. */
236 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
237 /* Arm or Thumb-2 32-bit code. */
238 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
239 /* 32-bit Thumb-2 code. */
240 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
241 /* Thumb-1 only. */
242 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
243 /* FPA emulator without LFM. */
244 #define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
246 /* The following two macros concern the ability to execute coprocessor
247 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
248 only ever tested when we know we are generating for VFP hardware; we need
249 to be more careful with TARGET_NEON as noted below. */
251 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
252 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
254 /* FPU supports VFPv3 instructions. */
255 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
257 /* FPU only supports VFP single-precision instructions. */
258 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
260 /* FPU supports VFP double-precision instructions. */
261 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
263 /* FPU supports half-precision floating-point with NEON element load/store. */
264 #define TARGET_NEON_FP16 \
265 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
267 /* FPU supports VFP half-precision floating-point. */
268 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
270 /* FPU supports Neon instructions. The setting of this macro gets
271 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
272 and TARGET_HARD_FLOAT to ensure that NEON instructions are
273 available. */
274 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
275 && TARGET_VFP && arm_fpu_desc->neon)
277 /* "DSP" multiply instructions, eg. SMULxy. */
278 #define TARGET_DSP_MULTIPLY \
279 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
280 /* Integer SIMD instructions, and extend-accumulate instructions. */
281 #define TARGET_INT_SIMD \
282 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
284 /* Should MOVW/MOVT be used in preference to a constant pool. */
285 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
287 /* We could use unified syntax for arm mode, but for now we just use it
288 for Thumb-2. */
289 #define TARGET_UNIFIED_ASM TARGET_THUMB2
291 /* Nonzero if this chip provides the DMB instruction. */
292 #define TARGET_HAVE_DMB (arm_arch7)
294 /* Nonzero if this chip implements a memory barrier via CP15. */
295 #define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
297 /* Nonzero if this chip implements a memory barrier instruction. */
298 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
300 /* Nonzero if this chip supports ldrex and strex */
301 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
303 /* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */
304 #define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7)
306 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
307 then TARGET_AAPCS_BASED must be true -- but the converse does not
308 hold. TARGET_BPABI implies the use of the BPABI runtime library,
309 etc., in addition to just the AAPCS calling conventions. */
310 #ifndef TARGET_BPABI
311 #define TARGET_BPABI false
312 #endif
314 /* Support for a compile-time default CPU, et cetera. The rules are:
315 --with-arch is ignored if -march or -mcpu are specified.
316 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
317 by --with-arch.
318 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
319 by -march).
320 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
321 specified.
322 --with-fpu is ignored if -mfpu is specified.
323 --with-abi is ignored is -mabi is specified. */
324 #define OPTION_DEFAULT_SPECS \
334 /* Which floating point model to use. */
335 enum arm_fp_model
336 {
337 ARM_FP_MODEL_UNKNOWN,
338 /* FPA model (Hardware or software). */
339 ARM_FP_MODEL_FPA,
340 /* Cirrus Maverick floating point model. */
341 ARM_FP_MODEL_MAVERICK,
342 /* VFP floating point model. */
343 ARM_FP_MODEL_VFP
344 };
346 enum vfp_reg_type
347 {
349 VFP_REG_D16,
350 VFP_REG_D32,
351 VFP_REG_SINGLE
352 };
355 {
364 /* Which floating point hardware to schedule for. */
367 enum float_abi_type
368 {
369 ARM_FLOAT_ABI_SOFT,
370 ARM_FLOAT_ABI_SOFTFP,
371 ARM_FLOAT_ABI_HARD
372 };
376 #ifndef TARGET_DEFAULT_FLOAT_ABI
377 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
378 #endif
380 /* Which __fp16 format to use.
381 The enumeration values correspond to the numbering for the
382 Tag_ABI_FP_16bit_format attribute.
383 */
384 enum arm_fp16_format_type
385 {
389 };
392 #define LARGEST_EXPONENT_IS_NORMAL(bits) \
393 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
395 /* Which ABI to use. */
396 enum arm_abi_type
397 {
398 ARM_ABI_APCS,
399 ARM_ABI_ATPCS,
400 ARM_ABI_AAPCS,
401 ARM_ABI_IWMMXT,
402 ARM_ABI_AAPCS_LINUX
403 };
407 #ifndef ARM_DEFAULT_ABI
408 #define ARM_DEFAULT_ABI ARM_ABI_APCS
409 #endif
411 /* Which thread pointer access sequence to use. */
413 TP_AUTO,
414 TP_SOFT,
415 TP_CP15
416 };
420 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
423 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
426 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
429 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
432 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
435 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
438 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */
441 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */
444 /* Nonzero if instructions not present in the 'M' profile can be used. */
447 /* Nonzero if instructions present in ARMv7E-M can be used. */
450 /* Nonzero if this chip can benefit from load scheduling. */
453 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
456 /* Nonzero if generating Thumb-1 code. */
459 /* Nonzero if this chip is a StrongARM. */
462 /* Nonzero if this chip is a Cirrus variant. */
465 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
468 /* Nonzero if this chip is an XScale. */
471 /* Nonzero if tuning for XScale. */
474 /* Nonzero if tuning for stores via the write buffer. */
477 /* Nonzero if tuning for Cortex-A9. */
480 /* Nonzero if we should define __THUMB_INTERWORK__ in the
481 preprocessor.
482 XXX This is a bit of a hack, it's intended to help work around
483 problems in GLD which doesn't understand that armv5t code is
484 interworking clean. */
487 /* Nonzero if chip supports Thumb 2. */
490 /* Nonzero if chip supports integer division instruction. */
493 #ifndef TARGET_DEFAULT
494 #define TARGET_DEFAULT (MASK_APCS_FRAME)
495 #endif
497 /* The frame pointer register used in gcc has nothing to do with debugging;
498 that is controlled by the APCS-FRAME option. */
499 #define CAN_DEBUG_WITHOUT_FP
501 #define OVERRIDE_OPTIONS arm_override_options ()
503 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
504 arm_optimization_options ((LEVEL), (SIZE))
506 /* Nonzero if PIC code requires explicit qualifiers to generate
507 PLT and GOT relocs rather than the assembler doing so implicitly.
508 Subtargets can override these if required. */
509 #ifndef NEED_GOT_RELOC
510 #define NEED_GOT_RELOC 0
511 #endif
512 #ifndef NEED_PLT_RELOC
513 #define NEED_PLT_RELOC 0
514 #endif
516 /* Nonzero if we need to refer to the GOT with a PC-relative
517 offset. In other words, generate
519 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
521 rather than
523 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
525 The default is true, which matches NetBSD. Subtargets can
526 override this if required. */
527 #ifndef GOT_PCREL
528 #define GOT_PCREL 1
529 #endif
530 \f
531 /* Target machine storage Layout. */
534 /* Define this macro if it is advisable to hold scalars in registers
535 in a wider mode than that declared by the program. In such cases,
536 the value is constrained to be within the bounds of the declared
537 type, but kept valid in the wider mode. The signedness of the
538 extension may differ from that of the type. */
540 /* It is far faster to zero extend chars than to sign extend them */
542 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
543 if (GET_MODE_CLASS (MODE) == MODE_INT \
544 && GET_MODE_SIZE (MODE) < 4) \
545 { \
546 if (MODE == QImode) \
547 UNSIGNEDP = 1; \
548 else if (MODE == HImode) \
549 UNSIGNEDP = 1; \
550 (MODE) = SImode; \
551 }
553 /* Define this if most significant bit is lowest numbered
554 in instructions that operate on numbered bit-fields. */
555 #define BITS_BIG_ENDIAN 0
557 /* Define this if most significant byte of a word is the lowest numbered.
558 Most ARM processors are run in little endian mode, so that is the default.
559 If you want to have it run-time selectable, change the definition in a
560 cover file to be TARGET_BIG_ENDIAN. */
561 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
563 /* Define this if most significant word of a multiword number is the lowest
564 numbered.
565 This is always false, even when in big-endian mode. */
566 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
568 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
569 on processor pre-defineds when compiling libgcc2.c. */
570 #if defined(__ARMEB__) && !defined(__ARMWEL__)
571 #define LIBGCC2_WORDS_BIG_ENDIAN 1
572 #else
573 #define LIBGCC2_WORDS_BIG_ENDIAN 0
574 #endif
576 /* Define this if most significant word of doubles is the lowest numbered.
577 The rules are different based on whether or not we use FPA-format,
578 VFP-format or some other floating point co-processor's format doubles. */
579 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
581 #define UNITS_PER_WORD 4
583 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
584 registers when autovectorizing for Neon, at least until multiple vector
585 widths are supported properly by the middle-end. */
586 #define UNITS_PER_SIMD_WORD(MODE) \
587 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
589 /* True if natural alignment is used for doubleword types. */
590 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
592 #define DOUBLEWORD_ALIGNMENT 64
594 #define PARM_BOUNDARY 32
596 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
598 #define PREFERRED_STACK_BOUNDARY \
599 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
601 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
603 /* The lowest bit is used to indicate Thumb-mode functions, so the
604 vbit must go into the delta field of pointers to member
605 functions. */
606 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
608 #define EMPTY_FIELD_BOUNDARY 32
610 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
612 /* XXX Blah -- this macro is used directly by libobjc. Since it
613 supports no vector modes, cut out the complexity and fall back
614 on BIGGEST_FIELD_ALIGNMENT. */
615 #ifdef IN_TARGET_LIBS
616 #define BIGGEST_FIELD_ALIGNMENT 64
617 #endif
619 /* Make strings word-aligned so strcpy from constants will be faster. */
620 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
622 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
623 ((TREE_CODE (EXP) == STRING_CST \
624 && !optimize_size \
625 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
626 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
628 /* Align definitions of arrays, unions and structures so that
629 initializations and copies can be made more efficient. This is not
630 ABI-changing, so it only affects places where we can see the
631 definition. */
632 #define DATA_ALIGNMENT(EXP, ALIGN) \
633 ((((ALIGN) < BITS_PER_WORD) \
634 && (TREE_CODE (EXP) == ARRAY_TYPE \
635 || TREE_CODE (EXP) == UNION_TYPE \
636 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
638 /* Similarly, make sure that objects on the stack are sensibly aligned. */
639 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
641 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
642 value set in previous versions of this toolchain was 8, which produces more
643 compact structures. The command line option -mstructure_size_boundary=<n>
644 can be used to change this value. For compatibility with the ARM SDK
645 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
646 0020D) page 2-20 says "Structures are aligned on word boundaries".
647 The AAPCS specifies a value of 8. */
648 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
651 /* This is the value used to initialize arm_structure_size_boundary. If a
652 particular arm target wants to change the default value it should change
653 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
654 for an example of this. */
655 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
656 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
657 #endif
659 /* Nonzero if move instructions will actually fail to work
660 when given unaligned data. */
661 #define STRICT_ALIGNMENT 1
663 /* wchar_t is unsigned under the AAPCS. */
664 #ifndef WCHAR_TYPE
667 #define WCHAR_TYPE_SIZE BITS_PER_WORD
668 #endif
670 #ifndef SIZE_TYPE
672 #endif
674 #ifndef PTRDIFF_TYPE
676 #endif
678 /* AAPCS requires that structure alignment is affected by bitfields. */
679 #ifndef PCC_BITFIELD_TYPE_MATTERS
680 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
681 #endif
683 \f
684 /* Standard register usage. */
686 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
687 (S - saved over call).
689 r0 * argument word/integer result
690 r1-r3 argument word
692 r4-r8 S register variable
693 r9 S (rfp) register variable (real frame pointer)
695 r10 F S (sl) stack limit (used by -mapcs-stack-check)
696 r11 F S (fp) argument pointer
697 r12 (ip) temp workspace
698 r13 F S (sp) lower end of current stack frame
699 r14 (lr) link address/workspace
700 r15 F (pc) program counter
702 f0 floating point result
703 f1-f3 floating point scratch
705 f4-f7 S floating point variable
707 cc This is NOT a real register, but is used internally
708 to represent things that use or set the condition
709 codes.
710 sfp This isn't either. It is used during rtl generation
711 since the offset between the frame pointer and the
712 auto's isn't known until after register allocation.
713 afp Nor this, we only need this because of non-local
714 goto. Without it fp appears to be used and the
715 elimination code won't get rid of sfp. It tracks
716 fp exactly at all times.
718 *: See CONDITIONAL_REGISTER_USAGE */
720 /*
721 mvf0 Cirrus floating point result
722 mvf1-mvf3 Cirrus floating point scratch
723 mvf4-mvf15 S Cirrus floating point variable. */
725 /* s0-s15 VFP scratch (aka d0-d7).
726 s16-s31 S VFP variable (aka d8-d15).
727 vfpcc Not a real register. Represents the VFP condition
728 code flags. */
730 /* The stack backtrace structure is as follows:
731 fp points to here: | save code pointer | [fp]
732 | return link value | [fp, #-4]
733 | return sp value | [fp, #-8]
734 | return fp value | [fp, #-12]
735 [| saved r10 value |]
736 [| saved r9 value |]
737 [| saved r8 value |]
738 [| saved r7 value |]
739 [| saved r6 value |]
740 [| saved r5 value |]
741 [| saved r4 value |]
742 [| saved r3 value |]
743 [| saved r2 value |]
744 [| saved r1 value |]
745 [| saved r0 value |]
746 [| saved f7 value |] three words
747 [| saved f6 value |] three words
748 [| saved f5 value |] three words
749 [| saved f4 value |] three words
750 r0-r3 are not normally saved in a C function. */
752 /* 1 for registers that have pervasive standard uses
753 and are not available for the register allocator. */
754 #define FIXED_REGISTERS \
755 { \
756 0,0,0,0,0,0,0,0, \
757 0,0,0,0,0,1,0,1, \
758 0,0,0,0,0,0,0,0, \
759 1,1,1, \
760 1,1,1,1,1,1,1,1, \
761 1,1,1,1,1,1,1,1, \
762 1,1,1,1,1,1,1,1, \
763 1,1,1,1,1,1,1,1, \
764 1,1,1,1, \
765 1,1,1,1,1,1,1,1, \
766 1,1,1,1,1,1,1,1, \
767 1,1,1,1,1,1,1,1, \
768 1,1,1,1,1,1,1,1, \
769 1,1,1,1,1,1,1,1, \
770 1,1,1,1,1,1,1,1, \
771 1,1,1,1,1,1,1,1, \
772 1,1,1,1,1,1,1,1, \
773 1 \
774 }
776 /* 1 for registers not available across function calls.
777 These must include the FIXED_REGISTERS and also any
778 registers that can be used without being saved.
779 The latter must include the registers where values are returned
780 and the register where structure-value addresses are passed.
781 Aside from that, you can include as many other registers as you like.
782 The CC is not preserved over function calls on the ARM 6, so it is
783 easier to assume this for all. SFP is preserved, since FP is. */
784 #define CALL_USED_REGISTERS \
785 { \
786 1,1,1,1,0,0,0,0, \
787 0,0,0,0,1,1,1,1, \
788 1,1,1,1,0,0,0,0, \
789 1,1,1, \
790 1,1,1,1,1,1,1,1, \
791 1,1,1,1,1,1,1,1, \
792 1,1,1,1,1,1,1,1, \
793 1,1,1,1,1,1,1,1, \
794 1,1,1,1, \
795 1,1,1,1,1,1,1,1, \
796 1,1,1,1,1,1,1,1, \
797 1,1,1,1,1,1,1,1, \
798 1,1,1,1,1,1,1,1, \
799 1,1,1,1,1,1,1,1, \
800 1,1,1,1,1,1,1,1, \
801 1,1,1,1,1,1,1,1, \
802 1,1,1,1,1,1,1,1, \
803 1 \
804 }
806 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
807 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
808 #endif
810 #define CONDITIONAL_REGISTER_USAGE \
811 { \
812 int regno; \
813 \
814 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
815 { \
816 for (regno = FIRST_FPA_REGNUM; \
817 regno <= LAST_FPA_REGNUM; ++regno) \
818 fixed_regs[regno] = call_used_regs[regno] = 1; \
819 } \
820 \
821 if (TARGET_THUMB1 && optimize_size) \
822 { \
823 /* When optimizing for size on Thumb-1, it's better not \
824 to use the HI regs, because of the overhead of \
826 for (regno = FIRST_HI_REGNUM; \
827 regno <= LAST_HI_REGNUM; ++regno) \
828 fixed_regs[regno] = call_used_regs[regno] = 1; \
829 } \
830 \
831 /* The link register can be clobbered by any branch insn, \
832 but we have no way to track that at present, so mark \
834 if (TARGET_THUMB1) \
835 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
836 \
837 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
838 { \
839 if (TARGET_MAVERICK) \
840 { \
841 for (regno = FIRST_FPA_REGNUM; \
842 regno <= LAST_FPA_REGNUM; ++ regno) \
843 fixed_regs[regno] = call_used_regs[regno] = 1; \
844 for (regno = FIRST_CIRRUS_FP_REGNUM; \
845 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
846 { \
847 fixed_regs[regno] = 0; \
848 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
849 } \
850 } \
851 if (TARGET_VFP) \
852 { \
853 /* VFPv3 registers are disabled when earlier VFP \
854 versions are selected due to the definition of \
856 for (regno = FIRST_VFP_REGNUM; \
857 regno <= LAST_VFP_REGNUM; ++ regno) \
858 { \
859 fixed_regs[regno] = 0; \
860 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
861 || regno >= FIRST_VFP_REGNUM + 32; \
862 } \
863 } \
864 } \
865 \
866 if (TARGET_REALLY_IWMMXT) \
867 { \
868 regno = FIRST_IWMMXT_GR_REGNUM; \
869 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
870 and wCG1 as call-preserved registers. The 2002/11/21 \
871 revision changed this so that all wCG registers are \
873 for (regno = FIRST_IWMMXT_GR_REGNUM; \
874 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
875 fixed_regs[regno] = 0; \
876 /* The XScale ABI has wR0 - wR9 as scratch registers, \
878 for (regno = FIRST_IWMMXT_REGNUM; \
879 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
880 { \
881 fixed_regs[regno] = 0; \
882 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
883 } \
884 } \
885 \
886 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
887 { \
888 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
889 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
890 } \
891 else if (TARGET_APCS_STACK) \
892 { \
893 fixed_regs[10] = 1; \
894 call_used_regs[10] = 1; \
895 } \
896 /* -mcaller-super-interworking reserves r11 for calls to \
897 _interwork_r11_call_via_rN(). Making the register global \
898 is an easy way of ensuring that it remains valid for all \
900 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
901 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
902 { \
903 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
904 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
905 if (TARGET_CALLER_INTERWORKING) \
906 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
907 } \
908 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
909 }
911 /* These are a couple of extensions to the formats accepted
912 by asm_fprintf:
913 %@ prints out ASM_COMMENT_START
914 %r prints out REGISTER_PREFIX reg_names[arg] */
915 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
917 fputs (ASM_COMMENT_START, FILE); \
918 break; \
919 \
921 fputs (REGISTER_PREFIX, FILE); \
922 fputs (reg_names [va_arg (ARGS, int)], FILE); \
923 break;
925 /* Round X up to the nearest word. */
926 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
928 /* Convert fron bytes to ints. */
929 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
931 /* The number of (integer) registers required to hold a quantity of type MODE.
932 Also used for VFP registers. */
933 #define ARM_NUM_REGS(MODE) \
934 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
936 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
937 #define ARM_NUM_REGS2(MODE, TYPE) \
938 ARM_NUM_INTS ((MODE) == BLKmode ? \
939 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
941 /* The number of (integer) argument register available. */
942 #define NUM_ARG_REGS 4
944 /* And similarly for the VFP. */
945 #define NUM_VFP_ARG_REGS 16
947 /* Return the register number of the N'th (integer) argument. */
948 #define ARG_REGISTER(N) (N - 1)
950 /* Specify the registers used for certain standard purposes.
951 The values of these macros are register numbers. */
953 /* The number of the last argument register. */
954 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
956 /* The numbers of the Thumb register ranges. */
957 #define FIRST_LO_REGNUM 0
958 #define LAST_LO_REGNUM 7
959 #define FIRST_HI_REGNUM 8
960 #define LAST_HI_REGNUM 11
962 #ifndef TARGET_UNWIND_INFO
963 /* We use sjlj exceptions for backwards compatibility. */
964 #define MUST_USE_SJLJ_EXCEPTIONS 1
965 #endif
967 /* We can generate DWARF2 Unwind info, even though we don't use it. */
968 #define DWARF2_UNWIND_INFO 1
970 /* Use r0 and r1 to pass exception handling information. */
971 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
973 /* The register that holds the return address in exception handlers. */
974 #define ARM_EH_STACKADJ_REGNUM 2
975 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
977 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
978 as an invisible last argument (possible since varargs don't exist in
979 Pascal), so the following is not true. */
980 #define STATIC_CHAIN_REGNUM 12
982 /* Define this to be where the real frame pointer is if it is not possible to
983 work out the offset between the frame pointer and the automatic variables
984 until after register allocation has taken place. FRAME_POINTER_REGNUM
985 should point to a special register that we will make sure is eliminated.
987 For the Thumb we have another problem. The TPCS defines the frame pointer
988 as r11, and GCC believes that it is always possible to use the frame pointer
989 as base register for addressing purposes. (See comments in
990 find_reloads_address()). But - the Thumb does not allow high registers,
991 including r11, to be used as base address registers. Hence our problem.
993 The solution used here, and in the old thumb port is to use r7 instead of
994 r11 as the hard frame pointer and to have special code to generate
995 backtrace structures on the stack (if required to do so via a command line
996 option) using r11. This is the only 'user visible' use of r11 as a frame
997 pointer. */
998 #define ARM_HARD_FRAME_POINTER_REGNUM 11
999 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
1001 #define HARD_FRAME_POINTER_REGNUM \
1002 (TARGET_ARM \
1003 ? ARM_HARD_FRAME_POINTER_REGNUM \
1004 : THUMB_HARD_FRAME_POINTER_REGNUM)
1006 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1008 /* Register to use for pushing function arguments. */
1009 #define STACK_POINTER_REGNUM SP_REGNUM
1011 /* ARM floating pointer registers. */
1012 #define FIRST_FPA_REGNUM 16
1013 #define LAST_FPA_REGNUM 23
1014 #define IS_FPA_REGNUM(REGNUM) \
1015 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
1017 #define FIRST_IWMMXT_GR_REGNUM 43
1018 #define LAST_IWMMXT_GR_REGNUM 46
1019 #define FIRST_IWMMXT_REGNUM 47
1020 #define LAST_IWMMXT_REGNUM 62
1021 #define IS_IWMMXT_REGNUM(REGNUM) \
1022 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1023 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1024 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1026 /* Base register for access to local variables of the function. */
1027 #define FRAME_POINTER_REGNUM 25
1029 /* Base register for access to arguments of the function. */
1030 #define ARG_POINTER_REGNUM 26
1032 #define FIRST_CIRRUS_FP_REGNUM 27
1033 #define LAST_CIRRUS_FP_REGNUM 42
1034 #define IS_CIRRUS_REGNUM(REGNUM) \
1035 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1037 #define FIRST_VFP_REGNUM 63
1039 #define LAST_VFP_REGNUM \
1040 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
1042 #define IS_VFP_REGNUM(REGNUM) \
1043 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1045 /* VFP registers are split into two types: those defined by VFP versions < 3
1046 have D registers overlaid on consecutive pairs of S registers. VFP version 3
1047 defines 16 new D registers (d16-d31) which, for simplicity and correctness
1048 in various parts of the backend, we implement as "fake" single-precision
1049 registers (which would be S32-S63, but cannot be used in that way). The
1050 following macros define these ranges of registers. */
1051 #define LAST_LO_VFP_REGNUM 94
1052 #define FIRST_HI_VFP_REGNUM 95
1053 #define LAST_HI_VFP_REGNUM 126
1055 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
1056 ((REGNUM) <= LAST_LO_VFP_REGNUM)
1058 /* DFmode values are only valid in even register pairs. */
1059 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1060 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1062 /* Neon Quad values must start at a multiple of four registers. */
1063 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1064 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1066 /* Neon structures of vectors must be in even register pairs and there
1067 must be enough registers available. Because of various patterns
1068 requiring quad registers, we require them to start at a multiple of
1069 four. */
1070 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1071 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1072 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1074 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1075 /* + 16 Cirrus registers take us up to 43. */
1076 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1077 /* VFP (VFP3) adds 32 (64) + 1 more. */
1078 #define FIRST_PSEUDO_REGISTER 128
1080 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1082 /* Value should be nonzero if functions must have frame pointers.
1083 Zero means the frame pointer need not be set up (and parms may be accessed
1084 via the stack pointer) in functions that seem suitable.
1085 If we have to have a frame pointer we might as well make use of it.
1086 APCS says that the frame pointer does not need to be pushed in leaf
1087 functions, or simple tail call functions. */
1089 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1090 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1091 #endif
1093 /* Return number of consecutive hard regs needed starting at reg REGNO
1094 to hold something of mode MODE.
1095 This is ordinarily the length in words of a value of mode MODE
1096 but can be less for certain modes in special long registers.
1098 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1099 mode. */
1100 #define HARD_REGNO_NREGS(REGNO, MODE) \
1101 ((TARGET_32BIT \
1102 && REGNO >= FIRST_FPA_REGNUM \
1103 && REGNO != FRAME_POINTER_REGNUM \
1104 && REGNO != ARG_POINTER_REGNUM) \
1105 && !IS_VFP_REGNUM (REGNO) \
1106 ? 1 : ARM_NUM_REGS (MODE))
1108 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1109 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1110 arm_hard_regno_mode_ok ((REGNO), (MODE))
1112 /* Value is 1 if it is a good idea to tie two pseudo registers
1113 when one has mode MODE1 and one has mode MODE2.
1114 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1115 for any hard reg, then this must be 0 for correct output. */
1116 #define MODES_TIEABLE_P(MODE1, MODE2) \
1117 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1119 #define VALID_IWMMXT_REG_MODE(MODE) \
1120 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1122 /* Modes valid for Neon D registers. */
1123 #define VALID_NEON_DREG_MODE(MODE) \
1124 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1125 || (MODE) == V2SFmode || (MODE) == DImode)
1127 /* Modes valid for Neon Q registers. */
1128 #define VALID_NEON_QREG_MODE(MODE) \
1129 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1130 || (MODE) == V4SFmode || (MODE) == V2DImode)
1132 /* Structure modes valid for Neon registers. */
1133 #define VALID_NEON_STRUCT_MODE(MODE) \
1134 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1135 || (MODE) == CImode || (MODE) == XImode)
1137 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1140 /* The order in which register should be allocated. It is good to use ip
1141 since no saving is required (though calls clobber it) and it never contains
1142 function parameters. It is quite good to use lr since other calls may
1143 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1144 least likely to contain a function parameter; in addition results are
1145 returned in r0.
1146 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1147 then D8-D15. The reason for doing this is to attempt to reduce register
1148 pressure when both single- and double-precision registers are used in a
1149 function. */
1151 #define REG_ALLOC_ORDER \
1152 { \
1153 3, 2, 1, 0, 12, 14, 4, 5, \
1154 6, 7, 8, 10, 9, 11, 13, 15, \
1155 16, 17, 18, 19, 20, 21, 22, 23, \
1156 27, 28, 29, 30, 31, 32, 33, 34, \
1157 35, 36, 37, 38, 39, 40, 41, 42, \
1158 43, 44, 45, 46, 47, 48, 49, 50, \
1159 51, 52, 53, 54, 55, 56, 57, 58, \
1160 59, 60, 61, 62, \
1161 24, 25, 26, \
1162 95, 96, 97, 98, 99, 100, 101, 102, \
1163 103, 104, 105, 106, 107, 108, 109, 110, \
1164 111, 112, 113, 114, 115, 116, 117, 118, \
1165 119, 120, 121, 122, 123, 124, 125, 126, \
1166 78, 77, 76, 75, 74, 73, 72, 71, \
1167 70, 69, 68, 67, 66, 65, 64, 63, \
1168 79, 80, 81, 82, 83, 84, 85, 86, \
1169 87, 88, 89, 90, 91, 92, 93, 94, \
1170 127 \
1171 }
1173 /* Use different register alloc ordering for Thumb. */
1174 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1176 /* Tell IRA to use the order we define rather than messing it up with its
1177 own cost calculations. */
1178 #define HONOR_REG_ALLOC_ORDER
1180 /* Interrupt functions can only use registers that have already been
1181 saved by the prologue, even if they would normally be
1182 call-clobbered. */
1183 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1184 (! IS_INTERRUPT (cfun->machine->func_type) || \
1185 df_regs_ever_live_p (DST))
1186 \f
1187 /* Register and constant classes. */
1189 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1190 Now that the Thumb is involved it has become more complicated. */
1191 enum reg_class
1192 {
1193 NO_REGS,
1194 FPA_REGS,
1195 CIRRUS_REGS,
1196 VFP_D0_D7_REGS,
1197 VFP_LO_REGS,
1198 VFP_HI_REGS,
1199 VFP_REGS,
1200 IWMMXT_GR_REGS,
1201 IWMMXT_REGS,
1202 LO_REGS,
1203 STACK_REG,
1204 BASE_REGS,
1205 HI_REGS,
1206 CC_REG,
1207 VFPCC_REG,
1208 GENERAL_REGS,
1209 CORE_REGS,
1210 ALL_REGS,
1211 LIM_REG_CLASSES
1212 };
1214 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1216 /* Give names of register classes as strings for dump file. */
1217 #define REG_CLASS_NAMES \
1218 { \
1237 }
1239 /* Define which registers fit in which classes.
1240 This is an initializer for a vector of HARD_REG_SET
1241 of length N_REG_CLASSES. */
1242 #define REG_CLASS_CONTENTS \
1243 { \
1262 }
1264 /* Any of the VFP register classes. */
1265 #define IS_VFP_CLASS(X) \
1266 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1267 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1269 /* The same information, inverted:
1270 Return the class number of the smallest class containing
1271 reg number REGNO. This could be a conditional expression
1272 or could index an array. */
1273 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1275 /* The following macro defines cover classes for Integrated Register
1276 Allocator. Cover classes is a set of non-intersected register
1277 classes covering all hard registers used for register allocation
1278 purpose. Any move between two registers of a cover class should be
1279 cheaper than load or store of the registers. The macro value is
1280 array of register classes with LIM_REG_CLASSES used as the end
1281 marker. */
1283 #define IRA_COVER_CLASSES \
1284 { \
1285 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1286 LIM_REG_CLASSES \
1287 }
1289 /* FPA registers can't do subreg as all values are reformatted to internal
1290 precision. VFP registers may only be accessed in the mode they
1291 were set. */
1292 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1293 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1294 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1295 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1296 : 0)
1298 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1299 using r0-r4 for function arguments, r7 for the stack frame and don't
1300 have enough left over to do doubleword arithmetic. */
1301 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1302 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1303 || (CLASS) == CC_REG)
1305 /* The class value for index registers, and the one for base regs. */
1306 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1307 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1309 /* For the Thumb the high registers cannot be used as base registers
1310 when addressing quantities in QI or HI mode; if we don't know the
1311 mode, then we must be conservative. */
1312 #define MODE_BASE_REG_CLASS(MODE) \
1313 (TARGET_32BIT ? CORE_REGS : \
1314 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1316 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1317 instead of BASE_REGS. */
1318 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1320 /* When this hook returns true for MODE, the compiler allows
1321 registers explicitly used in the rtl to be used as spill registers
1322 but prevents the compiler from extending the lifetime of these
1323 registers. */
1324 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1325 arm_small_register_classes_for_mode_p
1327 /* Given an rtx X being reloaded into a reg required to be
1328 in class CLASS, return the class of reg to actually use.
1329 In general this is just CLASS, but for the Thumb core registers and
1330 immediate constants we prefer a LO_REGS class or a subset. */
1331 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1332 (TARGET_32BIT ? (CLASS) : \
1333 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1334 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1335 ? LO_REGS : (CLASS)))
1337 /* Must leave BASE_REGS reloads alone */
1338 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1339 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1340 ? ((true_regnum (X) == -1 ? LO_REGS \
1341 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1342 : NO_REGS)) \
1343 : NO_REGS)
1345 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1346 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1347 ? ((true_regnum (X) == -1 ? LO_REGS \
1348 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1349 : NO_REGS)) \
1350 : NO_REGS)
1352 /* Return the register class of a scratch register needed to copy IN into
1353 or out of a register in CLASS in MODE. If it can be done directly,
1354 NO_REGS is returned. */
1355 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1357 ((TARGET_VFP && TARGET_HARD_FLOAT \
1358 && IS_VFP_CLASS (CLASS)) \
1359 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1360 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1361 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1362 : TARGET_32BIT \
1363 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1364 ? GENERAL_REGS : NO_REGS) \
1365 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1367 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1368 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1370 ((TARGET_VFP && TARGET_HARD_FLOAT \
1371 && IS_VFP_CLASS (CLASS)) \
1372 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1373 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1374 coproc_secondary_reload_class (MODE, X, TRUE) : \
1376 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1377 && (CLASS) == CIRRUS_REGS \
1378 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1379 ? GENERAL_REGS : \
1380 (TARGET_32BIT ? \
1381 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1382 && CONSTANT_P (X)) \
1383 ? GENERAL_REGS : \
1384 (((MODE) == HImode && ! arm_arch4 \
1385 && (GET_CODE (X) == MEM \
1386 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1387 && true_regnum (X) == -1))) \
1388 ? GENERAL_REGS : NO_REGS) \
1389 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1391 /* Try a machine-dependent way of reloading an illegitimate address
1392 operand. If we find one, push the reload and jump to WIN. This
1393 macro is used in only one place: `find_reloads_address' in reload.c.
1395 For the ARM, we wish to handle large displacements off a base
1396 register by splitting the addend across a MOV and the mem insn.
1397 This can cut the number of reloads needed. */
1398 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1399 do \
1400 { \
1401 if (GET_CODE (X) == PLUS \
1402 && GET_CODE (XEXP (X, 0)) == REG \
1403 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1404 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1405 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1406 { \
1407 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1408 HOST_WIDE_INT low, high; \
1409 \
1410 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1411 low = ((val & 0xf) ^ 0x8) - 0x8; \
1412 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1414 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1415 else if (MODE == SImode \
1416 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1417 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1419 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1420 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1422 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1423 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1424 && TARGET_HARD_FLOAT && TARGET_FPA) \
1426 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1427 else \
1428 break; \
1429 \
1430 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1431 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1432 - (unsigned HOST_WIDE_INT) 0x80000000); \
1434 if (low == 0 || high == 0 || (high + low != val)) \
1435 break; \
1436 \
1437 /* Reload the high part into a base reg; leave the low part \
1439 X = gen_rtx_PLUS (GET_MODE (X), \
1440 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1441 GEN_INT (high)), \
1442 GEN_INT (low)); \
1443 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1444 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1445 VOIDmode, 0, 0, OPNUM, TYPE); \
1446 goto WIN; \
1447 } \
1448 } \
1449 while (0)
1451 /* XXX If an HImode FP+large_offset address is converted to an HImode
1452 SP+large_offset address, then reload won't know how to fix it. It sees
1453 only that SP isn't valid for HImode, and so reloads the SP into an index
1454 register, but the resulting address is still invalid because the offset
1455 is too big. We fix it here instead by reloading the entire address. */
1456 /* We could probably achieve better results by defining PROMOTE_MODE to help
1457 cope with the variances between the Thumb's signed and unsigned byte and
1458 halfword load instructions. */
1459 /* ??? This should be safe for thumb2, but we may be able to do better. */
1460 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1461 do { \
1462 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1463 if (new_x) \
1464 { \
1465 X = new_x; \
1466 goto WIN; \
1467 } \
1468 } while (0)
1470 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1471 if (TARGET_ARM) \
1472 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1473 else \
1474 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1476 /* Return the maximum number of consecutive registers
1477 needed to represent mode MODE in a register of class CLASS.
1478 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1479 #define CLASS_MAX_NREGS(CLASS, MODE) \
1480 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1482 /* If defined, gives a class of registers that cannot be used as the
1483 operand of a SUBREG that changes the mode of the object illegally. */
1485 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns.
1486 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
1487 it is typically more expensive than a single memory access. We set
1488 the cost to less than two memory accesses so that floating
1489 point to integer conversion does not go through memory. */
1490 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1491 (TARGET_32BIT ? \
1492 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1493 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1494 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \
1495 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \
1496 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1497 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1498 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1499 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1500 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1501 2) \
1502 : \
1503 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1504 \f
1505 /* Stack layout; function entry, exit and calling. */
1507 /* Define this if pushing a word on the stack
1508 makes the stack pointer a smaller address. */
1509 #define STACK_GROWS_DOWNWARD 1
1511 /* Define this to nonzero if the nominal address of the stack frame
1512 is at the high-address end of the local variables;
1513 that is, each additional local variable allocated
1514 goes at a more negative offset in the frame. */
1515 #define FRAME_GROWS_DOWNWARD 1
1517 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1518 When present, it is one word in size, and sits at the top of the frame,
1519 between the soft frame pointer and either r7 or r11.
1521 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1522 and only then if some outgoing arguments are passed on the stack. It would
1523 be tempting to also check whether the stack arguments are passed by indirect
1524 calls, but there seems to be no reason in principle why a post-reload pass
1525 couldn't convert a direct call into an indirect one. */
1526 #define CALLER_INTERWORKING_SLOT_SIZE \
1527 (TARGET_CALLER_INTERWORKING \
1528 && crtl->outgoing_args_size != 0 \
1529 ? UNITS_PER_WORD : 0)
1531 /* Offset within stack frame to start allocating local variables at.
1532 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1533 first local allocated. Otherwise, it is the offset to the BEGINNING
1534 of the first local allocated. */
1535 #define STARTING_FRAME_OFFSET 0
1537 /* If we generate an insn to push BYTES bytes,
1538 this says how many the stack pointer really advances by. */
1539 /* The push insns do not do this rounding implicitly.
1540 So don't define this. */
1541 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1543 /* Define this if the maximum size of all the outgoing args is to be
1544 accumulated and pushed during the prologue. The amount can be
1545 found in the variable crtl->outgoing_args_size. */
1546 #define ACCUMULATE_OUTGOING_ARGS 1
1548 /* Offset of first parameter from the argument pointer register value. */
1549 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1551 /* Define how to find the value returned by a library function
1552 assuming the value has mode MODE. */
1553 #define LIBCALL_VALUE(MODE) \
1554 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \
1555 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1556 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1557 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1558 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1559 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1560 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1561 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1562 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1563 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1565 /* 1 if REGNO is a possible register number for a function value. */
1566 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1567 ((REGNO) == ARG_REGISTER (1) \
1568 || (TARGET_AAPCS_BASED && TARGET_32BIT \
1569 && TARGET_VFP && TARGET_HARD_FLOAT \
1570 && (REGNO) == FIRST_VFP_REGNUM) \
1571 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1572 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1573 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1574 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1575 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1577 /* Amount of memory needed for an untyped call to save all possible return
1578 registers. */
1579 #define APPLY_RESULT_SIZE arm_apply_result_size()
1581 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1582 values must be in memory. On the ARM, they need only do so if larger
1583 than a word, or if they contain elements offset from zero in the struct. */
1584 #define DEFAULT_PCC_STRUCT_RETURN 0
1586 /* These bits describe the different types of function supported
1587 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1588 normal function and an interworked function, for example. Knowing the
1589 type of a function is important for determining its prologue and
1590 epilogue sequences.
1591 Note value 7 is currently unassigned. Also note that the interrupt
1592 function types all have bit 2 set, so that they can be tested for easily.
1593 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1594 machine_function structure is initialized (to zero) func_type will
1595 default to unknown. This will force the first use of arm_current_func_type
1596 to call arm_compute_func_type. */
1604 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1606 /* In addition functions can have several type modifiers,
1607 outlined by these bit masks: */
1614 /* Some macros to test these flags. */
1615 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1616 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1617 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1618 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1619 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1620 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1623 /* Structure used to hold the function stack frame layout. Offsets are
1624 relative to the stack pointer on function entry. Positive offsets are
1625 in the direction of stack growth.
1626 Only soft_frame is used in thumb mode. */
1629 {
1637 }
1638 arm_stack_offsets;
1640 #ifndef GENERATOR_FILE
1641 /* A C structure for machine-specific, per-function data.
1642 This is added to the cfun structure. */
1644 {
1645 /* Additional stack adjustment in __builtin_eh_throw. */
1646 rtx eh_epilogue_sp_ofs;
1647 /* Records if LR has to be saved for far jumps. */
1649 /* Records if ARG_POINTER was ever live. */
1651 /* Records if the save of LR has been eliminated. */
1653 /* The size of the stack frame. Only valid after reload. */
1654 arm_stack_offsets stack_offsets;
1655 /* Records the type of the current function. */
1657 /* Record if the function has a variable argument list. */
1659 /* Records if sibcalls are blocked because an argument
1660 register is needed to preserve stack alignment. */
1662 /* The PIC register for this function. This might be a pseudo. */
1663 rtx pic_reg;
1664 /* Labels for per-function Thumb call-via stubs. One per potential calling
1665 register. We can never call via LR or PC. We can call via SP if a
1666 trampoline happens to be on the top of the stack. */
1668 /* Set to 1 when a return insn is output, this means that the epilogue
1669 is not needed. */
1671 /* When outputting Thumb-1 code, record the last insn that provides
1672 information about condition codes, and the comparison operands. */
1673 rtx thumb1_cc_insn;
1674 rtx thumb1_cc_op0;
1675 rtx thumb1_cc_op1;
1676 /* Also record the CC mode that is supported. */
1678 }
1679 machine_function;
1680 #endif
1682 /* As in the machine_function, a global set of call-via labels, for code
1683 that is in text_section. */
1686 /* The number of potential ways of assigning to a co-processor. */
1687 #define ARM_NUM_COPROC_SLOTS 1
1689 /* Enumeration of procedure calling standard variants. We don't really
1690 support all of these yet. */
1691 enum arm_pcs
1692 {
1696 /* This must be the last AAPCS variant. */
1700 ARM_PCS_UNKNOWN
1701 };
1703 /* Default procedure calling standard of current compilation unit. */
1706 /* A C type for declaring a variable that is used as the first argument of
1707 `FUNCTION_ARG' and other related values. */
1709 {
1710 /* This is the number of registers of arguments scanned so far. */
1712 /* This is the number of iWMMXt register arguments scanned so far. */
1716 /* Which procedure call variant to use for this call. */
1719 /* AAPCS related state tracking. */
1722 this argument, or -1 if using core
1723 registers. */
1728 split between core regs and stack.
1729 Zero otherwise. */
1732 and the stack. */
1733 /* Private data for tracking VFP register allocation */
1737 MACHMODE aapcs_vfp_rmode;
1740 /* Define where to put the arguments to a function.
1741 Value is zero to push the argument on the stack,
1742 or a hard register in which to store the argument.
1744 MODE is the argument's machine mode.
1745 TYPE is the data type of the argument (as a tree).
1746 This is null for libcalls where that information may
1747 not be available.
1748 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1749 the preceding args and about the function being called.
1750 NAMED is nonzero if this argument is a named parameter
1751 (otherwise it is an extra parameter matching an ellipsis).
1753 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1754 other arguments are passed on the stack. If (NAMED == 0) (which happens
1755 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1756 defined), say it is passed in the stack (function_prologue will
1757 indeed make it pass in the stack if necessary). */
1758 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1759 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1761 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1762 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1764 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1765 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1767 /* For AAPCS, padding should never be below the argument. For other ABIs,
1768 * mimic the default. */
1769 #define PAD_VARARGS_DOWN \
1770 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1772 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1773 for a call to a function whose data type is FNTYPE.
1774 For a library call, FNTYPE is 0.
1775 On the ARM, the offset starts at 0. */
1776 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1777 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1779 /* Update the data in CUM to advance over an argument
1780 of mode MODE and data type TYPE.
1781 (TYPE is null for libcalls where that information may not be available.) */
1782 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1783 arm_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1785 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1786 argument with the specified mode and type. If it is not defined,
1787 `PARM_BOUNDARY' is used for all arguments. */
1788 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1789 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1790 ? DOUBLEWORD_ALIGNMENT \
1791 : PARM_BOUNDARY )
1793 /* 1 if N is a possible register number for function argument passing.
1794 On the ARM, r0-r3 are used to pass args. */
1795 #define FUNCTION_ARG_REGNO_P(REGNO) \
1796 (IN_RANGE ((REGNO), 0, 3) \
1797 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1798 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1799 || (TARGET_IWMMXT_ABI \
1800 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1802 \f
1803 /* If your target environment doesn't prefix user functions with an
1804 underscore, you may wish to re-define this to prevent any conflicts. */
1805 #ifndef ARM_MCOUNT_NAME
1807 #endif
1809 /* Call the function profiler with a given profile label. The Acorn
1810 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1811 On the ARM the full profile code will look like:
1812 .data
1813 LP1
1814 .word 0
1815 .text
1816 mov ip, lr
1817 bl mcount
1818 .word LP1
1820 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1821 will output the .text section.
1823 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1824 ``prof'' doesn't seem to mind about this!
1826 Note - this version of the code is designed to work in both ARM and
1827 Thumb modes. */
1828 #ifndef ARM_FUNCTION_PROFILER
1829 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1830 { \
1831 char temp[20]; \
1832 rtx sym; \
1833 \
1835 IP_REGNUM, LR_REGNUM); \
1836 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1839 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1840 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1841 }
1842 #endif
1844 #ifdef THUMB_FUNCTION_PROFILER
1845 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1846 if (TARGET_ARM) \
1847 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1848 else \
1849 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1850 #else
1851 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1852 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1853 #endif
1855 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1856 the stack pointer does not matter. The value is tested only in
1857 functions that have frame pointers.
1858 No definition is equivalent to always zero.
1860 On the ARM, the function epilogue recovers the stack pointer from the
1861 frame. */
1862 #define EXIT_IGNORE_STACK 1
1864 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1866 /* Determine if the epilogue should be output as RTL.
1867 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1868 #define USE_RETURN_INSN(ISCOND) \
1869 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1871 /* Definitions for register eliminations.
1873 This is an array of structures. Each structure initializes one pair
1874 of eliminable registers. The "from" register number is given first,
1875 followed by "to". Eliminations of the same "from" register are listed
1876 in order of preference.
1878 We have two registers that can be eliminated on the ARM. First, the
1879 arg pointer register can often be eliminated in favor of the stack
1880 pointer register. Secondly, the pseudo frame pointer register can always
1881 be eliminated; it is replaced with either the stack or the real frame
1882 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1883 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1885 #define ELIMINABLE_REGS \
1886 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1887 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1888 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1889 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1890 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1891 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1892 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1894 /* Define the offset between two registers, one to be eliminated, and the
1895 other its replacement, at the start of a routine. */
1896 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1897 if (TARGET_ARM) \
1898 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1899 else \
1900 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1902 /* Special case handling of the location of arguments passed on the stack. */
1903 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1905 /* Initialize data used by insn expanders. This is called from insn_emit,
1906 once for every function before code is generated. */
1907 #define INIT_EXPANDERS arm_init_expanders ()
1909 /* Length in units of the trampoline for entering a nested function. */
1910 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1912 /* Alignment required for a trampoline in bits. */
1913 #define TRAMPOLINE_ALIGNMENT 32
1914 \f
1915 /* Addressing modes, and classification of registers for them. */
1916 #define HAVE_POST_INCREMENT 1
1917 #define HAVE_PRE_INCREMENT TARGET_32BIT
1918 #define HAVE_POST_DECREMENT TARGET_32BIT
1919 #define HAVE_PRE_DECREMENT TARGET_32BIT
1920 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1921 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1922 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1923 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1925 /* Macros to check register numbers against specific register classes. */
1927 /* These assume that REGNO is a hard or pseudo reg number.
1928 They give nonzero only if REGNO is a hard reg of the suitable class
1929 or a pseudo reg currently allocated to a suitable hard reg.
1930 Since they use reg_renumber, they are safe only once reg_renumber
1931 has been allocated, which happens in local-alloc.c. */
1932 #define TEST_REGNO(R, TEST, VALUE) \
1933 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1935 /* Don't allow the pc to be used. */
1936 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1937 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1938 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1939 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1941 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1942 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1943 || (GET_MODE_SIZE (MODE) >= 4 \
1944 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1946 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1947 (TARGET_THUMB1 \
1948 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1949 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1951 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1952 For Thumb, we can not use SP + reg, so reject SP. */
1953 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1954 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1956 /* For ARM code, we don't care about the mode, but for Thumb, the index
1957 must be suitable for use in a QImode load. */
1958 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1959 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1960 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1962 /* Maximum number of registers that can appear in a valid memory address.
1963 Shifts in addresses can't be by a register. */
1964 #define MAX_REGS_PER_ADDRESS 2
1966 /* Recognize any constant value that is a valid address. */
1967 /* XXX We can address any constant, eventually... */
1968 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1969 #define CONSTANT_ADDRESS_P(X) \
1970 (GET_CODE (X) == SYMBOL_REF \
1971 && (CONSTANT_POOL_ADDRESS_P (X) \
1972 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1974 /* True if SYMBOL + OFFSET constants must refer to something within
1975 SYMBOL's section. */
1976 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1978 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1979 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1980 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1981 #endif
1983 /* Nonzero if the constant value X is a legitimate general operand.
1984 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1986 On the ARM, allow any integer (invalid ones are removed later by insn
1987 patterns), nice doubles and symbol_refs which refer to the function's
1988 constant pool XXX.
1990 When generating pic allow anything. */
1991 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1993 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1994 ( GET_CODE (X) == CONST_INT \
1995 || GET_CODE (X) == CONST_DOUBLE \
1996 || CONSTANT_ADDRESS_P (X) \
1997 || flag_pic)
1999 #define LEGITIMATE_CONSTANT_P(X) \
2000 (!arm_cannot_force_const_mem (X) \
2001 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
2002 : THUMB_LEGITIMATE_CONSTANT_P (X)))
2004 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2005 #define SUBTARGET_NAME_ENCODING_LENGTHS
2006 #endif
2008 /* This is a C fragment for the inside of a switch statement.
2009 Each case label should return the number of characters to
2010 be stripped from the start of a function's name, if that
2011 name starts with the indicated character. */
2012 #define ARM_NAME_ENCODING_LENGTHS \
2014 SUBTARGET_NAME_ENCODING_LENGTHS
2016 /* This is how to output a reference to a user-level label named NAME.
2017 `assemble_name' uses this. */
2018 #undef ASM_OUTPUT_LABELREF
2019 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2020 arm_asm_output_labelref (FILE, NAME)
2022 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
2023 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2024 if (TARGET_THUMB2) \
2025 thumb2_asm_output_opcode (STREAM);
2027 /* The EABI specifies that constructors should go in .init_array.
2028 Other targets use .ctors for compatibility. */
2029 #ifndef ARM_EABI_CTORS_SECTION_OP
2030 #define ARM_EABI_CTORS_SECTION_OP \
2032 #endif
2033 #ifndef ARM_EABI_DTORS_SECTION_OP
2034 #define ARM_EABI_DTORS_SECTION_OP \
2036 #endif
2037 #define ARM_CTORS_SECTION_OP \
2039 #define ARM_DTORS_SECTION_OP \
2042 /* Define CTORS_SECTION_ASM_OP. */
2043 #undef CTORS_SECTION_ASM_OP
2044 #undef DTORS_SECTION_ASM_OP
2045 #ifndef IN_LIBGCC2
2046 # define CTORS_SECTION_ASM_OP \
2047 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2048 # define DTORS_SECTION_ASM_OP \
2049 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2051 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2052 so we cannot use the definition above. */
2053 # ifdef __ARM_EABI__
2054 /* The .ctors section is not part of the EABI, so we do not define
2055 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2056 from trying to use it. We do define it when doing normal
2057 compilation, as .init_array can be used instead of .ctors. */
2058 /* There is no need to emit begin or end markers when using
2059 init_array; the dynamic linker will compute the size of the
2060 array itself based on special symbols created by the static
2061 linker. However, we do need to arrange to set up
2062 exception-handling here. */
2063 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2065 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2068 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2069 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2073 /* True if the operating system can merge entities with vague linkage
2074 (e.g., symbols in COMDAT group) during dynamic linking. */
2075 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2076 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2077 #endif
2079 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2081 #ifdef TARGET_UNWIND_INFO
2082 #define ARM_EABI_UNWIND_TABLES \
2083 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2084 #else
2085 #define ARM_EABI_UNWIND_TABLES 0
2086 #endif
2088 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2089 and check its validity for a certain class.
2090 We have two alternate definitions for each of them.
2091 The usual definition accepts all pseudo regs; the other rejects
2092 them unless they have been allocated suitable hard regs.
2093 The symbol REG_OK_STRICT causes the latter definition to be used.
2094 Thumb-2 has the same restrictions as arm. */
2095 #ifndef REG_OK_STRICT
2097 #define ARM_REG_OK_FOR_BASE_P(X) \
2098 (REGNO (X) <= LAST_ARM_REGNUM \
2099 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2100 || REGNO (X) == FRAME_POINTER_REGNUM \
2101 || REGNO (X) == ARG_POINTER_REGNUM)
2103 #define ARM_REG_OK_FOR_INDEX_P(X) \
2104 ((REGNO (X) <= LAST_ARM_REGNUM \
2105 && REGNO (X) != STACK_POINTER_REGNUM) \
2106 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2107 || REGNO (X) == FRAME_POINTER_REGNUM \
2108 || REGNO (X) == ARG_POINTER_REGNUM)
2110 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2111 (REGNO (X) <= LAST_LO_REGNUM \
2112 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2113 || (GET_MODE_SIZE (MODE) >= 4 \
2114 && (REGNO (X) == STACK_POINTER_REGNUM \
2115 || (X) == hard_frame_pointer_rtx \
2116 || (X) == arg_pointer_rtx)))
2118 #define REG_STRICT_P 0
2122 #define ARM_REG_OK_FOR_BASE_P(X) \
2123 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2125 #define ARM_REG_OK_FOR_INDEX_P(X) \
2126 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2128 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2129 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2131 #define REG_STRICT_P 1
2135 /* Now define some helpers in terms of the above. */
2137 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2138 (TARGET_THUMB1 \
2139 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2140 : ARM_REG_OK_FOR_BASE_P (X))
2142 /* For 16-bit Thumb, a valid index register is anything that can be used in
2143 a byte load instruction. */
2144 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2145 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2147 /* Nonzero if X is a hard reg that can be used as an index
2148 or if it is a pseudo reg. On the Thumb, the stack pointer
2149 is not suitable. */
2150 #define REG_OK_FOR_INDEX_P(X) \
2151 (TARGET_THUMB1 \
2152 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2153 : ARM_REG_OK_FOR_INDEX_P (X))
2155 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2156 For Thumb, we can not use SP + reg, so reject SP. */
2157 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2158 REG_OK_FOR_INDEX_P (X)
2159 \f
2160 #define ARM_BASE_REGISTER_RTX_P(X) \
2161 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2163 #define ARM_INDEX_REGISTER_RTX_P(X) \
2164 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2165 \f
2166 /* Define this for compatibility reasons. */
2167 #define HANDLE_PRAGMA_PACK_PUSH_POP
2169 /* Specify the machine mode that this machine uses
2170 for the index in the tablejump instruction. */
2171 #define CASE_VECTOR_MODE Pmode
2173 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
2174 || (TARGET_THUMB1 \
2175 && (optimize_size || flag_pic)))
2177 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2178 (TARGET_THUMB1 \
2179 ? (min >= 0 && max < 512 \
2180 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2181 : min >= -256 && max < 256 \
2182 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2183 : min >= 0 && max < 8192 \
2184 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2185 : min >= -4096 && max < 4096 \
2186 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2187 : SImode) \
2188 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2189 : (max >= 0x200) ? HImode \
2190 : QImode))
2192 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2193 unsigned is probably best, but may break some code. */
2194 #ifndef DEFAULT_SIGNED_CHAR
2195 #define DEFAULT_SIGNED_CHAR 0
2196 #endif
2198 /* Max number of bytes we can move from memory to memory
2199 in one reasonably fast instruction. */
2200 #define MOVE_MAX 4
2202 #undef MOVE_RATIO
2203 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2205 /* Define if operations between registers always perform the operation
2206 on the full register even if a narrower mode is specified. */
2207 #define WORD_REGISTER_OPERATIONS
2209 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2210 will either zero-extend or sign-extend. The value of this macro should
2211 be the code that says which one of the two operations is implicitly
2212 done, UNKNOWN if none. */
2213 #define LOAD_EXTEND_OP(MODE) \
2214 (TARGET_THUMB ? ZERO_EXTEND : \
2215 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2216 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2218 /* Nonzero if access to memory by bytes is slow and undesirable. */
2219 #define SLOW_BYTE_ACCESS 0
2221 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2223 /* Immediate shift counts are truncated by the output routines (or was it
2224 the assembler?). Shift counts in a register are truncated by ARM. Note
2225 that the native compiler puts too large (> 32) immediate shift counts
2226 into a register and shifts by the register, letting the ARM decide what
2227 to do instead of doing that itself. */
2228 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2229 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2230 On the arm, Y in a register is used modulo 256 for the shift. Only for
2231 rotates is modulo 32 used. */
2232 /* #define SHIFT_COUNT_TRUNCATED 1 */
2234 /* All integers have the same format so truncation is easy. */
2235 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2237 /* Calling from registers is a massive pain. */
2238 #define NO_FUNCTION_CSE 1
2240 /* The machine modes of pointers and functions */
2241 #define Pmode SImode
2242 #define FUNCTION_MODE Pmode
2244 #define ARM_FRAME_RTX(X) \
2245 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2246 || (X) == arg_pointer_rtx)
2248 /* Moves to and from memory are quite expensive */
2249 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2250 (TARGET_32BIT ? 10 : \
2251 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2252 * (CLASS == LO_REGS ? 1 : 2)))
2254 /* Try to generate sequences that don't involve branches, we can then use
2255 conditional instructions */
2256 #define BRANCH_COST(speed_p, predictable_p) \
2257 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2258 \f
2259 /* Position Independent Code. */
2260 /* We decide which register to use based on the compilation options and
2261 the assembler in use; this is more general than the APCS restriction of
2262 using sb (r9) all the time. */
2265 /* The register number of the register used to address a table of static
2266 data addresses in memory. */
2267 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2269 /* We can't directly access anything that contains a symbol,
2270 nor can we indirect via the constant pool. One exception is
2271 UNSPEC_TLS, which is always PIC. */
2272 #define LEGITIMATE_PIC_OPERAND_P(X) \
2273 (!(symbol_mentioned_p (X) \
2274 || label_mentioned_p (X) \
2275 || (GET_CODE (X) == SYMBOL_REF \
2276 && CONSTANT_POOL_ADDRESS_P (X) \
2277 && (symbol_mentioned_p (get_pool_constant (X)) \
2278 || label_mentioned_p (get_pool_constant (X))))) \
2279 || tls_mentioned_p (X))
2281 /* We need to know when we are making a constant pool; this determines
2282 whether data needs to be in the GOT or can be referenced via a GOT
2283 offset. */
2285 \f
2286 /* Handle pragmas for compatibility with Intel's compilers. */
2287 /* Also abuse this to register additional C specific EABI attributes. */
2288 #define REGISTER_TARGET_PRAGMAS() do { \
2292 arm_lang_object_attributes_init(); \
2293 } while (0)
2295 /* Condition code information. */
2296 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2297 return the mode to be used for the comparison. */
2299 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2301 #define REVERSIBLE_CC_MODE(MODE) 1
2303 #define REVERSE_CONDITION(CODE,MODE) \
2304 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2305 ? reverse_condition_maybe_unordered (code) \
2306 : reverse_condition (code))
2308 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2309 (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1))
2311 /* The arm5 clz instruction returns 32. */
2312 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2313 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2314 \f
2315 #define CC_STATUS_INIT \
2316 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2318 #undef ASM_APP_OFF
2322 /* Output a push or a pop instruction (only used when profiling).
2323 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2324 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2325 that r7 isn't used by the function profiler, so we can use it as a
2326 scratch reg. WARNING: This isn't safe in the general case! It may be
2327 sensitive to future changes in final.c:profile_function. */
2328 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2329 do \
2330 { \
2331 if (TARGET_ARM) \
2333 STACK_POINTER_REGNUM, REGNO); \
2334 else if (TARGET_THUMB1 \
2335 && (REGNO) == STATIC_CHAIN_REGNUM) \
2336 { \
2340 } \
2341 else \
2343 } while (0)
2346 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2347 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2348 do \
2349 { \
2350 if (TARGET_ARM) \
2352 STACK_POINTER_REGNUM, REGNO); \
2353 else if (TARGET_THUMB1 \
2354 && (REGNO) == STATIC_CHAIN_REGNUM) \
2355 { \
2359 } \
2360 else \
2362 } while (0)
2364 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2365 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2367 /* This is how to output a label which precedes a jumptable. Since
2368 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2369 #undef ASM_OUTPUT_CASE_LABEL
2370 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2371 do \
2372 { \
2373 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2374 ASM_OUTPUT_ALIGN (FILE, 2); \
2375 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2376 } \
2377 while (0)
2379 /* Make sure subsequent insns are aligned after a TBB. */
2380 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2381 do \
2382 { \
2383 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2384 ASM_OUTPUT_ALIGN (FILE, 1); \
2385 } \
2386 while (0)
2388 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2389 do \
2390 { \
2391 if (TARGET_THUMB) \
2392 { \
2393 if (is_called_in_ARM_mode (DECL) \
2394 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2395 && cfun->is_thunk)) \
2397 else if (TARGET_THUMB1) \
2399 else \
2401 } \
2402 if (TARGET_POKE_FUNCTION_NAME) \
2403 arm_poke_function_name (STREAM, (const char *) NAME); \
2404 } \
2405 while (0)
2407 /* For aliases of functions we use .thumb_set instead. */
2408 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2409 do \
2410 { \
2411 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2412 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2413 \
2414 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2415 { \
2417 assemble_name (FILE, LABEL1); \
2419 assemble_name (FILE, LABEL2); \
2421 } \
2422 else \
2423 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2424 } \
2425 while (0)
2427 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2428 /* To support -falign-* switches we need to use .p2align so
2429 that alignment directives in code sections will be padded
2430 with no-op instructions, rather than zeroes. */
2431 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2432 if ((LOG) != 0) \
2433 { \
2434 if ((MAX_SKIP) == 0) \
2436 else \
2438 (int) (LOG), (int) (MAX_SKIP)); \
2439 }
2440 #endif
2441 \f
2442 /* Add two bytes to the length of conditionally executed Thumb-2
2443 instructions for the IT instruction. */
2444 #define ADJUST_INSN_LENGTH(insn, length) \
2445 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2446 length += 2;
2448 /* Only perform branch elimination (by making instructions conditional) if
2449 we're optimizing. For Thumb-2 check if any IT instructions need
2450 outputting. */
2451 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2452 if (TARGET_ARM && optimize) \
2453 arm_final_prescan_insn (INSN); \
2454 else if (TARGET_THUMB2) \
2455 thumb2_final_prescan_insn (INSN); \
2456 else if (TARGET_THUMB1) \
2457 thumb1_final_prescan_insn (INSN)
2459 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2460 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2461 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2462 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2463 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2464 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2465 : 0))))
2467 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2468 if (arm_output_addr_const_extra (file, x) == FALSE) \
2469 goto fail
2471 /* A C expression whose value is RTL representing the value of the return
2472 address for the frame COUNT steps up from the current frame. */
2474 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2475 arm_return_addr (COUNT, FRAME)
2477 /* Mask of the bits in the PC that contain the real return address
2478 when running in 26-bit mode. */
2479 #define RETURN_ADDR_MASK26 (0x03fffffc)
2481 /* Pick up the return address upon entry to a procedure. Used for
2482 dwarf2 unwind information. This also enables the table driven
2483 mechanism. */
2484 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2485 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2487 /* Used to mask out junk bits from the return address, such as
2488 processor state, interrupt status, condition codes and the like. */
2489 #define MASK_RETURN_ADDR \
2490 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2491 in 26 bit mode, the condition codes must be masked out of the \
2492 return address. This does not apply to ARM6 and later processors \
2494 ((arm_arch4 || TARGET_THUMB) \
2495 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2496 : arm_gen_return_addr_mask ())
2498 \f
2499 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2500 symbolic names defined here (which would require too much duplication).
2501 FIXME? */
2502 enum arm_builtins
2503 {
2504 ARM_BUILTIN_GETWCX,
2505 ARM_BUILTIN_SETWCX,
2507 ARM_BUILTIN_WZERO,
2509 ARM_BUILTIN_WAVG2BR,
2510 ARM_BUILTIN_WAVG2HR,
2511 ARM_BUILTIN_WAVG2B,
2512 ARM_BUILTIN_WAVG2H,
2514 ARM_BUILTIN_WACCB,
2515 ARM_BUILTIN_WACCH,
2516 ARM_BUILTIN_WACCW,
2518 ARM_BUILTIN_WMACS,
2519 ARM_BUILTIN_WMACSZ,
2520 ARM_BUILTIN_WMACU,
2521 ARM_BUILTIN_WMACUZ,
2523 ARM_BUILTIN_WSADB,
2524 ARM_BUILTIN_WSADBZ,
2525 ARM_BUILTIN_WSADH,
2526 ARM_BUILTIN_WSADHZ,
2528 ARM_BUILTIN_WALIGN,
2530 ARM_BUILTIN_TMIA,
2531 ARM_BUILTIN_TMIAPH,
2532 ARM_BUILTIN_TMIABB,
2533 ARM_BUILTIN_TMIABT,
2534 ARM_BUILTIN_TMIATB,
2535 ARM_BUILTIN_TMIATT,
2537 ARM_BUILTIN_TMOVMSKB,
2538 ARM_BUILTIN_TMOVMSKH,
2539 ARM_BUILTIN_TMOVMSKW,
2541 ARM_BUILTIN_TBCSTB,
2542 ARM_BUILTIN_TBCSTH,
2543 ARM_BUILTIN_TBCSTW,
2545 ARM_BUILTIN_WMADDS,
2546 ARM_BUILTIN_WMADDU,
2548 ARM_BUILTIN_WPACKHSS,
2549 ARM_BUILTIN_WPACKWSS,
2550 ARM_BUILTIN_WPACKDSS,
2551 ARM_BUILTIN_WPACKHUS,
2552 ARM_BUILTIN_WPACKWUS,
2553 ARM_BUILTIN_WPACKDUS,
2555 ARM_BUILTIN_WADDB,
2556 ARM_BUILTIN_WADDH,
2557 ARM_BUILTIN_WADDW,
2558 ARM_BUILTIN_WADDSSB,
2559 ARM_BUILTIN_WADDSSH,
2560 ARM_BUILTIN_WADDSSW,
2561 ARM_BUILTIN_WADDUSB,
2562 ARM_BUILTIN_WADDUSH,
2563 ARM_BUILTIN_WADDUSW,
2564 ARM_BUILTIN_WSUBB,
2565 ARM_BUILTIN_WSUBH,
2566 ARM_BUILTIN_WSUBW,
2567 ARM_BUILTIN_WSUBSSB,
2568 ARM_BUILTIN_WSUBSSH,
2569 ARM_BUILTIN_WSUBSSW,
2570 ARM_BUILTIN_WSUBUSB,
2571 ARM_BUILTIN_WSUBUSH,
2572 ARM_BUILTIN_WSUBUSW,
2574 ARM_BUILTIN_WAND,
2575 ARM_BUILTIN_WANDN,
2576 ARM_BUILTIN_WOR,
2577 ARM_BUILTIN_WXOR,
2579 ARM_BUILTIN_WCMPEQB,
2580 ARM_BUILTIN_WCMPEQH,
2581 ARM_BUILTIN_WCMPEQW,
2582 ARM_BUILTIN_WCMPGTUB,
2583 ARM_BUILTIN_WCMPGTUH,
2584 ARM_BUILTIN_WCMPGTUW,
2585 ARM_BUILTIN_WCMPGTSB,
2586 ARM_BUILTIN_WCMPGTSH,
2587 ARM_BUILTIN_WCMPGTSW,
2589 ARM_BUILTIN_TEXTRMSB,
2590 ARM_BUILTIN_TEXTRMSH,
2591 ARM_BUILTIN_TEXTRMSW,
2592 ARM_BUILTIN_TEXTRMUB,
2593 ARM_BUILTIN_TEXTRMUH,
2594 ARM_BUILTIN_TEXTRMUW,
2595 ARM_BUILTIN_TINSRB,
2596 ARM_BUILTIN_TINSRH,
2597 ARM_BUILTIN_TINSRW,
2599 ARM_BUILTIN_WMAXSW,
2600 ARM_BUILTIN_WMAXSH,
2601 ARM_BUILTIN_WMAXSB,
2602 ARM_BUILTIN_WMAXUW,
2603 ARM_BUILTIN_WMAXUH,
2604 ARM_BUILTIN_WMAXUB,
2605 ARM_BUILTIN_WMINSW,
2606 ARM_BUILTIN_WMINSH,
2607 ARM_BUILTIN_WMINSB,
2608 ARM_BUILTIN_WMINUW,
2609 ARM_BUILTIN_WMINUH,
2610 ARM_BUILTIN_WMINUB,
2612 ARM_BUILTIN_WMULUM,
2613 ARM_BUILTIN_WMULSM,
2614 ARM_BUILTIN_WMULUL,
2616 ARM_BUILTIN_PSADBH,
2617 ARM_BUILTIN_WSHUFH,
2619 ARM_BUILTIN_WSLLH,
2620 ARM_BUILTIN_WSLLW,
2621 ARM_BUILTIN_WSLLD,
2622 ARM_BUILTIN_WSRAH,
2623 ARM_BUILTIN_WSRAW,
2624 ARM_BUILTIN_WSRAD,
2625 ARM_BUILTIN_WSRLH,
2626 ARM_BUILTIN_WSRLW,
2627 ARM_BUILTIN_WSRLD,
2628 ARM_BUILTIN_WRORH,
2629 ARM_BUILTIN_WRORW,
2630 ARM_BUILTIN_WRORD,
2631 ARM_BUILTIN_WSLLHI,
2632 ARM_BUILTIN_WSLLWI,
2633 ARM_BUILTIN_WSLLDI,
2634 ARM_BUILTIN_WSRAHI,
2635 ARM_BUILTIN_WSRAWI,
2636 ARM_BUILTIN_WSRADI,
2637 ARM_BUILTIN_WSRLHI,
2638 ARM_BUILTIN_WSRLWI,
2639 ARM_BUILTIN_WSRLDI,
2640 ARM_BUILTIN_WRORHI,
2641 ARM_BUILTIN_WRORWI,
2642 ARM_BUILTIN_WRORDI,
2644 ARM_BUILTIN_WUNPCKIHB,
2645 ARM_BUILTIN_WUNPCKIHH,
2646 ARM_BUILTIN_WUNPCKIHW,
2647 ARM_BUILTIN_WUNPCKILB,
2648 ARM_BUILTIN_WUNPCKILH,
2649 ARM_BUILTIN_WUNPCKILW,
2651 ARM_BUILTIN_WUNPCKEHSB,
2652 ARM_BUILTIN_WUNPCKEHSH,
2653 ARM_BUILTIN_WUNPCKEHSW,
2654 ARM_BUILTIN_WUNPCKEHUB,
2655 ARM_BUILTIN_WUNPCKEHUH,
2656 ARM_BUILTIN_WUNPCKEHUW,
2657 ARM_BUILTIN_WUNPCKELSB,
2658 ARM_BUILTIN_WUNPCKELSH,
2659 ARM_BUILTIN_WUNPCKELSW,
2660 ARM_BUILTIN_WUNPCKELUB,
2661 ARM_BUILTIN_WUNPCKELUH,
2662 ARM_BUILTIN_WUNPCKELUW,
2664 ARM_BUILTIN_THREAD_POINTER,
2666 ARM_BUILTIN_NEON_BASE,
2669 };
2671 /* Do not emit .note.GNU-stack by default. */
2672 #ifndef NEED_INDICATE_EXEC_STACK
2673 #define NEED_INDICATE_EXEC_STACK 0
2674 #endif
2676 /* The maximum number of parallel loads or stores we support in an ldm/stm
2677 instruction. */
2678 #define MAX_LDM_STM_OPS 4