| blob | b45f675b4bc8eb97f530e1099750072d5c773dec |
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
29 /* We can't use enum machine_mode inside a generator file because it
30 hasn't been created yet; we shouldn't be using any code that
31 needs the real definition though, so this ought to be safe. */
32 #ifdef GENERATOR_FILE
33 #define MACHMODE int
34 #else
36 #define MACHMODE enum machine_mode
37 #endif
41 /* The architecture define. */
44 /* Target CPU builtins. */
45 #define TARGET_CPU_CPP_BUILTINS() \
46 do \
47 { \
48 /* Define __arm__ even when in thumb mode, for \
52 if (TARGET_THUMB) \
54 if (TARGET_THUMB2) \
56 \
57 if (TARGET_BIG_END) \
58 { \
60 if (TARGET_THUMB) \
62 if (TARGET_LITTLE_WORDS) \
64 } \
65 else \
66 { \
68 if (TARGET_THUMB) \
70 } \
71 \
72 if (TARGET_SOFT_FLOAT) \
74 \
75 if (TARGET_VFP) \
77 \
78 if (TARGET_NEON) \
80 \
81 /* Add a define for interworking. \
83 if (arm_cpp_interwork) \
85 \
88 \
89 builtin_define (arm_arch_name); \
90 if (arm_arch_cirrus) \
92 if (arm_arch_xscale) \
94 if (arm_arch_iwmmxt) \
96 if (TARGET_AAPCS_BASED) \
98 } while (0)
100 /* The various ARM cores. */
101 enum processor_type
102 {
103 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
104 IDENT,
106 #undef ARM_CORE
107 /* Used to indicate that no processor has been specified. */
108 arm_none
109 };
111 enum target_cpus
112 {
113 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
114 TARGET_CPU_##IDENT,
116 #undef ARM_CORE
117 TARGET_CPU_generic
118 };
120 /* The processor for which instructions should be scheduled. */
124 {
127 }
128 arm_cc;
132 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
137 /* The label of the current constant pool. */
139 /* Set to 1 when a return insn is output, this means that the epilogue
140 is not needed. */
142 /* Callback to output language specific object attributes. */
144 \f
145 /* Just in case configure has failed to define anything. */
146 #ifndef TARGET_CPU_DEFAULT
147 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
148 #endif
151 #undef CPP_SPEC
153 %{msoft-float:%{mhard-float: \
154 %e-msoft-float and -mhard_float may not be used together}} \
155 %{mbig-endian:%{mlittle-endian: \
156 %e-mbig-endian and -mlittle-endian may not be used together}}"
158 #ifndef CC1_SPEC
160 #endif
162 /* This macro defines names of additional specifications to put in the specs
163 that can be used in various specifications like CC1_SPEC. Its definition
164 is an initializer with a subgrouping for each command option.
166 Each subgrouping contains a string constant, that defines the
167 specification name, and a string constant that used by the GCC driver
168 program.
170 Do not define this macro if it does not need to do anything. */
171 #define EXTRA_SPECS \
173 SUBTARGET_EXTRA_SPECS
175 #ifndef SUBTARGET_EXTRA_SPECS
176 #define SUBTARGET_EXTRA_SPECS
177 #endif
179 #ifndef SUBTARGET_CPP_SPEC
181 #endif
182 \f
183 /* Run-time Target Specification. */
184 #ifndef TARGET_VERSION
186 #endif
188 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
189 /* Use hardware floating point instructions. */
190 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
191 /* Use hardware floating point calling convention. */
192 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
193 #define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA)
194 #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
195 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
196 #define TARGET_IWMMXT (arm_arch_iwmmxt)
197 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
198 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
199 #define TARGET_ARM (! TARGET_THUMB)
201 #define TARGET_BACKTRACE (leaf_function_p () \
202 ? TARGET_TPCS_LEAF_FRAME \
203 : TARGET_TPCS_FRAME)
204 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
205 #define TARGET_AAPCS_BASED \
206 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
208 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
209 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
211 /* Only 16-bit thumb code. */
212 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
213 /* Arm or Thumb-2 32-bit code. */
214 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
215 /* 32-bit Thumb-2 code. */
216 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
217 /* Thumb-1 only. */
218 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
219 /* FPA emulator without LFM. */
220 #define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
222 /* The following two macros concern the ability to execute coprocessor
223 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
224 only ever tested when we know we are generating for VFP hardware; we need
225 to be more careful with TARGET_NEON as noted below. */
227 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
228 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
230 /* FPU supports VFPv3 instructions. */
231 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
233 /* FPU only supports VFP single-precision instructions. */
234 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
236 /* FPU supports VFP double-precision instructions. */
237 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
239 /* FPU supports half-precision floating-point with NEON element load/store. */
240 #define TARGET_NEON_FP16 \
241 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
243 /* FPU supports VFP half-precision floating-point. */
244 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
246 /* FPU supports Neon instructions. The setting of this macro gets
247 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
248 and TARGET_HARD_FLOAT to ensure that NEON instructions are
249 available. */
250 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
251 && TARGET_VFP && arm_fpu_desc->neon)
253 /* "DSP" multiply instructions, eg. SMULxy. */
254 #define TARGET_DSP_MULTIPLY \
255 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
256 /* Integer SIMD instructions, and extend-accumulate instructions. */
257 #define TARGET_INT_SIMD \
258 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
260 /* Should MOVW/MOVT be used in preference to a constant pool. */
261 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
263 /* We could use unified syntax for arm mode, but for now we just use it
264 for Thumb-2. */
265 #define TARGET_UNIFIED_ASM TARGET_THUMB2
268 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
269 then TARGET_AAPCS_BASED must be true -- but the converse does not
270 hold. TARGET_BPABI implies the use of the BPABI runtime library,
271 etc., in addition to just the AAPCS calling conventions. */
272 #ifndef TARGET_BPABI
273 #define TARGET_BPABI false
274 #endif
276 /* Support for a compile-time default CPU, et cetera. The rules are:
277 --with-arch is ignored if -march or -mcpu are specified.
278 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
279 by --with-arch.
280 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
281 by -march).
282 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
283 specified.
284 --with-fpu is ignored if -mfpu is specified.
285 --with-abi is ignored is -mabi is specified. */
286 #define OPTION_DEFAULT_SPECS \
296 /* Which floating point model to use. */
297 enum arm_fp_model
298 {
299 ARM_FP_MODEL_UNKNOWN,
300 /* FPA model (Hardware or software). */
301 ARM_FP_MODEL_FPA,
302 /* Cirrus Maverick floating point model. */
303 ARM_FP_MODEL_MAVERICK,
304 /* VFP floating point model. */
305 ARM_FP_MODEL_VFP
306 };
308 enum vfp_reg_type
309 {
311 VFP_REG_D16,
312 VFP_REG_D32,
313 VFP_REG_SINGLE
314 };
317 {
326 /* Which floating point hardware to schedule for. */
329 enum float_abi_type
330 {
331 ARM_FLOAT_ABI_SOFT,
332 ARM_FLOAT_ABI_SOFTFP,
333 ARM_FLOAT_ABI_HARD
334 };
338 #ifndef TARGET_DEFAULT_FLOAT_ABI
339 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
340 #endif
342 /* Which __fp16 format to use.
343 The enumeration values correspond to the numbering for the
344 Tag_ABI_FP_16bit_format attribute.
345 */
346 enum arm_fp16_format_type
347 {
351 };
354 #define LARGEST_EXPONENT_IS_NORMAL(bits) \
355 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
357 /* Which ABI to use. */
358 enum arm_abi_type
359 {
360 ARM_ABI_APCS,
361 ARM_ABI_ATPCS,
362 ARM_ABI_AAPCS,
363 ARM_ABI_IWMMXT,
364 ARM_ABI_AAPCS_LINUX
365 };
369 #ifndef ARM_DEFAULT_ABI
370 #define ARM_DEFAULT_ABI ARM_ABI_APCS
371 #endif
373 /* Which thread pointer access sequence to use. */
375 TP_AUTO,
376 TP_SOFT,
377 TP_CP15
378 };
382 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
385 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
388 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
391 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
394 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
397 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
400 /* Nonzero if instructions not present in the 'M' profile can be used. */
403 /* Nonzero if instructions present in ARMv7E-M can be used. */
406 /* Nonzero if this chip can benefit from load scheduling. */
409 /* Nonzero if generating thumb code. */
412 /* Nonzero if this chip is a StrongARM. */
415 /* Nonzero if this chip is a Cirrus variant. */
418 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
421 /* Nonzero if this chip is an XScale. */
424 /* Nonzero if tuning for XScale. */
427 /* Nonzero if tuning for stores via the write buffer. */
430 /* Nonzero if tuning for Cortex-A9. */
433 /* Nonzero if we should define __THUMB_INTERWORK__ in the
434 preprocessor.
435 XXX This is a bit of a hack, it's intended to help work around
436 problems in GLD which doesn't understand that armv5t code is
437 interworking clean. */
440 /* Nonzero if chip supports Thumb 2. */
443 /* Nonzero if chip supports integer division instruction. */
446 #ifndef TARGET_DEFAULT
447 #define TARGET_DEFAULT (MASK_APCS_FRAME)
448 #endif
450 /* The frame pointer register used in gcc has nothing to do with debugging;
451 that is controlled by the APCS-FRAME option. */
452 #define CAN_DEBUG_WITHOUT_FP
454 #define OVERRIDE_OPTIONS arm_override_options ()
456 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
457 arm_optimization_options ((LEVEL), (SIZE))
459 /* Nonzero if PIC code requires explicit qualifiers to generate
460 PLT and GOT relocs rather than the assembler doing so implicitly.
461 Subtargets can override these if required. */
462 #ifndef NEED_GOT_RELOC
463 #define NEED_GOT_RELOC 0
464 #endif
465 #ifndef NEED_PLT_RELOC
466 #define NEED_PLT_RELOC 0
467 #endif
469 /* Nonzero if we need to refer to the GOT with a PC-relative
470 offset. In other words, generate
472 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
474 rather than
476 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
478 The default is true, which matches NetBSD. Subtargets can
479 override this if required. */
480 #ifndef GOT_PCREL
481 #define GOT_PCREL 1
482 #endif
483 \f
484 /* Target machine storage Layout. */
487 /* Define this macro if it is advisable to hold scalars in registers
488 in a wider mode than that declared by the program. In such cases,
489 the value is constrained to be within the bounds of the declared
490 type, but kept valid in the wider mode. The signedness of the
491 extension may differ from that of the type. */
493 /* It is far faster to zero extend chars than to sign extend them */
495 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
496 if (GET_MODE_CLASS (MODE) == MODE_INT \
497 && GET_MODE_SIZE (MODE) < 4) \
498 { \
499 if (MODE == QImode) \
500 UNSIGNEDP = 1; \
501 else if (MODE == HImode) \
502 UNSIGNEDP = 1; \
503 (MODE) = SImode; \
504 }
506 /* Define this if most significant bit is lowest numbered
507 in instructions that operate on numbered bit-fields. */
508 #define BITS_BIG_ENDIAN 0
510 /* Define this if most significant byte of a word is the lowest numbered.
511 Most ARM processors are run in little endian mode, so that is the default.
512 If you want to have it run-time selectable, change the definition in a
513 cover file to be TARGET_BIG_ENDIAN. */
514 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
516 /* Define this if most significant word of a multiword number is the lowest
517 numbered.
518 This is always false, even when in big-endian mode. */
519 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
521 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
522 on processor pre-defineds when compiling libgcc2.c. */
523 #if defined(__ARMEB__) && !defined(__ARMWEL__)
524 #define LIBGCC2_WORDS_BIG_ENDIAN 1
525 #else
526 #define LIBGCC2_WORDS_BIG_ENDIAN 0
527 #endif
529 /* Define this if most significant word of doubles is the lowest numbered.
530 The rules are different based on whether or not we use FPA-format,
531 VFP-format or some other floating point co-processor's format doubles. */
532 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
534 #define UNITS_PER_WORD 4
536 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
537 registers when autovectorizing for Neon, at least until multiple vector
538 widths are supported properly by the middle-end. */
539 #define UNITS_PER_SIMD_WORD(MODE) \
540 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
542 /* True if natural alignment is used for doubleword types. */
543 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
545 #define DOUBLEWORD_ALIGNMENT 64
547 #define PARM_BOUNDARY 32
549 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
551 #define PREFERRED_STACK_BOUNDARY \
552 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
554 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
556 /* The lowest bit is used to indicate Thumb-mode functions, so the
557 vbit must go into the delta field of pointers to member
558 functions. */
559 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
561 #define EMPTY_FIELD_BOUNDARY 32
563 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
565 /* XXX Blah -- this macro is used directly by libobjc. Since it
566 supports no vector modes, cut out the complexity and fall back
567 on BIGGEST_FIELD_ALIGNMENT. */
568 #ifdef IN_TARGET_LIBS
569 #define BIGGEST_FIELD_ALIGNMENT 64
570 #endif
572 /* Make strings word-aligned so strcpy from constants will be faster. */
573 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
575 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
576 ((TREE_CODE (EXP) == STRING_CST \
577 && !optimize_size \
578 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
579 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
581 /* Align definitions of arrays, unions and structures so that
582 initializations and copies can be made more efficient. This is not
583 ABI-changing, so it only affects places where we can see the
584 definition. */
585 #define DATA_ALIGNMENT(EXP, ALIGN) \
586 ((((ALIGN) < BITS_PER_WORD) \
587 && (TREE_CODE (EXP) == ARRAY_TYPE \
588 || TREE_CODE (EXP) == UNION_TYPE \
589 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
591 /* Similarly, make sure that objects on the stack are sensibly aligned. */
592 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
594 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
595 value set in previous versions of this toolchain was 8, which produces more
596 compact structures. The command line option -mstructure_size_boundary=<n>
597 can be used to change this value. For compatibility with the ARM SDK
598 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
599 0020D) page 2-20 says "Structures are aligned on word boundaries".
600 The AAPCS specifies a value of 8. */
601 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
604 /* This is the value used to initialize arm_structure_size_boundary. If a
605 particular arm target wants to change the default value it should change
606 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
607 for an example of this. */
608 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
609 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
610 #endif
612 /* Nonzero if move instructions will actually fail to work
613 when given unaligned data. */
614 #define STRICT_ALIGNMENT 1
616 /* wchar_t is unsigned under the AAPCS. */
617 #ifndef WCHAR_TYPE
620 #define WCHAR_TYPE_SIZE BITS_PER_WORD
621 #endif
623 #ifndef SIZE_TYPE
625 #endif
627 #ifndef PTRDIFF_TYPE
629 #endif
631 /* AAPCS requires that structure alignment is affected by bitfields. */
632 #ifndef PCC_BITFIELD_TYPE_MATTERS
633 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
634 #endif
636 \f
637 /* Standard register usage. */
639 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
640 (S - saved over call).
642 r0 * argument word/integer result
643 r1-r3 argument word
645 r4-r8 S register variable
646 r9 S (rfp) register variable (real frame pointer)
648 r10 F S (sl) stack limit (used by -mapcs-stack-check)
649 r11 F S (fp) argument pointer
650 r12 (ip) temp workspace
651 r13 F S (sp) lower end of current stack frame
652 r14 (lr) link address/workspace
653 r15 F (pc) program counter
655 f0 floating point result
656 f1-f3 floating point scratch
658 f4-f7 S floating point variable
660 cc This is NOT a real register, but is used internally
661 to represent things that use or set the condition
662 codes.
663 sfp This isn't either. It is used during rtl generation
664 since the offset between the frame pointer and the
665 auto's isn't known until after register allocation.
666 afp Nor this, we only need this because of non-local
667 goto. Without it fp appears to be used and the
668 elimination code won't get rid of sfp. It tracks
669 fp exactly at all times.
671 *: See CONDITIONAL_REGISTER_USAGE */
673 /*
674 mvf0 Cirrus floating point result
675 mvf1-mvf3 Cirrus floating point scratch
676 mvf4-mvf15 S Cirrus floating point variable. */
678 /* s0-s15 VFP scratch (aka d0-d7).
679 s16-s31 S VFP variable (aka d8-d15).
680 vfpcc Not a real register. Represents the VFP condition
681 code flags. */
683 /* The stack backtrace structure is as follows:
684 fp points to here: | save code pointer | [fp]
685 | return link value | [fp, #-4]
686 | return sp value | [fp, #-8]
687 | return fp value | [fp, #-12]
688 [| saved r10 value |]
689 [| saved r9 value |]
690 [| saved r8 value |]
691 [| saved r7 value |]
692 [| saved r6 value |]
693 [| saved r5 value |]
694 [| saved r4 value |]
695 [| saved r3 value |]
696 [| saved r2 value |]
697 [| saved r1 value |]
698 [| saved r0 value |]
699 [| saved f7 value |] three words
700 [| saved f6 value |] three words
701 [| saved f5 value |] three words
702 [| saved f4 value |] three words
703 r0-r3 are not normally saved in a C function. */
705 /* 1 for registers that have pervasive standard uses
706 and are not available for the register allocator. */
707 #define FIXED_REGISTERS \
708 { \
709 0,0,0,0,0,0,0,0, \
710 0,0,0,0,0,1,0,1, \
711 0,0,0,0,0,0,0,0, \
712 1,1,1, \
713 1,1,1,1,1,1,1,1, \
714 1,1,1,1,1,1,1,1, \
715 1,1,1,1,1,1,1,1, \
716 1,1,1,1,1,1,1,1, \
717 1,1,1,1, \
718 1,1,1,1,1,1,1,1, \
719 1,1,1,1,1,1,1,1, \
720 1,1,1,1,1,1,1,1, \
721 1,1,1,1,1,1,1,1, \
722 1,1,1,1,1,1,1,1, \
723 1,1,1,1,1,1,1,1, \
724 1,1,1,1,1,1,1,1, \
725 1,1,1,1,1,1,1,1, \
726 1 \
727 }
729 /* 1 for registers not available across function calls.
730 These must include the FIXED_REGISTERS and also any
731 registers that can be used without being saved.
732 The latter must include the registers where values are returned
733 and the register where structure-value addresses are passed.
734 Aside from that, you can include as many other registers as you like.
735 The CC is not preserved over function calls on the ARM 6, so it is
736 easier to assume this for all. SFP is preserved, since FP is. */
737 #define CALL_USED_REGISTERS \
738 { \
739 1,1,1,1,0,0,0,0, \
740 0,0,0,0,1,1,1,1, \
741 1,1,1,1,0,0,0,0, \
742 1,1,1, \
743 1,1,1,1,1,1,1,1, \
744 1,1,1,1,1,1,1,1, \
745 1,1,1,1,1,1,1,1, \
746 1,1,1,1,1,1,1,1, \
747 1,1,1,1, \
748 1,1,1,1,1,1,1,1, \
749 1,1,1,1,1,1,1,1, \
750 1,1,1,1,1,1,1,1, \
751 1,1,1,1,1,1,1,1, \
752 1,1,1,1,1,1,1,1, \
753 1,1,1,1,1,1,1,1, \
754 1,1,1,1,1,1,1,1, \
755 1,1,1,1,1,1,1,1, \
756 1 \
757 }
759 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
760 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
761 #endif
763 #define CONDITIONAL_REGISTER_USAGE \
764 { \
765 int regno; \
766 \
767 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
768 { \
769 for (regno = FIRST_FPA_REGNUM; \
770 regno <= LAST_FPA_REGNUM; ++regno) \
771 fixed_regs[regno] = call_used_regs[regno] = 1; \
772 } \
773 \
774 if (TARGET_THUMB1 && optimize_size) \
775 { \
776 /* When optimizing for size on Thumb-1, it's better not \
777 to use the HI regs, because of the overhead of \
779 for (regno = FIRST_HI_REGNUM; \
780 regno <= LAST_HI_REGNUM; ++regno) \
781 fixed_regs[regno] = call_used_regs[regno] = 1; \
782 } \
783 \
784 /* The link register can be clobbered by any branch insn, \
785 but we have no way to track that at present, so mark \
787 if (TARGET_THUMB1) \
788 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
789 \
790 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
791 { \
792 if (TARGET_MAVERICK) \
793 { \
794 for (regno = FIRST_FPA_REGNUM; \
795 regno <= LAST_FPA_REGNUM; ++ regno) \
796 fixed_regs[regno] = call_used_regs[regno] = 1; \
797 for (regno = FIRST_CIRRUS_FP_REGNUM; \
798 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
799 { \
800 fixed_regs[regno] = 0; \
801 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
802 } \
803 } \
804 if (TARGET_VFP) \
805 { \
806 /* VFPv3 registers are disabled when earlier VFP \
807 versions are selected due to the definition of \
809 for (regno = FIRST_VFP_REGNUM; \
810 regno <= LAST_VFP_REGNUM; ++ regno) \
811 { \
812 fixed_regs[regno] = 0; \
813 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
814 || regno >= FIRST_VFP_REGNUM + 32; \
815 } \
816 } \
817 } \
818 \
819 if (TARGET_REALLY_IWMMXT) \
820 { \
821 regno = FIRST_IWMMXT_GR_REGNUM; \
822 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
823 and wCG1 as call-preserved registers. The 2002/11/21 \
824 revision changed this so that all wCG registers are \
826 for (regno = FIRST_IWMMXT_GR_REGNUM; \
827 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
828 fixed_regs[regno] = 0; \
829 /* The XScale ABI has wR0 - wR9 as scratch registers, \
831 for (regno = FIRST_IWMMXT_REGNUM; \
832 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
833 { \
834 fixed_regs[regno] = 0; \
835 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
836 } \
837 } \
838 \
839 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
840 { \
841 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
842 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
843 } \
844 else if (TARGET_APCS_STACK) \
845 { \
846 fixed_regs[10] = 1; \
847 call_used_regs[10] = 1; \
848 } \
849 /* -mcaller-super-interworking reserves r11 for calls to \
850 _interwork_r11_call_via_rN(). Making the register global \
851 is an easy way of ensuring that it remains valid for all \
853 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
854 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
855 { \
856 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
857 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
858 if (TARGET_CALLER_INTERWORKING) \
859 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
860 } \
861 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
862 }
864 /* These are a couple of extensions to the formats accepted
865 by asm_fprintf:
866 %@ prints out ASM_COMMENT_START
867 %r prints out REGISTER_PREFIX reg_names[arg] */
868 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
870 fputs (ASM_COMMENT_START, FILE); \
871 break; \
872 \
874 fputs (REGISTER_PREFIX, FILE); \
875 fputs (reg_names [va_arg (ARGS, int)], FILE); \
876 break;
878 /* Round X up to the nearest word. */
879 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
881 /* Convert fron bytes to ints. */
882 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
884 /* The number of (integer) registers required to hold a quantity of type MODE.
885 Also used for VFP registers. */
886 #define ARM_NUM_REGS(MODE) \
887 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
889 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
890 #define ARM_NUM_REGS2(MODE, TYPE) \
891 ARM_NUM_INTS ((MODE) == BLKmode ? \
892 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
894 /* The number of (integer) argument register available. */
895 #define NUM_ARG_REGS 4
897 /* And similarly for the VFP. */
898 #define NUM_VFP_ARG_REGS 16
900 /* Return the register number of the N'th (integer) argument. */
901 #define ARG_REGISTER(N) (N - 1)
903 /* Specify the registers used for certain standard purposes.
904 The values of these macros are register numbers. */
906 /* The number of the last argument register. */
907 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
909 /* The numbers of the Thumb register ranges. */
910 #define FIRST_LO_REGNUM 0
911 #define LAST_LO_REGNUM 7
912 #define FIRST_HI_REGNUM 8
913 #define LAST_HI_REGNUM 11
915 #ifndef TARGET_UNWIND_INFO
916 /* We use sjlj exceptions for backwards compatibility. */
917 #define MUST_USE_SJLJ_EXCEPTIONS 1
918 #endif
920 /* We can generate DWARF2 Unwind info, even though we don't use it. */
921 #define DWARF2_UNWIND_INFO 1
923 /* Use r0 and r1 to pass exception handling information. */
924 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
926 /* The register that holds the return address in exception handlers. */
927 #define ARM_EH_STACKADJ_REGNUM 2
928 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
930 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
931 as an invisible last argument (possible since varargs don't exist in
932 Pascal), so the following is not true. */
933 #define STATIC_CHAIN_REGNUM 12
935 /* Define this to be where the real frame pointer is if it is not possible to
936 work out the offset between the frame pointer and the automatic variables
937 until after register allocation has taken place. FRAME_POINTER_REGNUM
938 should point to a special register that we will make sure is eliminated.
940 For the Thumb we have another problem. The TPCS defines the frame pointer
941 as r11, and GCC believes that it is always possible to use the frame pointer
942 as base register for addressing purposes. (See comments in
943 find_reloads_address()). But - the Thumb does not allow high registers,
944 including r11, to be used as base address registers. Hence our problem.
946 The solution used here, and in the old thumb port is to use r7 instead of
947 r11 as the hard frame pointer and to have special code to generate
948 backtrace structures on the stack (if required to do so via a command line
949 option) using r11. This is the only 'user visible' use of r11 as a frame
950 pointer. */
951 #define ARM_HARD_FRAME_POINTER_REGNUM 11
952 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
954 #define HARD_FRAME_POINTER_REGNUM \
955 (TARGET_ARM \
956 ? ARM_HARD_FRAME_POINTER_REGNUM \
957 : THUMB_HARD_FRAME_POINTER_REGNUM)
959 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
961 /* Register to use for pushing function arguments. */
962 #define STACK_POINTER_REGNUM SP_REGNUM
964 /* ARM floating pointer registers. */
965 #define FIRST_FPA_REGNUM 16
966 #define LAST_FPA_REGNUM 23
967 #define IS_FPA_REGNUM(REGNUM) \
968 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
970 #define FIRST_IWMMXT_GR_REGNUM 43
971 #define LAST_IWMMXT_GR_REGNUM 46
972 #define FIRST_IWMMXT_REGNUM 47
973 #define LAST_IWMMXT_REGNUM 62
974 #define IS_IWMMXT_REGNUM(REGNUM) \
975 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
976 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
977 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
979 /* Base register for access to local variables of the function. */
980 #define FRAME_POINTER_REGNUM 25
982 /* Base register for access to arguments of the function. */
983 #define ARG_POINTER_REGNUM 26
985 #define FIRST_CIRRUS_FP_REGNUM 27
986 #define LAST_CIRRUS_FP_REGNUM 42
987 #define IS_CIRRUS_REGNUM(REGNUM) \
988 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
990 #define FIRST_VFP_REGNUM 63
992 #define LAST_VFP_REGNUM \
993 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
995 #define IS_VFP_REGNUM(REGNUM) \
996 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
998 /* VFP registers are split into two types: those defined by VFP versions < 3
999 have D registers overlaid on consecutive pairs of S registers. VFP version 3
1000 defines 16 new D registers (d16-d31) which, for simplicity and correctness
1001 in various parts of the backend, we implement as "fake" single-precision
1002 registers (which would be S32-S63, but cannot be used in that way). The
1003 following macros define these ranges of registers. */
1004 #define LAST_LO_VFP_REGNUM 94
1005 #define FIRST_HI_VFP_REGNUM 95
1006 #define LAST_HI_VFP_REGNUM 126
1008 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
1009 ((REGNUM) <= LAST_LO_VFP_REGNUM)
1011 /* DFmode values are only valid in even register pairs. */
1012 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1013 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1015 /* Neon Quad values must start at a multiple of four registers. */
1016 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1017 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1019 /* Neon structures of vectors must be in even register pairs and there
1020 must be enough registers available. Because of various patterns
1021 requiring quad registers, we require them to start at a multiple of
1022 four. */
1023 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1024 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1025 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1027 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1028 /* + 16 Cirrus registers take us up to 43. */
1029 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1030 /* VFP (VFP3) adds 32 (64) + 1 more. */
1031 #define FIRST_PSEUDO_REGISTER 128
1033 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1035 /* Value should be nonzero if functions must have frame pointers.
1036 Zero means the frame pointer need not be set up (and parms may be accessed
1037 via the stack pointer) in functions that seem suitable.
1038 If we have to have a frame pointer we might as well make use of it.
1039 APCS says that the frame pointer does not need to be pushed in leaf
1040 functions, or simple tail call functions. */
1042 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1043 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1044 #endif
1046 /* Return number of consecutive hard regs needed starting at reg REGNO
1047 to hold something of mode MODE.
1048 This is ordinarily the length in words of a value of mode MODE
1049 but can be less for certain modes in special long registers.
1051 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1052 mode. */
1053 #define HARD_REGNO_NREGS(REGNO, MODE) \
1054 ((TARGET_32BIT \
1055 && REGNO >= FIRST_FPA_REGNUM \
1056 && REGNO != FRAME_POINTER_REGNUM \
1057 && REGNO != ARG_POINTER_REGNUM) \
1058 && !IS_VFP_REGNUM (REGNO) \
1059 ? 1 : ARM_NUM_REGS (MODE))
1061 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1062 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1063 arm_hard_regno_mode_ok ((REGNO), (MODE))
1065 /* Value is 1 if it is a good idea to tie two pseudo registers
1066 when one has mode MODE1 and one has mode MODE2.
1067 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1068 for any hard reg, then this must be 0 for correct output. */
1069 #define MODES_TIEABLE_P(MODE1, MODE2) \
1070 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1072 #define VALID_IWMMXT_REG_MODE(MODE) \
1073 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1075 /* Modes valid for Neon D registers. */
1076 #define VALID_NEON_DREG_MODE(MODE) \
1077 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1078 || (MODE) == V2SFmode || (MODE) == DImode)
1080 /* Modes valid for Neon Q registers. */
1081 #define VALID_NEON_QREG_MODE(MODE) \
1082 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1083 || (MODE) == V4SFmode || (MODE) == V2DImode)
1085 /* Structure modes valid for Neon registers. */
1086 #define VALID_NEON_STRUCT_MODE(MODE) \
1087 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1088 || (MODE) == CImode || (MODE) == XImode)
1090 /* The order in which register should be allocated. It is good to use ip
1091 since no saving is required (though calls clobber it) and it never contains
1092 function parameters. It is quite good to use lr since other calls may
1093 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1094 least likely to contain a function parameter; in addition results are
1095 returned in r0.
1096 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1097 then D8-D15. The reason for doing this is to attempt to reduce register
1098 pressure when both single- and double-precision registers are used in a
1099 function. */
1101 #define REG_ALLOC_ORDER \
1102 { \
1103 3, 2, 1, 0, 12, 14, 4, 5, \
1104 6, 7, 8, 10, 9, 11, 13, 15, \
1105 16, 17, 18, 19, 20, 21, 22, 23, \
1106 27, 28, 29, 30, 31, 32, 33, 34, \
1107 35, 36, 37, 38, 39, 40, 41, 42, \
1108 43, 44, 45, 46, 47, 48, 49, 50, \
1109 51, 52, 53, 54, 55, 56, 57, 58, \
1110 59, 60, 61, 62, \
1111 24, 25, 26, \
1112 95, 96, 97, 98, 99, 100, 101, 102, \
1113 103, 104, 105, 106, 107, 108, 109, 110, \
1114 111, 112, 113, 114, 115, 116, 117, 118, \
1115 119, 120, 121, 122, 123, 124, 125, 126, \
1116 78, 77, 76, 75, 74, 73, 72, 71, \
1117 70, 69, 68, 67, 66, 65, 64, 63, \
1118 79, 80, 81, 82, 83, 84, 85, 86, \
1119 87, 88, 89, 90, 91, 92, 93, 94, \
1120 127 \
1121 }
1123 /* Use different register alloc ordering for Thumb. */
1124 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1126 /* Tell IRA to use the order we define rather than messing it up with its
1127 own cost calculations. */
1128 #define HONOR_REG_ALLOC_ORDER
1130 /* Interrupt functions can only use registers that have already been
1131 saved by the prologue, even if they would normally be
1132 call-clobbered. */
1133 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1134 (! IS_INTERRUPT (cfun->machine->func_type) || \
1135 df_regs_ever_live_p (DST))
1136 \f
1137 /* Register and constant classes. */
1139 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1140 Now that the Thumb is involved it has become more complicated. */
1141 enum reg_class
1142 {
1143 NO_REGS,
1144 FPA_REGS,
1145 CIRRUS_REGS,
1146 VFP_D0_D7_REGS,
1147 VFP_LO_REGS,
1148 VFP_HI_REGS,
1149 VFP_REGS,
1150 IWMMXT_GR_REGS,
1151 IWMMXT_REGS,
1152 LO_REGS,
1153 STACK_REG,
1154 BASE_REGS,
1155 HI_REGS,
1156 CC_REG,
1157 VFPCC_REG,
1158 GENERAL_REGS,
1159 CORE_REGS,
1160 ALL_REGS,
1161 LIM_REG_CLASSES
1162 };
1164 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1166 /* Give names of register classes as strings for dump file. */
1167 #define REG_CLASS_NAMES \
1168 { \
1187 }
1189 /* Define which registers fit in which classes.
1190 This is an initializer for a vector of HARD_REG_SET
1191 of length N_REG_CLASSES. */
1192 #define REG_CLASS_CONTENTS \
1193 { \
1212 }
1214 /* Any of the VFP register classes. */
1215 #define IS_VFP_CLASS(X) \
1216 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1217 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1219 /* The same information, inverted:
1220 Return the class number of the smallest class containing
1221 reg number REGNO. This could be a conditional expression
1222 or could index an array. */
1223 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1225 /* The following macro defines cover classes for Integrated Register
1226 Allocator. Cover classes is a set of non-intersected register
1227 classes covering all hard registers used for register allocation
1228 purpose. Any move between two registers of a cover class should be
1229 cheaper than load or store of the registers. The macro value is
1230 array of register classes with LIM_REG_CLASSES used as the end
1231 marker. */
1233 #define IRA_COVER_CLASSES \
1234 { \
1235 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1236 LIM_REG_CLASSES \
1237 }
1239 /* FPA registers can't do subreg as all values are reformatted to internal
1240 precision. VFP registers may only be accessed in the mode they
1241 were set. */
1242 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1243 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1244 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1245 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1246 : 0)
1248 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1249 using r0-r4 for function arguments, r7 for the stack frame and don't
1250 have enough left over to do doubleword arithmetic. */
1251 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1252 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1253 || (CLASS) == CC_REG)
1255 /* The class value for index registers, and the one for base regs. */
1256 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1257 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1259 /* For the Thumb the high registers cannot be used as base registers
1260 when addressing quantities in QI or HI mode; if we don't know the
1261 mode, then we must be conservative. */
1262 #define MODE_BASE_REG_CLASS(MODE) \
1263 (TARGET_32BIT ? CORE_REGS : \
1264 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1266 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1267 instead of BASE_REGS. */
1268 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1270 /* When this hook returns true for MODE, the compiler allows
1271 registers explicitly used in the rtl to be used as spill registers
1272 but prevents the compiler from extending the lifetime of these
1273 registers. */
1274 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1275 arm_small_register_classes_for_mode_p
1277 /* Given an rtx X being reloaded into a reg required to be
1278 in class CLASS, return the class of reg to actually use.
1279 In general this is just CLASS, but for the Thumb core registers and
1280 immediate constants we prefer a LO_REGS class or a subset. */
1281 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1282 (TARGET_32BIT ? (CLASS) : \
1283 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1284 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1285 ? LO_REGS : (CLASS)))
1287 /* Must leave BASE_REGS reloads alone */
1288 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1289 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1290 ? ((true_regnum (X) == -1 ? LO_REGS \
1291 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1292 : NO_REGS)) \
1293 : NO_REGS)
1295 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1296 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1297 ? ((true_regnum (X) == -1 ? LO_REGS \
1298 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1299 : NO_REGS)) \
1300 : NO_REGS)
1302 /* Return the register class of a scratch register needed to copy IN into
1303 or out of a register in CLASS in MODE. If it can be done directly,
1304 NO_REGS is returned. */
1305 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1307 ((TARGET_VFP && TARGET_HARD_FLOAT \
1308 && IS_VFP_CLASS (CLASS)) \
1309 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1310 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1311 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1312 : TARGET_32BIT \
1313 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1314 ? GENERAL_REGS : NO_REGS) \
1315 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1317 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1318 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1320 ((TARGET_VFP && TARGET_HARD_FLOAT \
1321 && IS_VFP_CLASS (CLASS)) \
1322 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1323 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1324 coproc_secondary_reload_class (MODE, X, TRUE) : \
1326 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1327 && (CLASS) == CIRRUS_REGS \
1328 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1329 ? GENERAL_REGS : \
1330 (TARGET_32BIT ? \
1331 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1332 && CONSTANT_P (X)) \
1333 ? GENERAL_REGS : \
1334 (((MODE) == HImode && ! arm_arch4 \
1335 && (GET_CODE (X) == MEM \
1336 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1337 && true_regnum (X) == -1))) \
1338 ? GENERAL_REGS : NO_REGS) \
1339 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1341 /* Try a machine-dependent way of reloading an illegitimate address
1342 operand. If we find one, push the reload and jump to WIN. This
1343 macro is used in only one place: `find_reloads_address' in reload.c.
1345 For the ARM, we wish to handle large displacements off a base
1346 register by splitting the addend across a MOV and the mem insn.
1347 This can cut the number of reloads needed. */
1348 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1349 do \
1350 { \
1351 if (GET_CODE (X) == PLUS \
1352 && GET_CODE (XEXP (X, 0)) == REG \
1353 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1354 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1355 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1356 { \
1357 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1358 HOST_WIDE_INT low, high; \
1359 \
1360 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1361 low = ((val & 0xf) ^ 0x8) - 0x8; \
1362 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1364 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1365 else if (MODE == SImode \
1366 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1367 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1369 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1370 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1372 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1373 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1374 && TARGET_HARD_FLOAT && TARGET_FPA) \
1376 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1377 else \
1378 break; \
1379 \
1380 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1381 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1382 - (unsigned HOST_WIDE_INT) 0x80000000); \
1384 if (low == 0 || high == 0 || (high + low != val)) \
1385 break; \
1386 \
1387 /* Reload the high part into a base reg; leave the low part \
1389 X = gen_rtx_PLUS (GET_MODE (X), \
1390 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1391 GEN_INT (high)), \
1392 GEN_INT (low)); \
1393 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1394 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1395 VOIDmode, 0, 0, OPNUM, TYPE); \
1396 goto WIN; \
1397 } \
1398 } \
1399 while (0)
1401 /* XXX If an HImode FP+large_offset address is converted to an HImode
1402 SP+large_offset address, then reload won't know how to fix it. It sees
1403 only that SP isn't valid for HImode, and so reloads the SP into an index
1404 register, but the resulting address is still invalid because the offset
1405 is too big. We fix it here instead by reloading the entire address. */
1406 /* We could probably achieve better results by defining PROMOTE_MODE to help
1407 cope with the variances between the Thumb's signed and unsigned byte and
1408 halfword load instructions. */
1409 /* ??? This should be safe for thumb2, but we may be able to do better. */
1410 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1411 do { \
1412 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1413 if (new_x) \
1414 { \
1415 X = new_x; \
1416 goto WIN; \
1417 } \
1418 } while (0)
1420 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1421 if (TARGET_ARM) \
1422 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1423 else \
1424 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1426 /* Return the maximum number of consecutive registers
1427 needed to represent mode MODE in a register of class CLASS.
1428 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1429 #define CLASS_MAX_NREGS(CLASS, MODE) \
1430 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1432 /* If defined, gives a class of registers that cannot be used as the
1433 operand of a SUBREG that changes the mode of the object illegally. */
1435 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns.
1436 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
1437 it is typically more expensive than a single memory access. We set
1438 the cost to less than two memory accesses so that floating
1439 point to integer conversion does not go through memory. */
1440 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1441 (TARGET_32BIT ? \
1442 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1443 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1444 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \
1445 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \
1446 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1447 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1448 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1449 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1450 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1451 2) \
1452 : \
1453 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1454 \f
1455 /* Stack layout; function entry, exit and calling. */
1457 /* Define this if pushing a word on the stack
1458 makes the stack pointer a smaller address. */
1459 #define STACK_GROWS_DOWNWARD 1
1461 /* Define this to nonzero if the nominal address of the stack frame
1462 is at the high-address end of the local variables;
1463 that is, each additional local variable allocated
1464 goes at a more negative offset in the frame. */
1465 #define FRAME_GROWS_DOWNWARD 1
1467 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1468 When present, it is one word in size, and sits at the top of the frame,
1469 between the soft frame pointer and either r7 or r11.
1471 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1472 and only then if some outgoing arguments are passed on the stack. It would
1473 be tempting to also check whether the stack arguments are passed by indirect
1474 calls, but there seems to be no reason in principle why a post-reload pass
1475 couldn't convert a direct call into an indirect one. */
1476 #define CALLER_INTERWORKING_SLOT_SIZE \
1477 (TARGET_CALLER_INTERWORKING \
1478 && crtl->outgoing_args_size != 0 \
1479 ? UNITS_PER_WORD : 0)
1481 /* Offset within stack frame to start allocating local variables at.
1482 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1483 first local allocated. Otherwise, it is the offset to the BEGINNING
1484 of the first local allocated. */
1485 #define STARTING_FRAME_OFFSET 0
1487 /* If we generate an insn to push BYTES bytes,
1488 this says how many the stack pointer really advances by. */
1489 /* The push insns do not do this rounding implicitly.
1490 So don't define this. */
1491 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1493 /* Define this if the maximum size of all the outgoing args is to be
1494 accumulated and pushed during the prologue. The amount can be
1495 found in the variable crtl->outgoing_args_size. */
1496 #define ACCUMULATE_OUTGOING_ARGS 1
1498 /* Offset of first parameter from the argument pointer register value. */
1499 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1501 /* Value is the number of byte of arguments automatically
1502 popped when returning from a subroutine call.
1503 FUNDECL is the declaration node of the function (as a tree),
1504 FUNTYPE is the data type of the function (as a tree),
1505 or for a library call it is an identifier node for the subroutine name.
1506 SIZE is the number of bytes of arguments passed on the stack.
1508 On the ARM, the caller does not pop any of its arguments that were passed
1509 on the stack. */
1510 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1512 /* Define how to find the value returned by a library function
1513 assuming the value has mode MODE. */
1514 #define LIBCALL_VALUE(MODE) \
1515 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \
1516 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1517 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1518 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1519 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1520 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1521 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1522 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1523 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1524 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1526 /* 1 if REGNO is a possible register number for a function value. */
1527 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1528 ((REGNO) == ARG_REGISTER (1) \
1529 || (TARGET_AAPCS_BASED && TARGET_32BIT \
1530 && TARGET_VFP && TARGET_HARD_FLOAT \
1531 && (REGNO) == FIRST_VFP_REGNUM) \
1532 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1533 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1534 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1535 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1536 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1538 /* Amount of memory needed for an untyped call to save all possible return
1539 registers. */
1540 #define APPLY_RESULT_SIZE arm_apply_result_size()
1542 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1543 values must be in memory. On the ARM, they need only do so if larger
1544 than a word, or if they contain elements offset from zero in the struct. */
1545 #define DEFAULT_PCC_STRUCT_RETURN 0
1547 /* These bits describe the different types of function supported
1548 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1549 normal function and an interworked function, for example. Knowing the
1550 type of a function is important for determining its prologue and
1551 epilogue sequences.
1552 Note value 7 is currently unassigned. Also note that the interrupt
1553 function types all have bit 2 set, so that they can be tested for easily.
1554 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1555 machine_function structure is initialized (to zero) func_type will
1556 default to unknown. This will force the first use of arm_current_func_type
1557 to call arm_compute_func_type. */
1565 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1567 /* In addition functions can have several type modifiers,
1568 outlined by these bit masks: */
1575 /* Some macros to test these flags. */
1576 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1577 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1578 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1579 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1580 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1581 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1584 /* Structure used to hold the function stack frame layout. Offsets are
1585 relative to the stack pointer on function entry. Positive offsets are
1586 in the direction of stack growth.
1587 Only soft_frame is used in thumb mode. */
1590 {
1598 }
1599 arm_stack_offsets;
1601 /* A C structure for machine-specific, per-function data.
1602 This is added to the cfun structure. */
1604 {
1605 /* Additional stack adjustment in __builtin_eh_throw. */
1606 rtx eh_epilogue_sp_ofs;
1607 /* Records if LR has to be saved for far jumps. */
1609 /* Records if ARG_POINTER was ever live. */
1611 /* Records if the save of LR has been eliminated. */
1613 /* The size of the stack frame. Only valid after reload. */
1614 arm_stack_offsets stack_offsets;
1615 /* Records the type of the current function. */
1617 /* Record if the function has a variable argument list. */
1619 /* Records if sibcalls are blocked because an argument
1620 register is needed to preserve stack alignment. */
1622 /* The PIC register for this function. This might be a pseudo. */
1623 rtx pic_reg;
1624 /* Labels for per-function Thumb call-via stubs. One per potential calling
1625 register. We can never call via LR or PC. We can call via SP if a
1626 trampoline happens to be on the top of the stack. */
1628 /* Set to 1 when a return insn is output, this means that the epilogue
1629 is not needed. */
1631 }
1632 machine_function;
1634 /* As in the machine_function, a global set of call-via labels, for code
1635 that is in text_section. */
1638 /* The number of potential ways of assigning to a co-processor. */
1639 #define ARM_NUM_COPROC_SLOTS 1
1641 /* Enumeration of procedure calling standard variants. We don't really
1642 support all of these yet. */
1643 enum arm_pcs
1644 {
1648 /* This must be the last AAPCS variant. */
1652 ARM_PCS_UNKNOWN
1653 };
1655 /* A C type for declaring a variable that is used as the first argument of
1656 `FUNCTION_ARG' and other related values. */
1658 {
1659 /* This is the number of registers of arguments scanned so far. */
1661 /* This is the number of iWMMXt register arguments scanned so far. */
1665 /* Which procedure call variant to use for this call. */
1668 /* AAPCS related state tracking. */
1671 this argument, or -1 if using core
1672 registers. */
1677 split between core regs and stack.
1678 Zero otherwise. */
1681 and the stack. */
1682 /* Private data for tracking VFP register allocation */
1686 MACHMODE aapcs_vfp_rmode;
1689 /* Define where to put the arguments to a function.
1690 Value is zero to push the argument on the stack,
1691 or a hard register in which to store the argument.
1693 MODE is the argument's machine mode.
1694 TYPE is the data type of the argument (as a tree).
1695 This is null for libcalls where that information may
1696 not be available.
1697 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1698 the preceding args and about the function being called.
1699 NAMED is nonzero if this argument is a named parameter
1700 (otherwise it is an extra parameter matching an ellipsis).
1702 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1703 other arguments are passed on the stack. If (NAMED == 0) (which happens
1704 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1705 defined), say it is passed in the stack (function_prologue will
1706 indeed make it pass in the stack if necessary). */
1707 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1708 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1710 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1711 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1713 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1714 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1716 /* For AAPCS, padding should never be below the argument. For other ABIs,
1717 * mimic the default. */
1718 #define PAD_VARARGS_DOWN \
1719 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1721 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1722 for a call to a function whose data type is FNTYPE.
1723 For a library call, FNTYPE is 0.
1724 On the ARM, the offset starts at 0. */
1725 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1726 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1728 /* Update the data in CUM to advance over an argument
1729 of mode MODE and data type TYPE.
1730 (TYPE is null for libcalls where that information may not be available.) */
1731 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1732 arm_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1734 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1735 argument with the specified mode and type. If it is not defined,
1736 `PARM_BOUNDARY' is used for all arguments. */
1737 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1738 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1739 ? DOUBLEWORD_ALIGNMENT \
1740 : PARM_BOUNDARY )
1742 /* 1 if N is a possible register number for function argument passing.
1743 On the ARM, r0-r3 are used to pass args. */
1744 #define FUNCTION_ARG_REGNO_P(REGNO) \
1745 (IN_RANGE ((REGNO), 0, 3) \
1746 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1747 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1748 || (TARGET_IWMMXT_ABI \
1749 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1751 \f
1752 /* If your target environment doesn't prefix user functions with an
1753 underscore, you may wish to re-define this to prevent any conflicts. */
1754 #ifndef ARM_MCOUNT_NAME
1756 #endif
1758 /* Call the function profiler with a given profile label. The Acorn
1759 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1760 On the ARM the full profile code will look like:
1761 .data
1762 LP1
1763 .word 0
1764 .text
1765 mov ip, lr
1766 bl mcount
1767 .word LP1
1769 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1770 will output the .text section.
1772 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1773 ``prof'' doesn't seem to mind about this!
1775 Note - this version of the code is designed to work in both ARM and
1776 Thumb modes. */
1777 #ifndef ARM_FUNCTION_PROFILER
1778 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1779 { \
1780 char temp[20]; \
1781 rtx sym; \
1782 \
1784 IP_REGNUM, LR_REGNUM); \
1785 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1788 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1789 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1790 }
1791 #endif
1793 #ifdef THUMB_FUNCTION_PROFILER
1794 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1795 if (TARGET_ARM) \
1796 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1797 else \
1798 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1799 #else
1800 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1801 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1802 #endif
1804 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1805 the stack pointer does not matter. The value is tested only in
1806 functions that have frame pointers.
1807 No definition is equivalent to always zero.
1809 On the ARM, the function epilogue recovers the stack pointer from the
1810 frame. */
1811 #define EXIT_IGNORE_STACK 1
1813 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1815 /* Determine if the epilogue should be output as RTL.
1816 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1817 #define USE_RETURN_INSN(ISCOND) \
1818 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1820 /* Definitions for register eliminations.
1822 This is an array of structures. Each structure initializes one pair
1823 of eliminable registers. The "from" register number is given first,
1824 followed by "to". Eliminations of the same "from" register are listed
1825 in order of preference.
1827 We have two registers that can be eliminated on the ARM. First, the
1828 arg pointer register can often be eliminated in favor of the stack
1829 pointer register. Secondly, the pseudo frame pointer register can always
1830 be eliminated; it is replaced with either the stack or the real frame
1831 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1832 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1834 #define ELIMINABLE_REGS \
1835 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1836 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1837 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1838 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1839 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1840 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1841 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1843 /* Define the offset between two registers, one to be eliminated, and the
1844 other its replacement, at the start of a routine. */
1845 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1846 if (TARGET_ARM) \
1847 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1848 else \
1849 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1851 /* Special case handling of the location of arguments passed on the stack. */
1852 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1854 /* Initialize data used by insn expanders. This is called from insn_emit,
1855 once for every function before code is generated. */
1856 #define INIT_EXPANDERS arm_init_expanders ()
1858 /* Length in units of the trampoline for entering a nested function. */
1859 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1861 /* Alignment required for a trampoline in bits. */
1862 #define TRAMPOLINE_ALIGNMENT 32
1863 \f
1864 /* Addressing modes, and classification of registers for them. */
1865 #define HAVE_POST_INCREMENT 1
1866 #define HAVE_PRE_INCREMENT TARGET_32BIT
1867 #define HAVE_POST_DECREMENT TARGET_32BIT
1868 #define HAVE_PRE_DECREMENT TARGET_32BIT
1869 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1870 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1871 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1872 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1874 /* Macros to check register numbers against specific register classes. */
1876 /* These assume that REGNO is a hard or pseudo reg number.
1877 They give nonzero only if REGNO is a hard reg of the suitable class
1878 or a pseudo reg currently allocated to a suitable hard reg.
1879 Since they use reg_renumber, they are safe only once reg_renumber
1880 has been allocated, which happens in local-alloc.c. */
1881 #define TEST_REGNO(R, TEST, VALUE) \
1882 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1884 /* Don't allow the pc to be used. */
1885 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1886 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1887 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1888 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1890 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1891 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1892 || (GET_MODE_SIZE (MODE) >= 4 \
1893 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1895 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1896 (TARGET_THUMB1 \
1897 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1898 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1900 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1901 For Thumb, we can not use SP + reg, so reject SP. */
1902 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1903 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1905 /* For ARM code, we don't care about the mode, but for Thumb, the index
1906 must be suitable for use in a QImode load. */
1907 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1908 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1909 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1911 /* Maximum number of registers that can appear in a valid memory address.
1912 Shifts in addresses can't be by a register. */
1913 #define MAX_REGS_PER_ADDRESS 2
1915 /* Recognize any constant value that is a valid address. */
1916 /* XXX We can address any constant, eventually... */
1917 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1918 #define CONSTANT_ADDRESS_P(X) \
1919 (GET_CODE (X) == SYMBOL_REF \
1920 && (CONSTANT_POOL_ADDRESS_P (X) \
1921 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1923 /* True if SYMBOL + OFFSET constants must refer to something within
1924 SYMBOL's section. */
1925 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1927 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1928 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1929 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1930 #endif
1932 /* Nonzero if the constant value X is a legitimate general operand.
1933 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1935 On the ARM, allow any integer (invalid ones are removed later by insn
1936 patterns), nice doubles and symbol_refs which refer to the function's
1937 constant pool XXX.
1939 When generating pic allow anything. */
1940 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1942 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1943 ( GET_CODE (X) == CONST_INT \
1944 || GET_CODE (X) == CONST_DOUBLE \
1945 || CONSTANT_ADDRESS_P (X) \
1946 || flag_pic)
1948 #define LEGITIMATE_CONSTANT_P(X) \
1949 (!arm_cannot_force_const_mem (X) \
1950 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1951 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1953 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1954 #define SUBTARGET_NAME_ENCODING_LENGTHS
1955 #endif
1957 /* This is a C fragment for the inside of a switch statement.
1958 Each case label should return the number of characters to
1959 be stripped from the start of a function's name, if that
1960 name starts with the indicated character. */
1961 #define ARM_NAME_ENCODING_LENGTHS \
1963 SUBTARGET_NAME_ENCODING_LENGTHS
1965 /* This is how to output a reference to a user-level label named NAME.
1966 `assemble_name' uses this. */
1967 #undef ASM_OUTPUT_LABELREF
1968 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1969 arm_asm_output_labelref (FILE, NAME)
1971 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1972 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1973 if (TARGET_THUMB2) \
1974 thumb2_asm_output_opcode (STREAM);
1976 /* The EABI specifies that constructors should go in .init_array.
1977 Other targets use .ctors for compatibility. */
1978 #ifndef ARM_EABI_CTORS_SECTION_OP
1979 #define ARM_EABI_CTORS_SECTION_OP \
1981 #endif
1982 #ifndef ARM_EABI_DTORS_SECTION_OP
1983 #define ARM_EABI_DTORS_SECTION_OP \
1985 #endif
1986 #define ARM_CTORS_SECTION_OP \
1988 #define ARM_DTORS_SECTION_OP \
1991 /* Define CTORS_SECTION_ASM_OP. */
1992 #undef CTORS_SECTION_ASM_OP
1993 #undef DTORS_SECTION_ASM_OP
1994 #ifndef IN_LIBGCC2
1995 # define CTORS_SECTION_ASM_OP \
1996 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1997 # define DTORS_SECTION_ASM_OP \
1998 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2000 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2001 so we cannot use the definition above. */
2002 # ifdef __ARM_EABI__
2003 /* The .ctors section is not part of the EABI, so we do not define
2004 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2005 from trying to use it. We do define it when doing normal
2006 compilation, as .init_array can be used instead of .ctors. */
2007 /* There is no need to emit begin or end markers when using
2008 init_array; the dynamic linker will compute the size of the
2009 array itself based on special symbols created by the static
2010 linker. However, we do need to arrange to set up
2011 exception-handling here. */
2012 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2014 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2017 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2018 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2022 /* True if the operating system can merge entities with vague linkage
2023 (e.g., symbols in COMDAT group) during dynamic linking. */
2024 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2025 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2026 #endif
2028 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2030 #ifdef TARGET_UNWIND_INFO
2031 #define ARM_EABI_UNWIND_TABLES \
2032 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2033 #else
2034 #define ARM_EABI_UNWIND_TABLES 0
2035 #endif
2037 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2038 and check its validity for a certain class.
2039 We have two alternate definitions for each of them.
2040 The usual definition accepts all pseudo regs; the other rejects
2041 them unless they have been allocated suitable hard regs.
2042 The symbol REG_OK_STRICT causes the latter definition to be used.
2043 Thumb-2 has the same restrictions as arm. */
2044 #ifndef REG_OK_STRICT
2046 #define ARM_REG_OK_FOR_BASE_P(X) \
2047 (REGNO (X) <= LAST_ARM_REGNUM \
2048 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2049 || REGNO (X) == FRAME_POINTER_REGNUM \
2050 || REGNO (X) == ARG_POINTER_REGNUM)
2052 #define ARM_REG_OK_FOR_INDEX_P(X) \
2053 ((REGNO (X) <= LAST_ARM_REGNUM \
2054 && REGNO (X) != STACK_POINTER_REGNUM) \
2055 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2056 || REGNO (X) == FRAME_POINTER_REGNUM \
2057 || REGNO (X) == ARG_POINTER_REGNUM)
2059 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2060 (REGNO (X) <= LAST_LO_REGNUM \
2061 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2062 || (GET_MODE_SIZE (MODE) >= 4 \
2063 && (REGNO (X) == STACK_POINTER_REGNUM \
2064 || (X) == hard_frame_pointer_rtx \
2065 || (X) == arg_pointer_rtx)))
2067 #define REG_STRICT_P 0
2071 #define ARM_REG_OK_FOR_BASE_P(X) \
2072 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2074 #define ARM_REG_OK_FOR_INDEX_P(X) \
2075 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2077 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2078 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2080 #define REG_STRICT_P 1
2084 /* Now define some helpers in terms of the above. */
2086 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2087 (TARGET_THUMB1 \
2088 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2089 : ARM_REG_OK_FOR_BASE_P (X))
2091 /* For 16-bit Thumb, a valid index register is anything that can be used in
2092 a byte load instruction. */
2093 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2094 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2096 /* Nonzero if X is a hard reg that can be used as an index
2097 or if it is a pseudo reg. On the Thumb, the stack pointer
2098 is not suitable. */
2099 #define REG_OK_FOR_INDEX_P(X) \
2100 (TARGET_THUMB1 \
2101 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2102 : ARM_REG_OK_FOR_INDEX_P (X))
2104 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2105 For Thumb, we can not use SP + reg, so reject SP. */
2106 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2107 REG_OK_FOR_INDEX_P (X)
2108 \f
2109 #define ARM_BASE_REGISTER_RTX_P(X) \
2110 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2112 #define ARM_INDEX_REGISTER_RTX_P(X) \
2113 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2114 \f
2115 /* Define this for compatibility reasons. */
2116 #define HANDLE_PRAGMA_PACK_PUSH_POP
2118 /* Specify the machine mode that this machine uses
2119 for the index in the tablejump instruction. */
2120 #define CASE_VECTOR_MODE Pmode
2122 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
2123 || (TARGET_THUMB1 \
2124 && (optimize_size || flag_pic)))
2126 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2127 (TARGET_THUMB1 \
2128 ? (min >= 0 && max < 512 \
2129 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2130 : min >= -256 && max < 256 \
2131 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2132 : min >= 0 && max < 8192 \
2133 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2134 : min >= -4096 && max < 4096 \
2135 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2136 : SImode) \
2137 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2138 : (max >= 0x200) ? HImode \
2139 : QImode))
2141 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2142 unsigned is probably best, but may break some code. */
2143 #ifndef DEFAULT_SIGNED_CHAR
2144 #define DEFAULT_SIGNED_CHAR 0
2145 #endif
2147 /* Max number of bytes we can move from memory to memory
2148 in one reasonably fast instruction. */
2149 #define MOVE_MAX 4
2151 #undef MOVE_RATIO
2152 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2154 /* Define if operations between registers always perform the operation
2155 on the full register even if a narrower mode is specified. */
2156 #define WORD_REGISTER_OPERATIONS
2158 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2159 will either zero-extend or sign-extend. The value of this macro should
2160 be the code that says which one of the two operations is implicitly
2161 done, UNKNOWN if none. */
2162 #define LOAD_EXTEND_OP(MODE) \
2163 (TARGET_THUMB ? ZERO_EXTEND : \
2164 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2165 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2167 /* Nonzero if access to memory by bytes is slow and undesirable. */
2168 #define SLOW_BYTE_ACCESS 0
2170 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2172 /* Immediate shift counts are truncated by the output routines (or was it
2173 the assembler?). Shift counts in a register are truncated by ARM. Note
2174 that the native compiler puts too large (> 32) immediate shift counts
2175 into a register and shifts by the register, letting the ARM decide what
2176 to do instead of doing that itself. */
2177 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2178 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2179 On the arm, Y in a register is used modulo 256 for the shift. Only for
2180 rotates is modulo 32 used. */
2181 /* #define SHIFT_COUNT_TRUNCATED 1 */
2183 /* All integers have the same format so truncation is easy. */
2184 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2186 /* Calling from registers is a massive pain. */
2187 #define NO_FUNCTION_CSE 1
2189 /* The machine modes of pointers and functions */
2190 #define Pmode SImode
2191 #define FUNCTION_MODE Pmode
2193 #define ARM_FRAME_RTX(X) \
2194 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2195 || (X) == arg_pointer_rtx)
2197 /* Moves to and from memory are quite expensive */
2198 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2199 (TARGET_32BIT ? 10 : \
2200 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2201 * (CLASS == LO_REGS ? 1 : 2)))
2203 /* Try to generate sequences that don't involve branches, we can then use
2204 conditional instructions */
2205 #define BRANCH_COST(speed_p, predictable_p) \
2206 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2207 \f
2208 /* Position Independent Code. */
2209 /* We decide which register to use based on the compilation options and
2210 the assembler in use; this is more general than the APCS restriction of
2211 using sb (r9) all the time. */
2214 /* The register number of the register used to address a table of static
2215 data addresses in memory. */
2216 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2218 /* We can't directly access anything that contains a symbol,
2219 nor can we indirect via the constant pool. One exception is
2220 UNSPEC_TLS, which is always PIC. */
2221 #define LEGITIMATE_PIC_OPERAND_P(X) \
2222 (!(symbol_mentioned_p (X) \
2223 || label_mentioned_p (X) \
2224 || (GET_CODE (X) == SYMBOL_REF \
2225 && CONSTANT_POOL_ADDRESS_P (X) \
2226 && (symbol_mentioned_p (get_pool_constant (X)) \
2227 || label_mentioned_p (get_pool_constant (X))))) \
2228 || tls_mentioned_p (X))
2230 /* We need to know when we are making a constant pool; this determines
2231 whether data needs to be in the GOT or can be referenced via a GOT
2232 offset. */
2234 \f
2235 /* Handle pragmas for compatibility with Intel's compilers. */
2236 /* Also abuse this to register additional C specific EABI attributes. */
2237 #define REGISTER_TARGET_PRAGMAS() do { \
2241 arm_lang_object_attributes_init(); \
2242 } while (0)
2244 /* Condition code information. */
2245 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2246 return the mode to be used for the comparison. */
2248 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2250 #define REVERSIBLE_CC_MODE(MODE) 1
2252 #define REVERSE_CONDITION(CODE,MODE) \
2253 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2254 ? reverse_condition_maybe_unordered (code) \
2255 : reverse_condition (code))
2257 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2258 do \
2259 { \
2260 if (GET_CODE (OP1) == CONST_INT \
2261 && ! (const_ok_for_arm (INTVAL (OP1)) \
2262 || (const_ok_for_arm (- INTVAL (OP1))))) \
2263 { \
2264 rtx const_op = OP1; \
2265 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2266 &const_op); \
2267 OP1 = const_op; \
2268 } \
2269 } \
2270 while (0)
2272 /* The arm5 clz instruction returns 32. */
2273 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2274 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2275 \f
2276 #undef ASM_APP_OFF
2280 /* Output a push or a pop instruction (only used when profiling).
2281 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2282 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2283 that r7 isn't used by the function profiler, so we can use it as a
2284 scratch reg. WARNING: This isn't safe in the general case! It may be
2285 sensitive to future changes in final.c:profile_function. */
2286 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2287 do \
2288 { \
2289 if (TARGET_ARM) \
2291 STACK_POINTER_REGNUM, REGNO); \
2292 else if (TARGET_THUMB1 \
2293 && (REGNO) == STATIC_CHAIN_REGNUM) \
2294 { \
2298 } \
2299 else \
2301 } while (0)
2304 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2305 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2306 do \
2307 { \
2308 if (TARGET_ARM) \
2310 STACK_POINTER_REGNUM, REGNO); \
2311 else if (TARGET_THUMB1 \
2312 && (REGNO) == STATIC_CHAIN_REGNUM) \
2313 { \
2317 } \
2318 else \
2320 } while (0)
2322 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2323 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2325 /* This is how to output a label which precedes a jumptable. Since
2326 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2327 #undef ASM_OUTPUT_CASE_LABEL
2328 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2329 do \
2330 { \
2331 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2332 ASM_OUTPUT_ALIGN (FILE, 2); \
2333 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2334 } \
2335 while (0)
2337 /* Make sure subsequent insns are aligned after a TBB. */
2338 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2339 do \
2340 { \
2341 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2342 ASM_OUTPUT_ALIGN (FILE, 1); \
2343 } \
2344 while (0)
2346 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2347 do \
2348 { \
2349 if (TARGET_THUMB) \
2350 { \
2351 if (is_called_in_ARM_mode (DECL) \
2352 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2353 && cfun->is_thunk)) \
2355 else if (TARGET_THUMB1) \
2357 else \
2359 } \
2360 if (TARGET_POKE_FUNCTION_NAME) \
2361 arm_poke_function_name (STREAM, (const char *) NAME); \
2362 } \
2363 while (0)
2365 /* For aliases of functions we use .thumb_set instead. */
2366 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2367 do \
2368 { \
2369 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2370 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2371 \
2372 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2373 { \
2375 assemble_name (FILE, LABEL1); \
2377 assemble_name (FILE, LABEL2); \
2379 } \
2380 else \
2381 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2382 } \
2383 while (0)
2385 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2386 /* To support -falign-* switches we need to use .p2align so
2387 that alignment directives in code sections will be padded
2388 with no-op instructions, rather than zeroes. */
2389 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2390 if ((LOG) != 0) \
2391 { \
2392 if ((MAX_SKIP) == 0) \
2394 else \
2396 (int) (LOG), (int) (MAX_SKIP)); \
2397 }
2398 #endif
2399 \f
2400 /* Add two bytes to the length of conditionally executed Thumb-2
2401 instructions for the IT instruction. */
2402 #define ADJUST_INSN_LENGTH(insn, length) \
2403 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2404 length += 2;
2406 /* Only perform branch elimination (by making instructions conditional) if
2407 we're optimizing. For Thumb-2 check if any IT instructions need
2408 outputting. */
2409 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2410 if (TARGET_ARM && optimize) \
2411 arm_final_prescan_insn (INSN); \
2412 else if (TARGET_THUMB2) \
2413 thumb2_final_prescan_insn (INSN); \
2414 else if (TARGET_THUMB1) \
2415 thumb1_final_prescan_insn (INSN)
2417 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2424 /* Output an operand of an instruction. */
2425 #define PRINT_OPERAND(STREAM, X, CODE) \
2426 arm_print_operand (STREAM, X, CODE)
2428 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2429 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2430 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2431 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2432 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2433 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2434 : 0))))
2436 /* Output the address of an operand. */
2437 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2438 { \
2439 int is_minus = GET_CODE (X) == MINUS; \
2440 \
2441 if (GET_CODE (X) == REG) \
2443 else if (GET_CODE (X) == PLUS || is_minus) \
2444 { \
2445 rtx base = XEXP (X, 0); \
2446 rtx index = XEXP (X, 1); \
2447 HOST_WIDE_INT offset = 0; \
2448 if (GET_CODE (base) != REG \
2449 || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) \
2450 { \
2454 rtx temp = base; \
2455 base = index; \
2456 index = temp; \
2457 } \
2458 switch (GET_CODE (index)) \
2459 { \
2460 case CONST_INT: \
2461 offset = INTVAL (index); \
2462 if (is_minus) \
2463 offset = -offset; \
2465 REGNO (base), offset); \
2466 break; \
2467 \
2468 case REG: \
2471 REGNO (index)); \
2472 break; \
2473 \
2474 case MULT: \
2475 case ASHIFTRT: \
2476 case LSHIFTRT: \
2477 case ASHIFT: \
2478 case ROTATERT: \
2479 { \
2482 REGNO (XEXP (index, 0))); \
2485 break; \
2486 } \
2487 \
2488 default: \
2489 gcc_unreachable (); \
2490 } \
2491 } \
2492 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2493 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2494 { \
2495 extern enum machine_mode output_memory_reference_mode; \
2496 \
2497 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2498 \
2499 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2501 REGNO (XEXP (X, 0)), \
2503 GET_MODE_SIZE (output_memory_reference_mode)); \
2504 else \
2506 REGNO (XEXP (X, 0)), \
2508 GET_MODE_SIZE (output_memory_reference_mode)); \
2509 } \
2510 else if (GET_CODE (X) == PRE_MODIFY) \
2511 { \
2513 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2515 INTVAL (XEXP (XEXP (X, 1), 1))); \
2516 else \
2518 REGNO (XEXP (XEXP (X, 1), 1))); \
2519 } \
2520 else if (GET_CODE (X) == POST_MODIFY) \
2521 { \
2523 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2525 INTVAL (XEXP (XEXP (X, 1), 1))); \
2526 else \
2528 REGNO (XEXP (XEXP (X, 1), 1))); \
2529 } \
2530 else output_addr_const (STREAM, X); \
2531 }
2533 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2534 { \
2535 if (GET_CODE (X) == REG) \
2537 else if (GET_CODE (X) == POST_INC) \
2539 else if (GET_CODE (X) == PLUS) \
2540 { \
2541 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2542 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2544 REGNO (XEXP (X, 0)), \
2545 INTVAL (XEXP (X, 1))); \
2546 else \
2548 REGNO (XEXP (X, 0)), \
2549 REGNO (XEXP (X, 1))); \
2550 } \
2551 else \
2552 output_addr_const (STREAM, X); \
2553 }
2555 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2556 if (TARGET_32BIT) \
2557 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2558 else \
2559 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2561 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2562 if (arm_output_addr_const_extra (file, x) == FALSE) \
2563 goto fail
2565 /* A C expression whose value is RTL representing the value of the return
2566 address for the frame COUNT steps up from the current frame. */
2568 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2569 arm_return_addr (COUNT, FRAME)
2571 /* Mask of the bits in the PC that contain the real return address
2572 when running in 26-bit mode. */
2573 #define RETURN_ADDR_MASK26 (0x03fffffc)
2575 /* Pick up the return address upon entry to a procedure. Used for
2576 dwarf2 unwind information. This also enables the table driven
2577 mechanism. */
2578 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2579 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2581 /* Used to mask out junk bits from the return address, such as
2582 processor state, interrupt status, condition codes and the like. */
2583 #define MASK_RETURN_ADDR \
2584 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2585 in 26 bit mode, the condition codes must be masked out of the \
2586 return address. This does not apply to ARM6 and later processors \
2588 ((arm_arch4 || TARGET_THUMB) \
2589 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2590 : arm_gen_return_addr_mask ())
2592 \f
2593 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2594 symbolic names defined here (which would require too much duplication).
2595 FIXME? */
2596 enum arm_builtins
2597 {
2598 ARM_BUILTIN_GETWCX,
2599 ARM_BUILTIN_SETWCX,
2601 ARM_BUILTIN_WZERO,
2603 ARM_BUILTIN_WAVG2BR,
2604 ARM_BUILTIN_WAVG2HR,
2605 ARM_BUILTIN_WAVG2B,
2606 ARM_BUILTIN_WAVG2H,
2608 ARM_BUILTIN_WACCB,
2609 ARM_BUILTIN_WACCH,
2610 ARM_BUILTIN_WACCW,
2612 ARM_BUILTIN_WMACS,
2613 ARM_BUILTIN_WMACSZ,
2614 ARM_BUILTIN_WMACU,
2615 ARM_BUILTIN_WMACUZ,
2617 ARM_BUILTIN_WSADB,
2618 ARM_BUILTIN_WSADBZ,
2619 ARM_BUILTIN_WSADH,
2620 ARM_BUILTIN_WSADHZ,
2622 ARM_BUILTIN_WALIGN,
2624 ARM_BUILTIN_TMIA,
2625 ARM_BUILTIN_TMIAPH,
2626 ARM_BUILTIN_TMIABB,
2627 ARM_BUILTIN_TMIABT,
2628 ARM_BUILTIN_TMIATB,
2629 ARM_BUILTIN_TMIATT,
2631 ARM_BUILTIN_TMOVMSKB,
2632 ARM_BUILTIN_TMOVMSKH,
2633 ARM_BUILTIN_TMOVMSKW,
2635 ARM_BUILTIN_TBCSTB,
2636 ARM_BUILTIN_TBCSTH,
2637 ARM_BUILTIN_TBCSTW,
2639 ARM_BUILTIN_WMADDS,
2640 ARM_BUILTIN_WMADDU,
2642 ARM_BUILTIN_WPACKHSS,
2643 ARM_BUILTIN_WPACKWSS,
2644 ARM_BUILTIN_WPACKDSS,
2645 ARM_BUILTIN_WPACKHUS,
2646 ARM_BUILTIN_WPACKWUS,
2647 ARM_BUILTIN_WPACKDUS,
2649 ARM_BUILTIN_WADDB,
2650 ARM_BUILTIN_WADDH,
2651 ARM_BUILTIN_WADDW,
2652 ARM_BUILTIN_WADDSSB,
2653 ARM_BUILTIN_WADDSSH,
2654 ARM_BUILTIN_WADDSSW,
2655 ARM_BUILTIN_WADDUSB,
2656 ARM_BUILTIN_WADDUSH,
2657 ARM_BUILTIN_WADDUSW,
2658 ARM_BUILTIN_WSUBB,
2659 ARM_BUILTIN_WSUBH,
2660 ARM_BUILTIN_WSUBW,
2661 ARM_BUILTIN_WSUBSSB,
2662 ARM_BUILTIN_WSUBSSH,
2663 ARM_BUILTIN_WSUBSSW,
2664 ARM_BUILTIN_WSUBUSB,
2665 ARM_BUILTIN_WSUBUSH,
2666 ARM_BUILTIN_WSUBUSW,
2668 ARM_BUILTIN_WAND,
2669 ARM_BUILTIN_WANDN,
2670 ARM_BUILTIN_WOR,
2671 ARM_BUILTIN_WXOR,
2673 ARM_BUILTIN_WCMPEQB,
2674 ARM_BUILTIN_WCMPEQH,
2675 ARM_BUILTIN_WCMPEQW,
2676 ARM_BUILTIN_WCMPGTUB,
2677 ARM_BUILTIN_WCMPGTUH,
2678 ARM_BUILTIN_WCMPGTUW,
2679 ARM_BUILTIN_WCMPGTSB,
2680 ARM_BUILTIN_WCMPGTSH,
2681 ARM_BUILTIN_WCMPGTSW,
2683 ARM_BUILTIN_TEXTRMSB,
2684 ARM_BUILTIN_TEXTRMSH,
2685 ARM_BUILTIN_TEXTRMSW,
2686 ARM_BUILTIN_TEXTRMUB,
2687 ARM_BUILTIN_TEXTRMUH,
2688 ARM_BUILTIN_TEXTRMUW,
2689 ARM_BUILTIN_TINSRB,
2690 ARM_BUILTIN_TINSRH,
2691 ARM_BUILTIN_TINSRW,
2693 ARM_BUILTIN_WMAXSW,
2694 ARM_BUILTIN_WMAXSH,
2695 ARM_BUILTIN_WMAXSB,
2696 ARM_BUILTIN_WMAXUW,
2697 ARM_BUILTIN_WMAXUH,
2698 ARM_BUILTIN_WMAXUB,
2699 ARM_BUILTIN_WMINSW,
2700 ARM_BUILTIN_WMINSH,
2701 ARM_BUILTIN_WMINSB,
2702 ARM_BUILTIN_WMINUW,
2703 ARM_BUILTIN_WMINUH,
2704 ARM_BUILTIN_WMINUB,
2706 ARM_BUILTIN_WMULUM,
2707 ARM_BUILTIN_WMULSM,
2708 ARM_BUILTIN_WMULUL,
2710 ARM_BUILTIN_PSADBH,
2711 ARM_BUILTIN_WSHUFH,
2713 ARM_BUILTIN_WSLLH,
2714 ARM_BUILTIN_WSLLW,
2715 ARM_BUILTIN_WSLLD,
2716 ARM_BUILTIN_WSRAH,
2717 ARM_BUILTIN_WSRAW,
2718 ARM_BUILTIN_WSRAD,
2719 ARM_BUILTIN_WSRLH,
2720 ARM_BUILTIN_WSRLW,
2721 ARM_BUILTIN_WSRLD,
2722 ARM_BUILTIN_WRORH,
2723 ARM_BUILTIN_WRORW,
2724 ARM_BUILTIN_WRORD,
2725 ARM_BUILTIN_WSLLHI,
2726 ARM_BUILTIN_WSLLWI,
2727 ARM_BUILTIN_WSLLDI,
2728 ARM_BUILTIN_WSRAHI,
2729 ARM_BUILTIN_WSRAWI,
2730 ARM_BUILTIN_WSRADI,
2731 ARM_BUILTIN_WSRLHI,
2732 ARM_BUILTIN_WSRLWI,
2733 ARM_BUILTIN_WSRLDI,
2734 ARM_BUILTIN_WRORHI,
2735 ARM_BUILTIN_WRORWI,
2736 ARM_BUILTIN_WRORDI,
2738 ARM_BUILTIN_WUNPCKIHB,
2739 ARM_BUILTIN_WUNPCKIHH,
2740 ARM_BUILTIN_WUNPCKIHW,
2741 ARM_BUILTIN_WUNPCKILB,
2742 ARM_BUILTIN_WUNPCKILH,
2743 ARM_BUILTIN_WUNPCKILW,
2745 ARM_BUILTIN_WUNPCKEHSB,
2746 ARM_BUILTIN_WUNPCKEHSH,
2747 ARM_BUILTIN_WUNPCKEHSW,
2748 ARM_BUILTIN_WUNPCKEHUB,
2749 ARM_BUILTIN_WUNPCKEHUH,
2750 ARM_BUILTIN_WUNPCKEHUW,
2751 ARM_BUILTIN_WUNPCKELSB,
2752 ARM_BUILTIN_WUNPCKELSH,
2753 ARM_BUILTIN_WUNPCKELSW,
2754 ARM_BUILTIN_WUNPCKELUB,
2755 ARM_BUILTIN_WUNPCKELUH,
2756 ARM_BUILTIN_WUNPCKELUW,
2758 ARM_BUILTIN_THREAD_POINTER,
2760 ARM_BUILTIN_NEON_BASE,
2763 };
2765 /* Do not emit .note.GNU-stack by default. */
2766 #ifndef NEED_INDICATE_EXEC_STACK
2767 #define NEED_INDICATE_EXEC_STACK 0
2768 #endif
2770 /* The maximum number of parallel loads or stores we support in an ldm/stm
2771 instruction. */
2772 #define MAX_LDM_STM_OPS 4