| blob | 08475b65e545d7e8154a3ef7ffab39f5e4f3e8f5 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; REGNOS
27 ;;
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
52 ;;
53 ;; UNSPEC usage
54 ;;
56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_PROBE_STACK 4) ; probe stack memory reference
59 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
60 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
61 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
62 (UNSPEC_MOVSI_GOT 8)
63 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
64 (UNSPEC_FCTIWZ 10)
65 (UNSPEC_FRIM 11)
66 (UNSPEC_FRIN 12)
67 (UNSPEC_FRIP 13)
68 (UNSPEC_FRIZ 14)
69 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
70 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
71 (UNSPEC_TLSGD 17)
72 (UNSPEC_TLSLD 18)
73 (UNSPEC_MOVESI_FROM_CR 19)
74 (UNSPEC_MOVESI_TO_CR 20)
75 (UNSPEC_TLSDTPREL 21)
76 (UNSPEC_TLSDTPRELHA 22)
77 (UNSPEC_TLSDTPRELLO 23)
78 (UNSPEC_TLSGOTDTPREL 24)
79 (UNSPEC_TLSTPREL 25)
80 (UNSPEC_TLSTPRELHA 26)
81 (UNSPEC_TLSTPRELLO 27)
82 (UNSPEC_TLSGOTTPREL 28)
83 (UNSPEC_TLSTLS 29)
84 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
85 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
86 (UNSPEC_STFIWX 32)
87 (UNSPEC_POPCNTB 33)
88 (UNSPEC_FRES 34)
89 (UNSPEC_SP_SET 35)
90 (UNSPEC_SP_TEST 36)
91 (UNSPEC_SYNC 37)
92 (UNSPEC_LWSYNC 38)
93 (UNSPEC_ISYNC 39)
94 (UNSPEC_SYNC_OP 40)
95 (UNSPEC_ATOMIC 41)
96 (UNSPEC_CMPXCHG 42)
97 (UNSPEC_XCHG 43)
98 (UNSPEC_AND 44)
99 (UNSPEC_DLMZB 45)
100 (UNSPEC_DLMZB_CR 46)
101 (UNSPEC_DLMZB_STRLEN 47)
102 (UNSPEC_RSQRT 48)
103 (UNSPEC_TOCREL 49)
104 (UNSPEC_MACHOPIC_OFFSET 50)
105 (UNSPEC_BPERM 51)
106 ])
108 ;;
109 ;; UNSPEC_VOLATILE usage
110 ;;
112 (define_constants
113 [(UNSPECV_BLOCK 0)
114 (UNSPECV_LL 1) ; load-locked
115 (UNSPECV_SC 2) ; store-conditional
116 (UNSPECV_EH_RR 9) ; eh_reg_restore
117 ])
118 \f
119 ;; Define an insn type attribute. This is used in function unit delay
120 ;; computations.
121 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
122 (const_string "integer"))
124 ;; Define floating point instruction sub-types for use with Xfpu.md
125 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
127 ;; Length (in bytes).
128 ; '(pc)' in the following doesn't include the instruction itself; it is
129 ; calculated as if the instruction had zero size.
130 (define_attr "length" ""
131 (if_then_else (eq_attr "type" "branch")
132 (if_then_else (and (ge (minus (match_dup 0) (pc))
133 (const_int -32768))
134 (lt (minus (match_dup 0) (pc))
135 (const_int 32764)))
136 (const_int 4)
137 (const_int 8))
138 (const_int 4)))
140 ;; Processor type -- this attribute must exactly match the processor_type
141 ;; enumeration in rs6000.h.
143 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2"
144 (const (symbol_ref "rs6000_cpu_attr")))
147 ;; If this instruction is microcoded on the CELL processor
148 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
149 (define_attr "cell_micro" "not,conditional,always"
150 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
151 (const_string "always")
152 (const_string "not")))
154 (automata_option "ndfa")
156 (include "rios1.md")
157 (include "rios2.md")
158 (include "rs64.md")
159 (include "mpc.md")
160 (include "40x.md")
161 (include "440.md")
162 (include "476.md")
163 (include "603.md")
164 (include "6xx.md")
165 (include "7xx.md")
166 (include "7450.md")
167 (include "8540.md")
168 (include "e300c2c3.md")
169 (include "e500mc.md")
170 (include "e500mc64.md")
171 (include "power4.md")
172 (include "power5.md")
173 (include "power6.md")
174 (include "power7.md")
175 (include "cell.md")
176 (include "xfpu.md")
177 (include "a2.md")
179 (include "predicates.md")
180 (include "constraints.md")
182 (include "darwin.md")
184 \f
185 ;; Mode iterators
187 ; This mode iterator allows :GPR to be used to indicate the allowable size
188 ; of whole values in GPRs.
189 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
191 ; Any supported integer mode.
192 (define_mode_iterator INT [QI HI SI DI TI])
194 ; Any supported integer mode that fits in one register.
195 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
197 ; extend modes for DImode
198 (define_mode_iterator QHSI [QI HI SI])
200 ; SImode or DImode, even if DImode doesn't fit in GPRs.
201 (define_mode_iterator SDI [SI DI])
203 ; The size of a pointer. Also, the size of the value that a record-condition
204 ; (one with a '.') will compare.
205 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
207 ; Any hardware-supported floating-point mode
208 (define_mode_iterator FP [
209 (SF "TARGET_HARD_FLOAT
210 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
211 (DF "TARGET_HARD_FLOAT
212 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
213 (TF "!TARGET_IEEEQUAD
214 && TARGET_HARD_FLOAT
215 && (TARGET_FPRS || TARGET_E500_DOUBLE)
216 && TARGET_LONG_DOUBLE_128")
217 (DD "TARGET_DFP")
218 (TD "TARGET_DFP")])
220 ; Various instructions that come in SI and DI forms.
221 ; A generic w/d attribute, for things like cmpw/cmpd.
222 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
224 ; DImode bits
225 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
227 ;; ISEL/ISEL64 target selection
228 (define_mode_attr sel [(SI "") (DI "64")])
230 ;; Suffix for reload patterns
231 (define_mode_attr ptrsize [(SI "32bit")
232 (DI "64bit")])
234 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
235 (DI "TARGET_64BIT")])
237 (define_mode_attr mptrsize [(SI "si")
238 (DI "di")])
240 \f
241 ;; Start with fixed-point load and store insns. Here we put only the more
242 ;; complex forms. Basic data transfer is done later.
244 (define_expand "zero_extend<mode>di2"
245 [(set (match_operand:DI 0 "gpc_reg_operand" "")
246 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
247 "TARGET_POWERPC64"
248 "")
250 (define_insn "*zero_extend<mode>di2_internal1"
251 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
252 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
253 "TARGET_POWERPC64"
254 "@
255 l<wd>z%U1%X1 %0,%1
256 rldicl %0,%1,0,<dbits>"
257 [(set_attr "type" "load,*")])
259 (define_insn "*zero_extend<mode>di2_internal2"
260 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
261 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
262 (const_int 0)))
263 (clobber (match_scratch:DI 2 "=r,r"))]
264 "TARGET_64BIT"
265 "@
266 rldicl. %2,%1,0,<dbits>
267 #"
268 [(set_attr "type" "compare")
269 (set_attr "length" "4,8")])
271 (define_split
272 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
273 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
274 (const_int 0)))
275 (clobber (match_scratch:DI 2 ""))]
276 "TARGET_POWERPC64 && reload_completed"
277 [(set (match_dup 2)
278 (zero_extend:DI (match_dup 1)))
279 (set (match_dup 0)
280 (compare:CC (match_dup 2)
281 (const_int 0)))]
282 "")
284 (define_insn "*zero_extend<mode>di2_internal3"
285 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
286 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
287 (const_int 0)))
288 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
289 (zero_extend:DI (match_dup 1)))]
290 "TARGET_64BIT"
291 "@
292 rldicl. %0,%1,0,<dbits>
293 #"
294 [(set_attr "type" "compare")
295 (set_attr "length" "4,8")])
297 (define_split
298 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
299 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
300 (const_int 0)))
301 (set (match_operand:DI 0 "gpc_reg_operand" "")
302 (zero_extend:DI (match_dup 1)))]
303 "TARGET_POWERPC64 && reload_completed"
304 [(set (match_dup 0)
305 (zero_extend:DI (match_dup 1)))
306 (set (match_dup 2)
307 (compare:CC (match_dup 0)
308 (const_int 0)))]
309 "")
311 (define_insn "extendqidi2"
312 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
313 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
314 "TARGET_POWERPC64"
315 "extsb %0,%1"
316 [(set_attr "type" "exts")])
318 (define_insn ""
319 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
320 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
321 (const_int 0)))
322 (clobber (match_scratch:DI 2 "=r,r"))]
323 "TARGET_64BIT"
324 "@
325 extsb. %2,%1
326 #"
327 [(set_attr "type" "compare")
328 (set_attr "length" "4,8")])
330 (define_split
331 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
332 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
333 (const_int 0)))
334 (clobber (match_scratch:DI 2 ""))]
335 "TARGET_POWERPC64 && reload_completed"
336 [(set (match_dup 2)
337 (sign_extend:DI (match_dup 1)))
338 (set (match_dup 0)
339 (compare:CC (match_dup 2)
340 (const_int 0)))]
341 "")
343 (define_insn ""
344 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
345 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
346 (const_int 0)))
347 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
348 (sign_extend:DI (match_dup 1)))]
349 "TARGET_64BIT"
350 "@
351 extsb. %0,%1
352 #"
353 [(set_attr "type" "compare")
354 (set_attr "length" "4,8")])
356 (define_split
357 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
358 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
359 (const_int 0)))
360 (set (match_operand:DI 0 "gpc_reg_operand" "")
361 (sign_extend:DI (match_dup 1)))]
362 "TARGET_POWERPC64 && reload_completed"
363 [(set (match_dup 0)
364 (sign_extend:DI (match_dup 1)))
365 (set (match_dup 2)
366 (compare:CC (match_dup 0)
367 (const_int 0)))]
368 "")
370 (define_expand "extendhidi2"
371 [(set (match_operand:DI 0 "gpc_reg_operand" "")
372 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
373 "TARGET_POWERPC64"
374 "")
376 (define_insn ""
377 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
378 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
379 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
380 "@
381 lha%U1%X1 %0,%1
382 extsh %0,%1"
383 [(set_attr "type" "load_ext,exts")])
385 (define_insn ""
386 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
387 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
388 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
389 "extsh %0,%1"
390 [(set_attr "type" "exts")])
392 (define_insn ""
393 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
394 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
395 (const_int 0)))
396 (clobber (match_scratch:DI 2 "=r,r"))]
397 "TARGET_64BIT"
398 "@
399 extsh. %2,%1
400 #"
401 [(set_attr "type" "compare")
402 (set_attr "length" "4,8")])
404 (define_split
405 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
406 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
407 (const_int 0)))
408 (clobber (match_scratch:DI 2 ""))]
409 "TARGET_POWERPC64 && reload_completed"
410 [(set (match_dup 2)
411 (sign_extend:DI (match_dup 1)))
412 (set (match_dup 0)
413 (compare:CC (match_dup 2)
414 (const_int 0)))]
415 "")
417 (define_insn ""
418 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
419 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
420 (const_int 0)))
421 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
422 (sign_extend:DI (match_dup 1)))]
423 "TARGET_64BIT"
424 "@
425 extsh. %0,%1
426 #"
427 [(set_attr "type" "compare")
428 (set_attr "length" "4,8")])
430 (define_split
431 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
432 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
433 (const_int 0)))
434 (set (match_operand:DI 0 "gpc_reg_operand" "")
435 (sign_extend:DI (match_dup 1)))]
436 "TARGET_POWERPC64 && reload_completed"
437 [(set (match_dup 0)
438 (sign_extend:DI (match_dup 1)))
439 (set (match_dup 2)
440 (compare:CC (match_dup 0)
441 (const_int 0)))]
442 "")
444 (define_expand "extendsidi2"
445 [(set (match_operand:DI 0 "gpc_reg_operand" "")
446 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
447 "TARGET_POWERPC64"
448 "")
450 (define_insn ""
451 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
452 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
453 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
454 "@
455 lwa%U1%X1 %0,%1
456 extsw %0,%1"
457 [(set_attr "type" "load_ext,exts")])
459 (define_insn ""
460 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
461 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
462 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
463 "extsw %0,%1"
464 [(set_attr "type" "exts")])
466 (define_insn ""
467 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
468 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
469 (const_int 0)))
470 (clobber (match_scratch:DI 2 "=r,r"))]
471 "TARGET_64BIT"
472 "@
473 extsw. %2,%1
474 #"
475 [(set_attr "type" "compare")
476 (set_attr "length" "4,8")])
478 (define_split
479 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
480 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
481 (const_int 0)))
482 (clobber (match_scratch:DI 2 ""))]
483 "TARGET_POWERPC64 && reload_completed"
484 [(set (match_dup 2)
485 (sign_extend:DI (match_dup 1)))
486 (set (match_dup 0)
487 (compare:CC (match_dup 2)
488 (const_int 0)))]
489 "")
491 (define_insn ""
492 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
493 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
494 (const_int 0)))
495 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
496 (sign_extend:DI (match_dup 1)))]
497 "TARGET_64BIT"
498 "@
499 extsw. %0,%1
500 #"
501 [(set_attr "type" "compare")
502 (set_attr "length" "4,8")])
504 (define_split
505 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
506 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
507 (const_int 0)))
508 (set (match_operand:DI 0 "gpc_reg_operand" "")
509 (sign_extend:DI (match_dup 1)))]
510 "TARGET_POWERPC64 && reload_completed"
511 [(set (match_dup 0)
512 (sign_extend:DI (match_dup 1)))
513 (set (match_dup 2)
514 (compare:CC (match_dup 0)
515 (const_int 0)))]
516 "")
518 (define_expand "zero_extendqisi2"
519 [(set (match_operand:SI 0 "gpc_reg_operand" "")
520 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
521 ""
522 "")
524 (define_insn ""
525 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
526 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
527 ""
528 "@
529 lbz%U1%X1 %0,%1
530 {rlinm|rlwinm} %0,%1,0,0xff"
531 [(set_attr "type" "load,*")])
533 (define_insn ""
534 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
535 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
536 (const_int 0)))
537 (clobber (match_scratch:SI 2 "=r,r"))]
538 ""
539 "@
540 {andil.|andi.} %2,%1,0xff
541 #"
542 [(set_attr "type" "fast_compare,compare")
543 (set_attr "length" "4,8")])
545 (define_split
546 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
547 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
548 (const_int 0)))
549 (clobber (match_scratch:SI 2 ""))]
550 "reload_completed"
551 [(set (match_dup 2)
552 (zero_extend:SI (match_dup 1)))
553 (set (match_dup 0)
554 (compare:CC (match_dup 2)
555 (const_int 0)))]
556 "")
558 (define_insn ""
559 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
560 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
561 (const_int 0)))
562 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
563 (zero_extend:SI (match_dup 1)))]
564 ""
565 "@
566 {andil.|andi.} %0,%1,0xff
567 #"
568 [(set_attr "type" "fast_compare,compare")
569 (set_attr "length" "4,8")])
571 (define_split
572 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
573 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
574 (const_int 0)))
575 (set (match_operand:SI 0 "gpc_reg_operand" "")
576 (zero_extend:SI (match_dup 1)))]
577 "reload_completed"
578 [(set (match_dup 0)
579 (zero_extend:SI (match_dup 1)))
580 (set (match_dup 2)
581 (compare:CC (match_dup 0)
582 (const_int 0)))]
583 "")
585 (define_expand "extendqisi2"
586 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
587 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
588 ""
589 "
590 {
591 if (TARGET_POWERPC)
592 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
593 else if (TARGET_POWER)
594 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
595 else
596 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
597 DONE;
598 }")
600 (define_insn "extendqisi2_ppc"
601 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
602 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
603 "TARGET_POWERPC"
604 "extsb %0,%1"
605 [(set_attr "type" "exts")])
607 (define_insn ""
608 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
609 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
610 (const_int 0)))
611 (clobber (match_scratch:SI 2 "=r,r"))]
612 "TARGET_POWERPC"
613 "@
614 extsb. %2,%1
615 #"
616 [(set_attr "type" "compare")
617 (set_attr "length" "4,8")])
619 (define_split
620 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
621 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
622 (const_int 0)))
623 (clobber (match_scratch:SI 2 ""))]
624 "TARGET_POWERPC && reload_completed"
625 [(set (match_dup 2)
626 (sign_extend:SI (match_dup 1)))
627 (set (match_dup 0)
628 (compare:CC (match_dup 2)
629 (const_int 0)))]
630 "")
632 (define_insn ""
633 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
634 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
635 (const_int 0)))
636 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
637 (sign_extend:SI (match_dup 1)))]
638 "TARGET_POWERPC"
639 "@
640 extsb. %0,%1
641 #"
642 [(set_attr "type" "compare")
643 (set_attr "length" "4,8")])
645 (define_split
646 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
647 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
648 (const_int 0)))
649 (set (match_operand:SI 0 "gpc_reg_operand" "")
650 (sign_extend:SI (match_dup 1)))]
651 "TARGET_POWERPC && reload_completed"
652 [(set (match_dup 0)
653 (sign_extend:SI (match_dup 1)))
654 (set (match_dup 2)
655 (compare:CC (match_dup 0)
656 (const_int 0)))]
657 "")
659 (define_expand "extendqisi2_power"
660 [(parallel [(set (match_dup 2)
661 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
662 (const_int 24)))
663 (clobber (scratch:SI))])
664 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
665 (ashiftrt:SI (match_dup 2)
666 (const_int 24)))
667 (clobber (scratch:SI))])]
668 "TARGET_POWER"
669 "
670 { operands[1] = gen_lowpart (SImode, operands[1]);
671 operands[2] = gen_reg_rtx (SImode); }")
673 (define_expand "extendqisi2_no_power"
674 [(set (match_dup 2)
675 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
676 (const_int 24)))
677 (set (match_operand:SI 0 "gpc_reg_operand" "")
678 (ashiftrt:SI (match_dup 2)
679 (const_int 24)))]
680 "! TARGET_POWER && ! TARGET_POWERPC"
681 "
682 { operands[1] = gen_lowpart (SImode, operands[1]);
683 operands[2] = gen_reg_rtx (SImode); }")
685 (define_expand "zero_extendqihi2"
686 [(set (match_operand:HI 0 "gpc_reg_operand" "")
687 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
688 ""
689 "")
691 (define_insn ""
692 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
693 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
694 ""
695 "@
696 lbz%U1%X1 %0,%1
697 {rlinm|rlwinm} %0,%1,0,0xff"
698 [(set_attr "type" "load,*")])
700 (define_insn ""
701 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
702 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
703 (const_int 0)))
704 (clobber (match_scratch:HI 2 "=r,r"))]
705 ""
706 "@
707 {andil.|andi.} %2,%1,0xff
708 #"
709 [(set_attr "type" "fast_compare,compare")
710 (set_attr "length" "4,8")])
712 (define_split
713 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
714 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
715 (const_int 0)))
716 (clobber (match_scratch:HI 2 ""))]
717 "reload_completed"
718 [(set (match_dup 2)
719 (zero_extend:HI (match_dup 1)))
720 (set (match_dup 0)
721 (compare:CC (match_dup 2)
722 (const_int 0)))]
723 "")
725 (define_insn ""
726 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
727 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
728 (const_int 0)))
729 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
730 (zero_extend:HI (match_dup 1)))]
731 ""
732 "@
733 {andil.|andi.} %0,%1,0xff
734 #"
735 [(set_attr "type" "fast_compare,compare")
736 (set_attr "length" "4,8")])
738 (define_split
739 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
740 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
741 (const_int 0)))
742 (set (match_operand:HI 0 "gpc_reg_operand" "")
743 (zero_extend:HI (match_dup 1)))]
744 "reload_completed"
745 [(set (match_dup 0)
746 (zero_extend:HI (match_dup 1)))
747 (set (match_dup 2)
748 (compare:CC (match_dup 0)
749 (const_int 0)))]
750 "")
752 (define_expand "extendqihi2"
753 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
754 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
755 ""
756 "
757 {
758 if (TARGET_POWERPC)
759 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
760 else if (TARGET_POWER)
761 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
762 else
763 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
764 DONE;
765 }")
767 (define_insn "extendqihi2_ppc"
768 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
769 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
770 "TARGET_POWERPC"
771 "extsb %0,%1"
772 [(set_attr "type" "exts")])
774 (define_insn ""
775 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
776 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
777 (const_int 0)))
778 (clobber (match_scratch:HI 2 "=r,r"))]
779 "TARGET_POWERPC"
780 "@
781 extsb. %2,%1
782 #"
783 [(set_attr "type" "compare")
784 (set_attr "length" "4,8")])
786 (define_split
787 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
788 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
789 (const_int 0)))
790 (clobber (match_scratch:HI 2 ""))]
791 "TARGET_POWERPC && reload_completed"
792 [(set (match_dup 2)
793 (sign_extend:HI (match_dup 1)))
794 (set (match_dup 0)
795 (compare:CC (match_dup 2)
796 (const_int 0)))]
797 "")
799 (define_insn ""
800 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
801 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
802 (const_int 0)))
803 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
804 (sign_extend:HI (match_dup 1)))]
805 "TARGET_POWERPC"
806 "@
807 extsb. %0,%1
808 #"
809 [(set_attr "type" "compare")
810 (set_attr "length" "4,8")])
812 (define_split
813 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
814 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
815 (const_int 0)))
816 (set (match_operand:HI 0 "gpc_reg_operand" "")
817 (sign_extend:HI (match_dup 1)))]
818 "TARGET_POWERPC && reload_completed"
819 [(set (match_dup 0)
820 (sign_extend:HI (match_dup 1)))
821 (set (match_dup 2)
822 (compare:CC (match_dup 0)
823 (const_int 0)))]
824 "")
826 (define_expand "extendqihi2_power"
827 [(parallel [(set (match_dup 2)
828 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
829 (const_int 24)))
830 (clobber (scratch:SI))])
831 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
832 (ashiftrt:SI (match_dup 2)
833 (const_int 24)))
834 (clobber (scratch:SI))])]
835 "TARGET_POWER"
836 "
837 { operands[0] = gen_lowpart (SImode, operands[0]);
838 operands[1] = gen_lowpart (SImode, operands[1]);
839 operands[2] = gen_reg_rtx (SImode); }")
841 (define_expand "extendqihi2_no_power"
842 [(set (match_dup 2)
843 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
844 (const_int 24)))
845 (set (match_operand:HI 0 "gpc_reg_operand" "")
846 (ashiftrt:SI (match_dup 2)
847 (const_int 24)))]
848 "! TARGET_POWER && ! TARGET_POWERPC"
849 "
850 { operands[0] = gen_lowpart (SImode, operands[0]);
851 operands[1] = gen_lowpart (SImode, operands[1]);
852 operands[2] = gen_reg_rtx (SImode); }")
854 (define_expand "zero_extendhisi2"
855 [(set (match_operand:SI 0 "gpc_reg_operand" "")
856 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
857 ""
858 "")
860 (define_insn ""
861 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
862 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
863 ""
864 "@
865 lhz%U1%X1 %0,%1
866 {rlinm|rlwinm} %0,%1,0,0xffff"
867 [(set_attr "type" "load,*")])
869 (define_insn ""
870 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
871 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
872 (const_int 0)))
873 (clobber (match_scratch:SI 2 "=r,r"))]
874 ""
875 "@
876 {andil.|andi.} %2,%1,0xffff
877 #"
878 [(set_attr "type" "fast_compare,compare")
879 (set_attr "length" "4,8")])
881 (define_split
882 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
883 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
884 (const_int 0)))
885 (clobber (match_scratch:SI 2 ""))]
886 "reload_completed"
887 [(set (match_dup 2)
888 (zero_extend:SI (match_dup 1)))
889 (set (match_dup 0)
890 (compare:CC (match_dup 2)
891 (const_int 0)))]
892 "")
894 (define_insn ""
895 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
896 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
897 (const_int 0)))
898 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
899 (zero_extend:SI (match_dup 1)))]
900 ""
901 "@
902 {andil.|andi.} %0,%1,0xffff
903 #"
904 [(set_attr "type" "fast_compare,compare")
905 (set_attr "length" "4,8")])
907 (define_split
908 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
909 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
910 (const_int 0)))
911 (set (match_operand:SI 0 "gpc_reg_operand" "")
912 (zero_extend:SI (match_dup 1)))]
913 "reload_completed"
914 [(set (match_dup 0)
915 (zero_extend:SI (match_dup 1)))
916 (set (match_dup 2)
917 (compare:CC (match_dup 0)
918 (const_int 0)))]
919 "")
921 (define_expand "extendhisi2"
922 [(set (match_operand:SI 0 "gpc_reg_operand" "")
923 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
924 ""
925 "")
927 (define_insn ""
928 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
929 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
930 "rs6000_gen_cell_microcode"
931 "@
932 lha%U1%X1 %0,%1
933 {exts|extsh} %0,%1"
934 [(set_attr "type" "load_ext,exts")])
936 (define_insn ""
937 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
938 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
939 "!rs6000_gen_cell_microcode"
940 "{exts|extsh} %0,%1"
941 [(set_attr "type" "exts")])
943 (define_insn ""
944 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
945 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
946 (const_int 0)))
947 (clobber (match_scratch:SI 2 "=r,r"))]
948 ""
949 "@
950 {exts.|extsh.} %2,%1
951 #"
952 [(set_attr "type" "compare")
953 (set_attr "length" "4,8")])
955 (define_split
956 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
957 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
958 (const_int 0)))
959 (clobber (match_scratch:SI 2 ""))]
960 "reload_completed"
961 [(set (match_dup 2)
962 (sign_extend:SI (match_dup 1)))
963 (set (match_dup 0)
964 (compare:CC (match_dup 2)
965 (const_int 0)))]
966 "")
968 (define_insn ""
969 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
970 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
971 (const_int 0)))
972 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
973 (sign_extend:SI (match_dup 1)))]
974 ""
975 "@
976 {exts.|extsh.} %0,%1
977 #"
978 [(set_attr "type" "compare")
979 (set_attr "length" "4,8")])
980 \f
981 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
983 (define_insn "*macchwc"
984 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
985 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
986 (match_operand:SI 2 "gpc_reg_operand" "r")
987 (const_int 16))
988 (sign_extend:SI
989 (match_operand:HI 1 "gpc_reg_operand" "r")))
990 (match_operand:SI 4 "gpc_reg_operand" "0"))
991 (const_int 0)))
992 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
993 (plus:SI (mult:SI (ashiftrt:SI
994 (match_dup 2)
995 (const_int 16))
996 (sign_extend:SI
997 (match_dup 1)))
998 (match_dup 4)))]
999 "TARGET_MULHW"
1000 "macchw. %0, %1, %2"
1001 [(set_attr "type" "imul3")])
1003 (define_insn "*macchw"
1004 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1005 (plus:SI (mult:SI (ashiftrt:SI
1006 (match_operand:SI 2 "gpc_reg_operand" "r")
1007 (const_int 16))
1008 (sign_extend:SI
1009 (match_operand:HI 1 "gpc_reg_operand" "r")))
1010 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1011 "TARGET_MULHW"
1012 "macchw %0, %1, %2"
1013 [(set_attr "type" "imul3")])
1015 (define_insn "*macchwuc"
1016 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1017 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1018 (match_operand:SI 2 "gpc_reg_operand" "r")
1019 (const_int 16))
1020 (zero_extend:SI
1021 (match_operand:HI 1 "gpc_reg_operand" "r")))
1022 (match_operand:SI 4 "gpc_reg_operand" "0"))
1023 (const_int 0)))
1024 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1025 (plus:SI (mult:SI (lshiftrt:SI
1026 (match_dup 2)
1027 (const_int 16))
1028 (zero_extend:SI
1029 (match_dup 1)))
1030 (match_dup 4)))]
1031 "TARGET_MULHW"
1032 "macchwu. %0, %1, %2"
1033 [(set_attr "type" "imul3")])
1035 (define_insn "*macchwu"
1036 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1037 (plus:SI (mult:SI (lshiftrt:SI
1038 (match_operand:SI 2 "gpc_reg_operand" "r")
1039 (const_int 16))
1040 (zero_extend:SI
1041 (match_operand:HI 1 "gpc_reg_operand" "r")))
1042 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1043 "TARGET_MULHW"
1044 "macchwu %0, %1, %2"
1045 [(set_attr "type" "imul3")])
1047 (define_insn "*machhwc"
1048 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1049 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1050 (match_operand:SI 1 "gpc_reg_operand" "%r")
1051 (const_int 16))
1052 (ashiftrt:SI
1053 (match_operand:SI 2 "gpc_reg_operand" "r")
1054 (const_int 16)))
1055 (match_operand:SI 4 "gpc_reg_operand" "0"))
1056 (const_int 0)))
1057 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1058 (plus:SI (mult:SI (ashiftrt:SI
1059 (match_dup 1)
1060 (const_int 16))
1061 (ashiftrt:SI
1062 (match_dup 2)
1063 (const_int 16)))
1064 (match_dup 4)))]
1065 "TARGET_MULHW"
1066 "machhw. %0, %1, %2"
1067 [(set_attr "type" "imul3")])
1069 (define_insn "*machhw"
1070 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1071 (plus:SI (mult:SI (ashiftrt:SI
1072 (match_operand:SI 1 "gpc_reg_operand" "%r")
1073 (const_int 16))
1074 (ashiftrt:SI
1075 (match_operand:SI 2 "gpc_reg_operand" "r")
1076 (const_int 16)))
1077 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1078 "TARGET_MULHW"
1079 "machhw %0, %1, %2"
1080 [(set_attr "type" "imul3")])
1082 (define_insn "*machhwuc"
1083 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1084 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1085 (match_operand:SI 1 "gpc_reg_operand" "%r")
1086 (const_int 16))
1087 (lshiftrt:SI
1088 (match_operand:SI 2 "gpc_reg_operand" "r")
1089 (const_int 16)))
1090 (match_operand:SI 4 "gpc_reg_operand" "0"))
1091 (const_int 0)))
1092 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1093 (plus:SI (mult:SI (lshiftrt:SI
1094 (match_dup 1)
1095 (const_int 16))
1096 (lshiftrt:SI
1097 (match_dup 2)
1098 (const_int 16)))
1099 (match_dup 4)))]
1100 "TARGET_MULHW"
1101 "machhwu. %0, %1, %2"
1102 [(set_attr "type" "imul3")])
1104 (define_insn "*machhwu"
1105 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1106 (plus:SI (mult:SI (lshiftrt:SI
1107 (match_operand:SI 1 "gpc_reg_operand" "%r")
1108 (const_int 16))
1109 (lshiftrt:SI
1110 (match_operand:SI 2 "gpc_reg_operand" "r")
1111 (const_int 16)))
1112 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1113 "TARGET_MULHW"
1114 "machhwu %0, %1, %2"
1115 [(set_attr "type" "imul3")])
1117 (define_insn "*maclhwc"
1118 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1119 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1120 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1121 (sign_extend:SI
1122 (match_operand:HI 2 "gpc_reg_operand" "r")))
1123 (match_operand:SI 4 "gpc_reg_operand" "0"))
1124 (const_int 0)))
1125 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1126 (plus:SI (mult:SI (sign_extend:SI
1127 (match_dup 1))
1128 (sign_extend:SI
1129 (match_dup 2)))
1130 (match_dup 4)))]
1131 "TARGET_MULHW"
1132 "maclhw. %0, %1, %2"
1133 [(set_attr "type" "imul3")])
1135 (define_insn "*maclhw"
1136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1137 (plus:SI (mult:SI (sign_extend:SI
1138 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1139 (sign_extend:SI
1140 (match_operand:HI 2 "gpc_reg_operand" "r")))
1141 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1142 "TARGET_MULHW"
1143 "maclhw %0, %1, %2"
1144 [(set_attr "type" "imul3")])
1146 (define_insn "*maclhwuc"
1147 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1148 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1149 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1150 (zero_extend:SI
1151 (match_operand:HI 2 "gpc_reg_operand" "r")))
1152 (match_operand:SI 4 "gpc_reg_operand" "0"))
1153 (const_int 0)))
1154 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1155 (plus:SI (mult:SI (zero_extend:SI
1156 (match_dup 1))
1157 (zero_extend:SI
1158 (match_dup 2)))
1159 (match_dup 4)))]
1160 "TARGET_MULHW"
1161 "maclhwu. %0, %1, %2"
1162 [(set_attr "type" "imul3")])
1164 (define_insn "*maclhwu"
1165 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1166 (plus:SI (mult:SI (zero_extend:SI
1167 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1168 (zero_extend:SI
1169 (match_operand:HI 2 "gpc_reg_operand" "r")))
1170 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1171 "TARGET_MULHW"
1172 "maclhwu %0, %1, %2"
1173 [(set_attr "type" "imul3")])
1175 (define_insn "*nmacchwc"
1176 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1177 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1178 (mult:SI (ashiftrt:SI
1179 (match_operand:SI 2 "gpc_reg_operand" "r")
1180 (const_int 16))
1181 (sign_extend:SI
1182 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1183 (const_int 0)))
1184 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1185 (minus:SI (match_dup 4)
1186 (mult:SI (ashiftrt:SI
1187 (match_dup 2)
1188 (const_int 16))
1189 (sign_extend:SI
1190 (match_dup 1)))))]
1191 "TARGET_MULHW"
1192 "nmacchw. %0, %1, %2"
1193 [(set_attr "type" "imul3")])
1195 (define_insn "*nmacchw"
1196 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1197 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1198 (mult:SI (ashiftrt:SI
1199 (match_operand:SI 2 "gpc_reg_operand" "r")
1200 (const_int 16))
1201 (sign_extend:SI
1202 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1203 "TARGET_MULHW"
1204 "nmacchw %0, %1, %2"
1205 [(set_attr "type" "imul3")])
1207 (define_insn "*nmachhwc"
1208 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1209 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1210 (mult:SI (ashiftrt:SI
1211 (match_operand:SI 1 "gpc_reg_operand" "%r")
1212 (const_int 16))
1213 (ashiftrt:SI
1214 (match_operand:SI 2 "gpc_reg_operand" "r")
1215 (const_int 16))))
1216 (const_int 0)))
1217 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1218 (minus:SI (match_dup 4)
1219 (mult:SI (ashiftrt:SI
1220 (match_dup 1)
1221 (const_int 16))
1222 (ashiftrt:SI
1223 (match_dup 2)
1224 (const_int 16)))))]
1225 "TARGET_MULHW"
1226 "nmachhw. %0, %1, %2"
1227 [(set_attr "type" "imul3")])
1229 (define_insn "*nmachhw"
1230 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1231 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1232 (mult:SI (ashiftrt:SI
1233 (match_operand:SI 1 "gpc_reg_operand" "%r")
1234 (const_int 16))
1235 (ashiftrt:SI
1236 (match_operand:SI 2 "gpc_reg_operand" "r")
1237 (const_int 16)))))]
1238 "TARGET_MULHW"
1239 "nmachhw %0, %1, %2"
1240 [(set_attr "type" "imul3")])
1242 (define_insn "*nmaclhwc"
1243 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1244 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1245 (mult:SI (sign_extend:SI
1246 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1247 (sign_extend:SI
1248 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1249 (const_int 0)))
1250 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1251 (minus:SI (match_dup 4)
1252 (mult:SI (sign_extend:SI
1253 (match_dup 1))
1254 (sign_extend:SI
1255 (match_dup 2)))))]
1256 "TARGET_MULHW"
1257 "nmaclhw. %0, %1, %2"
1258 [(set_attr "type" "imul3")])
1260 (define_insn "*nmaclhw"
1261 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1262 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1263 (mult:SI (sign_extend:SI
1264 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1265 (sign_extend:SI
1266 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1267 "TARGET_MULHW"
1268 "nmaclhw %0, %1, %2"
1269 [(set_attr "type" "imul3")])
1271 (define_insn "*mulchwc"
1272 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1273 (compare:CC (mult:SI (ashiftrt:SI
1274 (match_operand:SI 2 "gpc_reg_operand" "r")
1275 (const_int 16))
1276 (sign_extend:SI
1277 (match_operand:HI 1 "gpc_reg_operand" "r")))
1278 (const_int 0)))
1279 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1280 (mult:SI (ashiftrt:SI
1281 (match_dup 2)
1282 (const_int 16))
1283 (sign_extend:SI
1284 (match_dup 1))))]
1285 "TARGET_MULHW"
1286 "mulchw. %0, %1, %2"
1287 [(set_attr "type" "imul3")])
1289 (define_insn "*mulchw"
1290 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1291 (mult:SI (ashiftrt:SI
1292 (match_operand:SI 2 "gpc_reg_operand" "r")
1293 (const_int 16))
1294 (sign_extend:SI
1295 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1296 "TARGET_MULHW"
1297 "mulchw %0, %1, %2"
1298 [(set_attr "type" "imul3")])
1300 (define_insn "*mulchwuc"
1301 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1302 (compare:CC (mult:SI (lshiftrt:SI
1303 (match_operand:SI 2 "gpc_reg_operand" "r")
1304 (const_int 16))
1305 (zero_extend:SI
1306 (match_operand:HI 1 "gpc_reg_operand" "r")))
1307 (const_int 0)))
1308 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1309 (mult:SI (lshiftrt:SI
1310 (match_dup 2)
1311 (const_int 16))
1312 (zero_extend:SI
1313 (match_dup 1))))]
1314 "TARGET_MULHW"
1315 "mulchwu. %0, %1, %2"
1316 [(set_attr "type" "imul3")])
1318 (define_insn "*mulchwu"
1319 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1320 (mult:SI (lshiftrt:SI
1321 (match_operand:SI 2 "gpc_reg_operand" "r")
1322 (const_int 16))
1323 (zero_extend:SI
1324 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1325 "TARGET_MULHW"
1326 "mulchwu %0, %1, %2"
1327 [(set_attr "type" "imul3")])
1329 (define_insn "*mulhhwc"
1330 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1331 (compare:CC (mult:SI (ashiftrt:SI
1332 (match_operand:SI 1 "gpc_reg_operand" "%r")
1333 (const_int 16))
1334 (ashiftrt:SI
1335 (match_operand:SI 2 "gpc_reg_operand" "r")
1336 (const_int 16)))
1337 (const_int 0)))
1338 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1339 (mult:SI (ashiftrt:SI
1340 (match_dup 1)
1341 (const_int 16))
1342 (ashiftrt:SI
1343 (match_dup 2)
1344 (const_int 16))))]
1345 "TARGET_MULHW"
1346 "mulhhw. %0, %1, %2"
1347 [(set_attr "type" "imul3")])
1349 (define_insn "*mulhhw"
1350 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1351 (mult:SI (ashiftrt:SI
1352 (match_operand:SI 1 "gpc_reg_operand" "%r")
1353 (const_int 16))
1354 (ashiftrt:SI
1355 (match_operand:SI 2 "gpc_reg_operand" "r")
1356 (const_int 16))))]
1357 "TARGET_MULHW"
1358 "mulhhw %0, %1, %2"
1359 [(set_attr "type" "imul3")])
1361 (define_insn "*mulhhwuc"
1362 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1363 (compare:CC (mult:SI (lshiftrt:SI
1364 (match_operand:SI 1 "gpc_reg_operand" "%r")
1365 (const_int 16))
1366 (lshiftrt:SI
1367 (match_operand:SI 2 "gpc_reg_operand" "r")
1368 (const_int 16)))
1369 (const_int 0)))
1370 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1371 (mult:SI (lshiftrt:SI
1372 (match_dup 1)
1373 (const_int 16))
1374 (lshiftrt:SI
1375 (match_dup 2)
1376 (const_int 16))))]
1377 "TARGET_MULHW"
1378 "mulhhwu. %0, %1, %2"
1379 [(set_attr "type" "imul3")])
1381 (define_insn "*mulhhwu"
1382 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1383 (mult:SI (lshiftrt:SI
1384 (match_operand:SI 1 "gpc_reg_operand" "%r")
1385 (const_int 16))
1386 (lshiftrt:SI
1387 (match_operand:SI 2 "gpc_reg_operand" "r")
1388 (const_int 16))))]
1389 "TARGET_MULHW"
1390 "mulhhwu %0, %1, %2"
1391 [(set_attr "type" "imul3")])
1393 (define_insn "*mullhwc"
1394 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1395 (compare:CC (mult:SI (sign_extend:SI
1396 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1397 (sign_extend:SI
1398 (match_operand:HI 2 "gpc_reg_operand" "r")))
1399 (const_int 0)))
1400 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1401 (mult:SI (sign_extend:SI
1402 (match_dup 1))
1403 (sign_extend:SI
1404 (match_dup 2))))]
1405 "TARGET_MULHW"
1406 "mullhw. %0, %1, %2"
1407 [(set_attr "type" "imul3")])
1409 (define_insn "*mullhw"
1410 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1411 (mult:SI (sign_extend:SI
1412 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1413 (sign_extend:SI
1414 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1415 "TARGET_MULHW"
1416 "mullhw %0, %1, %2"
1417 [(set_attr "type" "imul3")])
1419 (define_insn "*mullhwuc"
1420 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1421 (compare:CC (mult:SI (zero_extend:SI
1422 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1423 (zero_extend:SI
1424 (match_operand:HI 2 "gpc_reg_operand" "r")))
1425 (const_int 0)))
1426 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1427 (mult:SI (zero_extend:SI
1428 (match_dup 1))
1429 (zero_extend:SI
1430 (match_dup 2))))]
1431 "TARGET_MULHW"
1432 "mullhwu. %0, %1, %2"
1433 [(set_attr "type" "imul3")])
1435 (define_insn "*mullhwu"
1436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1437 (mult:SI (zero_extend:SI
1438 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1439 (zero_extend:SI
1440 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1441 "TARGET_MULHW"
1442 "mullhwu %0, %1, %2"
1443 [(set_attr "type" "imul3")])
1444 \f
1445 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1446 (define_insn "dlmzb"
1447 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1448 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1449 (match_operand:SI 2 "gpc_reg_operand" "r")]
1450 UNSPEC_DLMZB_CR))
1451 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1452 (unspec:SI [(match_dup 1)
1453 (match_dup 2)]
1454 UNSPEC_DLMZB))]
1455 "TARGET_DLMZB"
1456 "dlmzb. %0, %1, %2")
1458 (define_expand "strlensi"
1459 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1460 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1461 (match_operand:QI 2 "const_int_operand" "")
1462 (match_operand 3 "const_int_operand" "")]
1463 UNSPEC_DLMZB_STRLEN))
1464 (clobber (match_scratch:CC 4 "=x"))]
1465 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1466 {
1467 rtx result = operands[0];
1468 rtx src = operands[1];
1469 rtx search_char = operands[2];
1470 rtx align = operands[3];
1471 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1472 rtx loop_label, end_label, mem, cr0, cond;
1473 if (search_char != const0_rtx
1474 || GET_CODE (align) != CONST_INT
1475 || INTVAL (align) < 8)
1476 FAIL;
1477 word1 = gen_reg_rtx (SImode);
1478 word2 = gen_reg_rtx (SImode);
1479 scratch_dlmzb = gen_reg_rtx (SImode);
1480 scratch_string = gen_reg_rtx (Pmode);
1481 loop_label = gen_label_rtx ();
1482 end_label = gen_label_rtx ();
1483 addr = force_reg (Pmode, XEXP (src, 0));
1484 emit_move_insn (scratch_string, addr);
1485 emit_label (loop_label);
1486 mem = change_address (src, SImode, scratch_string);
1487 emit_move_insn (word1, mem);
1488 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1489 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1490 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1491 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1492 emit_jump_insn (gen_rtx_SET (VOIDmode,
1493 pc_rtx,
1494 gen_rtx_IF_THEN_ELSE (VOIDmode,
1495 cond,
1496 gen_rtx_LABEL_REF
1497 (VOIDmode,
1498 end_label),
1499 pc_rtx)));
1500 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1501 emit_jump_insn (gen_rtx_SET (VOIDmode,
1502 pc_rtx,
1503 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1504 emit_barrier ();
1505 emit_label (end_label);
1506 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1507 emit_insn (gen_subsi3 (result, scratch_string, addr));
1508 emit_insn (gen_subsi3 (result, result, const1_rtx));
1509 DONE;
1510 })
1511 \f
1512 (define_split
1513 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1514 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1515 (const_int 0)))
1516 (set (match_operand:SI 0 "gpc_reg_operand" "")
1517 (sign_extend:SI (match_dup 1)))]
1518 "reload_completed"
1519 [(set (match_dup 0)
1520 (sign_extend:SI (match_dup 1)))
1521 (set (match_dup 2)
1522 (compare:CC (match_dup 0)
1523 (const_int 0)))]
1524 "")
1526 ;; Fixed-point arithmetic insns.
1528 (define_expand "add<mode>3"
1529 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1530 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1531 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1532 ""
1533 {
1534 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1535 {
1536 if (non_short_cint_operand (operands[2], DImode))
1537 FAIL;
1538 }
1539 else if (GET_CODE (operands[2]) == CONST_INT
1540 && ! add_operand (operands[2], <MODE>mode))
1541 {
1542 rtx tmp = ((!can_create_pseudo_p ()
1543 || rtx_equal_p (operands[0], operands[1]))
1544 ? operands[0] : gen_reg_rtx (<MODE>mode));
1546 HOST_WIDE_INT val = INTVAL (operands[2]);
1547 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1548 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1550 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1551 FAIL;
1553 /* The ordering here is important for the prolog expander.
1554 When space is allocated from the stack, adding 'low' first may
1555 produce a temporary deallocation (which would be bad). */
1556 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1557 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1558 DONE;
1559 }
1560 })
1562 ;; Discourage ai/addic because of carry but provide it in an alternative
1563 ;; allowing register zero as source.
1564 (define_insn "*add<mode>3_internal1"
1565 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1566 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1567 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1568 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1569 "@
1570 {cax|add} %0,%1,%2
1571 {cal %0,%2(%1)|addi %0,%1,%2}
1572 {ai|addic} %0,%1,%2
1573 {cau|addis} %0,%1,%v2"
1574 [(set_attr "length" "4,4,4,4")])
1576 (define_insn "addsi3_high"
1577 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1578 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1579 (high:SI (match_operand 2 "" ""))))]
1580 "TARGET_MACHO && !TARGET_64BIT"
1581 "{cau|addis} %0,%1,ha16(%2)"
1582 [(set_attr "length" "4")])
1584 (define_insn "*add<mode>3_internal2"
1585 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1586 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1587 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1588 (const_int 0)))
1589 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1590 ""
1591 "@
1592 {cax.|add.} %3,%1,%2
1593 {ai.|addic.} %3,%1,%2
1594 #
1595 #"
1596 [(set_attr "type" "fast_compare,compare,compare,compare")
1597 (set_attr "length" "4,4,8,8")])
1599 (define_split
1600 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1601 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1602 (match_operand:GPR 2 "reg_or_short_operand" ""))
1603 (const_int 0)))
1604 (clobber (match_scratch:GPR 3 ""))]
1605 "reload_completed"
1606 [(set (match_dup 3)
1607 (plus:GPR (match_dup 1)
1608 (match_dup 2)))
1609 (set (match_dup 0)
1610 (compare:CC (match_dup 3)
1611 (const_int 0)))]
1612 "")
1614 (define_insn "*add<mode>3_internal3"
1615 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1616 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1617 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1618 (const_int 0)))
1619 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1620 (plus:P (match_dup 1)
1621 (match_dup 2)))]
1622 ""
1623 "@
1624 {cax.|add.} %0,%1,%2
1625 {ai.|addic.} %0,%1,%2
1626 #
1627 #"
1628 [(set_attr "type" "fast_compare,compare,compare,compare")
1629 (set_attr "length" "4,4,8,8")])
1631 (define_split
1632 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1633 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1634 (match_operand:P 2 "reg_or_short_operand" ""))
1635 (const_int 0)))
1636 (set (match_operand:P 0 "gpc_reg_operand" "")
1637 (plus:P (match_dup 1) (match_dup 2)))]
1638 "reload_completed"
1639 [(set (match_dup 0)
1640 (plus:P (match_dup 1)
1641 (match_dup 2)))
1642 (set (match_dup 3)
1643 (compare:CC (match_dup 0)
1644 (const_int 0)))]
1645 "")
1647 ;; Split an add that we can't do in one insn into two insns, each of which
1648 ;; does one 16-bit part. This is used by combine. Note that the low-order
1649 ;; add should be last in case the result gets used in an address.
1651 (define_split
1652 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1653 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1654 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1655 ""
1656 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1657 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1658 {
1659 HOST_WIDE_INT val = INTVAL (operands[2]);
1660 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1661 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1663 operands[4] = GEN_INT (low);
1664 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1665 operands[3] = GEN_INT (rest);
1666 else if (can_create_pseudo_p ())
1667 {
1668 operands[3] = gen_reg_rtx (DImode);
1669 emit_move_insn (operands[3], operands[2]);
1670 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1671 DONE;
1672 }
1673 else
1674 FAIL;
1675 })
1677 (define_insn "one_cmpl<mode>2"
1678 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1679 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1680 ""
1681 "nor %0,%1,%1")
1683 (define_insn ""
1684 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1685 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1686 (const_int 0)))
1687 (clobber (match_scratch:P 2 "=r,r"))]
1688 ""
1689 "@
1690 nor. %2,%1,%1
1691 #"
1692 [(set_attr "type" "fast_compare,compare")
1693 (set_attr "length" "4,8")])
1695 (define_split
1696 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1697 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1698 (const_int 0)))
1699 (clobber (match_scratch:P 2 ""))]
1700 "reload_completed"
1701 [(set (match_dup 2)
1702 (not:P (match_dup 1)))
1703 (set (match_dup 0)
1704 (compare:CC (match_dup 2)
1705 (const_int 0)))]
1706 "")
1708 (define_insn ""
1709 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1710 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1711 (const_int 0)))
1712 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1713 (not:P (match_dup 1)))]
1714 ""
1715 "@
1716 nor. %0,%1,%1
1717 #"
1718 [(set_attr "type" "fast_compare,compare")
1719 (set_attr "length" "4,8")])
1721 (define_split
1722 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1723 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1724 (const_int 0)))
1725 (set (match_operand:P 0 "gpc_reg_operand" "")
1726 (not:P (match_dup 1)))]
1727 "reload_completed"
1728 [(set (match_dup 0)
1729 (not:P (match_dup 1)))
1730 (set (match_dup 2)
1731 (compare:CC (match_dup 0)
1732 (const_int 0)))]
1733 "")
1735 (define_insn ""
1736 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1737 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1738 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1739 "! TARGET_POWERPC"
1740 "{sf%I1|subf%I1c} %0,%2,%1")
1742 (define_insn ""
1743 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1744 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1745 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1746 "TARGET_POWERPC"
1747 "@
1748 subf %0,%2,%1
1749 subfic %0,%2,%1")
1751 (define_insn ""
1752 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1753 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1754 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1755 (const_int 0)))
1756 (clobber (match_scratch:SI 3 "=r,r"))]
1757 "! TARGET_POWERPC"
1758 "@
1759 {sf.|subfc.} %3,%2,%1
1760 #"
1761 [(set_attr "type" "compare")
1762 (set_attr "length" "4,8")])
1764 (define_insn ""
1765 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1766 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1767 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1768 (const_int 0)))
1769 (clobber (match_scratch:P 3 "=r,r"))]
1770 "TARGET_POWERPC"
1771 "@
1772 subf. %3,%2,%1
1773 #"
1774 [(set_attr "type" "fast_compare")
1775 (set_attr "length" "4,8")])
1777 (define_split
1778 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1779 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1780 (match_operand:P 2 "gpc_reg_operand" ""))
1781 (const_int 0)))
1782 (clobber (match_scratch:P 3 ""))]
1783 "reload_completed"
1784 [(set (match_dup 3)
1785 (minus:P (match_dup 1)
1786 (match_dup 2)))
1787 (set (match_dup 0)
1788 (compare:CC (match_dup 3)
1789 (const_int 0)))]
1790 "")
1792 (define_insn ""
1793 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1794 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1795 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1796 (const_int 0)))
1797 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1798 (minus:SI (match_dup 1) (match_dup 2)))]
1799 "! TARGET_POWERPC"
1800 "@
1801 {sf.|subfc.} %0,%2,%1
1802 #"
1803 [(set_attr "type" "compare")
1804 (set_attr "length" "4,8")])
1806 (define_insn ""
1807 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1808 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1809 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1810 (const_int 0)))
1811 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1812 (minus:P (match_dup 1)
1813 (match_dup 2)))]
1814 "TARGET_POWERPC"
1815 "@
1816 subf. %0,%2,%1
1817 #"
1818 [(set_attr "type" "fast_compare")
1819 (set_attr "length" "4,8")])
1821 (define_split
1822 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1823 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1824 (match_operand:P 2 "gpc_reg_operand" ""))
1825 (const_int 0)))
1826 (set (match_operand:P 0 "gpc_reg_operand" "")
1827 (minus:P (match_dup 1)
1828 (match_dup 2)))]
1829 "reload_completed"
1830 [(set (match_dup 0)
1831 (minus:P (match_dup 1)
1832 (match_dup 2)))
1833 (set (match_dup 3)
1834 (compare:CC (match_dup 0)
1835 (const_int 0)))]
1836 "")
1838 (define_expand "sub<mode>3"
1839 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1840 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1841 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1842 ""
1843 "
1844 {
1845 if (GET_CODE (operands[2]) == CONST_INT)
1846 {
1847 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1848 negate_rtx (<MODE>mode, operands[2])));
1849 DONE;
1850 }
1851 }")
1853 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1854 ;; instruction and some auxiliary computations. Then we just have a single
1855 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1856 ;; combine.
1858 (define_expand "sminsi3"
1859 [(set (match_dup 3)
1860 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1861 (match_operand:SI 2 "reg_or_short_operand" ""))
1862 (const_int 0)
1863 (minus:SI (match_dup 2) (match_dup 1))))
1864 (set (match_operand:SI 0 "gpc_reg_operand" "")
1865 (minus:SI (match_dup 2) (match_dup 3)))]
1866 "TARGET_POWER || TARGET_ISEL"
1867 "
1868 {
1869 if (TARGET_ISEL)
1870 {
1871 operands[2] = force_reg (SImode, operands[2]);
1872 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1873 DONE;
1874 }
1876 operands[3] = gen_reg_rtx (SImode);
1877 }")
1879 (define_split
1880 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1881 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1882 (match_operand:SI 2 "reg_or_short_operand" "")))
1883 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1884 "TARGET_POWER"
1885 [(set (match_dup 3)
1886 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1887 (const_int 0)
1888 (minus:SI (match_dup 2) (match_dup 1))))
1889 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1890 "")
1892 (define_expand "smaxsi3"
1893 [(set (match_dup 3)
1894 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1895 (match_operand:SI 2 "reg_or_short_operand" ""))
1896 (const_int 0)
1897 (minus:SI (match_dup 2) (match_dup 1))))
1898 (set (match_operand:SI 0 "gpc_reg_operand" "")
1899 (plus:SI (match_dup 3) (match_dup 1)))]
1900 "TARGET_POWER || TARGET_ISEL"
1901 "
1902 {
1903 if (TARGET_ISEL)
1904 {
1905 operands[2] = force_reg (SImode, operands[2]);
1906 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1907 DONE;
1908 }
1909 operands[3] = gen_reg_rtx (SImode);
1910 }")
1912 (define_split
1913 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1914 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1915 (match_operand:SI 2 "reg_or_short_operand" "")))
1916 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1917 "TARGET_POWER"
1918 [(set (match_dup 3)
1919 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1920 (const_int 0)
1921 (minus:SI (match_dup 2) (match_dup 1))))
1922 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1923 "")
1925 (define_expand "uminsi3"
1926 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1927 (match_dup 5)))
1928 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1929 (match_dup 5)))
1930 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1931 (const_int 0)
1932 (minus:SI (match_dup 4) (match_dup 3))))
1933 (set (match_operand:SI 0 "gpc_reg_operand" "")
1934 (minus:SI (match_dup 2) (match_dup 3)))]
1935 "TARGET_POWER || TARGET_ISEL"
1936 "
1937 {
1938 if (TARGET_ISEL)
1939 {
1940 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1941 DONE;
1942 }
1943 operands[3] = gen_reg_rtx (SImode);
1944 operands[4] = gen_reg_rtx (SImode);
1945 operands[5] = GEN_INT (-2147483647 - 1);
1946 }")
1948 (define_expand "umaxsi3"
1949 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1950 (match_dup 5)))
1951 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1952 (match_dup 5)))
1953 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1954 (const_int 0)
1955 (minus:SI (match_dup 4) (match_dup 3))))
1956 (set (match_operand:SI 0 "gpc_reg_operand" "")
1957 (plus:SI (match_dup 3) (match_dup 1)))]
1958 "TARGET_POWER || TARGET_ISEL"
1959 "
1960 {
1961 if (TARGET_ISEL)
1962 {
1963 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1964 DONE;
1965 }
1966 operands[3] = gen_reg_rtx (SImode);
1967 operands[4] = gen_reg_rtx (SImode);
1968 operands[5] = GEN_INT (-2147483647 - 1);
1969 }")
1971 (define_insn ""
1972 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1973 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1974 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1975 (const_int 0)
1976 (minus:SI (match_dup 2) (match_dup 1))))]
1977 "TARGET_POWER"
1978 "doz%I2 %0,%1,%2")
1980 (define_insn ""
1981 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1982 (compare:CC
1983 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1984 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1985 (const_int 0)
1986 (minus:SI (match_dup 2) (match_dup 1)))
1987 (const_int 0)))
1988 (clobber (match_scratch:SI 3 "=r,r"))]
1989 "TARGET_POWER"
1990 "@
1991 doz%I2. %3,%1,%2
1992 #"
1993 [(set_attr "type" "delayed_compare")
1994 (set_attr "length" "4,8")])
1996 (define_split
1997 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1998 (compare:CC
1999 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2000 (match_operand:SI 2 "reg_or_short_operand" ""))
2001 (const_int 0)
2002 (minus:SI (match_dup 2) (match_dup 1)))
2003 (const_int 0)))
2004 (clobber (match_scratch:SI 3 ""))]
2005 "TARGET_POWER && reload_completed"
2006 [(set (match_dup 3)
2007 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2008 (const_int 0)
2009 (minus:SI (match_dup 2) (match_dup 1))))
2010 (set (match_dup 0)
2011 (compare:CC (match_dup 3)
2012 (const_int 0)))]
2013 "")
2015 (define_insn ""
2016 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2017 (compare:CC
2018 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2019 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2020 (const_int 0)
2021 (minus:SI (match_dup 2) (match_dup 1)))
2022 (const_int 0)))
2023 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2024 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2025 (const_int 0)
2026 (minus:SI (match_dup 2) (match_dup 1))))]
2027 "TARGET_POWER"
2028 "@
2029 doz%I2. %0,%1,%2
2030 #"
2031 [(set_attr "type" "delayed_compare")
2032 (set_attr "length" "4,8")])
2034 (define_split
2035 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2036 (compare:CC
2037 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2038 (match_operand:SI 2 "reg_or_short_operand" ""))
2039 (const_int 0)
2040 (minus:SI (match_dup 2) (match_dup 1)))
2041 (const_int 0)))
2042 (set (match_operand:SI 0 "gpc_reg_operand" "")
2043 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2044 (const_int 0)
2045 (minus:SI (match_dup 2) (match_dup 1))))]
2046 "TARGET_POWER && reload_completed"
2047 [(set (match_dup 0)
2048 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2049 (const_int 0)
2050 (minus:SI (match_dup 2) (match_dup 1))))
2051 (set (match_dup 3)
2052 (compare:CC (match_dup 0)
2053 (const_int 0)))]
2054 "")
2056 ;; We don't need abs with condition code because such comparisons should
2057 ;; never be done.
2058 (define_expand "abssi2"
2059 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2060 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2061 ""
2062 "
2063 {
2064 if (TARGET_ISEL)
2065 {
2066 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2067 DONE;
2068 }
2069 else if (! TARGET_POWER)
2070 {
2071 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2072 DONE;
2073 }
2074 }")
2076 (define_insn "*abssi2_power"
2077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2078 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2079 "TARGET_POWER"
2080 "abs %0,%1")
2082 (define_insn_and_split "abs<mode>2_isel"
2083 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2084 (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
2085 (clobber (match_scratch:GPR 2 "=&b"))
2086 (clobber (match_scratch:CC 3 "=y"))]
2087 "TARGET_ISEL"
2088 "#"
2089 "&& reload_completed"
2090 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2091 (set (match_dup 3)
2092 (compare:CC (match_dup 1)
2093 (const_int 0)))
2094 (set (match_dup 0)
2095 (if_then_else:GPR (ge (match_dup 3)
2096 (const_int 0))
2097 (match_dup 1)
2098 (match_dup 2)))]
2099 "")
2101 (define_insn_and_split "nabs<mode>2_isel"
2102 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2103 (neg:GPR (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b"))))
2104 (clobber (match_scratch:GPR 2 "=&b"))
2105 (clobber (match_scratch:CC 3 "=y"))]
2106 "TARGET_ISEL"
2107 "#"
2108 "&& reload_completed"
2109 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2110 (set (match_dup 3)
2111 (compare:CC (match_dup 1)
2112 (const_int 0)))
2113 (set (match_dup 0)
2114 (if_then_else:GPR (ge (match_dup 3)
2115 (const_int 0))
2116 (match_dup 2)
2117 (match_dup 1)))]
2118 "")
2120 (define_insn_and_split "abssi2_nopower"
2121 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2122 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2123 (clobber (match_scratch:SI 2 "=&r,&r"))]
2124 "! TARGET_POWER && ! TARGET_ISEL"
2125 "#"
2126 "&& reload_completed"
2127 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2128 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2129 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2130 "")
2132 (define_insn "*nabs_power"
2133 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2134 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2135 "TARGET_POWER"
2136 "nabs %0,%1")
2138 (define_insn_and_split "*nabs_nopower"
2139 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2140 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2141 (clobber (match_scratch:SI 2 "=&r,&r"))]
2142 "! TARGET_POWER"
2143 "#"
2144 "&& reload_completed"
2145 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2146 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2147 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2148 "")
2150 (define_expand "neg<mode>2"
2151 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2152 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2153 ""
2154 "")
2156 (define_insn "*neg<mode>2_internal"
2157 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2158 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2159 ""
2160 "neg %0,%1")
2162 (define_insn ""
2163 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2164 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2165 (const_int 0)))
2166 (clobber (match_scratch:P 2 "=r,r"))]
2167 ""
2168 "@
2169 neg. %2,%1
2170 #"
2171 [(set_attr "type" "fast_compare")
2172 (set_attr "length" "4,8")])
2174 (define_split
2175 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2176 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2177 (const_int 0)))
2178 (clobber (match_scratch:P 2 ""))]
2179 "reload_completed"
2180 [(set (match_dup 2)
2181 (neg:P (match_dup 1)))
2182 (set (match_dup 0)
2183 (compare:CC (match_dup 2)
2184 (const_int 0)))]
2185 "")
2187 (define_insn ""
2188 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2189 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2190 (const_int 0)))
2191 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2192 (neg:P (match_dup 1)))]
2193 ""
2194 "@
2195 neg. %0,%1
2196 #"
2197 [(set_attr "type" "fast_compare")
2198 (set_attr "length" "4,8")])
2200 (define_split
2201 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2202 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2203 (const_int 0)))
2204 (set (match_operand:P 0 "gpc_reg_operand" "")
2205 (neg:P (match_dup 1)))]
2206 "reload_completed"
2207 [(set (match_dup 0)
2208 (neg:P (match_dup 1)))
2209 (set (match_dup 2)
2210 (compare:CC (match_dup 0)
2211 (const_int 0)))]
2212 "")
2214 (define_insn "clz<mode>2"
2215 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2216 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2217 ""
2218 "{cntlz|cntlz<wd>} %0,%1"
2219 [(set_attr "type" "cntlz")])
2221 (define_expand "ctz<mode>2"
2222 [(set (match_dup 2)
2223 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2224 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2225 (match_dup 2)))
2226 (clobber (scratch:CC))])
2227 (set (match_dup 4) (clz:GPR (match_dup 3)))
2228 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2229 (minus:GPR (match_dup 5) (match_dup 4)))]
2230 ""
2231 {
2232 operands[2] = gen_reg_rtx (<MODE>mode);
2233 operands[3] = gen_reg_rtx (<MODE>mode);
2234 operands[4] = gen_reg_rtx (<MODE>mode);
2235 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2236 })
2238 (define_expand "ffs<mode>2"
2239 [(set (match_dup 2)
2240 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2241 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2242 (match_dup 2)))
2243 (clobber (scratch:CC))])
2244 (set (match_dup 4) (clz:GPR (match_dup 3)))
2245 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2246 (minus:GPR (match_dup 5) (match_dup 4)))]
2247 ""
2248 {
2249 operands[2] = gen_reg_rtx (<MODE>mode);
2250 operands[3] = gen_reg_rtx (<MODE>mode);
2251 operands[4] = gen_reg_rtx (<MODE>mode);
2252 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2253 })
2255 (define_insn "popcntb<mode>2"
2256 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2257 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2258 UNSPEC_POPCNTB))]
2259 "TARGET_POPCNTB"
2260 "popcntb %0,%1")
2262 (define_insn "popcntwsi2"
2263 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2264 (popcount:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2265 "TARGET_POPCNTD"
2266 "popcntw %0,%1")
2268 (define_insn "popcntddi2"
2269 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2270 (popcount:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
2271 "TARGET_POPCNTD && TARGET_POWERPC64"
2272 "popcntd %0,%1")
2274 (define_expand "popcount<mode>2"
2275 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2276 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2277 "TARGET_POPCNTB || TARGET_POPCNTD"
2278 {
2279 rs6000_emit_popcount (operands[0], operands[1]);
2280 DONE;
2281 })
2283 (define_expand "parity<mode>2"
2284 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2285 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2286 "TARGET_POPCNTB"
2287 {
2288 rs6000_emit_parity (operands[0], operands[1]);
2289 DONE;
2290 })
2292 ;; Since the hardware zeros the upper part of the register, save generating the
2293 ;; AND immediate if we are converting to unsigned
2294 (define_insn "*bswaphi2_extenddi"
2295 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2296 (zero_extend:DI
2297 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2298 "TARGET_POWERPC64"
2299 "lhbrx %0,%y1"
2300 [(set_attr "length" "4")
2301 (set_attr "type" "load")])
2303 (define_insn "*bswaphi2_extendsi"
2304 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2305 (zero_extend:SI
2306 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2307 "TARGET_POWERPC"
2308 "lhbrx %0,%y1"
2309 [(set_attr "length" "4")
2310 (set_attr "type" "load")])
2312 (define_expand "bswaphi2"
2313 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2314 (bswap:HI
2315 (match_operand:HI 1 "reg_or_mem_operand" "")))
2316 (clobber (match_scratch:SI 2 ""))])]
2317 ""
2318 {
2319 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2320 operands[1] = force_reg (HImode, operands[1]);
2321 })
2323 (define_insn "bswaphi2_internal"
2324 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2325 (bswap:HI
2326 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2327 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2328 "TARGET_POWERPC"
2329 "@
2330 lhbrx %0,%y1
2331 sthbrx %1,%y0
2332 #"
2333 [(set_attr "length" "4,4,12")
2334 (set_attr "type" "load,store,*")])
2336 (define_split
2337 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2338 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2339 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2340 "TARGET_POWERPC && reload_completed"
2341 [(set (match_dup 3)
2342 (zero_extract:SI (match_dup 4)
2343 (const_int 8)
2344 (const_int 16)))
2345 (set (match_dup 2)
2346 (and:SI (ashift:SI (match_dup 4)
2347 (const_int 8))
2348 (const_int 65280))) ;; 0xff00
2349 (set (match_dup 3)
2350 (ior:SI (match_dup 3)
2351 (match_dup 2)))]
2352 "
2353 {
2354 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2355 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2356 }")
2358 (define_insn "*bswapsi2_extenddi"
2359 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2360 (zero_extend:DI
2361 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2362 "TARGET_POWERPC64"
2363 "lwbrx %0,%y1"
2364 [(set_attr "length" "4")
2365 (set_attr "type" "load")])
2367 (define_expand "bswapsi2"
2368 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2369 (bswap:SI
2370 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2371 ""
2372 {
2373 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2374 operands[1] = force_reg (SImode, operands[1]);
2375 })
2377 (define_insn "*bswapsi2_internal"
2378 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2379 (bswap:SI
2380 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2381 ""
2382 "@
2383 {lbrx|lwbrx} %0,%y1
2384 {stbrx|stwbrx} %1,%y0
2385 #"
2386 [(set_attr "length" "4,4,12")
2387 (set_attr "type" "load,store,*")])
2389 (define_split
2390 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2391 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2392 "reload_completed"
2393 [(set (match_dup 0)
2394 (rotate:SI (match_dup 1) (const_int 8)))
2395 (set (zero_extract:SI (match_dup 0)
2396 (const_int 8)
2397 (const_int 0))
2398 (match_dup 1))
2399 (set (zero_extract:SI (match_dup 0)
2400 (const_int 8)
2401 (const_int 16))
2402 (rotate:SI (match_dup 1)
2403 (const_int 16)))]
2404 "")
2406 (define_expand "bswapdi2"
2407 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2408 (bswap:DI
2409 (match_operand:DI 1 "reg_or_mem_operand" "")))
2410 (clobber (match_scratch:DI 2 ""))
2411 (clobber (match_scratch:DI 3 ""))
2412 (clobber (match_scratch:DI 4 ""))])]
2413 ""
2414 {
2415 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2416 operands[1] = force_reg (DImode, operands[1]);
2418 if (!TARGET_POWERPC64)
2419 {
2420 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2421 that uses 64-bit registers needs the same scratch registers as 64-bit
2422 mode. */
2423 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2424 DONE;
2425 }
2426 })
2428 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2429 (define_insn "*bswapdi2_ldbrx"
2430 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2431 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2432 (clobber (match_scratch:DI 2 "=X,X,&r"))
2433 (clobber (match_scratch:DI 3 "=X,X,&r"))
2434 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2435 "TARGET_POWERPC64 && TARGET_LDBRX
2436 && (REG_P (operands[0]) || REG_P (operands[1]))"
2437 "@
2438 ldbrx %0,%y1
2439 stdbrx %1,%y0
2440 #"
2441 [(set_attr "length" "4,4,36")
2442 (set_attr "type" "load,store,*")])
2444 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2445 (define_insn "*bswapdi2_64bit"
2446 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2447 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2448 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2449 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2450 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2451 "TARGET_POWERPC64 && !TARGET_LDBRX
2452 && (REG_P (operands[0]) || REG_P (operands[1]))"
2453 "#"
2454 [(set_attr "length" "16,12,36")])
2456 (define_split
2457 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2458 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2459 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2460 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2461 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2462 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2463 [(const_int 0)]
2464 "
2465 {
2466 rtx dest = operands[0];
2467 rtx src = operands[1];
2468 rtx op2 = operands[2];
2469 rtx op3 = operands[3];
2470 rtx op4 = operands[4];
2471 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2472 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2473 rtx addr1;
2474 rtx addr2;
2475 rtx word_high;
2476 rtx word_low;
2478 addr1 = XEXP (src, 0);
2479 if (GET_CODE (addr1) == PLUS)
2480 {
2481 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2482 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2483 }
2484 else
2485 {
2486 emit_move_insn (op2, GEN_INT (4));
2487 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2488 }
2490 if (BYTES_BIG_ENDIAN)
2491 {
2492 word_high = change_address (src, SImode, addr1);
2493 word_low = change_address (src, SImode, addr2);
2494 }
2495 else
2496 {
2497 word_high = change_address (src, SImode, addr2);
2498 word_low = change_address (src, SImode, addr1);
2499 }
2501 emit_insn (gen_bswapsi2 (op3_32, word_low));
2502 emit_insn (gen_bswapsi2 (op4_32, word_high));
2503 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2504 emit_insn (gen_iordi3 (dest, dest, op4));
2505 }")
2507 (define_split
2508 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2509 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2510 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2511 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2512 (clobber (match_operand:DI 4 "" ""))]
2513 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2514 [(const_int 0)]
2515 "
2516 {
2517 rtx dest = operands[0];
2518 rtx src = operands[1];
2519 rtx op2 = operands[2];
2520 rtx op3 = operands[3];
2521 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2522 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2523 rtx addr1;
2524 rtx addr2;
2525 rtx word_high;
2526 rtx word_low;
2528 addr1 = XEXP (dest, 0);
2529 if (GET_CODE (addr1) == PLUS)
2530 {
2531 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2532 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2533 }
2534 else
2535 {
2536 emit_move_insn (op2, GEN_INT (4));
2537 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2538 }
2540 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2541 if (BYTES_BIG_ENDIAN)
2542 {
2543 word_high = change_address (dest, SImode, addr1);
2544 word_low = change_address (dest, SImode, addr2);
2545 emit_insn (gen_bswapsi2 (word_high, src_si));
2546 emit_insn (gen_bswapsi2 (word_low, op3_si));
2547 }
2548 else
2549 {
2550 word_high = change_address (dest, SImode, addr2);
2551 word_low = change_address (dest, SImode, addr1);
2552 emit_insn (gen_bswapsi2 (word_low, src_si));
2553 emit_insn (gen_bswapsi2 (word_high, op3_si));
2554 }
2555 }")
2557 (define_split
2558 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2559 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2560 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2561 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2562 (clobber (match_operand:DI 4 "" ""))]
2563 "TARGET_POWERPC64 && reload_completed"
2564 [(const_int 0)]
2565 "
2566 {
2567 rtx dest = operands[0];
2568 rtx src = operands[1];
2569 rtx op2 = operands[2];
2570 rtx op3 = operands[3];
2571 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2572 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2573 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2574 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2576 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2577 emit_insn (gen_bswapsi2 (dest_si, src_si));
2578 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2579 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2580 emit_insn (gen_iordi3 (dest, dest, op3));
2581 }")
2583 (define_insn "bswapdi2_32bit"
2584 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2585 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2586 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2587 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2588 "#"
2589 [(set_attr "length" "16,12,36")])
2591 (define_split
2592 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2593 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2594 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2595 "!TARGET_POWERPC64 && reload_completed"
2596 [(const_int 0)]
2597 "
2598 {
2599 rtx dest = operands[0];
2600 rtx src = operands[1];
2601 rtx op2 = operands[2];
2602 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2603 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2604 rtx addr1;
2605 rtx addr2;
2606 rtx word_high;
2607 rtx word_low;
2609 addr1 = XEXP (src, 0);
2610 if (GET_CODE (addr1) == PLUS)
2611 {
2612 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2613 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2614 }
2615 else
2616 {
2617 emit_move_insn (op2, GEN_INT (4));
2618 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2619 }
2621 if (BYTES_BIG_ENDIAN)
2622 {
2623 word_high = change_address (src, SImode, addr1);
2624 word_low = change_address (src, SImode, addr2);
2625 }
2626 else
2627 {
2628 word_high = change_address (src, SImode, addr2);
2629 word_low = change_address (src, SImode, addr1);
2630 }
2632 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2633 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2634 }")
2636 (define_split
2637 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2638 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2639 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2640 "!TARGET_POWERPC64 && reload_completed"
2641 [(const_int 0)]
2642 "
2643 {
2644 rtx dest = operands[0];
2645 rtx src = operands[1];
2646 rtx op2 = operands[2];
2647 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2648 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2649 rtx addr1;
2650 rtx addr2;
2651 rtx word_high;
2652 rtx word_low;
2654 addr1 = XEXP (dest, 0);
2655 if (GET_CODE (addr1) == PLUS)
2656 {
2657 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2658 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2659 }
2660 else
2661 {
2662 emit_move_insn (op2, GEN_INT (4));
2663 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2664 }
2666 if (BYTES_BIG_ENDIAN)
2667 {
2668 word_high = change_address (dest, SImode, addr1);
2669 word_low = change_address (dest, SImode, addr2);
2670 }
2671 else
2672 {
2673 word_high = change_address (dest, SImode, addr2);
2674 word_low = change_address (dest, SImode, addr1);
2675 }
2677 emit_insn (gen_bswapsi2 (word_high, src_low));
2678 emit_insn (gen_bswapsi2 (word_low, src_high));
2679 }")
2681 (define_split
2682 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2683 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2684 (clobber (match_operand:SI 2 "" ""))]
2685 "!TARGET_POWERPC64 && reload_completed"
2686 [(const_int 0)]
2687 "
2688 {
2689 rtx dest = operands[0];
2690 rtx src = operands[1];
2691 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2692 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2693 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2694 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2696 emit_insn (gen_bswapsi2 (dest_high, src_low));
2697 emit_insn (gen_bswapsi2 (dest_low, src_high));
2698 }")
2700 (define_expand "mulsi3"
2701 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2702 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2703 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2704 ""
2705 "
2706 {
2707 if (TARGET_POWER)
2708 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2709 else
2710 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2711 DONE;
2712 }")
2714 (define_insn "mulsi3_mq"
2715 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2716 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2717 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2718 (clobber (match_scratch:SI 3 "=q,q"))]
2719 "TARGET_POWER"
2720 "@
2721 {muls|mullw} %0,%1,%2
2722 {muli|mulli} %0,%1,%2"
2723 [(set (attr "type")
2724 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2725 (const_string "imul3")
2726 (match_operand:SI 2 "short_cint_operand" "")
2727 (const_string "imul2")]
2728 (const_string "imul")))])
2730 (define_insn "mulsi3_no_mq"
2731 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2732 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2733 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2734 "! TARGET_POWER"
2735 "@
2736 {muls|mullw} %0,%1,%2
2737 {muli|mulli} %0,%1,%2"
2738 [(set (attr "type")
2739 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2740 (const_string "imul3")
2741 (match_operand:SI 2 "short_cint_operand" "")
2742 (const_string "imul2")]
2743 (const_string "imul")))])
2745 (define_insn "*mulsi3_mq_internal1"
2746 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2747 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2748 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2749 (const_int 0)))
2750 (clobber (match_scratch:SI 3 "=r,r"))
2751 (clobber (match_scratch:SI 4 "=q,q"))]
2752 "TARGET_POWER"
2753 "@
2754 {muls.|mullw.} %3,%1,%2
2755 #"
2756 [(set_attr "type" "imul_compare")
2757 (set_attr "length" "4,8")])
2759 (define_split
2760 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2761 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2762 (match_operand:SI 2 "gpc_reg_operand" ""))
2763 (const_int 0)))
2764 (clobber (match_scratch:SI 3 ""))
2765 (clobber (match_scratch:SI 4 ""))]
2766 "TARGET_POWER && reload_completed"
2767 [(parallel [(set (match_dup 3)
2768 (mult:SI (match_dup 1) (match_dup 2)))
2769 (clobber (match_dup 4))])
2770 (set (match_dup 0)
2771 (compare:CC (match_dup 3)
2772 (const_int 0)))]
2773 "")
2775 (define_insn "*mulsi3_no_mq_internal1"
2776 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2777 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2778 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2779 (const_int 0)))
2780 (clobber (match_scratch:SI 3 "=r,r"))]
2781 "! TARGET_POWER"
2782 "@
2783 {muls.|mullw.} %3,%1,%2
2784 #"
2785 [(set_attr "type" "imul_compare")
2786 (set_attr "length" "4,8")])
2788 (define_split
2789 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2790 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2791 (match_operand:SI 2 "gpc_reg_operand" ""))
2792 (const_int 0)))
2793 (clobber (match_scratch:SI 3 ""))]
2794 "! TARGET_POWER && reload_completed"
2795 [(set (match_dup 3)
2796 (mult:SI (match_dup 1) (match_dup 2)))
2797 (set (match_dup 0)
2798 (compare:CC (match_dup 3)
2799 (const_int 0)))]
2800 "")
2802 (define_insn "*mulsi3_mq_internal2"
2803 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2804 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2805 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2806 (const_int 0)))
2807 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2808 (mult:SI (match_dup 1) (match_dup 2)))
2809 (clobber (match_scratch:SI 4 "=q,q"))]
2810 "TARGET_POWER"
2811 "@
2812 {muls.|mullw.} %0,%1,%2
2813 #"
2814 [(set_attr "type" "imul_compare")
2815 (set_attr "length" "4,8")])
2817 (define_split
2818 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2819 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2820 (match_operand:SI 2 "gpc_reg_operand" ""))
2821 (const_int 0)))
2822 (set (match_operand:SI 0 "gpc_reg_operand" "")
2823 (mult:SI (match_dup 1) (match_dup 2)))
2824 (clobber (match_scratch:SI 4 ""))]
2825 "TARGET_POWER && reload_completed"
2826 [(parallel [(set (match_dup 0)
2827 (mult:SI (match_dup 1) (match_dup 2)))
2828 (clobber (match_dup 4))])
2829 (set (match_dup 3)
2830 (compare:CC (match_dup 0)
2831 (const_int 0)))]
2832 "")
2834 (define_insn "*mulsi3_no_mq_internal2"
2835 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2836 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2837 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2838 (const_int 0)))
2839 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2840 (mult:SI (match_dup 1) (match_dup 2)))]
2841 "! TARGET_POWER"
2842 "@
2843 {muls.|mullw.} %0,%1,%2
2844 #"
2845 [(set_attr "type" "imul_compare")
2846 (set_attr "length" "4,8")])
2848 (define_split
2849 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2850 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2851 (match_operand:SI 2 "gpc_reg_operand" ""))
2852 (const_int 0)))
2853 (set (match_operand:SI 0 "gpc_reg_operand" "")
2854 (mult:SI (match_dup 1) (match_dup 2)))]
2855 "! TARGET_POWER && reload_completed"
2856 [(set (match_dup 0)
2857 (mult:SI (match_dup 1) (match_dup 2)))
2858 (set (match_dup 3)
2859 (compare:CC (match_dup 0)
2860 (const_int 0)))]
2861 "")
2863 ;; Operand 1 is divided by operand 2; quotient goes to operand
2864 ;; 0 and remainder to operand 3.
2865 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2867 (define_expand "divmodsi4"
2868 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2869 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2870 (match_operand:SI 2 "gpc_reg_operand" "")))
2871 (set (match_operand:SI 3 "register_operand" "")
2872 (mod:SI (match_dup 1) (match_dup 2)))])]
2873 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2874 "
2875 {
2876 if (! TARGET_POWER && ! TARGET_POWERPC)
2877 {
2878 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2879 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2880 emit_insn (gen_divss_call ());
2881 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2882 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2883 DONE;
2884 }
2885 }")
2887 (define_insn "*divmodsi4_internal"
2888 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2889 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2890 (match_operand:SI 2 "gpc_reg_operand" "r")))
2891 (set (match_operand:SI 3 "register_operand" "=q")
2892 (mod:SI (match_dup 1) (match_dup 2)))]
2893 "TARGET_POWER"
2894 "divs %0,%1,%2"
2895 [(set_attr "type" "idiv")])
2897 (define_expand "udiv<mode>3"
2898 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2899 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2900 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2901 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2902 "
2903 {
2904 if (! TARGET_POWER && ! TARGET_POWERPC)
2905 {
2906 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2907 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2908 emit_insn (gen_quous_call ());
2909 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2910 DONE;
2911 }
2912 else if (TARGET_POWER)
2913 {
2914 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2915 DONE;
2916 }
2917 }")
2919 (define_insn "udivsi3_mq"
2920 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2921 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2922 (match_operand:SI 2 "gpc_reg_operand" "r")))
2923 (clobber (match_scratch:SI 3 "=q"))]
2924 "TARGET_POWERPC && TARGET_POWER"
2925 "divwu %0,%1,%2"
2926 [(set_attr "type" "idiv")])
2928 (define_insn "*udivsi3_no_mq"
2929 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2930 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2931 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2932 "TARGET_POWERPC && ! TARGET_POWER"
2933 "div<wd>u %0,%1,%2"
2934 [(set (attr "type")
2935 (cond [(match_operand:SI 0 "" "")
2936 (const_string "idiv")]
2937 (const_string "ldiv")))])
2940 ;; For powers of two we can do srai/aze for divide and then adjust for
2941 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2942 ;; used; for PowerPC, force operands into register and do a normal divide;
2943 ;; for AIX common-mode, use quoss call on register operands.
2944 (define_expand "div<mode>3"
2945 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2946 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2947 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2948 ""
2949 "
2950 {
2951 if (GET_CODE (operands[2]) == CONST_INT
2952 && INTVAL (operands[2]) > 0
2953 && exact_log2 (INTVAL (operands[2])) >= 0)
2954 ;
2955 else if (TARGET_POWERPC)
2956 {
2957 operands[2] = force_reg (<MODE>mode, operands[2]);
2958 if (TARGET_POWER)
2959 {
2960 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2961 DONE;
2962 }
2963 }
2964 else if (TARGET_POWER)
2965 FAIL;
2966 else
2967 {
2968 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2969 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2970 emit_insn (gen_quoss_call ());
2971 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2972 DONE;
2973 }
2974 }")
2976 (define_insn "divsi3_mq"
2977 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2978 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2979 (match_operand:SI 2 "gpc_reg_operand" "r")))
2980 (clobber (match_scratch:SI 3 "=q"))]
2981 "TARGET_POWERPC && TARGET_POWER"
2982 "divw %0,%1,%2"
2983 [(set_attr "type" "idiv")])
2985 (define_insn "*div<mode>3_no_mq"
2986 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2987 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2988 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2989 "TARGET_POWERPC && ! TARGET_POWER"
2990 "div<wd> %0,%1,%2"
2991 [(set (attr "type")
2992 (cond [(match_operand:SI 0 "" "")
2993 (const_string "idiv")]
2994 (const_string "ldiv")))])
2996 (define_expand "mod<mode>3"
2997 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2998 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2999 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
3000 ""
3001 "
3002 {
3003 int i;
3004 rtx temp1;
3005 rtx temp2;
3007 if (GET_CODE (operands[2]) != CONST_INT
3008 || INTVAL (operands[2]) <= 0
3009 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
3010 FAIL;
3012 temp1 = gen_reg_rtx (<MODE>mode);
3013 temp2 = gen_reg_rtx (<MODE>mode);
3015 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
3016 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
3017 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
3018 DONE;
3019 }")
3021 (define_insn ""
3022 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3023 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3024 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
3025 ""
3026 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
3027 [(set_attr "type" "two")
3028 (set_attr "length" "8")])
3030 (define_insn ""
3031 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3032 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3033 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3034 (const_int 0)))
3035 (clobber (match_scratch:P 3 "=r,r"))]
3036 ""
3037 "@
3038 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
3039 #"
3040 [(set_attr "type" "compare")
3041 (set_attr "length" "8,12")
3042 (set_attr "cell_micro" "not")])
3044 (define_split
3045 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3046 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3047 (match_operand:GPR 2 "exact_log2_cint_operand"
3048 ""))
3049 (const_int 0)))
3050 (clobber (match_scratch:GPR 3 ""))]
3051 "reload_completed"
3052 [(set (match_dup 3)
3053 (div:<MODE> (match_dup 1) (match_dup 2)))
3054 (set (match_dup 0)
3055 (compare:CC (match_dup 3)
3056 (const_int 0)))]
3057 "")
3059 (define_insn ""
3060 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3061 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3062 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3063 (const_int 0)))
3064 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
3065 (div:P (match_dup 1) (match_dup 2)))]
3066 ""
3067 "@
3068 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
3069 #"
3070 [(set_attr "type" "compare")
3071 (set_attr "length" "8,12")
3072 (set_attr "cell_micro" "not")])
3074 (define_split
3075 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3076 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3077 (match_operand:GPR 2 "exact_log2_cint_operand"
3078 ""))
3079 (const_int 0)))
3080 (set (match_operand:GPR 0 "gpc_reg_operand" "")
3081 (div:GPR (match_dup 1) (match_dup 2)))]
3082 "reload_completed"
3083 [(set (match_dup 0)
3084 (div:<MODE> (match_dup 1) (match_dup 2)))
3085 (set (match_dup 3)
3086 (compare:CC (match_dup 0)
3087 (const_int 0)))]
3088 "")
3090 (define_insn ""
3091 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3092 (udiv:SI
3093 (plus:DI (ashift:DI
3094 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3095 (const_int 32))
3096 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
3097 (match_operand:SI 3 "gpc_reg_operand" "r")))
3098 (set (match_operand:SI 2 "register_operand" "=*q")
3099 (umod:SI
3100 (plus:DI (ashift:DI
3101 (zero_extend:DI (match_dup 1)) (const_int 32))
3102 (zero_extend:DI (match_dup 4)))
3103 (match_dup 3)))]
3104 "TARGET_POWER"
3105 "div %0,%1,%3"
3106 [(set_attr "type" "idiv")])
3108 ;; To do unsigned divide we handle the cases of the divisor looking like a
3109 ;; negative number. If it is a constant that is less than 2**31, we don't
3110 ;; have to worry about the branches. So make a few subroutines here.
3111 ;;
3112 ;; First comes the normal case.
3113 (define_expand "udivmodsi4_normal"
3114 [(set (match_dup 4) (const_int 0))
3115 (parallel [(set (match_operand:SI 0 "" "")
3116 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3117 (const_int 32))
3118 (zero_extend:DI (match_operand:SI 1 "" "")))
3119 (match_operand:SI 2 "" "")))
3120 (set (match_operand:SI 3 "" "")
3121 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3122 (const_int 32))
3123 (zero_extend:DI (match_dup 1)))
3124 (match_dup 2)))])]
3125 "TARGET_POWER"
3126 "
3127 { operands[4] = gen_reg_rtx (SImode); }")
3129 ;; This handles the branches.
3130 (define_expand "udivmodsi4_tests"
3131 [(set (match_operand:SI 0 "" "") (const_int 0))
3132 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
3133 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
3134 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
3135 (label_ref (match_operand:SI 4 "" "")) (pc)))
3136 (set (match_dup 0) (const_int 1))
3137 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
3138 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
3139 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
3140 (label_ref (match_dup 4)) (pc)))]
3141 "TARGET_POWER"
3142 "
3143 { operands[5] = gen_reg_rtx (CCUNSmode);
3144 operands[6] = gen_reg_rtx (CCmode);
3145 }")
3147 (define_expand "udivmodsi4"
3148 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3149 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
3150 (match_operand:SI 2 "reg_or_cint_operand" "")))
3151 (set (match_operand:SI 3 "gpc_reg_operand" "")
3152 (umod:SI (match_dup 1) (match_dup 2)))])]
3153 ""
3154 "
3155 {
3156 rtx label = 0;
3158 if (! TARGET_POWER)
3159 {
3160 if (! TARGET_POWERPC)
3161 {
3162 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3163 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3164 emit_insn (gen_divus_call ());
3165 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3166 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3167 DONE;
3168 }
3169 else
3170 FAIL;
3171 }
3173 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
3174 {
3175 operands[2] = force_reg (SImode, operands[2]);
3176 label = gen_label_rtx ();
3177 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
3178 operands[3], label));
3179 }
3180 else
3181 operands[2] = force_reg (SImode, operands[2]);
3183 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
3184 operands[3]));
3185 if (label)
3186 emit_label (label);
3188 DONE;
3189 }")
3191 ;; AIX architecture-independent common-mode multiply (DImode),
3192 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
3193 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
3194 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
3195 ;; assumed unused if generating common-mode, so ignore.
3196 (define_insn "mulh_call"
3197 [(set (reg:SI 3)
3198 (truncate:SI
3199 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
3200 (sign_extend:DI (reg:SI 4)))
3201 (const_int 32))))
3202 (clobber (reg:SI LR_REGNO))]
3203 "! TARGET_POWER && ! TARGET_POWERPC"
3204 "bla __mulh"
3205 [(set_attr "type" "imul")])
3207 (define_insn "mull_call"
3208 [(set (reg:DI 3)
3209 (mult:DI (sign_extend:DI (reg:SI 3))
3210 (sign_extend:DI (reg:SI 4))))
3211 (clobber (reg:SI LR_REGNO))
3212 (clobber (reg:SI 0))]
3213 "! TARGET_POWER && ! TARGET_POWERPC"
3214 "bla __mull"
3215 [(set_attr "type" "imul")])
3217 (define_insn "divss_call"
3218 [(set (reg:SI 3)
3219 (div:SI (reg:SI 3) (reg:SI 4)))
3220 (set (reg:SI 4)
3221 (mod:SI (reg:SI 3) (reg:SI 4)))
3222 (clobber (reg:SI LR_REGNO))
3223 (clobber (reg:SI 0))]
3224 "! TARGET_POWER && ! TARGET_POWERPC"
3225 "bla __divss"
3226 [(set_attr "type" "idiv")])
3228 (define_insn "divus_call"
3229 [(set (reg:SI 3)
3230 (udiv:SI (reg:SI 3) (reg:SI 4)))
3231 (set (reg:SI 4)
3232 (umod:SI (reg:SI 3) (reg:SI 4)))
3233 (clobber (reg:SI LR_REGNO))
3234 (clobber (reg:SI 0))
3235 (clobber (match_scratch:CC 0 "=x"))
3236 (clobber (reg:CC CR1_REGNO))]
3237 "! TARGET_POWER && ! TARGET_POWERPC"
3238 "bla __divus"
3239 [(set_attr "type" "idiv")])
3241 (define_insn "quoss_call"
3242 [(set (reg:SI 3)
3243 (div:SI (reg:SI 3) (reg:SI 4)))
3244 (clobber (reg:SI LR_REGNO))]
3245 "! TARGET_POWER && ! TARGET_POWERPC"
3246 "bla __quoss"
3247 [(set_attr "type" "idiv")])
3249 (define_insn "quous_call"
3250 [(set (reg:SI 3)
3251 (udiv:SI (reg:SI 3) (reg:SI 4)))
3252 (clobber (reg:SI LR_REGNO))
3253 (clobber (reg:SI 0))
3254 (clobber (match_scratch:CC 0 "=x"))
3255 (clobber (reg:CC CR1_REGNO))]
3256 "! TARGET_POWER && ! TARGET_POWERPC"
3257 "bla __quous"
3258 [(set_attr "type" "idiv")])
3259 \f
3260 ;; Logical instructions
3261 ;; The logical instructions are mostly combined by using match_operator,
3262 ;; but the plain AND insns are somewhat different because there is no
3263 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3264 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3266 (define_expand "andsi3"
3267 [(parallel
3268 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3269 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3270 (match_operand:SI 2 "and_operand" "")))
3271 (clobber (match_scratch:CC 3 ""))])]
3272 ""
3273 "")
3275 (define_insn "andsi3_mc"
3276 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3277 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3278 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3279 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3280 "rs6000_gen_cell_microcode"
3281 "@
3282 and %0,%1,%2
3283 {rlinm|rlwinm} %0,%1,0,%m2,%M2
3284 {andil.|andi.} %0,%1,%b2
3285 {andiu.|andis.} %0,%1,%u2"
3286 [(set_attr "type" "*,*,fast_compare,fast_compare")])
3288 (define_insn "andsi3_nomc"
3289 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3290 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3291 (match_operand:SI 2 "and_operand" "?r,T")))
3292 (clobber (match_scratch:CC 3 "=X,X"))]
3293 "!rs6000_gen_cell_microcode"
3294 "@
3295 and %0,%1,%2
3296 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3298 (define_insn "andsi3_internal0_nomc"
3299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3300 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3301 (match_operand:SI 2 "and_operand" "?r,T")))]
3302 "!rs6000_gen_cell_microcode"
3303 "@
3304 and %0,%1,%2
3305 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3308 ;; Note to set cr's other than cr0 we do the and immediate and then
3309 ;; the test again -- this avoids a mfcr which on the higher end
3310 ;; machines causes an execution serialization
3312 (define_insn "*andsi3_internal2_mc"
3313 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3314 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3315 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3316 (const_int 0)))
3317 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3318 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3319 "TARGET_32BIT && rs6000_gen_cell_microcode"
3320 "@
3321 and. %3,%1,%2
3322 {andil.|andi.} %3,%1,%b2
3323 {andiu.|andis.} %3,%1,%u2
3324 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3325 #
3326 #
3327 #
3328 #"
3329 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3330 compare,compare,compare,compare")
3331 (set_attr "length" "4,4,4,4,8,8,8,8")])
3333 (define_insn "*andsi3_internal3_mc"
3334 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3335 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3336 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3337 (const_int 0)))
3338 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3339 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3340 "TARGET_64BIT && rs6000_gen_cell_microcode"
3341 "@
3342 #
3343 {andil.|andi.} %3,%1,%b2
3344 {andiu.|andis.} %3,%1,%u2
3345 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3346 #
3347 #
3348 #
3349 #"
3350 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3351 compare,compare,compare")
3352 (set_attr "length" "8,4,4,4,8,8,8,8")])
3354 (define_split
3355 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3356 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3357 (match_operand:GPR 2 "and_operand" ""))
3358 (const_int 0)))
3359 (clobber (match_scratch:GPR 3 ""))
3360 (clobber (match_scratch:CC 4 ""))]
3361 "reload_completed"
3362 [(parallel [(set (match_dup 3)
3363 (and:<MODE> (match_dup 1)
3364 (match_dup 2)))
3365 (clobber (match_dup 4))])
3366 (set (match_dup 0)
3367 (compare:CC (match_dup 3)
3368 (const_int 0)))]
3369 "")
3371 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3372 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3374 (define_split
3375 [(set (match_operand:CC 0 "cc_reg_operand" "")
3376 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3377 (match_operand:SI 2 "gpc_reg_operand" ""))
3378 (const_int 0)))
3379 (clobber (match_scratch:SI 3 ""))
3380 (clobber (match_scratch:CC 4 ""))]
3381 "TARGET_POWERPC64 && reload_completed"
3382 [(parallel [(set (match_dup 3)
3383 (and:SI (match_dup 1)
3384 (match_dup 2)))
3385 (clobber (match_dup 4))])
3386 (set (match_dup 0)
3387 (compare:CC (match_dup 3)
3388 (const_int 0)))]
3389 "")
3391 (define_insn "*andsi3_internal4"
3392 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3393 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3394 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3395 (const_int 0)))
3396 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3397 (and:SI (match_dup 1)
3398 (match_dup 2)))
3399 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3400 "TARGET_32BIT && rs6000_gen_cell_microcode"
3401 "@
3402 and. %0,%1,%2
3403 {andil.|andi.} %0,%1,%b2
3404 {andiu.|andis.} %0,%1,%u2
3405 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3406 #
3407 #
3408 #
3409 #"
3410 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3411 compare,compare,compare,compare")
3412 (set_attr "length" "4,4,4,4,8,8,8,8")])
3414 (define_insn "*andsi3_internal5_mc"
3415 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3416 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3417 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3418 (const_int 0)))
3419 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3420 (and:SI (match_dup 1)
3421 (match_dup 2)))
3422 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3423 "TARGET_64BIT && rs6000_gen_cell_microcode"
3424 "@
3425 #
3426 {andil.|andi.} %0,%1,%b2
3427 {andiu.|andis.} %0,%1,%u2
3428 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3429 #
3430 #
3431 #
3432 #"
3433 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3434 compare,compare,compare")
3435 (set_attr "length" "8,4,4,4,8,8,8,8")])
3437 (define_split
3438 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3439 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3440 (match_operand:SI 2 "and_operand" ""))
3441 (const_int 0)))
3442 (set (match_operand:SI 0 "gpc_reg_operand" "")
3443 (and:SI (match_dup 1)
3444 (match_dup 2)))
3445 (clobber (match_scratch:CC 4 ""))]
3446 "reload_completed"
3447 [(parallel [(set (match_dup 0)
3448 (and:SI (match_dup 1)
3449 (match_dup 2)))
3450 (clobber (match_dup 4))])
3451 (set (match_dup 3)
3452 (compare:CC (match_dup 0)
3453 (const_int 0)))]
3454 "")
3456 (define_split
3457 [(set (match_operand:CC 3 "cc_reg_operand" "")
3458 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3459 (match_operand:SI 2 "gpc_reg_operand" ""))
3460 (const_int 0)))
3461 (set (match_operand:SI 0 "gpc_reg_operand" "")
3462 (and:SI (match_dup 1)
3463 (match_dup 2)))
3464 (clobber (match_scratch:CC 4 ""))]
3465 "TARGET_POWERPC64 && reload_completed"
3466 [(parallel [(set (match_dup 0)
3467 (and:SI (match_dup 1)
3468 (match_dup 2)))
3469 (clobber (match_dup 4))])
3470 (set (match_dup 3)
3471 (compare:CC (match_dup 0)
3472 (const_int 0)))]
3473 "")
3475 ;; Handle the PowerPC64 rlwinm corner case
3477 (define_insn_and_split "*andsi3_internal6"
3478 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3479 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3480 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3481 "TARGET_POWERPC64"
3482 "#"
3483 "TARGET_POWERPC64"
3484 [(set (match_dup 0)
3485 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3486 (match_dup 4)))
3487 (set (match_dup 0)
3488 (rotate:SI (match_dup 0) (match_dup 5)))]
3489 "
3490 {
3491 int mb = extract_MB (operands[2]);
3492 int me = extract_ME (operands[2]);
3493 operands[3] = GEN_INT (me + 1);
3494 operands[5] = GEN_INT (32 - (me + 1));
3495 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3496 }"
3497 [(set_attr "length" "8")])
3499 (define_expand "iorsi3"
3500 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3501 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3502 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3503 ""
3504 "
3505 {
3506 if (GET_CODE (operands[2]) == CONST_INT
3507 && ! logical_operand (operands[2], SImode))
3508 {
3509 HOST_WIDE_INT value = INTVAL (operands[2]);
3510 rtx tmp = ((!can_create_pseudo_p ()
3511 || rtx_equal_p (operands[0], operands[1]))
3512 ? operands[0] : gen_reg_rtx (SImode));
3514 emit_insn (gen_iorsi3 (tmp, operands[1],
3515 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3516 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3517 DONE;
3518 }
3519 }")
3521 (define_expand "xorsi3"
3522 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3523 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3524 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3525 ""
3526 "
3527 {
3528 if (GET_CODE (operands[2]) == CONST_INT
3529 && ! logical_operand (operands[2], SImode))
3530 {
3531 HOST_WIDE_INT value = INTVAL (operands[2]);
3532 rtx tmp = ((!can_create_pseudo_p ()
3533 || rtx_equal_p (operands[0], operands[1]))
3534 ? operands[0] : gen_reg_rtx (SImode));
3536 emit_insn (gen_xorsi3 (tmp, operands[1],
3537 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3538 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3539 DONE;
3540 }
3541 }")
3543 (define_insn "*boolsi3_internal1"
3544 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3545 (match_operator:SI 3 "boolean_or_operator"
3546 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3547 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3548 ""
3549 "@
3550 %q3 %0,%1,%2
3551 {%q3il|%q3i} %0,%1,%b2
3552 {%q3iu|%q3is} %0,%1,%u2")
3554 (define_insn "*boolsi3_internal2"
3555 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3556 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3557 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3558 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3559 (const_int 0)))
3560 (clobber (match_scratch:SI 3 "=r,r"))]
3561 "TARGET_32BIT"
3562 "@
3563 %q4. %3,%1,%2
3564 #"
3565 [(set_attr "type" "fast_compare,compare")
3566 (set_attr "length" "4,8")])
3568 (define_split
3569 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3570 (compare:CC (match_operator:SI 4 "boolean_operator"
3571 [(match_operand:SI 1 "gpc_reg_operand" "")
3572 (match_operand:SI 2 "gpc_reg_operand" "")])
3573 (const_int 0)))
3574 (clobber (match_scratch:SI 3 ""))]
3575 "TARGET_32BIT && reload_completed"
3576 [(set (match_dup 3) (match_dup 4))
3577 (set (match_dup 0)
3578 (compare:CC (match_dup 3)
3579 (const_int 0)))]
3580 "")
3582 (define_insn "*boolsi3_internal3"
3583 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3584 (compare:CC (match_operator:SI 4 "boolean_operator"
3585 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3586 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3587 (const_int 0)))
3588 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3589 (match_dup 4))]
3590 "TARGET_32BIT"
3591 "@
3592 %q4. %0,%1,%2
3593 #"
3594 [(set_attr "type" "fast_compare,compare")
3595 (set_attr "length" "4,8")])
3597 (define_split
3598 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3599 (compare:CC (match_operator:SI 4 "boolean_operator"
3600 [(match_operand:SI 1 "gpc_reg_operand" "")
3601 (match_operand:SI 2 "gpc_reg_operand" "")])
3602 (const_int 0)))
3603 (set (match_operand:SI 0 "gpc_reg_operand" "")
3604 (match_dup 4))]
3605 "TARGET_32BIT && reload_completed"
3606 [(set (match_dup 0) (match_dup 4))
3607 (set (match_dup 3)
3608 (compare:CC (match_dup 0)
3609 (const_int 0)))]
3610 "")
3612 ;; Split a logical operation that we can't do in one insn into two insns,
3613 ;; each of which does one 16-bit part. This is used by combine.
3615 (define_split
3616 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3617 (match_operator:SI 3 "boolean_or_operator"
3618 [(match_operand:SI 1 "gpc_reg_operand" "")
3619 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3620 ""
3621 [(set (match_dup 0) (match_dup 4))
3622 (set (match_dup 0) (match_dup 5))]
3623 "
3624 {
3625 rtx i;
3626 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3627 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3628 operands[1], i);
3629 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3630 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3631 operands[0], i);
3632 }")
3634 (define_insn "*boolcsi3_internal1"
3635 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3636 (match_operator:SI 3 "boolean_operator"
3637 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3638 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3639 ""
3640 "%q3 %0,%2,%1")
3642 (define_insn "*boolcsi3_internal2"
3643 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3644 (compare:CC (match_operator:SI 4 "boolean_operator"
3645 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3646 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3647 (const_int 0)))
3648 (clobber (match_scratch:SI 3 "=r,r"))]
3649 "TARGET_32BIT"
3650 "@
3651 %q4. %3,%2,%1
3652 #"
3653 [(set_attr "type" "compare")
3654 (set_attr "length" "4,8")])
3656 (define_split
3657 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3658 (compare:CC (match_operator:SI 4 "boolean_operator"
3659 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3660 (match_operand:SI 2 "gpc_reg_operand" "")])
3661 (const_int 0)))
3662 (clobber (match_scratch:SI 3 ""))]
3663 "TARGET_32BIT && reload_completed"
3664 [(set (match_dup 3) (match_dup 4))
3665 (set (match_dup 0)
3666 (compare:CC (match_dup 3)
3667 (const_int 0)))]
3668 "")
3670 (define_insn "*boolcsi3_internal3"
3671 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3672 (compare:CC (match_operator:SI 4 "boolean_operator"
3673 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3674 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3675 (const_int 0)))
3676 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3677 (match_dup 4))]
3678 "TARGET_32BIT"
3679 "@
3680 %q4. %0,%2,%1
3681 #"
3682 [(set_attr "type" "compare")
3683 (set_attr "length" "4,8")])
3685 (define_split
3686 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3687 (compare:CC (match_operator:SI 4 "boolean_operator"
3688 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3689 (match_operand:SI 2 "gpc_reg_operand" "")])
3690 (const_int 0)))
3691 (set (match_operand:SI 0 "gpc_reg_operand" "")
3692 (match_dup 4))]
3693 "TARGET_32BIT && reload_completed"
3694 [(set (match_dup 0) (match_dup 4))
3695 (set (match_dup 3)
3696 (compare:CC (match_dup 0)
3697 (const_int 0)))]
3698 "")
3700 (define_insn "*boolccsi3_internal1"
3701 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3702 (match_operator:SI 3 "boolean_operator"
3703 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3704 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3705 ""
3706 "%q3 %0,%1,%2")
3708 (define_insn "*boolccsi3_internal2"
3709 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3710 (compare:CC (match_operator:SI 4 "boolean_operator"
3711 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3712 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3713 (const_int 0)))
3714 (clobber (match_scratch:SI 3 "=r,r"))]
3715 "TARGET_32BIT"
3716 "@
3717 %q4. %3,%1,%2
3718 #"
3719 [(set_attr "type" "fast_compare,compare")
3720 (set_attr "length" "4,8")])
3722 (define_split
3723 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3724 (compare:CC (match_operator:SI 4 "boolean_operator"
3725 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3726 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3727 (const_int 0)))
3728 (clobber (match_scratch:SI 3 ""))]
3729 "TARGET_32BIT && reload_completed"
3730 [(set (match_dup 3) (match_dup 4))
3731 (set (match_dup 0)
3732 (compare:CC (match_dup 3)
3733 (const_int 0)))]
3734 "")
3736 (define_insn "*boolccsi3_internal3"
3737 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3738 (compare:CC (match_operator:SI 4 "boolean_operator"
3739 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3740 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3741 (const_int 0)))
3742 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3743 (match_dup 4))]
3744 "TARGET_32BIT"
3745 "@
3746 %q4. %0,%1,%2
3747 #"
3748 [(set_attr "type" "fast_compare,compare")
3749 (set_attr "length" "4,8")])
3751 (define_split
3752 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3753 (compare:CC (match_operator:SI 4 "boolean_operator"
3754 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3755 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3756 (const_int 0)))
3757 (set (match_operand:SI 0 "gpc_reg_operand" "")
3758 (match_dup 4))]
3759 "TARGET_32BIT && reload_completed"
3760 [(set (match_dup 0) (match_dup 4))
3761 (set (match_dup 3)
3762 (compare:CC (match_dup 0)
3763 (const_int 0)))]
3764 "")
3766 ;; maskir insn. We need four forms because things might be in arbitrary
3767 ;; orders. Don't define forms that only set CR fields because these
3768 ;; would modify an input register.
3770 (define_insn "*maskir_internal1"
3771 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3772 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3773 (match_operand:SI 1 "gpc_reg_operand" "0"))
3774 (and:SI (match_dup 2)
3775 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3776 "TARGET_POWER"
3777 "maskir %0,%3,%2")
3779 (define_insn "*maskir_internal2"
3780 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3781 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3782 (match_operand:SI 1 "gpc_reg_operand" "0"))
3783 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3784 (match_dup 2))))]
3785 "TARGET_POWER"
3786 "maskir %0,%3,%2")
3788 (define_insn "*maskir_internal3"
3789 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3790 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3791 (match_operand:SI 3 "gpc_reg_operand" "r"))
3792 (and:SI (not:SI (match_dup 2))
3793 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3794 "TARGET_POWER"
3795 "maskir %0,%3,%2")
3797 (define_insn "*maskir_internal4"
3798 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3799 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3800 (match_operand:SI 2 "gpc_reg_operand" "r"))
3801 (and:SI (not:SI (match_dup 2))
3802 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3803 "TARGET_POWER"
3804 "maskir %0,%3,%2")
3806 (define_insn "*maskir_internal5"
3807 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3808 (compare:CC
3809 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3810 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3811 (and:SI (match_dup 2)
3812 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3813 (const_int 0)))
3814 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3815 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3816 (and:SI (match_dup 2) (match_dup 3))))]
3817 "TARGET_POWER"
3818 "@
3819 maskir. %0,%3,%2
3820 #"
3821 [(set_attr "type" "compare")
3822 (set_attr "length" "4,8")])
3824 (define_split
3825 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3826 (compare:CC
3827 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3828 (match_operand:SI 1 "gpc_reg_operand" ""))
3829 (and:SI (match_dup 2)
3830 (match_operand:SI 3 "gpc_reg_operand" "")))
3831 (const_int 0)))
3832 (set (match_operand:SI 0 "gpc_reg_operand" "")
3833 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3834 (and:SI (match_dup 2) (match_dup 3))))]
3835 "TARGET_POWER && reload_completed"
3836 [(set (match_dup 0)
3837 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3838 (and:SI (match_dup 2) (match_dup 3))))
3839 (set (match_dup 4)
3840 (compare:CC (match_dup 0)
3841 (const_int 0)))]
3842 "")
3844 (define_insn "*maskir_internal6"
3845 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3846 (compare:CC
3847 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3848 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3849 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3850 (match_dup 2)))
3851 (const_int 0)))
3852 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3853 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3854 (and:SI (match_dup 3) (match_dup 2))))]
3855 "TARGET_POWER"
3856 "@
3857 maskir. %0,%3,%2
3858 #"
3859 [(set_attr "type" "compare")
3860 (set_attr "length" "4,8")])
3862 (define_split
3863 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3864 (compare:CC
3865 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3866 (match_operand:SI 1 "gpc_reg_operand" ""))
3867 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3868 (match_dup 2)))
3869 (const_int 0)))
3870 (set (match_operand:SI 0 "gpc_reg_operand" "")
3871 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3872 (and:SI (match_dup 3) (match_dup 2))))]
3873 "TARGET_POWER && reload_completed"
3874 [(set (match_dup 0)
3875 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3876 (and:SI (match_dup 3) (match_dup 2))))
3877 (set (match_dup 4)
3878 (compare:CC (match_dup 0)
3879 (const_int 0)))]
3880 "")
3882 (define_insn "*maskir_internal7"
3883 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3884 (compare:CC
3885 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3886 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3887 (and:SI (not:SI (match_dup 2))
3888 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3889 (const_int 0)))
3890 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3891 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3892 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3893 "TARGET_POWER"
3894 "@
3895 maskir. %0,%3,%2
3896 #"
3897 [(set_attr "type" "compare")
3898 (set_attr "length" "4,8")])
3900 (define_split
3901 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3902 (compare:CC
3903 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3904 (match_operand:SI 3 "gpc_reg_operand" ""))
3905 (and:SI (not:SI (match_dup 2))
3906 (match_operand:SI 1 "gpc_reg_operand" "")))
3907 (const_int 0)))
3908 (set (match_operand:SI 0 "gpc_reg_operand" "")
3909 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3910 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3911 "TARGET_POWER && reload_completed"
3912 [(set (match_dup 0)
3913 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3914 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3915 (set (match_dup 4)
3916 (compare:CC (match_dup 0)
3917 (const_int 0)))]
3918 "")
3920 (define_insn "*maskir_internal8"
3921 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3922 (compare:CC
3923 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3924 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3925 (and:SI (not:SI (match_dup 2))
3926 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3927 (const_int 0)))
3928 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3929 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3930 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3931 "TARGET_POWER"
3932 "@
3933 maskir. %0,%3,%2
3934 #"
3935 [(set_attr "type" "compare")
3936 (set_attr "length" "4,8")])
3938 (define_split
3939 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3940 (compare:CC
3941 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3942 (match_operand:SI 2 "gpc_reg_operand" ""))
3943 (and:SI (not:SI (match_dup 2))
3944 (match_operand:SI 1 "gpc_reg_operand" "")))
3945 (const_int 0)))
3946 (set (match_operand:SI 0 "gpc_reg_operand" "")
3947 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3948 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3949 "TARGET_POWER && reload_completed"
3950 [(set (match_dup 0)
3951 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3952 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3953 (set (match_dup 4)
3954 (compare:CC (match_dup 0)
3955 (const_int 0)))]
3956 "")
3957 \f
3958 ;; Rotate and shift insns, in all their variants. These support shifts,
3959 ;; field inserts and extracts, and various combinations thereof.
3960 (define_expand "insv"
3961 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3962 (match_operand:SI 1 "const_int_operand" "")
3963 (match_operand:SI 2 "const_int_operand" ""))
3964 (match_operand 3 "gpc_reg_operand" ""))]
3965 ""
3966 "
3967 {
3968 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3969 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3970 compiler if the address of the structure is taken later. Likewise, do
3971 not handle invalid E500 subregs. */
3972 if (GET_CODE (operands[0]) == SUBREG
3973 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3974 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3975 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3976 FAIL;
3978 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3979 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3980 else
3981 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3982 DONE;
3983 }")
3985 (define_insn "insvsi"
3986 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3987 (match_operand:SI 1 "const_int_operand" "i")
3988 (match_operand:SI 2 "const_int_operand" "i"))
3989 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3990 ""
3991 "*
3992 {
3993 int start = INTVAL (operands[2]) & 31;
3994 int size = INTVAL (operands[1]) & 31;
3996 operands[4] = GEN_INT (32 - start - size);
3997 operands[1] = GEN_INT (start + size - 1);
3998 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3999 }"
4000 [(set_attr "type" "insert_word")])
4002 (define_insn "*insvsi_internal1"
4003 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4004 (match_operand:SI 1 "const_int_operand" "i")
4005 (match_operand:SI 2 "const_int_operand" "i"))
4006 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4007 (match_operand:SI 4 "const_int_operand" "i")))]
4008 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4009 "*
4010 {
4011 int shift = INTVAL (operands[4]) & 31;
4012 int start = INTVAL (operands[2]) & 31;
4013 int size = INTVAL (operands[1]) & 31;
4015 operands[4] = GEN_INT (shift - start - size);
4016 operands[1] = GEN_INT (start + size - 1);
4017 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4018 }"
4019 [(set_attr "type" "insert_word")])
4021 (define_insn "*insvsi_internal2"
4022 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4023 (match_operand:SI 1 "const_int_operand" "i")
4024 (match_operand:SI 2 "const_int_operand" "i"))
4025 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4026 (match_operand:SI 4 "const_int_operand" "i")))]
4027 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4028 "*
4029 {
4030 int shift = INTVAL (operands[4]) & 31;
4031 int start = INTVAL (operands[2]) & 31;
4032 int size = INTVAL (operands[1]) & 31;
4034 operands[4] = GEN_INT (32 - shift - start - size);
4035 operands[1] = GEN_INT (start + size - 1);
4036 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4037 }"
4038 [(set_attr "type" "insert_word")])
4040 (define_insn "*insvsi_internal3"
4041 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4042 (match_operand:SI 1 "const_int_operand" "i")
4043 (match_operand:SI 2 "const_int_operand" "i"))
4044 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4045 (match_operand:SI 4 "const_int_operand" "i")))]
4046 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4047 "*
4048 {
4049 int shift = INTVAL (operands[4]) & 31;
4050 int start = INTVAL (operands[2]) & 31;
4051 int size = INTVAL (operands[1]) & 31;
4053 operands[4] = GEN_INT (32 - shift - start - size);
4054 operands[1] = GEN_INT (start + size - 1);
4055 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4056 }"
4057 [(set_attr "type" "insert_word")])
4059 (define_insn "*insvsi_internal4"
4060 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4061 (match_operand:SI 1 "const_int_operand" "i")
4062 (match_operand:SI 2 "const_int_operand" "i"))
4063 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4064 (match_operand:SI 4 "const_int_operand" "i")
4065 (match_operand:SI 5 "const_int_operand" "i")))]
4066 "INTVAL (operands[4]) >= INTVAL (operands[1])"
4067 "*
4068 {
4069 int extract_start = INTVAL (operands[5]) & 31;
4070 int extract_size = INTVAL (operands[4]) & 31;
4071 int insert_start = INTVAL (operands[2]) & 31;
4072 int insert_size = INTVAL (operands[1]) & 31;
4074 /* Align extract field with insert field */
4075 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
4076 operands[1] = GEN_INT (insert_start + insert_size - 1);
4077 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
4078 }"
4079 [(set_attr "type" "insert_word")])
4081 ;; combine patterns for rlwimi
4082 (define_insn "*insvsi_internal5"
4083 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4084 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4085 (match_operand:SI 1 "mask_operand" "i"))
4086 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4087 (match_operand:SI 2 "const_int_operand" "i"))
4088 (match_operand:SI 5 "mask_operand" "i"))))]
4089 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4090 "*
4091 {
4092 int me = extract_ME(operands[5]);
4093 int mb = extract_MB(operands[5]);
4094 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4095 operands[2] = GEN_INT(mb);
4096 operands[1] = GEN_INT(me);
4097 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4098 }"
4099 [(set_attr "type" "insert_word")])
4101 (define_insn "*insvsi_internal6"
4102 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4103 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4104 (match_operand:SI 2 "const_int_operand" "i"))
4105 (match_operand:SI 5 "mask_operand" "i"))
4106 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4107 (match_operand:SI 1 "mask_operand" "i"))))]
4108 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4109 "*
4110 {
4111 int me = extract_ME(operands[5]);
4112 int mb = extract_MB(operands[5]);
4113 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4114 operands[2] = GEN_INT(mb);
4115 operands[1] = GEN_INT(me);
4116 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4117 }"
4118 [(set_attr "type" "insert_word")])
4120 (define_insn "insvdi"
4121 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4122 (match_operand:SI 1 "const_int_operand" "i")
4123 (match_operand:SI 2 "const_int_operand" "i"))
4124 (match_operand:DI 3 "gpc_reg_operand" "r"))]
4125 "TARGET_POWERPC64"
4126 "*
4127 {
4128 int start = INTVAL (operands[2]) & 63;
4129 int size = INTVAL (operands[1]) & 63;
4131 operands[1] = GEN_INT (64 - start - size);
4132 return \"rldimi %0,%3,%H1,%H2\";
4133 }"
4134 [(set_attr "type" "insert_dword")])
4136 (define_insn "*insvdi_internal2"
4137 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4138 (match_operand:SI 1 "const_int_operand" "i")
4139 (match_operand:SI 2 "const_int_operand" "i"))
4140 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4141 (match_operand:SI 4 "const_int_operand" "i")))]
4142 "TARGET_POWERPC64
4143 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4144 "*
4145 {
4146 int shift = INTVAL (operands[4]) & 63;
4147 int start = (INTVAL (operands[2]) & 63) - 32;
4148 int size = INTVAL (operands[1]) & 63;
4150 operands[4] = GEN_INT (64 - shift - start - size);
4151 operands[2] = GEN_INT (start);
4152 operands[1] = GEN_INT (start + size - 1);
4153 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4154 }")
4156 (define_insn "*insvdi_internal3"
4157 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4158 (match_operand:SI 1 "const_int_operand" "i")
4159 (match_operand:SI 2 "const_int_operand" "i"))
4160 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4161 (match_operand:SI 4 "const_int_operand" "i")))]
4162 "TARGET_POWERPC64
4163 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4164 "*
4165 {
4166 int shift = INTVAL (operands[4]) & 63;
4167 int start = (INTVAL (operands[2]) & 63) - 32;
4168 int size = INTVAL (operands[1]) & 63;
4170 operands[4] = GEN_INT (64 - shift - start - size);
4171 operands[2] = GEN_INT (start);
4172 operands[1] = GEN_INT (start + size - 1);
4173 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4174 }")
4176 (define_expand "extzv"
4177 [(set (match_operand 0 "gpc_reg_operand" "")
4178 (zero_extract (match_operand 1 "gpc_reg_operand" "")
4179 (match_operand:SI 2 "const_int_operand" "")
4180 (match_operand:SI 3 "const_int_operand" "")))]
4181 ""
4182 "
4183 {
4184 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4185 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4186 compiler if the address of the structure is taken later. */
4187 if (GET_CODE (operands[0]) == SUBREG
4188 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
4189 FAIL;
4191 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
4192 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
4193 else
4194 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
4195 DONE;
4196 }")
4198 (define_insn "extzvsi"
4199 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4200 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4201 (match_operand:SI 2 "const_int_operand" "i")
4202 (match_operand:SI 3 "const_int_operand" "i")))]
4203 ""
4204 "*
4205 {
4206 int start = INTVAL (operands[3]) & 31;
4207 int size = INTVAL (operands[2]) & 31;
4209 if (start + size >= 32)
4210 operands[3] = const0_rtx;
4211 else
4212 operands[3] = GEN_INT (start + size);
4213 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
4214 }")
4216 (define_insn "*extzvsi_internal1"
4217 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4218 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4219 (match_operand:SI 2 "const_int_operand" "i,i")
4220 (match_operand:SI 3 "const_int_operand" "i,i"))
4221 (const_int 0)))
4222 (clobber (match_scratch:SI 4 "=r,r"))]
4223 ""
4224 "*
4225 {
4226 int start = INTVAL (operands[3]) & 31;
4227 int size = INTVAL (operands[2]) & 31;
4229 /* Force split for non-cc0 compare. */
4230 if (which_alternative == 1)
4231 return \"#\";
4233 /* If the bit-field being tested fits in the upper or lower half of a
4234 word, it is possible to use andiu. or andil. to test it. This is
4235 useful because the condition register set-use delay is smaller for
4236 andi[ul]. than for rlinm. This doesn't work when the starting bit
4237 position is 0 because the LT and GT bits may be set wrong. */
4239 if ((start > 0 && start + size <= 16) || start >= 16)
4240 {
4241 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
4242 - (1 << (16 - (start & 15) - size))));
4243 if (start < 16)
4244 return \"{andiu.|andis.} %4,%1,%3\";
4245 else
4246 return \"{andil.|andi.} %4,%1,%3\";
4247 }
4249 if (start + size >= 32)
4250 operands[3] = const0_rtx;
4251 else
4252 operands[3] = GEN_INT (start + size);
4253 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
4254 }"
4255 [(set_attr "type" "delayed_compare")
4256 (set_attr "length" "4,8")])
4258 (define_split
4259 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4260 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4261 (match_operand:SI 2 "const_int_operand" "")
4262 (match_operand:SI 3 "const_int_operand" ""))
4263 (const_int 0)))
4264 (clobber (match_scratch:SI 4 ""))]
4265 "reload_completed"
4266 [(set (match_dup 4)
4267 (zero_extract:SI (match_dup 1) (match_dup 2)
4268 (match_dup 3)))
4269 (set (match_dup 0)
4270 (compare:CC (match_dup 4)
4271 (const_int 0)))]
4272 "")
4274 (define_insn "*extzvsi_internal2"
4275 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4276 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4277 (match_operand:SI 2 "const_int_operand" "i,i")
4278 (match_operand:SI 3 "const_int_operand" "i,i"))
4279 (const_int 0)))
4280 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4281 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4282 ""
4283 "*
4284 {
4285 int start = INTVAL (operands[3]) & 31;
4286 int size = INTVAL (operands[2]) & 31;
4288 /* Force split for non-cc0 compare. */
4289 if (which_alternative == 1)
4290 return \"#\";
4292 /* Since we are using the output value, we can't ignore any need for
4293 a shift. The bit-field must end at the LSB. */
4294 if (start >= 16 && start + size == 32)
4295 {
4296 operands[3] = GEN_INT ((1 << size) - 1);
4297 return \"{andil.|andi.} %0,%1,%3\";
4298 }
4300 if (start + size >= 32)
4301 operands[3] = const0_rtx;
4302 else
4303 operands[3] = GEN_INT (start + size);
4304 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
4305 }"
4306 [(set_attr "type" "delayed_compare")
4307 (set_attr "length" "4,8")])
4309 (define_split
4310 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4311 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4312 (match_operand:SI 2 "const_int_operand" "")
4313 (match_operand:SI 3 "const_int_operand" ""))
4314 (const_int 0)))
4315 (set (match_operand:SI 0 "gpc_reg_operand" "")
4316 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4317 "reload_completed"
4318 [(set (match_dup 0)
4319 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
4320 (set (match_dup 4)
4321 (compare:CC (match_dup 0)
4322 (const_int 0)))]
4323 "")
4325 (define_insn "extzvdi"
4326 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4327 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4328 (match_operand:SI 2 "const_int_operand" "i")
4329 (match_operand:SI 3 "const_int_operand" "i")))]
4330 "TARGET_POWERPC64"
4331 "*
4332 {
4333 int start = INTVAL (operands[3]) & 63;
4334 int size = INTVAL (operands[2]) & 63;
4336 if (start + size >= 64)
4337 operands[3] = const0_rtx;
4338 else
4339 operands[3] = GEN_INT (start + size);
4340 operands[2] = GEN_INT (64 - size);
4341 return \"rldicl %0,%1,%3,%2\";
4342 }")
4344 (define_insn "*extzvdi_internal1"
4345 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
4346 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4347 (match_operand:SI 2 "const_int_operand" "i")
4348 (match_operand:SI 3 "const_int_operand" "i"))
4349 (const_int 0)))
4350 (clobber (match_scratch:DI 4 "=r"))]
4351 "TARGET_64BIT && rs6000_gen_cell_microcode"
4352 "*
4353 {
4354 int start = INTVAL (operands[3]) & 63;
4355 int size = INTVAL (operands[2]) & 63;
4357 if (start + size >= 64)
4358 operands[3] = const0_rtx;
4359 else
4360 operands[3] = GEN_INT (start + size);
4361 operands[2] = GEN_INT (64 - size);
4362 return \"rldicl. %4,%1,%3,%2\";
4363 }"
4364 [(set_attr "type" "compare")])
4366 (define_insn "*extzvdi_internal2"
4367 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
4368 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4369 (match_operand:SI 2 "const_int_operand" "i")
4370 (match_operand:SI 3 "const_int_operand" "i"))
4371 (const_int 0)))
4372 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4373 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
4374 "TARGET_64BIT && rs6000_gen_cell_microcode"
4375 "*
4376 {
4377 int start = INTVAL (operands[3]) & 63;
4378 int size = INTVAL (operands[2]) & 63;
4380 if (start + size >= 64)
4381 operands[3] = const0_rtx;
4382 else
4383 operands[3] = GEN_INT (start + size);
4384 operands[2] = GEN_INT (64 - size);
4385 return \"rldicl. %0,%1,%3,%2\";
4386 }"
4387 [(set_attr "type" "compare")])
4389 (define_insn "rotlsi3"
4390 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4391 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4392 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4393 ""
4394 "@
4395 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4396 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4397 [(set_attr "type" "var_shift_rotate,integer")])
4399 (define_insn "*rotlsi3_64"
4400 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4401 (zero_extend:DI
4402 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4403 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4404 "TARGET_64BIT"
4405 "@
4406 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4407 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4408 [(set_attr "type" "var_shift_rotate,integer")])
4410 (define_insn "*rotlsi3_internal2"
4411 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4412 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4413 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4414 (const_int 0)))
4415 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4416 ""
4417 "@
4418 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4419 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4420 #
4421 #"
4422 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4423 (set_attr "length" "4,4,8,8")])
4425 (define_split
4426 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4427 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4428 (match_operand:SI 2 "reg_or_cint_operand" ""))
4429 (const_int 0)))
4430 (clobber (match_scratch:SI 3 ""))]
4431 "reload_completed"
4432 [(set (match_dup 3)
4433 (rotate:SI (match_dup 1) (match_dup 2)))
4434 (set (match_dup 0)
4435 (compare:CC (match_dup 3)
4436 (const_int 0)))]
4437 "")
4439 (define_insn "*rotlsi3_internal3"
4440 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4441 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4442 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4443 (const_int 0)))
4444 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4445 (rotate:SI (match_dup 1) (match_dup 2)))]
4446 ""
4447 "@
4448 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4449 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4450 #
4451 #"
4452 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4453 (set_attr "length" "4,4,8,8")])
4455 (define_split
4456 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4457 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4458 (match_operand:SI 2 "reg_or_cint_operand" ""))
4459 (const_int 0)))
4460 (set (match_operand:SI 0 "gpc_reg_operand" "")
4461 (rotate:SI (match_dup 1) (match_dup 2)))]
4462 "reload_completed"
4463 [(set (match_dup 0)
4464 (rotate:SI (match_dup 1) (match_dup 2)))
4465 (set (match_dup 3)
4466 (compare:CC (match_dup 0)
4467 (const_int 0)))]
4468 "")
4470 (define_insn "*rotlsi3_internal4"
4471 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4472 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4473 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4474 (match_operand:SI 3 "mask_operand" "n,n")))]
4475 ""
4476 "@
4477 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4478 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4479 [(set_attr "type" "var_shift_rotate,integer")])
4481 (define_insn "*rotlsi3_internal5"
4482 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4483 (compare:CC (and:SI
4484 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4485 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4486 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4487 (const_int 0)))
4488 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4489 ""
4490 "@
4491 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4492 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4493 #
4494 #"
4495 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4496 (set_attr "length" "4,4,8,8")])
4498 (define_split
4499 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4500 (compare:CC (and:SI
4501 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4502 (match_operand:SI 2 "reg_or_cint_operand" ""))
4503 (match_operand:SI 3 "mask_operand" ""))
4504 (const_int 0)))
4505 (clobber (match_scratch:SI 4 ""))]
4506 "reload_completed"
4507 [(set (match_dup 4)
4508 (and:SI (rotate:SI (match_dup 1)
4509 (match_dup 2))
4510 (match_dup 3)))
4511 (set (match_dup 0)
4512 (compare:CC (match_dup 4)
4513 (const_int 0)))]
4514 "")
4516 (define_insn "*rotlsi3_internal6"
4517 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4518 (compare:CC (and:SI
4519 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4520 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4521 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4522 (const_int 0)))
4523 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4524 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4525 ""
4526 "@
4527 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4528 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4529 #
4530 #"
4531 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4532 (set_attr "length" "4,4,8,8")])
4534 (define_split
4535 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4536 (compare:CC (and:SI
4537 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4538 (match_operand:SI 2 "reg_or_cint_operand" ""))
4539 (match_operand:SI 3 "mask_operand" ""))
4540 (const_int 0)))
4541 (set (match_operand:SI 0 "gpc_reg_operand" "")
4542 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4543 "reload_completed"
4544 [(set (match_dup 0)
4545 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4546 (set (match_dup 4)
4547 (compare:CC (match_dup 0)
4548 (const_int 0)))]
4549 "")
4551 (define_insn "*rotlsi3_internal7"
4552 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4553 (zero_extend:SI
4554 (subreg:QI
4555 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4556 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4557 ""
4558 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4559 [(set (attr "cell_micro")
4560 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4561 (const_string "not")
4562 (const_string "always")))])
4564 (define_insn "*rotlsi3_internal8"
4565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4566 (compare:CC (zero_extend:SI
4567 (subreg:QI
4568 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4569 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4570 (const_int 0)))
4571 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4572 ""
4573 "@
4574 {rlnm.|rlwnm.} %3,%1,%2,0xff
4575 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4576 #
4577 #"
4578 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4579 (set_attr "length" "4,4,8,8")])
4581 (define_split
4582 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4583 (compare:CC (zero_extend:SI
4584 (subreg:QI
4585 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4586 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4587 (const_int 0)))
4588 (clobber (match_scratch:SI 3 ""))]
4589 "reload_completed"
4590 [(set (match_dup 3)
4591 (zero_extend:SI (subreg:QI
4592 (rotate:SI (match_dup 1)
4593 (match_dup 2)) 0)))
4594 (set (match_dup 0)
4595 (compare:CC (match_dup 3)
4596 (const_int 0)))]
4597 "")
4599 (define_insn "*rotlsi3_internal9"
4600 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4601 (compare:CC (zero_extend:SI
4602 (subreg:QI
4603 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4604 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4605 (const_int 0)))
4606 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4607 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4608 ""
4609 "@
4610 {rlnm.|rlwnm.} %0,%1,%2,0xff
4611 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4612 #
4613 #"
4614 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4615 (set_attr "length" "4,4,8,8")])
4617 (define_split
4618 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4619 (compare:CC (zero_extend:SI
4620 (subreg:QI
4621 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4622 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4623 (const_int 0)))
4624 (set (match_operand:SI 0 "gpc_reg_operand" "")
4625 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4626 "reload_completed"
4627 [(set (match_dup 0)
4628 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4629 (set (match_dup 3)
4630 (compare:CC (match_dup 0)
4631 (const_int 0)))]
4632 "")
4634 (define_insn "*rotlsi3_internal10"
4635 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4636 (zero_extend:SI
4637 (subreg:HI
4638 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4639 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4640 ""
4641 "@
4642 {rlnm|rlwnm} %0,%1,%2,0xffff
4643 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4644 [(set_attr "type" "var_shift_rotate,integer")])
4647 (define_insn "*rotlsi3_internal11"
4648 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4649 (compare:CC (zero_extend:SI
4650 (subreg:HI
4651 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4652 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4653 (const_int 0)))
4654 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4655 ""
4656 "@
4657 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4658 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4659 #
4660 #"
4661 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4662 (set_attr "length" "4,4,8,8")])
4664 (define_split
4665 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4666 (compare:CC (zero_extend:SI
4667 (subreg:HI
4668 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4669 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4670 (const_int 0)))
4671 (clobber (match_scratch:SI 3 ""))]
4672 "reload_completed"
4673 [(set (match_dup 3)
4674 (zero_extend:SI (subreg:HI
4675 (rotate:SI (match_dup 1)
4676 (match_dup 2)) 0)))
4677 (set (match_dup 0)
4678 (compare:CC (match_dup 3)
4679 (const_int 0)))]
4680 "")
4682 (define_insn "*rotlsi3_internal12"
4683 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4684 (compare:CC (zero_extend:SI
4685 (subreg:HI
4686 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4687 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4688 (const_int 0)))
4689 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4690 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4691 ""
4692 "@
4693 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4694 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4695 #
4696 #"
4697 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4698 (set_attr "length" "4,4,8,8")])
4700 (define_split
4701 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4702 (compare:CC (zero_extend:SI
4703 (subreg:HI
4704 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4705 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4706 (const_int 0)))
4707 (set (match_operand:SI 0 "gpc_reg_operand" "")
4708 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4709 "reload_completed"
4710 [(set (match_dup 0)
4711 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4712 (set (match_dup 3)
4713 (compare:CC (match_dup 0)
4714 (const_int 0)))]
4715 "")
4717 ;; Note that we use "sle." instead of "sl." so that we can set
4718 ;; SHIFT_COUNT_TRUNCATED.
4720 (define_expand "ashlsi3"
4721 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4722 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4723 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4724 ""
4725 "
4726 {
4727 if (TARGET_POWER)
4728 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4729 else
4730 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4731 DONE;
4732 }")
4734 (define_insn "ashlsi3_power"
4735 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4736 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4737 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4738 (clobber (match_scratch:SI 3 "=q,X"))]
4739 "TARGET_POWER"
4740 "@
4741 sle %0,%1,%2
4742 {sli|slwi} %0,%1,%h2")
4744 (define_insn "ashlsi3_no_power"
4745 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4746 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4747 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4748 "! TARGET_POWER"
4749 "@
4750 {sl|slw} %0,%1,%2
4751 {sli|slwi} %0,%1,%h2"
4752 [(set_attr "type" "var_shift_rotate,shift")])
4754 (define_insn "*ashlsi3_64"
4755 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4756 (zero_extend:DI
4757 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4758 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4759 "TARGET_POWERPC64"
4760 "@
4761 {sl|slw} %0,%1,%2
4762 {sli|slwi} %0,%1,%h2"
4763 [(set_attr "type" "var_shift_rotate,shift")])
4765 (define_insn ""
4766 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4767 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4768 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4769 (const_int 0)))
4770 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4771 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4772 "TARGET_POWER"
4773 "@
4774 sle. %3,%1,%2
4775 {sli.|slwi.} %3,%1,%h2
4776 #
4777 #"
4778 [(set_attr "type" "delayed_compare")
4779 (set_attr "length" "4,4,8,8")])
4781 (define_split
4782 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4783 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4784 (match_operand:SI 2 "reg_or_cint_operand" ""))
4785 (const_int 0)))
4786 (clobber (match_scratch:SI 3 ""))
4787 (clobber (match_scratch:SI 4 ""))]
4788 "TARGET_POWER && reload_completed"
4789 [(parallel [(set (match_dup 3)
4790 (ashift:SI (match_dup 1) (match_dup 2)))
4791 (clobber (match_dup 4))])
4792 (set (match_dup 0)
4793 (compare:CC (match_dup 3)
4794 (const_int 0)))]
4795 "")
4797 (define_insn ""
4798 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4799 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4800 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4801 (const_int 0)))
4802 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4803 "! TARGET_POWER && TARGET_32BIT"
4804 "@
4805 {sl.|slw.} %3,%1,%2
4806 {sli.|slwi.} %3,%1,%h2
4807 #
4808 #"
4809 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4810 (set_attr "length" "4,4,8,8")])
4812 (define_split
4813 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4814 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4815 (match_operand:SI 2 "reg_or_cint_operand" ""))
4816 (const_int 0)))
4817 (clobber (match_scratch:SI 3 ""))]
4818 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4819 [(set (match_dup 3)
4820 (ashift:SI (match_dup 1) (match_dup 2)))
4821 (set (match_dup 0)
4822 (compare:CC (match_dup 3)
4823 (const_int 0)))]
4824 "")
4826 (define_insn ""
4827 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4828 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4829 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4830 (const_int 0)))
4831 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4832 (ashift:SI (match_dup 1) (match_dup 2)))
4833 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4834 "TARGET_POWER"
4835 "@
4836 sle. %0,%1,%2
4837 {sli.|slwi.} %0,%1,%h2
4838 #
4839 #"
4840 [(set_attr "type" "delayed_compare")
4841 (set_attr "length" "4,4,8,8")])
4843 (define_split
4844 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4845 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4846 (match_operand:SI 2 "reg_or_cint_operand" ""))
4847 (const_int 0)))
4848 (set (match_operand:SI 0 "gpc_reg_operand" "")
4849 (ashift:SI (match_dup 1) (match_dup 2)))
4850 (clobber (match_scratch:SI 4 ""))]
4851 "TARGET_POWER && reload_completed"
4852 [(parallel [(set (match_dup 0)
4853 (ashift:SI (match_dup 1) (match_dup 2)))
4854 (clobber (match_dup 4))])
4855 (set (match_dup 3)
4856 (compare:CC (match_dup 0)
4857 (const_int 0)))]
4858 "")
4860 (define_insn ""
4861 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4862 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4863 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4864 (const_int 0)))
4865 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4866 (ashift:SI (match_dup 1) (match_dup 2)))]
4867 "! TARGET_POWER && TARGET_32BIT"
4868 "@
4869 {sl.|slw.} %0,%1,%2
4870 {sli.|slwi.} %0,%1,%h2
4871 #
4872 #"
4873 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4874 (set_attr "length" "4,4,8,8")])
4876 (define_split
4877 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4878 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4879 (match_operand:SI 2 "reg_or_cint_operand" ""))
4880 (const_int 0)))
4881 (set (match_operand:SI 0 "gpc_reg_operand" "")
4882 (ashift:SI (match_dup 1) (match_dup 2)))]
4883 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4884 [(set (match_dup 0)
4885 (ashift:SI (match_dup 1) (match_dup 2)))
4886 (set (match_dup 3)
4887 (compare:CC (match_dup 0)
4888 (const_int 0)))]
4889 "")
4891 (define_insn "rlwinm"
4892 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4893 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4894 (match_operand:SI 2 "const_int_operand" "i"))
4895 (match_operand:SI 3 "mask_operand" "n")))]
4896 "includes_lshift_p (operands[2], operands[3])"
4897 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4899 (define_insn ""
4900 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4901 (compare:CC
4902 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4903 (match_operand:SI 2 "const_int_operand" "i,i"))
4904 (match_operand:SI 3 "mask_operand" "n,n"))
4905 (const_int 0)))
4906 (clobber (match_scratch:SI 4 "=r,r"))]
4907 "includes_lshift_p (operands[2], operands[3])"
4908 "@
4909 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4910 #"
4911 [(set_attr "type" "delayed_compare")
4912 (set_attr "length" "4,8")])
4914 (define_split
4915 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4916 (compare:CC
4917 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4918 (match_operand:SI 2 "const_int_operand" ""))
4919 (match_operand:SI 3 "mask_operand" ""))
4920 (const_int 0)))
4921 (clobber (match_scratch:SI 4 ""))]
4922 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4923 [(set (match_dup 4)
4924 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4925 (match_dup 3)))
4926 (set (match_dup 0)
4927 (compare:CC (match_dup 4)
4928 (const_int 0)))]
4929 "")
4931 (define_insn ""
4932 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4933 (compare:CC
4934 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4935 (match_operand:SI 2 "const_int_operand" "i,i"))
4936 (match_operand:SI 3 "mask_operand" "n,n"))
4937 (const_int 0)))
4938 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4939 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4940 "includes_lshift_p (operands[2], operands[3])"
4941 "@
4942 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4943 #"
4944 [(set_attr "type" "delayed_compare")
4945 (set_attr "length" "4,8")])
4947 (define_split
4948 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4949 (compare:CC
4950 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4951 (match_operand:SI 2 "const_int_operand" ""))
4952 (match_operand:SI 3 "mask_operand" ""))
4953 (const_int 0)))
4954 (set (match_operand:SI 0 "gpc_reg_operand" "")
4955 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4956 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4957 [(set (match_dup 0)
4958 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4959 (set (match_dup 4)
4960 (compare:CC (match_dup 0)
4961 (const_int 0)))]
4962 "")
4964 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4965 ;; "sli x,x,0".
4966 (define_expand "lshrsi3"
4967 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4968 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4969 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4970 ""
4971 "
4972 {
4973 if (TARGET_POWER)
4974 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4975 else
4976 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4977 DONE;
4978 }")
4980 (define_insn "lshrsi3_power"
4981 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4982 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4983 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4984 (clobber (match_scratch:SI 3 "=q,X,X"))]
4985 "TARGET_POWER"
4986 "@
4987 sre %0,%1,%2
4988 mr %0,%1
4989 {s%A2i|s%A2wi} %0,%1,%h2")
4991 (define_insn "lshrsi3_no_power"
4992 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4993 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4994 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4995 "! TARGET_POWER"
4996 "@
4997 mr %0,%1
4998 {sr|srw} %0,%1,%2
4999 {sri|srwi} %0,%1,%h2"
5000 [(set_attr "type" "integer,var_shift_rotate,shift")])
5002 (define_insn "*lshrsi3_64"
5003 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5004 (zero_extend:DI
5005 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5006 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5007 "TARGET_POWERPC64"
5008 "@
5009 {sr|srw} %0,%1,%2
5010 {sri|srwi} %0,%1,%h2"
5011 [(set_attr "type" "var_shift_rotate,shift")])
5013 (define_insn ""
5014 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5015 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5016 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5017 (const_int 0)))
5018 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
5019 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5020 "TARGET_POWER"
5021 "@
5022 sre. %3,%1,%2
5023 mr. %1,%1
5024 {s%A2i.|s%A2wi.} %3,%1,%h2
5025 #
5026 #
5027 #"
5028 [(set_attr "type" "delayed_compare")
5029 (set_attr "length" "4,4,4,8,8,8")])
5031 (define_split
5032 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5033 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5034 (match_operand:SI 2 "reg_or_cint_operand" ""))
5035 (const_int 0)))
5036 (clobber (match_scratch:SI 3 ""))
5037 (clobber (match_scratch:SI 4 ""))]
5038 "TARGET_POWER && reload_completed"
5039 [(parallel [(set (match_dup 3)
5040 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5041 (clobber (match_dup 4))])
5042 (set (match_dup 0)
5043 (compare:CC (match_dup 3)
5044 (const_int 0)))]
5045 "")
5047 (define_insn ""
5048 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5049 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5050 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5051 (const_int 0)))
5052 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
5053 "! TARGET_POWER && TARGET_32BIT"
5054 "@
5055 mr. %1,%1
5056 {sr.|srw.} %3,%1,%2
5057 {sri.|srwi.} %3,%1,%h2
5058 #
5059 #
5060 #"
5061 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5062 (set_attr "length" "4,4,4,8,8,8")])
5064 (define_split
5065 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5066 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5067 (match_operand:SI 2 "reg_or_cint_operand" ""))
5068 (const_int 0)))
5069 (clobber (match_scratch:SI 3 ""))]
5070 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5071 [(set (match_dup 3)
5072 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5073 (set (match_dup 0)
5074 (compare:CC (match_dup 3)
5075 (const_int 0)))]
5076 "")
5078 (define_insn ""
5079 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5080 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5081 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5082 (const_int 0)))
5083 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5084 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5085 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5086 "TARGET_POWER"
5087 "@
5088 sre. %0,%1,%2
5089 mr. %0,%1
5090 {s%A2i.|s%A2wi.} %0,%1,%h2
5091 #
5092 #
5093 #"
5094 [(set_attr "type" "delayed_compare")
5095 (set_attr "length" "4,4,4,8,8,8")])
5097 (define_split
5098 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5099 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5100 (match_operand:SI 2 "reg_or_cint_operand" ""))
5101 (const_int 0)))
5102 (set (match_operand:SI 0 "gpc_reg_operand" "")
5103 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5104 (clobber (match_scratch:SI 4 ""))]
5105 "TARGET_POWER && reload_completed"
5106 [(parallel [(set (match_dup 0)
5107 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5108 (clobber (match_dup 4))])
5109 (set (match_dup 3)
5110 (compare:CC (match_dup 0)
5111 (const_int 0)))]
5112 "")
5114 (define_insn ""
5115 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5116 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5117 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5118 (const_int 0)))
5119 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5120 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5121 "! TARGET_POWER && TARGET_32BIT"
5122 "@
5123 mr. %0,%1
5124 {sr.|srw.} %0,%1,%2
5125 {sri.|srwi.} %0,%1,%h2
5126 #
5127 #
5128 #"
5129 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5130 (set_attr "length" "4,4,4,8,8,8")])
5132 (define_split
5133 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5134 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5135 (match_operand:SI 2 "reg_or_cint_operand" ""))
5136 (const_int 0)))
5137 (set (match_operand:SI 0 "gpc_reg_operand" "")
5138 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5139 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5140 [(set (match_dup 0)
5141 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5142 (set (match_dup 3)
5143 (compare:CC (match_dup 0)
5144 (const_int 0)))]
5145 "")
5147 (define_insn ""
5148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5149 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5150 (match_operand:SI 2 "const_int_operand" "i"))
5151 (match_operand:SI 3 "mask_operand" "n")))]
5152 "includes_rshift_p (operands[2], operands[3])"
5153 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
5155 (define_insn ""
5156 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5157 (compare:CC
5158 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5159 (match_operand:SI 2 "const_int_operand" "i,i"))
5160 (match_operand:SI 3 "mask_operand" "n,n"))
5161 (const_int 0)))
5162 (clobber (match_scratch:SI 4 "=r,r"))]
5163 "includes_rshift_p (operands[2], operands[3])"
5164 "@
5165 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
5166 #"
5167 [(set_attr "type" "delayed_compare")
5168 (set_attr "length" "4,8")])
5170 (define_split
5171 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5172 (compare:CC
5173 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5174 (match_operand:SI 2 "const_int_operand" ""))
5175 (match_operand:SI 3 "mask_operand" ""))
5176 (const_int 0)))
5177 (clobber (match_scratch:SI 4 ""))]
5178 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5179 [(set (match_dup 4)
5180 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
5181 (match_dup 3)))
5182 (set (match_dup 0)
5183 (compare:CC (match_dup 4)
5184 (const_int 0)))]
5185 "")
5187 (define_insn ""
5188 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5189 (compare:CC
5190 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5191 (match_operand:SI 2 "const_int_operand" "i,i"))
5192 (match_operand:SI 3 "mask_operand" "n,n"))
5193 (const_int 0)))
5194 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5195 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5196 "includes_rshift_p (operands[2], operands[3])"
5197 "@
5198 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
5199 #"
5200 [(set_attr "type" "delayed_compare")
5201 (set_attr "length" "4,8")])
5203 (define_split
5204 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5205 (compare:CC
5206 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5207 (match_operand:SI 2 "const_int_operand" ""))
5208 (match_operand:SI 3 "mask_operand" ""))
5209 (const_int 0)))
5210 (set (match_operand:SI 0 "gpc_reg_operand" "")
5211 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5212 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5213 [(set (match_dup 0)
5214 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5215 (set (match_dup 4)
5216 (compare:CC (match_dup 0)
5217 (const_int 0)))]
5218 "")
5220 (define_insn ""
5221 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5222 (zero_extend:SI
5223 (subreg:QI
5224 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5225 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5226 "includes_rshift_p (operands[2], GEN_INT (255))"
5227 "{rlinm|rlwinm} %0,%1,%s2,0xff")
5229 (define_insn ""
5230 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5231 (compare:CC
5232 (zero_extend:SI
5233 (subreg:QI
5234 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5235 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5236 (const_int 0)))
5237 (clobber (match_scratch:SI 3 "=r,r"))]
5238 "includes_rshift_p (operands[2], GEN_INT (255))"
5239 "@
5240 {rlinm.|rlwinm.} %3,%1,%s2,0xff
5241 #"
5242 [(set_attr "type" "delayed_compare")
5243 (set_attr "length" "4,8")])
5245 (define_split
5246 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5247 (compare:CC
5248 (zero_extend:SI
5249 (subreg:QI
5250 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5251 (match_operand:SI 2 "const_int_operand" "")) 0))
5252 (const_int 0)))
5253 (clobber (match_scratch:SI 3 ""))]
5254 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5255 [(set (match_dup 3)
5256 (zero_extend:SI (subreg:QI
5257 (lshiftrt:SI (match_dup 1)
5258 (match_dup 2)) 0)))
5259 (set (match_dup 0)
5260 (compare:CC (match_dup 3)
5261 (const_int 0)))]
5262 "")
5264 (define_insn ""
5265 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5266 (compare:CC
5267 (zero_extend:SI
5268 (subreg:QI
5269 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5270 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5271 (const_int 0)))
5272 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5273 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5274 "includes_rshift_p (operands[2], GEN_INT (255))"
5275 "@
5276 {rlinm.|rlwinm.} %0,%1,%s2,0xff
5277 #"
5278 [(set_attr "type" "delayed_compare")
5279 (set_attr "length" "4,8")])
5281 (define_split
5282 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5283 (compare:CC
5284 (zero_extend:SI
5285 (subreg:QI
5286 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5287 (match_operand:SI 2 "const_int_operand" "")) 0))
5288 (const_int 0)))
5289 (set (match_operand:SI 0 "gpc_reg_operand" "")
5290 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5291 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5292 [(set (match_dup 0)
5293 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5294 (set (match_dup 3)
5295 (compare:CC (match_dup 0)
5296 (const_int 0)))]
5297 "")
5299 (define_insn ""
5300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5301 (zero_extend:SI
5302 (subreg:HI
5303 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5304 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5305 "includes_rshift_p (operands[2], GEN_INT (65535))"
5306 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
5308 (define_insn ""
5309 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5310 (compare:CC
5311 (zero_extend:SI
5312 (subreg:HI
5313 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5314 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5315 (const_int 0)))
5316 (clobber (match_scratch:SI 3 "=r,r"))]
5317 "includes_rshift_p (operands[2], GEN_INT (65535))"
5318 "@
5319 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
5320 #"
5321 [(set_attr "type" "delayed_compare")
5322 (set_attr "length" "4,8")])
5324 (define_split
5325 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5326 (compare:CC
5327 (zero_extend:SI
5328 (subreg:HI
5329 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5330 (match_operand:SI 2 "const_int_operand" "")) 0))
5331 (const_int 0)))
5332 (clobber (match_scratch:SI 3 ""))]
5333 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5334 [(set (match_dup 3)
5335 (zero_extend:SI (subreg:HI
5336 (lshiftrt:SI (match_dup 1)
5337 (match_dup 2)) 0)))
5338 (set (match_dup 0)
5339 (compare:CC (match_dup 3)
5340 (const_int 0)))]
5341 "")
5343 (define_insn ""
5344 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5345 (compare:CC
5346 (zero_extend:SI
5347 (subreg:HI
5348 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5349 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5350 (const_int 0)))
5351 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5352 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5353 "includes_rshift_p (operands[2], GEN_INT (65535))"
5354 "@
5355 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
5356 #"
5357 [(set_attr "type" "delayed_compare")
5358 (set_attr "length" "4,8")])
5360 (define_split
5361 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5362 (compare:CC
5363 (zero_extend:SI
5364 (subreg:HI
5365 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5366 (match_operand:SI 2 "const_int_operand" "")) 0))
5367 (const_int 0)))
5368 (set (match_operand:SI 0 "gpc_reg_operand" "")
5369 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5370 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5371 [(set (match_dup 0)
5372 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5373 (set (match_dup 3)
5374 (compare:CC (match_dup 0)
5375 (const_int 0)))]
5376 "")
5378 (define_insn ""
5379 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5380 (const_int 1)
5381 (match_operand:SI 1 "gpc_reg_operand" "r"))
5382 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5383 (const_int 31)))]
5384 "TARGET_POWER"
5385 "rrib %0,%1,%2")
5387 (define_insn ""
5388 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5389 (const_int 1)
5390 (match_operand:SI 1 "gpc_reg_operand" "r"))
5391 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5392 (const_int 31)))]
5393 "TARGET_POWER"
5394 "rrib %0,%1,%2")
5396 (define_insn ""
5397 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5398 (const_int 1)
5399 (match_operand:SI 1 "gpc_reg_operand" "r"))
5400 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5401 (const_int 1)
5402 (const_int 0)))]
5403 "TARGET_POWER"
5404 "rrib %0,%1,%2")
5406 (define_expand "ashrsi3"
5407 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5408 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5409 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5410 ""
5411 "
5412 {
5413 if (TARGET_POWER)
5414 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
5415 else
5416 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
5417 DONE;
5418 }")
5420 (define_insn "ashrsi3_power"
5421 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5422 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5423 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
5424 (clobber (match_scratch:SI 3 "=q,X"))]
5425 "TARGET_POWER"
5426 "@
5427 srea %0,%1,%2
5428 {srai|srawi} %0,%1,%h2"
5429 [(set_attr "type" "shift")])
5431 (define_insn "ashrsi3_no_power"
5432 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5433 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5434 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
5435 "! TARGET_POWER"
5436 "@
5437 {sra|sraw} %0,%1,%2
5438 {srai|srawi} %0,%1,%h2"
5439 [(set_attr "type" "var_shift_rotate,shift")])
5441 (define_insn "*ashrsi3_64"
5442 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5443 (sign_extend:DI
5444 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5445 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5446 "TARGET_POWERPC64"
5447 "@
5448 {sra|sraw} %0,%1,%2
5449 {srai|srawi} %0,%1,%h2"
5450 [(set_attr "type" "var_shift_rotate,shift")])
5452 (define_insn ""
5453 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5454 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5455 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5456 (const_int 0)))
5457 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5458 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5459 "TARGET_POWER"
5460 "@
5461 srea. %3,%1,%2
5462 {srai.|srawi.} %3,%1,%h2
5463 #
5464 #"
5465 [(set_attr "type" "delayed_compare")
5466 (set_attr "length" "4,4,8,8")])
5468 (define_split
5469 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5470 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5471 (match_operand:SI 2 "reg_or_cint_operand" ""))
5472 (const_int 0)))
5473 (clobber (match_scratch:SI 3 ""))
5474 (clobber (match_scratch:SI 4 ""))]
5475 "TARGET_POWER && reload_completed"
5476 [(parallel [(set (match_dup 3)
5477 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5478 (clobber (match_dup 4))])
5479 (set (match_dup 0)
5480 (compare:CC (match_dup 3)
5481 (const_int 0)))]
5482 "")
5484 (define_insn ""
5485 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5486 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5487 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5488 (const_int 0)))
5489 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5490 "! TARGET_POWER"
5491 "@
5492 {sra.|sraw.} %3,%1,%2
5493 {srai.|srawi.} %3,%1,%h2
5494 #
5495 #"
5496 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5497 (set_attr "length" "4,4,8,8")])
5499 (define_split
5500 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5501 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5502 (match_operand:SI 2 "reg_or_cint_operand" ""))
5503 (const_int 0)))
5504 (clobber (match_scratch:SI 3 ""))]
5505 "! TARGET_POWER && reload_completed"
5506 [(set (match_dup 3)
5507 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5508 (set (match_dup 0)
5509 (compare:CC (match_dup 3)
5510 (const_int 0)))]
5511 "")
5513 (define_insn ""
5514 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5515 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5516 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5517 (const_int 0)))
5518 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5519 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5520 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5521 "TARGET_POWER"
5522 "@
5523 srea. %0,%1,%2
5524 {srai.|srawi.} %0,%1,%h2
5525 #
5526 #"
5527 [(set_attr "type" "delayed_compare")
5528 (set_attr "length" "4,4,8,8")])
5530 (define_split
5531 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5532 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5533 (match_operand:SI 2 "reg_or_cint_operand" ""))
5534 (const_int 0)))
5535 (set (match_operand:SI 0 "gpc_reg_operand" "")
5536 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5537 (clobber (match_scratch:SI 4 ""))]
5538 "TARGET_POWER && reload_completed"
5539 [(parallel [(set (match_dup 0)
5540 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5541 (clobber (match_dup 4))])
5542 (set (match_dup 3)
5543 (compare:CC (match_dup 0)
5544 (const_int 0)))]
5545 "")
5547 (define_insn ""
5548 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5549 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5550 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5551 (const_int 0)))
5552 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5553 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5554 "! TARGET_POWER"
5555 "@
5556 {sra.|sraw.} %0,%1,%2
5557 {srai.|srawi.} %0,%1,%h2
5558 #
5559 #"
5560 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5561 (set_attr "length" "4,4,8,8")])
5562 \f
5563 (define_split
5564 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5565 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5566 (match_operand:SI 2 "reg_or_cint_operand" ""))
5567 (const_int 0)))
5568 (set (match_operand:SI 0 "gpc_reg_operand" "")
5569 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5570 "! TARGET_POWER && reload_completed"
5571 [(set (match_dup 0)
5572 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5573 (set (match_dup 3)
5574 (compare:CC (match_dup 0)
5575 (const_int 0)))]
5576 "")
5578 ;; Floating-point insns, excluding normal data motion.
5579 ;;
5580 ;; PowerPC has a full set of single-precision floating point instructions.
5581 ;;
5582 ;; For the POWER architecture, we pretend that we have both SFmode and
5583 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5584 ;; The only conversions we will do will be when storing to memory. In that
5585 ;; case, we will use the "frsp" instruction before storing.
5586 ;;
5587 ;; Note that when we store into a single-precision memory location, we need to
5588 ;; use the frsp insn first. If the register being stored isn't dead, we
5589 ;; need a scratch register for the frsp. But this is difficult when the store
5590 ;; is done by reload. It is not incorrect to do the frsp on the register in
5591 ;; this case, we just lose precision that we would have otherwise gotten but
5592 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5594 (define_expand "extendsfdf2"
5595 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5596 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5597 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5598 "")
5600 (define_insn_and_split "*extendsfdf2_fpr"
5601 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5602 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5603 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5604 "@
5605 #
5606 fmr %0,%1
5607 lfs%U1%X1 %0,%1"
5608 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5609 [(const_int 0)]
5610 {
5611 emit_note (NOTE_INSN_DELETED);
5612 DONE;
5613 }
5614 [(set_attr "type" "fp,fp,fpload")])
5616 (define_expand "truncdfsf2"
5617 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5618 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5619 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5620 "")
5622 (define_insn "*truncdfsf2_fpr"
5623 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5624 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5625 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5626 "frsp %0,%1"
5627 [(set_attr "type" "fp")])
5629 (define_insn "aux_truncdfsf2"
5630 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5631 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5632 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5633 "frsp %0,%1"
5634 [(set_attr "type" "fp")])
5636 (define_expand "negsf2"
5637 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5638 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5639 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5640 "")
5642 (define_insn "*negsf2"
5643 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5644 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5645 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5646 "fneg %0,%1"
5647 [(set_attr "type" "fp")])
5649 (define_expand "abssf2"
5650 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5651 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5652 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5653 "")
5655 (define_insn "*abssf2"
5656 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5657 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5658 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5659 "fabs %0,%1"
5660 [(set_attr "type" "fp")])
5662 (define_insn ""
5663 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5664 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5665 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5666 "fnabs %0,%1"
5667 [(set_attr "type" "fp")])
5669 (define_expand "addsf3"
5670 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5671 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5672 (match_operand:SF 2 "gpc_reg_operand" "")))]
5673 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5674 "")
5676 (define_insn ""
5677 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5678 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5679 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5680 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5681 "fadds %0,%1,%2"
5682 [(set_attr "type" "fp")
5683 (set_attr "fp_type" "fp_addsub_s")])
5685 (define_insn ""
5686 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5687 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5688 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5689 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5690 "{fa|fadd} %0,%1,%2"
5691 [(set_attr "type" "fp")])
5693 (define_expand "subsf3"
5694 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5695 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5696 (match_operand:SF 2 "gpc_reg_operand" "")))]
5697 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5698 "")
5700 (define_insn ""
5701 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5702 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5703 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5704 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5705 "fsubs %0,%1,%2"
5706 [(set_attr "type" "fp")
5707 (set_attr "fp_type" "fp_addsub_s")])
5709 (define_insn ""
5710 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5711 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5712 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5713 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5714 "{fs|fsub} %0,%1,%2"
5715 [(set_attr "type" "fp")])
5717 (define_expand "mulsf3"
5718 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5719 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5720 (match_operand:SF 2 "gpc_reg_operand" "")))]
5721 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5722 "")
5724 (define_insn ""
5725 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5726 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5727 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5728 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5729 "fmuls %0,%1,%2"
5730 [(set_attr "type" "fp")
5731 (set_attr "fp_type" "fp_mul_s")])
5733 (define_insn ""
5734 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5735 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5736 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5737 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5738 "{fm|fmul} %0,%1,%2"
5739 [(set_attr "type" "dmul")])
5741 (define_expand "divsf3"
5742 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5743 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5744 (match_operand:SF 2 "gpc_reg_operand" "")))]
5745 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5746 "")
5748 (define_insn ""
5749 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5750 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5751 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5752 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5753 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5754 "fdivs %0,%1,%2"
5755 [(set_attr "type" "sdiv")])
5757 (define_insn ""
5758 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5759 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5760 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5761 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5762 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5763 "{fd|fdiv} %0,%1,%2"
5764 [(set_attr "type" "ddiv")])
5766 (define_expand "recipsf3"
5767 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5768 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5769 (match_operand:SF 2 "gpc_reg_operand" "f")]
5770 UNSPEC_FRES))]
5771 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5772 && flag_finite_math_only && !flag_trapping_math"
5773 {
5774 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5775 DONE;
5776 })
5778 (define_insn "fres"
5779 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5780 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5781 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5782 "fres %0,%1"
5783 [(set_attr "type" "fp")])
5785 (define_insn "*fmaddsf4_powerpc"
5786 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5787 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5788 (match_operand:SF 2 "gpc_reg_operand" "f"))
5789 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5790 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5791 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5792 "fmadds %0,%1,%2,%3"
5793 [(set_attr "type" "fp")
5794 (set_attr "fp_type" "fp_maddsub_s")])
5796 (define_insn "*fmaddsf4_power"
5797 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5798 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5799 (match_operand:SF 2 "gpc_reg_operand" "f"))
5800 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5801 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5802 "{fma|fmadd} %0,%1,%2,%3"
5803 [(set_attr "type" "dmul")])
5805 (define_insn "*fmsubsf4_powerpc"
5806 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5807 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5808 (match_operand:SF 2 "gpc_reg_operand" "f"))
5809 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5810 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5811 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5812 "fmsubs %0,%1,%2,%3"
5813 [(set_attr "type" "fp")
5814 (set_attr "fp_type" "fp_maddsub_s")])
5816 (define_insn "*fmsubsf4_power"
5817 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5818 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5819 (match_operand:SF 2 "gpc_reg_operand" "f"))
5820 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5821 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5822 "{fms|fmsub} %0,%1,%2,%3"
5823 [(set_attr "type" "dmul")])
5825 (define_insn "*fnmaddsf4_powerpc_1"
5826 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5827 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5828 (match_operand:SF 2 "gpc_reg_operand" "f"))
5829 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5830 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5831 && TARGET_SINGLE_FLOAT"
5832 "fnmadds %0,%1,%2,%3"
5833 [(set_attr "type" "fp")
5834 (set_attr "fp_type" "fp_maddsub_s")])
5836 (define_insn "*fnmaddsf4_powerpc_2"
5837 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5838 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5839 (match_operand:SF 2 "gpc_reg_operand" "f"))
5840 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5841 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5842 && ! HONOR_SIGNED_ZEROS (SFmode)"
5843 "fnmadds %0,%1,%2,%3"
5844 [(set_attr "type" "fp")
5845 (set_attr "fp_type" "fp_maddsub_s")])
5847 (define_insn "*fnmaddsf4_power_1"
5848 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5849 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5850 (match_operand:SF 2 "gpc_reg_operand" "f"))
5851 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5852 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5853 "{fnma|fnmadd} %0,%1,%2,%3"
5854 [(set_attr "type" "dmul")])
5856 (define_insn "*fnmaddsf4_power_2"
5857 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5858 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5859 (match_operand:SF 2 "gpc_reg_operand" "f"))
5860 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5861 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5862 && ! HONOR_SIGNED_ZEROS (SFmode)"
5863 "{fnma|fnmadd} %0,%1,%2,%3"
5864 [(set_attr "type" "dmul")])
5866 (define_insn "*fnmsubsf4_powerpc_1"
5867 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5868 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5869 (match_operand:SF 2 "gpc_reg_operand" "f"))
5870 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5871 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5872 && TARGET_SINGLE_FLOAT"
5873 "fnmsubs %0,%1,%2,%3"
5874 [(set_attr "type" "fp")
5875 (set_attr "fp_type" "fp_maddsub_s")])
5877 (define_insn "*fnmsubsf4_powerpc_2"
5878 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5879 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5880 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5881 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5882 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5883 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5884 "fnmsubs %0,%1,%2,%3"
5885 [(set_attr "type" "fp")
5886 (set_attr "fp_type" "fp_maddsub_s")])
5888 (define_insn "*fnmsubsf4_power_1"
5889 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5890 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5891 (match_operand:SF 2 "gpc_reg_operand" "f"))
5892 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5893 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5894 "{fnms|fnmsub} %0,%1,%2,%3"
5895 [(set_attr "type" "dmul")])
5897 (define_insn "*fnmsubsf4_power_2"
5898 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5899 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5900 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5901 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5902 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5903 && ! HONOR_SIGNED_ZEROS (SFmode)"
5904 "{fnms|fnmsub} %0,%1,%2,%3"
5905 [(set_attr "type" "dmul")])
5907 (define_expand "sqrtsf2"
5908 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5909 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5910 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5911 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5912 && !TARGET_SIMPLE_FPU"
5913 "")
5915 (define_insn ""
5916 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5917 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5918 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5919 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5920 "fsqrts %0,%1"
5921 [(set_attr "type" "ssqrt")])
5923 (define_insn ""
5924 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5925 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5926 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5927 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5928 "fsqrt %0,%1"
5929 [(set_attr "type" "dsqrt")])
5931 (define_expand "rsqrtsf2"
5932 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5933 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5934 UNSPEC_RSQRT))]
5935 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5936 && flag_finite_math_only && !flag_trapping_math"
5937 {
5938 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5939 DONE;
5940 })
5942 (define_insn "*rsqrt_internal1"
5943 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5944 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5945 UNSPEC_RSQRT))]
5946 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5947 "frsqrte %0,%1"
5948 [(set_attr "type" "fp")])
5950 (define_expand "copysignsf3"
5951 [(set (match_dup 3)
5952 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5953 (set (match_dup 4)
5954 (neg:SF (abs:SF (match_dup 1))))
5955 (set (match_operand:SF 0 "gpc_reg_operand" "")
5956 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5957 (match_dup 5))
5958 (match_dup 3)
5959 (match_dup 4)))]
5960 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5961 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5962 {
5963 operands[3] = gen_reg_rtx (SFmode);
5964 operands[4] = gen_reg_rtx (SFmode);
5965 operands[5] = CONST0_RTX (SFmode);
5966 })
5968 (define_expand "copysigndf3"
5969 [(set (match_dup 3)
5970 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5971 (set (match_dup 4)
5972 (neg:DF (abs:DF (match_dup 1))))
5973 (set (match_operand:DF 0 "gpc_reg_operand" "")
5974 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5975 (match_dup 5))
5976 (match_dup 3)
5977 (match_dup 4)))]
5978 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5979 && ((TARGET_PPC_GFXOPT
5980 && !HONOR_NANS (DFmode)
5981 && !HONOR_SIGNED_ZEROS (DFmode))
5982 || VECTOR_UNIT_VSX_P (DFmode))"
5983 {
5984 if (VECTOR_UNIT_VSX_P (DFmode))
5985 {
5986 emit_insn (gen_vsx_copysigndf3 (operands[0], operands[1],
5987 operands[2], CONST0_RTX (DFmode)));
5988 DONE;
5989 }
5990 operands[3] = gen_reg_rtx (DFmode);
5991 operands[4] = gen_reg_rtx (DFmode);
5992 operands[5] = CONST0_RTX (DFmode);
5993 })
5995 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5996 ;; fsel instruction and some auxiliary computations. Then we just have a
5997 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5998 ;; combine.
5999 (define_expand "smaxsf3"
6000 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6001 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6002 (match_operand:SF 2 "gpc_reg_operand" ""))
6003 (match_dup 1)
6004 (match_dup 2)))]
6005 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6006 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6007 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6009 (define_expand "sminsf3"
6010 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6011 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6012 (match_operand:SF 2 "gpc_reg_operand" ""))
6013 (match_dup 2)
6014 (match_dup 1)))]
6015 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6016 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6017 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6019 (define_split
6020 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6021 (match_operator:SF 3 "min_max_operator"
6022 [(match_operand:SF 1 "gpc_reg_operand" "")
6023 (match_operand:SF 2 "gpc_reg_operand" "")]))]
6024 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6025 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6026 [(const_int 0)]
6027 "
6028 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6029 operands[1], operands[2]);
6030 DONE;
6031 }")
6033 (define_expand "mov<mode>cc"
6034 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
6035 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6036 (match_operand:GPR 2 "gpc_reg_operand" "")
6037 (match_operand:GPR 3 "gpc_reg_operand" "")))]
6038 "TARGET_ISEL<sel>"
6039 "
6040 {
6041 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6042 DONE;
6043 else
6044 FAIL;
6045 }")
6047 ;; We use the BASE_REGS for the isel input operands because, if rA is
6048 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
6049 ;; because we may switch the operands and rB may end up being rA.
6050 ;;
6051 ;; We need 2 patterns: an unsigned and a signed pattern. We could
6052 ;; leave out the mode in operand 4 and use one pattern, but reload can
6053 ;; change the mode underneath our feet and then gets confused trying
6054 ;; to reload the value.
6055 (define_insn "isel_signed_<mode>"
6056 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6057 (if_then_else:GPR
6058 (match_operator 1 "comparison_operator"
6059 [(match_operand:CC 4 "cc_reg_operand" "y")
6060 (const_int 0)])
6061 (match_operand:GPR 2 "gpc_reg_operand" "b")
6062 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6063 "TARGET_ISEL<sel>"
6064 "*
6065 { return output_isel (operands); }"
6066 [(set_attr "type" "isel")
6067 (set_attr "length" "4")])
6069 (define_insn "isel_unsigned_<mode>"
6070 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6071 (if_then_else:GPR
6072 (match_operator 1 "comparison_operator"
6073 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
6074 (const_int 0)])
6075 (match_operand:GPR 2 "gpc_reg_operand" "b")
6076 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6077 "TARGET_ISEL<sel>"
6078 "*
6079 { return output_isel (operands); }"
6080 [(set_attr "type" "isel")
6081 (set_attr "length" "4")])
6083 (define_expand "movsfcc"
6084 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6085 (if_then_else:SF (match_operand 1 "comparison_operator" "")
6086 (match_operand:SF 2 "gpc_reg_operand" "")
6087 (match_operand:SF 3 "gpc_reg_operand" "")))]
6088 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6089 "
6090 {
6091 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6092 DONE;
6093 else
6094 FAIL;
6095 }")
6097 (define_insn "*fselsfsf4"
6098 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6099 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6100 (match_operand:SF 4 "zero_fp_constant" "F"))
6101 (match_operand:SF 2 "gpc_reg_operand" "f")
6102 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6103 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6104 "fsel %0,%1,%2,%3"
6105 [(set_attr "type" "fp")])
6107 (define_insn "*fseldfsf4"
6108 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6109 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6110 (match_operand:DF 4 "zero_fp_constant" "F"))
6111 (match_operand:SF 2 "gpc_reg_operand" "f")
6112 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6113 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6114 "fsel %0,%1,%2,%3"
6115 [(set_attr "type" "fp")])
6117 (define_expand "negdf2"
6118 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6119 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6120 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6121 "")
6123 (define_insn "*negdf2_fpr"
6124 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6125 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6126 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6127 && !VECTOR_UNIT_VSX_P (DFmode)"
6128 "fneg %0,%1"
6129 [(set_attr "type" "fp")])
6131 (define_expand "absdf2"
6132 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6133 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6134 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6135 "")
6137 (define_insn "*absdf2_fpr"
6138 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6139 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6140 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6141 && !VECTOR_UNIT_VSX_P (DFmode)"
6142 "fabs %0,%1"
6143 [(set_attr "type" "fp")])
6145 (define_insn "*nabsdf2_fpr"
6146 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6147 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6148 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6149 && !VECTOR_UNIT_VSX_P (DFmode)"
6150 "fnabs %0,%1"
6151 [(set_attr "type" "fp")])
6153 (define_expand "adddf3"
6154 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6155 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6156 (match_operand:DF 2 "gpc_reg_operand" "")))]
6157 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6158 "")
6160 (define_insn "*adddf3_fpr"
6161 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6162 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6163 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6164 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6165 && !VECTOR_UNIT_VSX_P (DFmode)"
6166 "{fa|fadd} %0,%1,%2"
6167 [(set_attr "type" "fp")
6168 (set_attr "fp_type" "fp_addsub_d")])
6170 (define_expand "subdf3"
6171 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6172 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6173 (match_operand:DF 2 "gpc_reg_operand" "")))]
6174 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6175 "")
6177 (define_insn "*subdf3_fpr"
6178 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6179 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6180 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6181 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6182 && !VECTOR_UNIT_VSX_P (DFmode)"
6183 "{fs|fsub} %0,%1,%2"
6184 [(set_attr "type" "fp")
6185 (set_attr "fp_type" "fp_addsub_d")])
6187 (define_expand "muldf3"
6188 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6189 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
6190 (match_operand:DF 2 "gpc_reg_operand" "")))]
6191 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6192 "")
6194 (define_insn "*muldf3_fpr"
6195 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6196 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6197 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6198 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6199 && !VECTOR_UNIT_VSX_P (DFmode)"
6200 "{fm|fmul} %0,%1,%2"
6201 [(set_attr "type" "dmul")
6202 (set_attr "fp_type" "fp_mul_d")])
6204 (define_expand "divdf3"
6205 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6206 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
6207 (match_operand:DF 2 "gpc_reg_operand" "")))]
6208 "TARGET_HARD_FLOAT
6209 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
6210 && !TARGET_SIMPLE_FPU"
6211 "")
6213 (define_insn "*divdf3_fpr"
6214 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6215 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6216 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6217 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
6218 && !VECTOR_UNIT_VSX_P (DFmode)"
6219 "{fd|fdiv} %0,%1,%2"
6220 [(set_attr "type" "ddiv")])
6222 (define_expand "recipdf3"
6223 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6224 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")
6225 (match_operand:DF 2 "gpc_reg_operand" "d")]
6226 UNSPEC_FRES))]
6227 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
6228 && flag_finite_math_only && !flag_trapping_math"
6229 {
6230 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
6231 DONE;
6232 })
6234 (define_expand "fred"
6235 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6236 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRES))]
6237 "(TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)) && flag_finite_math_only"
6238 "")
6240 (define_insn "*fred_fpr"
6241 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6242 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
6243 "TARGET_POPCNTB && flag_finite_math_only && !VECTOR_UNIT_VSX_P (DFmode)"
6244 "fre %0,%1"
6245 [(set_attr "type" "fp")])
6247 (define_insn "*fmadddf4_fpr"
6248 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6249 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6250 (match_operand:DF 2 "gpc_reg_operand" "d"))
6251 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6252 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6253 && VECTOR_UNIT_NONE_P (DFmode)"
6254 "{fma|fmadd} %0,%1,%2,%3"
6255 [(set_attr "type" "dmul")
6256 (set_attr "fp_type" "fp_maddsub_d")])
6258 (define_insn "*fmsubdf4_fpr"
6259 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6260 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6261 (match_operand:DF 2 "gpc_reg_operand" "d"))
6262 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6263 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6264 && VECTOR_UNIT_NONE_P (DFmode)"
6265 "{fms|fmsub} %0,%1,%2,%3"
6266 [(set_attr "type" "dmul")
6267 (set_attr "fp_type" "fp_maddsub_d")])
6269 (define_insn "*fnmadddf4_fpr_1"
6270 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6271 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6272 (match_operand:DF 2 "gpc_reg_operand" "d"))
6273 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6274 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6275 && VECTOR_UNIT_NONE_P (DFmode)"
6276 "{fnma|fnmadd} %0,%1,%2,%3"
6277 [(set_attr "type" "dmul")
6278 (set_attr "fp_type" "fp_maddsub_d")])
6280 (define_insn "*fnmadddf4_fpr_2"
6281 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6282 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d"))
6283 (match_operand:DF 2 "gpc_reg_operand" "d"))
6284 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6285 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6286 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6287 "{fnma|fnmadd} %0,%1,%2,%3"
6288 [(set_attr "type" "dmul")
6289 (set_attr "fp_type" "fp_maddsub_d")])
6291 (define_insn "*fnmsubdf4_fpr_1"
6292 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6293 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6294 (match_operand:DF 2 "gpc_reg_operand" "d"))
6295 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6296 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6297 && VECTOR_UNIT_NONE_P (DFmode)"
6298 "{fnms|fnmsub} %0,%1,%2,%3"
6299 [(set_attr "type" "dmul")
6300 (set_attr "fp_type" "fp_maddsub_d")])
6302 (define_insn "*fnmsubdf4_fpr_2"
6303 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6304 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d")
6305 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6306 (match_operand:DF 2 "gpc_reg_operand" "d"))))]
6307 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6308 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6309 "{fnms|fnmsub} %0,%1,%2,%3"
6310 [(set_attr "type" "dmul")
6311 (set_attr "fp_type" "fp_maddsub_d")])
6313 (define_expand "sqrtdf2"
6314 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6315 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6316 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6317 && TARGET_DOUBLE_FLOAT"
6318 "")
6320 (define_insn "*sqrtdf2_fpr"
6321 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6322 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6323 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6324 && TARGET_DOUBLE_FLOAT
6325 && !VECTOR_UNIT_VSX_P (DFmode)"
6326 "fsqrt %0,%1"
6327 [(set_attr "type" "dsqrt")])
6329 ;; The conditional move instructions allow us to perform max and min
6330 ;; operations even when
6332 (define_expand "smaxdf3"
6333 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6334 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6335 (match_operand:DF 2 "gpc_reg_operand" ""))
6336 (match_dup 1)
6337 (match_dup 2)))]
6338 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6339 && !flag_trapping_math"
6340 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6342 (define_expand "smindf3"
6343 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6344 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6345 (match_operand:DF 2 "gpc_reg_operand" ""))
6346 (match_dup 2)
6347 (match_dup 1)))]
6348 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6349 && !flag_trapping_math"
6350 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6352 (define_split
6353 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6354 (match_operator:DF 3 "min_max_operator"
6355 [(match_operand:DF 1 "gpc_reg_operand" "")
6356 (match_operand:DF 2 "gpc_reg_operand" "")]))]
6357 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6358 && !flag_trapping_math"
6359 [(const_int 0)]
6360 "
6361 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6362 operands[1], operands[2]);
6363 DONE;
6364 }")
6366 (define_expand "movdfcc"
6367 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6368 (if_then_else:DF (match_operand 1 "comparison_operator" "")
6369 (match_operand:DF 2 "gpc_reg_operand" "")
6370 (match_operand:DF 3 "gpc_reg_operand" "")))]
6371 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6372 "
6373 {
6374 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6375 DONE;
6376 else
6377 FAIL;
6378 }")
6380 (define_insn "*fseldfdf4"
6381 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6382 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6383 (match_operand:DF 4 "zero_fp_constant" "F"))
6384 (match_operand:DF 2 "gpc_reg_operand" "d")
6385 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6386 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6387 "fsel %0,%1,%2,%3"
6388 [(set_attr "type" "fp")])
6390 (define_insn "*fselsfdf4"
6391 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6392 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6393 (match_operand:SF 4 "zero_fp_constant" "F"))
6394 (match_operand:DF 2 "gpc_reg_operand" "d")
6395 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6396 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6397 "fsel %0,%1,%2,%3"
6398 [(set_attr "type" "fp")])
6399 \f
6400 ;; Conversions to and from floating-point.
6402 (define_expand "fixuns_truncsfsi2"
6403 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6404 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6405 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6406 "")
6408 (define_expand "fix_truncsfsi2"
6409 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6410 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6411 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6412 "")
6414 (define_expand "fixuns_truncdfsi2"
6415 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6416 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
6417 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
6418 "")
6420 (define_expand "fixuns_truncdfdi2"
6421 [(set (match_operand:DI 0 "register_operand" "")
6422 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
6423 "TARGET_HARD_FLOAT && TARGET_VSX"
6424 "")
6426 ; For each of these conversions, there is a define_expand, a define_insn
6427 ; with a '#' template, and a define_split (with C code). The idea is
6428 ; to allow constant folding with the template of the define_insn,
6429 ; then to have the insns split later (between sched1 and final).
6431 (define_expand "floatsidf2"
6432 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6433 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6434 (use (match_dup 2))
6435 (use (match_dup 3))
6436 (clobber (match_dup 4))
6437 (clobber (match_dup 5))
6438 (clobber (match_dup 6))])]
6439 "TARGET_HARD_FLOAT
6440 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6441 "
6442 {
6443 if (TARGET_E500_DOUBLE)
6444 {
6445 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
6446 DONE;
6447 }
6448 if (TARGET_POWERPC64)
6449 {
6450 rtx x = convert_to_mode (DImode, operands[1], 0);
6451 emit_insn (gen_floatdidf2 (operands[0], x));
6452 DONE;
6453 }
6455 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6456 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
6457 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6458 operands[5] = gen_reg_rtx (DFmode);
6459 operands[6] = gen_reg_rtx (SImode);
6460 }")
6462 (define_insn_and_split "*floatsidf2_internal"
6463 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6464 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6465 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6466 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6467 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6468 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6469 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
6470 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6471 "#"
6472 ""
6473 [(pc)]
6474 "
6475 {
6476 rtx lowword, highword;
6477 gcc_assert (MEM_P (operands[4]));
6478 highword = adjust_address (operands[4], SImode, 0);
6479 lowword = adjust_address (operands[4], SImode, 4);
6480 if (! WORDS_BIG_ENDIAN)
6481 {
6482 rtx tmp;
6483 tmp = highword; highword = lowword; lowword = tmp;
6484 }
6486 emit_insn (gen_xorsi3 (operands[6], operands[1],
6487 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
6488 emit_move_insn (lowword, operands[6]);
6489 emit_move_insn (highword, operands[2]);
6490 emit_move_insn (operands[5], operands[4]);
6491 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6492 DONE;
6493 }"
6494 [(set_attr "length" "24")])
6496 (define_expand "floatunssisf2"
6497 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6498 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6499 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6500 "")
6502 (define_expand "floatunssidf2"
6503 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6504 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6505 (use (match_dup 2))
6506 (use (match_dup 3))
6507 (clobber (match_dup 4))
6508 (clobber (match_dup 5))])]
6509 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6510 "
6511 {
6512 if (TARGET_E500_DOUBLE)
6513 {
6514 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6515 DONE;
6516 }
6517 if (TARGET_POWERPC64)
6518 {
6519 rtx x = convert_to_mode (DImode, operands[1], 1);
6520 emit_insn (gen_floatdidf2 (operands[0], x));
6521 DONE;
6522 }
6524 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6525 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6526 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6527 operands[5] = gen_reg_rtx (DFmode);
6528 }")
6530 (define_insn_and_split "*floatunssidf2_internal"
6531 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6532 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6533 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6534 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6535 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6536 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6537 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6538 "#"
6539 ""
6540 [(pc)]
6541 "
6542 {
6543 rtx lowword, highword;
6544 gcc_assert (MEM_P (operands[4]));
6545 highword = adjust_address (operands[4], SImode, 0);
6546 lowword = adjust_address (operands[4], SImode, 4);
6547 if (! WORDS_BIG_ENDIAN)
6548 {
6549 rtx tmp;
6550 tmp = highword; highword = lowword; lowword = tmp;
6551 }
6553 emit_move_insn (lowword, operands[1]);
6554 emit_move_insn (highword, operands[2]);
6555 emit_move_insn (operands[5], operands[4]);
6556 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6557 DONE;
6558 }"
6559 [(set_attr "length" "20")])
6561 (define_expand "fix_truncdfsi2"
6562 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
6563 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
6564 (clobber (match_dup 2))
6565 (clobber (match_dup 3))])]
6566 "(TARGET_POWER2 || TARGET_POWERPC)
6567 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6568 "
6569 {
6570 if (TARGET_E500_DOUBLE)
6571 {
6572 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
6573 DONE;
6574 }
6575 operands[2] = gen_reg_rtx (DImode);
6576 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6577 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
6578 {
6579 operands[3] = gen_reg_rtx (DImode);
6580 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
6581 operands[2], operands[3]));
6582 DONE;
6583 }
6584 if (TARGET_PPC_GFXOPT)
6585 {
6586 rtx orig_dest = operands[0];
6587 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
6588 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
6589 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
6590 operands[2]));
6591 if (operands[0] != orig_dest)
6592 emit_move_insn (orig_dest, operands[0]);
6593 DONE;
6594 }
6595 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6596 }")
6598 (define_insn_and_split "*fix_truncdfsi2_internal"
6599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6600 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6601 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6602 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6603 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6604 && TARGET_DOUBLE_FLOAT"
6605 "#"
6606 ""
6607 [(pc)]
6608 "
6609 {
6610 rtx lowword;
6611 gcc_assert (MEM_P (operands[3]));
6612 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6614 emit_insn (gen_fctiwz (operands[2], operands[1]));
6615 emit_move_insn (operands[3], operands[2]);
6616 emit_move_insn (operands[0], lowword);
6617 DONE;
6618 }"
6619 [(set_attr "length" "16")])
6621 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6622 [(set (match_operand:SI 0 "memory_operand" "=Z")
6623 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6624 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))]
6625 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6626 && TARGET_DOUBLE_FLOAT
6627 && TARGET_PPC_GFXOPT"
6628 "#"
6629 "&& 1"
6630 [(pc)]
6631 "
6632 {
6633 emit_insn (gen_fctiwz (operands[2], operands[1]));
6634 emit_insn (gen_stfiwx (operands[0], operands[2]));
6635 DONE;
6636 }"
6637 [(set_attr "length" "16")])
6639 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6641 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6642 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6643 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6644 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6645 && TARGET_DOUBLE_FLOAT"
6646 "#"
6647 "&& 1"
6648 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6649 (set (match_dup 3) (match_dup 2))
6650 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6651 ""
6652 [(set_attr "length" "12")])
6654 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6655 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6656 ; because the first makes it clear that operand 0 is not live
6657 ; before the instruction.
6658 (define_insn "fctiwz"
6659 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6660 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))]
6661 UNSPEC_FCTIWZ))]
6662 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6663 && TARGET_DOUBLE_FLOAT"
6664 "{fcirz|fctiwz} %0,%1"
6665 [(set_attr "type" "fp")])
6667 (define_expand "btruncdf2"
6668 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6669 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIZ))]
6670 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6671 "")
6673 (define_insn "*btruncdf2_fpr"
6674 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6675 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6676 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6677 && !VECTOR_UNIT_VSX_P (DFmode)"
6678 "friz %0,%1"
6679 [(set_attr "type" "fp")])
6681 (define_insn "btruncsf2"
6682 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6683 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6684 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6685 "friz %0,%1"
6686 [(set_attr "type" "fp")])
6688 (define_expand "ceildf2"
6689 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6690 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIP))]
6691 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6692 "")
6694 (define_insn "*ceildf2_fpr"
6695 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6696 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIP))]
6697 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6698 && !VECTOR_UNIT_VSX_P (DFmode)"
6699 "frip %0,%1"
6700 [(set_attr "type" "fp")])
6702 (define_insn "ceilsf2"
6703 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6704 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6705 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6706 "frip %0,%1"
6707 [(set_attr "type" "fp")])
6709 (define_expand "floordf2"
6710 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6711 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIM))]
6712 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6713 "")
6715 (define_insn "*floordf2_fpr"
6716 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6717 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIM))]
6718 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6719 && !VECTOR_UNIT_VSX_P (DFmode)"
6720 "frim %0,%1"
6721 [(set_attr "type" "fp")])
6723 (define_insn "floorsf2"
6724 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6725 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6726 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6727 "frim %0,%1"
6728 [(set_attr "type" "fp")])
6730 ;; No VSX equivalent to frin
6731 (define_insn "rounddf2"
6732 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6733 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIN))]
6734 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6735 "frin %0,%1"
6736 [(set_attr "type" "fp")])
6738 (define_insn "roundsf2"
6739 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6740 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6741 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6742 "frin %0,%1"
6743 [(set_attr "type" "fp")])
6745 (define_expand "ftruncdf2"
6746 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6747 (fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6748 "VECTOR_UNIT_VSX_P (DFmode)"
6749 "")
6751 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6752 (define_insn "stfiwx"
6753 [(set (match_operand:SI 0 "memory_operand" "=Z")
6754 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6755 UNSPEC_STFIWX))]
6756 "TARGET_PPC_GFXOPT"
6757 "stfiwx %1,%y0"
6758 [(set_attr "type" "fpstore")])
6760 (define_expand "floatsisf2"
6761 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6762 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6763 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6764 "")
6766 (define_expand "floatdidf2"
6767 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6768 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6769 "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6770 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6771 "")
6773 (define_insn "*floatdidf2_fpr"
6774 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6775 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))]
6776 "(TARGET_POWERPC64 || TARGET_XILINX_FPU)
6777 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6778 && !VECTOR_UNIT_VSX_P (DFmode)"
6779 "fcfid %0,%1"
6780 [(set_attr "type" "fp")])
6782 (define_expand "floatunsdidf2"
6783 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6784 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6785 "TARGET_VSX"
6786 "")
6788 (define_expand "fix_truncdfdi2"
6789 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6790 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "")))]
6791 "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6792 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6793 "")
6795 (define_insn "*fix_truncdfdi2_fpr"
6796 [(set (match_operand:DI 0 "gpc_reg_operand" "=!d#r")
6797 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d")))]
6798 "(TARGET_POWERPC64 || TARGET_XILINX_FPU)
6799 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6800 && !VECTOR_UNIT_VSX_P (DFmode)"
6801 "fctidz %0,%1"
6802 [(set_attr "type" "fp")])
6804 (define_expand "floatdisf2"
6805 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6806 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6807 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6808 "
6809 {
6810 rtx val = operands[1];
6811 if (!flag_unsafe_math_optimizations)
6812 {
6813 rtx label = gen_label_rtx ();
6814 val = gen_reg_rtx (DImode);
6815 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6816 emit_label (label);
6817 }
6818 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6819 DONE;
6820 }")
6822 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6823 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6824 ;; from double rounding.
6825 (define_insn_and_split "floatdisf2_internal1"
6826 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6827 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))
6828 (clobber (match_scratch:DF 2 "=d"))]
6829 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6830 "#"
6831 "&& reload_completed"
6832 [(set (match_dup 2)
6833 (float:DF (match_dup 1)))
6834 (set (match_dup 0)
6835 (float_truncate:SF (match_dup 2)))]
6836 "")
6838 ;; Twiddles bits to avoid double rounding.
6839 ;; Bits that might be truncated when converting to DFmode are replaced
6840 ;; by a bit that won't be lost at that stage, but is below the SFmode
6841 ;; rounding position.
6842 (define_expand "floatdisf2_internal2"
6843 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6844 (const_int 53)))
6845 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6846 (const_int 2047)))
6847 (clobber (scratch:CC))])
6848 (set (match_dup 3) (plus:DI (match_dup 3)
6849 (const_int 1)))
6850 (set (match_dup 0) (plus:DI (match_dup 0)
6851 (const_int 2047)))
6852 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6853 (const_int 2)))
6854 (set (match_dup 0) (ior:DI (match_dup 0)
6855 (match_dup 1)))
6856 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6857 (const_int -2048)))
6858 (clobber (scratch:CC))])
6859 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6860 (label_ref (match_operand:DI 2 "" ""))
6861 (pc)))
6862 (set (match_dup 0) (match_dup 1))]
6863 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6864 "
6865 {
6866 operands[3] = gen_reg_rtx (DImode);
6867 operands[4] = gen_reg_rtx (CCUNSmode);
6868 }")
6869 \f
6870 ;; Define the DImode operations that can be done in a small number
6871 ;; of instructions. The & constraints are to prevent the register
6872 ;; allocator from allocating registers that overlap with the inputs
6873 ;; (for example, having an input in 7,8 and an output in 6,7). We
6874 ;; also allow for the output being the same as one of the inputs.
6876 (define_insn "*adddi3_noppc64"
6877 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6878 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6879 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6880 "! TARGET_POWERPC64"
6881 "*
6882 {
6883 if (WORDS_BIG_ENDIAN)
6884 return (GET_CODE (operands[2])) != CONST_INT
6885 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6886 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6887 else
6888 return (GET_CODE (operands[2])) != CONST_INT
6889 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6890 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6891 }"
6892 [(set_attr "type" "two")
6893 (set_attr "length" "8")])
6895 (define_insn "*subdi3_noppc64"
6896 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6897 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6898 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6899 "! TARGET_POWERPC64"
6900 "*
6901 {
6902 if (WORDS_BIG_ENDIAN)
6903 return (GET_CODE (operands[1]) != CONST_INT)
6904 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6905 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6906 else
6907 return (GET_CODE (operands[1]) != CONST_INT)
6908 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6909 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6910 }"
6911 [(set_attr "type" "two")
6912 (set_attr "length" "8")])
6914 (define_insn "*negdi2_noppc64"
6915 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6916 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6917 "! TARGET_POWERPC64"
6918 "*
6919 {
6920 return (WORDS_BIG_ENDIAN)
6921 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6922 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6923 }"
6924 [(set_attr "type" "two")
6925 (set_attr "length" "8")])
6927 (define_expand "mulsidi3"
6928 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6929 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6930 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6931 "! TARGET_POWERPC64"
6932 "
6933 {
6934 if (! TARGET_POWER && ! TARGET_POWERPC)
6935 {
6936 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6937 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6938 emit_insn (gen_mull_call ());
6939 if (WORDS_BIG_ENDIAN)
6940 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6941 else
6942 {
6943 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6944 gen_rtx_REG (SImode, 3));
6945 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6946 gen_rtx_REG (SImode, 4));
6947 }
6948 DONE;
6949 }
6950 else if (TARGET_POWER)
6951 {
6952 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6953 DONE;
6954 }
6955 }")
6957 (define_insn "mulsidi3_mq"
6958 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6959 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6960 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6961 (clobber (match_scratch:SI 3 "=q"))]
6962 "TARGET_POWER"
6963 "mul %0,%1,%2\;mfmq %L0"
6964 [(set_attr "type" "imul")
6965 (set_attr "length" "8")])
6967 (define_insn "*mulsidi3_no_mq"
6968 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6969 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6970 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6971 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6972 "*
6973 {
6974 return (WORDS_BIG_ENDIAN)
6975 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6976 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6977 }"
6978 [(set_attr "type" "imul")
6979 (set_attr "length" "8")])
6981 (define_split
6982 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6983 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6984 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6985 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6986 [(set (match_dup 3)
6987 (truncate:SI
6988 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6989 (sign_extend:DI (match_dup 2)))
6990 (const_int 32))))
6991 (set (match_dup 4)
6992 (mult:SI (match_dup 1)
6993 (match_dup 2)))]
6994 "
6995 {
6996 int endian = (WORDS_BIG_ENDIAN == 0);
6997 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6998 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6999 }")
7001 (define_expand "umulsidi3"
7002 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7003 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7004 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7005 "TARGET_POWERPC && ! TARGET_POWERPC64"
7006 "
7007 {
7008 if (TARGET_POWER)
7009 {
7010 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
7011 DONE;
7012 }
7013 }")
7015 (define_insn "umulsidi3_mq"
7016 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7017 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7018 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7019 (clobber (match_scratch:SI 3 "=q"))]
7020 "TARGET_POWERPC && TARGET_POWER"
7021 "*
7022 {
7023 return (WORDS_BIG_ENDIAN)
7024 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7025 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7026 }"
7027 [(set_attr "type" "imul")
7028 (set_attr "length" "8")])
7030 (define_insn "*umulsidi3_no_mq"
7031 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7032 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7033 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7034 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7035 "*
7036 {
7037 return (WORDS_BIG_ENDIAN)
7038 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7039 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7040 }"
7041 [(set_attr "type" "imul")
7042 (set_attr "length" "8")])
7044 (define_split
7045 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7046 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7047 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7048 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7049 [(set (match_dup 3)
7050 (truncate:SI
7051 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
7052 (zero_extend:DI (match_dup 2)))
7053 (const_int 32))))
7054 (set (match_dup 4)
7055 (mult:SI (match_dup 1)
7056 (match_dup 2)))]
7057 "
7058 {
7059 int endian = (WORDS_BIG_ENDIAN == 0);
7060 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7061 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7062 }")
7064 (define_expand "smulsi3_highpart"
7065 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7066 (truncate:SI
7067 (lshiftrt:DI (mult:DI (sign_extend:DI
7068 (match_operand:SI 1 "gpc_reg_operand" ""))
7069 (sign_extend:DI
7070 (match_operand:SI 2 "gpc_reg_operand" "")))
7071 (const_int 32))))]
7072 ""
7073 "
7074 {
7075 if (! TARGET_POWER && ! TARGET_POWERPC)
7076 {
7077 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7078 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7079 emit_insn (gen_mulh_call ());
7080 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
7081 DONE;
7082 }
7083 else if (TARGET_POWER)
7084 {
7085 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7086 DONE;
7087 }
7088 }")
7090 (define_insn "smulsi3_highpart_mq"
7091 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7092 (truncate:SI
7093 (lshiftrt:DI (mult:DI (sign_extend:DI
7094 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7095 (sign_extend:DI
7096 (match_operand:SI 2 "gpc_reg_operand" "r")))
7097 (const_int 32))))
7098 (clobber (match_scratch:SI 3 "=q"))]
7099 "TARGET_POWER"
7100 "mul %0,%1,%2"
7101 [(set_attr "type" "imul")])
7103 (define_insn "*smulsi3_highpart_no_mq"
7104 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7105 (truncate:SI
7106 (lshiftrt:DI (mult:DI (sign_extend:DI
7107 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7108 (sign_extend:DI
7109 (match_operand:SI 2 "gpc_reg_operand" "r")))
7110 (const_int 32))))]
7111 "TARGET_POWERPC && ! TARGET_POWER"
7112 "mulhw %0,%1,%2"
7113 [(set_attr "type" "imul")])
7115 (define_expand "umulsi3_highpart"
7116 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7117 (truncate:SI
7118 (lshiftrt:DI (mult:DI (zero_extend:DI
7119 (match_operand:SI 1 "gpc_reg_operand" ""))
7120 (zero_extend:DI
7121 (match_operand:SI 2 "gpc_reg_operand" "")))
7122 (const_int 32))))]
7123 "TARGET_POWERPC"
7124 "
7125 {
7126 if (TARGET_POWER)
7127 {
7128 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7129 DONE;
7130 }
7131 }")
7133 (define_insn "umulsi3_highpart_mq"
7134 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7135 (truncate:SI
7136 (lshiftrt:DI (mult:DI (zero_extend:DI
7137 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7138 (zero_extend:DI
7139 (match_operand:SI 2 "gpc_reg_operand" "r")))
7140 (const_int 32))))
7141 (clobber (match_scratch:SI 3 "=q"))]
7142 "TARGET_POWERPC && TARGET_POWER"
7143 "mulhwu %0,%1,%2"
7144 [(set_attr "type" "imul")])
7146 (define_insn "*umulsi3_highpart_no_mq"
7147 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7148 (truncate:SI
7149 (lshiftrt:DI (mult:DI (zero_extend:DI
7150 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7151 (zero_extend:DI
7152 (match_operand:SI 2 "gpc_reg_operand" "r")))
7153 (const_int 32))))]
7154 "TARGET_POWERPC && ! TARGET_POWER"
7155 "mulhwu %0,%1,%2"
7156 [(set_attr "type" "imul")])
7158 ;; If operands 0 and 2 are in the same register, we have a problem. But
7159 ;; operands 0 and 1 (the usual case) can be in the same register. That's
7160 ;; why we have the strange constraints below.
7161 (define_insn "ashldi3_power"
7162 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7163 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7164 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7165 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7166 "TARGET_POWER"
7167 "@
7168 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
7169 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7170 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7171 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
7172 [(set_attr "length" "8")])
7174 (define_insn "lshrdi3_power"
7175 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7176 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7177 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7178 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7179 "TARGET_POWER"
7180 "@
7181 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
7182 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7183 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7184 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
7185 [(set_attr "length" "8")])
7187 ;; Shift by a variable amount is too complex to be worth open-coding. We
7188 ;; just handle shifts by constants.
7189 (define_insn "ashrdi3_power"
7190 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7191 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7192 (match_operand:SI 2 "const_int_operand" "M,i")))
7193 (clobber (match_scratch:SI 3 "=X,q"))]
7194 "TARGET_POWER"
7195 "@
7196 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7197 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
7198 [(set_attr "type" "shift")
7199 (set_attr "length" "8")])
7201 (define_insn "ashrdi3_no_power"
7202 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
7203 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7204 (match_operand:SI 2 "const_int_operand" "M,i")))]
7205 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
7206 "@
7207 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7208 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
7209 [(set_attr "type" "two,three")
7210 (set_attr "length" "8,12")])
7212 (define_insn "*ashrdisi3_noppc64"
7213 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7214 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7215 (const_int 32)) 4))]
7216 "TARGET_32BIT && !TARGET_POWERPC64"
7217 "*
7218 {
7219 if (REGNO (operands[0]) == REGNO (operands[1]))
7220 return \"\";
7221 else
7222 return \"mr %0,%1\";
7223 }"
7224 [(set_attr "length" "4")])
7226 \f
7227 ;; PowerPC64 DImode operations.
7229 (define_expand "absdi2"
7230 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7231 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
7232 "TARGET_POWERPC64"
7233 "
7234 {
7235 if (TARGET_ISEL)
7236 emit_insn (gen_absdi2_isel (operands[0], operands[1]));
7237 else
7238 emit_insn (gen_absdi2_internal (operands[0], operands[1]));
7239 DONE;
7240 }")
7242 (define_insn_and_split "absdi2_internal"
7243 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7244 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
7245 (clobber (match_scratch:DI 2 "=&r,&r"))]
7246 "TARGET_POWERPC64 && !TARGET_ISEL"
7247 "#"
7248 "&& reload_completed"
7249 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7250 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7251 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
7252 "")
7254 (define_insn_and_split "*nabsdi2"
7255 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7256 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
7257 (clobber (match_scratch:DI 2 "=&r,&r"))]
7258 "TARGET_POWERPC64 && !TARGET_ISEL"
7259 "#"
7260 "&& reload_completed"
7261 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7262 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7263 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7264 "")
7266 (define_insn "muldi3"
7267 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7268 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7269 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
7270 "TARGET_POWERPC64"
7271 "@
7272 mulld %0,%1,%2
7273 mulli %0,%1,%2"
7274 [(set (attr "type")
7275 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
7276 (const_string "imul3")
7277 (match_operand:SI 2 "short_cint_operand" "")
7278 (const_string "imul2")]
7279 (const_string "lmul")))])
7281 (define_insn "*muldi3_internal1"
7282 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7283 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7284 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7285 (const_int 0)))
7286 (clobber (match_scratch:DI 3 "=r,r"))]
7287 "TARGET_POWERPC64"
7288 "@
7289 mulld. %3,%1,%2
7290 #"
7291 [(set_attr "type" "lmul_compare")
7292 (set_attr "length" "4,8")])
7294 (define_split
7295 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7296 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7297 (match_operand:DI 2 "gpc_reg_operand" ""))
7298 (const_int 0)))
7299 (clobber (match_scratch:DI 3 ""))]
7300 "TARGET_POWERPC64 && reload_completed"
7301 [(set (match_dup 3)
7302 (mult:DI (match_dup 1) (match_dup 2)))
7303 (set (match_dup 0)
7304 (compare:CC (match_dup 3)
7305 (const_int 0)))]
7306 "")
7308 (define_insn "*muldi3_internal2"
7309 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7310 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7311 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7312 (const_int 0)))
7313 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7314 (mult:DI (match_dup 1) (match_dup 2)))]
7315 "TARGET_POWERPC64"
7316 "@
7317 mulld. %0,%1,%2
7318 #"
7319 [(set_attr "type" "lmul_compare")
7320 (set_attr "length" "4,8")])
7322 (define_split
7323 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7324 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7325 (match_operand:DI 2 "gpc_reg_operand" ""))
7326 (const_int 0)))
7327 (set (match_operand:DI 0 "gpc_reg_operand" "")
7328 (mult:DI (match_dup 1) (match_dup 2)))]
7329 "TARGET_POWERPC64 && reload_completed"
7330 [(set (match_dup 0)
7331 (mult:DI (match_dup 1) (match_dup 2)))
7332 (set (match_dup 3)
7333 (compare:CC (match_dup 0)
7334 (const_int 0)))]
7335 "")
7337 (define_insn "smuldi3_highpart"
7338 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7339 (truncate:DI
7340 (lshiftrt:TI (mult:TI (sign_extend:TI
7341 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7342 (sign_extend:TI
7343 (match_operand:DI 2 "gpc_reg_operand" "r")))
7344 (const_int 64))))]
7345 "TARGET_POWERPC64"
7346 "mulhd %0,%1,%2"
7347 [(set_attr "type" "lmul")])
7349 (define_insn "umuldi3_highpart"
7350 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7351 (truncate:DI
7352 (lshiftrt:TI (mult:TI (zero_extend:TI
7353 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7354 (zero_extend:TI
7355 (match_operand:DI 2 "gpc_reg_operand" "r")))
7356 (const_int 64))))]
7357 "TARGET_POWERPC64"
7358 "mulhdu %0,%1,%2"
7359 [(set_attr "type" "lmul")])
7361 (define_insn "rotldi3"
7362 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7363 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7364 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7365 "TARGET_POWERPC64"
7366 "@
7367 rldcl %0,%1,%2,0
7368 rldicl %0,%1,%H2,0"
7369 [(set_attr "type" "var_shift_rotate,integer")])
7371 (define_insn "*rotldi3_internal2"
7372 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7373 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7374 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7375 (const_int 0)))
7376 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7377 "TARGET_64BIT"
7378 "@
7379 rldcl. %3,%1,%2,0
7380 rldicl. %3,%1,%H2,0
7381 #
7382 #"
7383 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7384 (set_attr "length" "4,4,8,8")])
7386 (define_split
7387 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7388 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7389 (match_operand:DI 2 "reg_or_cint_operand" ""))
7390 (const_int 0)))
7391 (clobber (match_scratch:DI 3 ""))]
7392 "TARGET_POWERPC64 && reload_completed"
7393 [(set (match_dup 3)
7394 (rotate:DI (match_dup 1) (match_dup 2)))
7395 (set (match_dup 0)
7396 (compare:CC (match_dup 3)
7397 (const_int 0)))]
7398 "")
7400 (define_insn "*rotldi3_internal3"
7401 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7402 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7403 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7404 (const_int 0)))
7405 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7406 (rotate:DI (match_dup 1) (match_dup 2)))]
7407 "TARGET_64BIT"
7408 "@
7409 rldcl. %0,%1,%2,0
7410 rldicl. %0,%1,%H2,0
7411 #
7412 #"
7413 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7414 (set_attr "length" "4,4,8,8")])
7416 (define_split
7417 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7418 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7419 (match_operand:DI 2 "reg_or_cint_operand" ""))
7420 (const_int 0)))
7421 (set (match_operand:DI 0 "gpc_reg_operand" "")
7422 (rotate:DI (match_dup 1) (match_dup 2)))]
7423 "TARGET_POWERPC64 && reload_completed"
7424 [(set (match_dup 0)
7425 (rotate:DI (match_dup 1) (match_dup 2)))
7426 (set (match_dup 3)
7427 (compare:CC (match_dup 0)
7428 (const_int 0)))]
7429 "")
7431 (define_insn "*rotldi3_internal4"
7432 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7433 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7434 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7435 (match_operand:DI 3 "mask64_operand" "n,n")))]
7436 "TARGET_POWERPC64"
7437 "@
7438 rldc%B3 %0,%1,%2,%S3
7439 rldic%B3 %0,%1,%H2,%S3"
7440 [(set_attr "type" "var_shift_rotate,integer")])
7442 (define_insn "*rotldi3_internal5"
7443 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7444 (compare:CC (and:DI
7445 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7446 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7447 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7448 (const_int 0)))
7449 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7450 "TARGET_64BIT"
7451 "@
7452 rldc%B3. %4,%1,%2,%S3
7453 rldic%B3. %4,%1,%H2,%S3
7454 #
7455 #"
7456 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7457 (set_attr "length" "4,4,8,8")])
7459 (define_split
7460 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7461 (compare:CC (and:DI
7462 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7463 (match_operand:DI 2 "reg_or_cint_operand" ""))
7464 (match_operand:DI 3 "mask64_operand" ""))
7465 (const_int 0)))
7466 (clobber (match_scratch:DI 4 ""))]
7467 "TARGET_POWERPC64 && reload_completed"
7468 [(set (match_dup 4)
7469 (and:DI (rotate:DI (match_dup 1)
7470 (match_dup 2))
7471 (match_dup 3)))
7472 (set (match_dup 0)
7473 (compare:CC (match_dup 4)
7474 (const_int 0)))]
7475 "")
7477 (define_insn "*rotldi3_internal6"
7478 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
7479 (compare:CC (and:DI
7480 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7481 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7482 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7483 (const_int 0)))
7484 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7485 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7486 "TARGET_64BIT"
7487 "@
7488 rldc%B3. %0,%1,%2,%S3
7489 rldic%B3. %0,%1,%H2,%S3
7490 #
7491 #"
7492 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7493 (set_attr "length" "4,4,8,8")])
7495 (define_split
7496 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7497 (compare:CC (and:DI
7498 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7499 (match_operand:DI 2 "reg_or_cint_operand" ""))
7500 (match_operand:DI 3 "mask64_operand" ""))
7501 (const_int 0)))
7502 (set (match_operand:DI 0 "gpc_reg_operand" "")
7503 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7504 "TARGET_POWERPC64 && reload_completed"
7505 [(set (match_dup 0)
7506 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7507 (set (match_dup 4)
7508 (compare:CC (match_dup 0)
7509 (const_int 0)))]
7510 "")
7512 (define_insn "*rotldi3_internal7"
7513 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7514 (zero_extend:DI
7515 (subreg:QI
7516 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7517 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7518 "TARGET_POWERPC64"
7519 "@
7520 rldcl %0,%1,%2,56
7521 rldicl %0,%1,%H2,56"
7522 [(set_attr "type" "var_shift_rotate,integer")])
7524 (define_insn "*rotldi3_internal8"
7525 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7526 (compare:CC (zero_extend:DI
7527 (subreg:QI
7528 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7529 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7530 (const_int 0)))
7531 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7532 "TARGET_64BIT"
7533 "@
7534 rldcl. %3,%1,%2,56
7535 rldicl. %3,%1,%H2,56
7536 #
7537 #"
7538 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7539 (set_attr "length" "4,4,8,8")])
7541 (define_split
7542 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7543 (compare:CC (zero_extend:DI
7544 (subreg:QI
7545 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7546 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7547 (const_int 0)))
7548 (clobber (match_scratch:DI 3 ""))]
7549 "TARGET_POWERPC64 && reload_completed"
7550 [(set (match_dup 3)
7551 (zero_extend:DI (subreg:QI
7552 (rotate:DI (match_dup 1)
7553 (match_dup 2)) 0)))
7554 (set (match_dup 0)
7555 (compare:CC (match_dup 3)
7556 (const_int 0)))]
7557 "")
7559 (define_insn "*rotldi3_internal9"
7560 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7561 (compare:CC (zero_extend:DI
7562 (subreg:QI
7563 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7564 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7565 (const_int 0)))
7566 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7567 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7568 "TARGET_64BIT"
7569 "@
7570 rldcl. %0,%1,%2,56
7571 rldicl. %0,%1,%H2,56
7572 #
7573 #"
7574 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7575 (set_attr "length" "4,4,8,8")])
7577 (define_split
7578 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7579 (compare:CC (zero_extend:DI
7580 (subreg:QI
7581 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7582 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7583 (const_int 0)))
7584 (set (match_operand:DI 0 "gpc_reg_operand" "")
7585 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7586 "TARGET_POWERPC64 && reload_completed"
7587 [(set (match_dup 0)
7588 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7589 (set (match_dup 3)
7590 (compare:CC (match_dup 0)
7591 (const_int 0)))]
7592 "")
7594 (define_insn "*rotldi3_internal10"
7595 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7596 (zero_extend:DI
7597 (subreg:HI
7598 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7599 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7600 "TARGET_POWERPC64"
7601 "@
7602 rldcl %0,%1,%2,48
7603 rldicl %0,%1,%H2,48"
7604 [(set_attr "type" "var_shift_rotate,integer")])
7606 (define_insn "*rotldi3_internal11"
7607 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7608 (compare:CC (zero_extend:DI
7609 (subreg:HI
7610 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7611 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7612 (const_int 0)))
7613 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7614 "TARGET_64BIT"
7615 "@
7616 rldcl. %3,%1,%2,48
7617 rldicl. %3,%1,%H2,48
7618 #
7619 #"
7620 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7621 (set_attr "length" "4,4,8,8")])
7623 (define_split
7624 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7625 (compare:CC (zero_extend:DI
7626 (subreg:HI
7627 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7628 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7629 (const_int 0)))
7630 (clobber (match_scratch:DI 3 ""))]
7631 "TARGET_POWERPC64 && reload_completed"
7632 [(set (match_dup 3)
7633 (zero_extend:DI (subreg:HI
7634 (rotate:DI (match_dup 1)
7635 (match_dup 2)) 0)))
7636 (set (match_dup 0)
7637 (compare:CC (match_dup 3)
7638 (const_int 0)))]
7639 "")
7641 (define_insn "*rotldi3_internal12"
7642 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7643 (compare:CC (zero_extend:DI
7644 (subreg:HI
7645 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7646 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7647 (const_int 0)))
7648 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7649 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7650 "TARGET_64BIT"
7651 "@
7652 rldcl. %0,%1,%2,48
7653 rldicl. %0,%1,%H2,48
7654 #
7655 #"
7656 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7657 (set_attr "length" "4,4,8,8")])
7659 (define_split
7660 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7661 (compare:CC (zero_extend:DI
7662 (subreg:HI
7663 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7664 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7665 (const_int 0)))
7666 (set (match_operand:DI 0 "gpc_reg_operand" "")
7667 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7668 "TARGET_POWERPC64 && reload_completed"
7669 [(set (match_dup 0)
7670 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7671 (set (match_dup 3)
7672 (compare:CC (match_dup 0)
7673 (const_int 0)))]
7674 "")
7676 (define_insn "*rotldi3_internal13"
7677 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7678 (zero_extend:DI
7679 (subreg:SI
7680 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7681 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7682 "TARGET_POWERPC64"
7683 "@
7684 rldcl %0,%1,%2,32
7685 rldicl %0,%1,%H2,32"
7686 [(set_attr "type" "var_shift_rotate,integer")])
7688 (define_insn "*rotldi3_internal14"
7689 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7690 (compare:CC (zero_extend:DI
7691 (subreg:SI
7692 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7693 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7694 (const_int 0)))
7695 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7696 "TARGET_64BIT"
7697 "@
7698 rldcl. %3,%1,%2,32
7699 rldicl. %3,%1,%H2,32
7700 #
7701 #"
7702 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7703 (set_attr "length" "4,4,8,8")])
7705 (define_split
7706 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7707 (compare:CC (zero_extend:DI
7708 (subreg:SI
7709 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7710 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7711 (const_int 0)))
7712 (clobber (match_scratch:DI 3 ""))]
7713 "TARGET_POWERPC64 && reload_completed"
7714 [(set (match_dup 3)
7715 (zero_extend:DI (subreg:SI
7716 (rotate:DI (match_dup 1)
7717 (match_dup 2)) 0)))
7718 (set (match_dup 0)
7719 (compare:CC (match_dup 3)
7720 (const_int 0)))]
7721 "")
7723 (define_insn "*rotldi3_internal15"
7724 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7725 (compare:CC (zero_extend:DI
7726 (subreg:SI
7727 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7728 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7729 (const_int 0)))
7730 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7731 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7732 "TARGET_64BIT"
7733 "@
7734 rldcl. %0,%1,%2,32
7735 rldicl. %0,%1,%H2,32
7736 #
7737 #"
7738 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7739 (set_attr "length" "4,4,8,8")])
7741 (define_split
7742 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7743 (compare:CC (zero_extend:DI
7744 (subreg:SI
7745 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7746 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7747 (const_int 0)))
7748 (set (match_operand:DI 0 "gpc_reg_operand" "")
7749 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7750 "TARGET_POWERPC64 && reload_completed"
7751 [(set (match_dup 0)
7752 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7753 (set (match_dup 3)
7754 (compare:CC (match_dup 0)
7755 (const_int 0)))]
7756 "")
7758 (define_expand "ashldi3"
7759 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7760 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7761 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7762 "TARGET_POWERPC64 || TARGET_POWER"
7763 "
7764 {
7765 if (TARGET_POWERPC64)
7766 ;
7767 else if (TARGET_POWER)
7768 {
7769 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7770 DONE;
7771 }
7772 else
7773 FAIL;
7774 }")
7776 (define_insn "*ashldi3_internal1"
7777 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7778 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7779 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7780 "TARGET_POWERPC64"
7781 "@
7782 sld %0,%1,%2
7783 sldi %0,%1,%H2"
7784 [(set_attr "type" "var_shift_rotate,shift")])
7786 (define_insn "*ashldi3_internal2"
7787 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7788 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7789 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7790 (const_int 0)))
7791 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7792 "TARGET_64BIT"
7793 "@
7794 sld. %3,%1,%2
7795 sldi. %3,%1,%H2
7796 #
7797 #"
7798 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7799 (set_attr "length" "4,4,8,8")])
7801 (define_split
7802 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7803 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7804 (match_operand:SI 2 "reg_or_cint_operand" ""))
7805 (const_int 0)))
7806 (clobber (match_scratch:DI 3 ""))]
7807 "TARGET_POWERPC64 && reload_completed"
7808 [(set (match_dup 3)
7809 (ashift:DI (match_dup 1) (match_dup 2)))
7810 (set (match_dup 0)
7811 (compare:CC (match_dup 3)
7812 (const_int 0)))]
7813 "")
7815 (define_insn "*ashldi3_internal3"
7816 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7817 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7818 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7819 (const_int 0)))
7820 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7821 (ashift:DI (match_dup 1) (match_dup 2)))]
7822 "TARGET_64BIT"
7823 "@
7824 sld. %0,%1,%2
7825 sldi. %0,%1,%H2
7826 #
7827 #"
7828 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7829 (set_attr "length" "4,4,8,8")])
7831 (define_split
7832 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7833 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7834 (match_operand:SI 2 "reg_or_cint_operand" ""))
7835 (const_int 0)))
7836 (set (match_operand:DI 0 "gpc_reg_operand" "")
7837 (ashift:DI (match_dup 1) (match_dup 2)))]
7838 "TARGET_POWERPC64 && reload_completed"
7839 [(set (match_dup 0)
7840 (ashift:DI (match_dup 1) (match_dup 2)))
7841 (set (match_dup 3)
7842 (compare:CC (match_dup 0)
7843 (const_int 0)))]
7844 "")
7846 (define_insn "*ashldi3_internal4"
7847 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7848 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7849 (match_operand:SI 2 "const_int_operand" "i"))
7850 (match_operand:DI 3 "const_int_operand" "n")))]
7851 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7852 "rldic %0,%1,%H2,%W3")
7854 (define_insn "ashldi3_internal5"
7855 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7856 (compare:CC
7857 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7858 (match_operand:SI 2 "const_int_operand" "i,i"))
7859 (match_operand:DI 3 "const_int_operand" "n,n"))
7860 (const_int 0)))
7861 (clobber (match_scratch:DI 4 "=r,r"))]
7862 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7863 "@
7864 rldic. %4,%1,%H2,%W3
7865 #"
7866 [(set_attr "type" "compare")
7867 (set_attr "length" "4,8")])
7869 (define_split
7870 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7871 (compare:CC
7872 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7873 (match_operand:SI 2 "const_int_operand" ""))
7874 (match_operand:DI 3 "const_int_operand" ""))
7875 (const_int 0)))
7876 (clobber (match_scratch:DI 4 ""))]
7877 "TARGET_POWERPC64 && reload_completed
7878 && includes_rldic_lshift_p (operands[2], operands[3])"
7879 [(set (match_dup 4)
7880 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7881 (match_dup 3)))
7882 (set (match_dup 0)
7883 (compare:CC (match_dup 4)
7884 (const_int 0)))]
7885 "")
7887 (define_insn "*ashldi3_internal6"
7888 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7889 (compare:CC
7890 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7891 (match_operand:SI 2 "const_int_operand" "i,i"))
7892 (match_operand:DI 3 "const_int_operand" "n,n"))
7893 (const_int 0)))
7894 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7895 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7896 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7897 "@
7898 rldic. %0,%1,%H2,%W3
7899 #"
7900 [(set_attr "type" "compare")
7901 (set_attr "length" "4,8")])
7903 (define_split
7904 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7905 (compare:CC
7906 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7907 (match_operand:SI 2 "const_int_operand" ""))
7908 (match_operand:DI 3 "const_int_operand" ""))
7909 (const_int 0)))
7910 (set (match_operand:DI 0 "gpc_reg_operand" "")
7911 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7912 "TARGET_POWERPC64 && reload_completed
7913 && includes_rldic_lshift_p (operands[2], operands[3])"
7914 [(set (match_dup 0)
7915 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7916 (match_dup 3)))
7917 (set (match_dup 4)
7918 (compare:CC (match_dup 0)
7919 (const_int 0)))]
7920 "")
7922 (define_insn "*ashldi3_internal7"
7923 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7924 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7925 (match_operand:SI 2 "const_int_operand" "i"))
7926 (match_operand:DI 3 "mask64_operand" "n")))]
7927 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7928 "rldicr %0,%1,%H2,%S3")
7930 (define_insn "ashldi3_internal8"
7931 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7932 (compare:CC
7933 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7934 (match_operand:SI 2 "const_int_operand" "i,i"))
7935 (match_operand:DI 3 "mask64_operand" "n,n"))
7936 (const_int 0)))
7937 (clobber (match_scratch:DI 4 "=r,r"))]
7938 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7939 "@
7940 rldicr. %4,%1,%H2,%S3
7941 #"
7942 [(set_attr "type" "compare")
7943 (set_attr "length" "4,8")])
7945 (define_split
7946 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7947 (compare:CC
7948 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7949 (match_operand:SI 2 "const_int_operand" ""))
7950 (match_operand:DI 3 "mask64_operand" ""))
7951 (const_int 0)))
7952 (clobber (match_scratch:DI 4 ""))]
7953 "TARGET_POWERPC64 && reload_completed
7954 && includes_rldicr_lshift_p (operands[2], operands[3])"
7955 [(set (match_dup 4)
7956 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7957 (match_dup 3)))
7958 (set (match_dup 0)
7959 (compare:CC (match_dup 4)
7960 (const_int 0)))]
7961 "")
7963 (define_insn "*ashldi3_internal9"
7964 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7965 (compare:CC
7966 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7967 (match_operand:SI 2 "const_int_operand" "i,i"))
7968 (match_operand:DI 3 "mask64_operand" "n,n"))
7969 (const_int 0)))
7970 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7971 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7972 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7973 "@
7974 rldicr. %0,%1,%H2,%S3
7975 #"
7976 [(set_attr "type" "compare")
7977 (set_attr "length" "4,8")])
7979 (define_split
7980 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7981 (compare:CC
7982 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7983 (match_operand:SI 2 "const_int_operand" ""))
7984 (match_operand:DI 3 "mask64_operand" ""))
7985 (const_int 0)))
7986 (set (match_operand:DI 0 "gpc_reg_operand" "")
7987 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7988 "TARGET_POWERPC64 && reload_completed
7989 && includes_rldicr_lshift_p (operands[2], operands[3])"
7990 [(set (match_dup 0)
7991 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7992 (match_dup 3)))
7993 (set (match_dup 4)
7994 (compare:CC (match_dup 0)
7995 (const_int 0)))]
7996 "")
7998 (define_expand "lshrdi3"
7999 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8000 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8001 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8002 "TARGET_POWERPC64 || TARGET_POWER"
8003 "
8004 {
8005 if (TARGET_POWERPC64)
8006 ;
8007 else if (TARGET_POWER)
8008 {
8009 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
8010 DONE;
8011 }
8012 else
8013 FAIL;
8014 }")
8016 (define_insn "*lshrdi3_internal1"
8017 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8018 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8019 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8020 "TARGET_POWERPC64"
8021 "@
8022 srd %0,%1,%2
8023 srdi %0,%1,%H2"
8024 [(set_attr "type" "var_shift_rotate,shift")])
8026 (define_insn "*lshrdi3_internal2"
8027 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8028 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8029 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8030 (const_int 0)))
8031 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8032 "TARGET_64BIT "
8033 "@
8034 srd. %3,%1,%2
8035 srdi. %3,%1,%H2
8036 #
8037 #"
8038 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8039 (set_attr "length" "4,4,8,8")])
8041 (define_split
8042 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8043 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8044 (match_operand:SI 2 "reg_or_cint_operand" ""))
8045 (const_int 0)))
8046 (clobber (match_scratch:DI 3 ""))]
8047 "TARGET_POWERPC64 && reload_completed"
8048 [(set (match_dup 3)
8049 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8050 (set (match_dup 0)
8051 (compare:CC (match_dup 3)
8052 (const_int 0)))]
8053 "")
8055 (define_insn "*lshrdi3_internal3"
8056 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8057 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8058 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8059 (const_int 0)))
8060 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8061 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8062 "TARGET_64BIT"
8063 "@
8064 srd. %0,%1,%2
8065 srdi. %0,%1,%H2
8066 #
8067 #"
8068 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8069 (set_attr "length" "4,4,8,8")])
8071 (define_split
8072 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8073 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8074 (match_operand:SI 2 "reg_or_cint_operand" ""))
8075 (const_int 0)))
8076 (set (match_operand:DI 0 "gpc_reg_operand" "")
8077 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8078 "TARGET_POWERPC64 && reload_completed"
8079 [(set (match_dup 0)
8080 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8081 (set (match_dup 3)
8082 (compare:CC (match_dup 0)
8083 (const_int 0)))]
8084 "")
8086 (define_expand "ashrdi3"
8087 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8088 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8089 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8090 "WORDS_BIG_ENDIAN"
8091 "
8092 {
8093 if (TARGET_POWERPC64)
8094 ;
8095 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
8096 {
8097 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
8098 DONE;
8099 }
8100 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
8101 && WORDS_BIG_ENDIAN)
8102 {
8103 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
8104 DONE;
8105 }
8106 else
8107 FAIL;
8108 }")
8110 (define_insn "*ashrdi3_internal1"
8111 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8112 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8113 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8114 "TARGET_POWERPC64"
8115 "@
8116 srad %0,%1,%2
8117 sradi %0,%1,%H2"
8118 [(set_attr "type" "var_shift_rotate,shift")])
8120 (define_insn "*ashrdi3_internal2"
8121 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8122 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8123 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8124 (const_int 0)))
8125 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8126 "TARGET_64BIT"
8127 "@
8128 srad. %3,%1,%2
8129 sradi. %3,%1,%H2
8130 #
8131 #"
8132 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8133 (set_attr "length" "4,4,8,8")])
8135 (define_split
8136 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8137 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8138 (match_operand:SI 2 "reg_or_cint_operand" ""))
8139 (const_int 0)))
8140 (clobber (match_scratch:DI 3 ""))]
8141 "TARGET_POWERPC64 && reload_completed"
8142 [(set (match_dup 3)
8143 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8144 (set (match_dup 0)
8145 (compare:CC (match_dup 3)
8146 (const_int 0)))]
8147 "")
8149 (define_insn "*ashrdi3_internal3"
8150 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8151 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8152 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8153 (const_int 0)))
8154 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8155 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8156 "TARGET_64BIT"
8157 "@
8158 srad. %0,%1,%2
8159 sradi. %0,%1,%H2
8160 #
8161 #"
8162 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8163 (set_attr "length" "4,4,8,8")])
8165 (define_split
8166 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8167 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8168 (match_operand:SI 2 "reg_or_cint_operand" ""))
8169 (const_int 0)))
8170 (set (match_operand:DI 0 "gpc_reg_operand" "")
8171 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8172 "TARGET_POWERPC64 && reload_completed"
8173 [(set (match_dup 0)
8174 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8175 (set (match_dup 3)
8176 (compare:CC (match_dup 0)
8177 (const_int 0)))]
8178 "")
8180 (define_expand "anddi3"
8181 [(parallel
8182 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8183 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8184 (match_operand:DI 2 "and64_2_operand" "")))
8185 (clobber (match_scratch:CC 3 ""))])]
8186 "TARGET_POWERPC64"
8187 "")
8189 (define_insn "anddi3_mc"
8190 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8191 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8192 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8193 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8194 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8195 "@
8196 and %0,%1,%2
8197 rldic%B2 %0,%1,0,%S2
8198 rlwinm %0,%1,0,%m2,%M2
8199 andi. %0,%1,%b2
8200 andis. %0,%1,%u2
8201 #"
8202 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8203 (set_attr "length" "4,4,4,4,4,8")])
8205 (define_insn "anddi3_nomc"
8206 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8207 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8208 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8209 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8210 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8211 "@
8212 and %0,%1,%2
8213 rldic%B2 %0,%1,0,%S2
8214 rlwinm %0,%1,0,%m2,%M2
8215 #"
8216 [(set_attr "length" "4,4,4,8")])
8218 (define_split
8219 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8220 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8221 (match_operand:DI 2 "mask64_2_operand" "")))
8222 (clobber (match_scratch:CC 3 ""))]
8223 "TARGET_POWERPC64
8224 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8225 && !mask_operand (operands[2], DImode)
8226 && !mask64_operand (operands[2], DImode)"
8227 [(set (match_dup 0)
8228 (and:DI (rotate:DI (match_dup 1)
8229 (match_dup 4))
8230 (match_dup 5)))
8231 (set (match_dup 0)
8232 (and:DI (rotate:DI (match_dup 0)
8233 (match_dup 6))
8234 (match_dup 7)))]
8235 {
8236 build_mask64_2_operands (operands[2], &operands[4]);
8237 })
8239 (define_insn "*anddi3_internal2_mc"
8240 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8241 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8242 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8243 (const_int 0)))
8244 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8245 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8246 "TARGET_64BIT && rs6000_gen_cell_microcode"
8247 "@
8248 and. %3,%1,%2
8249 rldic%B2. %3,%1,0,%S2
8250 rlwinm. %3,%1,0,%m2,%M2
8251 andi. %3,%1,%b2
8252 andis. %3,%1,%u2
8253 #
8254 #
8255 #
8256 #
8257 #
8258 #
8259 #"
8260 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8261 fast_compare,compare,compare,compare,compare,compare,\
8262 compare,compare")
8263 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8265 (define_split
8266 [(set (match_operand:CC 0 "cc_reg_operand" "")
8267 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8268 (match_operand:DI 2 "mask64_2_operand" ""))
8269 (const_int 0)))
8270 (clobber (match_scratch:DI 3 ""))
8271 (clobber (match_scratch:CC 4 ""))]
8272 "TARGET_64BIT && reload_completed
8273 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8274 && !mask_operand (operands[2], DImode)
8275 && !mask64_operand (operands[2], DImode)"
8276 [(set (match_dup 3)
8277 (and:DI (rotate:DI (match_dup 1)
8278 (match_dup 5))
8279 (match_dup 6)))
8280 (parallel [(set (match_dup 0)
8281 (compare:CC (and:DI (rotate:DI (match_dup 3)
8282 (match_dup 7))
8283 (match_dup 8))
8284 (const_int 0)))
8285 (clobber (match_dup 3))])]
8286 "
8287 {
8288 build_mask64_2_operands (operands[2], &operands[5]);
8289 }")
8291 (define_insn "*anddi3_internal3_mc"
8292 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8293 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8294 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8295 (const_int 0)))
8296 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8297 (and:DI (match_dup 1) (match_dup 2)))
8298 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8299 "TARGET_64BIT && rs6000_gen_cell_microcode"
8300 "@
8301 and. %0,%1,%2
8302 rldic%B2. %0,%1,0,%S2
8303 rlwinm. %0,%1,0,%m2,%M2
8304 andi. %0,%1,%b2
8305 andis. %0,%1,%u2
8306 #
8307 #
8308 #
8309 #
8310 #
8311 #
8312 #"
8313 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8314 fast_compare,compare,compare,compare,compare,compare,\
8315 compare,compare")
8316 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8318 (define_split
8319 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8320 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8321 (match_operand:DI 2 "and64_2_operand" ""))
8322 (const_int 0)))
8323 (set (match_operand:DI 0 "gpc_reg_operand" "")
8324 (and:DI (match_dup 1) (match_dup 2)))
8325 (clobber (match_scratch:CC 4 ""))]
8326 "TARGET_64BIT && reload_completed"
8327 [(parallel [(set (match_dup 0)
8328 (and:DI (match_dup 1) (match_dup 2)))
8329 (clobber (match_dup 4))])
8330 (set (match_dup 3)
8331 (compare:CC (match_dup 0)
8332 (const_int 0)))]
8333 "")
8335 (define_split
8336 [(set (match_operand:CC 3 "cc_reg_operand" "")
8337 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8338 (match_operand:DI 2 "mask64_2_operand" ""))
8339 (const_int 0)))
8340 (set (match_operand:DI 0 "gpc_reg_operand" "")
8341 (and:DI (match_dup 1) (match_dup 2)))
8342 (clobber (match_scratch:CC 4 ""))]
8343 "TARGET_64BIT && reload_completed
8344 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8345 && !mask_operand (operands[2], DImode)
8346 && !mask64_operand (operands[2], DImode)"
8347 [(set (match_dup 0)
8348 (and:DI (rotate:DI (match_dup 1)
8349 (match_dup 5))
8350 (match_dup 6)))
8351 (parallel [(set (match_dup 3)
8352 (compare:CC (and:DI (rotate:DI (match_dup 0)
8353 (match_dup 7))
8354 (match_dup 8))
8355 (const_int 0)))
8356 (set (match_dup 0)
8357 (and:DI (rotate:DI (match_dup 0)
8358 (match_dup 7))
8359 (match_dup 8)))])]
8360 "
8361 {
8362 build_mask64_2_operands (operands[2], &operands[5]);
8363 }")
8365 (define_expand "iordi3"
8366 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8367 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8368 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8369 "TARGET_POWERPC64"
8370 "
8371 {
8372 if (non_logical_cint_operand (operands[2], DImode))
8373 {
8374 HOST_WIDE_INT value;
8375 rtx tmp = ((!can_create_pseudo_p ()
8376 || rtx_equal_p (operands[0], operands[1]))
8377 ? operands[0] : gen_reg_rtx (DImode));
8379 if (GET_CODE (operands[2]) == CONST_INT)
8380 {
8381 value = INTVAL (operands[2]);
8382 emit_insn (gen_iordi3 (tmp, operands[1],
8383 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8384 }
8385 else
8386 {
8387 value = CONST_DOUBLE_LOW (operands[2]);
8388 emit_insn (gen_iordi3 (tmp, operands[1],
8389 immed_double_const (value
8390 & (~ (HOST_WIDE_INT) 0xffff),
8391 0, DImode)));
8392 }
8394 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8395 DONE;
8396 }
8397 }")
8399 (define_expand "xordi3"
8400 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8401 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8402 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8403 "TARGET_POWERPC64"
8404 "
8405 {
8406 if (non_logical_cint_operand (operands[2], DImode))
8407 {
8408 HOST_WIDE_INT value;
8409 rtx tmp = ((!can_create_pseudo_p ()
8410 || rtx_equal_p (operands[0], operands[1]))
8411 ? operands[0] : gen_reg_rtx (DImode));
8413 if (GET_CODE (operands[2]) == CONST_INT)
8414 {
8415 value = INTVAL (operands[2]);
8416 emit_insn (gen_xordi3 (tmp, operands[1],
8417 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8418 }
8419 else
8420 {
8421 value = CONST_DOUBLE_LOW (operands[2]);
8422 emit_insn (gen_xordi3 (tmp, operands[1],
8423 immed_double_const (value
8424 & (~ (HOST_WIDE_INT) 0xffff),
8425 0, DImode)));
8426 }
8428 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8429 DONE;
8430 }
8431 }")
8433 (define_insn "*booldi3_internal1"
8434 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8435 (match_operator:DI 3 "boolean_or_operator"
8436 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8437 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8438 "TARGET_POWERPC64"
8439 "@
8440 %q3 %0,%1,%2
8441 %q3i %0,%1,%b2
8442 %q3is %0,%1,%u2")
8444 (define_insn "*booldi3_internal2"
8445 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8446 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8447 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8448 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8449 (const_int 0)))
8450 (clobber (match_scratch:DI 3 "=r,r"))]
8451 "TARGET_64BIT"
8452 "@
8453 %q4. %3,%1,%2
8454 #"
8455 [(set_attr "type" "fast_compare,compare")
8456 (set_attr "length" "4,8")])
8458 (define_split
8459 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8460 (compare:CC (match_operator:DI 4 "boolean_operator"
8461 [(match_operand:DI 1 "gpc_reg_operand" "")
8462 (match_operand:DI 2 "gpc_reg_operand" "")])
8463 (const_int 0)))
8464 (clobber (match_scratch:DI 3 ""))]
8465 "TARGET_POWERPC64 && reload_completed"
8466 [(set (match_dup 3) (match_dup 4))
8467 (set (match_dup 0)
8468 (compare:CC (match_dup 3)
8469 (const_int 0)))]
8470 "")
8472 (define_insn "*booldi3_internal3"
8473 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8474 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8475 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8476 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8477 (const_int 0)))
8478 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8479 (match_dup 4))]
8480 "TARGET_64BIT"
8481 "@
8482 %q4. %0,%1,%2
8483 #"
8484 [(set_attr "type" "fast_compare,compare")
8485 (set_attr "length" "4,8")])
8487 (define_split
8488 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8489 (compare:CC (match_operator:DI 4 "boolean_operator"
8490 [(match_operand:DI 1 "gpc_reg_operand" "")
8491 (match_operand:DI 2 "gpc_reg_operand" "")])
8492 (const_int 0)))
8493 (set (match_operand:DI 0 "gpc_reg_operand" "")
8494 (match_dup 4))]
8495 "TARGET_POWERPC64 && reload_completed"
8496 [(set (match_dup 0) (match_dup 4))
8497 (set (match_dup 3)
8498 (compare:CC (match_dup 0)
8499 (const_int 0)))]
8500 "")
8502 ;; Split a logical operation that we can't do in one insn into two insns,
8503 ;; each of which does one 16-bit part. This is used by combine.
8505 (define_split
8506 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8507 (match_operator:DI 3 "boolean_or_operator"
8508 [(match_operand:DI 1 "gpc_reg_operand" "")
8509 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8510 "TARGET_POWERPC64"
8511 [(set (match_dup 0) (match_dup 4))
8512 (set (match_dup 0) (match_dup 5))]
8513 "
8514 {
8515 rtx i3,i4;
8517 if (GET_CODE (operands[2]) == CONST_DOUBLE)
8518 {
8519 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
8520 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
8521 0, DImode);
8522 i4 = GEN_INT (value & 0xffff);
8523 }
8524 else
8525 {
8526 i3 = GEN_INT (INTVAL (operands[2])
8527 & (~ (HOST_WIDE_INT) 0xffff));
8528 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8529 }
8530 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8531 operands[1], i3);
8532 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8533 operands[0], i4);
8534 }")
8536 (define_insn "*boolcdi3_internal1"
8537 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8538 (match_operator:DI 3 "boolean_operator"
8539 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8540 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8541 "TARGET_POWERPC64"
8542 "%q3 %0,%2,%1")
8544 (define_insn "*boolcdi3_internal2"
8545 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8546 (compare:CC (match_operator:DI 4 "boolean_operator"
8547 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8548 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8549 (const_int 0)))
8550 (clobber (match_scratch:DI 3 "=r,r"))]
8551 "TARGET_64BIT"
8552 "@
8553 %q4. %3,%2,%1
8554 #"
8555 [(set_attr "type" "fast_compare,compare")
8556 (set_attr "length" "4,8")])
8558 (define_split
8559 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8560 (compare:CC (match_operator:DI 4 "boolean_operator"
8561 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8562 (match_operand:DI 2 "gpc_reg_operand" "")])
8563 (const_int 0)))
8564 (clobber (match_scratch:DI 3 ""))]
8565 "TARGET_POWERPC64 && reload_completed"
8566 [(set (match_dup 3) (match_dup 4))
8567 (set (match_dup 0)
8568 (compare:CC (match_dup 3)
8569 (const_int 0)))]
8570 "")
8572 (define_insn "*boolcdi3_internal3"
8573 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8574 (compare:CC (match_operator:DI 4 "boolean_operator"
8575 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8576 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8577 (const_int 0)))
8578 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8579 (match_dup 4))]
8580 "TARGET_64BIT"
8581 "@
8582 %q4. %0,%2,%1
8583 #"
8584 [(set_attr "type" "fast_compare,compare")
8585 (set_attr "length" "4,8")])
8587 (define_split
8588 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8589 (compare:CC (match_operator:DI 4 "boolean_operator"
8590 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8591 (match_operand:DI 2 "gpc_reg_operand" "")])
8592 (const_int 0)))
8593 (set (match_operand:DI 0 "gpc_reg_operand" "")
8594 (match_dup 4))]
8595 "TARGET_POWERPC64 && reload_completed"
8596 [(set (match_dup 0) (match_dup 4))
8597 (set (match_dup 3)
8598 (compare:CC (match_dup 0)
8599 (const_int 0)))]
8600 "")
8602 (define_insn "*boolccdi3_internal1"
8603 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8604 (match_operator:DI 3 "boolean_operator"
8605 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8606 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8607 "TARGET_POWERPC64"
8608 "%q3 %0,%1,%2")
8610 (define_insn "*boolccdi3_internal2"
8611 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8612 (compare:CC (match_operator:DI 4 "boolean_operator"
8613 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8614 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8615 (const_int 0)))
8616 (clobber (match_scratch:DI 3 "=r,r"))]
8617 "TARGET_64BIT"
8618 "@
8619 %q4. %3,%1,%2
8620 #"
8621 [(set_attr "type" "fast_compare,compare")
8622 (set_attr "length" "4,8")])
8624 (define_split
8625 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8626 (compare:CC (match_operator:DI 4 "boolean_operator"
8627 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8628 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8629 (const_int 0)))
8630 (clobber (match_scratch:DI 3 ""))]
8631 "TARGET_POWERPC64 && reload_completed"
8632 [(set (match_dup 3) (match_dup 4))
8633 (set (match_dup 0)
8634 (compare:CC (match_dup 3)
8635 (const_int 0)))]
8636 "")
8638 (define_insn "*boolccdi3_internal3"
8639 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8640 (compare:CC (match_operator:DI 4 "boolean_operator"
8641 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8642 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8643 (const_int 0)))
8644 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8645 (match_dup 4))]
8646 "TARGET_64BIT"
8647 "@
8648 %q4. %0,%1,%2
8649 #"
8650 [(set_attr "type" "fast_compare,compare")
8651 (set_attr "length" "4,8")])
8653 (define_split
8654 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8655 (compare:CC (match_operator:DI 4 "boolean_operator"
8656 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8657 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8658 (const_int 0)))
8659 (set (match_operand:DI 0 "gpc_reg_operand" "")
8660 (match_dup 4))]
8661 "TARGET_POWERPC64 && reload_completed"
8662 [(set (match_dup 0) (match_dup 4))
8663 (set (match_dup 3)
8664 (compare:CC (match_dup 0)
8665 (const_int 0)))]
8666 "")
8668 (define_expand "smindi3"
8669 [(match_operand:DI 0 "gpc_reg_operand" "")
8670 (match_operand:DI 1 "gpc_reg_operand" "")
8671 (match_operand:DI 2 "gpc_reg_operand" "")]
8672 "TARGET_ISEL64"
8673 "
8674 {
8675 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
8676 DONE;
8677 }")
8679 (define_expand "smaxdi3"
8680 [(match_operand:DI 0 "gpc_reg_operand" "")
8681 (match_operand:DI 1 "gpc_reg_operand" "")
8682 (match_operand:DI 2 "gpc_reg_operand" "")]
8683 "TARGET_ISEL64"
8684 "
8685 {
8686 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
8687 DONE;
8688 }")
8690 (define_expand "umindi3"
8691 [(match_operand:DI 0 "gpc_reg_operand" "")
8692 (match_operand:DI 1 "gpc_reg_operand" "")
8693 (match_operand:DI 2 "gpc_reg_operand" "")]
8694 "TARGET_ISEL64"
8695 "
8696 {
8697 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
8698 DONE;
8699 }")
8701 (define_expand "umaxdi3"
8702 [(match_operand:DI 0 "gpc_reg_operand" "")
8703 (match_operand:DI 1 "gpc_reg_operand" "")
8704 (match_operand:DI 2 "gpc_reg_operand" "")]
8705 "TARGET_ISEL64"
8706 "
8707 {
8708 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
8709 DONE;
8710 }")
8712 \f
8713 ;; Now define ways of moving data around.
8715 ;; Set up a register with a value from the GOT table
8717 (define_expand "movsi_got"
8718 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8719 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8720 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8721 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8722 "
8723 {
8724 if (GET_CODE (operands[1]) == CONST)
8725 {
8726 rtx offset = const0_rtx;
8727 HOST_WIDE_INT value;
8729 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8730 value = INTVAL (offset);
8731 if (value != 0)
8732 {
8733 rtx tmp = (!can_create_pseudo_p ()
8734 ? operands[0]
8735 : gen_reg_rtx (Pmode));
8736 emit_insn (gen_movsi_got (tmp, operands[1]));
8737 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8738 DONE;
8739 }
8740 }
8742 operands[2] = rs6000_got_register (operands[1]);
8743 }")
8745 (define_insn "*movsi_got_internal"
8746 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8747 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8748 (match_operand:SI 2 "gpc_reg_operand" "b")]
8749 UNSPEC_MOVSI_GOT))]
8750 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8751 "{l|lwz} %0,%a1@got(%2)"
8752 [(set_attr "type" "load")])
8754 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8755 ;; didn't get allocated to a hard register.
8756 (define_split
8757 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8758 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8759 (match_operand:SI 2 "memory_operand" "")]
8760 UNSPEC_MOVSI_GOT))]
8761 "DEFAULT_ABI == ABI_V4
8762 && flag_pic == 1
8763 && (reload_in_progress || reload_completed)"
8764 [(set (match_dup 0) (match_dup 2))
8765 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8766 UNSPEC_MOVSI_GOT))]
8767 "")
8769 ;; For SI, we special-case integers that can't be loaded in one insn. We
8770 ;; do the load 16-bits at a time. We could do this by loading from memory,
8771 ;; and this is even supposed to be faster, but it is simpler not to get
8772 ;; integers in the TOC.
8773 (define_insn "movsi_low"
8774 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8775 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8776 (match_operand 2 "" ""))))]
8777 "TARGET_MACHO && ! TARGET_64BIT"
8778 "{l|lwz} %0,lo16(%2)(%1)"
8779 [(set_attr "type" "load")
8780 (set_attr "length" "4")])
8782 (define_insn "*movsi_internal1"
8783 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8784 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8785 "!TARGET_SINGLE_FPU &&
8786 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8787 "@
8788 mr %0,%1
8789 {cal|la} %0,%a1
8790 {l%U1%X1|lwz%U1%X1} %0,%1
8791 {st%U0%X0|stw%U0%X0} %1,%0
8792 {lil|li} %0,%1
8793 {liu|lis} %0,%v1
8794 #
8795 {cal|la} %0,%a1
8796 mf%1 %0
8797 mt%0 %1
8798 mt%0 %1
8799 mt%0 %1
8800 {cror 0,0,0|nop}"
8801 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8802 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8804 (define_insn "*movsi_internal1_single"
8805 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
8806 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
8807 "TARGET_SINGLE_FPU &&
8808 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8809 "@
8810 mr %0,%1
8811 {cal|la} %0,%a1
8812 {l%U1%X1|lwz%U1%X1} %0,%1
8813 {st%U0%X0|stw%U0%X0} %1,%0
8814 {lil|li} %0,%1
8815 {liu|lis} %0,%v1
8816 #
8817 {cal|la} %0,%a1
8818 mf%1 %0
8819 mt%0 %1
8820 mt%0 %1
8821 mt%0 %1
8822 {cror 0,0,0|nop}
8823 stfs%U0%X0 %1, %0
8824 lfs%U1%X1 %0, %1"
8825 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
8826 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
8828 ;; Split a load of a large constant into the appropriate two-insn
8829 ;; sequence.
8831 (define_split
8832 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8833 (match_operand:SI 1 "const_int_operand" ""))]
8834 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8835 && (INTVAL (operands[1]) & 0xffff) != 0"
8836 [(set (match_dup 0)
8837 (match_dup 2))
8838 (set (match_dup 0)
8839 (ior:SI (match_dup 0)
8840 (match_dup 3)))]
8841 "
8842 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8844 if (tem == operands[0])
8845 DONE;
8846 else
8847 FAIL;
8848 }")
8850 (define_insn "*mov<mode>_internal2"
8851 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8852 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8853 (const_int 0)))
8854 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8855 ""
8856 "@
8857 {cmpi|cmp<wd>i} %2,%0,0
8858 mr. %0,%1
8859 #"
8860 [(set_attr "type" "cmp,compare,cmp")
8861 (set_attr "length" "4,4,8")])
8863 (define_split
8864 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8865 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8866 (const_int 0)))
8867 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8868 "reload_completed"
8869 [(set (match_dup 0) (match_dup 1))
8870 (set (match_dup 2)
8871 (compare:CC (match_dup 0)
8872 (const_int 0)))]
8873 "")
8874 \f
8875 (define_insn "*movhi_internal"
8876 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8877 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8878 "gpc_reg_operand (operands[0], HImode)
8879 || gpc_reg_operand (operands[1], HImode)"
8880 "@
8881 mr %0,%1
8882 lhz%U1%X1 %0,%1
8883 sth%U0%X0 %1,%0
8884 {lil|li} %0,%w1
8885 mf%1 %0
8886 mt%0 %1
8887 mt%0 %1
8888 {cror 0,0,0|nop}"
8889 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8891 (define_expand "mov<mode>"
8892 [(set (match_operand:INT 0 "general_operand" "")
8893 (match_operand:INT 1 "any_operand" ""))]
8894 ""
8895 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8897 (define_insn "*movqi_internal"
8898 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8899 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8900 "gpc_reg_operand (operands[0], QImode)
8901 || gpc_reg_operand (operands[1], QImode)"
8902 "@
8903 mr %0,%1
8904 lbz%U1%X1 %0,%1
8905 stb%U0%X0 %1,%0
8906 {lil|li} %0,%1
8907 mf%1 %0
8908 mt%0 %1
8909 mt%0 %1
8910 {cror 0,0,0|nop}"
8911 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8912 \f
8913 ;; Here is how to move condition codes around. When we store CC data in
8914 ;; an integer register or memory, we store just the high-order 4 bits.
8915 ;; This lets us not shift in the most common case of CR0.
8916 (define_expand "movcc"
8917 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8918 (match_operand:CC 1 "nonimmediate_operand" ""))]
8919 ""
8920 "")
8922 (define_insn "*movcc_internal1"
8923 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8924 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8925 "register_operand (operands[0], CCmode)
8926 || register_operand (operands[1], CCmode)"
8927 "@
8928 mcrf %0,%1
8929 mtcrf 128,%1
8930 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8931 crxor %0,%0,%0
8932 mfcr %0%Q1
8933 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8934 mr %0,%1
8935 {lil|li} %0,%1
8936 mf%1 %0
8937 mt%0 %1
8938 mt%0 %1
8939 {l%U1%X1|lwz%U1%X1} %0,%1
8940 {st%U0%U1|stw%U0%U1} %1,%0"
8941 [(set (attr "type")
8942 (cond [(eq_attr "alternative" "0,3")
8943 (const_string "cr_logical")
8944 (eq_attr "alternative" "1,2")
8945 (const_string "mtcr")
8946 (eq_attr "alternative" "6,7,9")
8947 (const_string "integer")
8948 (eq_attr "alternative" "8")
8949 (const_string "mfjmpr")
8950 (eq_attr "alternative" "10")
8951 (const_string "mtjmpr")
8952 (eq_attr "alternative" "11")
8953 (const_string "load")
8954 (eq_attr "alternative" "12")
8955 (const_string "store")
8956 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8957 (const_string "mfcrf")
8958 ]
8959 (const_string "mfcr")))
8960 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8961 \f
8962 ;; For floating-point, we normally deal with the floating-point registers
8963 ;; unless -msoft-float is used. The sole exception is that parameter passing
8964 ;; can produce floating-point values in fixed-point registers. Unless the
8965 ;; value is a simple constant or already in memory, we deal with this by
8966 ;; allocating memory and copying the value explicitly via that memory location.
8967 (define_expand "movsf"
8968 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8969 (match_operand:SF 1 "any_operand" ""))]
8970 ""
8971 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8973 (define_split
8974 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8975 (match_operand:SF 1 "const_double_operand" ""))]
8976 "reload_completed
8977 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8978 || (GET_CODE (operands[0]) == SUBREG
8979 && GET_CODE (SUBREG_REG (operands[0])) == REG
8980 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8981 [(set (match_dup 2) (match_dup 3))]
8982 "
8983 {
8984 long l;
8985 REAL_VALUE_TYPE rv;
8987 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8988 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8990 if (! TARGET_POWERPC64)
8991 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8992 else
8993 operands[2] = gen_lowpart (SImode, operands[0]);
8995 operands[3] = gen_int_mode (l, SImode);
8996 }")
8998 (define_insn "*movsf_hardfloat"
8999 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
9000 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
9001 "(gpc_reg_operand (operands[0], SFmode)
9002 || gpc_reg_operand (operands[1], SFmode))
9003 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9004 "@
9005 mr %0,%1
9006 {l%U1%X1|lwz%U1%X1} %0,%1
9007 {st%U0%X0|stw%U0%X0} %1,%0
9008 fmr %0,%1
9009 lfs%U1%X1 %0,%1
9010 stfs%U0%X0 %1,%0
9011 mt%0 %1
9012 mt%0 %1
9013 mf%1 %0
9014 {cror 0,0,0|nop}
9015 #
9016 #"
9017 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
9018 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
9020 (define_insn "*movsf_softfloat"
9021 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
9022 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
9023 "(gpc_reg_operand (operands[0], SFmode)
9024 || gpc_reg_operand (operands[1], SFmode))
9025 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9026 "@
9027 mr %0,%1
9028 mt%0 %1
9029 mt%0 %1
9030 mf%1 %0
9031 {l%U1%X1|lwz%U1%X1} %0,%1
9032 {st%U0%X0|stw%U0%X0} %1,%0
9033 {lil|li} %0,%1
9034 {liu|lis} %0,%v1
9035 {cal|la} %0,%a1
9036 #
9037 #
9038 {cror 0,0,0|nop}"
9039 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
9040 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
9042 \f
9043 (define_expand "movdf"
9044 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9045 (match_operand:DF 1 "any_operand" ""))]
9046 ""
9047 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
9049 (define_split
9050 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9051 (match_operand:DF 1 "const_int_operand" ""))]
9052 "! TARGET_POWERPC64 && reload_completed
9053 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9054 || (GET_CODE (operands[0]) == SUBREG
9055 && GET_CODE (SUBREG_REG (operands[0])) == REG
9056 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9057 [(set (match_dup 2) (match_dup 4))
9058 (set (match_dup 3) (match_dup 1))]
9059 "
9060 {
9061 int endian = (WORDS_BIG_ENDIAN == 0);
9062 HOST_WIDE_INT value = INTVAL (operands[1]);
9064 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9065 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9066 #if HOST_BITS_PER_WIDE_INT == 32
9067 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9068 #else
9069 operands[4] = GEN_INT (value >> 32);
9070 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9071 #endif
9072 }")
9074 (define_split
9075 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9076 (match_operand:DF 1 "const_double_operand" ""))]
9077 "! TARGET_POWERPC64 && reload_completed
9078 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9079 || (GET_CODE (operands[0]) == SUBREG
9080 && GET_CODE (SUBREG_REG (operands[0])) == REG
9081 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9082 [(set (match_dup 2) (match_dup 4))
9083 (set (match_dup 3) (match_dup 5))]
9084 "
9085 {
9086 int endian = (WORDS_BIG_ENDIAN == 0);
9087 long l[2];
9088 REAL_VALUE_TYPE rv;
9090 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9091 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9093 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9094 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9095 operands[4] = gen_int_mode (l[endian], SImode);
9096 operands[5] = gen_int_mode (l[1 - endian], SImode);
9097 }")
9099 (define_split
9100 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9101 (match_operand:DF 1 "const_double_operand" ""))]
9102 "TARGET_POWERPC64 && reload_completed
9103 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9104 || (GET_CODE (operands[0]) == SUBREG
9105 && GET_CODE (SUBREG_REG (operands[0])) == REG
9106 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9107 [(set (match_dup 2) (match_dup 3))]
9108 "
9109 {
9110 int endian = (WORDS_BIG_ENDIAN == 0);
9111 long l[2];
9112 REAL_VALUE_TYPE rv;
9113 #if HOST_BITS_PER_WIDE_INT >= 64
9114 HOST_WIDE_INT val;
9115 #endif
9117 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9118 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9120 operands[2] = gen_lowpart (DImode, operands[0]);
9121 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9122 #if HOST_BITS_PER_WIDE_INT >= 64
9123 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9124 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9126 operands[3] = gen_int_mode (val, DImode);
9127 #else
9128 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
9129 #endif
9130 }")
9132 ;; Don't have reload use general registers to load a constant. First,
9133 ;; it might not work if the output operand is the equivalent of
9134 ;; a non-offsettable memref, but also it is less efficient than loading
9135 ;; the constant into an FP register, since it will probably be used there.
9136 ;; The "??" is a kludge until we can figure out a more reasonable way
9137 ;; of handling these non-offsettable values.
9138 (define_insn "*movdf_hardfloat32"
9139 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
9140 (match_operand:DF 1 "input_operand" "r,m,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
9141 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9142 && (gpc_reg_operand (operands[0], DFmode)
9143 || gpc_reg_operand (operands[1], DFmode))"
9144 "*
9145 {
9146 switch (which_alternative)
9147 {
9148 default:
9149 gcc_unreachable ();
9150 case 0:
9151 /* We normally copy the low-numbered register first. However, if
9152 the first register operand 0 is the same as the second register
9153 of operand 1, we must copy in the opposite order. */
9154 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9155 return \"mr %L0,%L1\;mr %0,%1\";
9156 else
9157 return \"mr %0,%1\;mr %L0,%L1\";
9158 case 1:
9159 if (rs6000_offsettable_memref_p (operands[1])
9160 || (GET_CODE (operands[1]) == MEM
9161 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
9162 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
9163 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
9164 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
9165 {
9166 /* If the low-address word is used in the address, we must load
9167 it last. Otherwise, load it first. Note that we cannot have
9168 auto-increment in that case since the address register is
9169 known to be dead. */
9170 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
9171 operands[1], 0))
9172 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
9173 else
9174 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
9175 }
9176 else
9177 {
9178 rtx addreg;
9180 addreg = find_addr_reg (XEXP (operands[1], 0));
9181 if (refers_to_regno_p (REGNO (operands[0]),
9182 REGNO (operands[0]) + 1,
9183 operands[1], 0))
9184 {
9185 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
9186 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
9187 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
9188 return \"{l%X1|lwz%X1} %0,%1\";
9189 }
9190 else
9191 {
9192 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
9193 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
9194 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
9195 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
9196 return \"\";
9197 }
9198 }
9199 case 2:
9200 if (rs6000_offsettable_memref_p (operands[0])
9201 || (GET_CODE (operands[0]) == MEM
9202 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
9203 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
9204 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
9205 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
9206 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
9207 else
9208 {
9209 rtx addreg;
9211 addreg = find_addr_reg (XEXP (operands[0], 0));
9212 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
9213 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
9214 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
9215 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
9216 return \"\";
9217 }
9218 case 3:
9219 case 4:
9220 return \"xxlor %x0,%x1,%x1\";
9221 case 5:
9222 case 6:
9223 return \"lxsd%U1x %x0,%y1\";
9224 case 7:
9225 case 8:
9226 return \"stxsd%U0x %x1,%y0\";
9227 case 9:
9228 return \"fmr %0,%1\";
9229 case 10:
9230 return \"lfd%U1%X1 %0,%1\";
9231 case 11:
9232 return \"stfd%U0%X0 %1,%0\";
9233 case 12:
9234 return \"xxlxor %x0,%x0,%x0\";
9235 case 13:
9236 case 14:
9237 case 15:
9238 return \"#\";
9239 }
9240 }"
9241 [(set_attr "type" "two,load,store,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
9242 (set_attr "length" "8,16,16,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9244 (define_insn "*movdf_softfloat32"
9245 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
9246 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
9247 "! TARGET_POWERPC64
9248 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9249 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9250 && (gpc_reg_operand (operands[0], DFmode)
9251 || gpc_reg_operand (operands[1], DFmode))"
9252 "*
9253 {
9254 switch (which_alternative)
9255 {
9256 default:
9257 gcc_unreachable ();
9258 case 0:
9259 /* We normally copy the low-numbered register first. However, if
9260 the first register operand 0 is the same as the second register of
9261 operand 1, we must copy in the opposite order. */
9262 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9263 return \"mr %L0,%L1\;mr %0,%1\";
9264 else
9265 return \"mr %0,%1\;mr %L0,%L1\";
9266 case 1:
9267 /* If the low-address word is used in the address, we must load
9268 it last. Otherwise, load it first. Note that we cannot have
9269 auto-increment in that case since the address register is
9270 known to be dead. */
9271 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
9272 operands[1], 0))
9273 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
9274 else
9275 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
9276 case 2:
9277 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
9278 case 3:
9279 case 4:
9280 case 5:
9281 return \"#\";
9282 }
9283 }"
9284 [(set_attr "type" "two,load,store,*,*,*")
9285 (set_attr "length" "8,8,8,8,12,16")])
9287 ; ld/std require word-aligned displacements -> 'Y' constraint.
9288 ; List Y->r and r->Y before r->r for reload.
9289 (define_insn "*movdf_hardfloat64_mfpgpr"
9290 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r,r,d")
9291 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
9292 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9293 && TARGET_DOUBLE_FLOAT
9294 && (gpc_reg_operand (operands[0], DFmode)
9295 || gpc_reg_operand (operands[1], DFmode))"
9296 "@
9297 std%U0%X0 %1,%0
9298 ld%U1%X1 %0,%1
9299 mr %0,%1
9300 xxlor %x0,%x1,%x1
9301 xxlor %x0,%x1,%x1
9302 lxsd%U1x %x0,%y1
9303 lxsd%U1x %x0,%y1
9304 stxsd%U0x %x1,%y0
9305 stxsd%U0x %x1,%y0
9306 fmr %0,%1
9307 lfd%U1%X1 %0,%1
9308 stfd%U0%X0 %1,%0
9309 xxlxor %x0,%x0,%x0
9310 mt%0 %1
9311 mf%1 %0
9312 {cror 0,0,0|nop}
9313 #
9314 #
9315 #
9316 mftgpr %0,%1
9317 mffgpr %0,%1"
9318 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
9319 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9321 ; ld/std require word-aligned displacements -> 'Y' constraint.
9322 ; List Y->r and r->Y before r->r for reload.
9323 (define_insn "*movdf_hardfloat64"
9324 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r")
9325 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
9326 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9327 && TARGET_DOUBLE_FLOAT
9328 && (gpc_reg_operand (operands[0], DFmode)
9329 || gpc_reg_operand (operands[1], DFmode))"
9330 "@
9331 std%U0%X0 %1,%0
9332 ld%U1%X1 %0,%1
9333 mr %0,%1
9334 xxlor %x0,%x1,%x1
9335 xxlor %x0,%x1,%x1
9336 lxsd%U1x %x0,%y1
9337 lxsd%U1x %x0,%y1
9338 stxsd%U0x %x1,%y0
9339 stxsd%U0x %x1,%y0
9340 fmr %0,%1
9341 lfd%U1%X1 %0,%1
9342 stfd%U0%X0 %1,%0
9343 xxlxor %x0,%x0,%x0
9344 mt%0 %1
9345 mf%1 %0
9346 {cror 0,0,0|nop}
9347 #
9348 #
9349 #"
9350 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
9351 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9353 (define_insn "*movdf_softfloat64"
9354 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
9355 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
9356 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9357 && (gpc_reg_operand (operands[0], DFmode)
9358 || gpc_reg_operand (operands[1], DFmode))"
9359 "@
9360 ld%U1%X1 %0,%1
9361 std%U0%X0 %1,%0
9362 mr %0,%1
9363 mt%0 %1
9364 mf%1 %0
9365 #
9366 #
9367 #
9368 {cror 0,0,0|nop}"
9369 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
9370 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9371 \f
9372 (define_expand "movtf"
9373 [(set (match_operand:TF 0 "general_operand" "")
9374 (match_operand:TF 1 "any_operand" ""))]
9375 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
9376 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
9378 ; It's important to list the o->f and f->o moves before f->f because
9379 ; otherwise reload, given m->f, will try to pick f->f and reload it,
9380 ; which doesn't make progress. Likewise r->Y must be before r->r.
9381 (define_insn_and_split "*movtf_internal"
9382 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
9383 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
9384 "!TARGET_IEEEQUAD
9385 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
9386 && (gpc_reg_operand (operands[0], TFmode)
9387 || gpc_reg_operand (operands[1], TFmode))"
9388 "#"
9389 "&& reload_completed"
9390 [(pc)]
9391 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9392 [(set_attr "length" "8,8,8,20,20,16")])
9394 (define_insn_and_split "*movtf_softfloat"
9395 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
9396 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
9397 "!TARGET_IEEEQUAD
9398 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
9399 && (gpc_reg_operand (operands[0], TFmode)
9400 || gpc_reg_operand (operands[1], TFmode))"
9401 "#"
9402 "&& reload_completed"
9403 [(pc)]
9404 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9405 [(set_attr "length" "20,20,16")])
9407 (define_expand "extenddftf2"
9408 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9409 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9410 "!TARGET_IEEEQUAD
9411 && TARGET_HARD_FLOAT
9412 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9413 && TARGET_LONG_DOUBLE_128"
9414 {
9415 if (TARGET_E500_DOUBLE)
9416 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9417 else
9418 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9419 DONE;
9420 })
9422 (define_expand "extenddftf2_fprs"
9423 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9424 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9425 (use (match_dup 2))])]
9426 "!TARGET_IEEEQUAD
9427 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9428 && TARGET_LONG_DOUBLE_128"
9429 {
9430 operands[2] = CONST0_RTX (DFmode);
9431 /* Generate GOT reference early for SVR4 PIC. */
9432 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9433 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9434 })
9436 (define_insn_and_split "*extenddftf2_internal"
9437 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
9438 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
9439 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
9440 "!TARGET_IEEEQUAD
9441 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9442 && TARGET_LONG_DOUBLE_128"
9443 "#"
9444 "&& reload_completed"
9445 [(pc)]
9446 {
9447 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9448 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9449 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9450 operands[1]);
9451 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9452 operands[2]);
9453 DONE;
9454 })
9456 (define_expand "extendsftf2"
9457 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9458 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9459 "!TARGET_IEEEQUAD
9460 && TARGET_HARD_FLOAT
9461 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9462 && TARGET_LONG_DOUBLE_128"
9463 {
9464 rtx tmp = gen_reg_rtx (DFmode);
9465 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9466 emit_insn (gen_extenddftf2 (operands[0], tmp));
9467 DONE;
9468 })
9470 (define_expand "trunctfdf2"
9471 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9472 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9473 "!TARGET_IEEEQUAD
9474 && TARGET_HARD_FLOAT
9475 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9476 && TARGET_LONG_DOUBLE_128"
9477 "")
9479 (define_insn_and_split "trunctfdf2_internal1"
9480 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9481 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9482 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9483 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9484 "@
9485 #
9486 fmr %0,%1"
9487 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9488 [(const_int 0)]
9489 {
9490 emit_note (NOTE_INSN_DELETED);
9491 DONE;
9492 }
9493 [(set_attr "type" "fp")])
9495 (define_insn "trunctfdf2_internal2"
9496 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9497 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9498 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9499 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9500 && TARGET_LONG_DOUBLE_128"
9501 "fadd %0,%1,%L1"
9502 [(set_attr "type" "fp")
9503 (set_attr "fp_type" "fp_addsub_d")])
9505 (define_expand "trunctfsf2"
9506 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9507 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9508 "!TARGET_IEEEQUAD
9509 && TARGET_HARD_FLOAT
9510 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9511 && TARGET_LONG_DOUBLE_128"
9512 {
9513 if (TARGET_E500_DOUBLE)
9514 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9515 else
9516 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9517 DONE;
9518 })
9520 (define_insn_and_split "trunctfsf2_fprs"
9521 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9522 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9523 (clobber (match_scratch:DF 2 "=d"))]
9524 "!TARGET_IEEEQUAD
9525 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9526 && TARGET_LONG_DOUBLE_128"
9527 "#"
9528 "&& reload_completed"
9529 [(set (match_dup 2)
9530 (float_truncate:DF (match_dup 1)))
9531 (set (match_dup 0)
9532 (float_truncate:SF (match_dup 2)))]
9533 "")
9535 (define_expand "floatsitf2"
9536 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9537 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9538 "!TARGET_IEEEQUAD
9539 && TARGET_HARD_FLOAT
9540 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9541 && TARGET_LONG_DOUBLE_128"
9542 {
9543 rtx tmp = gen_reg_rtx (DFmode);
9544 expand_float (tmp, operands[1], false);
9545 emit_insn (gen_extenddftf2 (operands[0], tmp));
9546 DONE;
9547 })
9549 ; fadd, but rounding towards zero.
9550 ; This is probably not the optimal code sequence.
9551 (define_insn "fix_trunc_helper"
9552 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9553 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9554 UNSPEC_FIX_TRUNC_TF))
9555 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9556 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9557 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9558 [(set_attr "type" "fp")
9559 (set_attr "length" "20")])
9561 (define_expand "fix_trunctfsi2"
9562 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9563 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9564 "!TARGET_IEEEQUAD
9565 && (TARGET_POWER2 || TARGET_POWERPC)
9566 && TARGET_HARD_FLOAT
9567 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9568 && TARGET_LONG_DOUBLE_128"
9569 {
9570 if (TARGET_E500_DOUBLE)
9571 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9572 else
9573 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9574 DONE;
9575 })
9577 (define_expand "fix_trunctfsi2_fprs"
9578 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9579 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9580 (clobber (match_dup 2))
9581 (clobber (match_dup 3))
9582 (clobber (match_dup 4))
9583 (clobber (match_dup 5))])]
9584 "!TARGET_IEEEQUAD
9585 && (TARGET_POWER2 || TARGET_POWERPC)
9586 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9587 {
9588 operands[2] = gen_reg_rtx (DFmode);
9589 operands[3] = gen_reg_rtx (DFmode);
9590 operands[4] = gen_reg_rtx (DImode);
9591 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
9592 })
9594 (define_insn_and_split "*fix_trunctfsi2_internal"
9595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9596 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9597 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9598 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9599 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9600 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9601 "!TARGET_IEEEQUAD
9602 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9603 "#"
9604 ""
9605 [(pc)]
9606 {
9607 rtx lowword;
9608 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9610 gcc_assert (MEM_P (operands[5]));
9611 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9613 emit_insn (gen_fctiwz (operands[4], operands[2]));
9614 emit_move_insn (operands[5], operands[4]);
9615 emit_move_insn (operands[0], lowword);
9616 DONE;
9617 })
9619 (define_expand "negtf2"
9620 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9621 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9622 "!TARGET_IEEEQUAD
9623 && TARGET_HARD_FLOAT
9624 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9625 && TARGET_LONG_DOUBLE_128"
9626 "")
9628 (define_insn "negtf2_internal"
9629 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9630 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9631 "!TARGET_IEEEQUAD
9632 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9633 "*
9634 {
9635 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9636 return \"fneg %L0,%L1\;fneg %0,%1\";
9637 else
9638 return \"fneg %0,%1\;fneg %L0,%L1\";
9639 }"
9640 [(set_attr "type" "fp")
9641 (set_attr "length" "8")])
9643 (define_expand "abstf2"
9644 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9645 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9646 "!TARGET_IEEEQUAD
9647 && TARGET_HARD_FLOAT
9648 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9649 && TARGET_LONG_DOUBLE_128"
9650 "
9651 {
9652 rtx label = gen_label_rtx ();
9653 if (TARGET_E500_DOUBLE)
9654 {
9655 if (flag_finite_math_only && !flag_trapping_math)
9656 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9657 else
9658 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9659 }
9660 else
9661 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9662 emit_label (label);
9663 DONE;
9664 }")
9666 (define_expand "abstf2_internal"
9667 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9668 (match_operand:TF 1 "gpc_reg_operand" ""))
9669 (set (match_dup 3) (match_dup 5))
9670 (set (match_dup 5) (abs:DF (match_dup 5)))
9671 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9672 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9673 (label_ref (match_operand 2 "" ""))
9674 (pc)))
9675 (set (match_dup 6) (neg:DF (match_dup 6)))]
9676 "!TARGET_IEEEQUAD
9677 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9678 && TARGET_LONG_DOUBLE_128"
9679 "
9680 {
9681 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9682 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9683 operands[3] = gen_reg_rtx (DFmode);
9684 operands[4] = gen_reg_rtx (CCFPmode);
9685 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9686 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9687 }")
9688 \f
9689 ;; Next come the multi-word integer load and store and the load and store
9690 ;; multiple insns.
9692 ; List r->r after r->"o<>", otherwise reload will try to reload a
9693 ; non-offsettable address by using r->r which won't make progress.
9694 (define_insn "*movdi_internal32"
9695 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r")
9696 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
9697 "! TARGET_POWERPC64
9698 && (gpc_reg_operand (operands[0], DImode)
9699 || gpc_reg_operand (operands[1], DImode))"
9700 "@
9701 #
9702 #
9703 #
9704 fmr %0,%1
9705 lfd%U1%X1 %0,%1
9706 stfd%U0%X0 %1,%0
9707 #"
9708 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
9710 (define_split
9711 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9712 (match_operand:DI 1 "const_int_operand" ""))]
9713 "! TARGET_POWERPC64 && reload_completed"
9714 [(set (match_dup 2) (match_dup 4))
9715 (set (match_dup 3) (match_dup 1))]
9716 "
9717 {
9718 HOST_WIDE_INT value = INTVAL (operands[1]);
9719 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9720 DImode);
9721 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9722 DImode);
9723 #if HOST_BITS_PER_WIDE_INT == 32
9724 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9725 #else
9726 operands[4] = GEN_INT (value >> 32);
9727 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9728 #endif
9729 }")
9731 (define_split
9732 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
9733 (match_operand:DI 1 "input_operand" ""))]
9734 "reload_completed && !TARGET_POWERPC64
9735 && gpr_or_gpr_p (operands[0], operands[1])"
9736 [(pc)]
9737 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9739 (define_insn "*movdi_mfpgpr"
9740 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
9741 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
9742 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9743 && (gpc_reg_operand (operands[0], DImode)
9744 || gpc_reg_operand (operands[1], DImode))"
9745 "@
9746 mr %0,%1
9747 ld%U1%X1 %0,%1
9748 std%U0%X0 %1,%0
9749 li %0,%1
9750 lis %0,%v1
9751 #
9752 {cal|la} %0,%a1
9753 fmr %0,%1
9754 lfd%U1%X1 %0,%1
9755 stfd%U0%X0 %1,%0
9756 mf%1 %0
9757 mt%0 %1
9758 {cror 0,0,0|nop}
9759 mftgpr %0,%1
9760 mffgpr %0,%1"
9761 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9762 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9764 (define_insn "*movdi_internal64"
9765 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
9766 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
9767 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9768 && (gpc_reg_operand (operands[0], DImode)
9769 || gpc_reg_operand (operands[1], DImode))"
9770 "@
9771 mr %0,%1
9772 ld%U1%X1 %0,%1
9773 std%U0%X0 %1,%0
9774 li %0,%1
9775 lis %0,%v1
9776 #
9777 {cal|la} %0,%a1
9778 fmr %0,%1
9779 lfd%U1%X1 %0,%1
9780 stfd%U0%X0 %1,%0
9781 mf%1 %0
9782 mt%0 %1
9783 {cror 0,0,0|nop}"
9784 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9785 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9787 ;; immediate value valid for a single instruction hiding in a const_double
9788 (define_insn ""
9789 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9790 (match_operand:DI 1 "const_double_operand" "F"))]
9791 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9792 && GET_CODE (operands[1]) == CONST_DOUBLE
9793 && num_insns_constant (operands[1], DImode) == 1"
9794 "*
9795 {
9796 return ((unsigned HOST_WIDE_INT)
9797 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9798 ? \"li %0,%1\" : \"lis %0,%v1\";
9799 }")
9801 ;; Generate all one-bits and clear left or right.
9802 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9803 (define_split
9804 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9805 (match_operand:DI 1 "mask64_operand" ""))]
9806 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9807 [(set (match_dup 0) (const_int -1))
9808 (set (match_dup 0)
9809 (and:DI (rotate:DI (match_dup 0)
9810 (const_int 0))
9811 (match_dup 1)))]
9812 "")
9814 ;; Split a load of a large constant into the appropriate five-instruction
9815 ;; sequence. Handle anything in a constant number of insns.
9816 ;; When non-easy constants can go in the TOC, this should use
9817 ;; easy_fp_constant predicate.
9818 (define_split
9819 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9820 (match_operand:DI 1 "const_int_operand" ""))]
9821 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9822 [(set (match_dup 0) (match_dup 2))
9823 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9824 "
9825 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9827 if (tem == operands[0])
9828 DONE;
9829 else
9830 FAIL;
9831 }")
9833 (define_split
9834 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9835 (match_operand:DI 1 "const_double_operand" ""))]
9836 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9837 [(set (match_dup 0) (match_dup 2))
9838 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9839 "
9840 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9842 if (tem == operands[0])
9843 DONE;
9844 else
9845 FAIL;
9846 }")
9847 \f
9848 ;; TImode is similar, except that we usually want to compute the address into
9849 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9850 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9852 ;; We say that MQ is clobbered in the last alternative because the first
9853 ;; alternative would never get used otherwise since it would need a reload
9854 ;; while the 2nd alternative would not. We put memory cases first so they
9855 ;; are preferred. Otherwise, we'd try to reload the output instead of
9856 ;; giving the SCRATCH mq.
9858 (define_insn "*movti_power"
9859 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9860 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9861 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9862 "TARGET_POWER && ! TARGET_POWERPC64
9863 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9864 "*
9865 {
9866 switch (which_alternative)
9867 {
9868 default:
9869 gcc_unreachable ();
9871 case 0:
9872 if (TARGET_STRING)
9873 return \"{stsi|stswi} %1,%P0,16\";
9874 case 1:
9875 case 2:
9876 return \"#\";
9877 case 3:
9878 /* If the address is not used in the output, we can use lsi. Otherwise,
9879 fall through to generating four loads. */
9880 if (TARGET_STRING
9881 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9882 return \"{lsi|lswi} %0,%P1,16\";
9883 /* ... fall through ... */
9884 case 4:
9885 case 5:
9886 return \"#\";
9887 }
9888 }"
9889 [(set_attr "type" "store,store,*,load,load,*")])
9891 (define_insn "*movti_string"
9892 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9893 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9894 "! TARGET_POWER && ! TARGET_POWERPC64
9895 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9896 "*
9897 {
9898 switch (which_alternative)
9899 {
9900 default:
9901 gcc_unreachable ();
9902 case 0:
9903 if (TARGET_STRING)
9904 return \"{stsi|stswi} %1,%P0,16\";
9905 case 1:
9906 case 2:
9907 return \"#\";
9908 case 3:
9909 /* If the address is not used in the output, we can use lsi. Otherwise,
9910 fall through to generating four loads. */
9911 if (TARGET_STRING
9912 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9913 return \"{lsi|lswi} %0,%P1,16\";
9914 /* ... fall through ... */
9915 case 4:
9916 case 5:
9917 return \"#\";
9918 }
9919 }"
9920 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
9921 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
9922 (const_string "always")
9923 (const_string "conditional")))])
9925 (define_insn "*movti_ppc64"
9926 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9927 (match_operand:TI 1 "input_operand" "r,r,m"))]
9928 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9929 || gpc_reg_operand (operands[1], TImode)))
9930 && VECTOR_MEM_NONE_P (TImode)"
9931 "#"
9932 [(set_attr "type" "*,store,load")])
9934 (define_split
9935 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9936 (match_operand:TI 1 "const_double_operand" ""))]
9937 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
9938 [(set (match_dup 2) (match_dup 4))
9939 (set (match_dup 3) (match_dup 5))]
9940 "
9941 {
9942 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9943 TImode);
9944 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9945 TImode);
9946 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9947 {
9948 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9949 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9950 }
9951 else if (GET_CODE (operands[1]) == CONST_INT)
9952 {
9953 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9954 operands[5] = operands[1];
9955 }
9956 else
9957 FAIL;
9958 }")
9960 (define_split
9961 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9962 (match_operand:TI 1 "input_operand" ""))]
9963 "reload_completed && VECTOR_MEM_NONE_P (TImode)
9964 && gpr_or_gpr_p (operands[0], operands[1])"
9965 [(pc)]
9966 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9967 \f
9968 (define_expand "load_multiple"
9969 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9970 (match_operand:SI 1 "" ""))
9971 (use (match_operand:SI 2 "" ""))])]
9972 "TARGET_STRING && !TARGET_POWERPC64"
9973 "
9974 {
9975 int regno;
9976 int count;
9977 rtx op1;
9978 int i;
9980 /* Support only loading a constant number of fixed-point registers from
9981 memory and only bother with this if more than two; the machine
9982 doesn't support more than eight. */
9983 if (GET_CODE (operands[2]) != CONST_INT
9984 || INTVAL (operands[2]) <= 2
9985 || INTVAL (operands[2]) > 8
9986 || GET_CODE (operands[1]) != MEM
9987 || GET_CODE (operands[0]) != REG
9988 || REGNO (operands[0]) >= 32)
9989 FAIL;
9991 count = INTVAL (operands[2]);
9992 regno = REGNO (operands[0]);
9994 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9995 op1 = replace_equiv_address (operands[1],
9996 force_reg (SImode, XEXP (operands[1], 0)));
9998 for (i = 0; i < count; i++)
9999 XVECEXP (operands[3], 0, i)
10000 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
10001 adjust_address_nv (op1, SImode, i * 4));
10002 }")
10004 (define_insn "*ldmsi8"
10005 [(match_parallel 0 "load_multiple_operation"
10006 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10007 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10008 (set (match_operand:SI 3 "gpc_reg_operand" "")
10009 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10010 (set (match_operand:SI 4 "gpc_reg_operand" "")
10011 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10012 (set (match_operand:SI 5 "gpc_reg_operand" "")
10013 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10014 (set (match_operand:SI 6 "gpc_reg_operand" "")
10015 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10016 (set (match_operand:SI 7 "gpc_reg_operand" "")
10017 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10018 (set (match_operand:SI 8 "gpc_reg_operand" "")
10019 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
10020 (set (match_operand:SI 9 "gpc_reg_operand" "")
10021 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
10022 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10023 "*
10024 { return rs6000_output_load_multiple (operands); }"
10025 [(set_attr "type" "load_ux")
10026 (set_attr "length" "32")])
10028 (define_insn "*ldmsi7"
10029 [(match_parallel 0 "load_multiple_operation"
10030 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10031 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10032 (set (match_operand:SI 3 "gpc_reg_operand" "")
10033 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10034 (set (match_operand:SI 4 "gpc_reg_operand" "")
10035 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10036 (set (match_operand:SI 5 "gpc_reg_operand" "")
10037 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10038 (set (match_operand:SI 6 "gpc_reg_operand" "")
10039 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10040 (set (match_operand:SI 7 "gpc_reg_operand" "")
10041 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10042 (set (match_operand:SI 8 "gpc_reg_operand" "")
10043 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
10044 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10045 "*
10046 { return rs6000_output_load_multiple (operands); }"
10047 [(set_attr "type" "load_ux")
10048 (set_attr "length" "32")])
10050 (define_insn "*ldmsi6"
10051 [(match_parallel 0 "load_multiple_operation"
10052 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10053 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10054 (set (match_operand:SI 3 "gpc_reg_operand" "")
10055 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10056 (set (match_operand:SI 4 "gpc_reg_operand" "")
10057 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10058 (set (match_operand:SI 5 "gpc_reg_operand" "")
10059 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10060 (set (match_operand:SI 6 "gpc_reg_operand" "")
10061 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10062 (set (match_operand:SI 7 "gpc_reg_operand" "")
10063 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
10064 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10065 "*
10066 { return rs6000_output_load_multiple (operands); }"
10067 [(set_attr "type" "load_ux")
10068 (set_attr "length" "32")])
10070 (define_insn "*ldmsi5"
10071 [(match_parallel 0 "load_multiple_operation"
10072 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10073 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10074 (set (match_operand:SI 3 "gpc_reg_operand" "")
10075 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10076 (set (match_operand:SI 4 "gpc_reg_operand" "")
10077 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10078 (set (match_operand:SI 5 "gpc_reg_operand" "")
10079 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10080 (set (match_operand:SI 6 "gpc_reg_operand" "")
10081 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10082 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10083 "*
10084 { return rs6000_output_load_multiple (operands); }"
10085 [(set_attr "type" "load_ux")
10086 (set_attr "length" "32")])
10088 (define_insn "*ldmsi4"
10089 [(match_parallel 0 "load_multiple_operation"
10090 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10091 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10092 (set (match_operand:SI 3 "gpc_reg_operand" "")
10093 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10094 (set (match_operand:SI 4 "gpc_reg_operand" "")
10095 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10096 (set (match_operand:SI 5 "gpc_reg_operand" "")
10097 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10098 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10099 "*
10100 { return rs6000_output_load_multiple (operands); }"
10101 [(set_attr "type" "load_ux")
10102 (set_attr "length" "32")])
10104 (define_insn "*ldmsi3"
10105 [(match_parallel 0 "load_multiple_operation"
10106 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10107 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10108 (set (match_operand:SI 3 "gpc_reg_operand" "")
10109 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10110 (set (match_operand:SI 4 "gpc_reg_operand" "")
10111 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10112 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10113 "*
10114 { return rs6000_output_load_multiple (operands); }"
10115 [(set_attr "type" "load_ux")
10116 (set_attr "length" "32")])
10118 (define_expand "store_multiple"
10119 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10120 (match_operand:SI 1 "" ""))
10121 (clobber (scratch:SI))
10122 (use (match_operand:SI 2 "" ""))])]
10123 "TARGET_STRING && !TARGET_POWERPC64"
10124 "
10125 {
10126 int regno;
10127 int count;
10128 rtx to;
10129 rtx op0;
10130 int i;
10132 /* Support only storing a constant number of fixed-point registers to
10133 memory and only bother with this if more than two; the machine
10134 doesn't support more than eight. */
10135 if (GET_CODE (operands[2]) != CONST_INT
10136 || INTVAL (operands[2]) <= 2
10137 || INTVAL (operands[2]) > 8
10138 || GET_CODE (operands[0]) != MEM
10139 || GET_CODE (operands[1]) != REG
10140 || REGNO (operands[1]) >= 32)
10141 FAIL;
10143 count = INTVAL (operands[2]);
10144 regno = REGNO (operands[1]);
10146 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10147 to = force_reg (SImode, XEXP (operands[0], 0));
10148 op0 = replace_equiv_address (operands[0], to);
10150 XVECEXP (operands[3], 0, 0)
10151 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10152 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10153 gen_rtx_SCRATCH (SImode));
10155 for (i = 1; i < count; i++)
10156 XVECEXP (operands[3], 0, i + 1)
10157 = gen_rtx_SET (VOIDmode,
10158 adjust_address_nv (op0, SImode, i * 4),
10159 gen_rtx_REG (SImode, regno + i));
10160 }")
10162 (define_insn "*stmsi8"
10163 [(match_parallel 0 "store_multiple_operation"
10164 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10165 (match_operand:SI 2 "gpc_reg_operand" "r"))
10166 (clobber (match_scratch:SI 3 "=X"))
10167 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10168 (match_operand:SI 4 "gpc_reg_operand" "r"))
10169 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10170 (match_operand:SI 5 "gpc_reg_operand" "r"))
10171 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10172 (match_operand:SI 6 "gpc_reg_operand" "r"))
10173 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10174 (match_operand:SI 7 "gpc_reg_operand" "r"))
10175 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10176 (match_operand:SI 8 "gpc_reg_operand" "r"))
10177 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10178 (match_operand:SI 9 "gpc_reg_operand" "r"))
10179 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10180 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10181 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10182 "{stsi|stswi} %2,%1,%O0"
10183 [(set_attr "type" "store_ux")
10184 (set_attr "cell_micro" "always")])
10186 (define_insn "*stmsi7"
10187 [(match_parallel 0 "store_multiple_operation"
10188 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10189 (match_operand:SI 2 "gpc_reg_operand" "r"))
10190 (clobber (match_scratch:SI 3 "=X"))
10191 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10192 (match_operand:SI 4 "gpc_reg_operand" "r"))
10193 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10194 (match_operand:SI 5 "gpc_reg_operand" "r"))
10195 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10196 (match_operand:SI 6 "gpc_reg_operand" "r"))
10197 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10198 (match_operand:SI 7 "gpc_reg_operand" "r"))
10199 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10200 (match_operand:SI 8 "gpc_reg_operand" "r"))
10201 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10202 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10203 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10204 "{stsi|stswi} %2,%1,%O0"
10205 [(set_attr "type" "store_ux")
10206 (set_attr "cell_micro" "always")])
10208 (define_insn "*stmsi6"
10209 [(match_parallel 0 "store_multiple_operation"
10210 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10211 (match_operand:SI 2 "gpc_reg_operand" "r"))
10212 (clobber (match_scratch:SI 3 "=X"))
10213 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10214 (match_operand:SI 4 "gpc_reg_operand" "r"))
10215 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10216 (match_operand:SI 5 "gpc_reg_operand" "r"))
10217 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10218 (match_operand:SI 6 "gpc_reg_operand" "r"))
10219 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10220 (match_operand:SI 7 "gpc_reg_operand" "r"))
10221 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10222 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10223 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10224 "{stsi|stswi} %2,%1,%O0"
10225 [(set_attr "type" "store_ux")
10226 (set_attr "cell_micro" "always")])
10228 (define_insn "*stmsi5"
10229 [(match_parallel 0 "store_multiple_operation"
10230 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10231 (match_operand:SI 2 "gpc_reg_operand" "r"))
10232 (clobber (match_scratch:SI 3 "=X"))
10233 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10234 (match_operand:SI 4 "gpc_reg_operand" "r"))
10235 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10236 (match_operand:SI 5 "gpc_reg_operand" "r"))
10237 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10238 (match_operand:SI 6 "gpc_reg_operand" "r"))
10239 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10240 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10241 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10242 "{stsi|stswi} %2,%1,%O0"
10243 [(set_attr "type" "store_ux")
10244 (set_attr "cell_micro" "always")])
10246 (define_insn "*stmsi4"
10247 [(match_parallel 0 "store_multiple_operation"
10248 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10249 (match_operand:SI 2 "gpc_reg_operand" "r"))
10250 (clobber (match_scratch:SI 3 "=X"))
10251 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10252 (match_operand:SI 4 "gpc_reg_operand" "r"))
10253 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10254 (match_operand:SI 5 "gpc_reg_operand" "r"))
10255 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10256 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10257 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10258 "{stsi|stswi} %2,%1,%O0"
10259 [(set_attr "type" "store_ux")
10260 (set_attr "cell_micro" "always")])
10262 (define_insn "*stmsi3"
10263 [(match_parallel 0 "store_multiple_operation"
10264 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10265 (match_operand:SI 2 "gpc_reg_operand" "r"))
10266 (clobber (match_scratch:SI 3 "=X"))
10267 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10268 (match_operand:SI 4 "gpc_reg_operand" "r"))
10269 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10270 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10271 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10272 "{stsi|stswi} %2,%1,%O0"
10273 [(set_attr "type" "store_ux")
10274 (set_attr "cell_micro" "always")])
10276 (define_insn "*stmsi8_power"
10277 [(match_parallel 0 "store_multiple_operation"
10278 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10279 (match_operand:SI 2 "gpc_reg_operand" "r"))
10280 (clobber (match_scratch:SI 3 "=q"))
10281 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10282 (match_operand:SI 4 "gpc_reg_operand" "r"))
10283 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10284 (match_operand:SI 5 "gpc_reg_operand" "r"))
10285 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10286 (match_operand:SI 6 "gpc_reg_operand" "r"))
10287 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10288 (match_operand:SI 7 "gpc_reg_operand" "r"))
10289 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10290 (match_operand:SI 8 "gpc_reg_operand" "r"))
10291 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10292 (match_operand:SI 9 "gpc_reg_operand" "r"))
10293 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10294 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10295 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10296 "{stsi|stswi} %2,%1,%O0"
10297 [(set_attr "type" "store_ux")
10298 (set_attr "cell_micro" "always")])
10300 (define_insn "*stmsi7_power"
10301 [(match_parallel 0 "store_multiple_operation"
10302 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10303 (match_operand:SI 2 "gpc_reg_operand" "r"))
10304 (clobber (match_scratch:SI 3 "=q"))
10305 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10306 (match_operand:SI 4 "gpc_reg_operand" "r"))
10307 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10308 (match_operand:SI 5 "gpc_reg_operand" "r"))
10309 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10310 (match_operand:SI 6 "gpc_reg_operand" "r"))
10311 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10312 (match_operand:SI 7 "gpc_reg_operand" "r"))
10313 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10314 (match_operand:SI 8 "gpc_reg_operand" "r"))
10315 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10316 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10317 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10318 "{stsi|stswi} %2,%1,%O0"
10319 [(set_attr "type" "store_ux")
10320 (set_attr "cell_micro" "always")])
10322 (define_insn "*stmsi6_power"
10323 [(match_parallel 0 "store_multiple_operation"
10324 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10325 (match_operand:SI 2 "gpc_reg_operand" "r"))
10326 (clobber (match_scratch:SI 3 "=q"))
10327 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10328 (match_operand:SI 4 "gpc_reg_operand" "r"))
10329 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10330 (match_operand:SI 5 "gpc_reg_operand" "r"))
10331 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10332 (match_operand:SI 6 "gpc_reg_operand" "r"))
10333 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10334 (match_operand:SI 7 "gpc_reg_operand" "r"))
10335 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10336 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10337 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10338 "{stsi|stswi} %2,%1,%O0"
10339 [(set_attr "type" "store_ux")
10340 (set_attr "cell_micro" "always")])
10342 (define_insn "*stmsi5_power"
10343 [(match_parallel 0 "store_multiple_operation"
10344 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10345 (match_operand:SI 2 "gpc_reg_operand" "r"))
10346 (clobber (match_scratch:SI 3 "=q"))
10347 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10348 (match_operand:SI 4 "gpc_reg_operand" "r"))
10349 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10350 (match_operand:SI 5 "gpc_reg_operand" "r"))
10351 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10352 (match_operand:SI 6 "gpc_reg_operand" "r"))
10353 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10354 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10355 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10356 "{stsi|stswi} %2,%1,%O0"
10357 [(set_attr "type" "store_ux")
10358 (set_attr "cell_micro" "always")])
10360 (define_insn "*stmsi4_power"
10361 [(match_parallel 0 "store_multiple_operation"
10362 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10363 (match_operand:SI 2 "gpc_reg_operand" "r"))
10364 (clobber (match_scratch:SI 3 "=q"))
10365 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10366 (match_operand:SI 4 "gpc_reg_operand" "r"))
10367 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10368 (match_operand:SI 5 "gpc_reg_operand" "r"))
10369 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10370 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10371 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10372 "{stsi|stswi} %2,%1,%O0"
10373 [(set_attr "type" "store_ux")
10374 (set_attr "cell_micro" "always")])
10376 (define_insn "*stmsi3_power"
10377 [(match_parallel 0 "store_multiple_operation"
10378 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10379 (match_operand:SI 2 "gpc_reg_operand" "r"))
10380 (clobber (match_scratch:SI 3 "=q"))
10381 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10382 (match_operand:SI 4 "gpc_reg_operand" "r"))
10383 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10384 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10385 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10386 "{stsi|stswi} %2,%1,%O0"
10387 [(set_attr "type" "store_ux")
10388 (set_attr "cell_micro" "always")])
10389 \f
10390 (define_expand "setmemsi"
10391 [(parallel [(set (match_operand:BLK 0 "" "")
10392 (match_operand 2 "const_int_operand" ""))
10393 (use (match_operand:SI 1 "" ""))
10394 (use (match_operand:SI 3 "" ""))])]
10395 ""
10396 "
10397 {
10398 /* If value to set is not zero, use the library routine. */
10399 if (operands[2] != const0_rtx)
10400 FAIL;
10402 if (expand_block_clear (operands))
10403 DONE;
10404 else
10405 FAIL;
10406 }")
10408 ;; String/block move insn.
10409 ;; Argument 0 is the destination
10410 ;; Argument 1 is the source
10411 ;; Argument 2 is the length
10412 ;; Argument 3 is the alignment
10414 (define_expand "movmemsi"
10415 [(parallel [(set (match_operand:BLK 0 "" "")
10416 (match_operand:BLK 1 "" ""))
10417 (use (match_operand:SI 2 "" ""))
10418 (use (match_operand:SI 3 "" ""))])]
10419 ""
10420 "
10421 {
10422 if (expand_block_move (operands))
10423 DONE;
10424 else
10425 FAIL;
10426 }")
10428 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10429 ;; register allocator doesn't have a clue about allocating 8 word registers.
10430 ;; rD/rS = r5 is preferred, efficient form.
10431 (define_expand "movmemsi_8reg"
10432 [(parallel [(set (match_operand 0 "" "")
10433 (match_operand 1 "" ""))
10434 (use (match_operand 2 "" ""))
10435 (use (match_operand 3 "" ""))
10436 (clobber (reg:SI 5))
10437 (clobber (reg:SI 6))
10438 (clobber (reg:SI 7))
10439 (clobber (reg:SI 8))
10440 (clobber (reg:SI 9))
10441 (clobber (reg:SI 10))
10442 (clobber (reg:SI 11))
10443 (clobber (reg:SI 12))
10444 (clobber (match_scratch:SI 4 ""))])]
10445 "TARGET_STRING"
10446 "")
10448 (define_insn ""
10449 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10450 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10451 (use (match_operand:SI 2 "immediate_operand" "i"))
10452 (use (match_operand:SI 3 "immediate_operand" "i"))
10453 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10454 (clobber (reg:SI 6))
10455 (clobber (reg:SI 7))
10456 (clobber (reg:SI 8))
10457 (clobber (reg:SI 9))
10458 (clobber (reg:SI 10))
10459 (clobber (reg:SI 11))
10460 (clobber (reg:SI 12))
10461 (clobber (match_scratch:SI 5 "=q"))]
10462 "TARGET_STRING && TARGET_POWER
10463 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10464 || INTVAL (operands[2]) == 0)
10465 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10466 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10467 && REGNO (operands[4]) == 5"
10468 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10469 [(set_attr "type" "store_ux")
10470 (set_attr "cell_micro" "always")
10471 (set_attr "length" "8")])
10473 (define_insn ""
10474 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10475 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10476 (use (match_operand:SI 2 "immediate_operand" "i"))
10477 (use (match_operand:SI 3 "immediate_operand" "i"))
10478 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10479 (clobber (reg:SI 6))
10480 (clobber (reg:SI 7))
10481 (clobber (reg:SI 8))
10482 (clobber (reg:SI 9))
10483 (clobber (reg:SI 10))
10484 (clobber (reg:SI 11))
10485 (clobber (reg:SI 12))
10486 (clobber (match_scratch:SI 5 "=X"))]
10487 "TARGET_STRING && ! TARGET_POWER
10488 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10489 || INTVAL (operands[2]) == 0)
10490 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10491 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10492 && REGNO (operands[4]) == 5"
10493 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10494 [(set_attr "type" "store_ux")
10495 (set_attr "cell_micro" "always")
10496 (set_attr "length" "8")])
10498 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10499 ;; register allocator doesn't have a clue about allocating 6 word registers.
10500 ;; rD/rS = r5 is preferred, efficient form.
10501 (define_expand "movmemsi_6reg"
10502 [(parallel [(set (match_operand 0 "" "")
10503 (match_operand 1 "" ""))
10504 (use (match_operand 2 "" ""))
10505 (use (match_operand 3 "" ""))
10506 (clobber (reg:SI 5))
10507 (clobber (reg:SI 6))
10508 (clobber (reg:SI 7))
10509 (clobber (reg:SI 8))
10510 (clobber (reg:SI 9))
10511 (clobber (reg:SI 10))
10512 (clobber (match_scratch:SI 4 ""))])]
10513 "TARGET_STRING"
10514 "")
10516 (define_insn ""
10517 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10518 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10519 (use (match_operand:SI 2 "immediate_operand" "i"))
10520 (use (match_operand:SI 3 "immediate_operand" "i"))
10521 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10522 (clobber (reg:SI 6))
10523 (clobber (reg:SI 7))
10524 (clobber (reg:SI 8))
10525 (clobber (reg:SI 9))
10526 (clobber (reg:SI 10))
10527 (clobber (match_scratch:SI 5 "=q"))]
10528 "TARGET_STRING && TARGET_POWER
10529 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
10530 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10531 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10532 && REGNO (operands[4]) == 5"
10533 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10534 [(set_attr "type" "store_ux")
10535 (set_attr "cell_micro" "always")
10536 (set_attr "length" "8")])
10538 (define_insn ""
10539 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10540 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10541 (use (match_operand:SI 2 "immediate_operand" "i"))
10542 (use (match_operand:SI 3 "immediate_operand" "i"))
10543 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10544 (clobber (reg:SI 6))
10545 (clobber (reg:SI 7))
10546 (clobber (reg:SI 8))
10547 (clobber (reg:SI 9))
10548 (clobber (reg:SI 10))
10549 (clobber (match_scratch:SI 5 "=X"))]
10550 "TARGET_STRING && ! TARGET_POWER
10551 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10552 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10553 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10554 && REGNO (operands[4]) == 5"
10555 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10556 [(set_attr "type" "store_ux")
10557 (set_attr "cell_micro" "always")
10558 (set_attr "length" "8")])
10560 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10561 ;; problems with TImode.
10562 ;; rD/rS = r5 is preferred, efficient form.
10563 (define_expand "movmemsi_4reg"
10564 [(parallel [(set (match_operand 0 "" "")
10565 (match_operand 1 "" ""))
10566 (use (match_operand 2 "" ""))
10567 (use (match_operand 3 "" ""))
10568 (clobber (reg:SI 5))
10569 (clobber (reg:SI 6))
10570 (clobber (reg:SI 7))
10571 (clobber (reg:SI 8))
10572 (clobber (match_scratch:SI 4 ""))])]
10573 "TARGET_STRING"
10574 "")
10576 (define_insn ""
10577 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10578 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10579 (use (match_operand:SI 2 "immediate_operand" "i"))
10580 (use (match_operand:SI 3 "immediate_operand" "i"))
10581 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10582 (clobber (reg:SI 6))
10583 (clobber (reg:SI 7))
10584 (clobber (reg:SI 8))
10585 (clobber (match_scratch:SI 5 "=q"))]
10586 "TARGET_STRING && TARGET_POWER
10587 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10588 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10589 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10590 && REGNO (operands[4]) == 5"
10591 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10592 [(set_attr "type" "store_ux")
10593 (set_attr "cell_micro" "always")
10594 (set_attr "length" "8")])
10596 (define_insn ""
10597 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10598 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10599 (use (match_operand:SI 2 "immediate_operand" "i"))
10600 (use (match_operand:SI 3 "immediate_operand" "i"))
10601 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10602 (clobber (reg:SI 6))
10603 (clobber (reg:SI 7))
10604 (clobber (reg:SI 8))
10605 (clobber (match_scratch:SI 5 "=X"))]
10606 "TARGET_STRING && ! TARGET_POWER
10607 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10608 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10609 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10610 && REGNO (operands[4]) == 5"
10611 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10612 [(set_attr "type" "store_ux")
10613 (set_attr "cell_micro" "always")
10614 (set_attr "length" "8")])
10616 ;; Move up to 8 bytes at a time.
10617 (define_expand "movmemsi_2reg"
10618 [(parallel [(set (match_operand 0 "" "")
10619 (match_operand 1 "" ""))
10620 (use (match_operand 2 "" ""))
10621 (use (match_operand 3 "" ""))
10622 (clobber (match_scratch:DI 4 ""))
10623 (clobber (match_scratch:SI 5 ""))])]
10624 "TARGET_STRING && ! TARGET_POWERPC64"
10625 "")
10627 (define_insn ""
10628 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10629 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10630 (use (match_operand:SI 2 "immediate_operand" "i"))
10631 (use (match_operand:SI 3 "immediate_operand" "i"))
10632 (clobber (match_scratch:DI 4 "=&r"))
10633 (clobber (match_scratch:SI 5 "=q"))]
10634 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
10635 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10636 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10637 [(set_attr "type" "store_ux")
10638 (set_attr "cell_micro" "always")
10639 (set_attr "length" "8")])
10641 (define_insn ""
10642 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10643 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10644 (use (match_operand:SI 2 "immediate_operand" "i"))
10645 (use (match_operand:SI 3 "immediate_operand" "i"))
10646 (clobber (match_scratch:DI 4 "=&r"))
10647 (clobber (match_scratch:SI 5 "=X"))]
10648 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
10649 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10650 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10651 [(set_attr "type" "store_ux")
10652 (set_attr "cell_micro" "always")
10653 (set_attr "length" "8")])
10655 ;; Move up to 4 bytes at a time.
10656 (define_expand "movmemsi_1reg"
10657 [(parallel [(set (match_operand 0 "" "")
10658 (match_operand 1 "" ""))
10659 (use (match_operand 2 "" ""))
10660 (use (match_operand 3 "" ""))
10661 (clobber (match_scratch:SI 4 ""))
10662 (clobber (match_scratch:SI 5 ""))])]
10663 "TARGET_STRING"
10664 "")
10666 (define_insn ""
10667 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10668 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10669 (use (match_operand:SI 2 "immediate_operand" "i"))
10670 (use (match_operand:SI 3 "immediate_operand" "i"))
10671 (clobber (match_scratch:SI 4 "=&r"))
10672 (clobber (match_scratch:SI 5 "=q"))]
10673 "TARGET_STRING && TARGET_POWER
10674 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10675 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10676 [(set_attr "type" "store_ux")
10677 (set_attr "cell_micro" "always")
10678 (set_attr "length" "8")])
10680 (define_insn ""
10681 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10682 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10683 (use (match_operand:SI 2 "immediate_operand" "i"))
10684 (use (match_operand:SI 3 "immediate_operand" "i"))
10685 (clobber (match_scratch:SI 4 "=&r"))
10686 (clobber (match_scratch:SI 5 "=X"))]
10687 "TARGET_STRING && ! TARGET_POWER
10688 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10689 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10690 [(set_attr "type" "store_ux")
10691 (set_attr "cell_micro" "always")
10692 (set_attr "length" "8")])
10693 \f
10694 ;; Define insns that do load or store with update. Some of these we can
10695 ;; get by using pre-decrement or pre-increment, but the hardware can also
10696 ;; do cases where the increment is not the size of the object.
10697 ;;
10698 ;; In all these cases, we use operands 0 and 1 for the register being
10699 ;; incremented because those are the operands that local-alloc will
10700 ;; tie and these are the pair most likely to be tieable (and the ones
10701 ;; that will benefit the most).
10703 (define_insn "*movdi_update1"
10704 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10705 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10706 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10707 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10708 (plus:DI (match_dup 1) (match_dup 2)))]
10709 "TARGET_POWERPC64 && TARGET_UPDATE
10710 && (!avoiding_indexed_address_p (DImode)
10711 || !gpc_reg_operand (operands[2], DImode))"
10712 "@
10713 ldux %3,%0,%2
10714 ldu %3,%2(%0)"
10715 [(set_attr "type" "load_ux,load_u")])
10717 (define_insn "movdi_<mode>_update"
10718 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10719 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10720 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10721 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10722 (plus:P (match_dup 1) (match_dup 2)))]
10723 "TARGET_POWERPC64 && TARGET_UPDATE
10724 && (!avoiding_indexed_address_p (Pmode)
10725 || !gpc_reg_operand (operands[2], Pmode)
10726 || (REG_P (operands[0])
10727 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10728 "@
10729 stdux %3,%0,%2
10730 stdu %3,%2(%0)"
10731 [(set_attr "type" "store_ux,store_u")])
10733 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10734 ;; needed for stack allocation, even if the user passes -mno-update.
10735 (define_insn "movdi_<mode>_update_stack"
10736 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10737 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10738 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10739 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10740 (plus:P (match_dup 1) (match_dup 2)))]
10741 "TARGET_POWERPC64"
10742 "@
10743 stdux %3,%0,%2
10744 stdu %3,%2(%0)"
10745 [(set_attr "type" "store_ux,store_u")])
10747 (define_insn "*movsi_update1"
10748 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10749 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10750 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10751 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10752 (plus:SI (match_dup 1) (match_dup 2)))]
10753 "TARGET_UPDATE
10754 && (!avoiding_indexed_address_p (SImode)
10755 || !gpc_reg_operand (operands[2], SImode))"
10756 "@
10757 {lux|lwzux} %3,%0,%2
10758 {lu|lwzu} %3,%2(%0)"
10759 [(set_attr "type" "load_ux,load_u")])
10761 (define_insn "*movsi_update2"
10762 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10763 (sign_extend:DI
10764 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10765 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10766 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10767 (plus:DI (match_dup 1) (match_dup 2)))]
10768 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10769 && !avoiding_indexed_address_p (DImode)"
10770 "lwaux %3,%0,%2"
10771 [(set_attr "type" "load_ext_ux")])
10773 (define_insn "movsi_update"
10774 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10775 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10776 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10777 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10778 (plus:SI (match_dup 1) (match_dup 2)))]
10779 "TARGET_UPDATE
10780 && (!avoiding_indexed_address_p (SImode)
10781 || !gpc_reg_operand (operands[2], SImode)
10782 || (REG_P (operands[0])
10783 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10784 "@
10785 {stux|stwux} %3,%0,%2
10786 {stu|stwu} %3,%2(%0)"
10787 [(set_attr "type" "store_ux,store_u")])
10789 ;; This is an unconditional pattern; needed for stack allocation, even
10790 ;; if the user passes -mno-update.
10791 (define_insn "movsi_update_stack"
10792 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10793 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10794 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10795 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10796 (plus:SI (match_dup 1) (match_dup 2)))]
10797 ""
10798 "@
10799 {stux|stwux} %3,%0,%2
10800 {stu|stwu} %3,%2(%0)"
10801 [(set_attr "type" "store_ux,store_u")])
10803 (define_insn "*movhi_update1"
10804 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10805 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10806 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10807 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10808 (plus:SI (match_dup 1) (match_dup 2)))]
10809 "TARGET_UPDATE
10810 && (!avoiding_indexed_address_p (SImode)
10811 || !gpc_reg_operand (operands[2], SImode))"
10812 "@
10813 lhzux %3,%0,%2
10814 lhzu %3,%2(%0)"
10815 [(set_attr "type" "load_ux,load_u")])
10817 (define_insn "*movhi_update2"
10818 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10819 (zero_extend:SI
10820 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10821 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10822 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10823 (plus:SI (match_dup 1) (match_dup 2)))]
10824 "TARGET_UPDATE
10825 && (!avoiding_indexed_address_p (SImode)
10826 || !gpc_reg_operand (operands[2], SImode))"
10827 "@
10828 lhzux %3,%0,%2
10829 lhzu %3,%2(%0)"
10830 [(set_attr "type" "load_ux,load_u")])
10832 (define_insn "*movhi_update3"
10833 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10834 (sign_extend:SI
10835 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10836 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10837 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10838 (plus:SI (match_dup 1) (match_dup 2)))]
10839 "TARGET_UPDATE && rs6000_gen_cell_microcode
10840 && (!avoiding_indexed_address_p (SImode)
10841 || !gpc_reg_operand (operands[2], SImode))"
10842 "@
10843 lhaux %3,%0,%2
10844 lhau %3,%2(%0)"
10845 [(set_attr "type" "load_ext_ux,load_ext_u")])
10847 (define_insn "*movhi_update4"
10848 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10849 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10850 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10851 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10852 (plus:SI (match_dup 1) (match_dup 2)))]
10853 "TARGET_UPDATE
10854 && (!avoiding_indexed_address_p (SImode)
10855 || !gpc_reg_operand (operands[2], SImode))"
10856 "@
10857 sthux %3,%0,%2
10858 sthu %3,%2(%0)"
10859 [(set_attr "type" "store_ux,store_u")])
10861 (define_insn "*movqi_update1"
10862 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10863 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10864 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10865 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10866 (plus:SI (match_dup 1) (match_dup 2)))]
10867 "TARGET_UPDATE
10868 && (!avoiding_indexed_address_p (SImode)
10869 || !gpc_reg_operand (operands[2], SImode))"
10870 "@
10871 lbzux %3,%0,%2
10872 lbzu %3,%2(%0)"
10873 [(set_attr "type" "load_ux,load_u")])
10875 (define_insn "*movqi_update2"
10876 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10877 (zero_extend:SI
10878 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10879 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10880 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10881 (plus:SI (match_dup 1) (match_dup 2)))]
10882 "TARGET_UPDATE
10883 && (!avoiding_indexed_address_p (SImode)
10884 || !gpc_reg_operand (operands[2], SImode))"
10885 "@
10886 lbzux %3,%0,%2
10887 lbzu %3,%2(%0)"
10888 [(set_attr "type" "load_ux,load_u")])
10890 (define_insn "*movqi_update3"
10891 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10892 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10893 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10894 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10895 (plus:SI (match_dup 1) (match_dup 2)))]
10896 "TARGET_UPDATE
10897 && (!avoiding_indexed_address_p (SImode)
10898 || !gpc_reg_operand (operands[2], SImode))"
10899 "@
10900 stbux %3,%0,%2
10901 stbu %3,%2(%0)"
10902 [(set_attr "type" "store_ux,store_u")])
10904 (define_insn "*movsf_update1"
10905 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10906 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10907 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10908 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10909 (plus:SI (match_dup 1) (match_dup 2)))]
10910 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10911 && (!avoiding_indexed_address_p (SImode)
10912 || !gpc_reg_operand (operands[2], SImode))"
10913 "@
10914 lfsux %3,%0,%2
10915 lfsu %3,%2(%0)"
10916 [(set_attr "type" "fpload_ux,fpload_u")])
10918 (define_insn "*movsf_update2"
10919 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10920 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10921 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10922 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10923 (plus:SI (match_dup 1) (match_dup 2)))]
10924 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10925 && (!avoiding_indexed_address_p (SImode)
10926 || !gpc_reg_operand (operands[2], SImode))"
10927 "@
10928 stfsux %3,%0,%2
10929 stfsu %3,%2(%0)"
10930 [(set_attr "type" "fpstore_ux,fpstore_u")])
10932 (define_insn "*movsf_update3"
10933 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10934 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10935 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10936 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10937 (plus:SI (match_dup 1) (match_dup 2)))]
10938 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10939 && (!avoiding_indexed_address_p (SImode)
10940 || !gpc_reg_operand (operands[2], SImode))"
10941 "@
10942 {lux|lwzux} %3,%0,%2
10943 {lu|lwzu} %3,%2(%0)"
10944 [(set_attr "type" "load_ux,load_u")])
10946 (define_insn "*movsf_update4"
10947 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10948 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10949 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10950 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10951 (plus:SI (match_dup 1) (match_dup 2)))]
10952 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10953 && (!avoiding_indexed_address_p (SImode)
10954 || !gpc_reg_operand (operands[2], SImode))"
10955 "@
10956 {stux|stwux} %3,%0,%2
10957 {stu|stwu} %3,%2(%0)"
10958 [(set_attr "type" "store_ux,store_u")])
10960 (define_insn "*movdf_update1"
10961 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10962 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10963 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10964 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10965 (plus:SI (match_dup 1) (match_dup 2)))]
10966 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10967 && (!avoiding_indexed_address_p (SImode)
10968 || !gpc_reg_operand (operands[2], SImode))"
10969 "@
10970 lfdux %3,%0,%2
10971 lfdu %3,%2(%0)"
10972 [(set_attr "type" "fpload_ux,fpload_u")])
10974 (define_insn "*movdf_update2"
10975 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10976 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10977 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10978 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10979 (plus:SI (match_dup 1) (match_dup 2)))]
10980 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10981 && (!avoiding_indexed_address_p (SImode)
10982 || !gpc_reg_operand (operands[2], SImode))"
10983 "@
10984 stfdux %3,%0,%2
10985 stfdu %3,%2(%0)"
10986 [(set_attr "type" "fpstore_ux,fpstore_u")])
10988 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10990 (define_insn "*lfq_power2"
10991 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10992 (match_operand:V2DF 1 "memory_operand" ""))]
10993 "TARGET_POWER2
10994 && TARGET_HARD_FLOAT && TARGET_FPRS"
10995 "lfq%U1%X1 %0,%1")
10997 (define_peephole2
10998 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10999 (match_operand:DF 1 "memory_operand" ""))
11000 (set (match_operand:DF 2 "gpc_reg_operand" "")
11001 (match_operand:DF 3 "memory_operand" ""))]
11002 "TARGET_POWER2
11003 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11004 && registers_ok_for_quad_peep (operands[0], operands[2])
11005 && mems_ok_for_quad_peep (operands[1], operands[3])"
11006 [(set (match_dup 0)
11007 (match_dup 1))]
11008 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
11009 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
11011 (define_insn "*stfq_power2"
11012 [(set (match_operand:V2DF 0 "memory_operand" "")
11013 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
11014 "TARGET_POWER2
11015 && TARGET_HARD_FLOAT && TARGET_FPRS"
11016 "stfq%U0%X0 %1,%0")
11019 (define_peephole2
11020 [(set (match_operand:DF 0 "memory_operand" "")
11021 (match_operand:DF 1 "gpc_reg_operand" ""))
11022 (set (match_operand:DF 2 "memory_operand" "")
11023 (match_operand:DF 3 "gpc_reg_operand" ""))]
11024 "TARGET_POWER2
11025 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11026 && registers_ok_for_quad_peep (operands[1], operands[3])
11027 && mems_ok_for_quad_peep (operands[0], operands[2])"
11028 [(set (match_dup 0)
11029 (match_dup 1))]
11030 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
11031 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
11033 ;; After inserting conditional returns we can sometimes have
11034 ;; unnecessary register moves. Unfortunately we cannot have a
11035 ;; modeless peephole here, because some single SImode sets have early
11036 ;; clobber outputs. Although those sets expand to multi-ppc-insn
11037 ;; sequences, using get_attr_length here will smash the operands
11038 ;; array. Neither is there an early_cobbler_p predicate.
11039 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
11040 (define_peephole2
11041 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11042 (match_operand:DF 1 "any_operand" ""))
11043 (set (match_operand:DF 2 "gpc_reg_operand" "")
11044 (match_dup 0))]
11045 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
11046 && peep2_reg_dead_p (2, operands[0])"
11047 [(set (match_dup 2) (match_dup 1))])
11049 (define_peephole2
11050 [(set (match_operand:SF 0 "gpc_reg_operand" "")
11051 (match_operand:SF 1 "any_operand" ""))
11052 (set (match_operand:SF 2 "gpc_reg_operand" "")
11053 (match_dup 0))]
11054 "peep2_reg_dead_p (2, operands[0])"
11055 [(set (match_dup 2) (match_dup 1))])
11057 \f
11058 ;; TLS support.
11060 ;; Mode attributes for different ABIs.
11061 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
11062 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
11063 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
11064 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
11066 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
11067 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11068 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11069 (match_operand 4 "" "g")))
11070 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11071 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11072 UNSPEC_TLSGD)
11073 (clobber (reg:SI LR_REGNO))]
11074 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11075 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
11076 "&& TARGET_TLS_MARKERS"
11077 [(set (match_dup 0)
11078 (unspec:TLSmode [(match_dup 1)
11079 (match_dup 2)]
11080 UNSPEC_TLSGD))
11081 (parallel [(set (match_dup 0)
11082 (call (mem:TLSmode (match_dup 3))
11083 (match_dup 4)))
11084 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11085 (clobber (reg:SI LR_REGNO))])]
11086 ""
11087 [(set_attr "type" "two")
11088 (set_attr "length" "12")])
11090 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
11091 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11092 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11093 (match_operand 4 "" "g")))
11094 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11095 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11096 UNSPEC_TLSGD)
11097 (clobber (reg:SI LR_REGNO))]
11098 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11099 {
11100 if (flag_pic)
11101 {
11102 if (TARGET_SECURE_PLT && flag_pic == 2)
11103 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11104 else
11105 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11106 }
11107 else
11108 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11109 }
11110 "&& TARGET_TLS_MARKERS"
11111 [(set (match_dup 0)
11112 (unspec:TLSmode [(match_dup 1)
11113 (match_dup 2)]
11114 UNSPEC_TLSGD))
11115 (parallel [(set (match_dup 0)
11116 (call (mem:TLSmode (match_dup 3))
11117 (match_dup 4)))
11118 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11119 (clobber (reg:SI LR_REGNO))])]
11120 ""
11121 [(set_attr "type" "two")
11122 (set_attr "length" "8")])
11124 (define_insn "*tls_gd<TLSmode:tls_abi_suffix>"
11125 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11126 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11127 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11128 UNSPEC_TLSGD))]
11129 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11130 "addi %0,%1,%2@got@tlsgd"
11131 [(set_attr "length" "4")])
11133 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11134 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11135 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11136 (match_operand 2 "" "g")))
11137 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11138 UNSPEC_TLSGD)
11139 (clobber (reg:SI LR_REGNO))]
11140 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11141 "bl %z1(%3@tlsgd)\;%."
11142 [(set_attr "type" "branch")
11143 (set_attr "length" "8")])
11145 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11146 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11147 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11148 (match_operand 2 "" "g")))
11149 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11150 UNSPEC_TLSGD)
11151 (clobber (reg:SI LR_REGNO))]
11152 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11153 {
11154 if (flag_pic)
11155 {
11156 if (TARGET_SECURE_PLT && flag_pic == 2)
11157 return "bl %z1+32768(%3@tlsgd)@plt";
11158 return "bl %z1(%3@tlsgd)@plt";
11159 }
11160 return "bl %z1(%3@tlsgd)";
11161 }
11162 [(set_attr "type" "branch")
11163 (set_attr "length" "4")])
11165 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11166 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11167 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11168 (match_operand 3 "" "g")))
11169 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11170 UNSPEC_TLSLD)
11171 (clobber (reg:SI LR_REGNO))]
11172 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11173 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
11174 "&& TARGET_TLS_MARKERS"
11175 [(set (match_dup 0)
11176 (unspec:TLSmode [(match_dup 1)]
11177 UNSPEC_TLSLD))
11178 (parallel [(set (match_dup 0)
11179 (call (mem:TLSmode (match_dup 2))
11180 (match_dup 3)))
11181 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11182 (clobber (reg:SI LR_REGNO))])]
11183 ""
11184 [(set_attr "length" "12")])
11186 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11187 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11188 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11189 (match_operand 3 "" "g")))
11190 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11191 UNSPEC_TLSLD)
11192 (clobber (reg:SI LR_REGNO))]
11193 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11194 {
11195 if (flag_pic)
11196 {
11197 if (TARGET_SECURE_PLT && flag_pic == 2)
11198 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11199 else
11200 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11201 }
11202 else
11203 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11204 }
11205 "&& TARGET_TLS_MARKERS"
11206 [(set (match_dup 0)
11207 (unspec:TLSmode [(match_dup 1)]
11208 UNSPEC_TLSLD))
11209 (parallel [(set (match_dup 0)
11210 (call (mem:TLSmode (match_dup 2))
11211 (match_dup 3)))
11212 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11213 (clobber (reg:SI LR_REGNO))])]
11214 ""
11215 [(set_attr "length" "8")])
11217 (define_insn "*tls_ld<TLSmode:tls_abi_suffix>"
11218 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11219 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11220 UNSPEC_TLSLD))]
11221 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11222 "addi %0,%1,%&@got@tlsld"
11223 [(set_attr "length" "4")])
11225 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11226 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11227 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11228 (match_operand 2 "" "g")))
11229 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11230 (clobber (reg:SI LR_REGNO))]
11231 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11232 "bl %z1(%&@tlsld)\;%."
11233 [(set_attr "type" "branch")
11234 (set_attr "length" "8")])
11236 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11237 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11238 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11239 (match_operand 2 "" "g")))
11240 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11241 (clobber (reg:SI LR_REGNO))]
11242 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11243 {
11244 if (flag_pic)
11245 {
11246 if (TARGET_SECURE_PLT && flag_pic == 2)
11247 return "bl %z1+32768(%&@tlsld)@plt";
11248 return "bl %z1(%&@tlsld)@plt";
11249 }
11250 return "bl %z1(%&@tlsld)";
11251 }
11252 [(set_attr "type" "branch")
11253 (set_attr "length" "4")])
11255 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11256 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11257 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11258 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11259 UNSPEC_TLSDTPREL))]
11260 "HAVE_AS_TLS"
11261 "addi %0,%1,%2@dtprel")
11263 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11264 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11265 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11266 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11267 UNSPEC_TLSDTPRELHA))]
11268 "HAVE_AS_TLS"
11269 "addis %0,%1,%2@dtprel@ha")
11271 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11272 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11273 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11274 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11275 UNSPEC_TLSDTPRELLO))]
11276 "HAVE_AS_TLS"
11277 "addi %0,%1,%2@dtprel@l")
11279 (define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11280 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11281 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11282 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11283 UNSPEC_TLSGOTDTPREL))]
11284 "HAVE_AS_TLS"
11285 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
11287 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11288 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11289 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11290 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11291 UNSPEC_TLSTPREL))]
11292 "HAVE_AS_TLS"
11293 "addi %0,%1,%2@tprel")
11295 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11296 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11297 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11298 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11299 UNSPEC_TLSTPRELHA))]
11300 "HAVE_AS_TLS"
11301 "addis %0,%1,%2@tprel@ha")
11303 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11304 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11305 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11306 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11307 UNSPEC_TLSTPRELLO))]
11308 "HAVE_AS_TLS"
11309 "addi %0,%1,%2@tprel@l")
11311 ;; "b" output constraint here and on tls_tls input to support linker tls
11312 ;; optimization. The linker may edit the instructions emitted by a
11313 ;; tls_got_tprel/tls_tls pair to addis,addi.
11314 (define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11315 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11316 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11317 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11318 UNSPEC_TLSGOTTPREL))]
11319 "HAVE_AS_TLS"
11320 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
11322 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11323 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11324 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11325 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11326 UNSPEC_TLSTLS))]
11327 "HAVE_AS_TLS"
11328 "add %0,%1,%2@tls")
11330 \f
11331 ;; Next come insns related to the calling sequence.
11332 ;;
11333 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11334 ;; We move the back-chain and decrement the stack pointer.
11336 (define_expand "allocate_stack"
11337 [(set (match_operand 0 "gpc_reg_operand" "")
11338 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11339 (set (reg 1)
11340 (minus (reg 1) (match_dup 1)))]
11341 ""
11342 "
11343 { rtx chain = gen_reg_rtx (Pmode);
11344 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11345 rtx neg_op0;
11346 rtx insn, par, set, mem;
11348 emit_move_insn (chain, stack_bot);
11350 /* Check stack bounds if necessary. */
11351 if (crtl->limit_stack)
11352 {
11353 rtx available;
11354 available = expand_binop (Pmode, sub_optab,
11355 stack_pointer_rtx, stack_limit_rtx,
11356 NULL_RTX, 1, OPTAB_WIDEN);
11357 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11358 }
11360 if (GET_CODE (operands[1]) != CONST_INT
11361 || INTVAL (operands[1]) < -32767
11362 || INTVAL (operands[1]) > 32768)
11363 {
11364 neg_op0 = gen_reg_rtx (Pmode);
11365 if (TARGET_32BIT)
11366 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11367 else
11368 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11369 }
11370 else
11371 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11373 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11374 : gen_movdi_di_update_stack))
11375 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11376 chain));
11377 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11378 it now and set the alias set/attributes. The above gen_*_update
11379 calls will generate a PARALLEL with the MEM set being the first
11380 operation. */
11381 par = PATTERN (insn);
11382 gcc_assert (GET_CODE (par) == PARALLEL);
11383 set = XVECEXP (par, 0, 0);
11384 gcc_assert (GET_CODE (set) == SET);
11385 mem = SET_DEST (set);
11386 gcc_assert (MEM_P (mem));
11387 MEM_NOTRAP_P (mem) = 1;
11388 set_mem_alias_set (mem, get_frame_alias_set ());
11390 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11391 DONE;
11392 }")
11394 ;; These patterns say how to save and restore the stack pointer. We need not
11395 ;; save the stack pointer at function level since we are careful to
11396 ;; preserve the backchain. At block level, we have to restore the backchain
11397 ;; when we restore the stack pointer.
11398 ;;
11399 ;; For nonlocal gotos, we must save both the stack pointer and its
11400 ;; backchain and restore both. Note that in the nonlocal case, the
11401 ;; save area is a memory location.
11403 (define_expand "save_stack_function"
11404 [(match_operand 0 "any_operand" "")
11405 (match_operand 1 "any_operand" "")]
11406 ""
11407 "DONE;")
11409 (define_expand "restore_stack_function"
11410 [(match_operand 0 "any_operand" "")
11411 (match_operand 1 "any_operand" "")]
11412 ""
11413 "DONE;")
11415 ;; Adjust stack pointer (op0) to a new value (op1).
11416 ;; First copy old stack backchain to new location, and ensure that the
11417 ;; scheduler won't reorder the sp assignment before the backchain write.
11418 (define_expand "restore_stack_block"
11419 [(set (match_dup 2) (match_dup 3))
11420 (set (match_dup 4) (match_dup 2))
11421 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
11422 (set (match_operand 0 "register_operand" "")
11423 (match_operand 1 "register_operand" ""))]
11424 ""
11425 "
11426 {
11427 operands[1] = force_reg (Pmode, operands[1]);
11428 operands[2] = gen_reg_rtx (Pmode);
11429 operands[3] = gen_frame_mem (Pmode, operands[0]);
11430 operands[4] = gen_frame_mem (Pmode, operands[1]);
11431 operands[5] = gen_frame_mem (BLKmode, operands[0]);
11432 }")
11434 (define_expand "save_stack_nonlocal"
11435 [(set (match_dup 3) (match_dup 4))
11436 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11437 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11438 ""
11439 "
11440 {
11441 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11443 /* Copy the backchain to the first word, sp to the second. */
11444 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11445 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11446 operands[3] = gen_reg_rtx (Pmode);
11447 operands[4] = gen_frame_mem (Pmode, operands[1]);
11448 }")
11450 (define_expand "restore_stack_nonlocal"
11451 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11452 (set (match_dup 3) (match_dup 4))
11453 (set (match_dup 5) (match_dup 2))
11454 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
11455 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11456 ""
11457 "
11458 {
11459 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11461 /* Restore the backchain from the first word, sp from the second. */
11462 operands[2] = gen_reg_rtx (Pmode);
11463 operands[3] = gen_reg_rtx (Pmode);
11464 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11465 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11466 operands[5] = gen_frame_mem (Pmode, operands[3]);
11467 operands[6] = gen_frame_mem (BLKmode, operands[0]);
11468 }")
11469 \f
11470 ;; TOC register handling.
11472 ;; Code to initialize the TOC register...
11474 (define_insn "load_toc_aix_si"
11475 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11476 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11477 (use (reg:SI 2))])]
11478 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11479 "*
11480 {
11481 char buf[30];
11482 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11483 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11484 operands[2] = gen_rtx_REG (Pmode, 2);
11485 return \"{l|lwz} %0,%1(%2)\";
11486 }"
11487 [(set_attr "type" "load")])
11489 (define_insn "load_toc_aix_di"
11490 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11491 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11492 (use (reg:DI 2))])]
11493 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
11494 "*
11495 {
11496 char buf[30];
11497 #ifdef TARGET_RELOCATABLE
11498 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11499 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11500 #else
11501 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11502 #endif
11503 if (TARGET_ELF)
11504 strcat (buf, \"@toc\");
11505 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11506 operands[2] = gen_rtx_REG (Pmode, 2);
11507 return \"ld %0,%1(%2)\";
11508 }"
11509 [(set_attr "type" "load")])
11511 (define_insn "load_toc_v4_pic_si"
11512 [(set (reg:SI LR_REGNO)
11513 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11514 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11515 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11516 [(set_attr "type" "branch")
11517 (set_attr "length" "4")])
11519 (define_insn "load_toc_v4_PIC_1"
11520 [(set (reg:SI LR_REGNO)
11521 (match_operand:SI 0 "immediate_operand" "s"))
11522 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11523 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
11524 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11525 "bcl 20,31,%0\\n%0:"
11526 [(set_attr "type" "branch")
11527 (set_attr "length" "4")])
11529 (define_insn "load_toc_v4_PIC_1b"
11530 [(set (reg:SI LR_REGNO)
11531 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
11532 UNSPEC_TOCPTR))]
11533 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11534 "bcl 20,31,$+8\\n\\t.long %0-$"
11535 [(set_attr "type" "branch")
11536 (set_attr "length" "8")])
11538 (define_insn "load_toc_v4_PIC_2"
11539 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11540 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11541 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11542 (match_operand:SI 3 "immediate_operand" "s")))))]
11543 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11544 "{l|lwz} %0,%2-%3(%1)"
11545 [(set_attr "type" "load")])
11547 (define_insn "load_toc_v4_PIC_3b"
11548 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
11549 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11550 (high:SI
11551 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11552 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11553 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11554 "{cau|addis} %0,%1,%2-%3@ha")
11556 (define_insn "load_toc_v4_PIC_3c"
11557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11558 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11559 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11560 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11561 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11562 "{cal %0,%2-%3@l(%1)|addi %0,%1,%2-%3@l}")
11564 ;; If the TOC is shared over a translation unit, as happens with all
11565 ;; the kinds of PIC that we support, we need to restore the TOC
11566 ;; pointer only when jumping over units of translation.
11567 ;; On Darwin, we need to reload the picbase.
11569 (define_expand "builtin_setjmp_receiver"
11570 [(use (label_ref (match_operand 0 "" "")))]
11571 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11572 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11573 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11574 "
11575 {
11576 #if TARGET_MACHO
11577 if (DEFAULT_ABI == ABI_DARWIN)
11578 {
11579 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11580 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11581 rtx tmplabrtx;
11582 char tmplab[20];
11584 crtl->uses_pic_offset_table = 1;
11585 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11586 CODE_LABEL_NUMBER (operands[0]));
11587 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11589 emit_insn (gen_load_macho_picbase (tmplabrtx));
11590 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11591 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11592 }
11593 else
11594 #endif
11595 rs6000_emit_load_toc_table (FALSE);
11596 DONE;
11597 }")
11599 ;; Elf specific ways of loading addresses for non-PIC code.
11600 ;; The output of this could be r0, but we make a very strong
11601 ;; preference for a base register because it will usually
11602 ;; be needed there.
11603 (define_insn "elf_high"
11604 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11605 (high:SI (match_operand 1 "" "")))]
11606 "TARGET_ELF && ! TARGET_64BIT"
11607 "{liu|lis} %0,%1@ha")
11609 (define_insn "elf_low"
11610 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11611 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11612 (match_operand 2 "" "")))]
11613 "TARGET_ELF && ! TARGET_64BIT"
11614 "@
11615 {cal|la} %0,%2@l(%1)
11616 {ai|addic} %0,%1,%K2")
11617 \f
11618 ;; A function pointer under AIX is a pointer to a data area whose first word
11619 ;; contains the actual address of the function, whose second word contains a
11620 ;; pointer to its TOC, and whose third word contains a value to place in the
11621 ;; static chain register (r11). Note that if we load the static chain, our
11622 ;; "trampoline" need not have any executable code.
11624 (define_expand "call_indirect_aix32"
11625 [(set (match_dup 2)
11626 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
11627 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11628 (reg:SI 2))
11629 (set (reg:SI 11)
11630 (mem:SI (plus:SI (match_dup 0)
11631 (const_int 8))))
11632 (parallel [(call (mem:SI (match_dup 2))
11633 (match_operand 1 "" ""))
11634 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
11635 (use (reg:SI 11))
11636 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11637 (clobber (reg:SI LR_REGNO))])]
11638 "TARGET_32BIT"
11639 "
11640 { operands[2] = gen_reg_rtx (SImode); }")
11642 (define_expand "call_indirect_aix64"
11643 [(set (match_dup 2)
11644 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
11645 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11646 (reg:DI 2))
11647 (set (reg:DI 11)
11648 (mem:DI (plus:DI (match_dup 0)
11649 (const_int 16))))
11650 (parallel [(call (mem:SI (match_dup 2))
11651 (match_operand 1 "" ""))
11652 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
11653 (use (reg:DI 11))
11654 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11655 (clobber (reg:SI LR_REGNO))])]
11656 "TARGET_64BIT"
11657 "
11658 { operands[2] = gen_reg_rtx (DImode); }")
11660 (define_expand "call_value_indirect_aix32"
11661 [(set (match_dup 3)
11662 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11663 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11664 (reg:SI 2))
11665 (set (reg:SI 11)
11666 (mem:SI (plus:SI (match_dup 1)
11667 (const_int 8))))
11668 (parallel [(set (match_operand 0 "" "")
11669 (call (mem:SI (match_dup 3))
11670 (match_operand 2 "" "")))
11671 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
11672 (use (reg:SI 11))
11673 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11674 (clobber (reg:SI LR_REGNO))])]
11675 "TARGET_32BIT"
11676 "
11677 { operands[3] = gen_reg_rtx (SImode); }")
11679 (define_expand "call_value_indirect_aix64"
11680 [(set (match_dup 3)
11681 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11682 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11683 (reg:DI 2))
11684 (set (reg:DI 11)
11685 (mem:DI (plus:DI (match_dup 1)
11686 (const_int 16))))
11687 (parallel [(set (match_operand 0 "" "")
11688 (call (mem:SI (match_dup 3))
11689 (match_operand 2 "" "")))
11690 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
11691 (use (reg:DI 11))
11692 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11693 (clobber (reg:SI LR_REGNO))])]
11694 "TARGET_64BIT"
11695 "
11696 { operands[3] = gen_reg_rtx (DImode); }")
11698 ;; Now the definitions for the call and call_value insns
11699 (define_expand "call"
11700 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11701 (match_operand 1 "" ""))
11702 (use (match_operand 2 "" ""))
11703 (clobber (reg:SI LR_REGNO))])]
11704 ""
11705 "
11706 {
11707 #if TARGET_MACHO
11708 if (MACHOPIC_INDIRECT)
11709 operands[0] = machopic_indirect_call_target (operands[0]);
11710 #endif
11712 gcc_assert (GET_CODE (operands[0]) == MEM);
11713 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11715 operands[0] = XEXP (operands[0], 0);
11717 if (GET_CODE (operands[0]) != SYMBOL_REF
11718 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
11719 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11720 {
11721 if (INTVAL (operands[2]) & CALL_LONG)
11722 operands[0] = rs6000_longcall_ref (operands[0]);
11724 switch (DEFAULT_ABI)
11725 {
11726 case ABI_V4:
11727 case ABI_DARWIN:
11728 operands[0] = force_reg (Pmode, operands[0]);
11729 break;
11731 case ABI_AIX:
11732 /* AIX function pointers are really pointers to a three word
11733 area. */
11734 emit_call_insn (TARGET_32BIT
11735 ? gen_call_indirect_aix32 (force_reg (SImode,
11736 operands[0]),
11737 operands[1])
11738 : gen_call_indirect_aix64 (force_reg (DImode,
11739 operands[0]),
11740 operands[1]));
11741 DONE;
11743 default:
11744 gcc_unreachable ();
11745 }
11746 }
11747 }")
11749 (define_expand "call_value"
11750 [(parallel [(set (match_operand 0 "" "")
11751 (call (mem:SI (match_operand 1 "address_operand" ""))
11752 (match_operand 2 "" "")))
11753 (use (match_operand 3 "" ""))
11754 (clobber (reg:SI LR_REGNO))])]
11755 ""
11756 "
11757 {
11758 #if TARGET_MACHO
11759 if (MACHOPIC_INDIRECT)
11760 operands[1] = machopic_indirect_call_target (operands[1]);
11761 #endif
11763 gcc_assert (GET_CODE (operands[1]) == MEM);
11764 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11766 operands[1] = XEXP (operands[1], 0);
11768 if (GET_CODE (operands[1]) != SYMBOL_REF
11769 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
11770 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11771 {
11772 if (INTVAL (operands[3]) & CALL_LONG)
11773 operands[1] = rs6000_longcall_ref (operands[1]);
11775 switch (DEFAULT_ABI)
11776 {
11777 case ABI_V4:
11778 case ABI_DARWIN:
11779 operands[1] = force_reg (Pmode, operands[1]);
11780 break;
11782 case ABI_AIX:
11783 /* AIX function pointers are really pointers to a three word
11784 area. */
11785 emit_call_insn (TARGET_32BIT
11786 ? gen_call_value_indirect_aix32 (operands[0],
11787 force_reg (SImode,
11788 operands[1]),
11789 operands[2])
11790 : gen_call_value_indirect_aix64 (operands[0],
11791 force_reg (DImode,
11792 operands[1]),
11793 operands[2]));
11794 DONE;
11796 default:
11797 gcc_unreachable ();
11798 }
11799 }
11800 }")
11802 ;; Call to function in current module. No TOC pointer reload needed.
11803 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11804 ;; either the function was not prototyped, or it was prototyped as a
11805 ;; variable argument function. It is > 0 if FP registers were passed
11806 ;; and < 0 if they were not.
11808 (define_insn "*call_local32"
11809 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11810 (match_operand 1 "" "g,g"))
11811 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11812 (clobber (reg:SI LR_REGNO))]
11813 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11814 "*
11815 {
11816 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11817 output_asm_insn (\"crxor 6,6,6\", operands);
11819 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11820 output_asm_insn (\"creqv 6,6,6\", operands);
11822 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11823 }"
11824 [(set_attr "type" "branch")
11825 (set_attr "length" "4,8")])
11827 (define_insn "*call_local64"
11828 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11829 (match_operand 1 "" "g,g"))
11830 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11831 (clobber (reg:SI LR_REGNO))]
11832 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11833 "*
11834 {
11835 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11836 output_asm_insn (\"crxor 6,6,6\", operands);
11838 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11839 output_asm_insn (\"creqv 6,6,6\", operands);
11841 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11842 }"
11843 [(set_attr "type" "branch")
11844 (set_attr "length" "4,8")])
11846 (define_insn "*call_value_local32"
11847 [(set (match_operand 0 "" "")
11848 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11849 (match_operand 2 "" "g,g")))
11850 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11851 (clobber (reg:SI LR_REGNO))]
11852 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11853 "*
11854 {
11855 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11856 output_asm_insn (\"crxor 6,6,6\", operands);
11858 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11859 output_asm_insn (\"creqv 6,6,6\", operands);
11861 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11862 }"
11863 [(set_attr "type" "branch")
11864 (set_attr "length" "4,8")])
11867 (define_insn "*call_value_local64"
11868 [(set (match_operand 0 "" "")
11869 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11870 (match_operand 2 "" "g,g")))
11871 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11872 (clobber (reg:SI LR_REGNO))]
11873 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11874 "*
11875 {
11876 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11877 output_asm_insn (\"crxor 6,6,6\", operands);
11879 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11880 output_asm_insn (\"creqv 6,6,6\", operands);
11882 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11883 }"
11884 [(set_attr "type" "branch")
11885 (set_attr "length" "4,8")])
11887 ;; Call to function which may be in another module. Restore the TOC
11888 ;; pointer (r2) after the call unless this is System V.
11889 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11890 ;; either the function was not prototyped, or it was prototyped as a
11891 ;; variable argument function. It is > 0 if FP registers were passed
11892 ;; and < 0 if they were not.
11894 (define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
11895 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11896 (match_operand 1 "" "g,g"))
11897 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
11898 (use (reg:SI 11))
11899 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11900 (clobber (reg:SI LR_REGNO))]
11901 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11902 "#"
11903 "&& reload_completed"
11904 [(set (reg:SI 2)
11905 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
11906 (parallel [(call (mem:SI (match_dup 0))
11907 (match_dup 1))
11908 (use (reg:SI 2))
11909 (use (reg:SI 11))
11910 (set (reg:SI 2)
11911 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11912 (clobber (reg:SI LR_REGNO))])]
11913 ""
11914 [(set_attr "type" "jmpreg")
11915 (set_attr "length" "12")])
11917 (define_insn "*call_indirect_nonlocal_aix32"
11918 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11919 (match_operand 1 "" "g,g"))
11920 (use (reg:SI 2))
11921 (use (reg:SI 11))
11922 (set (reg:SI 2)
11923 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11924 (clobber (reg:SI LR_REGNO))]
11925 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11926 "b%T0l\;{l|lwz} 2,20(1)"
11927 [(set_attr "type" "jmpreg")
11928 (set_attr "length" "8")])
11930 (define_insn "*call_nonlocal_aix32"
11931 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11932 (match_operand 1 "" "g"))
11933 (use (match_operand:SI 2 "immediate_operand" "O"))
11934 (clobber (reg:SI LR_REGNO))]
11935 "TARGET_32BIT
11936 && DEFAULT_ABI == ABI_AIX
11937 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11938 "bl %z0\;%."
11939 [(set_attr "type" "branch")
11940 (set_attr "length" "8")])
11942 (define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
11943 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11944 (match_operand 1 "" "g,g"))
11945 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
11946 (const_int 8))))
11947 (use (reg:DI 11))
11948 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11949 (clobber (reg:SI LR_REGNO))]
11950 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11951 "#"
11952 "&& reload_completed"
11953 [(set (reg:DI 2)
11954 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
11955 (parallel [(call (mem:SI (match_dup 0))
11956 (match_dup 1))
11957 (use (reg:DI 2))
11958 (use (reg:DI 11))
11959 (set (reg:DI 2)
11960 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11961 (clobber (reg:SI LR_REGNO))])]
11962 ""
11963 [(set_attr "type" "jmpreg")
11964 (set_attr "length" "12")])
11966 (define_insn "*call_indirect_nonlocal_aix64"
11967 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11968 (match_operand 1 "" "g,g"))
11969 (use (reg:DI 2))
11970 (use (reg:DI 11))
11971 (set (reg:DI 2)
11972 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11973 (clobber (reg:SI LR_REGNO))]
11974 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11975 "b%T0l\;ld 2,40(1)"
11976 [(set_attr "type" "jmpreg")
11977 (set_attr "length" "8")])
11979 (define_insn "*call_nonlocal_aix64"
11980 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11981 (match_operand 1 "" "g"))
11982 (use (match_operand:SI 2 "immediate_operand" "O"))
11983 (clobber (reg:SI LR_REGNO))]
11984 "TARGET_64BIT
11985 && DEFAULT_ABI == ABI_AIX
11986 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11987 "bl %z0\;%."
11988 [(set_attr "type" "branch")
11989 (set_attr "length" "8")])
11991 (define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
11992 [(set (match_operand 0 "" "")
11993 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11994 (match_operand 2 "" "g,g")))
11995 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
11996 (const_int 4))))
11997 (use (reg:SI 11))
11998 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11999 (clobber (reg:SI LR_REGNO))]
12000 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
12001 "#"
12002 "&& reload_completed"
12003 [(set (reg:SI 2)
12004 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
12005 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
12006 (match_dup 2)))
12007 (use (reg:SI 2))
12008 (use (reg:SI 11))
12009 (set (reg:SI 2)
12010 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12011 (clobber (reg:SI LR_REGNO))])]
12012 ""
12013 [(set_attr "type" "jmpreg")
12014 (set_attr "length" "12")])
12016 (define_insn "*call_value_indirect_nonlocal_aix32"
12017 [(set (match_operand 0 "" "")
12018 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
12019 (match_operand 2 "" "g,g")))
12020 (use (reg:SI 2))
12021 (use (reg:SI 11))
12022 (set (reg:SI 2)
12023 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12024 (clobber (reg:SI LR_REGNO))]
12025 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12026 "b%T1l\;{l|lwz} 2,20(1)"
12027 [(set_attr "type" "jmpreg")
12028 (set_attr "length" "8")])
12030 (define_insn "*call_value_nonlocal_aix32"
12031 [(set (match_operand 0 "" "")
12032 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12033 (match_operand 2 "" "g")))
12034 (use (match_operand:SI 3 "immediate_operand" "O"))
12035 (clobber (reg:SI LR_REGNO))]
12036 "TARGET_32BIT
12037 && DEFAULT_ABI == ABI_AIX
12038 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12039 "bl %z1\;%."
12040 [(set_attr "type" "branch")
12041 (set_attr "length" "8")])
12043 (define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
12044 [(set (match_operand 0 "" "")
12045 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
12046 (match_operand 2 "" "g,g")))
12047 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
12048 (const_int 8))))
12049 (use (reg:DI 11))
12050 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12051 (clobber (reg:SI LR_REGNO))]
12052 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
12053 "#"
12054 "&& reload_completed"
12055 [(set (reg:DI 2)
12056 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
12057 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
12058 (match_dup 2)))
12059 (use (reg:DI 2))
12060 (use (reg:DI 11))
12061 (set (reg:DI 2)
12062 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12063 (clobber (reg:SI LR_REGNO))])]
12064 ""
12065 [(set_attr "type" "jmpreg")
12066 (set_attr "length" "12")])
12068 (define_insn "*call_value_indirect_nonlocal_aix64"
12069 [(set (match_operand 0 "" "")
12070 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
12071 (match_operand 2 "" "g,g")))
12072 (use (reg:DI 2))
12073 (use (reg:DI 11))
12074 (set (reg:DI 2)
12075 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12076 (clobber (reg:SI LR_REGNO))]
12077 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12078 "b%T1l\;ld 2,40(1)"
12079 [(set_attr "type" "jmpreg")
12080 (set_attr "length" "8")])
12082 (define_insn "*call_value_nonlocal_aix64"
12083 [(set (match_operand 0 "" "")
12084 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12085 (match_operand 2 "" "g")))
12086 (use (match_operand:SI 3 "immediate_operand" "O"))
12087 (clobber (reg:SI LR_REGNO))]
12088 "TARGET_64BIT
12089 && DEFAULT_ABI == ABI_AIX
12090 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12091 "bl %z1\;%."
12092 [(set_attr "type" "branch")
12093 (set_attr "length" "8")])
12095 ;; A function pointer under System V is just a normal pointer
12096 ;; operands[0] is the function pointer
12097 ;; operands[1] is the stack size to clean up
12098 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12099 ;; which indicates how to set cr1
12101 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12102 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12103 (match_operand 1 "" "g,g,g,g"))
12104 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12105 (clobber (reg:SI LR_REGNO))]
12106 "DEFAULT_ABI == ABI_V4
12107 || DEFAULT_ABI == ABI_DARWIN"
12108 {
12109 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12110 output_asm_insn ("crxor 6,6,6", operands);
12112 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12113 output_asm_insn ("creqv 6,6,6", operands);
12115 return "b%T0l";
12116 }
12117 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12118 (set_attr "length" "4,4,8,8")])
12120 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12121 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12122 (match_operand 1 "" "g,g"))
12123 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12124 (clobber (reg:SI LR_REGNO))]
12125 "(DEFAULT_ABI == ABI_DARWIN
12126 || (DEFAULT_ABI == ABI_V4
12127 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12128 {
12129 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12130 output_asm_insn ("crxor 6,6,6", operands);
12132 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12133 output_asm_insn ("creqv 6,6,6", operands);
12135 #if TARGET_MACHO
12136 return output_call(insn, operands, 0, 2);
12137 #else
12138 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12139 {
12140 gcc_assert (!TARGET_SECURE_PLT);
12141 return "bl %z0@plt";
12142 }
12143 else
12144 return "bl %z0";
12145 #endif
12146 }
12147 "DEFAULT_ABI == ABI_V4
12148 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12149 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12150 [(parallel [(call (mem:SI (match_dup 0))
12151 (match_dup 1))
12152 (use (match_dup 2))
12153 (use (match_dup 3))
12154 (clobber (reg:SI LR_REGNO))])]
12155 {
12156 operands[3] = pic_offset_table_rtx;
12157 }
12158 [(set_attr "type" "branch,branch")
12159 (set_attr "length" "4,8")])
12161 (define_insn "*call_nonlocal_sysv_secure<mode>"
12162 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12163 (match_operand 1 "" "g,g"))
12164 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12165 (use (match_operand:SI 3 "register_operand" "r,r"))
12166 (clobber (reg:SI LR_REGNO))]
12167 "(DEFAULT_ABI == ABI_V4
12168 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12169 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12170 {
12171 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12172 output_asm_insn ("crxor 6,6,6", operands);
12174 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12175 output_asm_insn ("creqv 6,6,6", operands);
12177 if (flag_pic == 2)
12178 /* The magic 32768 offset here and in the other sysv call insns
12179 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12180 See sysv4.h:toc_section. */
12181 return "bl %z0+32768@plt";
12182 else
12183 return "bl %z0@plt";
12184 }
12185 [(set_attr "type" "branch,branch")
12186 (set_attr "length" "4,8")])
12188 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12189 [(set (match_operand 0 "" "")
12190 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12191 (match_operand 2 "" "g,g,g,g")))
12192 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12193 (clobber (reg:SI LR_REGNO))]
12194 "DEFAULT_ABI == ABI_V4
12195 || DEFAULT_ABI == ABI_DARWIN"
12196 {
12197 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12198 output_asm_insn ("crxor 6,6,6", operands);
12200 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12201 output_asm_insn ("creqv 6,6,6", operands);
12203 return "b%T1l";
12204 }
12205 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12206 (set_attr "length" "4,4,8,8")])
12208 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12209 [(set (match_operand 0 "" "")
12210 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12211 (match_operand 2 "" "g,g")))
12212 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12213 (clobber (reg:SI LR_REGNO))]
12214 "(DEFAULT_ABI == ABI_DARWIN
12215 || (DEFAULT_ABI == ABI_V4
12216 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12217 {
12218 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12219 output_asm_insn ("crxor 6,6,6", operands);
12221 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12222 output_asm_insn ("creqv 6,6,6", operands);
12224 #if TARGET_MACHO
12225 return output_call(insn, operands, 1, 3);
12226 #else
12227 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12228 {
12229 gcc_assert (!TARGET_SECURE_PLT);
12230 return "bl %z1@plt";
12231 }
12232 else
12233 return "bl %z1";
12234 #endif
12235 }
12236 "DEFAULT_ABI == ABI_V4
12237 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12238 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12239 [(parallel [(set (match_dup 0)
12240 (call (mem:SI (match_dup 1))
12241 (match_dup 2)))
12242 (use (match_dup 3))
12243 (use (match_dup 4))
12244 (clobber (reg:SI LR_REGNO))])]
12245 {
12246 operands[4] = pic_offset_table_rtx;
12247 }
12248 [(set_attr "type" "branch,branch")
12249 (set_attr "length" "4,8")])
12251 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12252 [(set (match_operand 0 "" "")
12253 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12254 (match_operand 2 "" "g,g")))
12255 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12256 (use (match_operand:SI 4 "register_operand" "r,r"))
12257 (clobber (reg:SI LR_REGNO))]
12258 "(DEFAULT_ABI == ABI_V4
12259 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12260 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12261 {
12262 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12263 output_asm_insn ("crxor 6,6,6", operands);
12265 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12266 output_asm_insn ("creqv 6,6,6", operands);
12268 if (flag_pic == 2)
12269 return "bl %z1+32768@plt";
12270 else
12271 return "bl %z1@plt";
12272 }
12273 [(set_attr "type" "branch,branch")
12274 (set_attr "length" "4,8")])
12276 ;; Call subroutine returning any type.
12277 (define_expand "untyped_call"
12278 [(parallel [(call (match_operand 0 "" "")
12279 (const_int 0))
12280 (match_operand 1 "" "")
12281 (match_operand 2 "" "")])]
12282 ""
12283 "
12284 {
12285 int i;
12287 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12289 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12290 {
12291 rtx set = XVECEXP (operands[2], 0, i);
12292 emit_move_insn (SET_DEST (set), SET_SRC (set));
12293 }
12295 /* The optimizer does not know that the call sets the function value
12296 registers we stored in the result block. We avoid problems by
12297 claiming that all hard registers are used and clobbered at this
12298 point. */
12299 emit_insn (gen_blockage ());
12301 DONE;
12302 }")
12304 ;; sibling call patterns
12305 (define_expand "sibcall"
12306 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12307 (match_operand 1 "" ""))
12308 (use (match_operand 2 "" ""))
12309 (use (reg:SI LR_REGNO))
12310 (return)])]
12311 ""
12312 "
12313 {
12314 #if TARGET_MACHO
12315 if (MACHOPIC_INDIRECT)
12316 operands[0] = machopic_indirect_call_target (operands[0]);
12317 #endif
12319 gcc_assert (GET_CODE (operands[0]) == MEM);
12320 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12322 operands[0] = XEXP (operands[0], 0);
12323 }")
12325 ;; this and similar patterns must be marked as using LR, otherwise
12326 ;; dataflow will try to delete the store into it. This is true
12327 ;; even when the actual reg to jump to is in CTR, when LR was
12328 ;; saved and restored around the PIC-setting BCL.
12329 (define_insn "*sibcall_local32"
12330 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12331 (match_operand 1 "" "g,g"))
12332 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12333 (use (reg:SI LR_REGNO))
12334 (return)]
12335 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12336 "*
12337 {
12338 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12339 output_asm_insn (\"crxor 6,6,6\", operands);
12341 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12342 output_asm_insn (\"creqv 6,6,6\", operands);
12344 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12345 }"
12346 [(set_attr "type" "branch")
12347 (set_attr "length" "4,8")])
12349 (define_insn "*sibcall_local64"
12350 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12351 (match_operand 1 "" "g,g"))
12352 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12353 (use (reg:SI LR_REGNO))
12354 (return)]
12355 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12356 "*
12357 {
12358 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12359 output_asm_insn (\"crxor 6,6,6\", operands);
12361 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12362 output_asm_insn (\"creqv 6,6,6\", operands);
12364 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12365 }"
12366 [(set_attr "type" "branch")
12367 (set_attr "length" "4,8")])
12369 (define_insn "*sibcall_value_local32"
12370 [(set (match_operand 0 "" "")
12371 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12372 (match_operand 2 "" "g,g")))
12373 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12374 (use (reg:SI LR_REGNO))
12375 (return)]
12376 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12377 "*
12378 {
12379 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12380 output_asm_insn (\"crxor 6,6,6\", operands);
12382 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12383 output_asm_insn (\"creqv 6,6,6\", operands);
12385 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12386 }"
12387 [(set_attr "type" "branch")
12388 (set_attr "length" "4,8")])
12391 (define_insn "*sibcall_value_local64"
12392 [(set (match_operand 0 "" "")
12393 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12394 (match_operand 2 "" "g,g")))
12395 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12396 (use (reg:SI LR_REGNO))
12397 (return)]
12398 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12399 "*
12400 {
12401 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12402 output_asm_insn (\"crxor 6,6,6\", operands);
12404 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12405 output_asm_insn (\"creqv 6,6,6\", operands);
12407 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12408 }"
12409 [(set_attr "type" "branch")
12410 (set_attr "length" "4,8")])
12412 (define_insn "*sibcall_nonlocal_aix32"
12413 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12414 (match_operand 1 "" "g"))
12415 (use (match_operand:SI 2 "immediate_operand" "O"))
12416 (use (reg:SI LR_REGNO))
12417 (return)]
12418 "TARGET_32BIT
12419 && DEFAULT_ABI == ABI_AIX
12420 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12421 "b %z0"
12422 [(set_attr "type" "branch")
12423 (set_attr "length" "4")])
12425 (define_insn "*sibcall_nonlocal_aix64"
12426 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12427 (match_operand 1 "" "g"))
12428 (use (match_operand:SI 2 "immediate_operand" "O"))
12429 (use (reg:SI LR_REGNO))
12430 (return)]
12431 "TARGET_64BIT
12432 && DEFAULT_ABI == ABI_AIX
12433 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12434 "b %z0"
12435 [(set_attr "type" "branch")
12436 (set_attr "length" "4")])
12438 (define_insn "*sibcall_value_nonlocal_aix32"
12439 [(set (match_operand 0 "" "")
12440 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12441 (match_operand 2 "" "g")))
12442 (use (match_operand:SI 3 "immediate_operand" "O"))
12443 (use (reg:SI LR_REGNO))
12444 (return)]
12445 "TARGET_32BIT
12446 && DEFAULT_ABI == ABI_AIX
12447 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12448 "b %z1"
12449 [(set_attr "type" "branch")
12450 (set_attr "length" "4")])
12452 (define_insn "*sibcall_value_nonlocal_aix64"
12453 [(set (match_operand 0 "" "")
12454 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12455 (match_operand 2 "" "g")))
12456 (use (match_operand:SI 3 "immediate_operand" "O"))
12457 (use (reg:SI LR_REGNO))
12458 (return)]
12459 "TARGET_64BIT
12460 && DEFAULT_ABI == ABI_AIX
12461 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12462 "b %z1"
12463 [(set_attr "type" "branch")
12464 (set_attr "length" "4")])
12466 (define_insn "*sibcall_nonlocal_sysv<mode>"
12467 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12468 (match_operand 1 "" ""))
12469 (use (match_operand 2 "immediate_operand" "O,n"))
12470 (use (reg:SI LR_REGNO))
12471 (return)]
12472 "(DEFAULT_ABI == ABI_DARWIN
12473 || DEFAULT_ABI == ABI_V4)
12474 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12475 "*
12476 {
12477 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12478 output_asm_insn (\"crxor 6,6,6\", operands);
12480 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12481 output_asm_insn (\"creqv 6,6,6\", operands);
12483 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12484 {
12485 gcc_assert (!TARGET_SECURE_PLT);
12486 return \"b %z0@plt\";
12487 }
12488 else
12489 return \"b %z0\";
12490 }"
12491 [(set_attr "type" "branch,branch")
12492 (set_attr "length" "4,8")])
12494 (define_expand "sibcall_value"
12495 [(parallel [(set (match_operand 0 "register_operand" "")
12496 (call (mem:SI (match_operand 1 "address_operand" ""))
12497 (match_operand 2 "" "")))
12498 (use (match_operand 3 "" ""))
12499 (use (reg:SI LR_REGNO))
12500 (return)])]
12501 ""
12502 "
12503 {
12504 #if TARGET_MACHO
12505 if (MACHOPIC_INDIRECT)
12506 operands[1] = machopic_indirect_call_target (operands[1]);
12507 #endif
12509 gcc_assert (GET_CODE (operands[1]) == MEM);
12510 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12512 operands[1] = XEXP (operands[1], 0);
12513 }")
12515 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12516 [(set (match_operand 0 "" "")
12517 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12518 (match_operand 2 "" "")))
12519 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12520 (use (reg:SI LR_REGNO))
12521 (return)]
12522 "(DEFAULT_ABI == ABI_DARWIN
12523 || DEFAULT_ABI == ABI_V4)
12524 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12525 "*
12526 {
12527 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12528 output_asm_insn (\"crxor 6,6,6\", operands);
12530 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12531 output_asm_insn (\"creqv 6,6,6\", operands);
12533 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12534 {
12535 gcc_assert (!TARGET_SECURE_PLT);
12536 return \"b %z1@plt\";
12537 }
12538 else
12539 return \"b %z1\";
12540 }"
12541 [(set_attr "type" "branch,branch")
12542 (set_attr "length" "4,8")])
12544 (define_expand "sibcall_epilogue"
12545 [(use (const_int 0))]
12546 "TARGET_SCHED_PROLOG"
12547 "
12548 {
12549 rs6000_emit_epilogue (TRUE);
12550 DONE;
12551 }")
12553 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12554 ;; all of memory. This blocks insns from being moved across this point.
12556 (define_insn "blockage"
12557 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12558 ""
12559 "")
12561 (define_insn "probe_stack"
12562 [(set (match_operand 0 "memory_operand" "=m")
12563 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
12564 ""
12565 "{st%U0%X0|stw%U0%X0} 0,%0"
12566 [(set_attr "type" "store")
12567 (set_attr "length" "4")])
12568 \f
12569 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12570 ;; signed & unsigned, and one type of branch.
12571 ;;
12572 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12573 ;; insns, and branches.
12575 (define_expand "cbranch<mode>4"
12576 [(use (match_operator 0 "rs6000_cbranch_operator"
12577 [(match_operand:GPR 1 "gpc_reg_operand" "")
12578 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12579 (use (match_operand 3 ""))]
12580 ""
12581 "
12582 {
12583 /* Take care of the possibility that operands[2] might be negative but
12584 this might be a logical operation. That insn doesn't exist. */
12585 if (GET_CODE (operands[2]) == CONST_INT
12586 && INTVAL (operands[2]) < 0)
12587 {
12588 operands[2] = force_reg (<MODE>mode, operands[2]);
12589 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12590 GET_MODE (operands[0]),
12591 operands[1], operands[2]);
12592 }
12594 rs6000_emit_cbranch (<MODE>mode, operands);
12595 DONE;
12596 }")
12598 (define_expand "cbranch<mode>4"
12599 [(use (match_operator 0 "rs6000_cbranch_operator"
12600 [(match_operand:FP 1 "gpc_reg_operand" "")
12601 (match_operand:FP 2 "gpc_reg_operand" "")]))
12602 (use (match_operand 3 ""))]
12603 ""
12604 "
12605 {
12606 rs6000_emit_cbranch (<MODE>mode, operands);
12607 DONE;
12608 }")
12610 (define_expand "cstore<mode>4"
12611 [(use (match_operator 1 "rs6000_cbranch_operator"
12612 [(match_operand:GPR 2 "gpc_reg_operand" "")
12613 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12614 (clobber (match_operand:SI 0 "register_operand"))]
12615 ""
12616 "
12617 {
12618 /* Take care of the possibility that operands[3] might be negative but
12619 this might be a logical operation. That insn doesn't exist. */
12620 if (GET_CODE (operands[3]) == CONST_INT
12621 && INTVAL (operands[3]) < 0)
12622 {
12623 operands[3] = force_reg (<MODE>mode, operands[3]);
12624 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12625 GET_MODE (operands[1]),
12626 operands[2], operands[3]);
12627 }
12629 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12630 For SEQ, likewise, except that comparisons with zero should be done
12631 with an scc insns. However, due to the order that combine see the
12632 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12633 the cases we don't want to handle or are best handled by portable
12634 code. */
12635 if (GET_CODE (operands[1]) == NE)
12636 FAIL;
12637 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12638 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12639 && operands[3] == const0_rtx)
12640 FAIL;
12641 rs6000_emit_sCOND (<MODE>mode, operands);
12642 DONE;
12643 }")
12645 (define_expand "cstore<mode>4"
12646 [(use (match_operator 1 "rs6000_cbranch_operator"
12647 [(match_operand:FP 2 "gpc_reg_operand" "")
12648 (match_operand:FP 3 "gpc_reg_operand" "")]))
12649 (clobber (match_operand:SI 0 "register_operand"))]
12650 ""
12651 "
12652 {
12653 rs6000_emit_sCOND (<MODE>mode, operands);
12654 DONE;
12655 }")
12658 (define_expand "stack_protect_set"
12659 [(match_operand 0 "memory_operand" "")
12660 (match_operand 1 "memory_operand" "")]
12661 ""
12662 {
12663 #ifdef TARGET_THREAD_SSP_OFFSET
12664 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12665 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12666 operands[1] = gen_rtx_MEM (Pmode, addr);
12667 #endif
12668 if (TARGET_64BIT)
12669 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12670 else
12671 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12672 DONE;
12673 })
12675 (define_insn "stack_protect_setsi"
12676 [(set (match_operand:SI 0 "memory_operand" "=m")
12677 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12678 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12679 "TARGET_32BIT"
12680 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
12681 [(set_attr "type" "three")
12682 (set_attr "length" "12")])
12684 (define_insn "stack_protect_setdi"
12685 [(set (match_operand:DI 0 "memory_operand" "=m")
12686 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12687 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12688 "TARGET_64BIT"
12689 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
12690 [(set_attr "type" "three")
12691 (set_attr "length" "12")])
12693 (define_expand "stack_protect_test"
12694 [(match_operand 0 "memory_operand" "")
12695 (match_operand 1 "memory_operand" "")
12696 (match_operand 2 "" "")]
12697 ""
12698 {
12699 rtx test, op0, op1;
12700 #ifdef TARGET_THREAD_SSP_OFFSET
12701 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12702 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12703 operands[1] = gen_rtx_MEM (Pmode, addr);
12704 #endif
12705 op0 = operands[0];
12706 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12707 test = gen_rtx_EQ (VOIDmode, op0, op1);
12708 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12709 DONE;
12710 })
12712 (define_insn "stack_protect_testsi"
12713 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12714 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12715 (match_operand:SI 2 "memory_operand" "m,m")]
12716 UNSPEC_SP_TEST))
12717 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12718 (clobber (match_scratch:SI 3 "=&r,&r"))]
12719 "TARGET_32BIT"
12720 "@
12721 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12722 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12723 [(set_attr "length" "16,20")])
12725 (define_insn "stack_protect_testdi"
12726 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12727 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
12728 (match_operand:DI 2 "memory_operand" "m,m")]
12729 UNSPEC_SP_TEST))
12730 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12731 (clobber (match_scratch:DI 3 "=&r,&r"))]
12732 "TARGET_64BIT"
12733 "@
12734 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12735 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12736 [(set_attr "length" "16,20")])
12738 \f
12739 ;; Here are the actual compare insns.
12740 (define_insn "*cmp<mode>_internal1"
12741 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12742 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12743 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12744 ""
12745 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
12746 [(set_attr "type" "cmp")])
12748 ;; If we are comparing a register for equality with a large constant,
12749 ;; we can do this with an XOR followed by a compare. But this is profitable
12750 ;; only if the large constant is only used for the comparison (and in this
12751 ;; case we already have a register to reuse as scratch).
12752 ;;
12753 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12754 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12756 (define_peephole2
12757 [(set (match_operand:SI 0 "register_operand")
12758 (match_operand:SI 1 "logical_const_operand" ""))
12759 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12760 [(match_dup 0)
12761 (match_operand:SI 2 "logical_const_operand" "")]))
12762 (set (match_operand:CC 4 "cc_reg_operand" "")
12763 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12764 (match_dup 0)))
12765 (set (pc)
12766 (if_then_else (match_operator 6 "equality_operator"
12767 [(match_dup 4) (const_int 0)])
12768 (match_operand 7 "" "")
12769 (match_operand 8 "" "")))]
12770 "peep2_reg_dead_p (3, operands[0])
12771 && peep2_reg_dead_p (4, operands[4])"
12772 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12773 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12774 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12776 {
12777 /* Get the constant we are comparing against, and see what it looks like
12778 when sign-extended from 16 to 32 bits. Then see what constant we could
12779 XOR with SEXTC to get the sign-extended value. */
12780 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12781 SImode,
12782 operands[1], operands[2]);
12783 HOST_WIDE_INT c = INTVAL (cnst);
12784 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12785 HOST_WIDE_INT xorv = c ^ sextc;
12787 operands[9] = GEN_INT (xorv);
12788 operands[10] = GEN_INT (sextc);
12789 })
12791 (define_insn "*cmpsi_internal2"
12792 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12793 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12794 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12795 ""
12796 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
12797 [(set_attr "type" "cmp")])
12799 (define_insn "*cmpdi_internal2"
12800 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12801 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12802 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12803 ""
12804 "cmpld%I2 %0,%1,%b2"
12805 [(set_attr "type" "cmp")])
12807 ;; The following two insns don't exist as single insns, but if we provide
12808 ;; them, we can swap an add and compare, which will enable us to overlap more
12809 ;; of the required delay between a compare and branch. We generate code for
12810 ;; them by splitting.
12812 (define_insn ""
12813 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12814 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12815 (match_operand:SI 2 "short_cint_operand" "i")))
12816 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12817 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12818 ""
12819 "#"
12820 [(set_attr "length" "8")])
12822 (define_insn ""
12823 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12824 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12825 (match_operand:SI 2 "u_short_cint_operand" "i")))
12826 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12827 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12828 ""
12829 "#"
12830 [(set_attr "length" "8")])
12832 (define_split
12833 [(set (match_operand:CC 3 "cc_reg_operand" "")
12834 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12835 (match_operand:SI 2 "short_cint_operand" "")))
12836 (set (match_operand:SI 0 "gpc_reg_operand" "")
12837 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12838 ""
12839 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12840 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12842 (define_split
12843 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12844 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12845 (match_operand:SI 2 "u_short_cint_operand" "")))
12846 (set (match_operand:SI 0 "gpc_reg_operand" "")
12847 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12848 ""
12849 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12850 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12852 (define_insn "*cmpsf_internal1"
12853 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12854 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12855 (match_operand:SF 2 "gpc_reg_operand" "f")))]
12856 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12857 "fcmpu %0,%1,%2"
12858 [(set_attr "type" "fpcompare")])
12860 (define_insn "*cmpdf_internal1"
12861 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12862 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12863 (match_operand:DF 2 "gpc_reg_operand" "d")))]
12864 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
12865 && !VECTOR_UNIT_VSX_P (DFmode)"
12866 "fcmpu %0,%1,%2"
12867 [(set_attr "type" "fpcompare")])
12869 ;; Only need to compare second words if first words equal
12870 (define_insn "*cmptf_internal1"
12871 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12872 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12873 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12874 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12875 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12876 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12877 [(set_attr "type" "fpcompare")
12878 (set_attr "length" "12")])
12880 (define_insn_and_split "*cmptf_internal2"
12881 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12882 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12883 (match_operand:TF 2 "gpc_reg_operand" "d")))
12884 (clobber (match_scratch:DF 3 "=d"))
12885 (clobber (match_scratch:DF 4 "=d"))
12886 (clobber (match_scratch:DF 5 "=d"))
12887 (clobber (match_scratch:DF 6 "=d"))
12888 (clobber (match_scratch:DF 7 "=d"))
12889 (clobber (match_scratch:DF 8 "=d"))
12890 (clobber (match_scratch:DF 9 "=d"))
12891 (clobber (match_scratch:DF 10 "=d"))]
12892 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12893 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12894 "#"
12895 "&& reload_completed"
12896 [(set (match_dup 3) (match_dup 13))
12897 (set (match_dup 4) (match_dup 14))
12898 (set (match_dup 9) (abs:DF (match_dup 5)))
12899 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12900 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12901 (label_ref (match_dup 11))
12902 (pc)))
12903 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12904 (set (pc) (label_ref (match_dup 12)))
12905 (match_dup 11)
12906 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12907 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12908 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12909 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
12910 (match_dup 12)]
12911 {
12912 REAL_VALUE_TYPE rv;
12913 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12914 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12916 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12917 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12918 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12919 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12920 operands[11] = gen_label_rtx ();
12921 operands[12] = gen_label_rtx ();
12922 real_inf (&rv);
12923 operands[13] = force_const_mem (DFmode,
12924 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12925 operands[14] = force_const_mem (DFmode,
12926 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12927 DFmode));
12928 if (TARGET_TOC)
12929 {
12930 operands[13] = gen_const_mem (DFmode,
12931 create_TOC_reference (XEXP (operands[13], 0)));
12932 operands[14] = gen_const_mem (DFmode,
12933 create_TOC_reference (XEXP (operands[14], 0)));
12934 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12935 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12936 }
12937 })
12938 \f
12939 ;; Now we have the scc insns. We can do some combinations because of the
12940 ;; way the machine works.
12941 ;;
12942 ;; Note that this is probably faster if we can put an insn between the
12943 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12944 ;; cases the insns below which don't use an intermediate CR field will
12945 ;; be used instead.
12946 (define_insn ""
12947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12948 (match_operator:SI 1 "scc_comparison_operator"
12949 [(match_operand 2 "cc_reg_operand" "y")
12950 (const_int 0)]))]
12951 ""
12952 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12953 [(set (attr "type")
12954 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12955 (const_string "mfcrf")
12956 ]
12957 (const_string "mfcr")))
12958 (set_attr "length" "8")])
12960 ;; Same as above, but get the GT bit.
12961 (define_insn "move_from_CR_gt_bit"
12962 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12963 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12964 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12965 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12966 [(set_attr "type" "mfcr")
12967 (set_attr "length" "8")])
12969 ;; Same as above, but get the OV/ORDERED bit.
12970 (define_insn "move_from_CR_ov_bit"
12971 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12972 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12973 "TARGET_ISEL"
12974 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12975 [(set_attr "type" "mfcr")
12976 (set_attr "length" "8")])
12978 (define_insn ""
12979 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12980 (match_operator:DI 1 "scc_comparison_operator"
12981 [(match_operand 2 "cc_reg_operand" "y")
12982 (const_int 0)]))]
12983 "TARGET_POWERPC64"
12984 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12985 [(set (attr "type")
12986 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12987 (const_string "mfcrf")
12988 ]
12989 (const_string "mfcr")))
12990 (set_attr "length" "8")])
12992 (define_insn ""
12993 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12994 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12995 [(match_operand 2 "cc_reg_operand" "y,y")
12996 (const_int 0)])
12997 (const_int 0)))
12998 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12999 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13000 "TARGET_32BIT"
13001 "@
13002 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
13003 #"
13004 [(set_attr "type" "delayed_compare")
13005 (set_attr "length" "8,16")])
13007 (define_split
13008 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13009 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13010 [(match_operand 2 "cc_reg_operand" "")
13011 (const_int 0)])
13012 (const_int 0)))
13013 (set (match_operand:SI 3 "gpc_reg_operand" "")
13014 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13015 "TARGET_32BIT && reload_completed"
13016 [(set (match_dup 3)
13017 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
13018 (set (match_dup 0)
13019 (compare:CC (match_dup 3)
13020 (const_int 0)))]
13021 "")
13023 (define_insn ""
13024 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13025 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13026 [(match_operand 2 "cc_reg_operand" "y")
13027 (const_int 0)])
13028 (match_operand:SI 3 "const_int_operand" "n")))]
13029 ""
13030 "*
13031 {
13032 int is_bit = ccr_bit (operands[1], 1);
13033 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13034 int count;
13036 if (is_bit >= put_bit)
13037 count = is_bit - put_bit;
13038 else
13039 count = 32 - (put_bit - is_bit);
13041 operands[4] = GEN_INT (count);
13042 operands[5] = GEN_INT (put_bit);
13044 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
13045 }"
13046 [(set (attr "type")
13047 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13048 (const_string "mfcrf")
13049 ]
13050 (const_string "mfcr")))
13051 (set_attr "length" "8")])
13053 (define_insn ""
13054 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13055 (compare:CC
13056 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13057 [(match_operand 2 "cc_reg_operand" "y,y")
13058 (const_int 0)])
13059 (match_operand:SI 3 "const_int_operand" "n,n"))
13060 (const_int 0)))
13061 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13062 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13063 (match_dup 3)))]
13064 ""
13065 "*
13066 {
13067 int is_bit = ccr_bit (operands[1], 1);
13068 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13069 int count;
13071 /* Force split for non-cc0 compare. */
13072 if (which_alternative == 1)
13073 return \"#\";
13075 if (is_bit >= put_bit)
13076 count = is_bit - put_bit;
13077 else
13078 count = 32 - (put_bit - is_bit);
13080 operands[5] = GEN_INT (count);
13081 operands[6] = GEN_INT (put_bit);
13083 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
13084 }"
13085 [(set_attr "type" "delayed_compare")
13086 (set_attr "length" "8,16")])
13088 (define_split
13089 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13090 (compare:CC
13091 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13092 [(match_operand 2 "cc_reg_operand" "")
13093 (const_int 0)])
13094 (match_operand:SI 3 "const_int_operand" ""))
13095 (const_int 0)))
13096 (set (match_operand:SI 4 "gpc_reg_operand" "")
13097 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13098 (match_dup 3)))]
13099 "reload_completed"
13100 [(set (match_dup 4)
13101 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13102 (match_dup 3)))
13103 (set (match_dup 0)
13104 (compare:CC (match_dup 4)
13105 (const_int 0)))]
13106 "")
13108 ;; There is a 3 cycle delay between consecutive mfcr instructions
13109 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13111 (define_peephole
13112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13113 (match_operator:SI 1 "scc_comparison_operator"
13114 [(match_operand 2 "cc_reg_operand" "y")
13115 (const_int 0)]))
13116 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13117 (match_operator:SI 4 "scc_comparison_operator"
13118 [(match_operand 5 "cc_reg_operand" "y")
13119 (const_int 0)]))]
13120 "REGNO (operands[2]) != REGNO (operands[5])"
13121 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13122 [(set_attr "type" "mfcr")
13123 (set_attr "length" "12")])
13125 (define_peephole
13126 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13127 (match_operator:DI 1 "scc_comparison_operator"
13128 [(match_operand 2 "cc_reg_operand" "y")
13129 (const_int 0)]))
13130 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13131 (match_operator:DI 4 "scc_comparison_operator"
13132 [(match_operand 5 "cc_reg_operand" "y")
13133 (const_int 0)]))]
13134 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13135 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13136 [(set_attr "type" "mfcr")
13137 (set_attr "length" "12")])
13139 ;; There are some scc insns that can be done directly, without a compare.
13140 ;; These are faster because they don't involve the communications between
13141 ;; the FXU and branch units. In fact, we will be replacing all of the
13142 ;; integer scc insns here or in the portable methods in emit_store_flag.
13143 ;;
13144 ;; Also support (neg (scc ..)) since that construct is used to replace
13145 ;; branches, (plus (scc ..) ..) since that construct is common and
13146 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13147 ;; cases where it is no more expensive than (neg (scc ..)).
13149 ;; Have reload force a constant into a register for the simple insns that
13150 ;; otherwise won't accept constants. We do this because it is faster than
13151 ;; the cmp/mfcr sequence we would otherwise generate.
13153 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13154 (DI "rKJI")])
13156 (define_insn_and_split "*eq<mode>"
13157 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13158 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13159 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13160 "!TARGET_POWER"
13161 "#"
13162 "!TARGET_POWER"
13163 [(set (match_dup 0)
13164 (clz:GPR (match_dup 3)))
13165 (set (match_dup 0)
13166 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13167 {
13168 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13169 {
13170 /* Use output operand as intermediate. */
13171 operands[3] = operands[0];
13173 if (logical_operand (operands[2], <MODE>mode))
13174 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13175 gen_rtx_XOR (<MODE>mode,
13176 operands[1], operands[2])));
13177 else
13178 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13179 gen_rtx_PLUS (<MODE>mode, operands[1],
13180 negate_rtx (<MODE>mode,
13181 operands[2]))));
13182 }
13183 else
13184 operands[3] = operands[1];
13186 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13187 })
13189 (define_insn_and_split "*eq<mode>_compare"
13190 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13191 (compare:CC
13192 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13193 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13194 (const_int 0)))
13195 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13196 (eq:P (match_dup 1) (match_dup 2)))]
13197 "!TARGET_POWER && optimize_size"
13198 "#"
13199 "!TARGET_POWER && optimize_size"
13200 [(set (match_dup 0)
13201 (clz:P (match_dup 4)))
13202 (parallel [(set (match_dup 3)
13203 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13204 (const_int 0)))
13205 (set (match_dup 0)
13206 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13207 {
13208 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13209 {
13210 /* Use output operand as intermediate. */
13211 operands[4] = operands[0];
13213 if (logical_operand (operands[2], <MODE>mode))
13214 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13215 gen_rtx_XOR (<MODE>mode,
13216 operands[1], operands[2])));
13217 else
13218 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13219 gen_rtx_PLUS (<MODE>mode, operands[1],
13220 negate_rtx (<MODE>mode,
13221 operands[2]))));
13222 }
13223 else
13224 operands[4] = operands[1];
13226 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13227 })
13229 (define_insn "*eqsi_power"
13230 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
13231 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13232 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
13233 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
13234 "TARGET_POWER"
13235 "@
13236 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13237 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
13238 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13239 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13240 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
13241 [(set_attr "type" "three,two,three,three,three")
13242 (set_attr "length" "12,8,12,12,12")])
13244 ;; We have insns of the form shown by the first define_insn below. If
13245 ;; there is something inside the comparison operation, we must split it.
13246 (define_split
13247 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13248 (plus:SI (match_operator 1 "comparison_operator"
13249 [(match_operand:SI 2 "" "")
13250 (match_operand:SI 3
13251 "reg_or_cint_operand" "")])
13252 (match_operand:SI 4 "gpc_reg_operand" "")))
13253 (clobber (match_operand:SI 5 "register_operand" ""))]
13254 "! gpc_reg_operand (operands[2], SImode)"
13255 [(set (match_dup 5) (match_dup 2))
13256 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
13257 (match_dup 4)))])
13259 (define_insn "*plus_eqsi"
13260 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13261 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13262 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13263 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13264 "TARGET_32BIT"
13265 "@
13266 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13267 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
13268 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13269 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13270 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13271 [(set_attr "type" "three,two,three,three,three")
13272 (set_attr "length" "12,8,12,12,12")])
13274 (define_insn "*compare_plus_eqsi"
13275 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13276 (compare:CC
13277 (plus:SI
13278 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13279 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13280 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13281 (const_int 0)))
13282 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13283 "TARGET_32BIT && optimize_size"
13284 "@
13285 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13286 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
13287 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13288 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13289 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13290 #
13291 #
13292 #
13293 #
13294 #"
13295 [(set_attr "type" "compare")
13296 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13298 (define_split
13299 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13300 (compare:CC
13301 (plus:SI
13302 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13303 (match_operand:SI 2 "scc_eq_operand" ""))
13304 (match_operand:SI 3 "gpc_reg_operand" ""))
13305 (const_int 0)))
13306 (clobber (match_scratch:SI 4 ""))]
13307 "TARGET_32BIT && optimize_size && reload_completed"
13308 [(set (match_dup 4)
13309 (plus:SI (eq:SI (match_dup 1)
13310 (match_dup 2))
13311 (match_dup 3)))
13312 (set (match_dup 0)
13313 (compare:CC (match_dup 4)
13314 (const_int 0)))]
13315 "")
13317 (define_insn "*plus_eqsi_compare"
13318 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13319 (compare:CC
13320 (plus:SI
13321 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13322 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13323 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13324 (const_int 0)))
13325 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13326 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13327 "TARGET_32BIT && optimize_size"
13328 "@
13329 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13330 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
13331 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13332 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13333 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13334 #
13335 #
13336 #
13337 #
13338 #"
13339 [(set_attr "type" "compare")
13340 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13342 (define_split
13343 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13344 (compare:CC
13345 (plus:SI
13346 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13347 (match_operand:SI 2 "scc_eq_operand" ""))
13348 (match_operand:SI 3 "gpc_reg_operand" ""))
13349 (const_int 0)))
13350 (set (match_operand:SI 0 "gpc_reg_operand" "")
13351 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13352 "TARGET_32BIT && optimize_size && reload_completed"
13353 [(set (match_dup 0)
13354 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13355 (set (match_dup 4)
13356 (compare:CC (match_dup 0)
13357 (const_int 0)))]
13358 "")
13360 (define_insn "*neg_eq0<mode>"
13361 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13362 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13363 (const_int 0))))]
13364 ""
13365 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
13366 [(set_attr "type" "two")
13367 (set_attr "length" "8")])
13369 (define_insn_and_split "*neg_eq<mode>"
13370 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13371 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13372 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13373 ""
13374 "#"
13375 ""
13376 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13377 {
13378 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13379 {
13380 /* Use output operand as intermediate. */
13381 operands[3] = operands[0];
13383 if (logical_operand (operands[2], <MODE>mode))
13384 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13385 gen_rtx_XOR (<MODE>mode,
13386 operands[1], operands[2])));
13387 else
13388 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13389 gen_rtx_PLUS (<MODE>mode, operands[1],
13390 negate_rtx (<MODE>mode,
13391 operands[2]))));
13392 }
13393 else
13394 operands[3] = operands[1];
13395 })
13397 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
13398 ;; since it nabs/sr is just as fast.
13399 (define_insn "*ne0si"
13400 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13401 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13402 (const_int 31)))
13403 (clobber (match_scratch:SI 2 "=&r"))]
13404 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
13405 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
13406 [(set_attr "type" "two")
13407 (set_attr "length" "8")])
13409 (define_insn "*ne0di"
13410 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13411 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13412 (const_int 63)))
13413 (clobber (match_scratch:DI 2 "=&r"))]
13414 "TARGET_64BIT"
13415 "addic %2,%1,-1\;subfe %0,%2,%1"
13416 [(set_attr "type" "two")
13417 (set_attr "length" "8")])
13419 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
13420 (define_insn "*plus_ne0si"
13421 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13422 (plus:SI (lshiftrt:SI
13423 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13424 (const_int 31))
13425 (match_operand:SI 2 "gpc_reg_operand" "r")))
13426 (clobber (match_scratch:SI 3 "=&r"))]
13427 "TARGET_32BIT"
13428 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
13429 [(set_attr "type" "two")
13430 (set_attr "length" "8")])
13432 (define_insn "*plus_ne0di"
13433 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13434 (plus:DI (lshiftrt:DI
13435 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13436 (const_int 63))
13437 (match_operand:DI 2 "gpc_reg_operand" "r")))
13438 (clobber (match_scratch:DI 3 "=&r"))]
13439 "TARGET_64BIT"
13440 "addic %3,%1,-1\;addze %0,%2"
13441 [(set_attr "type" "two")
13442 (set_attr "length" "8")])
13444 (define_insn "*compare_plus_ne0si"
13445 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13446 (compare:CC
13447 (plus:SI (lshiftrt:SI
13448 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13449 (const_int 31))
13450 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13451 (const_int 0)))
13452 (clobber (match_scratch:SI 3 "=&r,&r"))
13453 (clobber (match_scratch:SI 4 "=X,&r"))]
13454 "TARGET_32BIT"
13455 "@
13456 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
13457 #"
13458 [(set_attr "type" "compare")
13459 (set_attr "length" "8,12")])
13461 (define_split
13462 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13463 (compare:CC
13464 (plus:SI (lshiftrt:SI
13465 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13466 (const_int 31))
13467 (match_operand:SI 2 "gpc_reg_operand" ""))
13468 (const_int 0)))
13469 (clobber (match_scratch:SI 3 ""))
13470 (clobber (match_scratch:SI 4 ""))]
13471 "TARGET_32BIT && reload_completed"
13472 [(parallel [(set (match_dup 3)
13473 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
13474 (const_int 31))
13475 (match_dup 2)))
13476 (clobber (match_dup 4))])
13477 (set (match_dup 0)
13478 (compare:CC (match_dup 3)
13479 (const_int 0)))]
13480 "")
13482 (define_insn "*compare_plus_ne0di"
13483 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13484 (compare:CC
13485 (plus:DI (lshiftrt:DI
13486 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13487 (const_int 63))
13488 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13489 (const_int 0)))
13490 (clobber (match_scratch:DI 3 "=&r,&r"))]
13491 "TARGET_64BIT"
13492 "@
13493 addic %3,%1,-1\;addze. %3,%2
13494 #"
13495 [(set_attr "type" "compare")
13496 (set_attr "length" "8,12")])
13498 (define_split
13499 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13500 (compare:CC
13501 (plus:DI (lshiftrt:DI
13502 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13503 (const_int 63))
13504 (match_operand:DI 2 "gpc_reg_operand" ""))
13505 (const_int 0)))
13506 (clobber (match_scratch:DI 3 ""))]
13507 "TARGET_64BIT && reload_completed"
13508 [(set (match_dup 3)
13509 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
13510 (const_int 63))
13511 (match_dup 2)))
13512 (set (match_dup 0)
13513 (compare:CC (match_dup 3)
13514 (const_int 0)))]
13515 "")
13517 (define_insn "*plus_ne0si_compare"
13518 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13519 (compare:CC
13520 (plus:SI (lshiftrt:SI
13521 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13522 (const_int 31))
13523 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13524 (const_int 0)))
13525 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13526 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13527 (match_dup 2)))
13528 (clobber (match_scratch:SI 3 "=&r,&r"))]
13529 "TARGET_32BIT"
13530 "@
13531 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
13532 #"
13533 [(set_attr "type" "compare")
13534 (set_attr "length" "8,12")])
13536 (define_split
13537 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13538 (compare:CC
13539 (plus:SI (lshiftrt:SI
13540 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13541 (const_int 31))
13542 (match_operand:SI 2 "gpc_reg_operand" ""))
13543 (const_int 0)))
13544 (set (match_operand:SI 0 "gpc_reg_operand" "")
13545 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13546 (match_dup 2)))
13547 (clobber (match_scratch:SI 3 ""))]
13548 "TARGET_32BIT && reload_completed"
13549 [(parallel [(set (match_dup 0)
13550 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13551 (match_dup 2)))
13552 (clobber (match_dup 3))])
13553 (set (match_dup 4)
13554 (compare:CC (match_dup 0)
13555 (const_int 0)))]
13556 "")
13558 (define_insn "*plus_ne0di_compare"
13559 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13560 (compare:CC
13561 (plus:DI (lshiftrt:DI
13562 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13563 (const_int 63))
13564 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13565 (const_int 0)))
13566 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13567 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13568 (match_dup 2)))
13569 (clobber (match_scratch:DI 3 "=&r,&r"))]
13570 "TARGET_64BIT"
13571 "@
13572 addic %3,%1,-1\;addze. %0,%2
13573 #"
13574 [(set_attr "type" "compare")
13575 (set_attr "length" "8,12")])
13577 (define_split
13578 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13579 (compare:CC
13580 (plus:DI (lshiftrt:DI
13581 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13582 (const_int 63))
13583 (match_operand:DI 2 "gpc_reg_operand" ""))
13584 (const_int 0)))
13585 (set (match_operand:DI 0 "gpc_reg_operand" "")
13586 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13587 (match_dup 2)))
13588 (clobber (match_scratch:DI 3 ""))]
13589 "TARGET_64BIT && reload_completed"
13590 [(parallel [(set (match_dup 0)
13591 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13592 (match_dup 2)))
13593 (clobber (match_dup 3))])
13594 (set (match_dup 4)
13595 (compare:CC (match_dup 0)
13596 (const_int 0)))]
13597 "")
13599 (define_insn ""
13600 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13601 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13602 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
13603 (clobber (match_scratch:SI 3 "=r,X"))]
13604 "TARGET_POWER"
13605 "@
13606 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
13607 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
13608 [(set_attr "length" "12")])
13610 (define_insn ""
13611 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13612 (compare:CC
13613 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13614 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13615 (const_int 0)))
13616 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
13617 (le:SI (match_dup 1) (match_dup 2)))
13618 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
13619 "TARGET_POWER"
13620 "@
13621 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13622 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
13623 #
13624 #"
13625 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
13626 (set_attr "length" "12,12,16,16")])
13628 (define_split
13629 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13630 (compare:CC
13631 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13632 (match_operand:SI 2 "reg_or_short_operand" ""))
13633 (const_int 0)))
13634 (set (match_operand:SI 0 "gpc_reg_operand" "")
13635 (le:SI (match_dup 1) (match_dup 2)))
13636 (clobber (match_scratch:SI 3 ""))]
13637 "TARGET_POWER && reload_completed"
13638 [(parallel [(set (match_dup 0)
13639 (le:SI (match_dup 1) (match_dup 2)))
13640 (clobber (match_dup 3))])
13641 (set (match_dup 4)
13642 (compare:CC (match_dup 0)
13643 (const_int 0)))]
13644 "")
13646 (define_insn ""
13647 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13648 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13649 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
13650 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13651 "TARGET_POWER"
13652 "@
13653 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13654 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
13655 [(set_attr "length" "12")])
13657 (define_insn ""
13658 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13659 (compare:CC
13660 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13661 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13662 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13663 (const_int 0)))
13664 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13665 "TARGET_POWER"
13666 "@
13667 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13668 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
13669 #
13670 #"
13671 [(set_attr "type" "compare")
13672 (set_attr "length" "12,12,16,16")])
13674 (define_split
13675 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13676 (compare:CC
13677 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13678 (match_operand:SI 2 "reg_or_short_operand" ""))
13679 (match_operand:SI 3 "gpc_reg_operand" ""))
13680 (const_int 0)))
13681 (clobber (match_scratch:SI 4 ""))]
13682 "TARGET_POWER && reload_completed"
13683 [(set (match_dup 4)
13684 (plus:SI (le:SI (match_dup 1) (match_dup 2))
13685 (match_dup 3)))
13686 (set (match_dup 0)
13687 (compare:CC (match_dup 4)
13688 (const_int 0)))]
13689 "")
13691 (define_insn ""
13692 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13693 (compare:CC
13694 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13695 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13696 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13697 (const_int 0)))
13698 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13699 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13700 "TARGET_POWER"
13701 "@
13702 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13703 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
13704 #
13705 #"
13706 [(set_attr "type" "compare")
13707 (set_attr "length" "12,12,16,16")])
13709 (define_split
13710 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13711 (compare:CC
13712 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13713 (match_operand:SI 2 "reg_or_short_operand" ""))
13714 (match_operand:SI 3 "gpc_reg_operand" ""))
13715 (const_int 0)))
13716 (set (match_operand:SI 0 "gpc_reg_operand" "")
13717 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13718 "TARGET_POWER && reload_completed"
13719 [(set (match_dup 0)
13720 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13721 (set (match_dup 4)
13722 (compare:CC (match_dup 0)
13723 (const_int 0)))]
13724 "")
13726 (define_insn ""
13727 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13728 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13729 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
13730 "TARGET_POWER"
13731 "@
13732 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
13733 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
13734 [(set_attr "length" "12")])
13736 (define_insn "*leu<mode>"
13737 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13738 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13739 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13740 ""
13741 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13742 [(set_attr "type" "three")
13743 (set_attr "length" "12")])
13745 (define_insn "*leu<mode>_compare"
13746 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13747 (compare:CC
13748 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13749 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13750 (const_int 0)))
13751 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13752 (leu:P (match_dup 1) (match_dup 2)))]
13753 ""
13754 "@
13755 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13756 #"
13757 [(set_attr "type" "compare")
13758 (set_attr "length" "12,16")])
13760 (define_split
13761 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13762 (compare:CC
13763 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13764 (match_operand:P 2 "reg_or_short_operand" ""))
13765 (const_int 0)))
13766 (set (match_operand:P 0 "gpc_reg_operand" "")
13767 (leu:P (match_dup 1) (match_dup 2)))]
13768 "reload_completed"
13769 [(set (match_dup 0)
13770 (leu:P (match_dup 1) (match_dup 2)))
13771 (set (match_dup 3)
13772 (compare:CC (match_dup 0)
13773 (const_int 0)))]
13774 "")
13776 (define_insn "*plus_leu<mode>"
13777 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13778 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13779 (match_operand:P 2 "reg_or_short_operand" "rI"))
13780 (match_operand:P 3 "gpc_reg_operand" "r")))]
13781 ""
13782 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
13783 [(set_attr "type" "two")
13784 (set_attr "length" "8")])
13786 (define_insn ""
13787 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13788 (compare:CC
13789 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13790 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13791 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13792 (const_int 0)))
13793 (clobber (match_scratch:SI 4 "=&r,&r"))]
13794 "TARGET_32BIT"
13795 "@
13796 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
13797 #"
13798 [(set_attr "type" "compare")
13799 (set_attr "length" "8,12")])
13801 (define_split
13802 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13803 (compare:CC
13804 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13805 (match_operand:SI 2 "reg_or_short_operand" ""))
13806 (match_operand:SI 3 "gpc_reg_operand" ""))
13807 (const_int 0)))
13808 (clobber (match_scratch:SI 4 ""))]
13809 "TARGET_32BIT && reload_completed"
13810 [(set (match_dup 4)
13811 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13812 (match_dup 3)))
13813 (set (match_dup 0)
13814 (compare:CC (match_dup 4)
13815 (const_int 0)))]
13816 "")
13818 (define_insn ""
13819 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13820 (compare:CC
13821 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13822 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13823 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13824 (const_int 0)))
13825 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13826 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13827 "TARGET_32BIT"
13828 "@
13829 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
13830 #"
13831 [(set_attr "type" "compare")
13832 (set_attr "length" "8,12")])
13834 (define_split
13835 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13836 (compare:CC
13837 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13838 (match_operand:SI 2 "reg_or_short_operand" ""))
13839 (match_operand:SI 3 "gpc_reg_operand" ""))
13840 (const_int 0)))
13841 (set (match_operand:SI 0 "gpc_reg_operand" "")
13842 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13843 "TARGET_32BIT && reload_completed"
13844 [(set (match_dup 0)
13845 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13846 (set (match_dup 4)
13847 (compare:CC (match_dup 0)
13848 (const_int 0)))]
13849 "")
13851 (define_insn "*neg_leu<mode>"
13852 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13853 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13854 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13855 ""
13856 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
13857 [(set_attr "type" "three")
13858 (set_attr "length" "12")])
13860 (define_insn "*and_neg_leu<mode>"
13861 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13862 (and:P (neg:P
13863 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13864 (match_operand:P 2 "reg_or_short_operand" "rI")))
13865 (match_operand:P 3 "gpc_reg_operand" "r")))]
13866 ""
13867 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13868 [(set_attr "type" "three")
13869 (set_attr "length" "12")])
13871 (define_insn ""
13872 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13873 (compare:CC
13874 (and:SI (neg:SI
13875 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13876 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13877 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13878 (const_int 0)))
13879 (clobber (match_scratch:SI 4 "=&r,&r"))]
13880 "TARGET_32BIT"
13881 "@
13882 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13883 #"
13884 [(set_attr "type" "compare")
13885 (set_attr "length" "12,16")])
13887 (define_split
13888 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13889 (compare:CC
13890 (and:SI (neg:SI
13891 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13892 (match_operand:SI 2 "reg_or_short_operand" "")))
13893 (match_operand:SI 3 "gpc_reg_operand" ""))
13894 (const_int 0)))
13895 (clobber (match_scratch:SI 4 ""))]
13896 "TARGET_32BIT && reload_completed"
13897 [(set (match_dup 4)
13898 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13899 (match_dup 3)))
13900 (set (match_dup 0)
13901 (compare:CC (match_dup 4)
13902 (const_int 0)))]
13903 "")
13905 (define_insn ""
13906 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13907 (compare:CC
13908 (and:SI (neg:SI
13909 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13910 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13911 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13912 (const_int 0)))
13913 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13914 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13915 "TARGET_32BIT"
13916 "@
13917 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13918 #"
13919 [(set_attr "type" "compare")
13920 (set_attr "length" "12,16")])
13922 (define_split
13923 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13924 (compare:CC
13925 (and:SI (neg:SI
13926 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13927 (match_operand:SI 2 "reg_or_short_operand" "")))
13928 (match_operand:SI 3 "gpc_reg_operand" ""))
13929 (const_int 0)))
13930 (set (match_operand:SI 0 "gpc_reg_operand" "")
13931 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13932 "TARGET_32BIT && reload_completed"
13933 [(set (match_dup 0)
13934 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13935 (match_dup 3)))
13936 (set (match_dup 4)
13937 (compare:CC (match_dup 0)
13938 (const_int 0)))]
13939 "")
13941 (define_insn ""
13942 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13943 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13944 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13945 "TARGET_POWER"
13946 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13947 [(set_attr "length" "12")])
13949 (define_insn ""
13950 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13951 (compare:CC
13952 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13953 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13954 (const_int 0)))
13955 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13956 (lt:SI (match_dup 1) (match_dup 2)))]
13957 "TARGET_POWER"
13958 "@
13959 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13960 #"
13961 [(set_attr "type" "delayed_compare")
13962 (set_attr "length" "12,16")])
13964 (define_split
13965 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13966 (compare:CC
13967 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13968 (match_operand:SI 2 "reg_or_short_operand" ""))
13969 (const_int 0)))
13970 (set (match_operand:SI 0 "gpc_reg_operand" "")
13971 (lt:SI (match_dup 1) (match_dup 2)))]
13972 "TARGET_POWER && reload_completed"
13973 [(set (match_dup 0)
13974 (lt:SI (match_dup 1) (match_dup 2)))
13975 (set (match_dup 3)
13976 (compare:CC (match_dup 0)
13977 (const_int 0)))]
13978 "")
13980 (define_insn ""
13981 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13982 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13983 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13984 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13985 "TARGET_POWER"
13986 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13987 [(set_attr "length" "12")])
13989 (define_insn ""
13990 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13991 (compare:CC
13992 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13993 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13994 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13995 (const_int 0)))
13996 (clobber (match_scratch:SI 4 "=&r,&r"))]
13997 "TARGET_POWER"
13998 "@
13999 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14000 #"
14001 [(set_attr "type" "compare")
14002 (set_attr "length" "12,16")])
14004 (define_split
14005 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14006 (compare:CC
14007 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14008 (match_operand:SI 2 "reg_or_short_operand" ""))
14009 (match_operand:SI 3 "gpc_reg_operand" ""))
14010 (const_int 0)))
14011 (clobber (match_scratch:SI 4 ""))]
14012 "TARGET_POWER && reload_completed"
14013 [(set (match_dup 4)
14014 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
14015 (match_dup 3)))
14016 (set (match_dup 0)
14017 (compare:CC (match_dup 4)
14018 (const_int 0)))]
14019 "")
14021 (define_insn ""
14022 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14023 (compare:CC
14024 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14025 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14026 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14027 (const_int 0)))
14028 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14029 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14030 "TARGET_POWER"
14031 "@
14032 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14033 #"
14034 [(set_attr "type" "compare")
14035 (set_attr "length" "12,16")])
14037 (define_split
14038 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14039 (compare:CC
14040 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14041 (match_operand:SI 2 "reg_or_short_operand" ""))
14042 (match_operand:SI 3 "gpc_reg_operand" ""))
14043 (const_int 0)))
14044 (set (match_operand:SI 0 "gpc_reg_operand" "")
14045 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14046 "TARGET_POWER && reload_completed"
14047 [(set (match_dup 0)
14048 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14049 (set (match_dup 4)
14050 (compare:CC (match_dup 0)
14051 (const_int 0)))]
14052 "")
14054 (define_insn ""
14055 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14056 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14057 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14058 "TARGET_POWER"
14059 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14060 [(set_attr "length" "12")])
14062 (define_insn_and_split "*ltu<mode>"
14063 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14064 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14065 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14066 ""
14067 "#"
14068 ""
14069 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14070 (set (match_dup 0) (neg:P (match_dup 0)))]
14071 "")
14073 (define_insn_and_split "*ltu<mode>_compare"
14074 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14075 (compare:CC
14076 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14077 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14078 (const_int 0)))
14079 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14080 (ltu:P (match_dup 1) (match_dup 2)))]
14081 ""
14082 "#"
14083 ""
14084 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14085 (parallel [(set (match_dup 3)
14086 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14087 (set (match_dup 0) (neg:P (match_dup 0)))])]
14088 "")
14090 (define_insn_and_split "*plus_ltu<mode>"
14091 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14092 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14093 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14094 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14095 ""
14096 "#"
14097 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14098 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14099 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14100 "")
14102 (define_insn_and_split "*plus_ltu<mode>_compare"
14103 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14104 (compare:CC
14105 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14106 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14107 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14108 (const_int 0)))
14109 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14110 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14111 ""
14112 "#"
14113 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14114 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14115 (parallel [(set (match_dup 4)
14116 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14117 (const_int 0)))
14118 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14119 "")
14121 (define_insn "*neg_ltu<mode>"
14122 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14123 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14124 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14125 ""
14126 "@
14127 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
14128 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
14129 [(set_attr "type" "two")
14130 (set_attr "length" "8")])
14132 (define_insn ""
14133 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14134 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14135 (match_operand:SI 2 "reg_or_short_operand" "rI")))
14136 (clobber (match_scratch:SI 3 "=r"))]
14137 "TARGET_POWER"
14138 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
14139 [(set_attr "length" "12")])
14141 (define_insn ""
14142 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14143 (compare:CC
14144 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14145 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14146 (const_int 0)))
14147 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14148 (ge:SI (match_dup 1) (match_dup 2)))
14149 (clobber (match_scratch:SI 3 "=r,r"))]
14150 "TARGET_POWER"
14151 "@
14152 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14153 #"
14154 [(set_attr "type" "compare")
14155 (set_attr "length" "12,16")])
14157 (define_split
14158 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14159 (compare:CC
14160 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14161 (match_operand:SI 2 "reg_or_short_operand" ""))
14162 (const_int 0)))
14163 (set (match_operand:SI 0 "gpc_reg_operand" "")
14164 (ge:SI (match_dup 1) (match_dup 2)))
14165 (clobber (match_scratch:SI 3 ""))]
14166 "TARGET_POWER && reload_completed"
14167 [(parallel [(set (match_dup 0)
14168 (ge:SI (match_dup 1) (match_dup 2)))
14169 (clobber (match_dup 3))])
14170 (set (match_dup 4)
14171 (compare:CC (match_dup 0)
14172 (const_int 0)))]
14173 "")
14175 (define_insn ""
14176 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14177 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14178 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14179 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14180 "TARGET_POWER"
14181 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
14182 [(set_attr "length" "12")])
14184 (define_insn ""
14185 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14186 (compare:CC
14187 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14188 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14189 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14190 (const_int 0)))
14191 (clobber (match_scratch:SI 4 "=&r,&r"))]
14192 "TARGET_POWER"
14193 "@
14194 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14195 #"
14196 [(set_attr "type" "compare")
14197 (set_attr "length" "12,16")])
14199 (define_split
14200 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14201 (compare:CC
14202 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14203 (match_operand:SI 2 "reg_or_short_operand" ""))
14204 (match_operand:SI 3 "gpc_reg_operand" ""))
14205 (const_int 0)))
14206 (clobber (match_scratch:SI 4 ""))]
14207 "TARGET_POWER && reload_completed"
14208 [(set (match_dup 4)
14209 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
14210 (match_dup 3)))
14211 (set (match_dup 0)
14212 (compare:CC (match_dup 4)
14213 (const_int 0)))]
14214 "")
14216 (define_insn ""
14217 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14218 (compare:CC
14219 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14220 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14221 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14222 (const_int 0)))
14223 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14224 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14225 "TARGET_POWER"
14226 "@
14227 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14228 #"
14229 [(set_attr "type" "compare")
14230 (set_attr "length" "12,16")])
14232 (define_split
14233 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14234 (compare:CC
14235 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14236 (match_operand:SI 2 "reg_or_short_operand" ""))
14237 (match_operand:SI 3 "gpc_reg_operand" ""))
14238 (const_int 0)))
14239 (set (match_operand:SI 0 "gpc_reg_operand" "")
14240 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14241 "TARGET_POWER && reload_completed"
14242 [(set (match_dup 0)
14243 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14244 (set (match_dup 4)
14245 (compare:CC (match_dup 0)
14246 (const_int 0)))]
14247 "")
14249 (define_insn ""
14250 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14251 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14252 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14253 "TARGET_POWER"
14254 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
14255 [(set_attr "length" "12")])
14257 (define_insn "*geu<mode>"
14258 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14259 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14260 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14261 ""
14262 "@
14263 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
14264 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14265 [(set_attr "type" "three")
14266 (set_attr "length" "12")])
14268 (define_insn "*geu<mode>_compare"
14269 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14270 (compare:CC
14271 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14272 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14273 (const_int 0)))
14274 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14275 (geu:P (match_dup 1) (match_dup 2)))]
14276 ""
14277 "@
14278 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14279 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14280 #
14281 #"
14282 [(set_attr "type" "compare")
14283 (set_attr "length" "12,12,16,16")])
14285 (define_split
14286 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14287 (compare:CC
14288 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14289 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14290 (const_int 0)))
14291 (set (match_operand:P 0 "gpc_reg_operand" "")
14292 (geu:P (match_dup 1) (match_dup 2)))]
14293 "reload_completed"
14294 [(set (match_dup 0)
14295 (geu:P (match_dup 1) (match_dup 2)))
14296 (set (match_dup 3)
14297 (compare:CC (match_dup 0)
14298 (const_int 0)))]
14299 "")
14301 (define_insn "*plus_geu<mode>"
14302 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14303 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14304 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14305 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14306 ""
14307 "@
14308 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
14309 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
14310 [(set_attr "type" "two")
14311 (set_attr "length" "8")])
14313 (define_insn ""
14314 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14315 (compare:CC
14316 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14317 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14318 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14319 (const_int 0)))
14320 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14321 "TARGET_32BIT"
14322 "@
14323 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
14324 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
14325 #
14326 #"
14327 [(set_attr "type" "compare")
14328 (set_attr "length" "8,8,12,12")])
14330 (define_split
14331 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14332 (compare:CC
14333 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14334 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14335 (match_operand:SI 3 "gpc_reg_operand" ""))
14336 (const_int 0)))
14337 (clobber (match_scratch:SI 4 ""))]
14338 "TARGET_32BIT && reload_completed"
14339 [(set (match_dup 4)
14340 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14341 (match_dup 3)))
14342 (set (match_dup 0)
14343 (compare:CC (match_dup 4)
14344 (const_int 0)))]
14345 "")
14347 (define_insn ""
14348 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14349 (compare:CC
14350 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14351 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14352 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14353 (const_int 0)))
14354 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14355 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14356 "TARGET_32BIT"
14357 "@
14358 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
14359 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
14360 #
14361 #"
14362 [(set_attr "type" "compare")
14363 (set_attr "length" "8,8,12,12")])
14365 (define_split
14366 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14367 (compare:CC
14368 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14369 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14370 (match_operand:SI 3 "gpc_reg_operand" ""))
14371 (const_int 0)))
14372 (set (match_operand:SI 0 "gpc_reg_operand" "")
14373 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14374 "TARGET_32BIT && reload_completed"
14375 [(set (match_dup 0)
14376 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14377 (set (match_dup 4)
14378 (compare:CC (match_dup 0)
14379 (const_int 0)))]
14380 "")
14382 (define_insn "*neg_geu<mode>"
14383 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14384 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14385 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14386 ""
14387 "@
14388 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
14389 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
14390 [(set_attr "type" "three")
14391 (set_attr "length" "12")])
14393 (define_insn "*and_neg_geu<mode>"
14394 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14395 (and:P (neg:P
14396 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14397 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14398 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14399 ""
14400 "@
14401 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
14402 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14403 [(set_attr "type" "three")
14404 (set_attr "length" "12")])
14406 (define_insn ""
14407 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14408 (compare:CC
14409 (and:SI (neg:SI
14410 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14411 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14412 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14413 (const_int 0)))
14414 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14415 "TARGET_32BIT"
14416 "@
14417 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14418 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14419 #
14420 #"
14421 [(set_attr "type" "compare")
14422 (set_attr "length" "12,12,16,16")])
14424 (define_split
14425 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14426 (compare:CC
14427 (and:SI (neg:SI
14428 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14429 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14430 (match_operand:SI 3 "gpc_reg_operand" ""))
14431 (const_int 0)))
14432 (clobber (match_scratch:SI 4 ""))]
14433 "TARGET_32BIT && reload_completed"
14434 [(set (match_dup 4)
14435 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14436 (match_dup 3)))
14437 (set (match_dup 0)
14438 (compare:CC (match_dup 4)
14439 (const_int 0)))]
14440 "")
14442 (define_insn ""
14443 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14444 (compare:CC
14445 (and:SI (neg:SI
14446 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14447 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14448 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14449 (const_int 0)))
14450 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14451 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14452 "TARGET_32BIT"
14453 "@
14454 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14455 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14456 #
14457 #"
14458 [(set_attr "type" "compare")
14459 (set_attr "length" "12,12,16,16")])
14461 (define_split
14462 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14463 (compare:CC
14464 (and:SI (neg:SI
14465 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14466 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14467 (match_operand:SI 3 "gpc_reg_operand" ""))
14468 (const_int 0)))
14469 (set (match_operand:SI 0 "gpc_reg_operand" "")
14470 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14471 "TARGET_32BIT && reload_completed"
14472 [(set (match_dup 0)
14473 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14474 (set (match_dup 4)
14475 (compare:CC (match_dup 0)
14476 (const_int 0)))]
14477 "")
14479 (define_insn ""
14480 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14481 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14482 (match_operand:SI 2 "reg_or_short_operand" "r")))]
14483 "TARGET_POWER"
14484 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14485 [(set_attr "length" "12")])
14487 (define_insn ""
14488 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14489 (compare:CC
14490 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14491 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14492 (const_int 0)))
14493 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14494 (gt:SI (match_dup 1) (match_dup 2)))]
14495 "TARGET_POWER"
14496 "@
14497 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14498 #"
14499 [(set_attr "type" "delayed_compare")
14500 (set_attr "length" "12,16")])
14502 (define_split
14503 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14504 (compare:CC
14505 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14506 (match_operand:SI 2 "reg_or_short_operand" ""))
14507 (const_int 0)))
14508 (set (match_operand:SI 0 "gpc_reg_operand" "")
14509 (gt:SI (match_dup 1) (match_dup 2)))]
14510 "TARGET_POWER && reload_completed"
14511 [(set (match_dup 0)
14512 (gt:SI (match_dup 1) (match_dup 2)))
14513 (set (match_dup 3)
14514 (compare:CC (match_dup 0)
14515 (const_int 0)))]
14516 "")
14518 (define_insn "*plus_gt0<mode>"
14519 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14520 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
14521 (const_int 0))
14522 (match_operand:P 2 "gpc_reg_operand" "r")))]
14523 ""
14524 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
14525 [(set_attr "type" "three")
14526 (set_attr "length" "12")])
14528 (define_insn ""
14529 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14530 (compare:CC
14531 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14532 (const_int 0))
14533 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14534 (const_int 0)))
14535 (clobber (match_scratch:SI 3 "=&r,&r"))]
14536 "TARGET_32BIT"
14537 "@
14538 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
14539 #"
14540 [(set_attr "type" "compare")
14541 (set_attr "length" "12,16")])
14543 (define_split
14544 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14545 (compare:CC
14546 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14547 (const_int 0))
14548 (match_operand:SI 2 "gpc_reg_operand" ""))
14549 (const_int 0)))
14550 (clobber (match_scratch:SI 3 ""))]
14551 "TARGET_32BIT && reload_completed"
14552 [(set (match_dup 3)
14553 (plus:SI (gt:SI (match_dup 1) (const_int 0))
14554 (match_dup 2)))
14555 (set (match_dup 0)
14556 (compare:CC (match_dup 3)
14557 (const_int 0)))]
14558 "")
14560 (define_insn ""
14561 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14562 (compare:CC
14563 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14564 (const_int 0))
14565 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14566 (const_int 0)))
14567 (clobber (match_scratch:DI 3 "=&r,&r"))]
14568 "TARGET_64BIT"
14569 "@
14570 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14571 #"
14572 [(set_attr "type" "compare")
14573 (set_attr "length" "12,16")])
14575 (define_split
14576 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14577 (compare:CC
14578 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14579 (const_int 0))
14580 (match_operand:DI 2 "gpc_reg_operand" ""))
14581 (const_int 0)))
14582 (clobber (match_scratch:DI 3 ""))]
14583 "TARGET_64BIT && reload_completed"
14584 [(set (match_dup 3)
14585 (plus:DI (gt:DI (match_dup 1) (const_int 0))
14586 (match_dup 2)))
14587 (set (match_dup 0)
14588 (compare:CC (match_dup 3)
14589 (const_int 0)))]
14590 "")
14592 (define_insn ""
14593 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14594 (compare:CC
14595 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14596 (const_int 0))
14597 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14598 (const_int 0)))
14599 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14600 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14601 "TARGET_32BIT"
14602 "@
14603 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
14604 #"
14605 [(set_attr "type" "compare")
14606 (set_attr "length" "12,16")])
14608 (define_split
14609 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14610 (compare:CC
14611 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14612 (const_int 0))
14613 (match_operand:SI 2 "gpc_reg_operand" ""))
14614 (const_int 0)))
14615 (set (match_operand:SI 0 "gpc_reg_operand" "")
14616 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14617 "TARGET_32BIT && reload_completed"
14618 [(set (match_dup 0)
14619 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14620 (set (match_dup 3)
14621 (compare:CC (match_dup 0)
14622 (const_int 0)))]
14623 "")
14625 (define_insn ""
14626 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14627 (compare:CC
14628 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14629 (const_int 0))
14630 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14631 (const_int 0)))
14632 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14633 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14634 "TARGET_64BIT"
14635 "@
14636 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14637 #"
14638 [(set_attr "type" "compare")
14639 (set_attr "length" "12,16")])
14641 (define_split
14642 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14643 (compare:CC
14644 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14645 (const_int 0))
14646 (match_operand:DI 2 "gpc_reg_operand" ""))
14647 (const_int 0)))
14648 (set (match_operand:DI 0 "gpc_reg_operand" "")
14649 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14650 "TARGET_64BIT && reload_completed"
14651 [(set (match_dup 0)
14652 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14653 (set (match_dup 3)
14654 (compare:CC (match_dup 0)
14655 (const_int 0)))]
14656 "")
14658 (define_insn ""
14659 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14660 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14661 (match_operand:SI 2 "reg_or_short_operand" "r"))
14662 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14663 "TARGET_POWER"
14664 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14665 [(set_attr "length" "12")])
14667 (define_insn ""
14668 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14669 (compare:CC
14670 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14671 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14672 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14673 (const_int 0)))
14674 (clobber (match_scratch:SI 4 "=&r,&r"))]
14675 "TARGET_POWER"
14676 "@
14677 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14678 #"
14679 [(set_attr "type" "compare")
14680 (set_attr "length" "12,16")])
14682 (define_split
14683 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14684 (compare:CC
14685 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14686 (match_operand:SI 2 "reg_or_short_operand" ""))
14687 (match_operand:SI 3 "gpc_reg_operand" ""))
14688 (const_int 0)))
14689 (clobber (match_scratch:SI 4 ""))]
14690 "TARGET_POWER && reload_completed"
14691 [(set (match_dup 4)
14692 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14693 (set (match_dup 0)
14694 (compare:CC (match_dup 4)
14695 (const_int 0)))]
14696 "")
14698 (define_insn ""
14699 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14700 (compare:CC
14701 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14702 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14703 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14704 (const_int 0)))
14705 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14706 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14707 "TARGET_POWER"
14708 "@
14709 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14710 #"
14711 [(set_attr "type" "compare")
14712 (set_attr "length" "12,16")])
14714 (define_split
14715 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14716 (compare:CC
14717 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14718 (match_operand:SI 2 "reg_or_short_operand" ""))
14719 (match_operand:SI 3 "gpc_reg_operand" ""))
14720 (const_int 0)))
14721 (set (match_operand:SI 0 "gpc_reg_operand" "")
14722 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14723 "TARGET_POWER && reload_completed"
14724 [(set (match_dup 0)
14725 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14726 (set (match_dup 4)
14727 (compare:CC (match_dup 0)
14728 (const_int 0)))]
14729 "")
14731 (define_insn ""
14732 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14733 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14734 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
14735 "TARGET_POWER"
14736 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14737 [(set_attr "length" "12")])
14739 (define_insn_and_split "*gtu<mode>"
14740 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14741 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14742 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14743 ""
14744 "#"
14745 ""
14746 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14747 (set (match_dup 0) (neg:P (match_dup 0)))]
14748 "")
14750 (define_insn_and_split "*gtu<mode>_compare"
14751 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14752 (compare:CC
14753 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14754 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14755 (const_int 0)))
14756 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14757 (gtu:P (match_dup 1) (match_dup 2)))]
14758 ""
14759 "#"
14760 ""
14761 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14762 (parallel [(set (match_dup 3)
14763 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14764 (set (match_dup 0) (neg:P (match_dup 0)))])]
14765 "")
14767 (define_insn_and_split "*plus_gtu<mode>"
14768 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14769 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14770 (match_operand:P 2 "reg_or_short_operand" "rI"))
14771 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14772 ""
14773 "#"
14774 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14775 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14776 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14777 "")
14779 (define_insn_and_split "*plus_gtu<mode>_compare"
14780 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14781 (compare:CC
14782 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14783 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14784 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14785 (const_int 0)))
14786 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14787 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14788 ""
14789 "#"
14790 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14791 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14792 (parallel [(set (match_dup 4)
14793 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14794 (const_int 0)))
14795 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14796 "")
14798 (define_insn "*neg_gtu<mode>"
14799 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14800 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14801 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14802 ""
14803 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
14804 [(set_attr "type" "two")
14805 (set_attr "length" "8")])
14807 \f
14808 ;; Define both directions of branch and return. If we need a reload
14809 ;; register, we'd rather use CR0 since it is much easier to copy a
14810 ;; register CC value to there.
14812 (define_insn ""
14813 [(set (pc)
14814 (if_then_else (match_operator 1 "branch_comparison_operator"
14815 [(match_operand 2
14816 "cc_reg_operand" "y")
14817 (const_int 0)])
14818 (label_ref (match_operand 0 "" ""))
14819 (pc)))]
14820 ""
14821 "*
14822 {
14823 return output_cbranch (operands[1], \"%l0\", 0, insn);
14824 }"
14825 [(set_attr "type" "branch")])
14827 (define_insn ""
14828 [(set (pc)
14829 (if_then_else (match_operator 0 "branch_comparison_operator"
14830 [(match_operand 1
14831 "cc_reg_operand" "y")
14832 (const_int 0)])
14833 (return)
14834 (pc)))]
14835 "direct_return ()"
14836 "*
14837 {
14838 return output_cbranch (operands[0], NULL, 0, insn);
14839 }"
14840 [(set_attr "type" "jmpreg")
14841 (set_attr "length" "4")])
14843 (define_insn ""
14844 [(set (pc)
14845 (if_then_else (match_operator 1 "branch_comparison_operator"
14846 [(match_operand 2
14847 "cc_reg_operand" "y")
14848 (const_int 0)])
14849 (pc)
14850 (label_ref (match_operand 0 "" ""))))]
14851 ""
14852 "*
14853 {
14854 return output_cbranch (operands[1], \"%l0\", 1, insn);
14855 }"
14856 [(set_attr "type" "branch")])
14858 (define_insn ""
14859 [(set (pc)
14860 (if_then_else (match_operator 0 "branch_comparison_operator"
14861 [(match_operand 1
14862 "cc_reg_operand" "y")
14863 (const_int 0)])
14864 (pc)
14865 (return)))]
14866 "direct_return ()"
14867 "*
14868 {
14869 return output_cbranch (operands[0], NULL, 1, insn);
14870 }"
14871 [(set_attr "type" "jmpreg")
14872 (set_attr "length" "4")])
14874 ;; Logic on condition register values.
14876 ; This pattern matches things like
14877 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14878 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14879 ; (const_int 1)))
14880 ; which are generated by the branch logic.
14881 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14883 (define_insn "*cceq_ior_compare"
14884 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14885 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14886 [(match_operator:SI 2
14887 "branch_positive_comparison_operator"
14888 [(match_operand 3
14889 "cc_reg_operand" "y,y")
14890 (const_int 0)])
14891 (match_operator:SI 4
14892 "branch_positive_comparison_operator"
14893 [(match_operand 5
14894 "cc_reg_operand" "0,y")
14895 (const_int 0)])])
14896 (const_int 1)))]
14897 ""
14898 "cr%q1 %E0,%j2,%j4"
14899 [(set_attr "type" "cr_logical,delayed_cr")])
14901 ; Why is the constant -1 here, but 1 in the previous pattern?
14902 ; Because ~1 has all but the low bit set.
14903 (define_insn ""
14904 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14905 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14906 [(not:SI (match_operator:SI 2
14907 "branch_positive_comparison_operator"
14908 [(match_operand 3
14909 "cc_reg_operand" "y,y")
14910 (const_int 0)]))
14911 (match_operator:SI 4
14912 "branch_positive_comparison_operator"
14913 [(match_operand 5
14914 "cc_reg_operand" "0,y")
14915 (const_int 0)])])
14916 (const_int -1)))]
14917 ""
14918 "cr%q1 %E0,%j2,%j4"
14919 [(set_attr "type" "cr_logical,delayed_cr")])
14921 (define_insn "*cceq_rev_compare"
14922 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14923 (compare:CCEQ (match_operator:SI 1
14924 "branch_positive_comparison_operator"
14925 [(match_operand 2
14926 "cc_reg_operand" "0,y")
14927 (const_int 0)])
14928 (const_int 0)))]
14929 ""
14930 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14931 [(set_attr "type" "cr_logical,delayed_cr")])
14933 ;; If we are comparing the result of two comparisons, this can be done
14934 ;; using creqv or crxor.
14936 (define_insn_and_split ""
14937 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14938 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14939 [(match_operand 2 "cc_reg_operand" "y")
14940 (const_int 0)])
14941 (match_operator 3 "branch_comparison_operator"
14942 [(match_operand 4 "cc_reg_operand" "y")
14943 (const_int 0)])))]
14944 ""
14945 "#"
14946 ""
14947 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14948 (match_dup 5)))]
14949 "
14950 {
14951 int positive_1, positive_2;
14953 positive_1 = branch_positive_comparison_operator (operands[1],
14954 GET_MODE (operands[1]));
14955 positive_2 = branch_positive_comparison_operator (operands[3],
14956 GET_MODE (operands[3]));
14958 if (! positive_1)
14959 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14960 GET_CODE (operands[1])),
14961 SImode,
14962 operands[2], const0_rtx);
14963 else if (GET_MODE (operands[1]) != SImode)
14964 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14965 operands[2], const0_rtx);
14967 if (! positive_2)
14968 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14969 GET_CODE (operands[3])),
14970 SImode,
14971 operands[4], const0_rtx);
14972 else if (GET_MODE (operands[3]) != SImode)
14973 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14974 operands[4], const0_rtx);
14976 if (positive_1 == positive_2)
14977 {
14978 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14979 operands[5] = constm1_rtx;
14980 }
14981 else
14982 {
14983 operands[5] = const1_rtx;
14984 }
14985 }")
14987 ;; Unconditional branch and return.
14989 (define_insn "jump"
14990 [(set (pc)
14991 (label_ref (match_operand 0 "" "")))]
14992 ""
14993 "b %l0"
14994 [(set_attr "type" "branch")])
14996 (define_insn "return"
14997 [(return)]
14998 "direct_return ()"
14999 "{br|blr}"
15000 [(set_attr "type" "jmpreg")])
15002 (define_expand "indirect_jump"
15003 [(set (pc) (match_operand 0 "register_operand" ""))])
15005 (define_insn "*indirect_jump<mode>"
15006 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
15007 ""
15008 "@
15009 bctr
15010 {br|blr}"
15011 [(set_attr "type" "jmpreg")])
15013 ;; Table jump for switch statements:
15014 (define_expand "tablejump"
15015 [(use (match_operand 0 "" ""))
15016 (use (label_ref (match_operand 1 "" "")))]
15017 ""
15018 "
15019 {
15020 if (TARGET_32BIT)
15021 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
15022 else
15023 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
15024 DONE;
15025 }")
15027 (define_expand "tablejumpsi"
15028 [(set (match_dup 3)
15029 (plus:SI (match_operand:SI 0 "" "")
15030 (match_dup 2)))
15031 (parallel [(set (pc) (match_dup 3))
15032 (use (label_ref (match_operand 1 "" "")))])]
15033 "TARGET_32BIT"
15034 "
15035 { operands[0] = force_reg (SImode, operands[0]);
15036 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
15037 operands[3] = gen_reg_rtx (SImode);
15038 }")
15040 (define_expand "tablejumpdi"
15041 [(set (match_dup 4)
15042 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
15043 (set (match_dup 3)
15044 (plus:DI (match_dup 4)
15045 (match_dup 2)))
15046 (parallel [(set (pc) (match_dup 3))
15047 (use (label_ref (match_operand 1 "" "")))])]
15048 "TARGET_64BIT"
15049 "
15050 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
15051 operands[3] = gen_reg_rtx (DImode);
15052 operands[4] = gen_reg_rtx (DImode);
15053 }")
15055 (define_insn "*tablejump<mode>_internal1"
15056 [(set (pc)
15057 (match_operand:P 0 "register_operand" "c,*l"))
15058 (use (label_ref (match_operand 1 "" "")))]
15059 ""
15060 "@
15061 bctr
15062 {br|blr}"
15063 [(set_attr "type" "jmpreg")])
15065 (define_insn "nop"
15066 [(const_int 0)]
15067 ""
15068 "{cror 0,0,0|nop}")
15069 \f
15070 ;; Define the subtract-one-and-jump insns, starting with the template
15071 ;; so loop.c knows what to generate.
15073 (define_expand "doloop_end"
15074 [(use (match_operand 0 "" "")) ; loop pseudo
15075 (use (match_operand 1 "" "")) ; iterations; zero if unknown
15076 (use (match_operand 2 "" "")) ; max iterations
15077 (use (match_operand 3 "" "")) ; loop level
15078 (use (match_operand 4 "" ""))] ; label
15079 ""
15080 "
15081 {
15082 /* Only use this on innermost loops. */
15083 if (INTVAL (operands[3]) > 1)
15084 FAIL;
15085 if (TARGET_64BIT)
15086 {
15087 if (GET_MODE (operands[0]) != DImode)
15088 FAIL;
15089 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
15090 }
15091 else
15092 {
15093 if (GET_MODE (operands[0]) != SImode)
15094 FAIL;
15095 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
15096 }
15097 DONE;
15098 }")
15100 (define_expand "ctr<mode>"
15101 [(parallel [(set (pc)
15102 (if_then_else (ne (match_operand:P 0 "register_operand" "")
15103 (const_int 1))
15104 (label_ref (match_operand 1 "" ""))
15105 (pc)))
15106 (set (match_dup 0)
15107 (plus:P (match_dup 0)
15108 (const_int -1)))
15109 (clobber (match_scratch:CC 2 ""))
15110 (clobber (match_scratch:P 3 ""))])]
15111 ""
15112 "")
15114 ;; We need to be able to do this for any operand, including MEM, or we
15115 ;; will cause reload to blow up since we don't allow output reloads on
15116 ;; JUMP_INSNs.
15117 ;; For the length attribute to be calculated correctly, the
15118 ;; label MUST be operand 0.
15120 (define_insn "*ctr<mode>_internal1"
15121 [(set (pc)
15122 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15123 (const_int 1))
15124 (label_ref (match_operand 0 "" ""))
15125 (pc)))
15126 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15127 (plus:P (match_dup 1)
15128 (const_int -1)))
15129 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15130 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15131 ""
15132 "*
15133 {
15134 if (which_alternative != 0)
15135 return \"#\";
15136 else if (get_attr_length (insn) == 4)
15137 return \"{bdn|bdnz} %l0\";
15138 else
15139 return \"bdz $+8\;b %l0\";
15140 }"
15141 [(set_attr "type" "branch")
15142 (set_attr "length" "*,12,16,16")])
15144 (define_insn "*ctr<mode>_internal2"
15145 [(set (pc)
15146 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15147 (const_int 1))
15148 (pc)
15149 (label_ref (match_operand 0 "" ""))))
15150 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15151 (plus:P (match_dup 1)
15152 (const_int -1)))
15153 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15154 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15155 ""
15156 "*
15157 {
15158 if (which_alternative != 0)
15159 return \"#\";
15160 else if (get_attr_length (insn) == 4)
15161 return \"bdz %l0\";
15162 else
15163 return \"{bdn|bdnz} $+8\;b %l0\";
15164 }"
15165 [(set_attr "type" "branch")
15166 (set_attr "length" "*,12,16,16")])
15168 ;; Similar but use EQ
15170 (define_insn "*ctr<mode>_internal5"
15171 [(set (pc)
15172 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15173 (const_int 1))
15174 (label_ref (match_operand 0 "" ""))
15175 (pc)))
15176 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15177 (plus:P (match_dup 1)
15178 (const_int -1)))
15179 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15180 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15181 ""
15182 "*
15183 {
15184 if (which_alternative != 0)
15185 return \"#\";
15186 else if (get_attr_length (insn) == 4)
15187 return \"bdz %l0\";
15188 else
15189 return \"{bdn|bdnz} $+8\;b %l0\";
15190 }"
15191 [(set_attr "type" "branch")
15192 (set_attr "length" "*,12,16,16")])
15194 (define_insn "*ctr<mode>_internal6"
15195 [(set (pc)
15196 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15197 (const_int 1))
15198 (pc)
15199 (label_ref (match_operand 0 "" ""))))
15200 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15201 (plus:P (match_dup 1)
15202 (const_int -1)))
15203 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15204 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15205 ""
15206 "*
15207 {
15208 if (which_alternative != 0)
15209 return \"#\";
15210 else if (get_attr_length (insn) == 4)
15211 return \"{bdn|bdnz} %l0\";
15212 else
15213 return \"bdz $+8\;b %l0\";
15214 }"
15215 [(set_attr "type" "branch")
15216 (set_attr "length" "*,12,16,16")])
15218 ;; Now the splitters if we could not allocate the CTR register
15220 (define_split
15221 [(set (pc)
15222 (if_then_else (match_operator 2 "comparison_operator"
15223 [(match_operand:P 1 "gpc_reg_operand" "")
15224 (const_int 1)])
15225 (match_operand 5 "" "")
15226 (match_operand 6 "" "")))
15227 (set (match_operand:P 0 "gpc_reg_operand" "")
15228 (plus:P (match_dup 1) (const_int -1)))
15229 (clobber (match_scratch:CC 3 ""))
15230 (clobber (match_scratch:P 4 ""))]
15231 "reload_completed"
15232 [(parallel [(set (match_dup 3)
15233 (compare:CC (plus:P (match_dup 1)
15234 (const_int -1))
15235 (const_int 0)))
15236 (set (match_dup 0)
15237 (plus:P (match_dup 1)
15238 (const_int -1)))])
15239 (set (pc) (if_then_else (match_dup 7)
15240 (match_dup 5)
15241 (match_dup 6)))]
15242 "
15243 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15244 operands[3], const0_rtx); }")
15246 (define_split
15247 [(set (pc)
15248 (if_then_else (match_operator 2 "comparison_operator"
15249 [(match_operand:P 1 "gpc_reg_operand" "")
15250 (const_int 1)])
15251 (match_operand 5 "" "")
15252 (match_operand 6 "" "")))
15253 (set (match_operand:P 0 "nonimmediate_operand" "")
15254 (plus:P (match_dup 1) (const_int -1)))
15255 (clobber (match_scratch:CC 3 ""))
15256 (clobber (match_scratch:P 4 ""))]
15257 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15258 [(parallel [(set (match_dup 3)
15259 (compare:CC (plus:P (match_dup 1)
15260 (const_int -1))
15261 (const_int 0)))
15262 (set (match_dup 4)
15263 (plus:P (match_dup 1)
15264 (const_int -1)))])
15265 (set (match_dup 0)
15266 (match_dup 4))
15267 (set (pc) (if_then_else (match_dup 7)
15268 (match_dup 5)
15269 (match_dup 6)))]
15270 "
15271 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15272 operands[3], const0_rtx); }")
15273 \f
15274 (define_insn "trap"
15275 [(trap_if (const_int 1) (const_int 0))]
15276 ""
15277 "{t 31,0,0|trap}"
15278 [(set_attr "type" "trap")])
15280 (define_expand "ctrap<mode>4"
15281 [(trap_if (match_operator 0 "ordered_comparison_operator"
15282 [(match_operand:GPR 1 "register_operand")
15283 (match_operand:GPR 2 "reg_or_short_operand")])
15284 (match_operand 3 "zero_constant" ""))]
15285 ""
15286 "")
15288 (define_insn ""
15289 [(trap_if (match_operator 0 "ordered_comparison_operator"
15290 [(match_operand:GPR 1 "register_operand" "r")
15291 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15292 (const_int 0))]
15293 ""
15294 "{t|t<wd>}%V0%I2 %1,%2"
15295 [(set_attr "type" "trap")])
15296 \f
15297 ;; Insns related to generating the function prologue and epilogue.
15299 (define_expand "prologue"
15300 [(use (const_int 0))]
15301 "TARGET_SCHED_PROLOG"
15302 "
15303 {
15304 rs6000_emit_prologue ();
15305 DONE;
15306 }")
15308 (define_insn "*movesi_from_cr_one"
15309 [(match_parallel 0 "mfcr_operation"
15310 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15311 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15312 (match_operand 3 "immediate_operand" "n")]
15313 UNSPEC_MOVESI_FROM_CR))])]
15314 "TARGET_MFCRF"
15315 "*
15316 {
15317 int mask = 0;
15318 int i;
15319 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15320 {
15321 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15322 operands[4] = GEN_INT (mask);
15323 output_asm_insn (\"mfcr %1,%4\", operands);
15324 }
15325 return \"\";
15326 }"
15327 [(set_attr "type" "mfcrf")])
15329 (define_insn "movesi_from_cr"
15330 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15331 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15332 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15333 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15334 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15335 UNSPEC_MOVESI_FROM_CR))]
15336 ""
15337 "mfcr %0"
15338 [(set_attr "type" "mfcr")])
15340 (define_insn "*stmw"
15341 [(match_parallel 0 "stmw_operation"
15342 [(set (match_operand:SI 1 "memory_operand" "=m")
15343 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15344 "TARGET_MULTIPLE"
15345 "{stm|stmw} %2,%1"
15346 [(set_attr "type" "store_ux")])
15348 (define_insn "*save_gpregs_<mode>"
15349 [(match_parallel 0 "any_parallel_operand"
15350 [(clobber (reg:P 65))
15351 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15352 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15353 (set (match_operand:P 3 "memory_operand" "=m")
15354 (match_operand:P 4 "gpc_reg_operand" "r"))])]
15355 ""
15356 "bl %1"
15357 [(set_attr "type" "branch")
15358 (set_attr "length" "4")])
15360 (define_insn "*save_fpregs_<mode>"
15361 [(match_parallel 0 "any_parallel_operand"
15362 [(clobber (reg:P 65))
15363 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15364 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15365 (set (match_operand:DF 3 "memory_operand" "=m")
15366 (match_operand:DF 4 "gpc_reg_operand" "d"))])]
15367 ""
15368 "bl %1"
15369 [(set_attr "type" "branch")
15370 (set_attr "length" "4")])
15372 ; These are to explain that changes to the stack pointer should
15373 ; not be moved over stores to stack memory.
15374 (define_insn "stack_tie"
15375 [(set (match_operand:BLK 0 "memory_operand" "+m")
15376 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
15377 ""
15378 ""
15379 [(set_attr "length" "0")])
15382 (define_expand "epilogue"
15383 [(use (const_int 0))]
15384 "TARGET_SCHED_PROLOG"
15385 "
15386 {
15387 rs6000_emit_epilogue (FALSE);
15388 DONE;
15389 }")
15391 ; On some processors, doing the mtcrf one CC register at a time is
15392 ; faster (like on the 604e). On others, doing them all at once is
15393 ; faster; for instance, on the 601 and 750.
15395 (define_expand "movsi_to_cr_one"
15396 [(set (match_operand:CC 0 "cc_reg_operand" "")
15397 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15398 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15399 ""
15400 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15402 (define_insn "*movsi_to_cr"
15403 [(match_parallel 0 "mtcrf_operation"
15404 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15405 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15406 (match_operand 3 "immediate_operand" "n")]
15407 UNSPEC_MOVESI_TO_CR))])]
15408 ""
15409 "*
15410 {
15411 int mask = 0;
15412 int i;
15413 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15414 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15415 operands[4] = GEN_INT (mask);
15416 return \"mtcrf %4,%2\";
15417 }"
15418 [(set_attr "type" "mtcr")])
15420 (define_insn "*mtcrfsi"
15421 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15422 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15423 (match_operand 2 "immediate_operand" "n")]
15424 UNSPEC_MOVESI_TO_CR))]
15425 "GET_CODE (operands[0]) == REG
15426 && CR_REGNO_P (REGNO (operands[0]))
15427 && GET_CODE (operands[2]) == CONST_INT
15428 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15429 "mtcrf %R0,%1"
15430 [(set_attr "type" "mtcr")])
15432 ; The load-multiple instructions have similar properties.
15433 ; Note that "load_multiple" is a name known to the machine-independent
15434 ; code that actually corresponds to the PowerPC load-string.
15436 (define_insn "*lmw"
15437 [(match_parallel 0 "lmw_operation"
15438 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15439 (match_operand:SI 2 "memory_operand" "m"))])]
15440 "TARGET_MULTIPLE"
15441 "{lm|lmw} %1,%2"
15442 [(set_attr "type" "load_ux")
15443 (set_attr "cell_micro" "always")])
15445 (define_insn "*return_internal_<mode>"
15446 [(return)
15447 (use (match_operand:P 0 "register_operand" "lc"))]
15448 ""
15449 "b%T0"
15450 [(set_attr "type" "jmpreg")])
15452 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
15453 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
15455 (define_insn "*restore_gpregs_<mode>"
15456 [(match_parallel 0 "any_parallel_operand"
15457 [(clobber (match_operand:P 1 "register_operand" "=l"))
15458 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15459 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15460 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15461 (match_operand:P 5 "memory_operand" "m"))])]
15462 ""
15463 "bl %2"
15464 [(set_attr "type" "branch")
15465 (set_attr "length" "4")])
15467 (define_insn "*return_and_restore_gpregs_<mode>"
15468 [(match_parallel 0 "any_parallel_operand"
15469 [(return)
15470 (clobber (match_operand:P 1 "register_operand" "=l"))
15471 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15472 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15473 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15474 (match_operand:P 5 "memory_operand" "m"))])]
15475 ""
15476 "b %2"
15477 [(set_attr "type" "branch")
15478 (set_attr "length" "4")])
15480 (define_insn "*return_and_restore_fpregs_<mode>"
15481 [(match_parallel 0 "any_parallel_operand"
15482 [(return)
15483 (clobber (match_operand:P 1 "register_operand" "=l"))
15484 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15485 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15486 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
15487 (match_operand:DF 5 "memory_operand" "m"))])]
15488 ""
15489 "b %2"
15490 [(set_attr "type" "branch")
15491 (set_attr "length" "4")])
15493 (define_insn "*return_and_restore_fpregs_aix_<mode>"
15494 [(match_parallel 0 "any_parallel_operand"
15495 [(return)
15496 (use (match_operand:P 1 "register_operand" "l"))
15497 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15498 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15499 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
15500 (match_operand:DF 5 "memory_operand" "m"))])]
15501 ""
15502 "b %2"
15503 [(set_attr "type" "branch")
15504 (set_attr "length" "4")])
15506 ; This is used in compiling the unwind routines.
15507 (define_expand "eh_return"
15508 [(use (match_operand 0 "general_operand" ""))]
15509 ""
15510 "
15511 {
15512 if (TARGET_32BIT)
15513 emit_insn (gen_eh_set_lr_si (operands[0]));
15514 else
15515 emit_insn (gen_eh_set_lr_di (operands[0]));
15516 DONE;
15517 }")
15519 ; We can't expand this before we know where the link register is stored.
15520 (define_insn "eh_set_lr_<mode>"
15521 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
15522 UNSPECV_EH_RR)
15523 (clobber (match_scratch:P 1 "=&b"))]
15524 ""
15525 "#")
15527 (define_split
15528 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
15529 (clobber (match_scratch 1 ""))]
15530 "reload_completed"
15531 [(const_int 0)]
15532 "
15533 {
15534 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
15535 DONE;
15536 }")
15538 (define_insn "prefetch"
15539 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
15540 (match_operand:SI 1 "const_int_operand" "n")
15541 (match_operand:SI 2 "const_int_operand" "n"))]
15542 "TARGET_POWERPC"
15543 "*
15544 {
15545 if (GET_CODE (operands[0]) == REG)
15546 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
15547 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
15548 }"
15549 [(set_attr "type" "load")])
15550 \f
15551 (define_insn "bpermd_<mode>"
15552 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15553 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
15554 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
15555 "TARGET_POPCNTD"
15556 "bpermd %0,%1,%2"
15557 [(set_attr "type" "integer")])
15559 \f
15561 (include "sync.md")
15562 (include "vector.md")
15563 (include "vsx.md")
15564 (include "altivec.md")
15565 (include "spe.md")
15566 (include "dfp.md")
15567 (include "paired.md")