| blob | 3106648c81c756b4af203d8305d1e6d2bf7a5a7f |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; REGNOS
27 ;;
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (CA_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
52 ;;
53 ;; UNSPEC usage
54 ;;
56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_PROBE_STACK 4) ; probe stack memory reference
59 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
60 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
61 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
62 (UNSPEC_MOVSI_GOT 8)
63 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
64 (UNSPEC_FCTIWZ 10)
65 (UNSPEC_FRIM 11)
66 (UNSPEC_FRIN 12)
67 (UNSPEC_FRIP 13)
68 (UNSPEC_FRIZ 14)
69 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
70 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
71 (UNSPEC_TLSGD 17)
72 (UNSPEC_TLSLD 18)
73 (UNSPEC_MOVESI_FROM_CR 19)
74 (UNSPEC_MOVESI_TO_CR 20)
75 (UNSPEC_TLSDTPREL 21)
76 (UNSPEC_TLSDTPRELHA 22)
77 (UNSPEC_TLSDTPRELLO 23)
78 (UNSPEC_TLSGOTDTPREL 24)
79 (UNSPEC_TLSTPREL 25)
80 (UNSPEC_TLSTPRELHA 26)
81 (UNSPEC_TLSTPRELLO 27)
82 (UNSPEC_TLSGOTTPREL 28)
83 (UNSPEC_TLSTLS 29)
84 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
85 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
86 (UNSPEC_STFIWX 32)
87 (UNSPEC_POPCNTB 33)
88 (UNSPEC_FRES 34)
89 (UNSPEC_SP_SET 35)
90 (UNSPEC_SP_TEST 36)
91 (UNSPEC_SYNC 37)
92 (UNSPEC_LWSYNC 38)
93 (UNSPEC_ISYNC 39)
94 (UNSPEC_SYNC_OP 40)
95 (UNSPEC_ATOMIC 41)
96 (UNSPEC_CMPXCHG 42)
97 (UNSPEC_XCHG 43)
98 (UNSPEC_AND 44)
99 (UNSPEC_DLMZB 45)
100 (UNSPEC_DLMZB_CR 46)
101 (UNSPEC_DLMZB_STRLEN 47)
102 (UNSPEC_RSQRT 48)
103 (UNSPEC_TOCREL 49)
104 (UNSPEC_MACHOPIC_OFFSET 50)
105 (UNSPEC_BPERM 51)
106 ])
108 ;;
109 ;; UNSPEC_VOLATILE usage
110 ;;
112 (define_constants
113 [(UNSPECV_BLOCK 0)
114 (UNSPECV_LL 1) ; load-locked
115 (UNSPECV_SC 2) ; store-conditional
116 (UNSPECV_EH_RR 9) ; eh_reg_restore
117 ])
118 \f
119 ;; Define an insn type attribute. This is used in function unit delay
120 ;; computations.
121 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
122 (const_string "integer"))
124 ;; Define floating point instruction sub-types for use with Xfpu.md
125 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
127 ;; Length (in bytes).
128 ; '(pc)' in the following doesn't include the instruction itself; it is
129 ; calculated as if the instruction had zero size.
130 (define_attr "length" ""
131 (if_then_else (eq_attr "type" "branch")
132 (if_then_else (and (ge (minus (match_dup 0) (pc))
133 (const_int -32768))
134 (lt (minus (match_dup 0) (pc))
135 (const_int 32764)))
136 (const_int 4)
137 (const_int 8))
138 (const_int 4)))
140 ;; Processor type -- this attribute must exactly match the processor_type
141 ;; enumeration in rs6000.h.
143 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2"
144 (const (symbol_ref "rs6000_cpu_attr")))
147 ;; If this instruction is microcoded on the CELL processor
148 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
149 (define_attr "cell_micro" "not,conditional,always"
150 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
151 (const_string "always")
152 (const_string "not")))
154 (automata_option "ndfa")
156 (include "rios1.md")
157 (include "rios2.md")
158 (include "rs64.md")
159 (include "mpc.md")
160 (include "40x.md")
161 (include "440.md")
162 (include "476.md")
163 (include "603.md")
164 (include "6xx.md")
165 (include "7xx.md")
166 (include "7450.md")
167 (include "8540.md")
168 (include "e300c2c3.md")
169 (include "e500mc.md")
170 (include "e500mc64.md")
171 (include "power4.md")
172 (include "power5.md")
173 (include "power6.md")
174 (include "power7.md")
175 (include "cell.md")
176 (include "xfpu.md")
177 (include "a2.md")
179 (include "predicates.md")
180 (include "constraints.md")
182 (include "darwin.md")
184 \f
185 ;; Mode iterators
187 ; This mode iterator allows :GPR to be used to indicate the allowable size
188 ; of whole values in GPRs.
189 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
191 ; Any supported integer mode.
192 (define_mode_iterator INT [QI HI SI DI TI])
194 ; Any supported integer mode that fits in one register.
195 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
197 ; extend modes for DImode
198 (define_mode_iterator QHSI [QI HI SI])
200 ; SImode or DImode, even if DImode doesn't fit in GPRs.
201 (define_mode_iterator SDI [SI DI])
203 ; The size of a pointer. Also, the size of the value that a record-condition
204 ; (one with a '.') will compare; and the size used for arithmetic carries.
205 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
207 ; Any hardware-supported floating-point mode
208 (define_mode_iterator FP [
209 (SF "TARGET_HARD_FLOAT
210 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
211 (DF "TARGET_HARD_FLOAT
212 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
213 (TF "!TARGET_IEEEQUAD
214 && TARGET_HARD_FLOAT
215 && (TARGET_FPRS || TARGET_E500_DOUBLE)
216 && TARGET_LONG_DOUBLE_128")
217 (DD "TARGET_DFP")
218 (TD "TARGET_DFP")])
220 ; These modes do not fit in integer registers in 32-bit mode.
221 (define_mode_iterator DIFD [DI DF DD])
223 ;; Iterator for reciprocal estimate instructions
224 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
226 ; Various instructions that come in SI and DI forms.
227 ; A generic w/d attribute, for things like cmpw/cmpd.
228 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
230 ; DImode bits
231 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
233 ;; ISEL/ISEL64 target selection
234 (define_mode_attr sel [(SI "") (DI "64")])
236 ;; Suffix for reload patterns
237 (define_mode_attr ptrsize [(SI "32bit")
238 (DI "64bit")])
240 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
241 (DI "TARGET_64BIT")])
243 (define_mode_attr mptrsize [(SI "si")
244 (DI "di")])
246 (define_mode_attr rreg [(SF "f")
247 (DF "Ws")
248 (V4SF "Wf")
249 (V2DF "Wd")])
251 \f
252 ;; Start with fixed-point load and store insns. Here we put only the more
253 ;; complex forms. Basic data transfer is done later.
255 (define_expand "zero_extend<mode>di2"
256 [(set (match_operand:DI 0 "gpc_reg_operand" "")
257 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
258 "TARGET_POWERPC64"
259 "")
261 (define_insn "*zero_extend<mode>di2_internal1"
262 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
263 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
264 "TARGET_POWERPC64"
265 "@
266 l<wd>z%U1%X1 %0,%1
267 rldicl %0,%1,0,<dbits>"
268 [(set_attr "type" "load,*")])
270 (define_insn "*zero_extend<mode>di2_internal2"
271 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
272 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
273 (const_int 0)))
274 (clobber (match_scratch:DI 2 "=r,r"))]
275 "TARGET_64BIT"
276 "@
277 rldicl. %2,%1,0,<dbits>
278 #"
279 [(set_attr "type" "compare")
280 (set_attr "length" "4,8")])
282 (define_split
283 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
284 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
285 (const_int 0)))
286 (clobber (match_scratch:DI 2 ""))]
287 "TARGET_POWERPC64 && reload_completed"
288 [(set (match_dup 2)
289 (zero_extend:DI (match_dup 1)))
290 (set (match_dup 0)
291 (compare:CC (match_dup 2)
292 (const_int 0)))]
293 "")
295 (define_insn "*zero_extend<mode>di2_internal3"
296 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
297 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
298 (const_int 0)))
299 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
300 (zero_extend:DI (match_dup 1)))]
301 "TARGET_64BIT"
302 "@
303 rldicl. %0,%1,0,<dbits>
304 #"
305 [(set_attr "type" "compare")
306 (set_attr "length" "4,8")])
308 (define_split
309 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
310 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
311 (const_int 0)))
312 (set (match_operand:DI 0 "gpc_reg_operand" "")
313 (zero_extend:DI (match_dup 1)))]
314 "TARGET_POWERPC64 && reload_completed"
315 [(set (match_dup 0)
316 (zero_extend:DI (match_dup 1)))
317 (set (match_dup 2)
318 (compare:CC (match_dup 0)
319 (const_int 0)))]
320 "")
322 (define_insn "extendqidi2"
323 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
324 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
325 "TARGET_POWERPC64"
326 "extsb %0,%1"
327 [(set_attr "type" "exts")])
329 (define_insn ""
330 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
331 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
332 (const_int 0)))
333 (clobber (match_scratch:DI 2 "=r,r"))]
334 "TARGET_64BIT"
335 "@
336 extsb. %2,%1
337 #"
338 [(set_attr "type" "compare")
339 (set_attr "length" "4,8")])
341 (define_split
342 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
343 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
344 (const_int 0)))
345 (clobber (match_scratch:DI 2 ""))]
346 "TARGET_POWERPC64 && reload_completed"
347 [(set (match_dup 2)
348 (sign_extend:DI (match_dup 1)))
349 (set (match_dup 0)
350 (compare:CC (match_dup 2)
351 (const_int 0)))]
352 "")
354 (define_insn ""
355 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
356 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
357 (const_int 0)))
358 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
359 (sign_extend:DI (match_dup 1)))]
360 "TARGET_64BIT"
361 "@
362 extsb. %0,%1
363 #"
364 [(set_attr "type" "compare")
365 (set_attr "length" "4,8")])
367 (define_split
368 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
369 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
370 (const_int 0)))
371 (set (match_operand:DI 0 "gpc_reg_operand" "")
372 (sign_extend:DI (match_dup 1)))]
373 "TARGET_POWERPC64 && reload_completed"
374 [(set (match_dup 0)
375 (sign_extend:DI (match_dup 1)))
376 (set (match_dup 2)
377 (compare:CC (match_dup 0)
378 (const_int 0)))]
379 "")
381 (define_expand "extendhidi2"
382 [(set (match_operand:DI 0 "gpc_reg_operand" "")
383 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
384 "TARGET_POWERPC64"
385 "")
387 (define_insn ""
388 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
389 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
390 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
391 "@
392 lha%U1%X1 %0,%1
393 extsh %0,%1"
394 [(set_attr "type" "load_ext,exts")])
396 (define_insn ""
397 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
398 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
399 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
400 "extsh %0,%1"
401 [(set_attr "type" "exts")])
403 (define_insn ""
404 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
405 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
406 (const_int 0)))
407 (clobber (match_scratch:DI 2 "=r,r"))]
408 "TARGET_64BIT"
409 "@
410 extsh. %2,%1
411 #"
412 [(set_attr "type" "compare")
413 (set_attr "length" "4,8")])
415 (define_split
416 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
417 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
418 (const_int 0)))
419 (clobber (match_scratch:DI 2 ""))]
420 "TARGET_POWERPC64 && reload_completed"
421 [(set (match_dup 2)
422 (sign_extend:DI (match_dup 1)))
423 (set (match_dup 0)
424 (compare:CC (match_dup 2)
425 (const_int 0)))]
426 "")
428 (define_insn ""
429 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
430 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
431 (const_int 0)))
432 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
433 (sign_extend:DI (match_dup 1)))]
434 "TARGET_64BIT"
435 "@
436 extsh. %0,%1
437 #"
438 [(set_attr "type" "compare")
439 (set_attr "length" "4,8")])
441 (define_split
442 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
443 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
444 (const_int 0)))
445 (set (match_operand:DI 0 "gpc_reg_operand" "")
446 (sign_extend:DI (match_dup 1)))]
447 "TARGET_POWERPC64 && reload_completed"
448 [(set (match_dup 0)
449 (sign_extend:DI (match_dup 1)))
450 (set (match_dup 2)
451 (compare:CC (match_dup 0)
452 (const_int 0)))]
453 "")
455 (define_expand "extendsidi2"
456 [(set (match_operand:DI 0 "gpc_reg_operand" "")
457 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
458 "TARGET_POWERPC64"
459 "")
461 (define_insn ""
462 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
463 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
464 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
465 "@
466 lwa%U1%X1 %0,%1
467 extsw %0,%1"
468 [(set_attr "type" "load_ext,exts")])
470 (define_insn ""
471 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
472 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
473 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
474 "extsw %0,%1"
475 [(set_attr "type" "exts")])
477 (define_insn ""
478 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
479 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
480 (const_int 0)))
481 (clobber (match_scratch:DI 2 "=r,r"))]
482 "TARGET_64BIT"
483 "@
484 extsw. %2,%1
485 #"
486 [(set_attr "type" "compare")
487 (set_attr "length" "4,8")])
489 (define_split
490 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
491 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
492 (const_int 0)))
493 (clobber (match_scratch:DI 2 ""))]
494 "TARGET_POWERPC64 && reload_completed"
495 [(set (match_dup 2)
496 (sign_extend:DI (match_dup 1)))
497 (set (match_dup 0)
498 (compare:CC (match_dup 2)
499 (const_int 0)))]
500 "")
502 (define_insn ""
503 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
504 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
505 (const_int 0)))
506 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
507 (sign_extend:DI (match_dup 1)))]
508 "TARGET_64BIT"
509 "@
510 extsw. %0,%1
511 #"
512 [(set_attr "type" "compare")
513 (set_attr "length" "4,8")])
515 (define_split
516 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
517 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
518 (const_int 0)))
519 (set (match_operand:DI 0 "gpc_reg_operand" "")
520 (sign_extend:DI (match_dup 1)))]
521 "TARGET_POWERPC64 && reload_completed"
522 [(set (match_dup 0)
523 (sign_extend:DI (match_dup 1)))
524 (set (match_dup 2)
525 (compare:CC (match_dup 0)
526 (const_int 0)))]
527 "")
529 (define_expand "zero_extendqisi2"
530 [(set (match_operand:SI 0 "gpc_reg_operand" "")
531 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
532 ""
533 "")
535 (define_insn ""
536 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
537 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
538 ""
539 "@
540 lbz%U1%X1 %0,%1
541 {rlinm|rlwinm} %0,%1,0,0xff"
542 [(set_attr "type" "load,*")])
544 (define_insn ""
545 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
546 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
547 (const_int 0)))
548 (clobber (match_scratch:SI 2 "=r,r"))]
549 ""
550 "@
551 {andil.|andi.} %2,%1,0xff
552 #"
553 [(set_attr "type" "fast_compare,compare")
554 (set_attr "length" "4,8")])
556 (define_split
557 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
558 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
559 (const_int 0)))
560 (clobber (match_scratch:SI 2 ""))]
561 "reload_completed"
562 [(set (match_dup 2)
563 (zero_extend:SI (match_dup 1)))
564 (set (match_dup 0)
565 (compare:CC (match_dup 2)
566 (const_int 0)))]
567 "")
569 (define_insn ""
570 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
571 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
572 (const_int 0)))
573 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
574 (zero_extend:SI (match_dup 1)))]
575 ""
576 "@
577 {andil.|andi.} %0,%1,0xff
578 #"
579 [(set_attr "type" "fast_compare,compare")
580 (set_attr "length" "4,8")])
582 (define_split
583 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
584 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
585 (const_int 0)))
586 (set (match_operand:SI 0 "gpc_reg_operand" "")
587 (zero_extend:SI (match_dup 1)))]
588 "reload_completed"
589 [(set (match_dup 0)
590 (zero_extend:SI (match_dup 1)))
591 (set (match_dup 2)
592 (compare:CC (match_dup 0)
593 (const_int 0)))]
594 "")
596 (define_expand "extendqisi2"
597 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
598 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
599 ""
600 "
601 {
602 if (TARGET_POWERPC)
603 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
604 else if (TARGET_POWER)
605 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
606 else
607 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
608 DONE;
609 }")
611 (define_insn "extendqisi2_ppc"
612 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
613 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
614 "TARGET_POWERPC"
615 "extsb %0,%1"
616 [(set_attr "type" "exts")])
618 (define_insn ""
619 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
620 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
621 (const_int 0)))
622 (clobber (match_scratch:SI 2 "=r,r"))]
623 "TARGET_POWERPC"
624 "@
625 extsb. %2,%1
626 #"
627 [(set_attr "type" "compare")
628 (set_attr "length" "4,8")])
630 (define_split
631 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
632 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
633 (const_int 0)))
634 (clobber (match_scratch:SI 2 ""))]
635 "TARGET_POWERPC && reload_completed"
636 [(set (match_dup 2)
637 (sign_extend:SI (match_dup 1)))
638 (set (match_dup 0)
639 (compare:CC (match_dup 2)
640 (const_int 0)))]
641 "")
643 (define_insn ""
644 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
645 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
646 (const_int 0)))
647 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
648 (sign_extend:SI (match_dup 1)))]
649 "TARGET_POWERPC"
650 "@
651 extsb. %0,%1
652 #"
653 [(set_attr "type" "compare")
654 (set_attr "length" "4,8")])
656 (define_split
657 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
658 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
659 (const_int 0)))
660 (set (match_operand:SI 0 "gpc_reg_operand" "")
661 (sign_extend:SI (match_dup 1)))]
662 "TARGET_POWERPC && reload_completed"
663 [(set (match_dup 0)
664 (sign_extend:SI (match_dup 1)))
665 (set (match_dup 2)
666 (compare:CC (match_dup 0)
667 (const_int 0)))]
668 "")
670 (define_expand "extendqisi2_power"
671 [(parallel [(set (match_dup 2)
672 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
673 (const_int 24)))
674 (clobber (scratch:SI))])
675 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
676 (ashiftrt:SI (match_dup 2)
677 (const_int 24)))
678 (clobber (scratch:SI))])]
679 "TARGET_POWER"
680 "
681 { operands[1] = gen_lowpart (SImode, operands[1]);
682 operands[2] = gen_reg_rtx (SImode); }")
684 (define_expand "extendqisi2_no_power"
685 [(set (match_dup 2)
686 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
687 (const_int 24)))
688 (set (match_operand:SI 0 "gpc_reg_operand" "")
689 (ashiftrt:SI (match_dup 2)
690 (const_int 24)))]
691 "! TARGET_POWER && ! TARGET_POWERPC"
692 "
693 { operands[1] = gen_lowpart (SImode, operands[1]);
694 operands[2] = gen_reg_rtx (SImode); }")
696 (define_expand "zero_extendqihi2"
697 [(set (match_operand:HI 0 "gpc_reg_operand" "")
698 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
699 ""
700 "")
702 (define_insn ""
703 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
704 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
705 ""
706 "@
707 lbz%U1%X1 %0,%1
708 {rlinm|rlwinm} %0,%1,0,0xff"
709 [(set_attr "type" "load,*")])
711 (define_insn ""
712 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
713 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
714 (const_int 0)))
715 (clobber (match_scratch:HI 2 "=r,r"))]
716 ""
717 "@
718 {andil.|andi.} %2,%1,0xff
719 #"
720 [(set_attr "type" "fast_compare,compare")
721 (set_attr "length" "4,8")])
723 (define_split
724 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
725 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
726 (const_int 0)))
727 (clobber (match_scratch:HI 2 ""))]
728 "reload_completed"
729 [(set (match_dup 2)
730 (zero_extend:HI (match_dup 1)))
731 (set (match_dup 0)
732 (compare:CC (match_dup 2)
733 (const_int 0)))]
734 "")
736 (define_insn ""
737 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
738 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
739 (const_int 0)))
740 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
741 (zero_extend:HI (match_dup 1)))]
742 ""
743 "@
744 {andil.|andi.} %0,%1,0xff
745 #"
746 [(set_attr "type" "fast_compare,compare")
747 (set_attr "length" "4,8")])
749 (define_split
750 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
751 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
752 (const_int 0)))
753 (set (match_operand:HI 0 "gpc_reg_operand" "")
754 (zero_extend:HI (match_dup 1)))]
755 "reload_completed"
756 [(set (match_dup 0)
757 (zero_extend:HI (match_dup 1)))
758 (set (match_dup 2)
759 (compare:CC (match_dup 0)
760 (const_int 0)))]
761 "")
763 (define_expand "extendqihi2"
764 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
765 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
766 ""
767 "
768 {
769 if (TARGET_POWERPC)
770 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
771 else if (TARGET_POWER)
772 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
773 else
774 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
775 DONE;
776 }")
778 (define_insn "extendqihi2_ppc"
779 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
780 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
781 "TARGET_POWERPC"
782 "extsb %0,%1"
783 [(set_attr "type" "exts")])
785 (define_insn ""
786 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
787 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
788 (const_int 0)))
789 (clobber (match_scratch:HI 2 "=r,r"))]
790 "TARGET_POWERPC"
791 "@
792 extsb. %2,%1
793 #"
794 [(set_attr "type" "compare")
795 (set_attr "length" "4,8")])
797 (define_split
798 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
799 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
800 (const_int 0)))
801 (clobber (match_scratch:HI 2 ""))]
802 "TARGET_POWERPC && reload_completed"
803 [(set (match_dup 2)
804 (sign_extend:HI (match_dup 1)))
805 (set (match_dup 0)
806 (compare:CC (match_dup 2)
807 (const_int 0)))]
808 "")
810 (define_insn ""
811 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
812 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
813 (const_int 0)))
814 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
815 (sign_extend:HI (match_dup 1)))]
816 "TARGET_POWERPC"
817 "@
818 extsb. %0,%1
819 #"
820 [(set_attr "type" "compare")
821 (set_attr "length" "4,8")])
823 (define_split
824 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
825 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
826 (const_int 0)))
827 (set (match_operand:HI 0 "gpc_reg_operand" "")
828 (sign_extend:HI (match_dup 1)))]
829 "TARGET_POWERPC && reload_completed"
830 [(set (match_dup 0)
831 (sign_extend:HI (match_dup 1)))
832 (set (match_dup 2)
833 (compare:CC (match_dup 0)
834 (const_int 0)))]
835 "")
837 (define_expand "extendqihi2_power"
838 [(parallel [(set (match_dup 2)
839 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
840 (const_int 24)))
841 (clobber (scratch:SI))])
842 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
843 (ashiftrt:SI (match_dup 2)
844 (const_int 24)))
845 (clobber (scratch:SI))])]
846 "TARGET_POWER"
847 "
848 { operands[0] = gen_lowpart (SImode, operands[0]);
849 operands[1] = gen_lowpart (SImode, operands[1]);
850 operands[2] = gen_reg_rtx (SImode); }")
852 (define_expand "extendqihi2_no_power"
853 [(set (match_dup 2)
854 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
855 (const_int 24)))
856 (set (match_operand:HI 0 "gpc_reg_operand" "")
857 (ashiftrt:SI (match_dup 2)
858 (const_int 24)))]
859 "! TARGET_POWER && ! TARGET_POWERPC"
860 "
861 { operands[0] = gen_lowpart (SImode, operands[0]);
862 operands[1] = gen_lowpart (SImode, operands[1]);
863 operands[2] = gen_reg_rtx (SImode); }")
865 (define_expand "zero_extendhisi2"
866 [(set (match_operand:SI 0 "gpc_reg_operand" "")
867 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
868 ""
869 "")
871 (define_insn ""
872 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
873 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
874 ""
875 "@
876 lhz%U1%X1 %0,%1
877 {rlinm|rlwinm} %0,%1,0,0xffff"
878 [(set_attr "type" "load,*")])
880 (define_insn ""
881 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
882 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
883 (const_int 0)))
884 (clobber (match_scratch:SI 2 "=r,r"))]
885 ""
886 "@
887 {andil.|andi.} %2,%1,0xffff
888 #"
889 [(set_attr "type" "fast_compare,compare")
890 (set_attr "length" "4,8")])
892 (define_split
893 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
894 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
895 (const_int 0)))
896 (clobber (match_scratch:SI 2 ""))]
897 "reload_completed"
898 [(set (match_dup 2)
899 (zero_extend:SI (match_dup 1)))
900 (set (match_dup 0)
901 (compare:CC (match_dup 2)
902 (const_int 0)))]
903 "")
905 (define_insn ""
906 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
907 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
908 (const_int 0)))
909 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
910 (zero_extend:SI (match_dup 1)))]
911 ""
912 "@
913 {andil.|andi.} %0,%1,0xffff
914 #"
915 [(set_attr "type" "fast_compare,compare")
916 (set_attr "length" "4,8")])
918 (define_split
919 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
920 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
921 (const_int 0)))
922 (set (match_operand:SI 0 "gpc_reg_operand" "")
923 (zero_extend:SI (match_dup 1)))]
924 "reload_completed"
925 [(set (match_dup 0)
926 (zero_extend:SI (match_dup 1)))
927 (set (match_dup 2)
928 (compare:CC (match_dup 0)
929 (const_int 0)))]
930 "")
932 (define_expand "extendhisi2"
933 [(set (match_operand:SI 0 "gpc_reg_operand" "")
934 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
935 ""
936 "")
938 (define_insn ""
939 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
940 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
941 "rs6000_gen_cell_microcode"
942 "@
943 lha%U1%X1 %0,%1
944 {exts|extsh} %0,%1"
945 [(set_attr "type" "load_ext,exts")])
947 (define_insn ""
948 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
949 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
950 "!rs6000_gen_cell_microcode"
951 "{exts|extsh} %0,%1"
952 [(set_attr "type" "exts")])
954 (define_insn ""
955 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
956 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
957 (const_int 0)))
958 (clobber (match_scratch:SI 2 "=r,r"))]
959 ""
960 "@
961 {exts.|extsh.} %2,%1
962 #"
963 [(set_attr "type" "compare")
964 (set_attr "length" "4,8")])
966 (define_split
967 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
968 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
969 (const_int 0)))
970 (clobber (match_scratch:SI 2 ""))]
971 "reload_completed"
972 [(set (match_dup 2)
973 (sign_extend:SI (match_dup 1)))
974 (set (match_dup 0)
975 (compare:CC (match_dup 2)
976 (const_int 0)))]
977 "")
979 (define_insn ""
980 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
981 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
982 (const_int 0)))
983 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
984 (sign_extend:SI (match_dup 1)))]
985 ""
986 "@
987 {exts.|extsh.} %0,%1
988 #"
989 [(set_attr "type" "compare")
990 (set_attr "length" "4,8")])
991 \f
992 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
994 (define_insn "*macchwc"
995 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
996 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
997 (match_operand:SI 2 "gpc_reg_operand" "r")
998 (const_int 16))
999 (sign_extend:SI
1000 (match_operand:HI 1 "gpc_reg_operand" "r")))
1001 (match_operand:SI 4 "gpc_reg_operand" "0"))
1002 (const_int 0)))
1003 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1004 (plus:SI (mult:SI (ashiftrt:SI
1005 (match_dup 2)
1006 (const_int 16))
1007 (sign_extend:SI
1008 (match_dup 1)))
1009 (match_dup 4)))]
1010 "TARGET_MULHW"
1011 "macchw. %0, %1, %2"
1012 [(set_attr "type" "imul3")])
1014 (define_insn "*macchw"
1015 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1016 (plus:SI (mult:SI (ashiftrt:SI
1017 (match_operand:SI 2 "gpc_reg_operand" "r")
1018 (const_int 16))
1019 (sign_extend:SI
1020 (match_operand:HI 1 "gpc_reg_operand" "r")))
1021 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1022 "TARGET_MULHW"
1023 "macchw %0, %1, %2"
1024 [(set_attr "type" "imul3")])
1026 (define_insn "*macchwuc"
1027 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1028 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1029 (match_operand:SI 2 "gpc_reg_operand" "r")
1030 (const_int 16))
1031 (zero_extend:SI
1032 (match_operand:HI 1 "gpc_reg_operand" "r")))
1033 (match_operand:SI 4 "gpc_reg_operand" "0"))
1034 (const_int 0)))
1035 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1036 (plus:SI (mult:SI (lshiftrt:SI
1037 (match_dup 2)
1038 (const_int 16))
1039 (zero_extend:SI
1040 (match_dup 1)))
1041 (match_dup 4)))]
1042 "TARGET_MULHW"
1043 "macchwu. %0, %1, %2"
1044 [(set_attr "type" "imul3")])
1046 (define_insn "*macchwu"
1047 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1048 (plus:SI (mult:SI (lshiftrt:SI
1049 (match_operand:SI 2 "gpc_reg_operand" "r")
1050 (const_int 16))
1051 (zero_extend:SI
1052 (match_operand:HI 1 "gpc_reg_operand" "r")))
1053 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1054 "TARGET_MULHW"
1055 "macchwu %0, %1, %2"
1056 [(set_attr "type" "imul3")])
1058 (define_insn "*machhwc"
1059 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1060 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1061 (match_operand:SI 1 "gpc_reg_operand" "%r")
1062 (const_int 16))
1063 (ashiftrt:SI
1064 (match_operand:SI 2 "gpc_reg_operand" "r")
1065 (const_int 16)))
1066 (match_operand:SI 4 "gpc_reg_operand" "0"))
1067 (const_int 0)))
1068 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1069 (plus:SI (mult:SI (ashiftrt:SI
1070 (match_dup 1)
1071 (const_int 16))
1072 (ashiftrt:SI
1073 (match_dup 2)
1074 (const_int 16)))
1075 (match_dup 4)))]
1076 "TARGET_MULHW"
1077 "machhw. %0, %1, %2"
1078 [(set_attr "type" "imul3")])
1080 (define_insn "*machhw"
1081 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1082 (plus:SI (mult:SI (ashiftrt:SI
1083 (match_operand:SI 1 "gpc_reg_operand" "%r")
1084 (const_int 16))
1085 (ashiftrt:SI
1086 (match_operand:SI 2 "gpc_reg_operand" "r")
1087 (const_int 16)))
1088 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1089 "TARGET_MULHW"
1090 "machhw %0, %1, %2"
1091 [(set_attr "type" "imul3")])
1093 (define_insn "*machhwuc"
1094 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1095 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1096 (match_operand:SI 1 "gpc_reg_operand" "%r")
1097 (const_int 16))
1098 (lshiftrt:SI
1099 (match_operand:SI 2 "gpc_reg_operand" "r")
1100 (const_int 16)))
1101 (match_operand:SI 4 "gpc_reg_operand" "0"))
1102 (const_int 0)))
1103 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1104 (plus:SI (mult:SI (lshiftrt:SI
1105 (match_dup 1)
1106 (const_int 16))
1107 (lshiftrt:SI
1108 (match_dup 2)
1109 (const_int 16)))
1110 (match_dup 4)))]
1111 "TARGET_MULHW"
1112 "machhwu. %0, %1, %2"
1113 [(set_attr "type" "imul3")])
1115 (define_insn "*machhwu"
1116 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1117 (plus:SI (mult:SI (lshiftrt:SI
1118 (match_operand:SI 1 "gpc_reg_operand" "%r")
1119 (const_int 16))
1120 (lshiftrt:SI
1121 (match_operand:SI 2 "gpc_reg_operand" "r")
1122 (const_int 16)))
1123 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1124 "TARGET_MULHW"
1125 "machhwu %0, %1, %2"
1126 [(set_attr "type" "imul3")])
1128 (define_insn "*maclhwc"
1129 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1130 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1131 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1132 (sign_extend:SI
1133 (match_operand:HI 2 "gpc_reg_operand" "r")))
1134 (match_operand:SI 4 "gpc_reg_operand" "0"))
1135 (const_int 0)))
1136 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1137 (plus:SI (mult:SI (sign_extend:SI
1138 (match_dup 1))
1139 (sign_extend:SI
1140 (match_dup 2)))
1141 (match_dup 4)))]
1142 "TARGET_MULHW"
1143 "maclhw. %0, %1, %2"
1144 [(set_attr "type" "imul3")])
1146 (define_insn "*maclhw"
1147 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1148 (plus:SI (mult:SI (sign_extend:SI
1149 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1150 (sign_extend:SI
1151 (match_operand:HI 2 "gpc_reg_operand" "r")))
1152 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1153 "TARGET_MULHW"
1154 "maclhw %0, %1, %2"
1155 [(set_attr "type" "imul3")])
1157 (define_insn "*maclhwuc"
1158 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1159 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1160 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1161 (zero_extend:SI
1162 (match_operand:HI 2 "gpc_reg_operand" "r")))
1163 (match_operand:SI 4 "gpc_reg_operand" "0"))
1164 (const_int 0)))
1165 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1166 (plus:SI (mult:SI (zero_extend:SI
1167 (match_dup 1))
1168 (zero_extend:SI
1169 (match_dup 2)))
1170 (match_dup 4)))]
1171 "TARGET_MULHW"
1172 "maclhwu. %0, %1, %2"
1173 [(set_attr "type" "imul3")])
1175 (define_insn "*maclhwu"
1176 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1177 (plus:SI (mult:SI (zero_extend:SI
1178 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1179 (zero_extend:SI
1180 (match_operand:HI 2 "gpc_reg_operand" "r")))
1181 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1182 "TARGET_MULHW"
1183 "maclhwu %0, %1, %2"
1184 [(set_attr "type" "imul3")])
1186 (define_insn "*nmacchwc"
1187 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1188 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1189 (mult:SI (ashiftrt:SI
1190 (match_operand:SI 2 "gpc_reg_operand" "r")
1191 (const_int 16))
1192 (sign_extend:SI
1193 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1194 (const_int 0)))
1195 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1196 (minus:SI (match_dup 4)
1197 (mult:SI (ashiftrt:SI
1198 (match_dup 2)
1199 (const_int 16))
1200 (sign_extend:SI
1201 (match_dup 1)))))]
1202 "TARGET_MULHW"
1203 "nmacchw. %0, %1, %2"
1204 [(set_attr "type" "imul3")])
1206 (define_insn "*nmacchw"
1207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1208 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1209 (mult:SI (ashiftrt:SI
1210 (match_operand:SI 2 "gpc_reg_operand" "r")
1211 (const_int 16))
1212 (sign_extend:SI
1213 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1214 "TARGET_MULHW"
1215 "nmacchw %0, %1, %2"
1216 [(set_attr "type" "imul3")])
1218 (define_insn "*nmachhwc"
1219 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1220 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1221 (mult:SI (ashiftrt:SI
1222 (match_operand:SI 1 "gpc_reg_operand" "%r")
1223 (const_int 16))
1224 (ashiftrt:SI
1225 (match_operand:SI 2 "gpc_reg_operand" "r")
1226 (const_int 16))))
1227 (const_int 0)))
1228 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1229 (minus:SI (match_dup 4)
1230 (mult:SI (ashiftrt:SI
1231 (match_dup 1)
1232 (const_int 16))
1233 (ashiftrt:SI
1234 (match_dup 2)
1235 (const_int 16)))))]
1236 "TARGET_MULHW"
1237 "nmachhw. %0, %1, %2"
1238 [(set_attr "type" "imul3")])
1240 (define_insn "*nmachhw"
1241 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1242 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1243 (mult:SI (ashiftrt:SI
1244 (match_operand:SI 1 "gpc_reg_operand" "%r")
1245 (const_int 16))
1246 (ashiftrt:SI
1247 (match_operand:SI 2 "gpc_reg_operand" "r")
1248 (const_int 16)))))]
1249 "TARGET_MULHW"
1250 "nmachhw %0, %1, %2"
1251 [(set_attr "type" "imul3")])
1253 (define_insn "*nmaclhwc"
1254 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1255 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1256 (mult:SI (sign_extend:SI
1257 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1258 (sign_extend:SI
1259 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1260 (const_int 0)))
1261 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1262 (minus:SI (match_dup 4)
1263 (mult:SI (sign_extend:SI
1264 (match_dup 1))
1265 (sign_extend:SI
1266 (match_dup 2)))))]
1267 "TARGET_MULHW"
1268 "nmaclhw. %0, %1, %2"
1269 [(set_attr "type" "imul3")])
1271 (define_insn "*nmaclhw"
1272 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1273 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1274 (mult:SI (sign_extend:SI
1275 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1276 (sign_extend:SI
1277 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1278 "TARGET_MULHW"
1279 "nmaclhw %0, %1, %2"
1280 [(set_attr "type" "imul3")])
1282 (define_insn "*mulchwc"
1283 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1284 (compare:CC (mult:SI (ashiftrt:SI
1285 (match_operand:SI 2 "gpc_reg_operand" "r")
1286 (const_int 16))
1287 (sign_extend:SI
1288 (match_operand:HI 1 "gpc_reg_operand" "r")))
1289 (const_int 0)))
1290 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1291 (mult:SI (ashiftrt:SI
1292 (match_dup 2)
1293 (const_int 16))
1294 (sign_extend:SI
1295 (match_dup 1))))]
1296 "TARGET_MULHW"
1297 "mulchw. %0, %1, %2"
1298 [(set_attr "type" "imul3")])
1300 (define_insn "*mulchw"
1301 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1302 (mult:SI (ashiftrt:SI
1303 (match_operand:SI 2 "gpc_reg_operand" "r")
1304 (const_int 16))
1305 (sign_extend:SI
1306 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1307 "TARGET_MULHW"
1308 "mulchw %0, %1, %2"
1309 [(set_attr "type" "imul3")])
1311 (define_insn "*mulchwuc"
1312 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1313 (compare:CC (mult:SI (lshiftrt:SI
1314 (match_operand:SI 2 "gpc_reg_operand" "r")
1315 (const_int 16))
1316 (zero_extend:SI
1317 (match_operand:HI 1 "gpc_reg_operand" "r")))
1318 (const_int 0)))
1319 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1320 (mult:SI (lshiftrt:SI
1321 (match_dup 2)
1322 (const_int 16))
1323 (zero_extend:SI
1324 (match_dup 1))))]
1325 "TARGET_MULHW"
1326 "mulchwu. %0, %1, %2"
1327 [(set_attr "type" "imul3")])
1329 (define_insn "*mulchwu"
1330 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1331 (mult:SI (lshiftrt:SI
1332 (match_operand:SI 2 "gpc_reg_operand" "r")
1333 (const_int 16))
1334 (zero_extend:SI
1335 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1336 "TARGET_MULHW"
1337 "mulchwu %0, %1, %2"
1338 [(set_attr "type" "imul3")])
1340 (define_insn "*mulhhwc"
1341 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1342 (compare:CC (mult:SI (ashiftrt:SI
1343 (match_operand:SI 1 "gpc_reg_operand" "%r")
1344 (const_int 16))
1345 (ashiftrt:SI
1346 (match_operand:SI 2 "gpc_reg_operand" "r")
1347 (const_int 16)))
1348 (const_int 0)))
1349 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1350 (mult:SI (ashiftrt:SI
1351 (match_dup 1)
1352 (const_int 16))
1353 (ashiftrt:SI
1354 (match_dup 2)
1355 (const_int 16))))]
1356 "TARGET_MULHW"
1357 "mulhhw. %0, %1, %2"
1358 [(set_attr "type" "imul3")])
1360 (define_insn "*mulhhw"
1361 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1362 (mult:SI (ashiftrt:SI
1363 (match_operand:SI 1 "gpc_reg_operand" "%r")
1364 (const_int 16))
1365 (ashiftrt:SI
1366 (match_operand:SI 2 "gpc_reg_operand" "r")
1367 (const_int 16))))]
1368 "TARGET_MULHW"
1369 "mulhhw %0, %1, %2"
1370 [(set_attr "type" "imul3")])
1372 (define_insn "*mulhhwuc"
1373 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1374 (compare:CC (mult:SI (lshiftrt:SI
1375 (match_operand:SI 1 "gpc_reg_operand" "%r")
1376 (const_int 16))
1377 (lshiftrt:SI
1378 (match_operand:SI 2 "gpc_reg_operand" "r")
1379 (const_int 16)))
1380 (const_int 0)))
1381 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1382 (mult:SI (lshiftrt:SI
1383 (match_dup 1)
1384 (const_int 16))
1385 (lshiftrt:SI
1386 (match_dup 2)
1387 (const_int 16))))]
1388 "TARGET_MULHW"
1389 "mulhhwu. %0, %1, %2"
1390 [(set_attr "type" "imul3")])
1392 (define_insn "*mulhhwu"
1393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1394 (mult:SI (lshiftrt:SI
1395 (match_operand:SI 1 "gpc_reg_operand" "%r")
1396 (const_int 16))
1397 (lshiftrt:SI
1398 (match_operand:SI 2 "gpc_reg_operand" "r")
1399 (const_int 16))))]
1400 "TARGET_MULHW"
1401 "mulhhwu %0, %1, %2"
1402 [(set_attr "type" "imul3")])
1404 (define_insn "*mullhwc"
1405 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1406 (compare:CC (mult:SI (sign_extend:SI
1407 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1408 (sign_extend:SI
1409 (match_operand:HI 2 "gpc_reg_operand" "r")))
1410 (const_int 0)))
1411 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1412 (mult:SI (sign_extend:SI
1413 (match_dup 1))
1414 (sign_extend:SI
1415 (match_dup 2))))]
1416 "TARGET_MULHW"
1417 "mullhw. %0, %1, %2"
1418 [(set_attr "type" "imul3")])
1420 (define_insn "*mullhw"
1421 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1422 (mult:SI (sign_extend:SI
1423 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1424 (sign_extend:SI
1425 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1426 "TARGET_MULHW"
1427 "mullhw %0, %1, %2"
1428 [(set_attr "type" "imul3")])
1430 (define_insn "*mullhwuc"
1431 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1432 (compare:CC (mult:SI (zero_extend:SI
1433 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1434 (zero_extend:SI
1435 (match_operand:HI 2 "gpc_reg_operand" "r")))
1436 (const_int 0)))
1437 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1438 (mult:SI (zero_extend:SI
1439 (match_dup 1))
1440 (zero_extend:SI
1441 (match_dup 2))))]
1442 "TARGET_MULHW"
1443 "mullhwu. %0, %1, %2"
1444 [(set_attr "type" "imul3")])
1446 (define_insn "*mullhwu"
1447 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1448 (mult:SI (zero_extend:SI
1449 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1450 (zero_extend:SI
1451 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1452 "TARGET_MULHW"
1453 "mullhwu %0, %1, %2"
1454 [(set_attr "type" "imul3")])
1455 \f
1456 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1457 (define_insn "dlmzb"
1458 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1459 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1460 (match_operand:SI 2 "gpc_reg_operand" "r")]
1461 UNSPEC_DLMZB_CR))
1462 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1463 (unspec:SI [(match_dup 1)
1464 (match_dup 2)]
1465 UNSPEC_DLMZB))]
1466 "TARGET_DLMZB"
1467 "dlmzb. %0, %1, %2")
1469 (define_expand "strlensi"
1470 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1471 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1472 (match_operand:QI 2 "const_int_operand" "")
1473 (match_operand 3 "const_int_operand" "")]
1474 UNSPEC_DLMZB_STRLEN))
1475 (clobber (match_scratch:CC 4 "=x"))]
1476 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1477 {
1478 rtx result = operands[0];
1479 rtx src = operands[1];
1480 rtx search_char = operands[2];
1481 rtx align = operands[3];
1482 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1483 rtx loop_label, end_label, mem, cr0, cond;
1484 if (search_char != const0_rtx
1485 || GET_CODE (align) != CONST_INT
1486 || INTVAL (align) < 8)
1487 FAIL;
1488 word1 = gen_reg_rtx (SImode);
1489 word2 = gen_reg_rtx (SImode);
1490 scratch_dlmzb = gen_reg_rtx (SImode);
1491 scratch_string = gen_reg_rtx (Pmode);
1492 loop_label = gen_label_rtx ();
1493 end_label = gen_label_rtx ();
1494 addr = force_reg (Pmode, XEXP (src, 0));
1495 emit_move_insn (scratch_string, addr);
1496 emit_label (loop_label);
1497 mem = change_address (src, SImode, scratch_string);
1498 emit_move_insn (word1, mem);
1499 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1500 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1501 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1502 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1503 emit_jump_insn (gen_rtx_SET (VOIDmode,
1504 pc_rtx,
1505 gen_rtx_IF_THEN_ELSE (VOIDmode,
1506 cond,
1507 gen_rtx_LABEL_REF
1508 (VOIDmode,
1509 end_label),
1510 pc_rtx)));
1511 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1512 emit_jump_insn (gen_rtx_SET (VOIDmode,
1513 pc_rtx,
1514 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1515 emit_barrier ();
1516 emit_label (end_label);
1517 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1518 emit_insn (gen_subsi3 (result, scratch_string, addr));
1519 emit_insn (gen_subsi3 (result, result, const1_rtx));
1520 DONE;
1521 })
1522 \f
1523 (define_split
1524 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1525 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1526 (const_int 0)))
1527 (set (match_operand:SI 0 "gpc_reg_operand" "")
1528 (sign_extend:SI (match_dup 1)))]
1529 "reload_completed"
1530 [(set (match_dup 0)
1531 (sign_extend:SI (match_dup 1)))
1532 (set (match_dup 2)
1533 (compare:CC (match_dup 0)
1534 (const_int 0)))]
1535 "")
1537 ;; Fixed-point arithmetic insns.
1539 (define_expand "add<mode>3"
1540 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1541 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1542 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1543 ""
1544 {
1545 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1546 {
1547 if (non_short_cint_operand (operands[2], DImode))
1548 FAIL;
1549 }
1550 else if (GET_CODE (operands[2]) == CONST_INT
1551 && ! add_operand (operands[2], <MODE>mode))
1552 {
1553 rtx tmp = ((!can_create_pseudo_p ()
1554 || rtx_equal_p (operands[0], operands[1]))
1555 ? operands[0] : gen_reg_rtx (<MODE>mode));
1557 HOST_WIDE_INT val = INTVAL (operands[2]);
1558 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1559 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1561 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1562 FAIL;
1564 /* The ordering here is important for the prolog expander.
1565 When space is allocated from the stack, adding 'low' first may
1566 produce a temporary deallocation (which would be bad). */
1567 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1568 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1569 DONE;
1570 }
1571 })
1573 ;; Discourage ai/addic because of carry but provide it in an alternative
1574 ;; allowing register zero as source.
1575 (define_insn "*add<mode>3_internal1"
1576 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1577 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1578 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1579 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1580 "@
1581 {cax|add} %0,%1,%2
1582 {cal %0,%2(%1)|addi %0,%1,%2}
1583 {ai|addic} %0,%1,%2
1584 {cau|addis} %0,%1,%v2"
1585 [(set_attr "length" "4,4,4,4")])
1587 (define_insn "addsi3_high"
1588 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1589 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1590 (high:SI (match_operand 2 "" ""))))]
1591 "TARGET_MACHO && !TARGET_64BIT"
1592 "{cau|addis} %0,%1,ha16(%2)"
1593 [(set_attr "length" "4")])
1595 (define_insn "*add<mode>3_internal2"
1596 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1597 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1598 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1599 (const_int 0)))
1600 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1601 ""
1602 "@
1603 {cax.|add.} %3,%1,%2
1604 {ai.|addic.} %3,%1,%2
1605 #
1606 #"
1607 [(set_attr "type" "fast_compare,compare,compare,compare")
1608 (set_attr "length" "4,4,8,8")])
1610 (define_split
1611 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1612 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1613 (match_operand:GPR 2 "reg_or_short_operand" ""))
1614 (const_int 0)))
1615 (clobber (match_scratch:GPR 3 ""))]
1616 "reload_completed"
1617 [(set (match_dup 3)
1618 (plus:GPR (match_dup 1)
1619 (match_dup 2)))
1620 (set (match_dup 0)
1621 (compare:CC (match_dup 3)
1622 (const_int 0)))]
1623 "")
1625 (define_insn "*add<mode>3_internal3"
1626 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1627 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1628 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1629 (const_int 0)))
1630 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1631 (plus:P (match_dup 1)
1632 (match_dup 2)))]
1633 ""
1634 "@
1635 {cax.|add.} %0,%1,%2
1636 {ai.|addic.} %0,%1,%2
1637 #
1638 #"
1639 [(set_attr "type" "fast_compare,compare,compare,compare")
1640 (set_attr "length" "4,4,8,8")])
1642 (define_split
1643 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1644 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1645 (match_operand:P 2 "reg_or_short_operand" ""))
1646 (const_int 0)))
1647 (set (match_operand:P 0 "gpc_reg_operand" "")
1648 (plus:P (match_dup 1) (match_dup 2)))]
1649 "reload_completed"
1650 [(set (match_dup 0)
1651 (plus:P (match_dup 1)
1652 (match_dup 2)))
1653 (set (match_dup 3)
1654 (compare:CC (match_dup 0)
1655 (const_int 0)))]
1656 "")
1658 ;; Split an add that we can't do in one insn into two insns, each of which
1659 ;; does one 16-bit part. This is used by combine. Note that the low-order
1660 ;; add should be last in case the result gets used in an address.
1662 (define_split
1663 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1664 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1665 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1666 ""
1667 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1668 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1669 {
1670 HOST_WIDE_INT val = INTVAL (operands[2]);
1671 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1672 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1674 operands[4] = GEN_INT (low);
1675 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1676 operands[3] = GEN_INT (rest);
1677 else if (can_create_pseudo_p ())
1678 {
1679 operands[3] = gen_reg_rtx (DImode);
1680 emit_move_insn (operands[3], operands[2]);
1681 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1682 DONE;
1683 }
1684 else
1685 FAIL;
1686 })
1688 (define_insn "one_cmpl<mode>2"
1689 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1690 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1691 ""
1692 "nor %0,%1,%1")
1694 (define_insn ""
1695 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1696 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1697 (const_int 0)))
1698 (clobber (match_scratch:P 2 "=r,r"))]
1699 ""
1700 "@
1701 nor. %2,%1,%1
1702 #"
1703 [(set_attr "type" "fast_compare,compare")
1704 (set_attr "length" "4,8")])
1706 (define_split
1707 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1708 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1709 (const_int 0)))
1710 (clobber (match_scratch:P 2 ""))]
1711 "reload_completed"
1712 [(set (match_dup 2)
1713 (not:P (match_dup 1)))
1714 (set (match_dup 0)
1715 (compare:CC (match_dup 2)
1716 (const_int 0)))]
1717 "")
1719 (define_insn ""
1720 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1721 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1722 (const_int 0)))
1723 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1724 (not:P (match_dup 1)))]
1725 ""
1726 "@
1727 nor. %0,%1,%1
1728 #"
1729 [(set_attr "type" "fast_compare,compare")
1730 (set_attr "length" "4,8")])
1732 (define_split
1733 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1734 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1735 (const_int 0)))
1736 (set (match_operand:P 0 "gpc_reg_operand" "")
1737 (not:P (match_dup 1)))]
1738 "reload_completed"
1739 [(set (match_dup 0)
1740 (not:P (match_dup 1)))
1741 (set (match_dup 2)
1742 (compare:CC (match_dup 0)
1743 (const_int 0)))]
1744 "")
1746 (define_insn ""
1747 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1748 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1749 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1750 "! TARGET_POWERPC"
1751 "{sf%I1|subf%I1c} %0,%2,%1")
1753 (define_insn ""
1754 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1755 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1756 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1757 "TARGET_POWERPC"
1758 "@
1759 subf %0,%2,%1
1760 subfic %0,%2,%1")
1762 (define_insn ""
1763 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1764 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1765 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1766 (const_int 0)))
1767 (clobber (match_scratch:SI 3 "=r,r"))]
1768 "! TARGET_POWERPC"
1769 "@
1770 {sf.|subfc.} %3,%2,%1
1771 #"
1772 [(set_attr "type" "compare")
1773 (set_attr "length" "4,8")])
1775 (define_insn ""
1776 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1777 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1778 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1779 (const_int 0)))
1780 (clobber (match_scratch:P 3 "=r,r"))]
1781 "TARGET_POWERPC"
1782 "@
1783 subf. %3,%2,%1
1784 #"
1785 [(set_attr "type" "fast_compare")
1786 (set_attr "length" "4,8")])
1788 (define_split
1789 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1790 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1791 (match_operand:P 2 "gpc_reg_operand" ""))
1792 (const_int 0)))
1793 (clobber (match_scratch:P 3 ""))]
1794 "reload_completed"
1795 [(set (match_dup 3)
1796 (minus:P (match_dup 1)
1797 (match_dup 2)))
1798 (set (match_dup 0)
1799 (compare:CC (match_dup 3)
1800 (const_int 0)))]
1801 "")
1803 (define_insn ""
1804 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1805 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1806 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1807 (const_int 0)))
1808 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1809 (minus:SI (match_dup 1) (match_dup 2)))]
1810 "! TARGET_POWERPC"
1811 "@
1812 {sf.|subfc.} %0,%2,%1
1813 #"
1814 [(set_attr "type" "compare")
1815 (set_attr "length" "4,8")])
1817 (define_insn ""
1818 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1819 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1820 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1821 (const_int 0)))
1822 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1823 (minus:P (match_dup 1)
1824 (match_dup 2)))]
1825 "TARGET_POWERPC"
1826 "@
1827 subf. %0,%2,%1
1828 #"
1829 [(set_attr "type" "fast_compare")
1830 (set_attr "length" "4,8")])
1832 (define_split
1833 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1834 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1835 (match_operand:P 2 "gpc_reg_operand" ""))
1836 (const_int 0)))
1837 (set (match_operand:P 0 "gpc_reg_operand" "")
1838 (minus:P (match_dup 1)
1839 (match_dup 2)))]
1840 "reload_completed"
1841 [(set (match_dup 0)
1842 (minus:P (match_dup 1)
1843 (match_dup 2)))
1844 (set (match_dup 3)
1845 (compare:CC (match_dup 0)
1846 (const_int 0)))]
1847 "")
1849 (define_expand "sub<mode>3"
1850 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1851 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1852 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1853 ""
1854 "
1855 {
1856 if (GET_CODE (operands[2]) == CONST_INT)
1857 {
1858 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1859 negate_rtx (<MODE>mode, operands[2])));
1860 DONE;
1861 }
1862 }")
1864 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1865 ;; instruction and some auxiliary computations. Then we just have a single
1866 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1867 ;; combine.
1869 (define_expand "sminsi3"
1870 [(set (match_dup 3)
1871 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1872 (match_operand:SI 2 "reg_or_short_operand" ""))
1873 (const_int 0)
1874 (minus:SI (match_dup 2) (match_dup 1))))
1875 (set (match_operand:SI 0 "gpc_reg_operand" "")
1876 (minus:SI (match_dup 2) (match_dup 3)))]
1877 "TARGET_POWER || TARGET_ISEL"
1878 "
1879 {
1880 if (TARGET_ISEL)
1881 {
1882 operands[2] = force_reg (SImode, operands[2]);
1883 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1884 DONE;
1885 }
1887 operands[3] = gen_reg_rtx (SImode);
1888 }")
1890 (define_split
1891 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1892 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1893 (match_operand:SI 2 "reg_or_short_operand" "")))
1894 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1895 "TARGET_POWER"
1896 [(set (match_dup 3)
1897 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1898 (const_int 0)
1899 (minus:SI (match_dup 2) (match_dup 1))))
1900 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1901 "")
1903 (define_expand "smaxsi3"
1904 [(set (match_dup 3)
1905 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1906 (match_operand:SI 2 "reg_or_short_operand" ""))
1907 (const_int 0)
1908 (minus:SI (match_dup 2) (match_dup 1))))
1909 (set (match_operand:SI 0 "gpc_reg_operand" "")
1910 (plus:SI (match_dup 3) (match_dup 1)))]
1911 "TARGET_POWER || TARGET_ISEL"
1912 "
1913 {
1914 if (TARGET_ISEL)
1915 {
1916 operands[2] = force_reg (SImode, operands[2]);
1917 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1918 DONE;
1919 }
1920 operands[3] = gen_reg_rtx (SImode);
1921 }")
1923 (define_split
1924 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1925 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1926 (match_operand:SI 2 "reg_or_short_operand" "")))
1927 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1928 "TARGET_POWER"
1929 [(set (match_dup 3)
1930 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1931 (const_int 0)
1932 (minus:SI (match_dup 2) (match_dup 1))))
1933 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1934 "")
1936 (define_expand "uminsi3"
1937 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1938 (match_dup 5)))
1939 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1940 (match_dup 5)))
1941 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1942 (const_int 0)
1943 (minus:SI (match_dup 4) (match_dup 3))))
1944 (set (match_operand:SI 0 "gpc_reg_operand" "")
1945 (minus:SI (match_dup 2) (match_dup 3)))]
1946 "TARGET_POWER || TARGET_ISEL"
1947 "
1948 {
1949 if (TARGET_ISEL)
1950 {
1951 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1952 DONE;
1953 }
1954 operands[3] = gen_reg_rtx (SImode);
1955 operands[4] = gen_reg_rtx (SImode);
1956 operands[5] = GEN_INT (-2147483647 - 1);
1957 }")
1959 (define_expand "umaxsi3"
1960 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1961 (match_dup 5)))
1962 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1963 (match_dup 5)))
1964 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1965 (const_int 0)
1966 (minus:SI (match_dup 4) (match_dup 3))))
1967 (set (match_operand:SI 0 "gpc_reg_operand" "")
1968 (plus:SI (match_dup 3) (match_dup 1)))]
1969 "TARGET_POWER || TARGET_ISEL"
1970 "
1971 {
1972 if (TARGET_ISEL)
1973 {
1974 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1975 DONE;
1976 }
1977 operands[3] = gen_reg_rtx (SImode);
1978 operands[4] = gen_reg_rtx (SImode);
1979 operands[5] = GEN_INT (-2147483647 - 1);
1980 }")
1982 (define_insn ""
1983 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1984 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1985 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1986 (const_int 0)
1987 (minus:SI (match_dup 2) (match_dup 1))))]
1988 "TARGET_POWER"
1989 "doz%I2 %0,%1,%2")
1991 (define_insn ""
1992 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1993 (compare:CC
1994 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1995 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1996 (const_int 0)
1997 (minus:SI (match_dup 2) (match_dup 1)))
1998 (const_int 0)))
1999 (clobber (match_scratch:SI 3 "=r,r"))]
2000 "TARGET_POWER"
2001 "@
2002 doz%I2. %3,%1,%2
2003 #"
2004 [(set_attr "type" "delayed_compare")
2005 (set_attr "length" "4,8")])
2007 (define_split
2008 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2009 (compare:CC
2010 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2011 (match_operand:SI 2 "reg_or_short_operand" ""))
2012 (const_int 0)
2013 (minus:SI (match_dup 2) (match_dup 1)))
2014 (const_int 0)))
2015 (clobber (match_scratch:SI 3 ""))]
2016 "TARGET_POWER && reload_completed"
2017 [(set (match_dup 3)
2018 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2019 (const_int 0)
2020 (minus:SI (match_dup 2) (match_dup 1))))
2021 (set (match_dup 0)
2022 (compare:CC (match_dup 3)
2023 (const_int 0)))]
2024 "")
2026 (define_insn ""
2027 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2028 (compare:CC
2029 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2030 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2031 (const_int 0)
2032 (minus:SI (match_dup 2) (match_dup 1)))
2033 (const_int 0)))
2034 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2035 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2036 (const_int 0)
2037 (minus:SI (match_dup 2) (match_dup 1))))]
2038 "TARGET_POWER"
2039 "@
2040 doz%I2. %0,%1,%2
2041 #"
2042 [(set_attr "type" "delayed_compare")
2043 (set_attr "length" "4,8")])
2045 (define_split
2046 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2047 (compare:CC
2048 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2049 (match_operand:SI 2 "reg_or_short_operand" ""))
2050 (const_int 0)
2051 (minus:SI (match_dup 2) (match_dup 1)))
2052 (const_int 0)))
2053 (set (match_operand:SI 0 "gpc_reg_operand" "")
2054 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2055 (const_int 0)
2056 (minus:SI (match_dup 2) (match_dup 1))))]
2057 "TARGET_POWER && reload_completed"
2058 [(set (match_dup 0)
2059 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2060 (const_int 0)
2061 (minus:SI (match_dup 2) (match_dup 1))))
2062 (set (match_dup 3)
2063 (compare:CC (match_dup 0)
2064 (const_int 0)))]
2065 "")
2067 ;; We don't need abs with condition code because such comparisons should
2068 ;; never be done.
2069 (define_expand "abssi2"
2070 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2071 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2072 ""
2073 "
2074 {
2075 if (TARGET_ISEL)
2076 {
2077 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2078 DONE;
2079 }
2080 else if (! TARGET_POWER)
2081 {
2082 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2083 DONE;
2084 }
2085 }")
2087 (define_insn "*abssi2_power"
2088 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2089 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2090 "TARGET_POWER"
2091 "abs %0,%1")
2093 (define_insn_and_split "abs<mode>2_isel"
2094 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2095 (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
2096 (clobber (match_scratch:GPR 2 "=&b"))
2097 (clobber (match_scratch:CC 3 "=y"))]
2098 "TARGET_ISEL"
2099 "#"
2100 "&& reload_completed"
2101 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2102 (set (match_dup 3)
2103 (compare:CC (match_dup 1)
2104 (const_int 0)))
2105 (set (match_dup 0)
2106 (if_then_else:GPR (ge (match_dup 3)
2107 (const_int 0))
2108 (match_dup 1)
2109 (match_dup 2)))]
2110 "")
2112 (define_insn_and_split "nabs<mode>2_isel"
2113 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2114 (neg:GPR (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b"))))
2115 (clobber (match_scratch:GPR 2 "=&b"))
2116 (clobber (match_scratch:CC 3 "=y"))]
2117 "TARGET_ISEL"
2118 "#"
2119 "&& reload_completed"
2120 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2121 (set (match_dup 3)
2122 (compare:CC (match_dup 1)
2123 (const_int 0)))
2124 (set (match_dup 0)
2125 (if_then_else:GPR (ge (match_dup 3)
2126 (const_int 0))
2127 (match_dup 2)
2128 (match_dup 1)))]
2129 "")
2131 (define_insn_and_split "abssi2_nopower"
2132 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2133 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2134 (clobber (match_scratch:SI 2 "=&r,&r"))]
2135 "! TARGET_POWER && ! TARGET_ISEL"
2136 "#"
2137 "&& reload_completed"
2138 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2139 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2140 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2141 "")
2143 (define_insn "*nabs_power"
2144 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2145 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2146 "TARGET_POWER"
2147 "nabs %0,%1")
2149 (define_insn_and_split "*nabs_nopower"
2150 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2151 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2152 (clobber (match_scratch:SI 2 "=&r,&r"))]
2153 "! TARGET_POWER"
2154 "#"
2155 "&& reload_completed"
2156 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2157 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2158 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2159 "")
2161 (define_expand "neg<mode>2"
2162 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2163 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2164 ""
2165 "")
2167 (define_insn "*neg<mode>2_internal"
2168 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2169 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2170 ""
2171 "neg %0,%1")
2173 (define_insn ""
2174 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2175 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2176 (const_int 0)))
2177 (clobber (match_scratch:P 2 "=r,r"))]
2178 ""
2179 "@
2180 neg. %2,%1
2181 #"
2182 [(set_attr "type" "fast_compare")
2183 (set_attr "length" "4,8")])
2185 (define_split
2186 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2187 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2188 (const_int 0)))
2189 (clobber (match_scratch:P 2 ""))]
2190 "reload_completed"
2191 [(set (match_dup 2)
2192 (neg:P (match_dup 1)))
2193 (set (match_dup 0)
2194 (compare:CC (match_dup 2)
2195 (const_int 0)))]
2196 "")
2198 (define_insn ""
2199 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2200 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2201 (const_int 0)))
2202 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2203 (neg:P (match_dup 1)))]
2204 ""
2205 "@
2206 neg. %0,%1
2207 #"
2208 [(set_attr "type" "fast_compare")
2209 (set_attr "length" "4,8")])
2211 (define_split
2212 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2213 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2214 (const_int 0)))
2215 (set (match_operand:P 0 "gpc_reg_operand" "")
2216 (neg:P (match_dup 1)))]
2217 "reload_completed"
2218 [(set (match_dup 0)
2219 (neg:P (match_dup 1)))
2220 (set (match_dup 2)
2221 (compare:CC (match_dup 0)
2222 (const_int 0)))]
2223 "")
2225 (define_insn "clz<mode>2"
2226 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2227 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2228 ""
2229 "{cntlz|cntlz<wd>} %0,%1"
2230 [(set_attr "type" "cntlz")])
2232 (define_expand "ctz<mode>2"
2233 [(set (match_dup 2)
2234 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2235 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2236 (match_dup 2)))
2237 (clobber (scratch:CC))])
2238 (set (match_dup 4) (clz:GPR (match_dup 3)))
2239 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2240 (minus:GPR (match_dup 5) (match_dup 4)))]
2241 ""
2242 {
2243 operands[2] = gen_reg_rtx (<MODE>mode);
2244 operands[3] = gen_reg_rtx (<MODE>mode);
2245 operands[4] = gen_reg_rtx (<MODE>mode);
2246 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2247 })
2249 (define_expand "ffs<mode>2"
2250 [(set (match_dup 2)
2251 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2252 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2253 (match_dup 2)))
2254 (clobber (scratch:CC))])
2255 (set (match_dup 4) (clz:GPR (match_dup 3)))
2256 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2257 (minus:GPR (match_dup 5) (match_dup 4)))]
2258 ""
2259 {
2260 operands[2] = gen_reg_rtx (<MODE>mode);
2261 operands[3] = gen_reg_rtx (<MODE>mode);
2262 operands[4] = gen_reg_rtx (<MODE>mode);
2263 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2264 })
2266 (define_insn "popcntb<mode>2"
2267 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2268 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2269 UNSPEC_POPCNTB))]
2270 "TARGET_POPCNTB"
2271 "popcntb %0,%1")
2273 (define_insn "popcntwsi2"
2274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2275 (popcount:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2276 "TARGET_POPCNTD"
2277 "popcntw %0,%1")
2279 (define_insn "popcntddi2"
2280 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2281 (popcount:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
2282 "TARGET_POPCNTD && TARGET_POWERPC64"
2283 "popcntd %0,%1")
2285 (define_expand "popcount<mode>2"
2286 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2287 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2288 "TARGET_POPCNTB || TARGET_POPCNTD"
2289 {
2290 rs6000_emit_popcount (operands[0], operands[1]);
2291 DONE;
2292 })
2294 (define_expand "parity<mode>2"
2295 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2296 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2297 "TARGET_POPCNTB"
2298 {
2299 rs6000_emit_parity (operands[0], operands[1]);
2300 DONE;
2301 })
2303 ;; Since the hardware zeros the upper part of the register, save generating the
2304 ;; AND immediate if we are converting to unsigned
2305 (define_insn "*bswaphi2_extenddi"
2306 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2307 (zero_extend:DI
2308 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2309 "TARGET_POWERPC64"
2310 "lhbrx %0,%y1"
2311 [(set_attr "length" "4")
2312 (set_attr "type" "load")])
2314 (define_insn "*bswaphi2_extendsi"
2315 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2316 (zero_extend:SI
2317 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2318 "TARGET_POWERPC"
2319 "lhbrx %0,%y1"
2320 [(set_attr "length" "4")
2321 (set_attr "type" "load")])
2323 (define_expand "bswaphi2"
2324 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2325 (bswap:HI
2326 (match_operand:HI 1 "reg_or_mem_operand" "")))
2327 (clobber (match_scratch:SI 2 ""))])]
2328 ""
2329 {
2330 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2331 operands[1] = force_reg (HImode, operands[1]);
2332 })
2334 (define_insn "bswaphi2_internal"
2335 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2336 (bswap:HI
2337 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2338 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2339 "TARGET_POWERPC"
2340 "@
2341 lhbrx %0,%y1
2342 sthbrx %1,%y0
2343 #"
2344 [(set_attr "length" "4,4,12")
2345 (set_attr "type" "load,store,*")])
2347 (define_split
2348 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2349 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2350 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2351 "TARGET_POWERPC && reload_completed"
2352 [(set (match_dup 3)
2353 (zero_extract:SI (match_dup 4)
2354 (const_int 8)
2355 (const_int 16)))
2356 (set (match_dup 2)
2357 (and:SI (ashift:SI (match_dup 4)
2358 (const_int 8))
2359 (const_int 65280))) ;; 0xff00
2360 (set (match_dup 3)
2361 (ior:SI (match_dup 3)
2362 (match_dup 2)))]
2363 "
2364 {
2365 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2366 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2367 }")
2369 (define_insn "*bswapsi2_extenddi"
2370 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2371 (zero_extend:DI
2372 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2373 "TARGET_POWERPC64"
2374 "lwbrx %0,%y1"
2375 [(set_attr "length" "4")
2376 (set_attr "type" "load")])
2378 (define_expand "bswapsi2"
2379 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2380 (bswap:SI
2381 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2382 ""
2383 {
2384 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2385 operands[1] = force_reg (SImode, operands[1]);
2386 })
2388 (define_insn "*bswapsi2_internal"
2389 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2390 (bswap:SI
2391 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2392 ""
2393 "@
2394 {lbrx|lwbrx} %0,%y1
2395 {stbrx|stwbrx} %1,%y0
2396 #"
2397 [(set_attr "length" "4,4,12")
2398 (set_attr "type" "load,store,*")])
2400 (define_split
2401 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2402 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2403 "reload_completed"
2404 [(set (match_dup 0)
2405 (rotate:SI (match_dup 1) (const_int 8)))
2406 (set (zero_extract:SI (match_dup 0)
2407 (const_int 8)
2408 (const_int 0))
2409 (match_dup 1))
2410 (set (zero_extract:SI (match_dup 0)
2411 (const_int 8)
2412 (const_int 16))
2413 (rotate:SI (match_dup 1)
2414 (const_int 16)))]
2415 "")
2417 (define_expand "bswapdi2"
2418 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2419 (bswap:DI
2420 (match_operand:DI 1 "reg_or_mem_operand" "")))
2421 (clobber (match_scratch:DI 2 ""))
2422 (clobber (match_scratch:DI 3 ""))
2423 (clobber (match_scratch:DI 4 ""))])]
2424 ""
2425 {
2426 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2427 operands[1] = force_reg (DImode, operands[1]);
2429 if (!TARGET_POWERPC64)
2430 {
2431 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2432 that uses 64-bit registers needs the same scratch registers as 64-bit
2433 mode. */
2434 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2435 DONE;
2436 }
2437 })
2439 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2440 (define_insn "*bswapdi2_ldbrx"
2441 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2442 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2443 (clobber (match_scratch:DI 2 "=X,X,&r"))
2444 (clobber (match_scratch:DI 3 "=X,X,&r"))
2445 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2446 "TARGET_POWERPC64 && TARGET_LDBRX
2447 && (REG_P (operands[0]) || REG_P (operands[1]))"
2448 "@
2449 ldbrx %0,%y1
2450 stdbrx %1,%y0
2451 #"
2452 [(set_attr "length" "4,4,36")
2453 (set_attr "type" "load,store,*")])
2455 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2456 (define_insn "*bswapdi2_64bit"
2457 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2458 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2459 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2460 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2461 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2462 "TARGET_POWERPC64 && !TARGET_LDBRX
2463 && (REG_P (operands[0]) || REG_P (operands[1]))"
2464 "#"
2465 [(set_attr "length" "16,12,36")])
2467 (define_split
2468 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2469 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2470 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2471 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2472 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2473 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2474 [(const_int 0)]
2475 "
2476 {
2477 rtx dest = operands[0];
2478 rtx src = operands[1];
2479 rtx op2 = operands[2];
2480 rtx op3 = operands[3];
2481 rtx op4 = operands[4];
2482 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2483 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2484 rtx addr1;
2485 rtx addr2;
2486 rtx word_high;
2487 rtx word_low;
2489 addr1 = XEXP (src, 0);
2490 if (GET_CODE (addr1) == PLUS)
2491 {
2492 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2493 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2494 }
2495 else
2496 {
2497 emit_move_insn (op2, GEN_INT (4));
2498 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2499 }
2501 if (BYTES_BIG_ENDIAN)
2502 {
2503 word_high = change_address (src, SImode, addr1);
2504 word_low = change_address (src, SImode, addr2);
2505 }
2506 else
2507 {
2508 word_high = change_address (src, SImode, addr2);
2509 word_low = change_address (src, SImode, addr1);
2510 }
2512 emit_insn (gen_bswapsi2 (op3_32, word_low));
2513 emit_insn (gen_bswapsi2 (op4_32, word_high));
2514 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2515 emit_insn (gen_iordi3 (dest, dest, op4));
2516 }")
2518 (define_split
2519 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2520 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2521 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2522 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2523 (clobber (match_operand:DI 4 "" ""))]
2524 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2525 [(const_int 0)]
2526 "
2527 {
2528 rtx dest = operands[0];
2529 rtx src = operands[1];
2530 rtx op2 = operands[2];
2531 rtx op3 = operands[3];
2532 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2533 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2534 rtx addr1;
2535 rtx addr2;
2536 rtx word_high;
2537 rtx word_low;
2539 addr1 = XEXP (dest, 0);
2540 if (GET_CODE (addr1) == PLUS)
2541 {
2542 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2543 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2544 }
2545 else
2546 {
2547 emit_move_insn (op2, GEN_INT (4));
2548 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2549 }
2551 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2552 if (BYTES_BIG_ENDIAN)
2553 {
2554 word_high = change_address (dest, SImode, addr1);
2555 word_low = change_address (dest, SImode, addr2);
2556 emit_insn (gen_bswapsi2 (word_high, src_si));
2557 emit_insn (gen_bswapsi2 (word_low, op3_si));
2558 }
2559 else
2560 {
2561 word_high = change_address (dest, SImode, addr2);
2562 word_low = change_address (dest, SImode, addr1);
2563 emit_insn (gen_bswapsi2 (word_low, src_si));
2564 emit_insn (gen_bswapsi2 (word_high, op3_si));
2565 }
2566 }")
2568 (define_split
2569 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2570 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2571 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2572 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2573 (clobber (match_operand:DI 4 "" ""))]
2574 "TARGET_POWERPC64 && reload_completed"
2575 [(const_int 0)]
2576 "
2577 {
2578 rtx dest = operands[0];
2579 rtx src = operands[1];
2580 rtx op2 = operands[2];
2581 rtx op3 = operands[3];
2582 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2583 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2584 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2585 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2587 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2588 emit_insn (gen_bswapsi2 (dest_si, src_si));
2589 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2590 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2591 emit_insn (gen_iordi3 (dest, dest, op3));
2592 }")
2594 (define_insn "bswapdi2_32bit"
2595 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2596 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2597 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2598 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2599 "#"
2600 [(set_attr "length" "16,12,36")])
2602 (define_split
2603 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2604 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2605 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2606 "!TARGET_POWERPC64 && reload_completed"
2607 [(const_int 0)]
2608 "
2609 {
2610 rtx dest = operands[0];
2611 rtx src = operands[1];
2612 rtx op2 = operands[2];
2613 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2614 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2615 rtx addr1;
2616 rtx addr2;
2617 rtx word_high;
2618 rtx word_low;
2620 addr1 = XEXP (src, 0);
2621 if (GET_CODE (addr1) == PLUS)
2622 {
2623 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2624 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2625 }
2626 else
2627 {
2628 emit_move_insn (op2, GEN_INT (4));
2629 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2630 }
2632 if (BYTES_BIG_ENDIAN)
2633 {
2634 word_high = change_address (src, SImode, addr1);
2635 word_low = change_address (src, SImode, addr2);
2636 }
2637 else
2638 {
2639 word_high = change_address (src, SImode, addr2);
2640 word_low = change_address (src, SImode, addr1);
2641 }
2643 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2644 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2645 }")
2647 (define_split
2648 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2649 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2650 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2651 "!TARGET_POWERPC64 && reload_completed"
2652 [(const_int 0)]
2653 "
2654 {
2655 rtx dest = operands[0];
2656 rtx src = operands[1];
2657 rtx op2 = operands[2];
2658 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2659 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2660 rtx addr1;
2661 rtx addr2;
2662 rtx word_high;
2663 rtx word_low;
2665 addr1 = XEXP (dest, 0);
2666 if (GET_CODE (addr1) == PLUS)
2667 {
2668 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2669 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2670 }
2671 else
2672 {
2673 emit_move_insn (op2, GEN_INT (4));
2674 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2675 }
2677 if (BYTES_BIG_ENDIAN)
2678 {
2679 word_high = change_address (dest, SImode, addr1);
2680 word_low = change_address (dest, SImode, addr2);
2681 }
2682 else
2683 {
2684 word_high = change_address (dest, SImode, addr2);
2685 word_low = change_address (dest, SImode, addr1);
2686 }
2688 emit_insn (gen_bswapsi2 (word_high, src_low));
2689 emit_insn (gen_bswapsi2 (word_low, src_high));
2690 }")
2692 (define_split
2693 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2694 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2695 (clobber (match_operand:SI 2 "" ""))]
2696 "!TARGET_POWERPC64 && reload_completed"
2697 [(const_int 0)]
2698 "
2699 {
2700 rtx dest = operands[0];
2701 rtx src = operands[1];
2702 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2703 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2704 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2705 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2707 emit_insn (gen_bswapsi2 (dest_high, src_low));
2708 emit_insn (gen_bswapsi2 (dest_low, src_high));
2709 }")
2711 (define_expand "mulsi3"
2712 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2713 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2714 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2715 ""
2716 "
2717 {
2718 if (TARGET_POWER)
2719 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2720 else
2721 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2722 DONE;
2723 }")
2725 (define_insn "mulsi3_mq"
2726 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2727 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2728 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2729 (clobber (match_scratch:SI 3 "=q,q"))]
2730 "TARGET_POWER"
2731 "@
2732 {muls|mullw} %0,%1,%2
2733 {muli|mulli} %0,%1,%2"
2734 [(set (attr "type")
2735 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2736 (const_string "imul3")
2737 (match_operand:SI 2 "short_cint_operand" "")
2738 (const_string "imul2")]
2739 (const_string "imul")))])
2741 (define_insn "mulsi3_no_mq"
2742 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2743 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2744 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2745 "! TARGET_POWER"
2746 "@
2747 {muls|mullw} %0,%1,%2
2748 {muli|mulli} %0,%1,%2"
2749 [(set (attr "type")
2750 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2751 (const_string "imul3")
2752 (match_operand:SI 2 "short_cint_operand" "")
2753 (const_string "imul2")]
2754 (const_string "imul")))])
2756 (define_insn "*mulsi3_mq_internal1"
2757 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2758 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2759 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2760 (const_int 0)))
2761 (clobber (match_scratch:SI 3 "=r,r"))
2762 (clobber (match_scratch:SI 4 "=q,q"))]
2763 "TARGET_POWER"
2764 "@
2765 {muls.|mullw.} %3,%1,%2
2766 #"
2767 [(set_attr "type" "imul_compare")
2768 (set_attr "length" "4,8")])
2770 (define_split
2771 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2772 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2773 (match_operand:SI 2 "gpc_reg_operand" ""))
2774 (const_int 0)))
2775 (clobber (match_scratch:SI 3 ""))
2776 (clobber (match_scratch:SI 4 ""))]
2777 "TARGET_POWER && reload_completed"
2778 [(parallel [(set (match_dup 3)
2779 (mult:SI (match_dup 1) (match_dup 2)))
2780 (clobber (match_dup 4))])
2781 (set (match_dup 0)
2782 (compare:CC (match_dup 3)
2783 (const_int 0)))]
2784 "")
2786 (define_insn "*mulsi3_no_mq_internal1"
2787 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2788 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2789 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2790 (const_int 0)))
2791 (clobber (match_scratch:SI 3 "=r,r"))]
2792 "! TARGET_POWER"
2793 "@
2794 {muls.|mullw.} %3,%1,%2
2795 #"
2796 [(set_attr "type" "imul_compare")
2797 (set_attr "length" "4,8")])
2799 (define_split
2800 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2801 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2802 (match_operand:SI 2 "gpc_reg_operand" ""))
2803 (const_int 0)))
2804 (clobber (match_scratch:SI 3 ""))]
2805 "! TARGET_POWER && reload_completed"
2806 [(set (match_dup 3)
2807 (mult:SI (match_dup 1) (match_dup 2)))
2808 (set (match_dup 0)
2809 (compare:CC (match_dup 3)
2810 (const_int 0)))]
2811 "")
2813 (define_insn "*mulsi3_mq_internal2"
2814 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2815 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2816 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2817 (const_int 0)))
2818 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2819 (mult:SI (match_dup 1) (match_dup 2)))
2820 (clobber (match_scratch:SI 4 "=q,q"))]
2821 "TARGET_POWER"
2822 "@
2823 {muls.|mullw.} %0,%1,%2
2824 #"
2825 [(set_attr "type" "imul_compare")
2826 (set_attr "length" "4,8")])
2828 (define_split
2829 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2830 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2831 (match_operand:SI 2 "gpc_reg_operand" ""))
2832 (const_int 0)))
2833 (set (match_operand:SI 0 "gpc_reg_operand" "")
2834 (mult:SI (match_dup 1) (match_dup 2)))
2835 (clobber (match_scratch:SI 4 ""))]
2836 "TARGET_POWER && reload_completed"
2837 [(parallel [(set (match_dup 0)
2838 (mult:SI (match_dup 1) (match_dup 2)))
2839 (clobber (match_dup 4))])
2840 (set (match_dup 3)
2841 (compare:CC (match_dup 0)
2842 (const_int 0)))]
2843 "")
2845 (define_insn "*mulsi3_no_mq_internal2"
2846 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2847 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2848 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2849 (const_int 0)))
2850 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2851 (mult:SI (match_dup 1) (match_dup 2)))]
2852 "! TARGET_POWER"
2853 "@
2854 {muls.|mullw.} %0,%1,%2
2855 #"
2856 [(set_attr "type" "imul_compare")
2857 (set_attr "length" "4,8")])
2859 (define_split
2860 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2861 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2862 (match_operand:SI 2 "gpc_reg_operand" ""))
2863 (const_int 0)))
2864 (set (match_operand:SI 0 "gpc_reg_operand" "")
2865 (mult:SI (match_dup 1) (match_dup 2)))]
2866 "! TARGET_POWER && reload_completed"
2867 [(set (match_dup 0)
2868 (mult:SI (match_dup 1) (match_dup 2)))
2869 (set (match_dup 3)
2870 (compare:CC (match_dup 0)
2871 (const_int 0)))]
2872 "")
2874 ;; Operand 1 is divided by operand 2; quotient goes to operand
2875 ;; 0 and remainder to operand 3.
2876 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2878 (define_expand "divmodsi4"
2879 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2880 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2881 (match_operand:SI 2 "gpc_reg_operand" "")))
2882 (set (match_operand:SI 3 "register_operand" "")
2883 (mod:SI (match_dup 1) (match_dup 2)))])]
2884 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2885 "
2886 {
2887 if (! TARGET_POWER && ! TARGET_POWERPC)
2888 {
2889 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2890 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2891 emit_insn (gen_divss_call ());
2892 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2893 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2894 DONE;
2895 }
2896 }")
2898 (define_insn "*divmodsi4_internal"
2899 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2900 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2901 (match_operand:SI 2 "gpc_reg_operand" "r")))
2902 (set (match_operand:SI 3 "register_operand" "=q")
2903 (mod:SI (match_dup 1) (match_dup 2)))]
2904 "TARGET_POWER"
2905 "divs %0,%1,%2"
2906 [(set_attr "type" "idiv")])
2908 (define_expand "udiv<mode>3"
2909 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2910 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2911 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2912 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2913 "
2914 {
2915 if (! TARGET_POWER && ! TARGET_POWERPC)
2916 {
2917 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2918 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2919 emit_insn (gen_quous_call ());
2920 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2921 DONE;
2922 }
2923 else if (TARGET_POWER)
2924 {
2925 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2926 DONE;
2927 }
2928 }")
2930 (define_insn "udivsi3_mq"
2931 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2932 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2933 (match_operand:SI 2 "gpc_reg_operand" "r")))
2934 (clobber (match_scratch:SI 3 "=q"))]
2935 "TARGET_POWERPC && TARGET_POWER"
2936 "divwu %0,%1,%2"
2937 [(set_attr "type" "idiv")])
2939 (define_insn "*udivsi3_no_mq"
2940 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2941 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2942 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2943 "TARGET_POWERPC && ! TARGET_POWER"
2944 "div<wd>u %0,%1,%2"
2945 [(set (attr "type")
2946 (cond [(match_operand:SI 0 "" "")
2947 (const_string "idiv")]
2948 (const_string "ldiv")))])
2951 ;; For powers of two we can do srai/aze for divide and then adjust for
2952 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2953 ;; used; for PowerPC, force operands into register and do a normal divide;
2954 ;; for AIX common-mode, use quoss call on register operands.
2955 (define_expand "div<mode>3"
2956 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2957 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2958 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2959 ""
2960 "
2961 {
2962 if (GET_CODE (operands[2]) == CONST_INT
2963 && INTVAL (operands[2]) > 0
2964 && exact_log2 (INTVAL (operands[2])) >= 0)
2965 ;
2966 else if (TARGET_POWERPC)
2967 {
2968 operands[2] = force_reg (<MODE>mode, operands[2]);
2969 if (TARGET_POWER)
2970 {
2971 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2972 DONE;
2973 }
2974 }
2975 else if (TARGET_POWER)
2976 FAIL;
2977 else
2978 {
2979 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2980 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2981 emit_insn (gen_quoss_call ());
2982 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2983 DONE;
2984 }
2985 }")
2987 (define_insn "divsi3_mq"
2988 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2989 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2990 (match_operand:SI 2 "gpc_reg_operand" "r")))
2991 (clobber (match_scratch:SI 3 "=q"))]
2992 "TARGET_POWERPC && TARGET_POWER"
2993 "divw %0,%1,%2"
2994 [(set_attr "type" "idiv")])
2996 (define_insn "*div<mode>3_no_mq"
2997 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2998 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2999 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
3000 "TARGET_POWERPC && ! TARGET_POWER"
3001 "div<wd> %0,%1,%2"
3002 [(set (attr "type")
3003 (cond [(match_operand:SI 0 "" "")
3004 (const_string "idiv")]
3005 (const_string "ldiv")))])
3007 (define_expand "mod<mode>3"
3008 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
3009 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
3010 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
3011 ""
3012 "
3013 {
3014 int i;
3015 rtx temp1;
3016 rtx temp2;
3018 if (GET_CODE (operands[2]) != CONST_INT
3019 || INTVAL (operands[2]) <= 0
3020 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
3021 FAIL;
3023 temp1 = gen_reg_rtx (<MODE>mode);
3024 temp2 = gen_reg_rtx (<MODE>mode);
3026 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
3027 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
3028 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
3029 DONE;
3030 }")
3032 (define_insn ""
3033 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3034 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3035 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
3036 ""
3037 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
3038 [(set_attr "type" "two")
3039 (set_attr "length" "8")])
3041 (define_insn ""
3042 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3043 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3044 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3045 (const_int 0)))
3046 (clobber (match_scratch:P 3 "=r,r"))]
3047 ""
3048 "@
3049 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
3050 #"
3051 [(set_attr "type" "compare")
3052 (set_attr "length" "8,12")
3053 (set_attr "cell_micro" "not")])
3055 (define_split
3056 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3057 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3058 (match_operand:GPR 2 "exact_log2_cint_operand"
3059 ""))
3060 (const_int 0)))
3061 (clobber (match_scratch:GPR 3 ""))]
3062 "reload_completed"
3063 [(set (match_dup 3)
3064 (div:<MODE> (match_dup 1) (match_dup 2)))
3065 (set (match_dup 0)
3066 (compare:CC (match_dup 3)
3067 (const_int 0)))]
3068 "")
3070 (define_insn ""
3071 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3072 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3073 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3074 (const_int 0)))
3075 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
3076 (div:P (match_dup 1) (match_dup 2)))]
3077 ""
3078 "@
3079 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
3080 #"
3081 [(set_attr "type" "compare")
3082 (set_attr "length" "8,12")
3083 (set_attr "cell_micro" "not")])
3085 (define_split
3086 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3087 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3088 (match_operand:GPR 2 "exact_log2_cint_operand"
3089 ""))
3090 (const_int 0)))
3091 (set (match_operand:GPR 0 "gpc_reg_operand" "")
3092 (div:GPR (match_dup 1) (match_dup 2)))]
3093 "reload_completed"
3094 [(set (match_dup 0)
3095 (div:<MODE> (match_dup 1) (match_dup 2)))
3096 (set (match_dup 3)
3097 (compare:CC (match_dup 0)
3098 (const_int 0)))]
3099 "")
3101 (define_insn ""
3102 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3103 (udiv:SI
3104 (plus:DI (ashift:DI
3105 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3106 (const_int 32))
3107 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
3108 (match_operand:SI 3 "gpc_reg_operand" "r")))
3109 (set (match_operand:SI 2 "register_operand" "=*q")
3110 (umod:SI
3111 (plus:DI (ashift:DI
3112 (zero_extend:DI (match_dup 1)) (const_int 32))
3113 (zero_extend:DI (match_dup 4)))
3114 (match_dup 3)))]
3115 "TARGET_POWER"
3116 "div %0,%1,%3"
3117 [(set_attr "type" "idiv")])
3119 ;; To do unsigned divide we handle the cases of the divisor looking like a
3120 ;; negative number. If it is a constant that is less than 2**31, we don't
3121 ;; have to worry about the branches. So make a few subroutines here.
3122 ;;
3123 ;; First comes the normal case.
3124 (define_expand "udivmodsi4_normal"
3125 [(set (match_dup 4) (const_int 0))
3126 (parallel [(set (match_operand:SI 0 "" "")
3127 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3128 (const_int 32))
3129 (zero_extend:DI (match_operand:SI 1 "" "")))
3130 (match_operand:SI 2 "" "")))
3131 (set (match_operand:SI 3 "" "")
3132 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3133 (const_int 32))
3134 (zero_extend:DI (match_dup 1)))
3135 (match_dup 2)))])]
3136 "TARGET_POWER"
3137 "
3138 { operands[4] = gen_reg_rtx (SImode); }")
3140 ;; This handles the branches.
3141 (define_expand "udivmodsi4_tests"
3142 [(set (match_operand:SI 0 "" "") (const_int 0))
3143 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
3144 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
3145 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
3146 (label_ref (match_operand:SI 4 "" "")) (pc)))
3147 (set (match_dup 0) (const_int 1))
3148 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
3149 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
3150 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
3151 (label_ref (match_dup 4)) (pc)))]
3152 "TARGET_POWER"
3153 "
3154 { operands[5] = gen_reg_rtx (CCUNSmode);
3155 operands[6] = gen_reg_rtx (CCmode);
3156 }")
3158 (define_expand "udivmodsi4"
3159 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3160 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
3161 (match_operand:SI 2 "reg_or_cint_operand" "")))
3162 (set (match_operand:SI 3 "gpc_reg_operand" "")
3163 (umod:SI (match_dup 1) (match_dup 2)))])]
3164 ""
3165 "
3166 {
3167 rtx label = 0;
3169 if (! TARGET_POWER)
3170 {
3171 if (! TARGET_POWERPC)
3172 {
3173 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3174 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3175 emit_insn (gen_divus_call ());
3176 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3177 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3178 DONE;
3179 }
3180 else
3181 FAIL;
3182 }
3184 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
3185 {
3186 operands[2] = force_reg (SImode, operands[2]);
3187 label = gen_label_rtx ();
3188 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
3189 operands[3], label));
3190 }
3191 else
3192 operands[2] = force_reg (SImode, operands[2]);
3194 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
3195 operands[3]));
3196 if (label)
3197 emit_label (label);
3199 DONE;
3200 }")
3202 ;; AIX architecture-independent common-mode multiply (DImode),
3203 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
3204 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
3205 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
3206 ;; assumed unused if generating common-mode, so ignore.
3207 (define_insn "mulh_call"
3208 [(set (reg:SI 3)
3209 (truncate:SI
3210 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
3211 (sign_extend:DI (reg:SI 4)))
3212 (const_int 32))))
3213 (clobber (reg:SI LR_REGNO))]
3214 "! TARGET_POWER && ! TARGET_POWERPC"
3215 "bla __mulh"
3216 [(set_attr "type" "imul")])
3218 (define_insn "mull_call"
3219 [(set (reg:DI 3)
3220 (mult:DI (sign_extend:DI (reg:SI 3))
3221 (sign_extend:DI (reg:SI 4))))
3222 (clobber (reg:SI LR_REGNO))
3223 (clobber (reg:SI 0))]
3224 "! TARGET_POWER && ! TARGET_POWERPC"
3225 "bla __mull"
3226 [(set_attr "type" "imul")])
3228 (define_insn "divss_call"
3229 [(set (reg:SI 3)
3230 (div:SI (reg:SI 3) (reg:SI 4)))
3231 (set (reg:SI 4)
3232 (mod:SI (reg:SI 3) (reg:SI 4)))
3233 (clobber (reg:SI LR_REGNO))
3234 (clobber (reg:SI 0))]
3235 "! TARGET_POWER && ! TARGET_POWERPC"
3236 "bla __divss"
3237 [(set_attr "type" "idiv")])
3239 (define_insn "divus_call"
3240 [(set (reg:SI 3)
3241 (udiv:SI (reg:SI 3) (reg:SI 4)))
3242 (set (reg:SI 4)
3243 (umod:SI (reg:SI 3) (reg:SI 4)))
3244 (clobber (reg:SI LR_REGNO))
3245 (clobber (reg:SI 0))
3246 (clobber (match_scratch:CC 0 "=x"))
3247 (clobber (reg:CC CR1_REGNO))]
3248 "! TARGET_POWER && ! TARGET_POWERPC"
3249 "bla __divus"
3250 [(set_attr "type" "idiv")])
3252 (define_insn "quoss_call"
3253 [(set (reg:SI 3)
3254 (div:SI (reg:SI 3) (reg:SI 4)))
3255 (clobber (reg:SI LR_REGNO))]
3256 "! TARGET_POWER && ! TARGET_POWERPC"
3257 "bla __quoss"
3258 [(set_attr "type" "idiv")])
3260 (define_insn "quous_call"
3261 [(set (reg:SI 3)
3262 (udiv:SI (reg:SI 3) (reg:SI 4)))
3263 (clobber (reg:SI LR_REGNO))
3264 (clobber (reg:SI 0))
3265 (clobber (match_scratch:CC 0 "=x"))
3266 (clobber (reg:CC CR1_REGNO))]
3267 "! TARGET_POWER && ! TARGET_POWERPC"
3268 "bla __quous"
3269 [(set_attr "type" "idiv")])
3270 \f
3271 ;; Logical instructions
3272 ;; The logical instructions are mostly combined by using match_operator,
3273 ;; but the plain AND insns are somewhat different because there is no
3274 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3275 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3277 (define_expand "andsi3"
3278 [(parallel
3279 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3280 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3281 (match_operand:SI 2 "and_operand" "")))
3282 (clobber (match_scratch:CC 3 ""))])]
3283 ""
3284 "")
3286 (define_insn "andsi3_mc"
3287 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3288 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3289 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3290 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3291 "rs6000_gen_cell_microcode"
3292 "@
3293 and %0,%1,%2
3294 {rlinm|rlwinm} %0,%1,0,%m2,%M2
3295 {andil.|andi.} %0,%1,%b2
3296 {andiu.|andis.} %0,%1,%u2"
3297 [(set_attr "type" "*,*,fast_compare,fast_compare")])
3299 (define_insn "andsi3_nomc"
3300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3301 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3302 (match_operand:SI 2 "and_operand" "?r,T")))
3303 (clobber (match_scratch:CC 3 "=X,X"))]
3304 "!rs6000_gen_cell_microcode"
3305 "@
3306 and %0,%1,%2
3307 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3309 (define_insn "andsi3_internal0_nomc"
3310 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3311 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3312 (match_operand:SI 2 "and_operand" "?r,T")))]
3313 "!rs6000_gen_cell_microcode"
3314 "@
3315 and %0,%1,%2
3316 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3319 ;; Note to set cr's other than cr0 we do the and immediate and then
3320 ;; the test again -- this avoids a mfcr which on the higher end
3321 ;; machines causes an execution serialization
3323 (define_insn "*andsi3_internal2_mc"
3324 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3325 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3326 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3327 (const_int 0)))
3328 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3329 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3330 "TARGET_32BIT && rs6000_gen_cell_microcode"
3331 "@
3332 and. %3,%1,%2
3333 {andil.|andi.} %3,%1,%b2
3334 {andiu.|andis.} %3,%1,%u2
3335 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3336 #
3337 #
3338 #
3339 #"
3340 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3341 compare,compare,compare,compare")
3342 (set_attr "length" "4,4,4,4,8,8,8,8")])
3344 (define_insn "*andsi3_internal3_mc"
3345 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3346 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3347 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3348 (const_int 0)))
3349 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3350 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3351 "TARGET_64BIT && rs6000_gen_cell_microcode"
3352 "@
3353 #
3354 {andil.|andi.} %3,%1,%b2
3355 {andiu.|andis.} %3,%1,%u2
3356 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3357 #
3358 #
3359 #
3360 #"
3361 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3362 compare,compare,compare")
3363 (set_attr "length" "8,4,4,4,8,8,8,8")])
3365 (define_split
3366 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3367 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3368 (match_operand:GPR 2 "and_operand" ""))
3369 (const_int 0)))
3370 (clobber (match_scratch:GPR 3 ""))
3371 (clobber (match_scratch:CC 4 ""))]
3372 "reload_completed"
3373 [(parallel [(set (match_dup 3)
3374 (and:<MODE> (match_dup 1)
3375 (match_dup 2)))
3376 (clobber (match_dup 4))])
3377 (set (match_dup 0)
3378 (compare:CC (match_dup 3)
3379 (const_int 0)))]
3380 "")
3382 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3383 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3385 (define_split
3386 [(set (match_operand:CC 0 "cc_reg_operand" "")
3387 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3388 (match_operand:SI 2 "gpc_reg_operand" ""))
3389 (const_int 0)))
3390 (clobber (match_scratch:SI 3 ""))
3391 (clobber (match_scratch:CC 4 ""))]
3392 "TARGET_POWERPC64 && reload_completed"
3393 [(parallel [(set (match_dup 3)
3394 (and:SI (match_dup 1)
3395 (match_dup 2)))
3396 (clobber (match_dup 4))])
3397 (set (match_dup 0)
3398 (compare:CC (match_dup 3)
3399 (const_int 0)))]
3400 "")
3402 (define_insn "*andsi3_internal4"
3403 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3404 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3405 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3406 (const_int 0)))
3407 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3408 (and:SI (match_dup 1)
3409 (match_dup 2)))
3410 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3411 "TARGET_32BIT && rs6000_gen_cell_microcode"
3412 "@
3413 and. %0,%1,%2
3414 {andil.|andi.} %0,%1,%b2
3415 {andiu.|andis.} %0,%1,%u2
3416 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3417 #
3418 #
3419 #
3420 #"
3421 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3422 compare,compare,compare,compare")
3423 (set_attr "length" "4,4,4,4,8,8,8,8")])
3425 (define_insn "*andsi3_internal5_mc"
3426 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3427 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3428 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3429 (const_int 0)))
3430 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3431 (and:SI (match_dup 1)
3432 (match_dup 2)))
3433 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3434 "TARGET_64BIT && rs6000_gen_cell_microcode"
3435 "@
3436 #
3437 {andil.|andi.} %0,%1,%b2
3438 {andiu.|andis.} %0,%1,%u2
3439 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3440 #
3441 #
3442 #
3443 #"
3444 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3445 compare,compare,compare")
3446 (set_attr "length" "8,4,4,4,8,8,8,8")])
3448 (define_split
3449 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3450 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3451 (match_operand:SI 2 "and_operand" ""))
3452 (const_int 0)))
3453 (set (match_operand:SI 0 "gpc_reg_operand" "")
3454 (and:SI (match_dup 1)
3455 (match_dup 2)))
3456 (clobber (match_scratch:CC 4 ""))]
3457 "reload_completed"
3458 [(parallel [(set (match_dup 0)
3459 (and:SI (match_dup 1)
3460 (match_dup 2)))
3461 (clobber (match_dup 4))])
3462 (set (match_dup 3)
3463 (compare:CC (match_dup 0)
3464 (const_int 0)))]
3465 "")
3467 (define_split
3468 [(set (match_operand:CC 3 "cc_reg_operand" "")
3469 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3470 (match_operand:SI 2 "gpc_reg_operand" ""))
3471 (const_int 0)))
3472 (set (match_operand:SI 0 "gpc_reg_operand" "")
3473 (and:SI (match_dup 1)
3474 (match_dup 2)))
3475 (clobber (match_scratch:CC 4 ""))]
3476 "TARGET_POWERPC64 && reload_completed"
3477 [(parallel [(set (match_dup 0)
3478 (and:SI (match_dup 1)
3479 (match_dup 2)))
3480 (clobber (match_dup 4))])
3481 (set (match_dup 3)
3482 (compare:CC (match_dup 0)
3483 (const_int 0)))]
3484 "")
3486 ;; Handle the PowerPC64 rlwinm corner case
3488 (define_insn_and_split "*andsi3_internal6"
3489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3490 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3491 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3492 "TARGET_POWERPC64"
3493 "#"
3494 "TARGET_POWERPC64"
3495 [(set (match_dup 0)
3496 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3497 (match_dup 4)))
3498 (set (match_dup 0)
3499 (rotate:SI (match_dup 0) (match_dup 5)))]
3500 "
3501 {
3502 int mb = extract_MB (operands[2]);
3503 int me = extract_ME (operands[2]);
3504 operands[3] = GEN_INT (me + 1);
3505 operands[5] = GEN_INT (32 - (me + 1));
3506 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3507 }"
3508 [(set_attr "length" "8")])
3510 (define_expand "iorsi3"
3511 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3512 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3513 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3514 ""
3515 "
3516 {
3517 if (GET_CODE (operands[2]) == CONST_INT
3518 && ! logical_operand (operands[2], SImode))
3519 {
3520 HOST_WIDE_INT value = INTVAL (operands[2]);
3521 rtx tmp = ((!can_create_pseudo_p ()
3522 || rtx_equal_p (operands[0], operands[1]))
3523 ? operands[0] : gen_reg_rtx (SImode));
3525 emit_insn (gen_iorsi3 (tmp, operands[1],
3526 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3527 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3528 DONE;
3529 }
3530 }")
3532 (define_expand "xorsi3"
3533 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3534 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3535 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3536 ""
3537 "
3538 {
3539 if (GET_CODE (operands[2]) == CONST_INT
3540 && ! logical_operand (operands[2], SImode))
3541 {
3542 HOST_WIDE_INT value = INTVAL (operands[2]);
3543 rtx tmp = ((!can_create_pseudo_p ()
3544 || rtx_equal_p (operands[0], operands[1]))
3545 ? operands[0] : gen_reg_rtx (SImode));
3547 emit_insn (gen_xorsi3 (tmp, operands[1],
3548 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3549 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3550 DONE;
3551 }
3552 }")
3554 (define_insn "*boolsi3_internal1"
3555 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3556 (match_operator:SI 3 "boolean_or_operator"
3557 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3558 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3559 ""
3560 "@
3561 %q3 %0,%1,%2
3562 {%q3il|%q3i} %0,%1,%b2
3563 {%q3iu|%q3is} %0,%1,%u2")
3565 (define_insn "*boolsi3_internal2"
3566 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3567 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3568 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3569 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3570 (const_int 0)))
3571 (clobber (match_scratch:SI 3 "=r,r"))]
3572 "TARGET_32BIT"
3573 "@
3574 %q4. %3,%1,%2
3575 #"
3576 [(set_attr "type" "fast_compare,compare")
3577 (set_attr "length" "4,8")])
3579 (define_split
3580 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3581 (compare:CC (match_operator:SI 4 "boolean_operator"
3582 [(match_operand:SI 1 "gpc_reg_operand" "")
3583 (match_operand:SI 2 "gpc_reg_operand" "")])
3584 (const_int 0)))
3585 (clobber (match_scratch:SI 3 ""))]
3586 "TARGET_32BIT && reload_completed"
3587 [(set (match_dup 3) (match_dup 4))
3588 (set (match_dup 0)
3589 (compare:CC (match_dup 3)
3590 (const_int 0)))]
3591 "")
3593 (define_insn "*boolsi3_internal3"
3594 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3595 (compare:CC (match_operator:SI 4 "boolean_operator"
3596 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3597 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3598 (const_int 0)))
3599 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3600 (match_dup 4))]
3601 "TARGET_32BIT"
3602 "@
3603 %q4. %0,%1,%2
3604 #"
3605 [(set_attr "type" "fast_compare,compare")
3606 (set_attr "length" "4,8")])
3608 (define_split
3609 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3610 (compare:CC (match_operator:SI 4 "boolean_operator"
3611 [(match_operand:SI 1 "gpc_reg_operand" "")
3612 (match_operand:SI 2 "gpc_reg_operand" "")])
3613 (const_int 0)))
3614 (set (match_operand:SI 0 "gpc_reg_operand" "")
3615 (match_dup 4))]
3616 "TARGET_32BIT && reload_completed"
3617 [(set (match_dup 0) (match_dup 4))
3618 (set (match_dup 3)
3619 (compare:CC (match_dup 0)
3620 (const_int 0)))]
3621 "")
3623 ;; Split a logical operation that we can't do in one insn into two insns,
3624 ;; each of which does one 16-bit part. This is used by combine.
3626 (define_split
3627 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3628 (match_operator:SI 3 "boolean_or_operator"
3629 [(match_operand:SI 1 "gpc_reg_operand" "")
3630 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3631 ""
3632 [(set (match_dup 0) (match_dup 4))
3633 (set (match_dup 0) (match_dup 5))]
3634 "
3635 {
3636 rtx i;
3637 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3638 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3639 operands[1], i);
3640 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3641 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3642 operands[0], i);
3643 }")
3645 (define_insn "*boolcsi3_internal1"
3646 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3647 (match_operator:SI 3 "boolean_operator"
3648 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3649 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3650 ""
3651 "%q3 %0,%2,%1")
3653 (define_insn "*boolcsi3_internal2"
3654 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3655 (compare:CC (match_operator:SI 4 "boolean_operator"
3656 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3657 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3658 (const_int 0)))
3659 (clobber (match_scratch:SI 3 "=r,r"))]
3660 "TARGET_32BIT"
3661 "@
3662 %q4. %3,%2,%1
3663 #"
3664 [(set_attr "type" "compare")
3665 (set_attr "length" "4,8")])
3667 (define_split
3668 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3669 (compare:CC (match_operator:SI 4 "boolean_operator"
3670 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3671 (match_operand:SI 2 "gpc_reg_operand" "")])
3672 (const_int 0)))
3673 (clobber (match_scratch:SI 3 ""))]
3674 "TARGET_32BIT && reload_completed"
3675 [(set (match_dup 3) (match_dup 4))
3676 (set (match_dup 0)
3677 (compare:CC (match_dup 3)
3678 (const_int 0)))]
3679 "")
3681 (define_insn "*boolcsi3_internal3"
3682 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3683 (compare:CC (match_operator:SI 4 "boolean_operator"
3684 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3685 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3686 (const_int 0)))
3687 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3688 (match_dup 4))]
3689 "TARGET_32BIT"
3690 "@
3691 %q4. %0,%2,%1
3692 #"
3693 [(set_attr "type" "compare")
3694 (set_attr "length" "4,8")])
3696 (define_split
3697 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3698 (compare:CC (match_operator:SI 4 "boolean_operator"
3699 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3700 (match_operand:SI 2 "gpc_reg_operand" "")])
3701 (const_int 0)))
3702 (set (match_operand:SI 0 "gpc_reg_operand" "")
3703 (match_dup 4))]
3704 "TARGET_32BIT && reload_completed"
3705 [(set (match_dup 0) (match_dup 4))
3706 (set (match_dup 3)
3707 (compare:CC (match_dup 0)
3708 (const_int 0)))]
3709 "")
3711 (define_insn "*boolccsi3_internal1"
3712 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3713 (match_operator:SI 3 "boolean_operator"
3714 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3715 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3716 ""
3717 "%q3 %0,%1,%2")
3719 (define_insn "*boolccsi3_internal2"
3720 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3721 (compare:CC (match_operator:SI 4 "boolean_operator"
3722 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3723 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3724 (const_int 0)))
3725 (clobber (match_scratch:SI 3 "=r,r"))]
3726 "TARGET_32BIT"
3727 "@
3728 %q4. %3,%1,%2
3729 #"
3730 [(set_attr "type" "fast_compare,compare")
3731 (set_attr "length" "4,8")])
3733 (define_split
3734 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3735 (compare:CC (match_operator:SI 4 "boolean_operator"
3736 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3737 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3738 (const_int 0)))
3739 (clobber (match_scratch:SI 3 ""))]
3740 "TARGET_32BIT && reload_completed"
3741 [(set (match_dup 3) (match_dup 4))
3742 (set (match_dup 0)
3743 (compare:CC (match_dup 3)
3744 (const_int 0)))]
3745 "")
3747 (define_insn "*boolccsi3_internal3"
3748 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3749 (compare:CC (match_operator:SI 4 "boolean_operator"
3750 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3751 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3752 (const_int 0)))
3753 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3754 (match_dup 4))]
3755 "TARGET_32BIT"
3756 "@
3757 %q4. %0,%1,%2
3758 #"
3759 [(set_attr "type" "fast_compare,compare")
3760 (set_attr "length" "4,8")])
3762 (define_split
3763 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3764 (compare:CC (match_operator:SI 4 "boolean_operator"
3765 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3766 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3767 (const_int 0)))
3768 (set (match_operand:SI 0 "gpc_reg_operand" "")
3769 (match_dup 4))]
3770 "TARGET_32BIT && reload_completed"
3771 [(set (match_dup 0) (match_dup 4))
3772 (set (match_dup 3)
3773 (compare:CC (match_dup 0)
3774 (const_int 0)))]
3775 "")
3777 ;; maskir insn. We need four forms because things might be in arbitrary
3778 ;; orders. Don't define forms that only set CR fields because these
3779 ;; would modify an input register.
3781 (define_insn "*maskir_internal1"
3782 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3783 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3784 (match_operand:SI 1 "gpc_reg_operand" "0"))
3785 (and:SI (match_dup 2)
3786 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3787 "TARGET_POWER"
3788 "maskir %0,%3,%2")
3790 (define_insn "*maskir_internal2"
3791 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3792 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3793 (match_operand:SI 1 "gpc_reg_operand" "0"))
3794 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3795 (match_dup 2))))]
3796 "TARGET_POWER"
3797 "maskir %0,%3,%2")
3799 (define_insn "*maskir_internal3"
3800 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3801 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3802 (match_operand:SI 3 "gpc_reg_operand" "r"))
3803 (and:SI (not:SI (match_dup 2))
3804 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3805 "TARGET_POWER"
3806 "maskir %0,%3,%2")
3808 (define_insn "*maskir_internal4"
3809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3810 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3811 (match_operand:SI 2 "gpc_reg_operand" "r"))
3812 (and:SI (not:SI (match_dup 2))
3813 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3814 "TARGET_POWER"
3815 "maskir %0,%3,%2")
3817 (define_insn "*maskir_internal5"
3818 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3819 (compare:CC
3820 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3821 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3822 (and:SI (match_dup 2)
3823 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3824 (const_int 0)))
3825 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3826 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3827 (and:SI (match_dup 2) (match_dup 3))))]
3828 "TARGET_POWER"
3829 "@
3830 maskir. %0,%3,%2
3831 #"
3832 [(set_attr "type" "compare")
3833 (set_attr "length" "4,8")])
3835 (define_split
3836 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3837 (compare:CC
3838 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3839 (match_operand:SI 1 "gpc_reg_operand" ""))
3840 (and:SI (match_dup 2)
3841 (match_operand:SI 3 "gpc_reg_operand" "")))
3842 (const_int 0)))
3843 (set (match_operand:SI 0 "gpc_reg_operand" "")
3844 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3845 (and:SI (match_dup 2) (match_dup 3))))]
3846 "TARGET_POWER && reload_completed"
3847 [(set (match_dup 0)
3848 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3849 (and:SI (match_dup 2) (match_dup 3))))
3850 (set (match_dup 4)
3851 (compare:CC (match_dup 0)
3852 (const_int 0)))]
3853 "")
3855 (define_insn "*maskir_internal6"
3856 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3857 (compare:CC
3858 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3859 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3860 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3861 (match_dup 2)))
3862 (const_int 0)))
3863 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3864 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3865 (and:SI (match_dup 3) (match_dup 2))))]
3866 "TARGET_POWER"
3867 "@
3868 maskir. %0,%3,%2
3869 #"
3870 [(set_attr "type" "compare")
3871 (set_attr "length" "4,8")])
3873 (define_split
3874 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3875 (compare:CC
3876 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3877 (match_operand:SI 1 "gpc_reg_operand" ""))
3878 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3879 (match_dup 2)))
3880 (const_int 0)))
3881 (set (match_operand:SI 0 "gpc_reg_operand" "")
3882 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3883 (and:SI (match_dup 3) (match_dup 2))))]
3884 "TARGET_POWER && reload_completed"
3885 [(set (match_dup 0)
3886 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3887 (and:SI (match_dup 3) (match_dup 2))))
3888 (set (match_dup 4)
3889 (compare:CC (match_dup 0)
3890 (const_int 0)))]
3891 "")
3893 (define_insn "*maskir_internal7"
3894 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3895 (compare:CC
3896 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3897 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3898 (and:SI (not:SI (match_dup 2))
3899 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3900 (const_int 0)))
3901 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3902 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3903 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3904 "TARGET_POWER"
3905 "@
3906 maskir. %0,%3,%2
3907 #"
3908 [(set_attr "type" "compare")
3909 (set_attr "length" "4,8")])
3911 (define_split
3912 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3913 (compare:CC
3914 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3915 (match_operand:SI 3 "gpc_reg_operand" ""))
3916 (and:SI (not:SI (match_dup 2))
3917 (match_operand:SI 1 "gpc_reg_operand" "")))
3918 (const_int 0)))
3919 (set (match_operand:SI 0 "gpc_reg_operand" "")
3920 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3921 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3922 "TARGET_POWER && reload_completed"
3923 [(set (match_dup 0)
3924 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3925 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3926 (set (match_dup 4)
3927 (compare:CC (match_dup 0)
3928 (const_int 0)))]
3929 "")
3931 (define_insn "*maskir_internal8"
3932 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3933 (compare:CC
3934 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3935 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3936 (and:SI (not:SI (match_dup 2))
3937 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3938 (const_int 0)))
3939 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3940 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3941 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3942 "TARGET_POWER"
3943 "@
3944 maskir. %0,%3,%2
3945 #"
3946 [(set_attr "type" "compare")
3947 (set_attr "length" "4,8")])
3949 (define_split
3950 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3951 (compare:CC
3952 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3953 (match_operand:SI 2 "gpc_reg_operand" ""))
3954 (and:SI (not:SI (match_dup 2))
3955 (match_operand:SI 1 "gpc_reg_operand" "")))
3956 (const_int 0)))
3957 (set (match_operand:SI 0 "gpc_reg_operand" "")
3958 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3959 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3960 "TARGET_POWER && reload_completed"
3961 [(set (match_dup 0)
3962 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3963 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3964 (set (match_dup 4)
3965 (compare:CC (match_dup 0)
3966 (const_int 0)))]
3967 "")
3968 \f
3969 ;; Rotate and shift insns, in all their variants. These support shifts,
3970 ;; field inserts and extracts, and various combinations thereof.
3971 (define_expand "insv"
3972 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3973 (match_operand:SI 1 "const_int_operand" "")
3974 (match_operand:SI 2 "const_int_operand" ""))
3975 (match_operand 3 "gpc_reg_operand" ""))]
3976 ""
3977 "
3978 {
3979 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3980 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3981 compiler if the address of the structure is taken later. Likewise, do
3982 not handle invalid E500 subregs. */
3983 if (GET_CODE (operands[0]) == SUBREG
3984 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3985 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3986 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3987 FAIL;
3989 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3990 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3991 else
3992 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3993 DONE;
3994 }")
3996 (define_insn "insvsi"
3997 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3998 (match_operand:SI 1 "const_int_operand" "i")
3999 (match_operand:SI 2 "const_int_operand" "i"))
4000 (match_operand:SI 3 "gpc_reg_operand" "r"))]
4001 ""
4002 "*
4003 {
4004 int start = INTVAL (operands[2]) & 31;
4005 int size = INTVAL (operands[1]) & 31;
4007 operands[4] = GEN_INT (32 - start - size);
4008 operands[1] = GEN_INT (start + size - 1);
4009 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4010 }"
4011 [(set_attr "type" "insert_word")])
4013 (define_insn "*insvsi_internal1"
4014 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4015 (match_operand:SI 1 "const_int_operand" "i")
4016 (match_operand:SI 2 "const_int_operand" "i"))
4017 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4018 (match_operand:SI 4 "const_int_operand" "i")))]
4019 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4020 "*
4021 {
4022 int shift = INTVAL (operands[4]) & 31;
4023 int start = INTVAL (operands[2]) & 31;
4024 int size = INTVAL (operands[1]) & 31;
4026 operands[4] = GEN_INT (shift - start - size);
4027 operands[1] = GEN_INT (start + size - 1);
4028 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4029 }"
4030 [(set_attr "type" "insert_word")])
4032 (define_insn "*insvsi_internal2"
4033 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4034 (match_operand:SI 1 "const_int_operand" "i")
4035 (match_operand:SI 2 "const_int_operand" "i"))
4036 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4037 (match_operand:SI 4 "const_int_operand" "i")))]
4038 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4039 "*
4040 {
4041 int shift = INTVAL (operands[4]) & 31;
4042 int start = INTVAL (operands[2]) & 31;
4043 int size = INTVAL (operands[1]) & 31;
4045 operands[4] = GEN_INT (32 - shift - start - size);
4046 operands[1] = GEN_INT (start + size - 1);
4047 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4048 }"
4049 [(set_attr "type" "insert_word")])
4051 (define_insn "*insvsi_internal3"
4052 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4053 (match_operand:SI 1 "const_int_operand" "i")
4054 (match_operand:SI 2 "const_int_operand" "i"))
4055 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4056 (match_operand:SI 4 "const_int_operand" "i")))]
4057 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4058 "*
4059 {
4060 int shift = INTVAL (operands[4]) & 31;
4061 int start = INTVAL (operands[2]) & 31;
4062 int size = INTVAL (operands[1]) & 31;
4064 operands[4] = GEN_INT (32 - shift - start - size);
4065 operands[1] = GEN_INT (start + size - 1);
4066 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4067 }"
4068 [(set_attr "type" "insert_word")])
4070 (define_insn "*insvsi_internal4"
4071 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4072 (match_operand:SI 1 "const_int_operand" "i")
4073 (match_operand:SI 2 "const_int_operand" "i"))
4074 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4075 (match_operand:SI 4 "const_int_operand" "i")
4076 (match_operand:SI 5 "const_int_operand" "i")))]
4077 "INTVAL (operands[4]) >= INTVAL (operands[1])"
4078 "*
4079 {
4080 int extract_start = INTVAL (operands[5]) & 31;
4081 int extract_size = INTVAL (operands[4]) & 31;
4082 int insert_start = INTVAL (operands[2]) & 31;
4083 int insert_size = INTVAL (operands[1]) & 31;
4085 /* Align extract field with insert field */
4086 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
4087 operands[1] = GEN_INT (insert_start + insert_size - 1);
4088 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
4089 }"
4090 [(set_attr "type" "insert_word")])
4092 ;; combine patterns for rlwimi
4093 (define_insn "*insvsi_internal5"
4094 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4095 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4096 (match_operand:SI 1 "mask_operand" "i"))
4097 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4098 (match_operand:SI 2 "const_int_operand" "i"))
4099 (match_operand:SI 5 "mask_operand" "i"))))]
4100 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4101 "*
4102 {
4103 int me = extract_ME(operands[5]);
4104 int mb = extract_MB(operands[5]);
4105 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4106 operands[2] = GEN_INT(mb);
4107 operands[1] = GEN_INT(me);
4108 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4109 }"
4110 [(set_attr "type" "insert_word")])
4112 (define_insn "*insvsi_internal6"
4113 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4114 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4115 (match_operand:SI 2 "const_int_operand" "i"))
4116 (match_operand:SI 5 "mask_operand" "i"))
4117 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4118 (match_operand:SI 1 "mask_operand" "i"))))]
4119 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4120 "*
4121 {
4122 int me = extract_ME(operands[5]);
4123 int mb = extract_MB(operands[5]);
4124 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4125 operands[2] = GEN_INT(mb);
4126 operands[1] = GEN_INT(me);
4127 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4128 }"
4129 [(set_attr "type" "insert_word")])
4131 (define_insn "insvdi"
4132 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4133 (match_operand:SI 1 "const_int_operand" "i")
4134 (match_operand:SI 2 "const_int_operand" "i"))
4135 (match_operand:DI 3 "gpc_reg_operand" "r"))]
4136 "TARGET_POWERPC64"
4137 "*
4138 {
4139 int start = INTVAL (operands[2]) & 63;
4140 int size = INTVAL (operands[1]) & 63;
4142 operands[1] = GEN_INT (64 - start - size);
4143 return \"rldimi %0,%3,%H1,%H2\";
4144 }"
4145 [(set_attr "type" "insert_dword")])
4147 (define_insn "*insvdi_internal2"
4148 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4149 (match_operand:SI 1 "const_int_operand" "i")
4150 (match_operand:SI 2 "const_int_operand" "i"))
4151 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4152 (match_operand:SI 4 "const_int_operand" "i")))]
4153 "TARGET_POWERPC64
4154 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4155 "*
4156 {
4157 int shift = INTVAL (operands[4]) & 63;
4158 int start = (INTVAL (operands[2]) & 63) - 32;
4159 int size = INTVAL (operands[1]) & 63;
4161 operands[4] = GEN_INT (64 - shift - start - size);
4162 operands[2] = GEN_INT (start);
4163 operands[1] = GEN_INT (start + size - 1);
4164 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4165 }")
4167 (define_insn "*insvdi_internal3"
4168 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4169 (match_operand:SI 1 "const_int_operand" "i")
4170 (match_operand:SI 2 "const_int_operand" "i"))
4171 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4172 (match_operand:SI 4 "const_int_operand" "i")))]
4173 "TARGET_POWERPC64
4174 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4175 "*
4176 {
4177 int shift = INTVAL (operands[4]) & 63;
4178 int start = (INTVAL (operands[2]) & 63) - 32;
4179 int size = INTVAL (operands[1]) & 63;
4181 operands[4] = GEN_INT (64 - shift - start - size);
4182 operands[2] = GEN_INT (start);
4183 operands[1] = GEN_INT (start + size - 1);
4184 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4185 }")
4187 (define_expand "extzv"
4188 [(set (match_operand 0 "gpc_reg_operand" "")
4189 (zero_extract (match_operand 1 "gpc_reg_operand" "")
4190 (match_operand:SI 2 "const_int_operand" "")
4191 (match_operand:SI 3 "const_int_operand" "")))]
4192 ""
4193 "
4194 {
4195 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4196 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4197 compiler if the address of the structure is taken later. */
4198 if (GET_CODE (operands[0]) == SUBREG
4199 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
4200 FAIL;
4202 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
4203 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
4204 else
4205 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
4206 DONE;
4207 }")
4209 (define_insn "extzvsi"
4210 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4211 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4212 (match_operand:SI 2 "const_int_operand" "i")
4213 (match_operand:SI 3 "const_int_operand" "i")))]
4214 ""
4215 "*
4216 {
4217 int start = INTVAL (operands[3]) & 31;
4218 int size = INTVAL (operands[2]) & 31;
4220 if (start + size >= 32)
4221 operands[3] = const0_rtx;
4222 else
4223 operands[3] = GEN_INT (start + size);
4224 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
4225 }")
4227 (define_insn "*extzvsi_internal1"
4228 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4229 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4230 (match_operand:SI 2 "const_int_operand" "i,i")
4231 (match_operand:SI 3 "const_int_operand" "i,i"))
4232 (const_int 0)))
4233 (clobber (match_scratch:SI 4 "=r,r"))]
4234 ""
4235 "*
4236 {
4237 int start = INTVAL (operands[3]) & 31;
4238 int size = INTVAL (operands[2]) & 31;
4240 /* Force split for non-cc0 compare. */
4241 if (which_alternative == 1)
4242 return \"#\";
4244 /* If the bit-field being tested fits in the upper or lower half of a
4245 word, it is possible to use andiu. or andil. to test it. This is
4246 useful because the condition register set-use delay is smaller for
4247 andi[ul]. than for rlinm. This doesn't work when the starting bit
4248 position is 0 because the LT and GT bits may be set wrong. */
4250 if ((start > 0 && start + size <= 16) || start >= 16)
4251 {
4252 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
4253 - (1 << (16 - (start & 15) - size))));
4254 if (start < 16)
4255 return \"{andiu.|andis.} %4,%1,%3\";
4256 else
4257 return \"{andil.|andi.} %4,%1,%3\";
4258 }
4260 if (start + size >= 32)
4261 operands[3] = const0_rtx;
4262 else
4263 operands[3] = GEN_INT (start + size);
4264 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
4265 }"
4266 [(set_attr "type" "delayed_compare")
4267 (set_attr "length" "4,8")])
4269 (define_split
4270 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4271 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4272 (match_operand:SI 2 "const_int_operand" "")
4273 (match_operand:SI 3 "const_int_operand" ""))
4274 (const_int 0)))
4275 (clobber (match_scratch:SI 4 ""))]
4276 "reload_completed"
4277 [(set (match_dup 4)
4278 (zero_extract:SI (match_dup 1) (match_dup 2)
4279 (match_dup 3)))
4280 (set (match_dup 0)
4281 (compare:CC (match_dup 4)
4282 (const_int 0)))]
4283 "")
4285 (define_insn "*extzvsi_internal2"
4286 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4287 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4288 (match_operand:SI 2 "const_int_operand" "i,i")
4289 (match_operand:SI 3 "const_int_operand" "i,i"))
4290 (const_int 0)))
4291 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4292 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4293 ""
4294 "*
4295 {
4296 int start = INTVAL (operands[3]) & 31;
4297 int size = INTVAL (operands[2]) & 31;
4299 /* Force split for non-cc0 compare. */
4300 if (which_alternative == 1)
4301 return \"#\";
4303 /* Since we are using the output value, we can't ignore any need for
4304 a shift. The bit-field must end at the LSB. */
4305 if (start >= 16 && start + size == 32)
4306 {
4307 operands[3] = GEN_INT ((1 << size) - 1);
4308 return \"{andil.|andi.} %0,%1,%3\";
4309 }
4311 if (start + size >= 32)
4312 operands[3] = const0_rtx;
4313 else
4314 operands[3] = GEN_INT (start + size);
4315 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
4316 }"
4317 [(set_attr "type" "delayed_compare")
4318 (set_attr "length" "4,8")])
4320 (define_split
4321 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4322 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4323 (match_operand:SI 2 "const_int_operand" "")
4324 (match_operand:SI 3 "const_int_operand" ""))
4325 (const_int 0)))
4326 (set (match_operand:SI 0 "gpc_reg_operand" "")
4327 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4328 "reload_completed"
4329 [(set (match_dup 0)
4330 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
4331 (set (match_dup 4)
4332 (compare:CC (match_dup 0)
4333 (const_int 0)))]
4334 "")
4336 (define_insn "extzvdi"
4337 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4338 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4339 (match_operand:SI 2 "const_int_operand" "i")
4340 (match_operand:SI 3 "const_int_operand" "i")))]
4341 "TARGET_POWERPC64"
4342 "*
4343 {
4344 int start = INTVAL (operands[3]) & 63;
4345 int size = INTVAL (operands[2]) & 63;
4347 if (start + size >= 64)
4348 operands[3] = const0_rtx;
4349 else
4350 operands[3] = GEN_INT (start + size);
4351 operands[2] = GEN_INT (64 - size);
4352 return \"rldicl %0,%1,%3,%2\";
4353 }")
4355 (define_insn "*extzvdi_internal1"
4356 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
4357 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4358 (match_operand:SI 2 "const_int_operand" "i")
4359 (match_operand:SI 3 "const_int_operand" "i"))
4360 (const_int 0)))
4361 (clobber (match_scratch:DI 4 "=r"))]
4362 "TARGET_64BIT && rs6000_gen_cell_microcode"
4363 "*
4364 {
4365 int start = INTVAL (operands[3]) & 63;
4366 int size = INTVAL (operands[2]) & 63;
4368 if (start + size >= 64)
4369 operands[3] = const0_rtx;
4370 else
4371 operands[3] = GEN_INT (start + size);
4372 operands[2] = GEN_INT (64 - size);
4373 return \"rldicl. %4,%1,%3,%2\";
4374 }"
4375 [(set_attr "type" "compare")])
4377 (define_insn "*extzvdi_internal2"
4378 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
4379 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4380 (match_operand:SI 2 "const_int_operand" "i")
4381 (match_operand:SI 3 "const_int_operand" "i"))
4382 (const_int 0)))
4383 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4384 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
4385 "TARGET_64BIT && rs6000_gen_cell_microcode"
4386 "*
4387 {
4388 int start = INTVAL (operands[3]) & 63;
4389 int size = INTVAL (operands[2]) & 63;
4391 if (start + size >= 64)
4392 operands[3] = const0_rtx;
4393 else
4394 operands[3] = GEN_INT (start + size);
4395 operands[2] = GEN_INT (64 - size);
4396 return \"rldicl. %0,%1,%3,%2\";
4397 }"
4398 [(set_attr "type" "compare")])
4400 (define_insn "rotlsi3"
4401 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4402 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4403 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4404 ""
4405 "@
4406 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4407 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4408 [(set_attr "type" "var_shift_rotate,integer")])
4410 (define_insn "*rotlsi3_64"
4411 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4412 (zero_extend:DI
4413 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4414 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4415 "TARGET_64BIT"
4416 "@
4417 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4418 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4419 [(set_attr "type" "var_shift_rotate,integer")])
4421 (define_insn "*rotlsi3_internal2"
4422 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4423 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4424 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4425 (const_int 0)))
4426 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4427 ""
4428 "@
4429 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4430 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4431 #
4432 #"
4433 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4434 (set_attr "length" "4,4,8,8")])
4436 (define_split
4437 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4438 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4439 (match_operand:SI 2 "reg_or_cint_operand" ""))
4440 (const_int 0)))
4441 (clobber (match_scratch:SI 3 ""))]
4442 "reload_completed"
4443 [(set (match_dup 3)
4444 (rotate:SI (match_dup 1) (match_dup 2)))
4445 (set (match_dup 0)
4446 (compare:CC (match_dup 3)
4447 (const_int 0)))]
4448 "")
4450 (define_insn "*rotlsi3_internal3"
4451 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4452 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4453 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4454 (const_int 0)))
4455 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4456 (rotate:SI (match_dup 1) (match_dup 2)))]
4457 ""
4458 "@
4459 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4460 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4461 #
4462 #"
4463 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4464 (set_attr "length" "4,4,8,8")])
4466 (define_split
4467 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4468 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4469 (match_operand:SI 2 "reg_or_cint_operand" ""))
4470 (const_int 0)))
4471 (set (match_operand:SI 0 "gpc_reg_operand" "")
4472 (rotate:SI (match_dup 1) (match_dup 2)))]
4473 "reload_completed"
4474 [(set (match_dup 0)
4475 (rotate:SI (match_dup 1) (match_dup 2)))
4476 (set (match_dup 3)
4477 (compare:CC (match_dup 0)
4478 (const_int 0)))]
4479 "")
4481 (define_insn "*rotlsi3_internal4"
4482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4483 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4484 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4485 (match_operand:SI 3 "mask_operand" "n,n")))]
4486 ""
4487 "@
4488 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4489 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4490 [(set_attr "type" "var_shift_rotate,integer")])
4492 (define_insn "*rotlsi3_internal5"
4493 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4494 (compare:CC (and:SI
4495 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4496 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4497 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4498 (const_int 0)))
4499 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4500 ""
4501 "@
4502 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4503 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4504 #
4505 #"
4506 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4507 (set_attr "length" "4,4,8,8")])
4509 (define_split
4510 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4511 (compare:CC (and:SI
4512 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4513 (match_operand:SI 2 "reg_or_cint_operand" ""))
4514 (match_operand:SI 3 "mask_operand" ""))
4515 (const_int 0)))
4516 (clobber (match_scratch:SI 4 ""))]
4517 "reload_completed"
4518 [(set (match_dup 4)
4519 (and:SI (rotate:SI (match_dup 1)
4520 (match_dup 2))
4521 (match_dup 3)))
4522 (set (match_dup 0)
4523 (compare:CC (match_dup 4)
4524 (const_int 0)))]
4525 "")
4527 (define_insn "*rotlsi3_internal6"
4528 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4529 (compare:CC (and:SI
4530 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4531 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4532 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4533 (const_int 0)))
4534 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4535 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4536 ""
4537 "@
4538 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4539 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4540 #
4541 #"
4542 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4543 (set_attr "length" "4,4,8,8")])
4545 (define_split
4546 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4547 (compare:CC (and:SI
4548 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4549 (match_operand:SI 2 "reg_or_cint_operand" ""))
4550 (match_operand:SI 3 "mask_operand" ""))
4551 (const_int 0)))
4552 (set (match_operand:SI 0 "gpc_reg_operand" "")
4553 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4554 "reload_completed"
4555 [(set (match_dup 0)
4556 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4557 (set (match_dup 4)
4558 (compare:CC (match_dup 0)
4559 (const_int 0)))]
4560 "")
4562 (define_insn "*rotlsi3_internal7"
4563 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4564 (zero_extend:SI
4565 (subreg:QI
4566 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4567 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4568 ""
4569 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4570 [(set (attr "cell_micro")
4571 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4572 (const_string "not")
4573 (const_string "always")))])
4575 (define_insn "*rotlsi3_internal8"
4576 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4577 (compare:CC (zero_extend:SI
4578 (subreg:QI
4579 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4580 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4581 (const_int 0)))
4582 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4583 ""
4584 "@
4585 {rlnm.|rlwnm.} %3,%1,%2,0xff
4586 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4587 #
4588 #"
4589 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4590 (set_attr "length" "4,4,8,8")])
4592 (define_split
4593 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4594 (compare:CC (zero_extend:SI
4595 (subreg:QI
4596 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4597 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4598 (const_int 0)))
4599 (clobber (match_scratch:SI 3 ""))]
4600 "reload_completed"
4601 [(set (match_dup 3)
4602 (zero_extend:SI (subreg:QI
4603 (rotate:SI (match_dup 1)
4604 (match_dup 2)) 0)))
4605 (set (match_dup 0)
4606 (compare:CC (match_dup 3)
4607 (const_int 0)))]
4608 "")
4610 (define_insn "*rotlsi3_internal9"
4611 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4612 (compare:CC (zero_extend:SI
4613 (subreg:QI
4614 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4615 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4616 (const_int 0)))
4617 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4618 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4619 ""
4620 "@
4621 {rlnm.|rlwnm.} %0,%1,%2,0xff
4622 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4623 #
4624 #"
4625 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4626 (set_attr "length" "4,4,8,8")])
4628 (define_split
4629 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4630 (compare:CC (zero_extend:SI
4631 (subreg:QI
4632 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4633 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4634 (const_int 0)))
4635 (set (match_operand:SI 0 "gpc_reg_operand" "")
4636 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4637 "reload_completed"
4638 [(set (match_dup 0)
4639 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4640 (set (match_dup 3)
4641 (compare:CC (match_dup 0)
4642 (const_int 0)))]
4643 "")
4645 (define_insn "*rotlsi3_internal10"
4646 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4647 (zero_extend:SI
4648 (subreg:HI
4649 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4650 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4651 ""
4652 "@
4653 {rlnm|rlwnm} %0,%1,%2,0xffff
4654 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4655 [(set_attr "type" "var_shift_rotate,integer")])
4658 (define_insn "*rotlsi3_internal11"
4659 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4660 (compare:CC (zero_extend:SI
4661 (subreg:HI
4662 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4663 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4664 (const_int 0)))
4665 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4666 ""
4667 "@
4668 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4669 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4670 #
4671 #"
4672 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4673 (set_attr "length" "4,4,8,8")])
4675 (define_split
4676 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4677 (compare:CC (zero_extend:SI
4678 (subreg:HI
4679 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4680 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4681 (const_int 0)))
4682 (clobber (match_scratch:SI 3 ""))]
4683 "reload_completed"
4684 [(set (match_dup 3)
4685 (zero_extend:SI (subreg:HI
4686 (rotate:SI (match_dup 1)
4687 (match_dup 2)) 0)))
4688 (set (match_dup 0)
4689 (compare:CC (match_dup 3)
4690 (const_int 0)))]
4691 "")
4693 (define_insn "*rotlsi3_internal12"
4694 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4695 (compare:CC (zero_extend:SI
4696 (subreg:HI
4697 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4698 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4699 (const_int 0)))
4700 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4701 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4702 ""
4703 "@
4704 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4705 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4706 #
4707 #"
4708 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4709 (set_attr "length" "4,4,8,8")])
4711 (define_split
4712 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4713 (compare:CC (zero_extend:SI
4714 (subreg:HI
4715 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4716 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4717 (const_int 0)))
4718 (set (match_operand:SI 0 "gpc_reg_operand" "")
4719 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4720 "reload_completed"
4721 [(set (match_dup 0)
4722 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4723 (set (match_dup 3)
4724 (compare:CC (match_dup 0)
4725 (const_int 0)))]
4726 "")
4728 ;; Note that we use "sle." instead of "sl." so that we can set
4729 ;; SHIFT_COUNT_TRUNCATED.
4731 (define_expand "ashlsi3"
4732 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4733 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4734 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4735 ""
4736 "
4737 {
4738 if (TARGET_POWER)
4739 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4740 else
4741 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4742 DONE;
4743 }")
4745 (define_insn "ashlsi3_power"
4746 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4747 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4748 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4749 (clobber (match_scratch:SI 3 "=q,X"))]
4750 "TARGET_POWER"
4751 "@
4752 sle %0,%1,%2
4753 {sli|slwi} %0,%1,%h2")
4755 (define_insn "ashlsi3_no_power"
4756 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4757 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4758 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4759 "! TARGET_POWER"
4760 "@
4761 {sl|slw} %0,%1,%2
4762 {sli|slwi} %0,%1,%h2"
4763 [(set_attr "type" "var_shift_rotate,shift")])
4765 (define_insn "*ashlsi3_64"
4766 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4767 (zero_extend:DI
4768 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4769 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4770 "TARGET_POWERPC64"
4771 "@
4772 {sl|slw} %0,%1,%2
4773 {sli|slwi} %0,%1,%h2"
4774 [(set_attr "type" "var_shift_rotate,shift")])
4776 (define_insn ""
4777 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4778 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4779 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4780 (const_int 0)))
4781 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4782 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4783 "TARGET_POWER"
4784 "@
4785 sle. %3,%1,%2
4786 {sli.|slwi.} %3,%1,%h2
4787 #
4788 #"
4789 [(set_attr "type" "delayed_compare")
4790 (set_attr "length" "4,4,8,8")])
4792 (define_split
4793 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4794 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4795 (match_operand:SI 2 "reg_or_cint_operand" ""))
4796 (const_int 0)))
4797 (clobber (match_scratch:SI 3 ""))
4798 (clobber (match_scratch:SI 4 ""))]
4799 "TARGET_POWER && reload_completed"
4800 [(parallel [(set (match_dup 3)
4801 (ashift:SI (match_dup 1) (match_dup 2)))
4802 (clobber (match_dup 4))])
4803 (set (match_dup 0)
4804 (compare:CC (match_dup 3)
4805 (const_int 0)))]
4806 "")
4808 (define_insn ""
4809 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4810 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4811 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4812 (const_int 0)))
4813 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4814 "! TARGET_POWER && TARGET_32BIT"
4815 "@
4816 {sl.|slw.} %3,%1,%2
4817 {sli.|slwi.} %3,%1,%h2
4818 #
4819 #"
4820 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4821 (set_attr "length" "4,4,8,8")])
4823 (define_split
4824 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4825 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4826 (match_operand:SI 2 "reg_or_cint_operand" ""))
4827 (const_int 0)))
4828 (clobber (match_scratch:SI 3 ""))]
4829 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4830 [(set (match_dup 3)
4831 (ashift:SI (match_dup 1) (match_dup 2)))
4832 (set (match_dup 0)
4833 (compare:CC (match_dup 3)
4834 (const_int 0)))]
4835 "")
4837 (define_insn ""
4838 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4839 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4840 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4841 (const_int 0)))
4842 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4843 (ashift:SI (match_dup 1) (match_dup 2)))
4844 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4845 "TARGET_POWER"
4846 "@
4847 sle. %0,%1,%2
4848 {sli.|slwi.} %0,%1,%h2
4849 #
4850 #"
4851 [(set_attr "type" "delayed_compare")
4852 (set_attr "length" "4,4,8,8")])
4854 (define_split
4855 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4856 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4857 (match_operand:SI 2 "reg_or_cint_operand" ""))
4858 (const_int 0)))
4859 (set (match_operand:SI 0 "gpc_reg_operand" "")
4860 (ashift:SI (match_dup 1) (match_dup 2)))
4861 (clobber (match_scratch:SI 4 ""))]
4862 "TARGET_POWER && reload_completed"
4863 [(parallel [(set (match_dup 0)
4864 (ashift:SI (match_dup 1) (match_dup 2)))
4865 (clobber (match_dup 4))])
4866 (set (match_dup 3)
4867 (compare:CC (match_dup 0)
4868 (const_int 0)))]
4869 "")
4871 (define_insn ""
4872 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4873 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4874 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4875 (const_int 0)))
4876 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4877 (ashift:SI (match_dup 1) (match_dup 2)))]
4878 "! TARGET_POWER && TARGET_32BIT"
4879 "@
4880 {sl.|slw.} %0,%1,%2
4881 {sli.|slwi.} %0,%1,%h2
4882 #
4883 #"
4884 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4885 (set_attr "length" "4,4,8,8")])
4887 (define_split
4888 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4889 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4890 (match_operand:SI 2 "reg_or_cint_operand" ""))
4891 (const_int 0)))
4892 (set (match_operand:SI 0 "gpc_reg_operand" "")
4893 (ashift:SI (match_dup 1) (match_dup 2)))]
4894 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4895 [(set (match_dup 0)
4896 (ashift:SI (match_dup 1) (match_dup 2)))
4897 (set (match_dup 3)
4898 (compare:CC (match_dup 0)
4899 (const_int 0)))]
4900 "")
4902 (define_insn "rlwinm"
4903 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4904 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4905 (match_operand:SI 2 "const_int_operand" "i"))
4906 (match_operand:SI 3 "mask_operand" "n")))]
4907 "includes_lshift_p (operands[2], operands[3])"
4908 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4910 (define_insn ""
4911 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4912 (compare:CC
4913 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4914 (match_operand:SI 2 "const_int_operand" "i,i"))
4915 (match_operand:SI 3 "mask_operand" "n,n"))
4916 (const_int 0)))
4917 (clobber (match_scratch:SI 4 "=r,r"))]
4918 "includes_lshift_p (operands[2], operands[3])"
4919 "@
4920 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4921 #"
4922 [(set_attr "type" "delayed_compare")
4923 (set_attr "length" "4,8")])
4925 (define_split
4926 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4927 (compare:CC
4928 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4929 (match_operand:SI 2 "const_int_operand" ""))
4930 (match_operand:SI 3 "mask_operand" ""))
4931 (const_int 0)))
4932 (clobber (match_scratch:SI 4 ""))]
4933 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4934 [(set (match_dup 4)
4935 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4936 (match_dup 3)))
4937 (set (match_dup 0)
4938 (compare:CC (match_dup 4)
4939 (const_int 0)))]
4940 "")
4942 (define_insn ""
4943 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4944 (compare:CC
4945 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4946 (match_operand:SI 2 "const_int_operand" "i,i"))
4947 (match_operand:SI 3 "mask_operand" "n,n"))
4948 (const_int 0)))
4949 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4950 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4951 "includes_lshift_p (operands[2], operands[3])"
4952 "@
4953 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4954 #"
4955 [(set_attr "type" "delayed_compare")
4956 (set_attr "length" "4,8")])
4958 (define_split
4959 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4960 (compare:CC
4961 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4962 (match_operand:SI 2 "const_int_operand" ""))
4963 (match_operand:SI 3 "mask_operand" ""))
4964 (const_int 0)))
4965 (set (match_operand:SI 0 "gpc_reg_operand" "")
4966 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4967 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4968 [(set (match_dup 0)
4969 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4970 (set (match_dup 4)
4971 (compare:CC (match_dup 0)
4972 (const_int 0)))]
4973 "")
4975 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4976 ;; "sli x,x,0".
4977 (define_expand "lshrsi3"
4978 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4979 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4980 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4981 ""
4982 "
4983 {
4984 if (TARGET_POWER)
4985 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4986 else
4987 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4988 DONE;
4989 }")
4991 (define_insn "lshrsi3_power"
4992 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4993 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4994 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4995 (clobber (match_scratch:SI 3 "=q,X,X"))]
4996 "TARGET_POWER"
4997 "@
4998 sre %0,%1,%2
4999 mr %0,%1
5000 {s%A2i|s%A2wi} %0,%1,%h2")
5002 (define_insn "lshrsi3_no_power"
5003 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5004 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5005 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
5006 "! TARGET_POWER"
5007 "@
5008 mr %0,%1
5009 {sr|srw} %0,%1,%2
5010 {sri|srwi} %0,%1,%h2"
5011 [(set_attr "type" "integer,var_shift_rotate,shift")])
5013 (define_insn "*lshrsi3_64"
5014 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5015 (zero_extend:DI
5016 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5017 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5018 "TARGET_POWERPC64"
5019 "@
5020 {sr|srw} %0,%1,%2
5021 {sri|srwi} %0,%1,%h2"
5022 [(set_attr "type" "var_shift_rotate,shift")])
5024 (define_insn ""
5025 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5026 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5027 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5028 (const_int 0)))
5029 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
5030 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5031 "TARGET_POWER"
5032 "@
5033 sre. %3,%1,%2
5034 mr. %1,%1
5035 {s%A2i.|s%A2wi.} %3,%1,%h2
5036 #
5037 #
5038 #"
5039 [(set_attr "type" "delayed_compare")
5040 (set_attr "length" "4,4,4,8,8,8")])
5042 (define_split
5043 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5044 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5045 (match_operand:SI 2 "reg_or_cint_operand" ""))
5046 (const_int 0)))
5047 (clobber (match_scratch:SI 3 ""))
5048 (clobber (match_scratch:SI 4 ""))]
5049 "TARGET_POWER && reload_completed"
5050 [(parallel [(set (match_dup 3)
5051 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5052 (clobber (match_dup 4))])
5053 (set (match_dup 0)
5054 (compare:CC (match_dup 3)
5055 (const_int 0)))]
5056 "")
5058 (define_insn ""
5059 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5060 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5061 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5062 (const_int 0)))
5063 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
5064 "! TARGET_POWER && TARGET_32BIT"
5065 "@
5066 mr. %1,%1
5067 {sr.|srw.} %3,%1,%2
5068 {sri.|srwi.} %3,%1,%h2
5069 #
5070 #
5071 #"
5072 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5073 (set_attr "length" "4,4,4,8,8,8")])
5075 (define_split
5076 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5077 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5078 (match_operand:SI 2 "reg_or_cint_operand" ""))
5079 (const_int 0)))
5080 (clobber (match_scratch:SI 3 ""))]
5081 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5082 [(set (match_dup 3)
5083 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5084 (set (match_dup 0)
5085 (compare:CC (match_dup 3)
5086 (const_int 0)))]
5087 "")
5089 (define_insn ""
5090 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5091 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5092 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5093 (const_int 0)))
5094 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5095 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5096 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5097 "TARGET_POWER"
5098 "@
5099 sre. %0,%1,%2
5100 mr. %0,%1
5101 {s%A2i.|s%A2wi.} %0,%1,%h2
5102 #
5103 #
5104 #"
5105 [(set_attr "type" "delayed_compare")
5106 (set_attr "length" "4,4,4,8,8,8")])
5108 (define_split
5109 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5110 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5111 (match_operand:SI 2 "reg_or_cint_operand" ""))
5112 (const_int 0)))
5113 (set (match_operand:SI 0 "gpc_reg_operand" "")
5114 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5115 (clobber (match_scratch:SI 4 ""))]
5116 "TARGET_POWER && reload_completed"
5117 [(parallel [(set (match_dup 0)
5118 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5119 (clobber (match_dup 4))])
5120 (set (match_dup 3)
5121 (compare:CC (match_dup 0)
5122 (const_int 0)))]
5123 "")
5125 (define_insn ""
5126 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5127 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5128 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5129 (const_int 0)))
5130 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5131 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5132 "! TARGET_POWER && TARGET_32BIT"
5133 "@
5134 mr. %0,%1
5135 {sr.|srw.} %0,%1,%2
5136 {sri.|srwi.} %0,%1,%h2
5137 #
5138 #
5139 #"
5140 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5141 (set_attr "length" "4,4,4,8,8,8")])
5143 (define_split
5144 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5145 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5146 (match_operand:SI 2 "reg_or_cint_operand" ""))
5147 (const_int 0)))
5148 (set (match_operand:SI 0 "gpc_reg_operand" "")
5149 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5150 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5151 [(set (match_dup 0)
5152 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5153 (set (match_dup 3)
5154 (compare:CC (match_dup 0)
5155 (const_int 0)))]
5156 "")
5158 (define_insn ""
5159 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5160 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5161 (match_operand:SI 2 "const_int_operand" "i"))
5162 (match_operand:SI 3 "mask_operand" "n")))]
5163 "includes_rshift_p (operands[2], operands[3])"
5164 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
5166 (define_insn ""
5167 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5168 (compare:CC
5169 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5170 (match_operand:SI 2 "const_int_operand" "i,i"))
5171 (match_operand:SI 3 "mask_operand" "n,n"))
5172 (const_int 0)))
5173 (clobber (match_scratch:SI 4 "=r,r"))]
5174 "includes_rshift_p (operands[2], operands[3])"
5175 "@
5176 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
5177 #"
5178 [(set_attr "type" "delayed_compare")
5179 (set_attr "length" "4,8")])
5181 (define_split
5182 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5183 (compare:CC
5184 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5185 (match_operand:SI 2 "const_int_operand" ""))
5186 (match_operand:SI 3 "mask_operand" ""))
5187 (const_int 0)))
5188 (clobber (match_scratch:SI 4 ""))]
5189 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5190 [(set (match_dup 4)
5191 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
5192 (match_dup 3)))
5193 (set (match_dup 0)
5194 (compare:CC (match_dup 4)
5195 (const_int 0)))]
5196 "")
5198 (define_insn ""
5199 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5200 (compare:CC
5201 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5202 (match_operand:SI 2 "const_int_operand" "i,i"))
5203 (match_operand:SI 3 "mask_operand" "n,n"))
5204 (const_int 0)))
5205 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5206 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5207 "includes_rshift_p (operands[2], operands[3])"
5208 "@
5209 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
5210 #"
5211 [(set_attr "type" "delayed_compare")
5212 (set_attr "length" "4,8")])
5214 (define_split
5215 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5216 (compare:CC
5217 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5218 (match_operand:SI 2 "const_int_operand" ""))
5219 (match_operand:SI 3 "mask_operand" ""))
5220 (const_int 0)))
5221 (set (match_operand:SI 0 "gpc_reg_operand" "")
5222 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5223 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5224 [(set (match_dup 0)
5225 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5226 (set (match_dup 4)
5227 (compare:CC (match_dup 0)
5228 (const_int 0)))]
5229 "")
5231 (define_insn ""
5232 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5233 (zero_extend:SI
5234 (subreg:QI
5235 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5236 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5237 "includes_rshift_p (operands[2], GEN_INT (255))"
5238 "{rlinm|rlwinm} %0,%1,%s2,0xff")
5240 (define_insn ""
5241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5242 (compare:CC
5243 (zero_extend:SI
5244 (subreg:QI
5245 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5246 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5247 (const_int 0)))
5248 (clobber (match_scratch:SI 3 "=r,r"))]
5249 "includes_rshift_p (operands[2], GEN_INT (255))"
5250 "@
5251 {rlinm.|rlwinm.} %3,%1,%s2,0xff
5252 #"
5253 [(set_attr "type" "delayed_compare")
5254 (set_attr "length" "4,8")])
5256 (define_split
5257 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5258 (compare:CC
5259 (zero_extend:SI
5260 (subreg:QI
5261 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5262 (match_operand:SI 2 "const_int_operand" "")) 0))
5263 (const_int 0)))
5264 (clobber (match_scratch:SI 3 ""))]
5265 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5266 [(set (match_dup 3)
5267 (zero_extend:SI (subreg:QI
5268 (lshiftrt:SI (match_dup 1)
5269 (match_dup 2)) 0)))
5270 (set (match_dup 0)
5271 (compare:CC (match_dup 3)
5272 (const_int 0)))]
5273 "")
5275 (define_insn ""
5276 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5277 (compare:CC
5278 (zero_extend:SI
5279 (subreg:QI
5280 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5281 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5282 (const_int 0)))
5283 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5284 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5285 "includes_rshift_p (operands[2], GEN_INT (255))"
5286 "@
5287 {rlinm.|rlwinm.} %0,%1,%s2,0xff
5288 #"
5289 [(set_attr "type" "delayed_compare")
5290 (set_attr "length" "4,8")])
5292 (define_split
5293 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5294 (compare:CC
5295 (zero_extend:SI
5296 (subreg:QI
5297 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5298 (match_operand:SI 2 "const_int_operand" "")) 0))
5299 (const_int 0)))
5300 (set (match_operand:SI 0 "gpc_reg_operand" "")
5301 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5302 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5303 [(set (match_dup 0)
5304 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5305 (set (match_dup 3)
5306 (compare:CC (match_dup 0)
5307 (const_int 0)))]
5308 "")
5310 (define_insn ""
5311 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5312 (zero_extend:SI
5313 (subreg:HI
5314 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5315 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5316 "includes_rshift_p (operands[2], GEN_INT (65535))"
5317 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
5319 (define_insn ""
5320 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5321 (compare:CC
5322 (zero_extend:SI
5323 (subreg:HI
5324 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5325 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5326 (const_int 0)))
5327 (clobber (match_scratch:SI 3 "=r,r"))]
5328 "includes_rshift_p (operands[2], GEN_INT (65535))"
5329 "@
5330 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
5331 #"
5332 [(set_attr "type" "delayed_compare")
5333 (set_attr "length" "4,8")])
5335 (define_split
5336 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5337 (compare:CC
5338 (zero_extend:SI
5339 (subreg:HI
5340 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5341 (match_operand:SI 2 "const_int_operand" "")) 0))
5342 (const_int 0)))
5343 (clobber (match_scratch:SI 3 ""))]
5344 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5345 [(set (match_dup 3)
5346 (zero_extend:SI (subreg:HI
5347 (lshiftrt:SI (match_dup 1)
5348 (match_dup 2)) 0)))
5349 (set (match_dup 0)
5350 (compare:CC (match_dup 3)
5351 (const_int 0)))]
5352 "")
5354 (define_insn ""
5355 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5356 (compare:CC
5357 (zero_extend:SI
5358 (subreg:HI
5359 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5360 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5361 (const_int 0)))
5362 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5363 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5364 "includes_rshift_p (operands[2], GEN_INT (65535))"
5365 "@
5366 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
5367 #"
5368 [(set_attr "type" "delayed_compare")
5369 (set_attr "length" "4,8")])
5371 (define_split
5372 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5373 (compare:CC
5374 (zero_extend:SI
5375 (subreg:HI
5376 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5377 (match_operand:SI 2 "const_int_operand" "")) 0))
5378 (const_int 0)))
5379 (set (match_operand:SI 0 "gpc_reg_operand" "")
5380 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5381 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5382 [(set (match_dup 0)
5383 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5384 (set (match_dup 3)
5385 (compare:CC (match_dup 0)
5386 (const_int 0)))]
5387 "")
5389 (define_insn ""
5390 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5391 (const_int 1)
5392 (match_operand:SI 1 "gpc_reg_operand" "r"))
5393 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5394 (const_int 31)))]
5395 "TARGET_POWER"
5396 "rrib %0,%1,%2")
5398 (define_insn ""
5399 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5400 (const_int 1)
5401 (match_operand:SI 1 "gpc_reg_operand" "r"))
5402 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5403 (const_int 31)))]
5404 "TARGET_POWER"
5405 "rrib %0,%1,%2")
5407 (define_insn ""
5408 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5409 (const_int 1)
5410 (match_operand:SI 1 "gpc_reg_operand" "r"))
5411 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5412 (const_int 1)
5413 (const_int 0)))]
5414 "TARGET_POWER"
5415 "rrib %0,%1,%2")
5417 (define_expand "ashrsi3"
5418 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5419 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5420 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5421 ""
5422 "
5423 {
5424 if (TARGET_POWER)
5425 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
5426 else
5427 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
5428 DONE;
5429 }")
5431 (define_insn "ashrsi3_power"
5432 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5433 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5434 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
5435 (clobber (match_scratch:SI 3 "=q,X"))]
5436 "TARGET_POWER"
5437 "@
5438 srea %0,%1,%2
5439 {srai|srawi} %0,%1,%h2"
5440 [(set_attr "type" "shift")])
5442 (define_insn "ashrsi3_no_power"
5443 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5444 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5445 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
5446 "! TARGET_POWER"
5447 "@
5448 {sra|sraw} %0,%1,%2
5449 {srai|srawi} %0,%1,%h2"
5450 [(set_attr "type" "var_shift_rotate,shift")])
5452 (define_insn "*ashrsi3_64"
5453 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5454 (sign_extend:DI
5455 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5456 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5457 "TARGET_POWERPC64"
5458 "@
5459 {sra|sraw} %0,%1,%2
5460 {srai|srawi} %0,%1,%h2"
5461 [(set_attr "type" "var_shift_rotate,shift")])
5463 (define_insn ""
5464 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5465 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5466 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5467 (const_int 0)))
5468 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5469 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5470 "TARGET_POWER"
5471 "@
5472 srea. %3,%1,%2
5473 {srai.|srawi.} %3,%1,%h2
5474 #
5475 #"
5476 [(set_attr "type" "delayed_compare")
5477 (set_attr "length" "4,4,8,8")])
5479 (define_split
5480 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5481 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5482 (match_operand:SI 2 "reg_or_cint_operand" ""))
5483 (const_int 0)))
5484 (clobber (match_scratch:SI 3 ""))
5485 (clobber (match_scratch:SI 4 ""))]
5486 "TARGET_POWER && reload_completed"
5487 [(parallel [(set (match_dup 3)
5488 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5489 (clobber (match_dup 4))])
5490 (set (match_dup 0)
5491 (compare:CC (match_dup 3)
5492 (const_int 0)))]
5493 "")
5495 (define_insn ""
5496 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5497 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5498 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5499 (const_int 0)))
5500 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5501 "! TARGET_POWER"
5502 "@
5503 {sra.|sraw.} %3,%1,%2
5504 {srai.|srawi.} %3,%1,%h2
5505 #
5506 #"
5507 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5508 (set_attr "length" "4,4,8,8")])
5510 (define_split
5511 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5512 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5513 (match_operand:SI 2 "reg_or_cint_operand" ""))
5514 (const_int 0)))
5515 (clobber (match_scratch:SI 3 ""))]
5516 "! TARGET_POWER && reload_completed"
5517 [(set (match_dup 3)
5518 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5519 (set (match_dup 0)
5520 (compare:CC (match_dup 3)
5521 (const_int 0)))]
5522 "")
5524 (define_insn ""
5525 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5526 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5527 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5528 (const_int 0)))
5529 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5530 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5531 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5532 "TARGET_POWER"
5533 "@
5534 srea. %0,%1,%2
5535 {srai.|srawi.} %0,%1,%h2
5536 #
5537 #"
5538 [(set_attr "type" "delayed_compare")
5539 (set_attr "length" "4,4,8,8")])
5541 (define_split
5542 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5543 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5544 (match_operand:SI 2 "reg_or_cint_operand" ""))
5545 (const_int 0)))
5546 (set (match_operand:SI 0 "gpc_reg_operand" "")
5547 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5548 (clobber (match_scratch:SI 4 ""))]
5549 "TARGET_POWER && reload_completed"
5550 [(parallel [(set (match_dup 0)
5551 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5552 (clobber (match_dup 4))])
5553 (set (match_dup 3)
5554 (compare:CC (match_dup 0)
5555 (const_int 0)))]
5556 "")
5558 (define_insn ""
5559 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5560 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5561 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5562 (const_int 0)))
5563 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5564 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5565 "! TARGET_POWER"
5566 "@
5567 {sra.|sraw.} %0,%1,%2
5568 {srai.|srawi.} %0,%1,%h2
5569 #
5570 #"
5571 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5572 (set_attr "length" "4,4,8,8")])
5573 \f
5574 ;; Builtins to replace a division to generate FRE reciprocal estimate
5575 ;; instructions and the necessary fixup instructions
5576 (define_expand "recip<mode>3"
5577 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5578 (match_operand:RECIPF 1 "gpc_reg_operand" "")
5579 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
5580 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
5581 {
5582 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
5583 DONE;
5584 })
5586 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
5587 ;; hardware division. This is only done before register allocation and with
5588 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
5589 (define_split
5590 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
5591 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
5592 (match_operand 2 "gpc_reg_operand" "")))]
5593 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5594 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
5595 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
5596 [(const_int 0)]
5597 {
5598 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
5599 DONE;
5600 })
5602 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5603 ;; appropriate fixup.
5604 (define_expand "rsqrt<mode>2"
5605 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5606 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5607 "RS6000_RECIP_HAVE_RSQRT_P (<MODE>mode)"
5608 {
5609 rs6000_emit_swrsqrt (operands[0], operands[1]);
5610 DONE;
5611 })
5612 \f
5613 (define_split
5614 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5615 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5616 (match_operand:SI 2 "reg_or_cint_operand" ""))
5617 (const_int 0)))
5618 (set (match_operand:SI 0 "gpc_reg_operand" "")
5619 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5620 "! TARGET_POWER && reload_completed"
5621 [(set (match_dup 0)
5622 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5623 (set (match_dup 3)
5624 (compare:CC (match_dup 0)
5625 (const_int 0)))]
5626 "")
5628 ;; Floating-point insns, excluding normal data motion.
5629 ;;
5630 ;; PowerPC has a full set of single-precision floating point instructions.
5631 ;;
5632 ;; For the POWER architecture, we pretend that we have both SFmode and
5633 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5634 ;; The only conversions we will do will be when storing to memory. In that
5635 ;; case, we will use the "frsp" instruction before storing.
5636 ;;
5637 ;; Note that when we store into a single-precision memory location, we need to
5638 ;; use the frsp insn first. If the register being stored isn't dead, we
5639 ;; need a scratch register for the frsp. But this is difficult when the store
5640 ;; is done by reload. It is not incorrect to do the frsp on the register in
5641 ;; this case, we just lose precision that we would have otherwise gotten but
5642 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5644 (define_expand "extendsfdf2"
5645 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5646 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5647 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5648 "")
5650 (define_insn_and_split "*extendsfdf2_fpr"
5651 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5652 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5653 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5654 "@
5655 #
5656 fmr %0,%1
5657 lfs%U1%X1 %0,%1"
5658 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5659 [(const_int 0)]
5660 {
5661 emit_note (NOTE_INSN_DELETED);
5662 DONE;
5663 }
5664 [(set_attr "type" "fp,fp,fpload")])
5666 (define_expand "truncdfsf2"
5667 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5668 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5669 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5670 "")
5672 (define_insn "*truncdfsf2_fpr"
5673 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5674 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5675 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5676 "frsp %0,%1"
5677 [(set_attr "type" "fp")])
5679 (define_insn "aux_truncdfsf2"
5680 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5681 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5682 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5683 "frsp %0,%1"
5684 [(set_attr "type" "fp")])
5686 (define_expand "negsf2"
5687 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5688 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5689 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5690 "")
5692 (define_insn "*negsf2"
5693 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5694 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5695 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5696 "fneg %0,%1"
5697 [(set_attr "type" "fp")])
5699 (define_expand "abssf2"
5700 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5701 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5702 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5703 "")
5705 (define_insn "*abssf2"
5706 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5707 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5708 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5709 "fabs %0,%1"
5710 [(set_attr "type" "fp")])
5712 (define_insn ""
5713 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5714 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5715 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5716 "fnabs %0,%1"
5717 [(set_attr "type" "fp")])
5719 (define_expand "addsf3"
5720 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5721 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5722 (match_operand:SF 2 "gpc_reg_operand" "")))]
5723 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5724 "")
5726 (define_insn ""
5727 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5728 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5729 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5730 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5731 "fadds %0,%1,%2"
5732 [(set_attr "type" "fp")
5733 (set_attr "fp_type" "fp_addsub_s")])
5735 (define_insn ""
5736 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5737 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5738 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5739 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5740 "{fa|fadd} %0,%1,%2"
5741 [(set_attr "type" "fp")])
5743 (define_expand "subsf3"
5744 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5745 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5746 (match_operand:SF 2 "gpc_reg_operand" "")))]
5747 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5748 "")
5750 (define_insn ""
5751 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5752 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5753 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5754 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5755 "fsubs %0,%1,%2"
5756 [(set_attr "type" "fp")
5757 (set_attr "fp_type" "fp_addsub_s")])
5759 (define_insn ""
5760 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5761 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5762 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5763 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5764 "{fs|fsub} %0,%1,%2"
5765 [(set_attr "type" "fp")])
5767 (define_expand "mulsf3"
5768 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5769 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5770 (match_operand:SF 2 "gpc_reg_operand" "")))]
5771 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5772 "")
5774 (define_insn ""
5775 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5776 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5777 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5778 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5779 "fmuls %0,%1,%2"
5780 [(set_attr "type" "fp")
5781 (set_attr "fp_type" "fp_mul_s")])
5783 (define_insn ""
5784 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5785 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5786 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5787 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5788 "{fm|fmul} %0,%1,%2"
5789 [(set_attr "type" "dmul")])
5791 (define_expand "divsf3"
5792 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5793 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5794 (match_operand:SF 2 "gpc_reg_operand" "")))]
5795 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5796 "")
5798 (define_insn ""
5799 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5800 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5801 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5802 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5803 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5804 "fdivs %0,%1,%2"
5805 [(set_attr "type" "sdiv")])
5807 (define_insn ""
5808 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5809 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5810 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5811 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5812 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5813 "{fd|fdiv} %0,%1,%2"
5814 [(set_attr "type" "ddiv")])
5816 (define_insn "fres"
5817 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5818 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5819 "TARGET_FRES"
5820 "fres %0,%1"
5821 [(set_attr "type" "fp")])
5823 (define_insn "*fmaddsf4_powerpc"
5824 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5825 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5826 (match_operand:SF 2 "gpc_reg_operand" "f"))
5827 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5828 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5829 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5830 "fmadds %0,%1,%2,%3"
5831 [(set_attr "type" "fp")
5832 (set_attr "fp_type" "fp_maddsub_s")])
5834 (define_insn "*fmaddsf4_power"
5835 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5836 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5837 (match_operand:SF 2 "gpc_reg_operand" "f"))
5838 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5839 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5840 "{fma|fmadd} %0,%1,%2,%3"
5841 [(set_attr "type" "dmul")])
5843 (define_insn "*fmsubsf4_powerpc"
5844 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5845 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5846 (match_operand:SF 2 "gpc_reg_operand" "f"))
5847 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5848 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5849 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5850 "fmsubs %0,%1,%2,%3"
5851 [(set_attr "type" "fp")
5852 (set_attr "fp_type" "fp_maddsub_s")])
5854 (define_insn "*fmsubsf4_power"
5855 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5856 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5857 (match_operand:SF 2 "gpc_reg_operand" "f"))
5858 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5859 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5860 "{fms|fmsub} %0,%1,%2,%3"
5861 [(set_attr "type" "dmul")])
5863 (define_insn "*fnmaddsf4_powerpc_1"
5864 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5865 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5866 (match_operand:SF 2 "gpc_reg_operand" "f"))
5867 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5868 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5869 && TARGET_SINGLE_FLOAT"
5870 "fnmadds %0,%1,%2,%3"
5871 [(set_attr "type" "fp")
5872 (set_attr "fp_type" "fp_maddsub_s")])
5874 (define_insn "*fnmaddsf4_powerpc_2"
5875 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5876 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5877 (match_operand:SF 2 "gpc_reg_operand" "f"))
5878 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5879 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5880 && ! HONOR_SIGNED_ZEROS (SFmode)"
5881 "fnmadds %0,%1,%2,%3"
5882 [(set_attr "type" "fp")
5883 (set_attr "fp_type" "fp_maddsub_s")])
5885 (define_insn "*fnmaddsf4_power_1"
5886 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5887 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5888 (match_operand:SF 2 "gpc_reg_operand" "f"))
5889 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5890 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5891 "{fnma|fnmadd} %0,%1,%2,%3"
5892 [(set_attr "type" "dmul")])
5894 (define_insn "*fnmaddsf4_power_2"
5895 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5896 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5897 (match_operand:SF 2 "gpc_reg_operand" "f"))
5898 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5899 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5900 && ! HONOR_SIGNED_ZEROS (SFmode)"
5901 "{fnma|fnmadd} %0,%1,%2,%3"
5902 [(set_attr "type" "dmul")])
5904 (define_insn "*fnmsubsf4_powerpc_1"
5905 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5906 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5907 (match_operand:SF 2 "gpc_reg_operand" "f"))
5908 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5909 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5910 && TARGET_SINGLE_FLOAT"
5911 "fnmsubs %0,%1,%2,%3"
5912 [(set_attr "type" "fp")
5913 (set_attr "fp_type" "fp_maddsub_s")])
5915 (define_insn "*fnmsubsf4_powerpc_2"
5916 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5917 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5918 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5919 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5920 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5921 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5922 "fnmsubs %0,%1,%2,%3"
5923 [(set_attr "type" "fp")
5924 (set_attr "fp_type" "fp_maddsub_s")])
5926 (define_insn "*fnmsubsf4_power_1"
5927 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5928 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5929 (match_operand:SF 2 "gpc_reg_operand" "f"))
5930 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5931 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5932 "{fnms|fnmsub} %0,%1,%2,%3"
5933 [(set_attr "type" "dmul")])
5935 (define_insn "*fnmsubsf4_power_2"
5936 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5937 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5938 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5939 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5940 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5941 && ! HONOR_SIGNED_ZEROS (SFmode)"
5942 "{fnms|fnmsub} %0,%1,%2,%3"
5943 [(set_attr "type" "dmul")])
5945 (define_expand "sqrtsf2"
5946 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5947 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5948 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5949 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5950 && !TARGET_SIMPLE_FPU"
5951 "")
5953 (define_insn ""
5954 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5955 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5956 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5957 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5958 "fsqrts %0,%1"
5959 [(set_attr "type" "ssqrt")])
5961 (define_insn ""
5962 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5963 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5964 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5965 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5966 "fsqrt %0,%1"
5967 [(set_attr "type" "dsqrt")])
5969 (define_insn "*rsqrtsf_internal1"
5970 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5971 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5972 UNSPEC_RSQRT))]
5973 "TARGET_FRSQRTES"
5974 "frsqrtes %0,%1"
5975 [(set_attr "type" "fp")])
5977 (define_expand "copysignsf3"
5978 [(set (match_dup 3)
5979 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5980 (set (match_dup 4)
5981 (neg:SF (abs:SF (match_dup 1))))
5982 (set (match_operand:SF 0 "gpc_reg_operand" "")
5983 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5984 (match_dup 5))
5985 (match_dup 3)
5986 (match_dup 4)))]
5987 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5988 && ((TARGET_PPC_GFXOPT
5989 && !HONOR_NANS (SFmode)
5990 && !HONOR_SIGNED_ZEROS (SFmode))
5991 || VECTOR_UNIT_VSX_P (DFmode))"
5992 {
5993 if (VECTOR_UNIT_VSX_P (DFmode))
5994 {
5995 emit_insn (gen_vsx_copysignsf3 (operands[0], operands[1], operands[2],
5996 CONST0_RTX (SFmode)));
5997 DONE;
5998 }
5999 operands[3] = gen_reg_rtx (SFmode);
6000 operands[4] = gen_reg_rtx (SFmode);
6001 operands[5] = CONST0_RTX (SFmode);
6002 })
6004 (define_expand "copysigndf3"
6005 [(set (match_dup 3)
6006 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
6007 (set (match_dup 4)
6008 (neg:DF (abs:DF (match_dup 1))))
6009 (set (match_operand:DF 0 "gpc_reg_operand" "")
6010 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
6011 (match_dup 5))
6012 (match_dup 3)
6013 (match_dup 4)))]
6014 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6015 && ((TARGET_PPC_GFXOPT
6016 && !HONOR_NANS (DFmode)
6017 && !HONOR_SIGNED_ZEROS (DFmode))
6018 || VECTOR_UNIT_VSX_P (DFmode))"
6019 {
6020 if (VECTOR_UNIT_VSX_P (DFmode))
6021 {
6022 emit_insn (gen_vsx_copysigndf3 (operands[0], operands[1],
6023 operands[2], CONST0_RTX (DFmode)));
6024 DONE;
6025 }
6026 operands[3] = gen_reg_rtx (DFmode);
6027 operands[4] = gen_reg_rtx (DFmode);
6028 operands[5] = CONST0_RTX (DFmode);
6029 })
6031 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
6032 ;; fsel instruction and some auxiliary computations. Then we just have a
6033 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
6034 ;; combine.
6035 (define_expand "smaxsf3"
6036 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6037 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6038 (match_operand:SF 2 "gpc_reg_operand" ""))
6039 (match_dup 1)
6040 (match_dup 2)))]
6041 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6042 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6043 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6045 (define_expand "sminsf3"
6046 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6047 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6048 (match_operand:SF 2 "gpc_reg_operand" ""))
6049 (match_dup 2)
6050 (match_dup 1)))]
6051 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6052 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6053 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6055 (define_split
6056 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6057 (match_operator:SF 3 "min_max_operator"
6058 [(match_operand:SF 1 "gpc_reg_operand" "")
6059 (match_operand:SF 2 "gpc_reg_operand" "")]))]
6060 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6061 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6062 [(const_int 0)]
6063 "
6064 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6065 operands[1], operands[2]);
6066 DONE;
6067 }")
6069 (define_expand "mov<mode>cc"
6070 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
6071 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6072 (match_operand:GPR 2 "gpc_reg_operand" "")
6073 (match_operand:GPR 3 "gpc_reg_operand" "")))]
6074 "TARGET_ISEL<sel>"
6075 "
6076 {
6077 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6078 DONE;
6079 else
6080 FAIL;
6081 }")
6083 ;; We use the BASE_REGS for the isel input operands because, if rA is
6084 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
6085 ;; because we may switch the operands and rB may end up being rA.
6086 ;;
6087 ;; We need 2 patterns: an unsigned and a signed pattern. We could
6088 ;; leave out the mode in operand 4 and use one pattern, but reload can
6089 ;; change the mode underneath our feet and then gets confused trying
6090 ;; to reload the value.
6091 (define_insn "isel_signed_<mode>"
6092 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6093 (if_then_else:GPR
6094 (match_operator 1 "comparison_operator"
6095 [(match_operand:CC 4 "cc_reg_operand" "y")
6096 (const_int 0)])
6097 (match_operand:GPR 2 "gpc_reg_operand" "b")
6098 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6099 "TARGET_ISEL<sel>"
6100 "*
6101 { return output_isel (operands); }"
6102 [(set_attr "type" "isel")
6103 (set_attr "length" "4")])
6105 (define_insn "isel_unsigned_<mode>"
6106 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6107 (if_then_else:GPR
6108 (match_operator 1 "comparison_operator"
6109 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
6110 (const_int 0)])
6111 (match_operand:GPR 2 "gpc_reg_operand" "b")
6112 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6113 "TARGET_ISEL<sel>"
6114 "*
6115 { return output_isel (operands); }"
6116 [(set_attr "type" "isel")
6117 (set_attr "length" "4")])
6119 (define_expand "movsfcc"
6120 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6121 (if_then_else:SF (match_operand 1 "comparison_operator" "")
6122 (match_operand:SF 2 "gpc_reg_operand" "")
6123 (match_operand:SF 3 "gpc_reg_operand" "")))]
6124 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6125 "
6126 {
6127 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6128 DONE;
6129 else
6130 FAIL;
6131 }")
6133 (define_insn "*fselsfsf4"
6134 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6135 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6136 (match_operand:SF 4 "zero_fp_constant" "F"))
6137 (match_operand:SF 2 "gpc_reg_operand" "f")
6138 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6139 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6140 "fsel %0,%1,%2,%3"
6141 [(set_attr "type" "fp")])
6143 (define_insn "*fseldfsf4"
6144 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6145 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6146 (match_operand:DF 4 "zero_fp_constant" "F"))
6147 (match_operand:SF 2 "gpc_reg_operand" "f")
6148 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6149 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6150 "fsel %0,%1,%2,%3"
6151 [(set_attr "type" "fp")])
6153 (define_expand "negdf2"
6154 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6155 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6156 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6157 "")
6159 (define_insn "*negdf2_fpr"
6160 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6161 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6162 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6163 && !VECTOR_UNIT_VSX_P (DFmode)"
6164 "fneg %0,%1"
6165 [(set_attr "type" "fp")])
6167 (define_expand "absdf2"
6168 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6169 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6170 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6171 "")
6173 (define_insn "*absdf2_fpr"
6174 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6175 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6176 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6177 && !VECTOR_UNIT_VSX_P (DFmode)"
6178 "fabs %0,%1"
6179 [(set_attr "type" "fp")])
6181 (define_insn "*nabsdf2_fpr"
6182 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6183 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6184 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6185 && !VECTOR_UNIT_VSX_P (DFmode)"
6186 "fnabs %0,%1"
6187 [(set_attr "type" "fp")])
6189 (define_expand "adddf3"
6190 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6191 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6192 (match_operand:DF 2 "gpc_reg_operand" "")))]
6193 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6194 "")
6196 (define_insn "*adddf3_fpr"
6197 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6198 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6199 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6200 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6201 && !VECTOR_UNIT_VSX_P (DFmode)"
6202 "{fa|fadd} %0,%1,%2"
6203 [(set_attr "type" "fp")
6204 (set_attr "fp_type" "fp_addsub_d")])
6206 (define_expand "subdf3"
6207 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6208 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6209 (match_operand:DF 2 "gpc_reg_operand" "")))]
6210 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6211 "")
6213 (define_insn "*subdf3_fpr"
6214 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6215 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6216 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6217 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6218 && !VECTOR_UNIT_VSX_P (DFmode)"
6219 "{fs|fsub} %0,%1,%2"
6220 [(set_attr "type" "fp")
6221 (set_attr "fp_type" "fp_addsub_d")])
6223 (define_expand "muldf3"
6224 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6225 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
6226 (match_operand:DF 2 "gpc_reg_operand" "")))]
6227 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6228 "")
6230 (define_insn "*muldf3_fpr"
6231 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6232 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6233 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6234 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6235 && !VECTOR_UNIT_VSX_P (DFmode)"
6236 "{fm|fmul} %0,%1,%2"
6237 [(set_attr "type" "dmul")
6238 (set_attr "fp_type" "fp_mul_d")])
6240 (define_expand "divdf3"
6241 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6242 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
6243 (match_operand:DF 2 "gpc_reg_operand" "")))]
6244 "TARGET_HARD_FLOAT
6245 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
6246 && !TARGET_SIMPLE_FPU"
6247 "")
6249 (define_insn "*divdf3_fpr"
6250 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6251 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6252 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6253 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
6254 && !VECTOR_UNIT_VSX_P (DFmode)"
6255 "{fd|fdiv} %0,%1,%2"
6256 [(set_attr "type" "ddiv")])
6258 (define_insn "*fred_fpr"
6259 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6260 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
6261 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
6262 "fre %0,%1"
6263 [(set_attr "type" "fp")])
6265 (define_insn "*rsqrtdf_internal1"
6266 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6267 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
6268 UNSPEC_RSQRT))]
6269 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
6270 "frsqrte %0,%1"
6271 [(set_attr "type" "fp")])
6273 (define_insn "*fmadddf4_fpr"
6274 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6275 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6276 (match_operand:DF 2 "gpc_reg_operand" "d"))
6277 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6278 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6279 && VECTOR_UNIT_NONE_P (DFmode)"
6280 "{fma|fmadd} %0,%1,%2,%3"
6281 [(set_attr "type" "dmul")
6282 (set_attr "fp_type" "fp_maddsub_d")])
6284 (define_insn "*fmsubdf4_fpr"
6285 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6286 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6287 (match_operand:DF 2 "gpc_reg_operand" "d"))
6288 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6289 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6290 && VECTOR_UNIT_NONE_P (DFmode)"
6291 "{fms|fmsub} %0,%1,%2,%3"
6292 [(set_attr "type" "dmul")
6293 (set_attr "fp_type" "fp_maddsub_d")])
6295 (define_insn "*fnmadddf4_fpr_1"
6296 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6297 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6298 (match_operand:DF 2 "gpc_reg_operand" "d"))
6299 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6300 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6301 && VECTOR_UNIT_NONE_P (DFmode)"
6302 "{fnma|fnmadd} %0,%1,%2,%3"
6303 [(set_attr "type" "dmul")
6304 (set_attr "fp_type" "fp_maddsub_d")])
6306 (define_insn "*fnmadddf4_fpr_2"
6307 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6308 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d"))
6309 (match_operand:DF 2 "gpc_reg_operand" "d"))
6310 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6311 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6312 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6313 "{fnma|fnmadd} %0,%1,%2,%3"
6314 [(set_attr "type" "dmul")
6315 (set_attr "fp_type" "fp_maddsub_d")])
6317 (define_insn "*fnmsubdf4_fpr_1"
6318 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6319 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6320 (match_operand:DF 2 "gpc_reg_operand" "d"))
6321 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6322 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6323 && VECTOR_UNIT_NONE_P (DFmode)"
6324 "{fnms|fnmsub} %0,%1,%2,%3"
6325 [(set_attr "type" "dmul")
6326 (set_attr "fp_type" "fp_maddsub_d")])
6328 (define_insn "*fnmsubdf4_fpr_2"
6329 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6330 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d")
6331 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6332 (match_operand:DF 2 "gpc_reg_operand" "d"))))]
6333 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6334 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6335 "{fnms|fnmsub} %0,%1,%2,%3"
6336 [(set_attr "type" "dmul")
6337 (set_attr "fp_type" "fp_maddsub_d")])
6339 (define_expand "sqrtdf2"
6340 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6341 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6342 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6343 && TARGET_DOUBLE_FLOAT"
6344 "")
6346 (define_insn "*sqrtdf2_fpr"
6347 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6348 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6349 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6350 && TARGET_DOUBLE_FLOAT
6351 && !VECTOR_UNIT_VSX_P (DFmode)"
6352 "fsqrt %0,%1"
6353 [(set_attr "type" "dsqrt")])
6355 ;; The conditional move instructions allow us to perform max and min
6356 ;; operations even when
6358 (define_expand "smaxdf3"
6359 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6360 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6361 (match_operand:DF 2 "gpc_reg_operand" ""))
6362 (match_dup 1)
6363 (match_dup 2)))]
6364 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6365 && !flag_trapping_math"
6366 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6368 (define_expand "smindf3"
6369 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6370 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6371 (match_operand:DF 2 "gpc_reg_operand" ""))
6372 (match_dup 2)
6373 (match_dup 1)))]
6374 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6375 && !flag_trapping_math"
6376 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6378 (define_split
6379 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6380 (match_operator:DF 3 "min_max_operator"
6381 [(match_operand:DF 1 "gpc_reg_operand" "")
6382 (match_operand:DF 2 "gpc_reg_operand" "")]))]
6383 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6384 && !flag_trapping_math"
6385 [(const_int 0)]
6386 "
6387 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6388 operands[1], operands[2]);
6389 DONE;
6390 }")
6392 (define_expand "movdfcc"
6393 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6394 (if_then_else:DF (match_operand 1 "comparison_operator" "")
6395 (match_operand:DF 2 "gpc_reg_operand" "")
6396 (match_operand:DF 3 "gpc_reg_operand" "")))]
6397 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6398 "
6399 {
6400 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6401 DONE;
6402 else
6403 FAIL;
6404 }")
6406 (define_insn "*fseldfdf4"
6407 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6408 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6409 (match_operand:DF 4 "zero_fp_constant" "F"))
6410 (match_operand:DF 2 "gpc_reg_operand" "d")
6411 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6412 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6413 "fsel %0,%1,%2,%3"
6414 [(set_attr "type" "fp")])
6416 (define_insn "*fselsfdf4"
6417 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6418 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6419 (match_operand:SF 4 "zero_fp_constant" "F"))
6420 (match_operand:DF 2 "gpc_reg_operand" "d")
6421 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6422 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6423 "fsel %0,%1,%2,%3"
6424 [(set_attr "type" "fp")])
6425 \f
6426 ;; Conversions to and from floating-point.
6428 (define_expand "fixuns_truncsfsi2"
6429 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6430 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6431 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6432 "")
6434 (define_expand "fix_truncsfsi2"
6435 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6436 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6437 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6438 "")
6440 (define_expand "fixuns_truncdfsi2"
6441 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6442 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
6443 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
6444 "")
6446 (define_expand "fixuns_truncdfdi2"
6447 [(set (match_operand:DI 0 "register_operand" "")
6448 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
6449 "TARGET_HARD_FLOAT && TARGET_VSX"
6450 "")
6452 ; For each of these conversions, there is a define_expand, a define_insn
6453 ; with a '#' template, and a define_split (with C code). The idea is
6454 ; to allow constant folding with the template of the define_insn,
6455 ; then to have the insns split later (between sched1 and final).
6457 (define_expand "floatsidf2"
6458 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6459 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6460 (use (match_dup 2))
6461 (use (match_dup 3))
6462 (clobber (match_dup 4))
6463 (clobber (match_dup 5))
6464 (clobber (match_dup 6))])]
6465 "TARGET_HARD_FLOAT
6466 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6467 "
6468 {
6469 if (TARGET_E500_DOUBLE)
6470 {
6471 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
6472 DONE;
6473 }
6474 if (TARGET_POWERPC64)
6475 {
6476 rtx x = convert_to_mode (DImode, operands[1], 0);
6477 emit_insn (gen_floatdidf2 (operands[0], x));
6478 DONE;
6479 }
6481 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6482 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
6483 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6484 operands[5] = gen_reg_rtx (DFmode);
6485 operands[6] = gen_reg_rtx (SImode);
6486 }")
6488 (define_insn_and_split "*floatsidf2_internal"
6489 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6490 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6491 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6492 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6493 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6494 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6495 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
6496 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6497 "#"
6498 ""
6499 [(pc)]
6500 "
6501 {
6502 rtx lowword, highword;
6503 gcc_assert (MEM_P (operands[4]));
6504 highword = adjust_address (operands[4], SImode, 0);
6505 lowword = adjust_address (operands[4], SImode, 4);
6506 if (! WORDS_BIG_ENDIAN)
6507 {
6508 rtx tmp;
6509 tmp = highword; highword = lowword; lowword = tmp;
6510 }
6512 emit_insn (gen_xorsi3 (operands[6], operands[1],
6513 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
6514 emit_move_insn (lowword, operands[6]);
6515 emit_move_insn (highword, operands[2]);
6516 emit_move_insn (operands[5], operands[4]);
6517 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6518 DONE;
6519 }"
6520 [(set_attr "length" "24")])
6522 (define_expand "floatunssisf2"
6523 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6524 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6525 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6526 "")
6528 (define_expand "floatunssidf2"
6529 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6530 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6531 (use (match_dup 2))
6532 (use (match_dup 3))
6533 (clobber (match_dup 4))
6534 (clobber (match_dup 5))])]
6535 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6536 "
6537 {
6538 if (TARGET_E500_DOUBLE)
6539 {
6540 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6541 DONE;
6542 }
6543 if (TARGET_POWERPC64)
6544 {
6545 rtx x = convert_to_mode (DImode, operands[1], 1);
6546 emit_insn (gen_floatdidf2 (operands[0], x));
6547 DONE;
6548 }
6550 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6551 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6552 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6553 operands[5] = gen_reg_rtx (DFmode);
6554 }")
6556 (define_insn_and_split "*floatunssidf2_internal"
6557 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6558 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6559 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6560 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6561 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6562 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6563 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6564 "#"
6565 ""
6566 [(pc)]
6567 "
6568 {
6569 rtx lowword, highword;
6570 gcc_assert (MEM_P (operands[4]));
6571 highword = adjust_address (operands[4], SImode, 0);
6572 lowword = adjust_address (operands[4], SImode, 4);
6573 if (! WORDS_BIG_ENDIAN)
6574 {
6575 rtx tmp;
6576 tmp = highword; highword = lowword; lowword = tmp;
6577 }
6579 emit_move_insn (lowword, operands[1]);
6580 emit_move_insn (highword, operands[2]);
6581 emit_move_insn (operands[5], operands[4]);
6582 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6583 DONE;
6584 }"
6585 [(set_attr "length" "20")])
6587 (define_expand "fix_truncdfsi2"
6588 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
6589 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
6590 (clobber (match_dup 2))
6591 (clobber (match_dup 3))])]
6592 "(TARGET_POWER2 || TARGET_POWERPC)
6593 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6594 "
6595 {
6596 if (TARGET_E500_DOUBLE)
6597 {
6598 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
6599 DONE;
6600 }
6601 operands[2] = gen_reg_rtx (DImode);
6602 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6603 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
6604 {
6605 operands[3] = gen_reg_rtx (DImode);
6606 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
6607 operands[2], operands[3]));
6608 DONE;
6609 }
6610 if (TARGET_PPC_GFXOPT)
6611 {
6612 rtx orig_dest = operands[0];
6613 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
6614 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
6615 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
6616 operands[2]));
6617 if (operands[0] != orig_dest)
6618 emit_move_insn (orig_dest, operands[0]);
6619 DONE;
6620 }
6621 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6622 }")
6624 (define_insn_and_split "*fix_truncdfsi2_internal"
6625 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6626 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6627 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6628 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6629 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6630 && TARGET_DOUBLE_FLOAT"
6631 "#"
6632 ""
6633 [(pc)]
6634 "
6635 {
6636 rtx lowword;
6637 gcc_assert (MEM_P (operands[3]));
6638 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6640 emit_insn (gen_fctiwz (operands[2], operands[1]));
6641 emit_move_insn (operands[3], operands[2]);
6642 emit_move_insn (operands[0], lowword);
6643 DONE;
6644 }"
6645 [(set_attr "length" "16")])
6647 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6648 [(set (match_operand:SI 0 "memory_operand" "=Z")
6649 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6650 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))]
6651 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6652 && TARGET_DOUBLE_FLOAT
6653 && TARGET_PPC_GFXOPT"
6654 "#"
6655 "&& 1"
6656 [(pc)]
6657 "
6658 {
6659 emit_insn (gen_fctiwz (operands[2], operands[1]));
6660 emit_insn (gen_stfiwx (operands[0], operands[2]));
6661 DONE;
6662 }"
6663 [(set_attr "length" "16")])
6665 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6666 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6667 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6668 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6669 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6670 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6671 && TARGET_DOUBLE_FLOAT"
6672 "#"
6673 "&& 1"
6674 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6675 (set (match_dup 3) (match_dup 2))
6676 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6677 ""
6678 [(set_attr "length" "12")])
6680 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6681 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6682 ; because the first makes it clear that operand 0 is not live
6683 ; before the instruction.
6684 (define_insn "fctiwz"
6685 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6686 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))]
6687 UNSPEC_FCTIWZ))]
6688 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6689 && TARGET_DOUBLE_FLOAT"
6690 "{fcirz|fctiwz} %0,%1"
6691 [(set_attr "type" "fp")])
6693 (define_expand "btruncdf2"
6694 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6695 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIZ))]
6696 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6697 "")
6699 (define_insn "*btruncdf2_fpr"
6700 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6701 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6702 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6703 && !VECTOR_UNIT_VSX_P (DFmode)"
6704 "friz %0,%1"
6705 [(set_attr "type" "fp")])
6707 (define_insn "btruncsf2"
6708 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6709 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6710 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6711 "friz %0,%1"
6712 [(set_attr "type" "fp")])
6714 (define_expand "ceildf2"
6715 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6716 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIP))]
6717 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6718 "")
6720 (define_insn "*ceildf2_fpr"
6721 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6722 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIP))]
6723 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6724 && !VECTOR_UNIT_VSX_P (DFmode)"
6725 "frip %0,%1"
6726 [(set_attr "type" "fp")])
6728 (define_insn "ceilsf2"
6729 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6730 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6731 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6732 "frip %0,%1"
6733 [(set_attr "type" "fp")])
6735 (define_expand "floordf2"
6736 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6737 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIM))]
6738 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6739 "")
6741 (define_insn "*floordf2_fpr"
6742 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6743 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIM))]
6744 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6745 && !VECTOR_UNIT_VSX_P (DFmode)"
6746 "frim %0,%1"
6747 [(set_attr "type" "fp")])
6749 (define_insn "floorsf2"
6750 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6751 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6752 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6753 "frim %0,%1"
6754 [(set_attr "type" "fp")])
6756 ;; No VSX equivalent to frin
6757 (define_insn "rounddf2"
6758 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6759 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIN))]
6760 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6761 "frin %0,%1"
6762 [(set_attr "type" "fp")])
6764 (define_insn "roundsf2"
6765 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6766 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6767 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6768 "frin %0,%1"
6769 [(set_attr "type" "fp")])
6771 (define_expand "ftruncdf2"
6772 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6773 (fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6774 "VECTOR_UNIT_VSX_P (DFmode)"
6775 "")
6777 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6778 (define_insn "stfiwx"
6779 [(set (match_operand:SI 0 "memory_operand" "=Z")
6780 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6781 UNSPEC_STFIWX))]
6782 "TARGET_PPC_GFXOPT"
6783 "stfiwx %1,%y0"
6784 [(set_attr "type" "fpstore")])
6786 (define_expand "floatsisf2"
6787 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6788 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6789 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6790 "")
6792 (define_expand "floatdidf2"
6793 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6794 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6795 "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6796 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6797 "")
6799 (define_insn "*floatdidf2_fpr"
6800 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6801 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))]
6802 "(TARGET_POWERPC64 || TARGET_XILINX_FPU)
6803 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6804 && !VECTOR_UNIT_VSX_P (DFmode)"
6805 "fcfid %0,%1"
6806 [(set_attr "type" "fp")])
6808 (define_expand "floatunsdidf2"
6809 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6810 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6811 "TARGET_VSX"
6812 "")
6814 (define_expand "fix_truncdfdi2"
6815 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6816 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "")))]
6817 "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6818 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6819 "")
6821 (define_insn "*fix_truncdfdi2_fpr"
6822 [(set (match_operand:DI 0 "gpc_reg_operand" "=!d#r")
6823 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d")))]
6824 "(TARGET_POWERPC64 || TARGET_XILINX_FPU)
6825 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6826 && !VECTOR_UNIT_VSX_P (DFmode)"
6827 "fctidz %0,%1"
6828 [(set_attr "type" "fp")])
6830 (define_expand "floatdisf2"
6831 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6832 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6833 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6834 "
6835 {
6836 rtx val = operands[1];
6837 if (!flag_unsafe_math_optimizations)
6838 {
6839 rtx label = gen_label_rtx ();
6840 val = gen_reg_rtx (DImode);
6841 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6842 emit_label (label);
6843 }
6844 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6845 DONE;
6846 }")
6848 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6849 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6850 ;; from double rounding.
6851 (define_insn_and_split "floatdisf2_internal1"
6852 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6853 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))
6854 (clobber (match_scratch:DF 2 "=d"))]
6855 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6856 "#"
6857 "&& reload_completed"
6858 [(set (match_dup 2)
6859 (float:DF (match_dup 1)))
6860 (set (match_dup 0)
6861 (float_truncate:SF (match_dup 2)))]
6862 "")
6864 ;; Twiddles bits to avoid double rounding.
6865 ;; Bits that might be truncated when converting to DFmode are replaced
6866 ;; by a bit that won't be lost at that stage, but is below the SFmode
6867 ;; rounding position.
6868 (define_expand "floatdisf2_internal2"
6869 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6870 (const_int 53)))
6871 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6872 (const_int 2047)))
6873 (clobber (scratch:CC))])
6874 (set (match_dup 3) (plus:DI (match_dup 3)
6875 (const_int 1)))
6876 (set (match_dup 0) (plus:DI (match_dup 0)
6877 (const_int 2047)))
6878 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6879 (const_int 2)))
6880 (set (match_dup 0) (ior:DI (match_dup 0)
6881 (match_dup 1)))
6882 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6883 (const_int -2048)))
6884 (clobber (scratch:CC))])
6885 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6886 (label_ref (match_operand:DI 2 "" ""))
6887 (pc)))
6888 (set (match_dup 0) (match_dup 1))]
6889 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6890 "
6891 {
6892 operands[3] = gen_reg_rtx (DImode);
6893 operands[4] = gen_reg_rtx (CCUNSmode);
6894 }")
6895 \f
6896 ;; Define the DImode operations that can be done in a small number
6897 ;; of instructions. The & constraints are to prevent the register
6898 ;; allocator from allocating registers that overlap with the inputs
6899 ;; (for example, having an input in 7,8 and an output in 6,7). We
6900 ;; also allow for the output being the same as one of the inputs.
6902 (define_insn "*adddi3_noppc64"
6903 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6904 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6905 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6906 "! TARGET_POWERPC64"
6907 "*
6908 {
6909 if (WORDS_BIG_ENDIAN)
6910 return (GET_CODE (operands[2])) != CONST_INT
6911 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6912 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6913 else
6914 return (GET_CODE (operands[2])) != CONST_INT
6915 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6916 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6917 }"
6918 [(set_attr "type" "two")
6919 (set_attr "length" "8")])
6921 (define_insn "*subdi3_noppc64"
6922 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6923 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6924 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6925 "! TARGET_POWERPC64"
6926 "*
6927 {
6928 if (WORDS_BIG_ENDIAN)
6929 return (GET_CODE (operands[1]) != CONST_INT)
6930 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6931 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6932 else
6933 return (GET_CODE (operands[1]) != CONST_INT)
6934 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6935 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6936 }"
6937 [(set_attr "type" "two")
6938 (set_attr "length" "8")])
6940 (define_insn "*negdi2_noppc64"
6941 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6942 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6943 "! TARGET_POWERPC64"
6944 "*
6945 {
6946 return (WORDS_BIG_ENDIAN)
6947 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6948 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6949 }"
6950 [(set_attr "type" "two")
6951 (set_attr "length" "8")])
6953 (define_expand "mulsidi3"
6954 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6955 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6956 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6957 "! TARGET_POWERPC64"
6958 "
6959 {
6960 if (! TARGET_POWER && ! TARGET_POWERPC)
6961 {
6962 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6963 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6964 emit_insn (gen_mull_call ());
6965 if (WORDS_BIG_ENDIAN)
6966 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6967 else
6968 {
6969 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6970 gen_rtx_REG (SImode, 3));
6971 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6972 gen_rtx_REG (SImode, 4));
6973 }
6974 DONE;
6975 }
6976 else if (TARGET_POWER)
6977 {
6978 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6979 DONE;
6980 }
6981 }")
6983 (define_insn "mulsidi3_mq"
6984 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6985 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6986 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6987 (clobber (match_scratch:SI 3 "=q"))]
6988 "TARGET_POWER"
6989 "mul %0,%1,%2\;mfmq %L0"
6990 [(set_attr "type" "imul")
6991 (set_attr "length" "8")])
6993 (define_insn "*mulsidi3_no_mq"
6994 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6995 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6996 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6997 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6998 "*
6999 {
7000 return (WORDS_BIG_ENDIAN)
7001 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
7002 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
7003 }"
7004 [(set_attr "type" "imul")
7005 (set_attr "length" "8")])
7007 (define_split
7008 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7009 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7010 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7011 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7012 [(set (match_dup 3)
7013 (truncate:SI
7014 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
7015 (sign_extend:DI (match_dup 2)))
7016 (const_int 32))))
7017 (set (match_dup 4)
7018 (mult:SI (match_dup 1)
7019 (match_dup 2)))]
7020 "
7021 {
7022 int endian = (WORDS_BIG_ENDIAN == 0);
7023 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7024 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7025 }")
7027 (define_expand "umulsidi3"
7028 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7029 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7030 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7031 "TARGET_POWERPC && ! TARGET_POWERPC64"
7032 "
7033 {
7034 if (TARGET_POWER)
7035 {
7036 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
7037 DONE;
7038 }
7039 }")
7041 (define_insn "umulsidi3_mq"
7042 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7043 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7044 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7045 (clobber (match_scratch:SI 3 "=q"))]
7046 "TARGET_POWERPC && TARGET_POWER"
7047 "*
7048 {
7049 return (WORDS_BIG_ENDIAN)
7050 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7051 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7052 }"
7053 [(set_attr "type" "imul")
7054 (set_attr "length" "8")])
7056 (define_insn "*umulsidi3_no_mq"
7057 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7058 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7059 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7060 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7061 "*
7062 {
7063 return (WORDS_BIG_ENDIAN)
7064 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7065 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7066 }"
7067 [(set_attr "type" "imul")
7068 (set_attr "length" "8")])
7070 (define_split
7071 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7072 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7073 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7074 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7075 [(set (match_dup 3)
7076 (truncate:SI
7077 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
7078 (zero_extend:DI (match_dup 2)))
7079 (const_int 32))))
7080 (set (match_dup 4)
7081 (mult:SI (match_dup 1)
7082 (match_dup 2)))]
7083 "
7084 {
7085 int endian = (WORDS_BIG_ENDIAN == 0);
7086 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7087 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7088 }")
7090 (define_expand "smulsi3_highpart"
7091 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7092 (truncate:SI
7093 (lshiftrt:DI (mult:DI (sign_extend:DI
7094 (match_operand:SI 1 "gpc_reg_operand" ""))
7095 (sign_extend:DI
7096 (match_operand:SI 2 "gpc_reg_operand" "")))
7097 (const_int 32))))]
7098 ""
7099 "
7100 {
7101 if (! TARGET_POWER && ! TARGET_POWERPC)
7102 {
7103 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7104 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7105 emit_insn (gen_mulh_call ());
7106 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
7107 DONE;
7108 }
7109 else if (TARGET_POWER)
7110 {
7111 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7112 DONE;
7113 }
7114 }")
7116 (define_insn "smulsi3_highpart_mq"
7117 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7118 (truncate:SI
7119 (lshiftrt:DI (mult:DI (sign_extend:DI
7120 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7121 (sign_extend:DI
7122 (match_operand:SI 2 "gpc_reg_operand" "r")))
7123 (const_int 32))))
7124 (clobber (match_scratch:SI 3 "=q"))]
7125 "TARGET_POWER"
7126 "mul %0,%1,%2"
7127 [(set_attr "type" "imul")])
7129 (define_insn "*smulsi3_highpart_no_mq"
7130 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7131 (truncate:SI
7132 (lshiftrt:DI (mult:DI (sign_extend:DI
7133 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7134 (sign_extend:DI
7135 (match_operand:SI 2 "gpc_reg_operand" "r")))
7136 (const_int 32))))]
7137 "TARGET_POWERPC && ! TARGET_POWER"
7138 "mulhw %0,%1,%2"
7139 [(set_attr "type" "imul")])
7141 (define_expand "umulsi3_highpart"
7142 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7143 (truncate:SI
7144 (lshiftrt:DI (mult:DI (zero_extend:DI
7145 (match_operand:SI 1 "gpc_reg_operand" ""))
7146 (zero_extend:DI
7147 (match_operand:SI 2 "gpc_reg_operand" "")))
7148 (const_int 32))))]
7149 "TARGET_POWERPC"
7150 "
7151 {
7152 if (TARGET_POWER)
7153 {
7154 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7155 DONE;
7156 }
7157 }")
7159 (define_insn "umulsi3_highpart_mq"
7160 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7161 (truncate:SI
7162 (lshiftrt:DI (mult:DI (zero_extend:DI
7163 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7164 (zero_extend:DI
7165 (match_operand:SI 2 "gpc_reg_operand" "r")))
7166 (const_int 32))))
7167 (clobber (match_scratch:SI 3 "=q"))]
7168 "TARGET_POWERPC && TARGET_POWER"
7169 "mulhwu %0,%1,%2"
7170 [(set_attr "type" "imul")])
7172 (define_insn "*umulsi3_highpart_no_mq"
7173 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7174 (truncate:SI
7175 (lshiftrt:DI (mult:DI (zero_extend:DI
7176 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7177 (zero_extend:DI
7178 (match_operand:SI 2 "gpc_reg_operand" "r")))
7179 (const_int 32))))]
7180 "TARGET_POWERPC && ! TARGET_POWER"
7181 "mulhwu %0,%1,%2"
7182 [(set_attr "type" "imul")])
7184 ;; If operands 0 and 2 are in the same register, we have a problem. But
7185 ;; operands 0 and 1 (the usual case) can be in the same register. That's
7186 ;; why we have the strange constraints below.
7187 (define_insn "ashldi3_power"
7188 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7189 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7190 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7191 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7192 "TARGET_POWER"
7193 "@
7194 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
7195 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7196 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7197 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
7198 [(set_attr "length" "8")])
7200 (define_insn "lshrdi3_power"
7201 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7202 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7203 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7204 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7205 "TARGET_POWER"
7206 "@
7207 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
7208 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7209 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7210 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
7211 [(set_attr "length" "8")])
7213 ;; Shift by a variable amount is too complex to be worth open-coding. We
7214 ;; just handle shifts by constants.
7215 (define_insn "ashrdi3_power"
7216 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7217 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7218 (match_operand:SI 2 "const_int_operand" "M,i")))
7219 (clobber (match_scratch:SI 3 "=X,q"))]
7220 "TARGET_POWER"
7221 "@
7222 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7223 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
7224 [(set_attr "type" "shift")
7225 (set_attr "length" "8")])
7227 (define_insn "ashrdi3_no_power"
7228 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
7229 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7230 (match_operand:SI 2 "const_int_operand" "M,i")))]
7231 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
7232 "@
7233 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7234 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
7235 [(set_attr "type" "two,three")
7236 (set_attr "length" "8,12")])
7238 (define_insn "*ashrdisi3_noppc64"
7239 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7240 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7241 (const_int 32)) 4))]
7242 "TARGET_32BIT && !TARGET_POWERPC64"
7243 "*
7244 {
7245 if (REGNO (operands[0]) == REGNO (operands[1]))
7246 return \"\";
7247 else
7248 return \"mr %0,%1\";
7249 }"
7250 [(set_attr "length" "4")])
7252 \f
7253 ;; PowerPC64 DImode operations.
7255 (define_expand "absdi2"
7256 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7257 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
7258 "TARGET_POWERPC64"
7259 "
7260 {
7261 if (TARGET_ISEL)
7262 emit_insn (gen_absdi2_isel (operands[0], operands[1]));
7263 else
7264 emit_insn (gen_absdi2_internal (operands[0], operands[1]));
7265 DONE;
7266 }")
7268 (define_insn_and_split "absdi2_internal"
7269 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7270 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
7271 (clobber (match_scratch:DI 2 "=&r,&r"))]
7272 "TARGET_POWERPC64 && !TARGET_ISEL"
7273 "#"
7274 "&& reload_completed"
7275 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7276 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7277 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
7278 "")
7280 (define_insn_and_split "*nabsdi2"
7281 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7282 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
7283 (clobber (match_scratch:DI 2 "=&r,&r"))]
7284 "TARGET_POWERPC64 && !TARGET_ISEL"
7285 "#"
7286 "&& reload_completed"
7287 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7288 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7289 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7290 "")
7292 (define_insn "muldi3"
7293 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7294 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7295 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
7296 "TARGET_POWERPC64"
7297 "@
7298 mulld %0,%1,%2
7299 mulli %0,%1,%2"
7300 [(set (attr "type")
7301 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
7302 (const_string "imul3")
7303 (match_operand:SI 2 "short_cint_operand" "")
7304 (const_string "imul2")]
7305 (const_string "lmul")))])
7307 (define_insn "*muldi3_internal1"
7308 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7309 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7310 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7311 (const_int 0)))
7312 (clobber (match_scratch:DI 3 "=r,r"))]
7313 "TARGET_POWERPC64"
7314 "@
7315 mulld. %3,%1,%2
7316 #"
7317 [(set_attr "type" "lmul_compare")
7318 (set_attr "length" "4,8")])
7320 (define_split
7321 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7322 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7323 (match_operand:DI 2 "gpc_reg_operand" ""))
7324 (const_int 0)))
7325 (clobber (match_scratch:DI 3 ""))]
7326 "TARGET_POWERPC64 && reload_completed"
7327 [(set (match_dup 3)
7328 (mult:DI (match_dup 1) (match_dup 2)))
7329 (set (match_dup 0)
7330 (compare:CC (match_dup 3)
7331 (const_int 0)))]
7332 "")
7334 (define_insn "*muldi3_internal2"
7335 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7336 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7337 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7338 (const_int 0)))
7339 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7340 (mult:DI (match_dup 1) (match_dup 2)))]
7341 "TARGET_POWERPC64"
7342 "@
7343 mulld. %0,%1,%2
7344 #"
7345 [(set_attr "type" "lmul_compare")
7346 (set_attr "length" "4,8")])
7348 (define_split
7349 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7350 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7351 (match_operand:DI 2 "gpc_reg_operand" ""))
7352 (const_int 0)))
7353 (set (match_operand:DI 0 "gpc_reg_operand" "")
7354 (mult:DI (match_dup 1) (match_dup 2)))]
7355 "TARGET_POWERPC64 && reload_completed"
7356 [(set (match_dup 0)
7357 (mult:DI (match_dup 1) (match_dup 2)))
7358 (set (match_dup 3)
7359 (compare:CC (match_dup 0)
7360 (const_int 0)))]
7361 "")
7363 (define_insn "smuldi3_highpart"
7364 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7365 (truncate:DI
7366 (lshiftrt:TI (mult:TI (sign_extend:TI
7367 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7368 (sign_extend:TI
7369 (match_operand:DI 2 "gpc_reg_operand" "r")))
7370 (const_int 64))))]
7371 "TARGET_POWERPC64"
7372 "mulhd %0,%1,%2"
7373 [(set_attr "type" "lmul")])
7375 (define_insn "umuldi3_highpart"
7376 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7377 (truncate:DI
7378 (lshiftrt:TI (mult:TI (zero_extend:TI
7379 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7380 (zero_extend:TI
7381 (match_operand:DI 2 "gpc_reg_operand" "r")))
7382 (const_int 64))))]
7383 "TARGET_POWERPC64"
7384 "mulhdu %0,%1,%2"
7385 [(set_attr "type" "lmul")])
7387 (define_insn "rotldi3"
7388 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7389 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7390 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7391 "TARGET_POWERPC64"
7392 "@
7393 rldcl %0,%1,%2,0
7394 rldicl %0,%1,%H2,0"
7395 [(set_attr "type" "var_shift_rotate,integer")])
7397 (define_insn "*rotldi3_internal2"
7398 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7399 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7400 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7401 (const_int 0)))
7402 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7403 "TARGET_64BIT"
7404 "@
7405 rldcl. %3,%1,%2,0
7406 rldicl. %3,%1,%H2,0
7407 #
7408 #"
7409 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7410 (set_attr "length" "4,4,8,8")])
7412 (define_split
7413 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7414 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7415 (match_operand:DI 2 "reg_or_cint_operand" ""))
7416 (const_int 0)))
7417 (clobber (match_scratch:DI 3 ""))]
7418 "TARGET_POWERPC64 && reload_completed"
7419 [(set (match_dup 3)
7420 (rotate:DI (match_dup 1) (match_dup 2)))
7421 (set (match_dup 0)
7422 (compare:CC (match_dup 3)
7423 (const_int 0)))]
7424 "")
7426 (define_insn "*rotldi3_internal3"
7427 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7428 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7429 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7430 (const_int 0)))
7431 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7432 (rotate:DI (match_dup 1) (match_dup 2)))]
7433 "TARGET_64BIT"
7434 "@
7435 rldcl. %0,%1,%2,0
7436 rldicl. %0,%1,%H2,0
7437 #
7438 #"
7439 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7440 (set_attr "length" "4,4,8,8")])
7442 (define_split
7443 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7444 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7445 (match_operand:DI 2 "reg_or_cint_operand" ""))
7446 (const_int 0)))
7447 (set (match_operand:DI 0 "gpc_reg_operand" "")
7448 (rotate:DI (match_dup 1) (match_dup 2)))]
7449 "TARGET_POWERPC64 && reload_completed"
7450 [(set (match_dup 0)
7451 (rotate:DI (match_dup 1) (match_dup 2)))
7452 (set (match_dup 3)
7453 (compare:CC (match_dup 0)
7454 (const_int 0)))]
7455 "")
7457 (define_insn "*rotldi3_internal4"
7458 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7459 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7460 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7461 (match_operand:DI 3 "mask64_operand" "n,n")))]
7462 "TARGET_POWERPC64"
7463 "@
7464 rldc%B3 %0,%1,%2,%S3
7465 rldic%B3 %0,%1,%H2,%S3"
7466 [(set_attr "type" "var_shift_rotate,integer")])
7468 (define_insn "*rotldi3_internal5"
7469 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7470 (compare:CC (and:DI
7471 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7472 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7473 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7474 (const_int 0)))
7475 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7476 "TARGET_64BIT"
7477 "@
7478 rldc%B3. %4,%1,%2,%S3
7479 rldic%B3. %4,%1,%H2,%S3
7480 #
7481 #"
7482 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7483 (set_attr "length" "4,4,8,8")])
7485 (define_split
7486 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7487 (compare:CC (and:DI
7488 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7489 (match_operand:DI 2 "reg_or_cint_operand" ""))
7490 (match_operand:DI 3 "mask64_operand" ""))
7491 (const_int 0)))
7492 (clobber (match_scratch:DI 4 ""))]
7493 "TARGET_POWERPC64 && reload_completed"
7494 [(set (match_dup 4)
7495 (and:DI (rotate:DI (match_dup 1)
7496 (match_dup 2))
7497 (match_dup 3)))
7498 (set (match_dup 0)
7499 (compare:CC (match_dup 4)
7500 (const_int 0)))]
7501 "")
7503 (define_insn "*rotldi3_internal6"
7504 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
7505 (compare:CC (and:DI
7506 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7507 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7508 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7509 (const_int 0)))
7510 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7511 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7512 "TARGET_64BIT"
7513 "@
7514 rldc%B3. %0,%1,%2,%S3
7515 rldic%B3. %0,%1,%H2,%S3
7516 #
7517 #"
7518 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7519 (set_attr "length" "4,4,8,8")])
7521 (define_split
7522 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7523 (compare:CC (and:DI
7524 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7525 (match_operand:DI 2 "reg_or_cint_operand" ""))
7526 (match_operand:DI 3 "mask64_operand" ""))
7527 (const_int 0)))
7528 (set (match_operand:DI 0 "gpc_reg_operand" "")
7529 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7530 "TARGET_POWERPC64 && reload_completed"
7531 [(set (match_dup 0)
7532 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7533 (set (match_dup 4)
7534 (compare:CC (match_dup 0)
7535 (const_int 0)))]
7536 "")
7538 (define_insn "*rotldi3_internal7"
7539 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7540 (zero_extend:DI
7541 (subreg:QI
7542 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7543 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7544 "TARGET_POWERPC64"
7545 "@
7546 rldcl %0,%1,%2,56
7547 rldicl %0,%1,%H2,56"
7548 [(set_attr "type" "var_shift_rotate,integer")])
7550 (define_insn "*rotldi3_internal8"
7551 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7552 (compare:CC (zero_extend:DI
7553 (subreg:QI
7554 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7555 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7556 (const_int 0)))
7557 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7558 "TARGET_64BIT"
7559 "@
7560 rldcl. %3,%1,%2,56
7561 rldicl. %3,%1,%H2,56
7562 #
7563 #"
7564 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7565 (set_attr "length" "4,4,8,8")])
7567 (define_split
7568 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7569 (compare:CC (zero_extend:DI
7570 (subreg:QI
7571 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7572 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7573 (const_int 0)))
7574 (clobber (match_scratch:DI 3 ""))]
7575 "TARGET_POWERPC64 && reload_completed"
7576 [(set (match_dup 3)
7577 (zero_extend:DI (subreg:QI
7578 (rotate:DI (match_dup 1)
7579 (match_dup 2)) 0)))
7580 (set (match_dup 0)
7581 (compare:CC (match_dup 3)
7582 (const_int 0)))]
7583 "")
7585 (define_insn "*rotldi3_internal9"
7586 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7587 (compare:CC (zero_extend:DI
7588 (subreg:QI
7589 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7590 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7591 (const_int 0)))
7592 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7593 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7594 "TARGET_64BIT"
7595 "@
7596 rldcl. %0,%1,%2,56
7597 rldicl. %0,%1,%H2,56
7598 #
7599 #"
7600 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7601 (set_attr "length" "4,4,8,8")])
7603 (define_split
7604 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7605 (compare:CC (zero_extend:DI
7606 (subreg:QI
7607 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7608 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7609 (const_int 0)))
7610 (set (match_operand:DI 0 "gpc_reg_operand" "")
7611 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7612 "TARGET_POWERPC64 && reload_completed"
7613 [(set (match_dup 0)
7614 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7615 (set (match_dup 3)
7616 (compare:CC (match_dup 0)
7617 (const_int 0)))]
7618 "")
7620 (define_insn "*rotldi3_internal10"
7621 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7622 (zero_extend:DI
7623 (subreg:HI
7624 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7625 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7626 "TARGET_POWERPC64"
7627 "@
7628 rldcl %0,%1,%2,48
7629 rldicl %0,%1,%H2,48"
7630 [(set_attr "type" "var_shift_rotate,integer")])
7632 (define_insn "*rotldi3_internal11"
7633 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7634 (compare:CC (zero_extend:DI
7635 (subreg:HI
7636 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7637 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7638 (const_int 0)))
7639 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7640 "TARGET_64BIT"
7641 "@
7642 rldcl. %3,%1,%2,48
7643 rldicl. %3,%1,%H2,48
7644 #
7645 #"
7646 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7647 (set_attr "length" "4,4,8,8")])
7649 (define_split
7650 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7651 (compare:CC (zero_extend:DI
7652 (subreg:HI
7653 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7654 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7655 (const_int 0)))
7656 (clobber (match_scratch:DI 3 ""))]
7657 "TARGET_POWERPC64 && reload_completed"
7658 [(set (match_dup 3)
7659 (zero_extend:DI (subreg:HI
7660 (rotate:DI (match_dup 1)
7661 (match_dup 2)) 0)))
7662 (set (match_dup 0)
7663 (compare:CC (match_dup 3)
7664 (const_int 0)))]
7665 "")
7667 (define_insn "*rotldi3_internal12"
7668 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7669 (compare:CC (zero_extend:DI
7670 (subreg:HI
7671 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7672 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7673 (const_int 0)))
7674 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7675 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7676 "TARGET_64BIT"
7677 "@
7678 rldcl. %0,%1,%2,48
7679 rldicl. %0,%1,%H2,48
7680 #
7681 #"
7682 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7683 (set_attr "length" "4,4,8,8")])
7685 (define_split
7686 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7687 (compare:CC (zero_extend:DI
7688 (subreg:HI
7689 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7690 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7691 (const_int 0)))
7692 (set (match_operand:DI 0 "gpc_reg_operand" "")
7693 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7694 "TARGET_POWERPC64 && reload_completed"
7695 [(set (match_dup 0)
7696 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7697 (set (match_dup 3)
7698 (compare:CC (match_dup 0)
7699 (const_int 0)))]
7700 "")
7702 (define_insn "*rotldi3_internal13"
7703 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7704 (zero_extend:DI
7705 (subreg:SI
7706 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7707 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7708 "TARGET_POWERPC64"
7709 "@
7710 rldcl %0,%1,%2,32
7711 rldicl %0,%1,%H2,32"
7712 [(set_attr "type" "var_shift_rotate,integer")])
7714 (define_insn "*rotldi3_internal14"
7715 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7716 (compare:CC (zero_extend:DI
7717 (subreg:SI
7718 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7719 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7720 (const_int 0)))
7721 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7722 "TARGET_64BIT"
7723 "@
7724 rldcl. %3,%1,%2,32
7725 rldicl. %3,%1,%H2,32
7726 #
7727 #"
7728 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7729 (set_attr "length" "4,4,8,8")])
7731 (define_split
7732 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7733 (compare:CC (zero_extend:DI
7734 (subreg:SI
7735 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7736 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7737 (const_int 0)))
7738 (clobber (match_scratch:DI 3 ""))]
7739 "TARGET_POWERPC64 && reload_completed"
7740 [(set (match_dup 3)
7741 (zero_extend:DI (subreg:SI
7742 (rotate:DI (match_dup 1)
7743 (match_dup 2)) 0)))
7744 (set (match_dup 0)
7745 (compare:CC (match_dup 3)
7746 (const_int 0)))]
7747 "")
7749 (define_insn "*rotldi3_internal15"
7750 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7751 (compare:CC (zero_extend:DI
7752 (subreg:SI
7753 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7754 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7755 (const_int 0)))
7756 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7757 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7758 "TARGET_64BIT"
7759 "@
7760 rldcl. %0,%1,%2,32
7761 rldicl. %0,%1,%H2,32
7762 #
7763 #"
7764 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7765 (set_attr "length" "4,4,8,8")])
7767 (define_split
7768 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7769 (compare:CC (zero_extend:DI
7770 (subreg:SI
7771 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7772 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7773 (const_int 0)))
7774 (set (match_operand:DI 0 "gpc_reg_operand" "")
7775 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7776 "TARGET_POWERPC64 && reload_completed"
7777 [(set (match_dup 0)
7778 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7779 (set (match_dup 3)
7780 (compare:CC (match_dup 0)
7781 (const_int 0)))]
7782 "")
7784 (define_expand "ashldi3"
7785 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7786 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7787 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7788 "TARGET_POWERPC64 || TARGET_POWER"
7789 "
7790 {
7791 if (TARGET_POWERPC64)
7792 ;
7793 else if (TARGET_POWER)
7794 {
7795 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7796 DONE;
7797 }
7798 else
7799 FAIL;
7800 }")
7802 (define_insn "*ashldi3_internal1"
7803 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7804 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7805 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7806 "TARGET_POWERPC64"
7807 "@
7808 sld %0,%1,%2
7809 sldi %0,%1,%H2"
7810 [(set_attr "type" "var_shift_rotate,shift")])
7812 (define_insn "*ashldi3_internal2"
7813 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7814 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7815 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7816 (const_int 0)))
7817 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7818 "TARGET_64BIT"
7819 "@
7820 sld. %3,%1,%2
7821 sldi. %3,%1,%H2
7822 #
7823 #"
7824 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7825 (set_attr "length" "4,4,8,8")])
7827 (define_split
7828 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7829 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7830 (match_operand:SI 2 "reg_or_cint_operand" ""))
7831 (const_int 0)))
7832 (clobber (match_scratch:DI 3 ""))]
7833 "TARGET_POWERPC64 && reload_completed"
7834 [(set (match_dup 3)
7835 (ashift:DI (match_dup 1) (match_dup 2)))
7836 (set (match_dup 0)
7837 (compare:CC (match_dup 3)
7838 (const_int 0)))]
7839 "")
7841 (define_insn "*ashldi3_internal3"
7842 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7843 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7844 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7845 (const_int 0)))
7846 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7847 (ashift:DI (match_dup 1) (match_dup 2)))]
7848 "TARGET_64BIT"
7849 "@
7850 sld. %0,%1,%2
7851 sldi. %0,%1,%H2
7852 #
7853 #"
7854 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7855 (set_attr "length" "4,4,8,8")])
7857 (define_split
7858 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7859 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7860 (match_operand:SI 2 "reg_or_cint_operand" ""))
7861 (const_int 0)))
7862 (set (match_operand:DI 0 "gpc_reg_operand" "")
7863 (ashift:DI (match_dup 1) (match_dup 2)))]
7864 "TARGET_POWERPC64 && reload_completed"
7865 [(set (match_dup 0)
7866 (ashift:DI (match_dup 1) (match_dup 2)))
7867 (set (match_dup 3)
7868 (compare:CC (match_dup 0)
7869 (const_int 0)))]
7870 "")
7872 (define_insn "*ashldi3_internal4"
7873 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7874 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7875 (match_operand:SI 2 "const_int_operand" "i"))
7876 (match_operand:DI 3 "const_int_operand" "n")))]
7877 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7878 "rldic %0,%1,%H2,%W3")
7880 (define_insn "ashldi3_internal5"
7881 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7882 (compare:CC
7883 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7884 (match_operand:SI 2 "const_int_operand" "i,i"))
7885 (match_operand:DI 3 "const_int_operand" "n,n"))
7886 (const_int 0)))
7887 (clobber (match_scratch:DI 4 "=r,r"))]
7888 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7889 "@
7890 rldic. %4,%1,%H2,%W3
7891 #"
7892 [(set_attr "type" "compare")
7893 (set_attr "length" "4,8")])
7895 (define_split
7896 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7897 (compare:CC
7898 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7899 (match_operand:SI 2 "const_int_operand" ""))
7900 (match_operand:DI 3 "const_int_operand" ""))
7901 (const_int 0)))
7902 (clobber (match_scratch:DI 4 ""))]
7903 "TARGET_POWERPC64 && reload_completed
7904 && includes_rldic_lshift_p (operands[2], operands[3])"
7905 [(set (match_dup 4)
7906 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7907 (match_dup 3)))
7908 (set (match_dup 0)
7909 (compare:CC (match_dup 4)
7910 (const_int 0)))]
7911 "")
7913 (define_insn "*ashldi3_internal6"
7914 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7915 (compare:CC
7916 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7917 (match_operand:SI 2 "const_int_operand" "i,i"))
7918 (match_operand:DI 3 "const_int_operand" "n,n"))
7919 (const_int 0)))
7920 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7921 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7922 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7923 "@
7924 rldic. %0,%1,%H2,%W3
7925 #"
7926 [(set_attr "type" "compare")
7927 (set_attr "length" "4,8")])
7929 (define_split
7930 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7931 (compare:CC
7932 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7933 (match_operand:SI 2 "const_int_operand" ""))
7934 (match_operand:DI 3 "const_int_operand" ""))
7935 (const_int 0)))
7936 (set (match_operand:DI 0 "gpc_reg_operand" "")
7937 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7938 "TARGET_POWERPC64 && reload_completed
7939 && includes_rldic_lshift_p (operands[2], operands[3])"
7940 [(set (match_dup 0)
7941 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7942 (match_dup 3)))
7943 (set (match_dup 4)
7944 (compare:CC (match_dup 0)
7945 (const_int 0)))]
7946 "")
7948 (define_insn "*ashldi3_internal7"
7949 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7950 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7951 (match_operand:SI 2 "const_int_operand" "i"))
7952 (match_operand:DI 3 "mask64_operand" "n")))]
7953 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7954 "rldicr %0,%1,%H2,%S3")
7956 (define_insn "ashldi3_internal8"
7957 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7958 (compare:CC
7959 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7960 (match_operand:SI 2 "const_int_operand" "i,i"))
7961 (match_operand:DI 3 "mask64_operand" "n,n"))
7962 (const_int 0)))
7963 (clobber (match_scratch:DI 4 "=r,r"))]
7964 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7965 "@
7966 rldicr. %4,%1,%H2,%S3
7967 #"
7968 [(set_attr "type" "compare")
7969 (set_attr "length" "4,8")])
7971 (define_split
7972 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7973 (compare:CC
7974 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7975 (match_operand:SI 2 "const_int_operand" ""))
7976 (match_operand:DI 3 "mask64_operand" ""))
7977 (const_int 0)))
7978 (clobber (match_scratch:DI 4 ""))]
7979 "TARGET_POWERPC64 && reload_completed
7980 && includes_rldicr_lshift_p (operands[2], operands[3])"
7981 [(set (match_dup 4)
7982 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7983 (match_dup 3)))
7984 (set (match_dup 0)
7985 (compare:CC (match_dup 4)
7986 (const_int 0)))]
7987 "")
7989 (define_insn "*ashldi3_internal9"
7990 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7991 (compare:CC
7992 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7993 (match_operand:SI 2 "const_int_operand" "i,i"))
7994 (match_operand:DI 3 "mask64_operand" "n,n"))
7995 (const_int 0)))
7996 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7997 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7998 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7999 "@
8000 rldicr. %0,%1,%H2,%S3
8001 #"
8002 [(set_attr "type" "compare")
8003 (set_attr "length" "4,8")])
8005 (define_split
8006 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8007 (compare:CC
8008 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8009 (match_operand:SI 2 "const_int_operand" ""))
8010 (match_operand:DI 3 "mask64_operand" ""))
8011 (const_int 0)))
8012 (set (match_operand:DI 0 "gpc_reg_operand" "")
8013 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8014 "TARGET_POWERPC64 && reload_completed
8015 && includes_rldicr_lshift_p (operands[2], operands[3])"
8016 [(set (match_dup 0)
8017 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8018 (match_dup 3)))
8019 (set (match_dup 4)
8020 (compare:CC (match_dup 0)
8021 (const_int 0)))]
8022 "")
8024 (define_expand "lshrdi3"
8025 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8026 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8027 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8028 "TARGET_POWERPC64 || TARGET_POWER"
8029 "
8030 {
8031 if (TARGET_POWERPC64)
8032 ;
8033 else if (TARGET_POWER)
8034 {
8035 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
8036 DONE;
8037 }
8038 else
8039 FAIL;
8040 }")
8042 (define_insn "*lshrdi3_internal1"
8043 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8044 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8045 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8046 "TARGET_POWERPC64"
8047 "@
8048 srd %0,%1,%2
8049 srdi %0,%1,%H2"
8050 [(set_attr "type" "var_shift_rotate,shift")])
8052 (define_insn "*lshrdi3_internal2"
8053 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8054 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8055 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8056 (const_int 0)))
8057 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8058 "TARGET_64BIT "
8059 "@
8060 srd. %3,%1,%2
8061 srdi. %3,%1,%H2
8062 #
8063 #"
8064 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8065 (set_attr "length" "4,4,8,8")])
8067 (define_split
8068 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8069 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8070 (match_operand:SI 2 "reg_or_cint_operand" ""))
8071 (const_int 0)))
8072 (clobber (match_scratch:DI 3 ""))]
8073 "TARGET_POWERPC64 && reload_completed"
8074 [(set (match_dup 3)
8075 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8076 (set (match_dup 0)
8077 (compare:CC (match_dup 3)
8078 (const_int 0)))]
8079 "")
8081 (define_insn "*lshrdi3_internal3"
8082 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8083 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8084 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8085 (const_int 0)))
8086 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8087 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8088 "TARGET_64BIT"
8089 "@
8090 srd. %0,%1,%2
8091 srdi. %0,%1,%H2
8092 #
8093 #"
8094 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8095 (set_attr "length" "4,4,8,8")])
8097 (define_split
8098 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8099 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8100 (match_operand:SI 2 "reg_or_cint_operand" ""))
8101 (const_int 0)))
8102 (set (match_operand:DI 0 "gpc_reg_operand" "")
8103 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8104 "TARGET_POWERPC64 && reload_completed"
8105 [(set (match_dup 0)
8106 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8107 (set (match_dup 3)
8108 (compare:CC (match_dup 0)
8109 (const_int 0)))]
8110 "")
8112 (define_expand "ashrdi3"
8113 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8114 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8115 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8116 "WORDS_BIG_ENDIAN"
8117 "
8118 {
8119 if (TARGET_POWERPC64)
8120 ;
8121 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
8122 {
8123 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
8124 DONE;
8125 }
8126 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
8127 && WORDS_BIG_ENDIAN)
8128 {
8129 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
8130 DONE;
8131 }
8132 else
8133 FAIL;
8134 }")
8136 (define_insn "*ashrdi3_internal1"
8137 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8138 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8139 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8140 "TARGET_POWERPC64"
8141 "@
8142 srad %0,%1,%2
8143 sradi %0,%1,%H2"
8144 [(set_attr "type" "var_shift_rotate,shift")])
8146 (define_insn "*ashrdi3_internal2"
8147 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8148 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8149 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8150 (const_int 0)))
8151 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8152 "TARGET_64BIT"
8153 "@
8154 srad. %3,%1,%2
8155 sradi. %3,%1,%H2
8156 #
8157 #"
8158 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8159 (set_attr "length" "4,4,8,8")])
8161 (define_split
8162 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8163 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8164 (match_operand:SI 2 "reg_or_cint_operand" ""))
8165 (const_int 0)))
8166 (clobber (match_scratch:DI 3 ""))]
8167 "TARGET_POWERPC64 && reload_completed"
8168 [(set (match_dup 3)
8169 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8170 (set (match_dup 0)
8171 (compare:CC (match_dup 3)
8172 (const_int 0)))]
8173 "")
8175 (define_insn "*ashrdi3_internal3"
8176 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8177 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8178 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8179 (const_int 0)))
8180 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8181 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8182 "TARGET_64BIT"
8183 "@
8184 srad. %0,%1,%2
8185 sradi. %0,%1,%H2
8186 #
8187 #"
8188 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8189 (set_attr "length" "4,4,8,8")])
8191 (define_split
8192 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8193 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8194 (match_operand:SI 2 "reg_or_cint_operand" ""))
8195 (const_int 0)))
8196 (set (match_operand:DI 0 "gpc_reg_operand" "")
8197 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8198 "TARGET_POWERPC64 && reload_completed"
8199 [(set (match_dup 0)
8200 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8201 (set (match_dup 3)
8202 (compare:CC (match_dup 0)
8203 (const_int 0)))]
8204 "")
8206 (define_expand "anddi3"
8207 [(parallel
8208 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8209 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8210 (match_operand:DI 2 "and64_2_operand" "")))
8211 (clobber (match_scratch:CC 3 ""))])]
8212 "TARGET_POWERPC64"
8213 "")
8215 (define_insn "anddi3_mc"
8216 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8217 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8218 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8219 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8220 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8221 "@
8222 and %0,%1,%2
8223 rldic%B2 %0,%1,0,%S2
8224 rlwinm %0,%1,0,%m2,%M2
8225 andi. %0,%1,%b2
8226 andis. %0,%1,%u2
8227 #"
8228 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8229 (set_attr "length" "4,4,4,4,4,8")])
8231 (define_insn "anddi3_nomc"
8232 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8233 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8234 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8235 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8236 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8237 "@
8238 and %0,%1,%2
8239 rldic%B2 %0,%1,0,%S2
8240 rlwinm %0,%1,0,%m2,%M2
8241 #"
8242 [(set_attr "length" "4,4,4,8")])
8244 (define_split
8245 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8246 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8247 (match_operand:DI 2 "mask64_2_operand" "")))
8248 (clobber (match_scratch:CC 3 ""))]
8249 "TARGET_POWERPC64
8250 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8251 && !mask_operand (operands[2], DImode)
8252 && !mask64_operand (operands[2], DImode)"
8253 [(set (match_dup 0)
8254 (and:DI (rotate:DI (match_dup 1)
8255 (match_dup 4))
8256 (match_dup 5)))
8257 (set (match_dup 0)
8258 (and:DI (rotate:DI (match_dup 0)
8259 (match_dup 6))
8260 (match_dup 7)))]
8261 {
8262 build_mask64_2_operands (operands[2], &operands[4]);
8263 })
8265 (define_insn "*anddi3_internal2_mc"
8266 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8267 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8268 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8269 (const_int 0)))
8270 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8271 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8272 "TARGET_64BIT && rs6000_gen_cell_microcode"
8273 "@
8274 and. %3,%1,%2
8275 rldic%B2. %3,%1,0,%S2
8276 rlwinm. %3,%1,0,%m2,%M2
8277 andi. %3,%1,%b2
8278 andis. %3,%1,%u2
8279 #
8280 #
8281 #
8282 #
8283 #
8284 #
8285 #"
8286 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8287 fast_compare,compare,compare,compare,compare,compare,\
8288 compare,compare")
8289 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8291 (define_split
8292 [(set (match_operand:CC 0 "cc_reg_operand" "")
8293 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8294 (match_operand:DI 2 "mask64_2_operand" ""))
8295 (const_int 0)))
8296 (clobber (match_scratch:DI 3 ""))
8297 (clobber (match_scratch:CC 4 ""))]
8298 "TARGET_64BIT && reload_completed
8299 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8300 && !mask_operand (operands[2], DImode)
8301 && !mask64_operand (operands[2], DImode)"
8302 [(set (match_dup 3)
8303 (and:DI (rotate:DI (match_dup 1)
8304 (match_dup 5))
8305 (match_dup 6)))
8306 (parallel [(set (match_dup 0)
8307 (compare:CC (and:DI (rotate:DI (match_dup 3)
8308 (match_dup 7))
8309 (match_dup 8))
8310 (const_int 0)))
8311 (clobber (match_dup 3))])]
8312 "
8313 {
8314 build_mask64_2_operands (operands[2], &operands[5]);
8315 }")
8317 (define_insn "*anddi3_internal3_mc"
8318 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8319 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8320 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8321 (const_int 0)))
8322 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8323 (and:DI (match_dup 1) (match_dup 2)))
8324 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8325 "TARGET_64BIT && rs6000_gen_cell_microcode"
8326 "@
8327 and. %0,%1,%2
8328 rldic%B2. %0,%1,0,%S2
8329 rlwinm. %0,%1,0,%m2,%M2
8330 andi. %0,%1,%b2
8331 andis. %0,%1,%u2
8332 #
8333 #
8334 #
8335 #
8336 #
8337 #
8338 #"
8339 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8340 fast_compare,compare,compare,compare,compare,compare,\
8341 compare,compare")
8342 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8344 (define_split
8345 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8346 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8347 (match_operand:DI 2 "and64_2_operand" ""))
8348 (const_int 0)))
8349 (set (match_operand:DI 0 "gpc_reg_operand" "")
8350 (and:DI (match_dup 1) (match_dup 2)))
8351 (clobber (match_scratch:CC 4 ""))]
8352 "TARGET_64BIT && reload_completed"
8353 [(parallel [(set (match_dup 0)
8354 (and:DI (match_dup 1) (match_dup 2)))
8355 (clobber (match_dup 4))])
8356 (set (match_dup 3)
8357 (compare:CC (match_dup 0)
8358 (const_int 0)))]
8359 "")
8361 (define_split
8362 [(set (match_operand:CC 3 "cc_reg_operand" "")
8363 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8364 (match_operand:DI 2 "mask64_2_operand" ""))
8365 (const_int 0)))
8366 (set (match_operand:DI 0 "gpc_reg_operand" "")
8367 (and:DI (match_dup 1) (match_dup 2)))
8368 (clobber (match_scratch:CC 4 ""))]
8369 "TARGET_64BIT && reload_completed
8370 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8371 && !mask_operand (operands[2], DImode)
8372 && !mask64_operand (operands[2], DImode)"
8373 [(set (match_dup 0)
8374 (and:DI (rotate:DI (match_dup 1)
8375 (match_dup 5))
8376 (match_dup 6)))
8377 (parallel [(set (match_dup 3)
8378 (compare:CC (and:DI (rotate:DI (match_dup 0)
8379 (match_dup 7))
8380 (match_dup 8))
8381 (const_int 0)))
8382 (set (match_dup 0)
8383 (and:DI (rotate:DI (match_dup 0)
8384 (match_dup 7))
8385 (match_dup 8)))])]
8386 "
8387 {
8388 build_mask64_2_operands (operands[2], &operands[5]);
8389 }")
8391 (define_expand "iordi3"
8392 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8393 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8394 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8395 "TARGET_POWERPC64"
8396 "
8397 {
8398 if (non_logical_cint_operand (operands[2], DImode))
8399 {
8400 HOST_WIDE_INT value;
8401 rtx tmp = ((!can_create_pseudo_p ()
8402 || rtx_equal_p (operands[0], operands[1]))
8403 ? operands[0] : gen_reg_rtx (DImode));
8405 if (GET_CODE (operands[2]) == CONST_INT)
8406 {
8407 value = INTVAL (operands[2]);
8408 emit_insn (gen_iordi3 (tmp, operands[1],
8409 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8410 }
8411 else
8412 {
8413 value = CONST_DOUBLE_LOW (operands[2]);
8414 emit_insn (gen_iordi3 (tmp, operands[1],
8415 immed_double_const (value
8416 & (~ (HOST_WIDE_INT) 0xffff),
8417 0, DImode)));
8418 }
8420 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8421 DONE;
8422 }
8423 }")
8425 (define_expand "xordi3"
8426 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8427 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8428 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8429 "TARGET_POWERPC64"
8430 "
8431 {
8432 if (non_logical_cint_operand (operands[2], DImode))
8433 {
8434 HOST_WIDE_INT value;
8435 rtx tmp = ((!can_create_pseudo_p ()
8436 || rtx_equal_p (operands[0], operands[1]))
8437 ? operands[0] : gen_reg_rtx (DImode));
8439 if (GET_CODE (operands[2]) == CONST_INT)
8440 {
8441 value = INTVAL (operands[2]);
8442 emit_insn (gen_xordi3 (tmp, operands[1],
8443 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8444 }
8445 else
8446 {
8447 value = CONST_DOUBLE_LOW (operands[2]);
8448 emit_insn (gen_xordi3 (tmp, operands[1],
8449 immed_double_const (value
8450 & (~ (HOST_WIDE_INT) 0xffff),
8451 0, DImode)));
8452 }
8454 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8455 DONE;
8456 }
8457 }")
8459 (define_insn "*booldi3_internal1"
8460 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8461 (match_operator:DI 3 "boolean_or_operator"
8462 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8463 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8464 "TARGET_POWERPC64"
8465 "@
8466 %q3 %0,%1,%2
8467 %q3i %0,%1,%b2
8468 %q3is %0,%1,%u2")
8470 (define_insn "*booldi3_internal2"
8471 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8472 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8473 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8474 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8475 (const_int 0)))
8476 (clobber (match_scratch:DI 3 "=r,r"))]
8477 "TARGET_64BIT"
8478 "@
8479 %q4. %3,%1,%2
8480 #"
8481 [(set_attr "type" "fast_compare,compare")
8482 (set_attr "length" "4,8")])
8484 (define_split
8485 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8486 (compare:CC (match_operator:DI 4 "boolean_operator"
8487 [(match_operand:DI 1 "gpc_reg_operand" "")
8488 (match_operand:DI 2 "gpc_reg_operand" "")])
8489 (const_int 0)))
8490 (clobber (match_scratch:DI 3 ""))]
8491 "TARGET_POWERPC64 && reload_completed"
8492 [(set (match_dup 3) (match_dup 4))
8493 (set (match_dup 0)
8494 (compare:CC (match_dup 3)
8495 (const_int 0)))]
8496 "")
8498 (define_insn "*booldi3_internal3"
8499 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8500 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8501 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8502 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8503 (const_int 0)))
8504 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8505 (match_dup 4))]
8506 "TARGET_64BIT"
8507 "@
8508 %q4. %0,%1,%2
8509 #"
8510 [(set_attr "type" "fast_compare,compare")
8511 (set_attr "length" "4,8")])
8513 (define_split
8514 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8515 (compare:CC (match_operator:DI 4 "boolean_operator"
8516 [(match_operand:DI 1 "gpc_reg_operand" "")
8517 (match_operand:DI 2 "gpc_reg_operand" "")])
8518 (const_int 0)))
8519 (set (match_operand:DI 0 "gpc_reg_operand" "")
8520 (match_dup 4))]
8521 "TARGET_POWERPC64 && reload_completed"
8522 [(set (match_dup 0) (match_dup 4))
8523 (set (match_dup 3)
8524 (compare:CC (match_dup 0)
8525 (const_int 0)))]
8526 "")
8528 ;; Split a logical operation that we can't do in one insn into two insns,
8529 ;; each of which does one 16-bit part. This is used by combine.
8531 (define_split
8532 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8533 (match_operator:DI 3 "boolean_or_operator"
8534 [(match_operand:DI 1 "gpc_reg_operand" "")
8535 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8536 "TARGET_POWERPC64"
8537 [(set (match_dup 0) (match_dup 4))
8538 (set (match_dup 0) (match_dup 5))]
8539 "
8540 {
8541 rtx i3,i4;
8543 if (GET_CODE (operands[2]) == CONST_DOUBLE)
8544 {
8545 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
8546 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
8547 0, DImode);
8548 i4 = GEN_INT (value & 0xffff);
8549 }
8550 else
8551 {
8552 i3 = GEN_INT (INTVAL (operands[2])
8553 & (~ (HOST_WIDE_INT) 0xffff));
8554 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8555 }
8556 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8557 operands[1], i3);
8558 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8559 operands[0], i4);
8560 }")
8562 (define_insn "*boolcdi3_internal1"
8563 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8564 (match_operator:DI 3 "boolean_operator"
8565 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8566 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8567 "TARGET_POWERPC64"
8568 "%q3 %0,%2,%1")
8570 (define_insn "*boolcdi3_internal2"
8571 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8572 (compare:CC (match_operator:DI 4 "boolean_operator"
8573 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8574 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8575 (const_int 0)))
8576 (clobber (match_scratch:DI 3 "=r,r"))]
8577 "TARGET_64BIT"
8578 "@
8579 %q4. %3,%2,%1
8580 #"
8581 [(set_attr "type" "fast_compare,compare")
8582 (set_attr "length" "4,8")])
8584 (define_split
8585 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8586 (compare:CC (match_operator:DI 4 "boolean_operator"
8587 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8588 (match_operand:DI 2 "gpc_reg_operand" "")])
8589 (const_int 0)))
8590 (clobber (match_scratch:DI 3 ""))]
8591 "TARGET_POWERPC64 && reload_completed"
8592 [(set (match_dup 3) (match_dup 4))
8593 (set (match_dup 0)
8594 (compare:CC (match_dup 3)
8595 (const_int 0)))]
8596 "")
8598 (define_insn "*boolcdi3_internal3"
8599 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8600 (compare:CC (match_operator:DI 4 "boolean_operator"
8601 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8602 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8603 (const_int 0)))
8604 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8605 (match_dup 4))]
8606 "TARGET_64BIT"
8607 "@
8608 %q4. %0,%2,%1
8609 #"
8610 [(set_attr "type" "fast_compare,compare")
8611 (set_attr "length" "4,8")])
8613 (define_split
8614 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8615 (compare:CC (match_operator:DI 4 "boolean_operator"
8616 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8617 (match_operand:DI 2 "gpc_reg_operand" "")])
8618 (const_int 0)))
8619 (set (match_operand:DI 0 "gpc_reg_operand" "")
8620 (match_dup 4))]
8621 "TARGET_POWERPC64 && reload_completed"
8622 [(set (match_dup 0) (match_dup 4))
8623 (set (match_dup 3)
8624 (compare:CC (match_dup 0)
8625 (const_int 0)))]
8626 "")
8628 (define_insn "*boolccdi3_internal1"
8629 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8630 (match_operator:DI 3 "boolean_operator"
8631 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8632 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8633 "TARGET_POWERPC64"
8634 "%q3 %0,%1,%2")
8636 (define_insn "*boolccdi3_internal2"
8637 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8638 (compare:CC (match_operator:DI 4 "boolean_operator"
8639 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8640 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8641 (const_int 0)))
8642 (clobber (match_scratch:DI 3 "=r,r"))]
8643 "TARGET_64BIT"
8644 "@
8645 %q4. %3,%1,%2
8646 #"
8647 [(set_attr "type" "fast_compare,compare")
8648 (set_attr "length" "4,8")])
8650 (define_split
8651 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8652 (compare:CC (match_operator:DI 4 "boolean_operator"
8653 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8654 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8655 (const_int 0)))
8656 (clobber (match_scratch:DI 3 ""))]
8657 "TARGET_POWERPC64 && reload_completed"
8658 [(set (match_dup 3) (match_dup 4))
8659 (set (match_dup 0)
8660 (compare:CC (match_dup 3)
8661 (const_int 0)))]
8662 "")
8664 (define_insn "*boolccdi3_internal3"
8665 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8666 (compare:CC (match_operator:DI 4 "boolean_operator"
8667 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8668 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8669 (const_int 0)))
8670 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8671 (match_dup 4))]
8672 "TARGET_64BIT"
8673 "@
8674 %q4. %0,%1,%2
8675 #"
8676 [(set_attr "type" "fast_compare,compare")
8677 (set_attr "length" "4,8")])
8679 (define_split
8680 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8681 (compare:CC (match_operator:DI 4 "boolean_operator"
8682 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8683 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8684 (const_int 0)))
8685 (set (match_operand:DI 0 "gpc_reg_operand" "")
8686 (match_dup 4))]
8687 "TARGET_POWERPC64 && reload_completed"
8688 [(set (match_dup 0) (match_dup 4))
8689 (set (match_dup 3)
8690 (compare:CC (match_dup 0)
8691 (const_int 0)))]
8692 "")
8694 (define_expand "smindi3"
8695 [(match_operand:DI 0 "gpc_reg_operand" "")
8696 (match_operand:DI 1 "gpc_reg_operand" "")
8697 (match_operand:DI 2 "gpc_reg_operand" "")]
8698 "TARGET_ISEL64"
8699 "
8700 {
8701 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
8702 DONE;
8703 }")
8705 (define_expand "smaxdi3"
8706 [(match_operand:DI 0 "gpc_reg_operand" "")
8707 (match_operand:DI 1 "gpc_reg_operand" "")
8708 (match_operand:DI 2 "gpc_reg_operand" "")]
8709 "TARGET_ISEL64"
8710 "
8711 {
8712 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
8713 DONE;
8714 }")
8716 (define_expand "umindi3"
8717 [(match_operand:DI 0 "gpc_reg_operand" "")
8718 (match_operand:DI 1 "gpc_reg_operand" "")
8719 (match_operand:DI 2 "gpc_reg_operand" "")]
8720 "TARGET_ISEL64"
8721 "
8722 {
8723 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
8724 DONE;
8725 }")
8727 (define_expand "umaxdi3"
8728 [(match_operand:DI 0 "gpc_reg_operand" "")
8729 (match_operand:DI 1 "gpc_reg_operand" "")
8730 (match_operand:DI 2 "gpc_reg_operand" "")]
8731 "TARGET_ISEL64"
8732 "
8733 {
8734 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
8735 DONE;
8736 }")
8738 \f
8739 ;; Now define ways of moving data around.
8741 ;; Set up a register with a value from the GOT table
8743 (define_expand "movsi_got"
8744 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8745 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8746 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8747 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8748 "
8749 {
8750 if (GET_CODE (operands[1]) == CONST)
8751 {
8752 rtx offset = const0_rtx;
8753 HOST_WIDE_INT value;
8755 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8756 value = INTVAL (offset);
8757 if (value != 0)
8758 {
8759 rtx tmp = (!can_create_pseudo_p ()
8760 ? operands[0]
8761 : gen_reg_rtx (Pmode));
8762 emit_insn (gen_movsi_got (tmp, operands[1]));
8763 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8764 DONE;
8765 }
8766 }
8768 operands[2] = rs6000_got_register (operands[1]);
8769 }")
8771 (define_insn "*movsi_got_internal"
8772 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8773 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8774 (match_operand:SI 2 "gpc_reg_operand" "b")]
8775 UNSPEC_MOVSI_GOT))]
8776 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8777 "{l|lwz} %0,%a1@got(%2)"
8778 [(set_attr "type" "load")])
8780 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8781 ;; didn't get allocated to a hard register.
8782 (define_split
8783 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8784 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8785 (match_operand:SI 2 "memory_operand" "")]
8786 UNSPEC_MOVSI_GOT))]
8787 "DEFAULT_ABI == ABI_V4
8788 && flag_pic == 1
8789 && (reload_in_progress || reload_completed)"
8790 [(set (match_dup 0) (match_dup 2))
8791 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8792 UNSPEC_MOVSI_GOT))]
8793 "")
8795 ;; For SI, we special-case integers that can't be loaded in one insn. We
8796 ;; do the load 16-bits at a time. We could do this by loading from memory,
8797 ;; and this is even supposed to be faster, but it is simpler not to get
8798 ;; integers in the TOC.
8799 (define_insn "movsi_low"
8800 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8801 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8802 (match_operand 2 "" ""))))]
8803 "TARGET_MACHO && ! TARGET_64BIT"
8804 "{l|lwz} %0,lo16(%2)(%1)"
8805 [(set_attr "type" "load")
8806 (set_attr "length" "4")])
8808 (define_insn "*movsi_internal1"
8809 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8810 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8811 "!TARGET_SINGLE_FPU &&
8812 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8813 "@
8814 mr %0,%1
8815 {cal|la} %0,%a1
8816 {l%U1%X1|lwz%U1%X1} %0,%1
8817 {st%U0%X0|stw%U0%X0} %1,%0
8818 {lil|li} %0,%1
8819 {liu|lis} %0,%v1
8820 #
8821 {cal|la} %0,%a1
8822 mf%1 %0
8823 mt%0 %1
8824 mt%0 %1
8825 mt%0 %1
8826 {cror 0,0,0|nop}"
8827 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8828 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8830 (define_insn "*movsi_internal1_single"
8831 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
8832 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
8833 "TARGET_SINGLE_FPU &&
8834 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8835 "@
8836 mr %0,%1
8837 {cal|la} %0,%a1
8838 {l%U1%X1|lwz%U1%X1} %0,%1
8839 {st%U0%X0|stw%U0%X0} %1,%0
8840 {lil|li} %0,%1
8841 {liu|lis} %0,%v1
8842 #
8843 {cal|la} %0,%a1
8844 mf%1 %0
8845 mt%0 %1
8846 mt%0 %1
8847 mt%0 %1
8848 {cror 0,0,0|nop}
8849 stfs%U0%X0 %1, %0
8850 lfs%U1%X1 %0, %1"
8851 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
8852 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
8854 ;; Split a load of a large constant into the appropriate two-insn
8855 ;; sequence.
8857 (define_split
8858 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8859 (match_operand:SI 1 "const_int_operand" ""))]
8860 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8861 && (INTVAL (operands[1]) & 0xffff) != 0"
8862 [(set (match_dup 0)
8863 (match_dup 2))
8864 (set (match_dup 0)
8865 (ior:SI (match_dup 0)
8866 (match_dup 3)))]
8867 "
8868 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8870 if (tem == operands[0])
8871 DONE;
8872 else
8873 FAIL;
8874 }")
8876 (define_insn "*mov<mode>_internal2"
8877 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8878 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8879 (const_int 0)))
8880 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8881 ""
8882 "@
8883 {cmpi|cmp<wd>i} %2,%0,0
8884 mr. %0,%1
8885 #"
8886 [(set_attr "type" "cmp,compare,cmp")
8887 (set_attr "length" "4,4,8")])
8889 (define_split
8890 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8891 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8892 (const_int 0)))
8893 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8894 "reload_completed"
8895 [(set (match_dup 0) (match_dup 1))
8896 (set (match_dup 2)
8897 (compare:CC (match_dup 0)
8898 (const_int 0)))]
8899 "")
8900 \f
8901 (define_insn "*movhi_internal"
8902 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8903 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8904 "gpc_reg_operand (operands[0], HImode)
8905 || gpc_reg_operand (operands[1], HImode)"
8906 "@
8907 mr %0,%1
8908 lhz%U1%X1 %0,%1
8909 sth%U0%X0 %1,%0
8910 {lil|li} %0,%w1
8911 mf%1 %0
8912 mt%0 %1
8913 mt%0 %1
8914 {cror 0,0,0|nop}"
8915 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8917 (define_expand "mov<mode>"
8918 [(set (match_operand:INT 0 "general_operand" "")
8919 (match_operand:INT 1 "any_operand" ""))]
8920 ""
8921 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8923 (define_insn "*movqi_internal"
8924 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8925 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8926 "gpc_reg_operand (operands[0], QImode)
8927 || gpc_reg_operand (operands[1], QImode)"
8928 "@
8929 mr %0,%1
8930 lbz%U1%X1 %0,%1
8931 stb%U0%X0 %1,%0
8932 {lil|li} %0,%1
8933 mf%1 %0
8934 mt%0 %1
8935 mt%0 %1
8936 {cror 0,0,0|nop}"
8937 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8938 \f
8939 ;; Here is how to move condition codes around. When we store CC data in
8940 ;; an integer register or memory, we store just the high-order 4 bits.
8941 ;; This lets us not shift in the most common case of CR0.
8942 (define_expand "movcc"
8943 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8944 (match_operand:CC 1 "nonimmediate_operand" ""))]
8945 ""
8946 "")
8948 (define_insn "*movcc_internal1"
8949 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8950 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8951 "register_operand (operands[0], CCmode)
8952 || register_operand (operands[1], CCmode)"
8953 "@
8954 mcrf %0,%1
8955 mtcrf 128,%1
8956 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8957 crxor %0,%0,%0
8958 mfcr %0%Q1
8959 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8960 mr %0,%1
8961 {lil|li} %0,%1
8962 mf%1 %0
8963 mt%0 %1
8964 mt%0 %1
8965 {l%U1%X1|lwz%U1%X1} %0,%1
8966 {st%U0%U1|stw%U0%U1} %1,%0"
8967 [(set (attr "type")
8968 (cond [(eq_attr "alternative" "0,3")
8969 (const_string "cr_logical")
8970 (eq_attr "alternative" "1,2")
8971 (const_string "mtcr")
8972 (eq_attr "alternative" "6,7,9")
8973 (const_string "integer")
8974 (eq_attr "alternative" "8")
8975 (const_string "mfjmpr")
8976 (eq_attr "alternative" "10")
8977 (const_string "mtjmpr")
8978 (eq_attr "alternative" "11")
8979 (const_string "load")
8980 (eq_attr "alternative" "12")
8981 (const_string "store")
8982 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8983 (const_string "mfcrf")
8984 ]
8985 (const_string "mfcr")))
8986 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8987 \f
8988 ;; For floating-point, we normally deal with the floating-point registers
8989 ;; unless -msoft-float is used. The sole exception is that parameter passing
8990 ;; can produce floating-point values in fixed-point registers. Unless the
8991 ;; value is a simple constant or already in memory, we deal with this by
8992 ;; allocating memory and copying the value explicitly via that memory location.
8993 (define_expand "movsf"
8994 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8995 (match_operand:SF 1 "any_operand" ""))]
8996 ""
8997 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8999 (define_split
9000 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9001 (match_operand:SF 1 "const_double_operand" ""))]
9002 "reload_completed
9003 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9004 || (GET_CODE (operands[0]) == SUBREG
9005 && GET_CODE (SUBREG_REG (operands[0])) == REG
9006 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9007 [(set (match_dup 2) (match_dup 3))]
9008 "
9009 {
9010 long l;
9011 REAL_VALUE_TYPE rv;
9013 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9014 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
9016 if (! TARGET_POWERPC64)
9017 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
9018 else
9019 operands[2] = gen_lowpart (SImode, operands[0]);
9021 operands[3] = gen_int_mode (l, SImode);
9022 }")
9024 (define_insn "*movsf_hardfloat"
9025 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
9026 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
9027 "(gpc_reg_operand (operands[0], SFmode)
9028 || gpc_reg_operand (operands[1], SFmode))
9029 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9030 "@
9031 mr %0,%1
9032 {l%U1%X1|lwz%U1%X1} %0,%1
9033 {st%U0%X0|stw%U0%X0} %1,%0
9034 fmr %0,%1
9035 lfs%U1%X1 %0,%1
9036 stfs%U0%X0 %1,%0
9037 mt%0 %1
9038 mt%0 %1
9039 mf%1 %0
9040 {cror 0,0,0|nop}
9041 #
9042 #"
9043 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
9044 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
9046 (define_insn "*movsf_softfloat"
9047 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
9048 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
9049 "(gpc_reg_operand (operands[0], SFmode)
9050 || gpc_reg_operand (operands[1], SFmode))
9051 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9052 "@
9053 mr %0,%1
9054 mt%0 %1
9055 mt%0 %1
9056 mf%1 %0
9057 {l%U1%X1|lwz%U1%X1} %0,%1
9058 {st%U0%X0|stw%U0%X0} %1,%0
9059 {lil|li} %0,%1
9060 {liu|lis} %0,%v1
9061 {cal|la} %0,%a1
9062 #
9063 #
9064 {cror 0,0,0|nop}"
9065 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
9066 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
9068 \f
9069 (define_expand "movdf"
9070 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9071 (match_operand:DF 1 "any_operand" ""))]
9072 ""
9073 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
9075 (define_split
9076 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9077 (match_operand:DF 1 "const_int_operand" ""))]
9078 "! TARGET_POWERPC64 && reload_completed
9079 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9080 || (GET_CODE (operands[0]) == SUBREG
9081 && GET_CODE (SUBREG_REG (operands[0])) == REG
9082 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9083 [(set (match_dup 2) (match_dup 4))
9084 (set (match_dup 3) (match_dup 1))]
9085 "
9086 {
9087 int endian = (WORDS_BIG_ENDIAN == 0);
9088 HOST_WIDE_INT value = INTVAL (operands[1]);
9090 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9091 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9092 #if HOST_BITS_PER_WIDE_INT == 32
9093 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9094 #else
9095 operands[4] = GEN_INT (value >> 32);
9096 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9097 #endif
9098 }")
9100 (define_split
9101 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9102 (match_operand:DF 1 "const_double_operand" ""))]
9103 "! TARGET_POWERPC64 && reload_completed
9104 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9105 || (GET_CODE (operands[0]) == SUBREG
9106 && GET_CODE (SUBREG_REG (operands[0])) == REG
9107 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9108 [(set (match_dup 2) (match_dup 4))
9109 (set (match_dup 3) (match_dup 5))]
9110 "
9111 {
9112 int endian = (WORDS_BIG_ENDIAN == 0);
9113 long l[2];
9114 REAL_VALUE_TYPE rv;
9116 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9117 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9119 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9120 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9121 operands[4] = gen_int_mode (l[endian], SImode);
9122 operands[5] = gen_int_mode (l[1 - endian], SImode);
9123 }")
9125 (define_split
9126 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9127 (match_operand:DF 1 "const_double_operand" ""))]
9128 "TARGET_POWERPC64 && reload_completed
9129 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9130 || (GET_CODE (operands[0]) == SUBREG
9131 && GET_CODE (SUBREG_REG (operands[0])) == REG
9132 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9133 [(set (match_dup 2) (match_dup 3))]
9134 "
9135 {
9136 int endian = (WORDS_BIG_ENDIAN == 0);
9137 long l[2];
9138 REAL_VALUE_TYPE rv;
9139 #if HOST_BITS_PER_WIDE_INT >= 64
9140 HOST_WIDE_INT val;
9141 #endif
9143 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9144 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9146 operands[2] = gen_lowpart (DImode, operands[0]);
9147 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9148 #if HOST_BITS_PER_WIDE_INT >= 64
9149 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9150 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9152 operands[3] = gen_int_mode (val, DImode);
9153 #else
9154 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
9155 #endif
9156 }")
9158 ;; Don't have reload use general registers to load a constant. First,
9159 ;; it might not work if the output operand is the equivalent of
9160 ;; a non-offsettable memref, but also it is less efficient than loading
9161 ;; the constant into an FP register, since it will probably be used there.
9162 ;; The "??" is a kludge until we can figure out a more reasonable way
9163 ;; of handling these non-offsettable values.
9164 (define_insn "*movdf_hardfloat32"
9165 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
9166 (match_operand:DF 1 "input_operand" "r,m,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
9167 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9168 && (gpc_reg_operand (operands[0], DFmode)
9169 || gpc_reg_operand (operands[1], DFmode))"
9170 "*
9171 {
9172 switch (which_alternative)
9173 {
9174 default:
9175 gcc_unreachable ();
9176 case 0:
9177 case 1:
9178 case 2:
9179 return \"#\";
9180 case 3:
9181 case 4:
9182 return \"xxlor %x0,%x1,%x1\";
9183 case 5:
9184 case 6:
9185 return \"lxsd%U1x %x0,%y1\";
9186 case 7:
9187 case 8:
9188 return \"stxsd%U0x %x1,%y0\";
9189 case 9:
9190 return \"fmr %0,%1\";
9191 case 10:
9192 return \"lfd%U1%X1 %0,%1\";
9193 case 11:
9194 return \"stfd%U0%X0 %1,%0\";
9195 case 12:
9196 return \"xxlxor %x0,%x0,%x0\";
9197 case 13:
9198 case 14:
9199 case 15:
9200 return \"#\";
9201 }
9202 }"
9203 [(set_attr "type" "two,load,store,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
9204 (set_attr "length" "8,16,16,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9206 (define_insn "*movdf_softfloat32"
9207 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
9208 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
9209 "! TARGET_POWERPC64
9210 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9211 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9212 && (gpc_reg_operand (operands[0], DFmode)
9213 || gpc_reg_operand (operands[1], DFmode))"
9214 "#"
9215 [(set_attr "type" "two,load,store,*,*,*")
9216 (set_attr "length" "8,8,8,8,12,16")])
9218 ; ld/std require word-aligned displacements -> 'Y' constraint.
9219 ; List Y->r and r->Y before r->r for reload.
9220 (define_insn "*movdf_hardfloat64_mfpgpr"
9221 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r,r,d")
9222 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
9223 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9224 && TARGET_DOUBLE_FLOAT
9225 && (gpc_reg_operand (operands[0], DFmode)
9226 || gpc_reg_operand (operands[1], DFmode))"
9227 "@
9228 std%U0%X0 %1,%0
9229 ld%U1%X1 %0,%1
9230 mr %0,%1
9231 xxlor %x0,%x1,%x1
9232 xxlor %x0,%x1,%x1
9233 lxsd%U1x %x0,%y1
9234 lxsd%U1x %x0,%y1
9235 stxsd%U0x %x1,%y0
9236 stxsd%U0x %x1,%y0
9237 fmr %0,%1
9238 lfd%U1%X1 %0,%1
9239 stfd%U0%X0 %1,%0
9240 xxlxor %x0,%x0,%x0
9241 mt%0 %1
9242 mf%1 %0
9243 {cror 0,0,0|nop}
9244 #
9245 #
9246 #
9247 mftgpr %0,%1
9248 mffgpr %0,%1"
9249 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
9250 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9252 ; ld/std require word-aligned displacements -> 'Y' constraint.
9253 ; List Y->r and r->Y before r->r for reload.
9254 (define_insn "*movdf_hardfloat64"
9255 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r")
9256 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
9257 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9258 && TARGET_DOUBLE_FLOAT
9259 && (gpc_reg_operand (operands[0], DFmode)
9260 || gpc_reg_operand (operands[1], DFmode))"
9261 "@
9262 std%U0%X0 %1,%0
9263 ld%U1%X1 %0,%1
9264 mr %0,%1
9265 xxlor %x0,%x1,%x1
9266 xxlor %x0,%x1,%x1
9267 lxsd%U1x %x0,%y1
9268 lxsd%U1x %x0,%y1
9269 stxsd%U0x %x1,%y0
9270 stxsd%U0x %x1,%y0
9271 fmr %0,%1
9272 lfd%U1%X1 %0,%1
9273 stfd%U0%X0 %1,%0
9274 xxlxor %x0,%x0,%x0
9275 mt%0 %1
9276 mf%1 %0
9277 {cror 0,0,0|nop}
9278 #
9279 #
9280 #"
9281 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
9282 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9284 (define_insn "*movdf_softfloat64"
9285 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
9286 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
9287 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9288 && (gpc_reg_operand (operands[0], DFmode)
9289 || gpc_reg_operand (operands[1], DFmode))"
9290 "@
9291 ld%U1%X1 %0,%1
9292 std%U0%X0 %1,%0
9293 mr %0,%1
9294 mt%0 %1
9295 mf%1 %0
9296 #
9297 #
9298 #
9299 {cror 0,0,0|nop}"
9300 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
9301 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9302 \f
9303 (define_expand "movtf"
9304 [(set (match_operand:TF 0 "general_operand" "")
9305 (match_operand:TF 1 "any_operand" ""))]
9306 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
9307 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
9309 ; It's important to list the o->f and f->o moves before f->f because
9310 ; otherwise reload, given m->f, will try to pick f->f and reload it,
9311 ; which doesn't make progress. Likewise r->Y must be before r->r.
9312 (define_insn_and_split "*movtf_internal"
9313 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
9314 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
9315 "!TARGET_IEEEQUAD
9316 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
9317 && (gpc_reg_operand (operands[0], TFmode)
9318 || gpc_reg_operand (operands[1], TFmode))"
9319 "#"
9320 "&& reload_completed"
9321 [(pc)]
9322 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9323 [(set_attr "length" "8,8,8,20,20,16")])
9325 (define_insn_and_split "*movtf_softfloat"
9326 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
9327 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
9328 "!TARGET_IEEEQUAD
9329 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
9330 && (gpc_reg_operand (operands[0], TFmode)
9331 || gpc_reg_operand (operands[1], TFmode))"
9332 "#"
9333 "&& reload_completed"
9334 [(pc)]
9335 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9336 [(set_attr "length" "20,20,16")])
9338 (define_expand "extenddftf2"
9339 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9340 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9341 "!TARGET_IEEEQUAD
9342 && TARGET_HARD_FLOAT
9343 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9344 && TARGET_LONG_DOUBLE_128"
9345 {
9346 if (TARGET_E500_DOUBLE)
9347 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9348 else
9349 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9350 DONE;
9351 })
9353 (define_expand "extenddftf2_fprs"
9354 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9355 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9356 (use (match_dup 2))])]
9357 "!TARGET_IEEEQUAD
9358 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9359 && TARGET_LONG_DOUBLE_128"
9360 {
9361 operands[2] = CONST0_RTX (DFmode);
9362 /* Generate GOT reference early for SVR4 PIC. */
9363 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9364 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9365 })
9367 (define_insn_and_split "*extenddftf2_internal"
9368 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
9369 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
9370 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
9371 "!TARGET_IEEEQUAD
9372 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9373 && TARGET_LONG_DOUBLE_128"
9374 "#"
9375 "&& reload_completed"
9376 [(pc)]
9377 {
9378 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9379 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9380 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9381 operands[1]);
9382 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9383 operands[2]);
9384 DONE;
9385 })
9387 (define_expand "extendsftf2"
9388 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9389 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9390 "!TARGET_IEEEQUAD
9391 && TARGET_HARD_FLOAT
9392 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9393 && TARGET_LONG_DOUBLE_128"
9394 {
9395 rtx tmp = gen_reg_rtx (DFmode);
9396 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9397 emit_insn (gen_extenddftf2 (operands[0], tmp));
9398 DONE;
9399 })
9401 (define_expand "trunctfdf2"
9402 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9403 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9404 "!TARGET_IEEEQUAD
9405 && TARGET_HARD_FLOAT
9406 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9407 && TARGET_LONG_DOUBLE_128"
9408 "")
9410 (define_insn_and_split "trunctfdf2_internal1"
9411 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9412 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9413 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9414 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9415 "@
9416 #
9417 fmr %0,%1"
9418 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9419 [(const_int 0)]
9420 {
9421 emit_note (NOTE_INSN_DELETED);
9422 DONE;
9423 }
9424 [(set_attr "type" "fp")])
9426 (define_insn "trunctfdf2_internal2"
9427 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9428 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9429 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9430 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9431 && TARGET_LONG_DOUBLE_128"
9432 "fadd %0,%1,%L1"
9433 [(set_attr "type" "fp")
9434 (set_attr "fp_type" "fp_addsub_d")])
9436 (define_expand "trunctfsf2"
9437 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9438 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9439 "!TARGET_IEEEQUAD
9440 && TARGET_HARD_FLOAT
9441 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9442 && TARGET_LONG_DOUBLE_128"
9443 {
9444 if (TARGET_E500_DOUBLE)
9445 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9446 else
9447 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9448 DONE;
9449 })
9451 (define_insn_and_split "trunctfsf2_fprs"
9452 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9453 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9454 (clobber (match_scratch:DF 2 "=d"))]
9455 "!TARGET_IEEEQUAD
9456 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9457 && TARGET_LONG_DOUBLE_128"
9458 "#"
9459 "&& reload_completed"
9460 [(set (match_dup 2)
9461 (float_truncate:DF (match_dup 1)))
9462 (set (match_dup 0)
9463 (float_truncate:SF (match_dup 2)))]
9464 "")
9466 (define_expand "floatsitf2"
9467 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9468 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9469 "!TARGET_IEEEQUAD
9470 && TARGET_HARD_FLOAT
9471 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9472 && TARGET_LONG_DOUBLE_128"
9473 {
9474 rtx tmp = gen_reg_rtx (DFmode);
9475 expand_float (tmp, operands[1], false);
9476 emit_insn (gen_extenddftf2 (operands[0], tmp));
9477 DONE;
9478 })
9480 ; fadd, but rounding towards zero.
9481 ; This is probably not the optimal code sequence.
9482 (define_insn "fix_trunc_helper"
9483 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9484 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9485 UNSPEC_FIX_TRUNC_TF))
9486 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9487 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9488 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9489 [(set_attr "type" "fp")
9490 (set_attr "length" "20")])
9492 (define_expand "fix_trunctfsi2"
9493 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9494 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9495 "!TARGET_IEEEQUAD
9496 && (TARGET_POWER2 || TARGET_POWERPC)
9497 && TARGET_HARD_FLOAT
9498 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9499 && TARGET_LONG_DOUBLE_128"
9500 {
9501 if (TARGET_E500_DOUBLE)
9502 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9503 else
9504 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9505 DONE;
9506 })
9508 (define_expand "fix_trunctfsi2_fprs"
9509 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9510 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9511 (clobber (match_dup 2))
9512 (clobber (match_dup 3))
9513 (clobber (match_dup 4))
9514 (clobber (match_dup 5))])]
9515 "!TARGET_IEEEQUAD
9516 && (TARGET_POWER2 || TARGET_POWERPC)
9517 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9518 {
9519 operands[2] = gen_reg_rtx (DFmode);
9520 operands[3] = gen_reg_rtx (DFmode);
9521 operands[4] = gen_reg_rtx (DImode);
9522 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
9523 })
9525 (define_insn_and_split "*fix_trunctfsi2_internal"
9526 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9527 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9528 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9529 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9530 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9531 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9532 "!TARGET_IEEEQUAD
9533 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9534 "#"
9535 ""
9536 [(pc)]
9537 {
9538 rtx lowword;
9539 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9541 gcc_assert (MEM_P (operands[5]));
9542 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9544 emit_insn (gen_fctiwz (operands[4], operands[2]));
9545 emit_move_insn (operands[5], operands[4]);
9546 emit_move_insn (operands[0], lowword);
9547 DONE;
9548 })
9550 (define_expand "negtf2"
9551 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9552 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9553 "!TARGET_IEEEQUAD
9554 && TARGET_HARD_FLOAT
9555 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9556 && TARGET_LONG_DOUBLE_128"
9557 "")
9559 (define_insn "negtf2_internal"
9560 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9561 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9562 "!TARGET_IEEEQUAD
9563 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9564 "*
9565 {
9566 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9567 return \"fneg %L0,%L1\;fneg %0,%1\";
9568 else
9569 return \"fneg %0,%1\;fneg %L0,%L1\";
9570 }"
9571 [(set_attr "type" "fp")
9572 (set_attr "length" "8")])
9574 (define_expand "abstf2"
9575 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9576 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9577 "!TARGET_IEEEQUAD
9578 && TARGET_HARD_FLOAT
9579 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9580 && TARGET_LONG_DOUBLE_128"
9581 "
9582 {
9583 rtx label = gen_label_rtx ();
9584 if (TARGET_E500_DOUBLE)
9585 {
9586 if (flag_finite_math_only && !flag_trapping_math)
9587 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9588 else
9589 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9590 }
9591 else
9592 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9593 emit_label (label);
9594 DONE;
9595 }")
9597 (define_expand "abstf2_internal"
9598 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9599 (match_operand:TF 1 "gpc_reg_operand" ""))
9600 (set (match_dup 3) (match_dup 5))
9601 (set (match_dup 5) (abs:DF (match_dup 5)))
9602 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9603 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9604 (label_ref (match_operand 2 "" ""))
9605 (pc)))
9606 (set (match_dup 6) (neg:DF (match_dup 6)))]
9607 "!TARGET_IEEEQUAD
9608 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9609 && TARGET_LONG_DOUBLE_128"
9610 "
9611 {
9612 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9613 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9614 operands[3] = gen_reg_rtx (DFmode);
9615 operands[4] = gen_reg_rtx (CCFPmode);
9616 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9617 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9618 }")
9619 \f
9620 ;; Next come the multi-word integer load and store and the load and store
9621 ;; multiple insns.
9623 ; List r->r after r->"o<>", otherwise reload will try to reload a
9624 ; non-offsettable address by using r->r which won't make progress.
9625 (define_insn "*movdi_internal32"
9626 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r")
9627 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
9628 "! TARGET_POWERPC64
9629 && (gpc_reg_operand (operands[0], DImode)
9630 || gpc_reg_operand (operands[1], DImode))"
9631 "@
9632 #
9633 #
9634 #
9635 fmr %0,%1
9636 lfd%U1%X1 %0,%1
9637 stfd%U0%X0 %1,%0
9638 #"
9639 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
9641 (define_split
9642 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9643 (match_operand:DI 1 "const_int_operand" ""))]
9644 "! TARGET_POWERPC64 && reload_completed"
9645 [(set (match_dup 2) (match_dup 4))
9646 (set (match_dup 3) (match_dup 1))]
9647 "
9648 {
9649 HOST_WIDE_INT value = INTVAL (operands[1]);
9650 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9651 DImode);
9652 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9653 DImode);
9654 #if HOST_BITS_PER_WIDE_INT == 32
9655 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9656 #else
9657 operands[4] = GEN_INT (value >> 32);
9658 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9659 #endif
9660 }")
9662 (define_split
9663 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
9664 (match_operand:DIFD 1 "input_operand" ""))]
9665 "reload_completed && !TARGET_POWERPC64
9666 && gpr_or_gpr_p (operands[0], operands[1])"
9667 [(pc)]
9668 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9670 (define_insn "*movdi_mfpgpr"
9671 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
9672 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
9673 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9674 && (gpc_reg_operand (operands[0], DImode)
9675 || gpc_reg_operand (operands[1], DImode))"
9676 "@
9677 mr %0,%1
9678 ld%U1%X1 %0,%1
9679 std%U0%X0 %1,%0
9680 li %0,%1
9681 lis %0,%v1
9682 #
9683 {cal|la} %0,%a1
9684 fmr %0,%1
9685 lfd%U1%X1 %0,%1
9686 stfd%U0%X0 %1,%0
9687 mf%1 %0
9688 mt%0 %1
9689 {cror 0,0,0|nop}
9690 mftgpr %0,%1
9691 mffgpr %0,%1"
9692 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9693 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9695 (define_insn "*movdi_internal64"
9696 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
9697 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
9698 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9699 && (gpc_reg_operand (operands[0], DImode)
9700 || gpc_reg_operand (operands[1], DImode))"
9701 "@
9702 mr %0,%1
9703 ld%U1%X1 %0,%1
9704 std%U0%X0 %1,%0
9705 li %0,%1
9706 lis %0,%v1
9707 #
9708 {cal|la} %0,%a1
9709 fmr %0,%1
9710 lfd%U1%X1 %0,%1
9711 stfd%U0%X0 %1,%0
9712 mf%1 %0
9713 mt%0 %1
9714 {cror 0,0,0|nop}"
9715 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9716 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9718 ;; immediate value valid for a single instruction hiding in a const_double
9719 (define_insn ""
9720 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9721 (match_operand:DI 1 "const_double_operand" "F"))]
9722 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9723 && GET_CODE (operands[1]) == CONST_DOUBLE
9724 && num_insns_constant (operands[1], DImode) == 1"
9725 "*
9726 {
9727 return ((unsigned HOST_WIDE_INT)
9728 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9729 ? \"li %0,%1\" : \"lis %0,%v1\";
9730 }")
9732 ;; Generate all one-bits and clear left or right.
9733 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9734 (define_split
9735 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9736 (match_operand:DI 1 "mask64_operand" ""))]
9737 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9738 [(set (match_dup 0) (const_int -1))
9739 (set (match_dup 0)
9740 (and:DI (rotate:DI (match_dup 0)
9741 (const_int 0))
9742 (match_dup 1)))]
9743 "")
9745 ;; Split a load of a large constant into the appropriate five-instruction
9746 ;; sequence. Handle anything in a constant number of insns.
9747 ;; When non-easy constants can go in the TOC, this should use
9748 ;; easy_fp_constant predicate.
9749 (define_split
9750 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9751 (match_operand:DI 1 "const_int_operand" ""))]
9752 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9753 [(set (match_dup 0) (match_dup 2))
9754 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9755 "
9756 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9758 if (tem == operands[0])
9759 DONE;
9760 else
9761 FAIL;
9762 }")
9764 (define_split
9765 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9766 (match_operand:DI 1 "const_double_operand" ""))]
9767 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9768 [(set (match_dup 0) (match_dup 2))
9769 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9770 "
9771 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9773 if (tem == operands[0])
9774 DONE;
9775 else
9776 FAIL;
9777 }")
9778 \f
9779 ;; TImode is similar, except that we usually want to compute the address into
9780 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9781 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9783 ;; We say that MQ is clobbered in the last alternative because the first
9784 ;; alternative would never get used otherwise since it would need a reload
9785 ;; while the 2nd alternative would not. We put memory cases first so they
9786 ;; are preferred. Otherwise, we'd try to reload the output instead of
9787 ;; giving the SCRATCH mq.
9789 (define_insn "*movti_power"
9790 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9791 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9792 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9793 "TARGET_POWER && ! TARGET_POWERPC64
9794 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9795 "*
9796 {
9797 switch (which_alternative)
9798 {
9799 default:
9800 gcc_unreachable ();
9802 case 0:
9803 if (TARGET_STRING)
9804 return \"{stsi|stswi} %1,%P0,16\";
9805 case 1:
9806 case 2:
9807 return \"#\";
9808 case 3:
9809 /* If the address is not used in the output, we can use lsi. Otherwise,
9810 fall through to generating four loads. */
9811 if (TARGET_STRING
9812 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9813 return \"{lsi|lswi} %0,%P1,16\";
9814 /* ... fall through ... */
9815 case 4:
9816 case 5:
9817 return \"#\";
9818 }
9819 }"
9820 [(set_attr "type" "store,store,*,load,load,*")])
9822 (define_insn "*movti_string"
9823 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9824 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9825 "! TARGET_POWER && ! TARGET_POWERPC64
9826 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9827 "*
9828 {
9829 switch (which_alternative)
9830 {
9831 default:
9832 gcc_unreachable ();
9833 case 0:
9834 if (TARGET_STRING)
9835 return \"{stsi|stswi} %1,%P0,16\";
9836 case 1:
9837 case 2:
9838 return \"#\";
9839 case 3:
9840 /* If the address is not used in the output, we can use lsi. Otherwise,
9841 fall through to generating four loads. */
9842 if (TARGET_STRING
9843 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9844 return \"{lsi|lswi} %0,%P1,16\";
9845 /* ... fall through ... */
9846 case 4:
9847 case 5:
9848 return \"#\";
9849 }
9850 }"
9851 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
9852 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
9853 (const_string "always")
9854 (const_string "conditional")))])
9856 (define_insn "*movti_ppc64"
9857 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9858 (match_operand:TI 1 "input_operand" "r,r,m"))]
9859 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9860 || gpc_reg_operand (operands[1], TImode)))
9861 && VECTOR_MEM_NONE_P (TImode)"
9862 "#"
9863 [(set_attr "type" "*,store,load")])
9865 (define_split
9866 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9867 (match_operand:TI 1 "const_double_operand" ""))]
9868 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
9869 [(set (match_dup 2) (match_dup 4))
9870 (set (match_dup 3) (match_dup 5))]
9871 "
9872 {
9873 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9874 TImode);
9875 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9876 TImode);
9877 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9878 {
9879 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9880 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9881 }
9882 else if (GET_CODE (operands[1]) == CONST_INT)
9883 {
9884 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9885 operands[5] = operands[1];
9886 }
9887 else
9888 FAIL;
9889 }")
9891 (define_split
9892 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9893 (match_operand:TI 1 "input_operand" ""))]
9894 "reload_completed && VECTOR_MEM_NONE_P (TImode)
9895 && gpr_or_gpr_p (operands[0], operands[1])"
9896 [(pc)]
9897 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9898 \f
9899 (define_expand "load_multiple"
9900 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9901 (match_operand:SI 1 "" ""))
9902 (use (match_operand:SI 2 "" ""))])]
9903 "TARGET_STRING && !TARGET_POWERPC64"
9904 "
9905 {
9906 int regno;
9907 int count;
9908 rtx op1;
9909 int i;
9911 /* Support only loading a constant number of fixed-point registers from
9912 memory and only bother with this if more than two; the machine
9913 doesn't support more than eight. */
9914 if (GET_CODE (operands[2]) != CONST_INT
9915 || INTVAL (operands[2]) <= 2
9916 || INTVAL (operands[2]) > 8
9917 || GET_CODE (operands[1]) != MEM
9918 || GET_CODE (operands[0]) != REG
9919 || REGNO (operands[0]) >= 32)
9920 FAIL;
9922 count = INTVAL (operands[2]);
9923 regno = REGNO (operands[0]);
9925 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9926 op1 = replace_equiv_address (operands[1],
9927 force_reg (SImode, XEXP (operands[1], 0)));
9929 for (i = 0; i < count; i++)
9930 XVECEXP (operands[3], 0, i)
9931 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9932 adjust_address_nv (op1, SImode, i * 4));
9933 }")
9935 (define_insn "*ldmsi8"
9936 [(match_parallel 0 "load_multiple_operation"
9937 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9938 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9939 (set (match_operand:SI 3 "gpc_reg_operand" "")
9940 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9941 (set (match_operand:SI 4 "gpc_reg_operand" "")
9942 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9943 (set (match_operand:SI 5 "gpc_reg_operand" "")
9944 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9945 (set (match_operand:SI 6 "gpc_reg_operand" "")
9946 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9947 (set (match_operand:SI 7 "gpc_reg_operand" "")
9948 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9949 (set (match_operand:SI 8 "gpc_reg_operand" "")
9950 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9951 (set (match_operand:SI 9 "gpc_reg_operand" "")
9952 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9953 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9954 "*
9955 { return rs6000_output_load_multiple (operands); }"
9956 [(set_attr "type" "load_ux")
9957 (set_attr "length" "32")])
9959 (define_insn "*ldmsi7"
9960 [(match_parallel 0 "load_multiple_operation"
9961 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9962 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9963 (set (match_operand:SI 3 "gpc_reg_operand" "")
9964 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9965 (set (match_operand:SI 4 "gpc_reg_operand" "")
9966 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9967 (set (match_operand:SI 5 "gpc_reg_operand" "")
9968 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9969 (set (match_operand:SI 6 "gpc_reg_operand" "")
9970 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9971 (set (match_operand:SI 7 "gpc_reg_operand" "")
9972 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9973 (set (match_operand:SI 8 "gpc_reg_operand" "")
9974 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9975 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9976 "*
9977 { return rs6000_output_load_multiple (operands); }"
9978 [(set_attr "type" "load_ux")
9979 (set_attr "length" "32")])
9981 (define_insn "*ldmsi6"
9982 [(match_parallel 0 "load_multiple_operation"
9983 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9984 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9985 (set (match_operand:SI 3 "gpc_reg_operand" "")
9986 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9987 (set (match_operand:SI 4 "gpc_reg_operand" "")
9988 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9989 (set (match_operand:SI 5 "gpc_reg_operand" "")
9990 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9991 (set (match_operand:SI 6 "gpc_reg_operand" "")
9992 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9993 (set (match_operand:SI 7 "gpc_reg_operand" "")
9994 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9995 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9996 "*
9997 { return rs6000_output_load_multiple (operands); }"
9998 [(set_attr "type" "load_ux")
9999 (set_attr "length" "32")])
10001 (define_insn "*ldmsi5"
10002 [(match_parallel 0 "load_multiple_operation"
10003 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10004 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10005 (set (match_operand:SI 3 "gpc_reg_operand" "")
10006 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10007 (set (match_operand:SI 4 "gpc_reg_operand" "")
10008 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10009 (set (match_operand:SI 5 "gpc_reg_operand" "")
10010 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10011 (set (match_operand:SI 6 "gpc_reg_operand" "")
10012 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10013 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10014 "*
10015 { return rs6000_output_load_multiple (operands); }"
10016 [(set_attr "type" "load_ux")
10017 (set_attr "length" "32")])
10019 (define_insn "*ldmsi4"
10020 [(match_parallel 0 "load_multiple_operation"
10021 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10022 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10023 (set (match_operand:SI 3 "gpc_reg_operand" "")
10024 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10025 (set (match_operand:SI 4 "gpc_reg_operand" "")
10026 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10027 (set (match_operand:SI 5 "gpc_reg_operand" "")
10028 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10029 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10030 "*
10031 { return rs6000_output_load_multiple (operands); }"
10032 [(set_attr "type" "load_ux")
10033 (set_attr "length" "32")])
10035 (define_insn "*ldmsi3"
10036 [(match_parallel 0 "load_multiple_operation"
10037 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10038 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10039 (set (match_operand:SI 3 "gpc_reg_operand" "")
10040 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10041 (set (match_operand:SI 4 "gpc_reg_operand" "")
10042 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10043 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10044 "*
10045 { return rs6000_output_load_multiple (operands); }"
10046 [(set_attr "type" "load_ux")
10047 (set_attr "length" "32")])
10049 (define_expand "store_multiple"
10050 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10051 (match_operand:SI 1 "" ""))
10052 (clobber (scratch:SI))
10053 (use (match_operand:SI 2 "" ""))])]
10054 "TARGET_STRING && !TARGET_POWERPC64"
10055 "
10056 {
10057 int regno;
10058 int count;
10059 rtx to;
10060 rtx op0;
10061 int i;
10063 /* Support only storing a constant number of fixed-point registers to
10064 memory and only bother with this if more than two; the machine
10065 doesn't support more than eight. */
10066 if (GET_CODE (operands[2]) != CONST_INT
10067 || INTVAL (operands[2]) <= 2
10068 || INTVAL (operands[2]) > 8
10069 || GET_CODE (operands[0]) != MEM
10070 || GET_CODE (operands[1]) != REG
10071 || REGNO (operands[1]) >= 32)
10072 FAIL;
10074 count = INTVAL (operands[2]);
10075 regno = REGNO (operands[1]);
10077 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10078 to = force_reg (SImode, XEXP (operands[0], 0));
10079 op0 = replace_equiv_address (operands[0], to);
10081 XVECEXP (operands[3], 0, 0)
10082 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10083 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10084 gen_rtx_SCRATCH (SImode));
10086 for (i = 1; i < count; i++)
10087 XVECEXP (operands[3], 0, i + 1)
10088 = gen_rtx_SET (VOIDmode,
10089 adjust_address_nv (op0, SImode, i * 4),
10090 gen_rtx_REG (SImode, regno + i));
10091 }")
10093 (define_insn "*stmsi8"
10094 [(match_parallel 0 "store_multiple_operation"
10095 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10096 (match_operand:SI 2 "gpc_reg_operand" "r"))
10097 (clobber (match_scratch:SI 3 "=X"))
10098 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10099 (match_operand:SI 4 "gpc_reg_operand" "r"))
10100 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10101 (match_operand:SI 5 "gpc_reg_operand" "r"))
10102 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10103 (match_operand:SI 6 "gpc_reg_operand" "r"))
10104 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10105 (match_operand:SI 7 "gpc_reg_operand" "r"))
10106 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10107 (match_operand:SI 8 "gpc_reg_operand" "r"))
10108 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10109 (match_operand:SI 9 "gpc_reg_operand" "r"))
10110 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10111 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10112 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10113 "{stsi|stswi} %2,%1,%O0"
10114 [(set_attr "type" "store_ux")
10115 (set_attr "cell_micro" "always")])
10117 (define_insn "*stmsi7"
10118 [(match_parallel 0 "store_multiple_operation"
10119 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10120 (match_operand:SI 2 "gpc_reg_operand" "r"))
10121 (clobber (match_scratch:SI 3 "=X"))
10122 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10123 (match_operand:SI 4 "gpc_reg_operand" "r"))
10124 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10125 (match_operand:SI 5 "gpc_reg_operand" "r"))
10126 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10127 (match_operand:SI 6 "gpc_reg_operand" "r"))
10128 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10129 (match_operand:SI 7 "gpc_reg_operand" "r"))
10130 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10131 (match_operand:SI 8 "gpc_reg_operand" "r"))
10132 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10133 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10134 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10135 "{stsi|stswi} %2,%1,%O0"
10136 [(set_attr "type" "store_ux")
10137 (set_attr "cell_micro" "always")])
10139 (define_insn "*stmsi6"
10140 [(match_parallel 0 "store_multiple_operation"
10141 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10142 (match_operand:SI 2 "gpc_reg_operand" "r"))
10143 (clobber (match_scratch:SI 3 "=X"))
10144 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10145 (match_operand:SI 4 "gpc_reg_operand" "r"))
10146 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10147 (match_operand:SI 5 "gpc_reg_operand" "r"))
10148 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10149 (match_operand:SI 6 "gpc_reg_operand" "r"))
10150 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10151 (match_operand:SI 7 "gpc_reg_operand" "r"))
10152 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10153 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10154 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10155 "{stsi|stswi} %2,%1,%O0"
10156 [(set_attr "type" "store_ux")
10157 (set_attr "cell_micro" "always")])
10159 (define_insn "*stmsi5"
10160 [(match_parallel 0 "store_multiple_operation"
10161 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10162 (match_operand:SI 2 "gpc_reg_operand" "r"))
10163 (clobber (match_scratch:SI 3 "=X"))
10164 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10165 (match_operand:SI 4 "gpc_reg_operand" "r"))
10166 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10167 (match_operand:SI 5 "gpc_reg_operand" "r"))
10168 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10169 (match_operand:SI 6 "gpc_reg_operand" "r"))
10170 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10171 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10172 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10173 "{stsi|stswi} %2,%1,%O0"
10174 [(set_attr "type" "store_ux")
10175 (set_attr "cell_micro" "always")])
10177 (define_insn "*stmsi4"
10178 [(match_parallel 0 "store_multiple_operation"
10179 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10180 (match_operand:SI 2 "gpc_reg_operand" "r"))
10181 (clobber (match_scratch:SI 3 "=X"))
10182 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10183 (match_operand:SI 4 "gpc_reg_operand" "r"))
10184 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10185 (match_operand:SI 5 "gpc_reg_operand" "r"))
10186 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10187 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10188 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10189 "{stsi|stswi} %2,%1,%O0"
10190 [(set_attr "type" "store_ux")
10191 (set_attr "cell_micro" "always")])
10193 (define_insn "*stmsi3"
10194 [(match_parallel 0 "store_multiple_operation"
10195 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10196 (match_operand:SI 2 "gpc_reg_operand" "r"))
10197 (clobber (match_scratch:SI 3 "=X"))
10198 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10199 (match_operand:SI 4 "gpc_reg_operand" "r"))
10200 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10201 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10202 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10203 "{stsi|stswi} %2,%1,%O0"
10204 [(set_attr "type" "store_ux")
10205 (set_attr "cell_micro" "always")])
10207 (define_insn "*stmsi8_power"
10208 [(match_parallel 0 "store_multiple_operation"
10209 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10210 (match_operand:SI 2 "gpc_reg_operand" "r"))
10211 (clobber (match_scratch:SI 3 "=q"))
10212 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10213 (match_operand:SI 4 "gpc_reg_operand" "r"))
10214 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10215 (match_operand:SI 5 "gpc_reg_operand" "r"))
10216 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10217 (match_operand:SI 6 "gpc_reg_operand" "r"))
10218 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10219 (match_operand:SI 7 "gpc_reg_operand" "r"))
10220 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10221 (match_operand:SI 8 "gpc_reg_operand" "r"))
10222 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10223 (match_operand:SI 9 "gpc_reg_operand" "r"))
10224 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10225 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10226 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10227 "{stsi|stswi} %2,%1,%O0"
10228 [(set_attr "type" "store_ux")
10229 (set_attr "cell_micro" "always")])
10231 (define_insn "*stmsi7_power"
10232 [(match_parallel 0 "store_multiple_operation"
10233 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10234 (match_operand:SI 2 "gpc_reg_operand" "r"))
10235 (clobber (match_scratch:SI 3 "=q"))
10236 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10237 (match_operand:SI 4 "gpc_reg_operand" "r"))
10238 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10239 (match_operand:SI 5 "gpc_reg_operand" "r"))
10240 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10241 (match_operand:SI 6 "gpc_reg_operand" "r"))
10242 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10243 (match_operand:SI 7 "gpc_reg_operand" "r"))
10244 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10245 (match_operand:SI 8 "gpc_reg_operand" "r"))
10246 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10247 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10248 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10249 "{stsi|stswi} %2,%1,%O0"
10250 [(set_attr "type" "store_ux")
10251 (set_attr "cell_micro" "always")])
10253 (define_insn "*stmsi6_power"
10254 [(match_parallel 0 "store_multiple_operation"
10255 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10256 (match_operand:SI 2 "gpc_reg_operand" "r"))
10257 (clobber (match_scratch:SI 3 "=q"))
10258 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10259 (match_operand:SI 4 "gpc_reg_operand" "r"))
10260 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10261 (match_operand:SI 5 "gpc_reg_operand" "r"))
10262 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10263 (match_operand:SI 6 "gpc_reg_operand" "r"))
10264 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10265 (match_operand:SI 7 "gpc_reg_operand" "r"))
10266 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10267 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10268 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10269 "{stsi|stswi} %2,%1,%O0"
10270 [(set_attr "type" "store_ux")
10271 (set_attr "cell_micro" "always")])
10273 (define_insn "*stmsi5_power"
10274 [(match_parallel 0 "store_multiple_operation"
10275 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10276 (match_operand:SI 2 "gpc_reg_operand" "r"))
10277 (clobber (match_scratch:SI 3 "=q"))
10278 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10279 (match_operand:SI 4 "gpc_reg_operand" "r"))
10280 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10281 (match_operand:SI 5 "gpc_reg_operand" "r"))
10282 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10283 (match_operand:SI 6 "gpc_reg_operand" "r"))
10284 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10285 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10286 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10287 "{stsi|stswi} %2,%1,%O0"
10288 [(set_attr "type" "store_ux")
10289 (set_attr "cell_micro" "always")])
10291 (define_insn "*stmsi4_power"
10292 [(match_parallel 0 "store_multiple_operation"
10293 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10294 (match_operand:SI 2 "gpc_reg_operand" "r"))
10295 (clobber (match_scratch:SI 3 "=q"))
10296 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10297 (match_operand:SI 4 "gpc_reg_operand" "r"))
10298 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10299 (match_operand:SI 5 "gpc_reg_operand" "r"))
10300 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10301 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10302 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10303 "{stsi|stswi} %2,%1,%O0"
10304 [(set_attr "type" "store_ux")
10305 (set_attr "cell_micro" "always")])
10307 (define_insn "*stmsi3_power"
10308 [(match_parallel 0 "store_multiple_operation"
10309 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10310 (match_operand:SI 2 "gpc_reg_operand" "r"))
10311 (clobber (match_scratch:SI 3 "=q"))
10312 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10313 (match_operand:SI 4 "gpc_reg_operand" "r"))
10314 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10315 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10316 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10317 "{stsi|stswi} %2,%1,%O0"
10318 [(set_attr "type" "store_ux")
10319 (set_attr "cell_micro" "always")])
10320 \f
10321 (define_expand "setmemsi"
10322 [(parallel [(set (match_operand:BLK 0 "" "")
10323 (match_operand 2 "const_int_operand" ""))
10324 (use (match_operand:SI 1 "" ""))
10325 (use (match_operand:SI 3 "" ""))])]
10326 ""
10327 "
10328 {
10329 /* If value to set is not zero, use the library routine. */
10330 if (operands[2] != const0_rtx)
10331 FAIL;
10333 if (expand_block_clear (operands))
10334 DONE;
10335 else
10336 FAIL;
10337 }")
10339 ;; String/block move insn.
10340 ;; Argument 0 is the destination
10341 ;; Argument 1 is the source
10342 ;; Argument 2 is the length
10343 ;; Argument 3 is the alignment
10345 (define_expand "movmemsi"
10346 [(parallel [(set (match_operand:BLK 0 "" "")
10347 (match_operand:BLK 1 "" ""))
10348 (use (match_operand:SI 2 "" ""))
10349 (use (match_operand:SI 3 "" ""))])]
10350 ""
10351 "
10352 {
10353 if (expand_block_move (operands))
10354 DONE;
10355 else
10356 FAIL;
10357 }")
10359 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10360 ;; register allocator doesn't have a clue about allocating 8 word registers.
10361 ;; rD/rS = r5 is preferred, efficient form.
10362 (define_expand "movmemsi_8reg"
10363 [(parallel [(set (match_operand 0 "" "")
10364 (match_operand 1 "" ""))
10365 (use (match_operand 2 "" ""))
10366 (use (match_operand 3 "" ""))
10367 (clobber (reg:SI 5))
10368 (clobber (reg:SI 6))
10369 (clobber (reg:SI 7))
10370 (clobber (reg:SI 8))
10371 (clobber (reg:SI 9))
10372 (clobber (reg:SI 10))
10373 (clobber (reg:SI 11))
10374 (clobber (reg:SI 12))
10375 (clobber (match_scratch:SI 4 ""))])]
10376 "TARGET_STRING"
10377 "")
10379 (define_insn ""
10380 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10381 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10382 (use (match_operand:SI 2 "immediate_operand" "i"))
10383 (use (match_operand:SI 3 "immediate_operand" "i"))
10384 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10385 (clobber (reg:SI 6))
10386 (clobber (reg:SI 7))
10387 (clobber (reg:SI 8))
10388 (clobber (reg:SI 9))
10389 (clobber (reg:SI 10))
10390 (clobber (reg:SI 11))
10391 (clobber (reg:SI 12))
10392 (clobber (match_scratch:SI 5 "=q"))]
10393 "TARGET_STRING && TARGET_POWER
10394 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10395 || INTVAL (operands[2]) == 0)
10396 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10397 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10398 && REGNO (operands[4]) == 5"
10399 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10400 [(set_attr "type" "store_ux")
10401 (set_attr "cell_micro" "always")
10402 (set_attr "length" "8")])
10404 (define_insn ""
10405 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10406 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10407 (use (match_operand:SI 2 "immediate_operand" "i"))
10408 (use (match_operand:SI 3 "immediate_operand" "i"))
10409 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10410 (clobber (reg:SI 6))
10411 (clobber (reg:SI 7))
10412 (clobber (reg:SI 8))
10413 (clobber (reg:SI 9))
10414 (clobber (reg:SI 10))
10415 (clobber (reg:SI 11))
10416 (clobber (reg:SI 12))
10417 (clobber (match_scratch:SI 5 "=X"))]
10418 "TARGET_STRING && ! TARGET_POWER
10419 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10420 || INTVAL (operands[2]) == 0)
10421 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10422 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10423 && REGNO (operands[4]) == 5"
10424 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10425 [(set_attr "type" "store_ux")
10426 (set_attr "cell_micro" "always")
10427 (set_attr "length" "8")])
10429 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10430 ;; register allocator doesn't have a clue about allocating 6 word registers.
10431 ;; rD/rS = r5 is preferred, efficient form.
10432 (define_expand "movmemsi_6reg"
10433 [(parallel [(set (match_operand 0 "" "")
10434 (match_operand 1 "" ""))
10435 (use (match_operand 2 "" ""))
10436 (use (match_operand 3 "" ""))
10437 (clobber (reg:SI 5))
10438 (clobber (reg:SI 6))
10439 (clobber (reg:SI 7))
10440 (clobber (reg:SI 8))
10441 (clobber (reg:SI 9))
10442 (clobber (reg:SI 10))
10443 (clobber (match_scratch:SI 4 ""))])]
10444 "TARGET_STRING"
10445 "")
10447 (define_insn ""
10448 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10449 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10450 (use (match_operand:SI 2 "immediate_operand" "i"))
10451 (use (match_operand:SI 3 "immediate_operand" "i"))
10452 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10453 (clobber (reg:SI 6))
10454 (clobber (reg:SI 7))
10455 (clobber (reg:SI 8))
10456 (clobber (reg:SI 9))
10457 (clobber (reg:SI 10))
10458 (clobber (match_scratch:SI 5 "=q"))]
10459 "TARGET_STRING && TARGET_POWER
10460 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
10461 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10462 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10463 && REGNO (operands[4]) == 5"
10464 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10465 [(set_attr "type" "store_ux")
10466 (set_attr "cell_micro" "always")
10467 (set_attr "length" "8")])
10469 (define_insn ""
10470 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10471 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10472 (use (match_operand:SI 2 "immediate_operand" "i"))
10473 (use (match_operand:SI 3 "immediate_operand" "i"))
10474 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10475 (clobber (reg:SI 6))
10476 (clobber (reg:SI 7))
10477 (clobber (reg:SI 8))
10478 (clobber (reg:SI 9))
10479 (clobber (reg:SI 10))
10480 (clobber (match_scratch:SI 5 "=X"))]
10481 "TARGET_STRING && ! TARGET_POWER
10482 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10483 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10484 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10485 && REGNO (operands[4]) == 5"
10486 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10487 [(set_attr "type" "store_ux")
10488 (set_attr "cell_micro" "always")
10489 (set_attr "length" "8")])
10491 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10492 ;; problems with TImode.
10493 ;; rD/rS = r5 is preferred, efficient form.
10494 (define_expand "movmemsi_4reg"
10495 [(parallel [(set (match_operand 0 "" "")
10496 (match_operand 1 "" ""))
10497 (use (match_operand 2 "" ""))
10498 (use (match_operand 3 "" ""))
10499 (clobber (reg:SI 5))
10500 (clobber (reg:SI 6))
10501 (clobber (reg:SI 7))
10502 (clobber (reg:SI 8))
10503 (clobber (match_scratch:SI 4 ""))])]
10504 "TARGET_STRING"
10505 "")
10507 (define_insn ""
10508 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10509 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10510 (use (match_operand:SI 2 "immediate_operand" "i"))
10511 (use (match_operand:SI 3 "immediate_operand" "i"))
10512 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10513 (clobber (reg:SI 6))
10514 (clobber (reg:SI 7))
10515 (clobber (reg:SI 8))
10516 (clobber (match_scratch:SI 5 "=q"))]
10517 "TARGET_STRING && TARGET_POWER
10518 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10519 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10520 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10521 && REGNO (operands[4]) == 5"
10522 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10523 [(set_attr "type" "store_ux")
10524 (set_attr "cell_micro" "always")
10525 (set_attr "length" "8")])
10527 (define_insn ""
10528 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10529 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10530 (use (match_operand:SI 2 "immediate_operand" "i"))
10531 (use (match_operand:SI 3 "immediate_operand" "i"))
10532 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10533 (clobber (reg:SI 6))
10534 (clobber (reg:SI 7))
10535 (clobber (reg:SI 8))
10536 (clobber (match_scratch:SI 5 "=X"))]
10537 "TARGET_STRING && ! TARGET_POWER
10538 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10539 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10540 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10541 && REGNO (operands[4]) == 5"
10542 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10543 [(set_attr "type" "store_ux")
10544 (set_attr "cell_micro" "always")
10545 (set_attr "length" "8")])
10547 ;; Move up to 8 bytes at a time.
10548 (define_expand "movmemsi_2reg"
10549 [(parallel [(set (match_operand 0 "" "")
10550 (match_operand 1 "" ""))
10551 (use (match_operand 2 "" ""))
10552 (use (match_operand 3 "" ""))
10553 (clobber (match_scratch:DI 4 ""))
10554 (clobber (match_scratch:SI 5 ""))])]
10555 "TARGET_STRING && ! TARGET_POWERPC64"
10556 "")
10558 (define_insn ""
10559 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10560 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10561 (use (match_operand:SI 2 "immediate_operand" "i"))
10562 (use (match_operand:SI 3 "immediate_operand" "i"))
10563 (clobber (match_scratch:DI 4 "=&r"))
10564 (clobber (match_scratch:SI 5 "=q"))]
10565 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
10566 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10567 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10568 [(set_attr "type" "store_ux")
10569 (set_attr "cell_micro" "always")
10570 (set_attr "length" "8")])
10572 (define_insn ""
10573 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10574 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10575 (use (match_operand:SI 2 "immediate_operand" "i"))
10576 (use (match_operand:SI 3 "immediate_operand" "i"))
10577 (clobber (match_scratch:DI 4 "=&r"))
10578 (clobber (match_scratch:SI 5 "=X"))]
10579 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
10580 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10581 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10582 [(set_attr "type" "store_ux")
10583 (set_attr "cell_micro" "always")
10584 (set_attr "length" "8")])
10586 ;; Move up to 4 bytes at a time.
10587 (define_expand "movmemsi_1reg"
10588 [(parallel [(set (match_operand 0 "" "")
10589 (match_operand 1 "" ""))
10590 (use (match_operand 2 "" ""))
10591 (use (match_operand 3 "" ""))
10592 (clobber (match_scratch:SI 4 ""))
10593 (clobber (match_scratch:SI 5 ""))])]
10594 "TARGET_STRING"
10595 "")
10597 (define_insn ""
10598 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10599 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10600 (use (match_operand:SI 2 "immediate_operand" "i"))
10601 (use (match_operand:SI 3 "immediate_operand" "i"))
10602 (clobber (match_scratch:SI 4 "=&r"))
10603 (clobber (match_scratch:SI 5 "=q"))]
10604 "TARGET_STRING && TARGET_POWER
10605 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10606 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10607 [(set_attr "type" "store_ux")
10608 (set_attr "cell_micro" "always")
10609 (set_attr "length" "8")])
10611 (define_insn ""
10612 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10613 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10614 (use (match_operand:SI 2 "immediate_operand" "i"))
10615 (use (match_operand:SI 3 "immediate_operand" "i"))
10616 (clobber (match_scratch:SI 4 "=&r"))
10617 (clobber (match_scratch:SI 5 "=X"))]
10618 "TARGET_STRING && ! TARGET_POWER
10619 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10620 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10621 [(set_attr "type" "store_ux")
10622 (set_attr "cell_micro" "always")
10623 (set_attr "length" "8")])
10624 \f
10625 ;; Define insns that do load or store with update. Some of these we can
10626 ;; get by using pre-decrement or pre-increment, but the hardware can also
10627 ;; do cases where the increment is not the size of the object.
10628 ;;
10629 ;; In all these cases, we use operands 0 and 1 for the register being
10630 ;; incremented because those are the operands that local-alloc will
10631 ;; tie and these are the pair most likely to be tieable (and the ones
10632 ;; that will benefit the most).
10634 (define_insn "*movdi_update1"
10635 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10636 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10637 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10638 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10639 (plus:DI (match_dup 1) (match_dup 2)))]
10640 "TARGET_POWERPC64 && TARGET_UPDATE
10641 && (!avoiding_indexed_address_p (DImode)
10642 || !gpc_reg_operand (operands[2], DImode))"
10643 "@
10644 ldux %3,%0,%2
10645 ldu %3,%2(%0)"
10646 [(set_attr "type" "load_ux,load_u")])
10648 (define_insn "movdi_<mode>_update"
10649 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10650 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10651 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10652 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10653 (plus:P (match_dup 1) (match_dup 2)))]
10654 "TARGET_POWERPC64 && TARGET_UPDATE
10655 && (!avoiding_indexed_address_p (Pmode)
10656 || !gpc_reg_operand (operands[2], Pmode)
10657 || (REG_P (operands[0])
10658 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10659 "@
10660 stdux %3,%0,%2
10661 stdu %3,%2(%0)"
10662 [(set_attr "type" "store_ux,store_u")])
10664 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10665 ;; needed for stack allocation, even if the user passes -mno-update.
10666 (define_insn "movdi_<mode>_update_stack"
10667 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10668 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10669 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10670 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10671 (plus:P (match_dup 1) (match_dup 2)))]
10672 "TARGET_POWERPC64"
10673 "@
10674 stdux %3,%0,%2
10675 stdu %3,%2(%0)"
10676 [(set_attr "type" "store_ux,store_u")])
10678 (define_insn "*movsi_update1"
10679 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10680 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10681 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10682 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10683 (plus:SI (match_dup 1) (match_dup 2)))]
10684 "TARGET_UPDATE
10685 && (!avoiding_indexed_address_p (SImode)
10686 || !gpc_reg_operand (operands[2], SImode))"
10687 "@
10688 {lux|lwzux} %3,%0,%2
10689 {lu|lwzu} %3,%2(%0)"
10690 [(set_attr "type" "load_ux,load_u")])
10692 (define_insn "*movsi_update2"
10693 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10694 (sign_extend:DI
10695 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10696 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10697 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10698 (plus:DI (match_dup 1) (match_dup 2)))]
10699 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10700 && !avoiding_indexed_address_p (DImode)"
10701 "lwaux %3,%0,%2"
10702 [(set_attr "type" "load_ext_ux")])
10704 (define_insn "movsi_update"
10705 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10706 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10707 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10708 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10709 (plus:SI (match_dup 1) (match_dup 2)))]
10710 "TARGET_UPDATE
10711 && (!avoiding_indexed_address_p (SImode)
10712 || !gpc_reg_operand (operands[2], SImode)
10713 || (REG_P (operands[0])
10714 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10715 "@
10716 {stux|stwux} %3,%0,%2
10717 {stu|stwu} %3,%2(%0)"
10718 [(set_attr "type" "store_ux,store_u")])
10720 ;; This is an unconditional pattern; needed for stack allocation, even
10721 ;; if the user passes -mno-update.
10722 (define_insn "movsi_update_stack"
10723 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10724 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10725 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10726 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10727 (plus:SI (match_dup 1) (match_dup 2)))]
10728 ""
10729 "@
10730 {stux|stwux} %3,%0,%2
10731 {stu|stwu} %3,%2(%0)"
10732 [(set_attr "type" "store_ux,store_u")])
10734 (define_insn "*movhi_update1"
10735 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10736 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10737 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10738 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10739 (plus:SI (match_dup 1) (match_dup 2)))]
10740 "TARGET_UPDATE
10741 && (!avoiding_indexed_address_p (SImode)
10742 || !gpc_reg_operand (operands[2], SImode))"
10743 "@
10744 lhzux %3,%0,%2
10745 lhzu %3,%2(%0)"
10746 [(set_attr "type" "load_ux,load_u")])
10748 (define_insn "*movhi_update2"
10749 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10750 (zero_extend:SI
10751 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10752 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10753 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10754 (plus:SI (match_dup 1) (match_dup 2)))]
10755 "TARGET_UPDATE
10756 && (!avoiding_indexed_address_p (SImode)
10757 || !gpc_reg_operand (operands[2], SImode))"
10758 "@
10759 lhzux %3,%0,%2
10760 lhzu %3,%2(%0)"
10761 [(set_attr "type" "load_ux,load_u")])
10763 (define_insn "*movhi_update3"
10764 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10765 (sign_extend:SI
10766 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10767 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10768 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10769 (plus:SI (match_dup 1) (match_dup 2)))]
10770 "TARGET_UPDATE && rs6000_gen_cell_microcode
10771 && (!avoiding_indexed_address_p (SImode)
10772 || !gpc_reg_operand (operands[2], SImode))"
10773 "@
10774 lhaux %3,%0,%2
10775 lhau %3,%2(%0)"
10776 [(set_attr "type" "load_ext_ux,load_ext_u")])
10778 (define_insn "*movhi_update4"
10779 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10780 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10781 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10782 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10783 (plus:SI (match_dup 1) (match_dup 2)))]
10784 "TARGET_UPDATE
10785 && (!avoiding_indexed_address_p (SImode)
10786 || !gpc_reg_operand (operands[2], SImode))"
10787 "@
10788 sthux %3,%0,%2
10789 sthu %3,%2(%0)"
10790 [(set_attr "type" "store_ux,store_u")])
10792 (define_insn "*movqi_update1"
10793 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10794 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10795 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10796 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10797 (plus:SI (match_dup 1) (match_dup 2)))]
10798 "TARGET_UPDATE
10799 && (!avoiding_indexed_address_p (SImode)
10800 || !gpc_reg_operand (operands[2], SImode))"
10801 "@
10802 lbzux %3,%0,%2
10803 lbzu %3,%2(%0)"
10804 [(set_attr "type" "load_ux,load_u")])
10806 (define_insn "*movqi_update2"
10807 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10808 (zero_extend:SI
10809 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10810 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10811 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10812 (plus:SI (match_dup 1) (match_dup 2)))]
10813 "TARGET_UPDATE
10814 && (!avoiding_indexed_address_p (SImode)
10815 || !gpc_reg_operand (operands[2], SImode))"
10816 "@
10817 lbzux %3,%0,%2
10818 lbzu %3,%2(%0)"
10819 [(set_attr "type" "load_ux,load_u")])
10821 (define_insn "*movqi_update3"
10822 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10823 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10824 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10825 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10826 (plus:SI (match_dup 1) (match_dup 2)))]
10827 "TARGET_UPDATE
10828 && (!avoiding_indexed_address_p (SImode)
10829 || !gpc_reg_operand (operands[2], SImode))"
10830 "@
10831 stbux %3,%0,%2
10832 stbu %3,%2(%0)"
10833 [(set_attr "type" "store_ux,store_u")])
10835 (define_insn "*movsf_update1"
10836 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10837 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10838 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10839 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10840 (plus:SI (match_dup 1) (match_dup 2)))]
10841 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10842 && (!avoiding_indexed_address_p (SImode)
10843 || !gpc_reg_operand (operands[2], SImode))"
10844 "@
10845 lfsux %3,%0,%2
10846 lfsu %3,%2(%0)"
10847 [(set_attr "type" "fpload_ux,fpload_u")])
10849 (define_insn "*movsf_update2"
10850 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10851 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10852 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10853 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10854 (plus:SI (match_dup 1) (match_dup 2)))]
10855 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10856 && (!avoiding_indexed_address_p (SImode)
10857 || !gpc_reg_operand (operands[2], SImode))"
10858 "@
10859 stfsux %3,%0,%2
10860 stfsu %3,%2(%0)"
10861 [(set_attr "type" "fpstore_ux,fpstore_u")])
10863 (define_insn "*movsf_update3"
10864 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10865 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10866 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10867 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10868 (plus:SI (match_dup 1) (match_dup 2)))]
10869 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10870 && (!avoiding_indexed_address_p (SImode)
10871 || !gpc_reg_operand (operands[2], SImode))"
10872 "@
10873 {lux|lwzux} %3,%0,%2
10874 {lu|lwzu} %3,%2(%0)"
10875 [(set_attr "type" "load_ux,load_u")])
10877 (define_insn "*movsf_update4"
10878 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10879 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10880 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10881 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10882 (plus:SI (match_dup 1) (match_dup 2)))]
10883 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10884 && (!avoiding_indexed_address_p (SImode)
10885 || !gpc_reg_operand (operands[2], SImode))"
10886 "@
10887 {stux|stwux} %3,%0,%2
10888 {stu|stwu} %3,%2(%0)"
10889 [(set_attr "type" "store_ux,store_u")])
10891 (define_insn "*movdf_update1"
10892 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10893 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10894 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10895 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10896 (plus:SI (match_dup 1) (match_dup 2)))]
10897 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10898 && (!avoiding_indexed_address_p (SImode)
10899 || !gpc_reg_operand (operands[2], SImode))"
10900 "@
10901 lfdux %3,%0,%2
10902 lfdu %3,%2(%0)"
10903 [(set_attr "type" "fpload_ux,fpload_u")])
10905 (define_insn "*movdf_update2"
10906 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10907 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10908 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10909 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10910 (plus:SI (match_dup 1) (match_dup 2)))]
10911 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10912 && (!avoiding_indexed_address_p (SImode)
10913 || !gpc_reg_operand (operands[2], SImode))"
10914 "@
10915 stfdux %3,%0,%2
10916 stfdu %3,%2(%0)"
10917 [(set_attr "type" "fpstore_ux,fpstore_u")])
10919 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10921 (define_insn "*lfq_power2"
10922 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10923 (match_operand:V2DF 1 "memory_operand" ""))]
10924 "TARGET_POWER2
10925 && TARGET_HARD_FLOAT && TARGET_FPRS"
10926 "lfq%U1%X1 %0,%1")
10928 (define_peephole2
10929 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10930 (match_operand:DF 1 "memory_operand" ""))
10931 (set (match_operand:DF 2 "gpc_reg_operand" "")
10932 (match_operand:DF 3 "memory_operand" ""))]
10933 "TARGET_POWER2
10934 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10935 && registers_ok_for_quad_peep (operands[0], operands[2])
10936 && mems_ok_for_quad_peep (operands[1], operands[3])"
10937 [(set (match_dup 0)
10938 (match_dup 1))]
10939 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10940 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10942 (define_insn "*stfq_power2"
10943 [(set (match_operand:V2DF 0 "memory_operand" "")
10944 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10945 "TARGET_POWER2
10946 && TARGET_HARD_FLOAT && TARGET_FPRS"
10947 "stfq%U0%X0 %1,%0")
10950 (define_peephole2
10951 [(set (match_operand:DF 0 "memory_operand" "")
10952 (match_operand:DF 1 "gpc_reg_operand" ""))
10953 (set (match_operand:DF 2 "memory_operand" "")
10954 (match_operand:DF 3 "gpc_reg_operand" ""))]
10955 "TARGET_POWER2
10956 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10957 && registers_ok_for_quad_peep (operands[1], operands[3])
10958 && mems_ok_for_quad_peep (operands[0], operands[2])"
10959 [(set (match_dup 0)
10960 (match_dup 1))]
10961 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10962 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10964 ;; After inserting conditional returns we can sometimes have
10965 ;; unnecessary register moves. Unfortunately we cannot have a
10966 ;; modeless peephole here, because some single SImode sets have early
10967 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10968 ;; sequences, using get_attr_length here will smash the operands
10969 ;; array. Neither is there an early_cobbler_p predicate.
10970 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10971 (define_peephole2
10972 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10973 (match_operand:DF 1 "any_operand" ""))
10974 (set (match_operand:DF 2 "gpc_reg_operand" "")
10975 (match_dup 0))]
10976 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10977 && peep2_reg_dead_p (2, operands[0])"
10978 [(set (match_dup 2) (match_dup 1))])
10980 (define_peephole2
10981 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10982 (match_operand:SF 1 "any_operand" ""))
10983 (set (match_operand:SF 2 "gpc_reg_operand" "")
10984 (match_dup 0))]
10985 "peep2_reg_dead_p (2, operands[0])"
10986 [(set (match_dup 2) (match_dup 1))])
10988 \f
10989 ;; TLS support.
10991 ;; Mode attributes for different ABIs.
10992 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10993 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10994 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10995 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10997 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
10998 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10999 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11000 (match_operand 4 "" "g")))
11001 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11002 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11003 UNSPEC_TLSGD)
11004 (clobber (reg:SI LR_REGNO))]
11005 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11006 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
11007 "&& TARGET_TLS_MARKERS"
11008 [(set (match_dup 0)
11009 (unspec:TLSmode [(match_dup 1)
11010 (match_dup 2)]
11011 UNSPEC_TLSGD))
11012 (parallel [(set (match_dup 0)
11013 (call (mem:TLSmode (match_dup 3))
11014 (match_dup 4)))
11015 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11016 (clobber (reg:SI LR_REGNO))])]
11017 ""
11018 [(set_attr "type" "two")
11019 (set_attr "length" "12")])
11021 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
11022 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11023 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11024 (match_operand 4 "" "g")))
11025 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11026 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11027 UNSPEC_TLSGD)
11028 (clobber (reg:SI LR_REGNO))]
11029 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11030 {
11031 if (flag_pic)
11032 {
11033 if (TARGET_SECURE_PLT && flag_pic == 2)
11034 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11035 else
11036 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11037 }
11038 else
11039 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11040 }
11041 "&& TARGET_TLS_MARKERS"
11042 [(set (match_dup 0)
11043 (unspec:TLSmode [(match_dup 1)
11044 (match_dup 2)]
11045 UNSPEC_TLSGD))
11046 (parallel [(set (match_dup 0)
11047 (call (mem:TLSmode (match_dup 3))
11048 (match_dup 4)))
11049 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11050 (clobber (reg:SI LR_REGNO))])]
11051 ""
11052 [(set_attr "type" "two")
11053 (set_attr "length" "8")])
11055 (define_insn "*tls_gd<TLSmode:tls_abi_suffix>"
11056 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11057 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11058 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11059 UNSPEC_TLSGD))]
11060 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11061 "addi %0,%1,%2@got@tlsgd"
11062 [(set_attr "length" "4")])
11064 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11065 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11066 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11067 (match_operand 2 "" "g")))
11068 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11069 UNSPEC_TLSGD)
11070 (clobber (reg:SI LR_REGNO))]
11071 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11072 "bl %z1(%3@tlsgd)\;%."
11073 [(set_attr "type" "branch")
11074 (set_attr "length" "8")])
11076 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11077 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11078 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11079 (match_operand 2 "" "g")))
11080 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11081 UNSPEC_TLSGD)
11082 (clobber (reg:SI LR_REGNO))]
11083 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11084 {
11085 if (flag_pic)
11086 {
11087 if (TARGET_SECURE_PLT && flag_pic == 2)
11088 return "bl %z1+32768(%3@tlsgd)@plt";
11089 return "bl %z1(%3@tlsgd)@plt";
11090 }
11091 return "bl %z1(%3@tlsgd)";
11092 }
11093 [(set_attr "type" "branch")
11094 (set_attr "length" "4")])
11096 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11097 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11098 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11099 (match_operand 3 "" "g")))
11100 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11101 UNSPEC_TLSLD)
11102 (clobber (reg:SI LR_REGNO))]
11103 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11104 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
11105 "&& TARGET_TLS_MARKERS"
11106 [(set (match_dup 0)
11107 (unspec:TLSmode [(match_dup 1)]
11108 UNSPEC_TLSLD))
11109 (parallel [(set (match_dup 0)
11110 (call (mem:TLSmode (match_dup 2))
11111 (match_dup 3)))
11112 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11113 (clobber (reg:SI LR_REGNO))])]
11114 ""
11115 [(set_attr "length" "12")])
11117 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11118 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11119 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11120 (match_operand 3 "" "g")))
11121 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11122 UNSPEC_TLSLD)
11123 (clobber (reg:SI LR_REGNO))]
11124 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11125 {
11126 if (flag_pic)
11127 {
11128 if (TARGET_SECURE_PLT && flag_pic == 2)
11129 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11130 else
11131 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11132 }
11133 else
11134 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11135 }
11136 "&& TARGET_TLS_MARKERS"
11137 [(set (match_dup 0)
11138 (unspec:TLSmode [(match_dup 1)]
11139 UNSPEC_TLSLD))
11140 (parallel [(set (match_dup 0)
11141 (call (mem:TLSmode (match_dup 2))
11142 (match_dup 3)))
11143 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11144 (clobber (reg:SI LR_REGNO))])]
11145 ""
11146 [(set_attr "length" "8")])
11148 (define_insn "*tls_ld<TLSmode:tls_abi_suffix>"
11149 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11150 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11151 UNSPEC_TLSLD))]
11152 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11153 "addi %0,%1,%&@got@tlsld"
11154 [(set_attr "length" "4")])
11156 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11157 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11158 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11159 (match_operand 2 "" "g")))
11160 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11161 (clobber (reg:SI LR_REGNO))]
11162 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11163 "bl %z1(%&@tlsld)\;%."
11164 [(set_attr "type" "branch")
11165 (set_attr "length" "8")])
11167 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11168 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11169 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11170 (match_operand 2 "" "g")))
11171 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11172 (clobber (reg:SI LR_REGNO))]
11173 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11174 {
11175 if (flag_pic)
11176 {
11177 if (TARGET_SECURE_PLT && flag_pic == 2)
11178 return "bl %z1+32768(%&@tlsld)@plt";
11179 return "bl %z1(%&@tlsld)@plt";
11180 }
11181 return "bl %z1(%&@tlsld)";
11182 }
11183 [(set_attr "type" "branch")
11184 (set_attr "length" "4")])
11186 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11187 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11188 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11189 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11190 UNSPEC_TLSDTPREL))]
11191 "HAVE_AS_TLS"
11192 "addi %0,%1,%2@dtprel")
11194 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11195 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11196 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11197 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11198 UNSPEC_TLSDTPRELHA))]
11199 "HAVE_AS_TLS"
11200 "addis %0,%1,%2@dtprel@ha")
11202 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11203 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11204 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11205 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11206 UNSPEC_TLSDTPRELLO))]
11207 "HAVE_AS_TLS"
11208 "addi %0,%1,%2@dtprel@l")
11210 (define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11211 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11212 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11213 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11214 UNSPEC_TLSGOTDTPREL))]
11215 "HAVE_AS_TLS"
11216 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
11218 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11219 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11220 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11221 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11222 UNSPEC_TLSTPREL))]
11223 "HAVE_AS_TLS"
11224 "addi %0,%1,%2@tprel")
11226 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11227 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11228 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11229 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11230 UNSPEC_TLSTPRELHA))]
11231 "HAVE_AS_TLS"
11232 "addis %0,%1,%2@tprel@ha")
11234 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11235 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11236 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11237 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11238 UNSPEC_TLSTPRELLO))]
11239 "HAVE_AS_TLS"
11240 "addi %0,%1,%2@tprel@l")
11242 ;; "b" output constraint here and on tls_tls input to support linker tls
11243 ;; optimization. The linker may edit the instructions emitted by a
11244 ;; tls_got_tprel/tls_tls pair to addis,addi.
11245 (define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11246 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11247 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11248 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11249 UNSPEC_TLSGOTTPREL))]
11250 "HAVE_AS_TLS"
11251 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
11253 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11254 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11255 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11256 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11257 UNSPEC_TLSTLS))]
11258 "HAVE_AS_TLS"
11259 "add %0,%1,%2@tls")
11261 \f
11262 ;; Next come insns related to the calling sequence.
11263 ;;
11264 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11265 ;; We move the back-chain and decrement the stack pointer.
11267 (define_expand "allocate_stack"
11268 [(set (match_operand 0 "gpc_reg_operand" "")
11269 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11270 (set (reg 1)
11271 (minus (reg 1) (match_dup 1)))]
11272 ""
11273 "
11274 { rtx chain = gen_reg_rtx (Pmode);
11275 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11276 rtx neg_op0;
11277 rtx insn, par, set, mem;
11279 emit_move_insn (chain, stack_bot);
11281 /* Check stack bounds if necessary. */
11282 if (crtl->limit_stack)
11283 {
11284 rtx available;
11285 available = expand_binop (Pmode, sub_optab,
11286 stack_pointer_rtx, stack_limit_rtx,
11287 NULL_RTX, 1, OPTAB_WIDEN);
11288 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11289 }
11291 if (GET_CODE (operands[1]) != CONST_INT
11292 || INTVAL (operands[1]) < -32767
11293 || INTVAL (operands[1]) > 32768)
11294 {
11295 neg_op0 = gen_reg_rtx (Pmode);
11296 if (TARGET_32BIT)
11297 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11298 else
11299 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11300 }
11301 else
11302 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11304 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11305 : gen_movdi_di_update_stack))
11306 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11307 chain));
11308 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11309 it now and set the alias set/attributes. The above gen_*_update
11310 calls will generate a PARALLEL with the MEM set being the first
11311 operation. */
11312 par = PATTERN (insn);
11313 gcc_assert (GET_CODE (par) == PARALLEL);
11314 set = XVECEXP (par, 0, 0);
11315 gcc_assert (GET_CODE (set) == SET);
11316 mem = SET_DEST (set);
11317 gcc_assert (MEM_P (mem));
11318 MEM_NOTRAP_P (mem) = 1;
11319 set_mem_alias_set (mem, get_frame_alias_set ());
11321 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11322 DONE;
11323 }")
11325 ;; These patterns say how to save and restore the stack pointer. We need not
11326 ;; save the stack pointer at function level since we are careful to
11327 ;; preserve the backchain. At block level, we have to restore the backchain
11328 ;; when we restore the stack pointer.
11329 ;;
11330 ;; For nonlocal gotos, we must save both the stack pointer and its
11331 ;; backchain and restore both. Note that in the nonlocal case, the
11332 ;; save area is a memory location.
11334 (define_expand "save_stack_function"
11335 [(match_operand 0 "any_operand" "")
11336 (match_operand 1 "any_operand" "")]
11337 ""
11338 "DONE;")
11340 (define_expand "restore_stack_function"
11341 [(match_operand 0 "any_operand" "")
11342 (match_operand 1 "any_operand" "")]
11343 ""
11344 "DONE;")
11346 ;; Adjust stack pointer (op0) to a new value (op1).
11347 ;; First copy old stack backchain to new location, and ensure that the
11348 ;; scheduler won't reorder the sp assignment before the backchain write.
11349 (define_expand "restore_stack_block"
11350 [(set (match_dup 2) (match_dup 3))
11351 (set (match_dup 4) (match_dup 2))
11352 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
11353 (set (match_operand 0 "register_operand" "")
11354 (match_operand 1 "register_operand" ""))]
11355 ""
11356 "
11357 {
11358 operands[1] = force_reg (Pmode, operands[1]);
11359 operands[2] = gen_reg_rtx (Pmode);
11360 operands[3] = gen_frame_mem (Pmode, operands[0]);
11361 operands[4] = gen_frame_mem (Pmode, operands[1]);
11362 operands[5] = gen_frame_mem (BLKmode, operands[0]);
11363 }")
11365 (define_expand "save_stack_nonlocal"
11366 [(set (match_dup 3) (match_dup 4))
11367 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11368 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11369 ""
11370 "
11371 {
11372 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11374 /* Copy the backchain to the first word, sp to the second. */
11375 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11376 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11377 operands[3] = gen_reg_rtx (Pmode);
11378 operands[4] = gen_frame_mem (Pmode, operands[1]);
11379 }")
11381 (define_expand "restore_stack_nonlocal"
11382 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11383 (set (match_dup 3) (match_dup 4))
11384 (set (match_dup 5) (match_dup 2))
11385 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
11386 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11387 ""
11388 "
11389 {
11390 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11392 /* Restore the backchain from the first word, sp from the second. */
11393 operands[2] = gen_reg_rtx (Pmode);
11394 operands[3] = gen_reg_rtx (Pmode);
11395 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11396 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11397 operands[5] = gen_frame_mem (Pmode, operands[3]);
11398 operands[6] = gen_frame_mem (BLKmode, operands[0]);
11399 }")
11400 \f
11401 ;; TOC register handling.
11403 ;; Code to initialize the TOC register...
11405 (define_insn "load_toc_aix_si"
11406 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11407 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11408 (use (reg:SI 2))])]
11409 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11410 "*
11411 {
11412 char buf[30];
11413 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11414 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11415 operands[2] = gen_rtx_REG (Pmode, 2);
11416 return \"{l|lwz} %0,%1(%2)\";
11417 }"
11418 [(set_attr "type" "load")])
11420 (define_insn "load_toc_aix_di"
11421 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11422 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11423 (use (reg:DI 2))])]
11424 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
11425 "*
11426 {
11427 char buf[30];
11428 #ifdef TARGET_RELOCATABLE
11429 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11430 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11431 #else
11432 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11433 #endif
11434 if (TARGET_ELF)
11435 strcat (buf, \"@toc\");
11436 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11437 operands[2] = gen_rtx_REG (Pmode, 2);
11438 return \"ld %0,%1(%2)\";
11439 }"
11440 [(set_attr "type" "load")])
11442 (define_insn "load_toc_v4_pic_si"
11443 [(set (reg:SI LR_REGNO)
11444 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11445 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11446 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11447 [(set_attr "type" "branch")
11448 (set_attr "length" "4")])
11450 (define_insn "load_toc_v4_PIC_1"
11451 [(set (reg:SI LR_REGNO)
11452 (match_operand:SI 0 "immediate_operand" "s"))
11453 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11454 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
11455 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11456 "bcl 20,31,%0\\n%0:"
11457 [(set_attr "type" "branch")
11458 (set_attr "length" "4")])
11460 (define_insn "load_toc_v4_PIC_1b"
11461 [(set (reg:SI LR_REGNO)
11462 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11463 (label_ref (match_operand 1 "" ""))]
11464 UNSPEC_TOCPTR))
11465 (match_dup 1)]
11466 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11467 "bcl 20,31,$+8\;.long %0-$"
11468 [(set_attr "type" "branch")
11469 (set_attr "length" "8")])
11471 (define_insn "load_toc_v4_PIC_2"
11472 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11473 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11474 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11475 (match_operand:SI 3 "immediate_operand" "s")))))]
11476 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11477 "{l|lwz} %0,%2-%3(%1)"
11478 [(set_attr "type" "load")])
11480 (define_insn "load_toc_v4_PIC_3b"
11481 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
11482 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11483 (high:SI
11484 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11485 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11486 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11487 "{cau|addis} %0,%1,%2-%3@ha")
11489 (define_insn "load_toc_v4_PIC_3c"
11490 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11491 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11492 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11493 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11494 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11495 "{cal %0,%2-%3@l(%1)|addi %0,%1,%2-%3@l}")
11497 ;; If the TOC is shared over a translation unit, as happens with all
11498 ;; the kinds of PIC that we support, we need to restore the TOC
11499 ;; pointer only when jumping over units of translation.
11500 ;; On Darwin, we need to reload the picbase.
11502 (define_expand "builtin_setjmp_receiver"
11503 [(use (label_ref (match_operand 0 "" "")))]
11504 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11505 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11506 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11507 "
11508 {
11509 #if TARGET_MACHO
11510 if (DEFAULT_ABI == ABI_DARWIN)
11511 {
11512 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11513 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11514 rtx tmplabrtx;
11515 char tmplab[20];
11517 crtl->uses_pic_offset_table = 1;
11518 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11519 CODE_LABEL_NUMBER (operands[0]));
11520 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11522 emit_insn (gen_load_macho_picbase (tmplabrtx));
11523 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11524 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11525 }
11526 else
11527 #endif
11528 rs6000_emit_load_toc_table (FALSE);
11529 DONE;
11530 }")
11532 ;; Elf specific ways of loading addresses for non-PIC code.
11533 ;; The output of this could be r0, but we make a very strong
11534 ;; preference for a base register because it will usually
11535 ;; be needed there.
11536 (define_insn "elf_high"
11537 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11538 (high:SI (match_operand 1 "" "")))]
11539 "TARGET_ELF && ! TARGET_64BIT"
11540 "{liu|lis} %0,%1@ha")
11542 (define_insn "elf_low"
11543 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11544 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11545 (match_operand 2 "" "")))]
11546 "TARGET_ELF && ! TARGET_64BIT"
11547 "@
11548 {cal|la} %0,%2@l(%1)
11549 {ai|addic} %0,%1,%K2")
11550 \f
11551 ;; A function pointer under AIX is a pointer to a data area whose first word
11552 ;; contains the actual address of the function, whose second word contains a
11553 ;; pointer to its TOC, and whose third word contains a value to place in the
11554 ;; static chain register (r11). Note that if we load the static chain, our
11555 ;; "trampoline" need not have any executable code.
11557 (define_expand "call_indirect_aix32"
11558 [(set (match_dup 2)
11559 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
11560 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11561 (reg:SI 2))
11562 (set (reg:SI 11)
11563 (mem:SI (plus:SI (match_dup 0)
11564 (const_int 8))))
11565 (parallel [(call (mem:SI (match_dup 2))
11566 (match_operand 1 "" ""))
11567 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
11568 (use (reg:SI 11))
11569 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11570 (clobber (reg:SI LR_REGNO))])]
11571 "TARGET_32BIT"
11572 "
11573 { operands[2] = gen_reg_rtx (SImode); }")
11575 (define_expand "call_indirect_aix64"
11576 [(set (match_dup 2)
11577 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
11578 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11579 (reg:DI 2))
11580 (set (reg:DI 11)
11581 (mem:DI (plus:DI (match_dup 0)
11582 (const_int 16))))
11583 (parallel [(call (mem:SI (match_dup 2))
11584 (match_operand 1 "" ""))
11585 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
11586 (use (reg:DI 11))
11587 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11588 (clobber (reg:SI LR_REGNO))])]
11589 "TARGET_64BIT"
11590 "
11591 { operands[2] = gen_reg_rtx (DImode); }")
11593 (define_expand "call_value_indirect_aix32"
11594 [(set (match_dup 3)
11595 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11596 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11597 (reg:SI 2))
11598 (set (reg:SI 11)
11599 (mem:SI (plus:SI (match_dup 1)
11600 (const_int 8))))
11601 (parallel [(set (match_operand 0 "" "")
11602 (call (mem:SI (match_dup 3))
11603 (match_operand 2 "" "")))
11604 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
11605 (use (reg:SI 11))
11606 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11607 (clobber (reg:SI LR_REGNO))])]
11608 "TARGET_32BIT"
11609 "
11610 { operands[3] = gen_reg_rtx (SImode); }")
11612 (define_expand "call_value_indirect_aix64"
11613 [(set (match_dup 3)
11614 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11615 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11616 (reg:DI 2))
11617 (set (reg:DI 11)
11618 (mem:DI (plus:DI (match_dup 1)
11619 (const_int 16))))
11620 (parallel [(set (match_operand 0 "" "")
11621 (call (mem:SI (match_dup 3))
11622 (match_operand 2 "" "")))
11623 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
11624 (use (reg:DI 11))
11625 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11626 (clobber (reg:SI LR_REGNO))])]
11627 "TARGET_64BIT"
11628 "
11629 { operands[3] = gen_reg_rtx (DImode); }")
11631 ;; Now the definitions for the call and call_value insns
11632 (define_expand "call"
11633 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11634 (match_operand 1 "" ""))
11635 (use (match_operand 2 "" ""))
11636 (clobber (reg:SI LR_REGNO))])]
11637 ""
11638 "
11639 {
11640 #if TARGET_MACHO
11641 if (MACHOPIC_INDIRECT)
11642 operands[0] = machopic_indirect_call_target (operands[0]);
11643 #endif
11645 gcc_assert (GET_CODE (operands[0]) == MEM);
11646 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11648 operands[0] = XEXP (operands[0], 0);
11650 if (GET_CODE (operands[0]) != SYMBOL_REF
11651 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
11652 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11653 {
11654 if (INTVAL (operands[2]) & CALL_LONG)
11655 operands[0] = rs6000_longcall_ref (operands[0]);
11657 switch (DEFAULT_ABI)
11658 {
11659 case ABI_V4:
11660 case ABI_DARWIN:
11661 operands[0] = force_reg (Pmode, operands[0]);
11662 break;
11664 case ABI_AIX:
11665 /* AIX function pointers are really pointers to a three word
11666 area. */
11667 emit_call_insn (TARGET_32BIT
11668 ? gen_call_indirect_aix32 (force_reg (SImode,
11669 operands[0]),
11670 operands[1])
11671 : gen_call_indirect_aix64 (force_reg (DImode,
11672 operands[0]),
11673 operands[1]));
11674 DONE;
11676 default:
11677 gcc_unreachable ();
11678 }
11679 }
11680 }")
11682 (define_expand "call_value"
11683 [(parallel [(set (match_operand 0 "" "")
11684 (call (mem:SI (match_operand 1 "address_operand" ""))
11685 (match_operand 2 "" "")))
11686 (use (match_operand 3 "" ""))
11687 (clobber (reg:SI LR_REGNO))])]
11688 ""
11689 "
11690 {
11691 #if TARGET_MACHO
11692 if (MACHOPIC_INDIRECT)
11693 operands[1] = machopic_indirect_call_target (operands[1]);
11694 #endif
11696 gcc_assert (GET_CODE (operands[1]) == MEM);
11697 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11699 operands[1] = XEXP (operands[1], 0);
11701 if (GET_CODE (operands[1]) != SYMBOL_REF
11702 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
11703 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11704 {
11705 if (INTVAL (operands[3]) & CALL_LONG)
11706 operands[1] = rs6000_longcall_ref (operands[1]);
11708 switch (DEFAULT_ABI)
11709 {
11710 case ABI_V4:
11711 case ABI_DARWIN:
11712 operands[1] = force_reg (Pmode, operands[1]);
11713 break;
11715 case ABI_AIX:
11716 /* AIX function pointers are really pointers to a three word
11717 area. */
11718 emit_call_insn (TARGET_32BIT
11719 ? gen_call_value_indirect_aix32 (operands[0],
11720 force_reg (SImode,
11721 operands[1]),
11722 operands[2])
11723 : gen_call_value_indirect_aix64 (operands[0],
11724 force_reg (DImode,
11725 operands[1]),
11726 operands[2]));
11727 DONE;
11729 default:
11730 gcc_unreachable ();
11731 }
11732 }
11733 }")
11735 ;; Call to function in current module. No TOC pointer reload needed.
11736 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11737 ;; either the function was not prototyped, or it was prototyped as a
11738 ;; variable argument function. It is > 0 if FP registers were passed
11739 ;; and < 0 if they were not.
11741 (define_insn "*call_local32"
11742 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11743 (match_operand 1 "" "g,g"))
11744 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11745 (clobber (reg:SI LR_REGNO))]
11746 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11747 "*
11748 {
11749 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11750 output_asm_insn (\"crxor 6,6,6\", operands);
11752 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11753 output_asm_insn (\"creqv 6,6,6\", operands);
11755 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11756 }"
11757 [(set_attr "type" "branch")
11758 (set_attr "length" "4,8")])
11760 (define_insn "*call_local64"
11761 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11762 (match_operand 1 "" "g,g"))
11763 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11764 (clobber (reg:SI LR_REGNO))]
11765 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11766 "*
11767 {
11768 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11769 output_asm_insn (\"crxor 6,6,6\", operands);
11771 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11772 output_asm_insn (\"creqv 6,6,6\", operands);
11774 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11775 }"
11776 [(set_attr "type" "branch")
11777 (set_attr "length" "4,8")])
11779 (define_insn "*call_value_local32"
11780 [(set (match_operand 0 "" "")
11781 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11782 (match_operand 2 "" "g,g")))
11783 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11784 (clobber (reg:SI LR_REGNO))]
11785 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11786 "*
11787 {
11788 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11789 output_asm_insn (\"crxor 6,6,6\", operands);
11791 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11792 output_asm_insn (\"creqv 6,6,6\", operands);
11794 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11795 }"
11796 [(set_attr "type" "branch")
11797 (set_attr "length" "4,8")])
11800 (define_insn "*call_value_local64"
11801 [(set (match_operand 0 "" "")
11802 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11803 (match_operand 2 "" "g,g")))
11804 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11805 (clobber (reg:SI LR_REGNO))]
11806 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11807 "*
11808 {
11809 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11810 output_asm_insn (\"crxor 6,6,6\", operands);
11812 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11813 output_asm_insn (\"creqv 6,6,6\", operands);
11815 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11816 }"
11817 [(set_attr "type" "branch")
11818 (set_attr "length" "4,8")])
11820 ;; Call to function which may be in another module. Restore the TOC
11821 ;; pointer (r2) after the call unless this is System V.
11822 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11823 ;; either the function was not prototyped, or it was prototyped as a
11824 ;; variable argument function. It is > 0 if FP registers were passed
11825 ;; and < 0 if they were not.
11827 (define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
11828 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11829 (match_operand 1 "" "g,g"))
11830 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
11831 (use (reg:SI 11))
11832 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11833 (clobber (reg:SI LR_REGNO))]
11834 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11835 "#"
11836 "&& reload_completed"
11837 [(set (reg:SI 2)
11838 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
11839 (parallel [(call (mem:SI (match_dup 0))
11840 (match_dup 1))
11841 (use (reg:SI 2))
11842 (use (reg:SI 11))
11843 (set (reg:SI 2)
11844 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11845 (clobber (reg:SI LR_REGNO))])]
11846 ""
11847 [(set_attr "type" "jmpreg")
11848 (set_attr "length" "12")])
11850 (define_insn "*call_indirect_nonlocal_aix32"
11851 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11852 (match_operand 1 "" "g,g"))
11853 (use (reg:SI 2))
11854 (use (reg:SI 11))
11855 (set (reg:SI 2)
11856 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11857 (clobber (reg:SI LR_REGNO))]
11858 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11859 "b%T0l\;{l|lwz} 2,20(1)"
11860 [(set_attr "type" "jmpreg")
11861 (set_attr "length" "8")])
11863 (define_insn "*call_nonlocal_aix32"
11864 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11865 (match_operand 1 "" "g"))
11866 (use (match_operand:SI 2 "immediate_operand" "O"))
11867 (clobber (reg:SI LR_REGNO))]
11868 "TARGET_32BIT
11869 && DEFAULT_ABI == ABI_AIX
11870 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11871 "bl %z0\;%."
11872 [(set_attr "type" "branch")
11873 (set_attr "length" "8")])
11875 (define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
11876 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11877 (match_operand 1 "" "g,g"))
11878 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
11879 (const_int 8))))
11880 (use (reg:DI 11))
11881 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11882 (clobber (reg:SI LR_REGNO))]
11883 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11884 "#"
11885 "&& reload_completed"
11886 [(set (reg:DI 2)
11887 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
11888 (parallel [(call (mem:SI (match_dup 0))
11889 (match_dup 1))
11890 (use (reg:DI 2))
11891 (use (reg:DI 11))
11892 (set (reg:DI 2)
11893 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11894 (clobber (reg:SI LR_REGNO))])]
11895 ""
11896 [(set_attr "type" "jmpreg")
11897 (set_attr "length" "12")])
11899 (define_insn "*call_indirect_nonlocal_aix64"
11900 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11901 (match_operand 1 "" "g,g"))
11902 (use (reg:DI 2))
11903 (use (reg:DI 11))
11904 (set (reg:DI 2)
11905 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11906 (clobber (reg:SI LR_REGNO))]
11907 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11908 "b%T0l\;ld 2,40(1)"
11909 [(set_attr "type" "jmpreg")
11910 (set_attr "length" "8")])
11912 (define_insn "*call_nonlocal_aix64"
11913 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11914 (match_operand 1 "" "g"))
11915 (use (match_operand:SI 2 "immediate_operand" "O"))
11916 (clobber (reg:SI LR_REGNO))]
11917 "TARGET_64BIT
11918 && DEFAULT_ABI == ABI_AIX
11919 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11920 "bl %z0\;%."
11921 [(set_attr "type" "branch")
11922 (set_attr "length" "8")])
11924 (define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
11925 [(set (match_operand 0 "" "")
11926 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11927 (match_operand 2 "" "g,g")))
11928 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
11929 (const_int 4))))
11930 (use (reg:SI 11))
11931 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11932 (clobber (reg:SI LR_REGNO))]
11933 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11934 "#"
11935 "&& reload_completed"
11936 [(set (reg:SI 2)
11937 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
11938 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11939 (match_dup 2)))
11940 (use (reg:SI 2))
11941 (use (reg:SI 11))
11942 (set (reg:SI 2)
11943 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11944 (clobber (reg:SI LR_REGNO))])]
11945 ""
11946 [(set_attr "type" "jmpreg")
11947 (set_attr "length" "12")])
11949 (define_insn "*call_value_indirect_nonlocal_aix32"
11950 [(set (match_operand 0 "" "")
11951 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11952 (match_operand 2 "" "g,g")))
11953 (use (reg:SI 2))
11954 (use (reg:SI 11))
11955 (set (reg:SI 2)
11956 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11957 (clobber (reg:SI LR_REGNO))]
11958 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11959 "b%T1l\;{l|lwz} 2,20(1)"
11960 [(set_attr "type" "jmpreg")
11961 (set_attr "length" "8")])
11963 (define_insn "*call_value_nonlocal_aix32"
11964 [(set (match_operand 0 "" "")
11965 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11966 (match_operand 2 "" "g")))
11967 (use (match_operand:SI 3 "immediate_operand" "O"))
11968 (clobber (reg:SI LR_REGNO))]
11969 "TARGET_32BIT
11970 && DEFAULT_ABI == ABI_AIX
11971 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11972 "bl %z1\;%."
11973 [(set_attr "type" "branch")
11974 (set_attr "length" "8")])
11976 (define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
11977 [(set (match_operand 0 "" "")
11978 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11979 (match_operand 2 "" "g,g")))
11980 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
11981 (const_int 8))))
11982 (use (reg:DI 11))
11983 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11984 (clobber (reg:SI LR_REGNO))]
11985 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11986 "#"
11987 "&& reload_completed"
11988 [(set (reg:DI 2)
11989 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
11990 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11991 (match_dup 2)))
11992 (use (reg:DI 2))
11993 (use (reg:DI 11))
11994 (set (reg:DI 2)
11995 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11996 (clobber (reg:SI LR_REGNO))])]
11997 ""
11998 [(set_attr "type" "jmpreg")
11999 (set_attr "length" "12")])
12001 (define_insn "*call_value_indirect_nonlocal_aix64"
12002 [(set (match_operand 0 "" "")
12003 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
12004 (match_operand 2 "" "g,g")))
12005 (use (reg:DI 2))
12006 (use (reg:DI 11))
12007 (set (reg:DI 2)
12008 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12009 (clobber (reg:SI LR_REGNO))]
12010 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12011 "b%T1l\;ld 2,40(1)"
12012 [(set_attr "type" "jmpreg")
12013 (set_attr "length" "8")])
12015 (define_insn "*call_value_nonlocal_aix64"
12016 [(set (match_operand 0 "" "")
12017 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12018 (match_operand 2 "" "g")))
12019 (use (match_operand:SI 3 "immediate_operand" "O"))
12020 (clobber (reg:SI LR_REGNO))]
12021 "TARGET_64BIT
12022 && DEFAULT_ABI == ABI_AIX
12023 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12024 "bl %z1\;%."
12025 [(set_attr "type" "branch")
12026 (set_attr "length" "8")])
12028 ;; A function pointer under System V is just a normal pointer
12029 ;; operands[0] is the function pointer
12030 ;; operands[1] is the stack size to clean up
12031 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12032 ;; which indicates how to set cr1
12034 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12035 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12036 (match_operand 1 "" "g,g,g,g"))
12037 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12038 (clobber (reg:SI LR_REGNO))]
12039 "DEFAULT_ABI == ABI_V4
12040 || DEFAULT_ABI == ABI_DARWIN"
12041 {
12042 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12043 output_asm_insn ("crxor 6,6,6", operands);
12045 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12046 output_asm_insn ("creqv 6,6,6", operands);
12048 return "b%T0l";
12049 }
12050 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12051 (set_attr "length" "4,4,8,8")])
12053 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12054 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12055 (match_operand 1 "" "g,g"))
12056 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12057 (clobber (reg:SI LR_REGNO))]
12058 "(DEFAULT_ABI == ABI_DARWIN
12059 || (DEFAULT_ABI == ABI_V4
12060 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12061 {
12062 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12063 output_asm_insn ("crxor 6,6,6", operands);
12065 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12066 output_asm_insn ("creqv 6,6,6", operands);
12068 #if TARGET_MACHO
12069 return output_call(insn, operands, 0, 2);
12070 #else
12071 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12072 {
12073 gcc_assert (!TARGET_SECURE_PLT);
12074 return "bl %z0@plt";
12075 }
12076 else
12077 return "bl %z0";
12078 #endif
12079 }
12080 "DEFAULT_ABI == ABI_V4
12081 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12082 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12083 [(parallel [(call (mem:SI (match_dup 0))
12084 (match_dup 1))
12085 (use (match_dup 2))
12086 (use (match_dup 3))
12087 (clobber (reg:SI LR_REGNO))])]
12088 {
12089 operands[3] = pic_offset_table_rtx;
12090 }
12091 [(set_attr "type" "branch,branch")
12092 (set_attr "length" "4,8")])
12094 (define_insn "*call_nonlocal_sysv_secure<mode>"
12095 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12096 (match_operand 1 "" "g,g"))
12097 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12098 (use (match_operand:SI 3 "register_operand" "r,r"))
12099 (clobber (reg:SI LR_REGNO))]
12100 "(DEFAULT_ABI == ABI_V4
12101 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12102 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12103 {
12104 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12105 output_asm_insn ("crxor 6,6,6", operands);
12107 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12108 output_asm_insn ("creqv 6,6,6", operands);
12110 if (flag_pic == 2)
12111 /* The magic 32768 offset here and in the other sysv call insns
12112 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12113 See sysv4.h:toc_section. */
12114 return "bl %z0+32768@plt";
12115 else
12116 return "bl %z0@plt";
12117 }
12118 [(set_attr "type" "branch,branch")
12119 (set_attr "length" "4,8")])
12121 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12122 [(set (match_operand 0 "" "")
12123 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12124 (match_operand 2 "" "g,g,g,g")))
12125 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12126 (clobber (reg:SI LR_REGNO))]
12127 "DEFAULT_ABI == ABI_V4
12128 || DEFAULT_ABI == ABI_DARWIN"
12129 {
12130 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12131 output_asm_insn ("crxor 6,6,6", operands);
12133 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12134 output_asm_insn ("creqv 6,6,6", operands);
12136 return "b%T1l";
12137 }
12138 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12139 (set_attr "length" "4,4,8,8")])
12141 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12142 [(set (match_operand 0 "" "")
12143 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12144 (match_operand 2 "" "g,g")))
12145 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12146 (clobber (reg:SI LR_REGNO))]
12147 "(DEFAULT_ABI == ABI_DARWIN
12148 || (DEFAULT_ABI == ABI_V4
12149 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12150 {
12151 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12152 output_asm_insn ("crxor 6,6,6", operands);
12154 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12155 output_asm_insn ("creqv 6,6,6", operands);
12157 #if TARGET_MACHO
12158 return output_call(insn, operands, 1, 3);
12159 #else
12160 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12161 {
12162 gcc_assert (!TARGET_SECURE_PLT);
12163 return "bl %z1@plt";
12164 }
12165 else
12166 return "bl %z1";
12167 #endif
12168 }
12169 "DEFAULT_ABI == ABI_V4
12170 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12171 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12172 [(parallel [(set (match_dup 0)
12173 (call (mem:SI (match_dup 1))
12174 (match_dup 2)))
12175 (use (match_dup 3))
12176 (use (match_dup 4))
12177 (clobber (reg:SI LR_REGNO))])]
12178 {
12179 operands[4] = pic_offset_table_rtx;
12180 }
12181 [(set_attr "type" "branch,branch")
12182 (set_attr "length" "4,8")])
12184 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12185 [(set (match_operand 0 "" "")
12186 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12187 (match_operand 2 "" "g,g")))
12188 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12189 (use (match_operand:SI 4 "register_operand" "r,r"))
12190 (clobber (reg:SI LR_REGNO))]
12191 "(DEFAULT_ABI == ABI_V4
12192 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12193 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12194 {
12195 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12196 output_asm_insn ("crxor 6,6,6", operands);
12198 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12199 output_asm_insn ("creqv 6,6,6", operands);
12201 if (flag_pic == 2)
12202 return "bl %z1+32768@plt";
12203 else
12204 return "bl %z1@plt";
12205 }
12206 [(set_attr "type" "branch,branch")
12207 (set_attr "length" "4,8")])
12209 ;; Call subroutine returning any type.
12210 (define_expand "untyped_call"
12211 [(parallel [(call (match_operand 0 "" "")
12212 (const_int 0))
12213 (match_operand 1 "" "")
12214 (match_operand 2 "" "")])]
12215 ""
12216 "
12217 {
12218 int i;
12220 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12222 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12223 {
12224 rtx set = XVECEXP (operands[2], 0, i);
12225 emit_move_insn (SET_DEST (set), SET_SRC (set));
12226 }
12228 /* The optimizer does not know that the call sets the function value
12229 registers we stored in the result block. We avoid problems by
12230 claiming that all hard registers are used and clobbered at this
12231 point. */
12232 emit_insn (gen_blockage ());
12234 DONE;
12235 }")
12237 ;; sibling call patterns
12238 (define_expand "sibcall"
12239 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12240 (match_operand 1 "" ""))
12241 (use (match_operand 2 "" ""))
12242 (use (reg:SI LR_REGNO))
12243 (return)])]
12244 ""
12245 "
12246 {
12247 #if TARGET_MACHO
12248 if (MACHOPIC_INDIRECT)
12249 operands[0] = machopic_indirect_call_target (operands[0]);
12250 #endif
12252 gcc_assert (GET_CODE (operands[0]) == MEM);
12253 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12255 operands[0] = XEXP (operands[0], 0);
12256 }")
12258 ;; this and similar patterns must be marked as using LR, otherwise
12259 ;; dataflow will try to delete the store into it. This is true
12260 ;; even when the actual reg to jump to is in CTR, when LR was
12261 ;; saved and restored around the PIC-setting BCL.
12262 (define_insn "*sibcall_local32"
12263 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12264 (match_operand 1 "" "g,g"))
12265 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12266 (use (reg:SI LR_REGNO))
12267 (return)]
12268 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12269 "*
12270 {
12271 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12272 output_asm_insn (\"crxor 6,6,6\", operands);
12274 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12275 output_asm_insn (\"creqv 6,6,6\", operands);
12277 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12278 }"
12279 [(set_attr "type" "branch")
12280 (set_attr "length" "4,8")])
12282 (define_insn "*sibcall_local64"
12283 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12284 (match_operand 1 "" "g,g"))
12285 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12286 (use (reg:SI LR_REGNO))
12287 (return)]
12288 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12289 "*
12290 {
12291 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12292 output_asm_insn (\"crxor 6,6,6\", operands);
12294 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12295 output_asm_insn (\"creqv 6,6,6\", operands);
12297 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12298 }"
12299 [(set_attr "type" "branch")
12300 (set_attr "length" "4,8")])
12302 (define_insn "*sibcall_value_local32"
12303 [(set (match_operand 0 "" "")
12304 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12305 (match_operand 2 "" "g,g")))
12306 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12307 (use (reg:SI LR_REGNO))
12308 (return)]
12309 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12310 "*
12311 {
12312 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12313 output_asm_insn (\"crxor 6,6,6\", operands);
12315 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12316 output_asm_insn (\"creqv 6,6,6\", operands);
12318 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12319 }"
12320 [(set_attr "type" "branch")
12321 (set_attr "length" "4,8")])
12324 (define_insn "*sibcall_value_local64"
12325 [(set (match_operand 0 "" "")
12326 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12327 (match_operand 2 "" "g,g")))
12328 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12329 (use (reg:SI LR_REGNO))
12330 (return)]
12331 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12332 "*
12333 {
12334 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12335 output_asm_insn (\"crxor 6,6,6\", operands);
12337 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12338 output_asm_insn (\"creqv 6,6,6\", operands);
12340 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12341 }"
12342 [(set_attr "type" "branch")
12343 (set_attr "length" "4,8")])
12345 (define_insn "*sibcall_nonlocal_aix32"
12346 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12347 (match_operand 1 "" "g"))
12348 (use (match_operand:SI 2 "immediate_operand" "O"))
12349 (use (reg:SI LR_REGNO))
12350 (return)]
12351 "TARGET_32BIT
12352 && DEFAULT_ABI == ABI_AIX
12353 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12354 "b %z0"
12355 [(set_attr "type" "branch")
12356 (set_attr "length" "4")])
12358 (define_insn "*sibcall_nonlocal_aix64"
12359 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12360 (match_operand 1 "" "g"))
12361 (use (match_operand:SI 2 "immediate_operand" "O"))
12362 (use (reg:SI LR_REGNO))
12363 (return)]
12364 "TARGET_64BIT
12365 && DEFAULT_ABI == ABI_AIX
12366 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12367 "b %z0"
12368 [(set_attr "type" "branch")
12369 (set_attr "length" "4")])
12371 (define_insn "*sibcall_value_nonlocal_aix32"
12372 [(set (match_operand 0 "" "")
12373 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12374 (match_operand 2 "" "g")))
12375 (use (match_operand:SI 3 "immediate_operand" "O"))
12376 (use (reg:SI LR_REGNO))
12377 (return)]
12378 "TARGET_32BIT
12379 && DEFAULT_ABI == ABI_AIX
12380 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12381 "b %z1"
12382 [(set_attr "type" "branch")
12383 (set_attr "length" "4")])
12385 (define_insn "*sibcall_value_nonlocal_aix64"
12386 [(set (match_operand 0 "" "")
12387 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12388 (match_operand 2 "" "g")))
12389 (use (match_operand:SI 3 "immediate_operand" "O"))
12390 (use (reg:SI LR_REGNO))
12391 (return)]
12392 "TARGET_64BIT
12393 && DEFAULT_ABI == ABI_AIX
12394 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12395 "b %z1"
12396 [(set_attr "type" "branch")
12397 (set_attr "length" "4")])
12399 (define_insn "*sibcall_nonlocal_sysv<mode>"
12400 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12401 (match_operand 1 "" ""))
12402 (use (match_operand 2 "immediate_operand" "O,n"))
12403 (use (reg:SI LR_REGNO))
12404 (return)]
12405 "(DEFAULT_ABI == ABI_DARWIN
12406 || DEFAULT_ABI == ABI_V4)
12407 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12408 "*
12409 {
12410 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12411 output_asm_insn (\"crxor 6,6,6\", operands);
12413 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12414 output_asm_insn (\"creqv 6,6,6\", operands);
12416 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12417 {
12418 gcc_assert (!TARGET_SECURE_PLT);
12419 return \"b %z0@plt\";
12420 }
12421 else
12422 return \"b %z0\";
12423 }"
12424 [(set_attr "type" "branch,branch")
12425 (set_attr "length" "4,8")])
12427 (define_expand "sibcall_value"
12428 [(parallel [(set (match_operand 0 "register_operand" "")
12429 (call (mem:SI (match_operand 1 "address_operand" ""))
12430 (match_operand 2 "" "")))
12431 (use (match_operand 3 "" ""))
12432 (use (reg:SI LR_REGNO))
12433 (return)])]
12434 ""
12435 "
12436 {
12437 #if TARGET_MACHO
12438 if (MACHOPIC_INDIRECT)
12439 operands[1] = machopic_indirect_call_target (operands[1]);
12440 #endif
12442 gcc_assert (GET_CODE (operands[1]) == MEM);
12443 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12445 operands[1] = XEXP (operands[1], 0);
12446 }")
12448 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12449 [(set (match_operand 0 "" "")
12450 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12451 (match_operand 2 "" "")))
12452 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12453 (use (reg:SI LR_REGNO))
12454 (return)]
12455 "(DEFAULT_ABI == ABI_DARWIN
12456 || DEFAULT_ABI == ABI_V4)
12457 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12458 "*
12459 {
12460 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12461 output_asm_insn (\"crxor 6,6,6\", operands);
12463 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12464 output_asm_insn (\"creqv 6,6,6\", operands);
12466 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12467 {
12468 gcc_assert (!TARGET_SECURE_PLT);
12469 return \"b %z1@plt\";
12470 }
12471 else
12472 return \"b %z1\";
12473 }"
12474 [(set_attr "type" "branch,branch")
12475 (set_attr "length" "4,8")])
12477 (define_expand "sibcall_epilogue"
12478 [(use (const_int 0))]
12479 "TARGET_SCHED_PROLOG"
12480 "
12481 {
12482 rs6000_emit_epilogue (TRUE);
12483 DONE;
12484 }")
12486 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12487 ;; all of memory. This blocks insns from being moved across this point.
12489 (define_insn "blockage"
12490 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12491 ""
12492 "")
12494 (define_insn "probe_stack"
12495 [(set (match_operand 0 "memory_operand" "=m")
12496 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
12497 ""
12498 "{st%U0%X0|stw%U0%X0} 0,%0"
12499 [(set_attr "type" "store")
12500 (set_attr "length" "4")])
12501 \f
12502 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12503 ;; signed & unsigned, and one type of branch.
12504 ;;
12505 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12506 ;; insns, and branches.
12508 (define_expand "cbranch<mode>4"
12509 [(use (match_operator 0 "rs6000_cbranch_operator"
12510 [(match_operand:GPR 1 "gpc_reg_operand" "")
12511 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12512 (use (match_operand 3 ""))]
12513 ""
12514 "
12515 {
12516 /* Take care of the possibility that operands[2] might be negative but
12517 this might be a logical operation. That insn doesn't exist. */
12518 if (GET_CODE (operands[2]) == CONST_INT
12519 && INTVAL (operands[2]) < 0)
12520 {
12521 operands[2] = force_reg (<MODE>mode, operands[2]);
12522 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12523 GET_MODE (operands[0]),
12524 operands[1], operands[2]);
12525 }
12527 rs6000_emit_cbranch (<MODE>mode, operands);
12528 DONE;
12529 }")
12531 (define_expand "cbranch<mode>4"
12532 [(use (match_operator 0 "rs6000_cbranch_operator"
12533 [(match_operand:FP 1 "gpc_reg_operand" "")
12534 (match_operand:FP 2 "gpc_reg_operand" "")]))
12535 (use (match_operand 3 ""))]
12536 ""
12537 "
12538 {
12539 rs6000_emit_cbranch (<MODE>mode, operands);
12540 DONE;
12541 }")
12543 (define_expand "cstore<mode>4"
12544 [(use (match_operator 1 "rs6000_cbranch_operator"
12545 [(match_operand:GPR 2 "gpc_reg_operand" "")
12546 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12547 (clobber (match_operand:SI 0 "register_operand"))]
12548 ""
12549 "
12550 {
12551 /* Take care of the possibility that operands[3] might be negative but
12552 this might be a logical operation. That insn doesn't exist. */
12553 if (GET_CODE (operands[3]) == CONST_INT
12554 && INTVAL (operands[3]) < 0)
12555 {
12556 operands[3] = force_reg (<MODE>mode, operands[3]);
12557 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12558 GET_MODE (operands[1]),
12559 operands[2], operands[3]);
12560 }
12562 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12563 For SEQ, likewise, except that comparisons with zero should be done
12564 with an scc insns. However, due to the order that combine see the
12565 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12566 the cases we don't want to handle or are best handled by portable
12567 code. */
12568 if (GET_CODE (operands[1]) == NE)
12569 FAIL;
12570 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12571 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12572 && operands[3] == const0_rtx)
12573 FAIL;
12574 rs6000_emit_sCOND (<MODE>mode, operands);
12575 DONE;
12576 }")
12578 (define_expand "cstore<mode>4"
12579 [(use (match_operator 1 "rs6000_cbranch_operator"
12580 [(match_operand:FP 2 "gpc_reg_operand" "")
12581 (match_operand:FP 3 "gpc_reg_operand" "")]))
12582 (clobber (match_operand:SI 0 "register_operand"))]
12583 ""
12584 "
12585 {
12586 rs6000_emit_sCOND (<MODE>mode, operands);
12587 DONE;
12588 }")
12591 (define_expand "stack_protect_set"
12592 [(match_operand 0 "memory_operand" "")
12593 (match_operand 1 "memory_operand" "")]
12594 ""
12595 {
12596 #ifdef TARGET_THREAD_SSP_OFFSET
12597 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12598 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12599 operands[1] = gen_rtx_MEM (Pmode, addr);
12600 #endif
12601 if (TARGET_64BIT)
12602 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12603 else
12604 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12605 DONE;
12606 })
12608 (define_insn "stack_protect_setsi"
12609 [(set (match_operand:SI 0 "memory_operand" "=m")
12610 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12611 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12612 "TARGET_32BIT"
12613 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
12614 [(set_attr "type" "three")
12615 (set_attr "length" "12")])
12617 (define_insn "stack_protect_setdi"
12618 [(set (match_operand:DI 0 "memory_operand" "=m")
12619 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12620 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12621 "TARGET_64BIT"
12622 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
12623 [(set_attr "type" "three")
12624 (set_attr "length" "12")])
12626 (define_expand "stack_protect_test"
12627 [(match_operand 0 "memory_operand" "")
12628 (match_operand 1 "memory_operand" "")
12629 (match_operand 2 "" "")]
12630 ""
12631 {
12632 rtx test, op0, op1;
12633 #ifdef TARGET_THREAD_SSP_OFFSET
12634 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12635 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12636 operands[1] = gen_rtx_MEM (Pmode, addr);
12637 #endif
12638 op0 = operands[0];
12639 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12640 test = gen_rtx_EQ (VOIDmode, op0, op1);
12641 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12642 DONE;
12643 })
12645 (define_insn "stack_protect_testsi"
12646 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12647 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12648 (match_operand:SI 2 "memory_operand" "m,m")]
12649 UNSPEC_SP_TEST))
12650 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12651 (clobber (match_scratch:SI 3 "=&r,&r"))]
12652 "TARGET_32BIT"
12653 "@
12654 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12655 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12656 [(set_attr "length" "16,20")])
12658 (define_insn "stack_protect_testdi"
12659 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12660 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
12661 (match_operand:DI 2 "memory_operand" "m,m")]
12662 UNSPEC_SP_TEST))
12663 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12664 (clobber (match_scratch:DI 3 "=&r,&r"))]
12665 "TARGET_64BIT"
12666 "@
12667 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12668 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12669 [(set_attr "length" "16,20")])
12671 \f
12672 ;; Here are the actual compare insns.
12673 (define_insn "*cmp<mode>_internal1"
12674 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12675 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12676 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12677 ""
12678 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
12679 [(set_attr "type" "cmp")])
12681 ;; If we are comparing a register for equality with a large constant,
12682 ;; we can do this with an XOR followed by a compare. But this is profitable
12683 ;; only if the large constant is only used for the comparison (and in this
12684 ;; case we already have a register to reuse as scratch).
12685 ;;
12686 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12687 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12689 (define_peephole2
12690 [(set (match_operand:SI 0 "register_operand")
12691 (match_operand:SI 1 "logical_const_operand" ""))
12692 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12693 [(match_dup 0)
12694 (match_operand:SI 2 "logical_const_operand" "")]))
12695 (set (match_operand:CC 4 "cc_reg_operand" "")
12696 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12697 (match_dup 0)))
12698 (set (pc)
12699 (if_then_else (match_operator 6 "equality_operator"
12700 [(match_dup 4) (const_int 0)])
12701 (match_operand 7 "" "")
12702 (match_operand 8 "" "")))]
12703 "peep2_reg_dead_p (3, operands[0])
12704 && peep2_reg_dead_p (4, operands[4])"
12705 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12706 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12707 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12709 {
12710 /* Get the constant we are comparing against, and see what it looks like
12711 when sign-extended from 16 to 32 bits. Then see what constant we could
12712 XOR with SEXTC to get the sign-extended value. */
12713 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12714 SImode,
12715 operands[1], operands[2]);
12716 HOST_WIDE_INT c = INTVAL (cnst);
12717 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12718 HOST_WIDE_INT xorv = c ^ sextc;
12720 operands[9] = GEN_INT (xorv);
12721 operands[10] = GEN_INT (sextc);
12722 })
12724 (define_insn "*cmpsi_internal2"
12725 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12726 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12727 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12728 ""
12729 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
12730 [(set_attr "type" "cmp")])
12732 (define_insn "*cmpdi_internal2"
12733 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12734 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12735 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12736 ""
12737 "cmpld%I2 %0,%1,%b2"
12738 [(set_attr "type" "cmp")])
12740 ;; The following two insns don't exist as single insns, but if we provide
12741 ;; them, we can swap an add and compare, which will enable us to overlap more
12742 ;; of the required delay between a compare and branch. We generate code for
12743 ;; them by splitting.
12745 (define_insn ""
12746 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12747 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12748 (match_operand:SI 2 "short_cint_operand" "i")))
12749 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12750 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12751 ""
12752 "#"
12753 [(set_attr "length" "8")])
12755 (define_insn ""
12756 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12757 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12758 (match_operand:SI 2 "u_short_cint_operand" "i")))
12759 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12760 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12761 ""
12762 "#"
12763 [(set_attr "length" "8")])
12765 (define_split
12766 [(set (match_operand:CC 3 "cc_reg_operand" "")
12767 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12768 (match_operand:SI 2 "short_cint_operand" "")))
12769 (set (match_operand:SI 0 "gpc_reg_operand" "")
12770 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12771 ""
12772 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12773 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12775 (define_split
12776 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12777 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12778 (match_operand:SI 2 "u_short_cint_operand" "")))
12779 (set (match_operand:SI 0 "gpc_reg_operand" "")
12780 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12781 ""
12782 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12783 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12785 (define_insn "*cmpsf_internal1"
12786 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12787 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12788 (match_operand:SF 2 "gpc_reg_operand" "f")))]
12789 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12790 "fcmpu %0,%1,%2"
12791 [(set_attr "type" "fpcompare")])
12793 (define_insn "*cmpdf_internal1"
12794 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12795 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12796 (match_operand:DF 2 "gpc_reg_operand" "d")))]
12797 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
12798 && !VECTOR_UNIT_VSX_P (DFmode)"
12799 "fcmpu %0,%1,%2"
12800 [(set_attr "type" "fpcompare")])
12802 ;; Only need to compare second words if first words equal
12803 (define_insn "*cmptf_internal1"
12804 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12805 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12806 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12807 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12808 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12809 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12810 [(set_attr "type" "fpcompare")
12811 (set_attr "length" "12")])
12813 (define_insn_and_split "*cmptf_internal2"
12814 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12815 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12816 (match_operand:TF 2 "gpc_reg_operand" "d")))
12817 (clobber (match_scratch:DF 3 "=d"))
12818 (clobber (match_scratch:DF 4 "=d"))
12819 (clobber (match_scratch:DF 5 "=d"))
12820 (clobber (match_scratch:DF 6 "=d"))
12821 (clobber (match_scratch:DF 7 "=d"))
12822 (clobber (match_scratch:DF 8 "=d"))
12823 (clobber (match_scratch:DF 9 "=d"))
12824 (clobber (match_scratch:DF 10 "=d"))]
12825 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12826 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12827 "#"
12828 "&& reload_completed"
12829 [(set (match_dup 3) (match_dup 13))
12830 (set (match_dup 4) (match_dup 14))
12831 (set (match_dup 9) (abs:DF (match_dup 5)))
12832 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12833 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12834 (label_ref (match_dup 11))
12835 (pc)))
12836 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12837 (set (pc) (label_ref (match_dup 12)))
12838 (match_dup 11)
12839 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12840 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12841 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12842 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
12843 (match_dup 12)]
12844 {
12845 REAL_VALUE_TYPE rv;
12846 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12847 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12849 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12850 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12851 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12852 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12853 operands[11] = gen_label_rtx ();
12854 operands[12] = gen_label_rtx ();
12855 real_inf (&rv);
12856 operands[13] = force_const_mem (DFmode,
12857 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12858 operands[14] = force_const_mem (DFmode,
12859 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12860 DFmode));
12861 if (TARGET_TOC)
12862 {
12863 operands[13] = gen_const_mem (DFmode,
12864 create_TOC_reference (XEXP (operands[13], 0)));
12865 operands[14] = gen_const_mem (DFmode,
12866 create_TOC_reference (XEXP (operands[14], 0)));
12867 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12868 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12869 }
12870 })
12871 \f
12872 ;; Now we have the scc insns. We can do some combinations because of the
12873 ;; way the machine works.
12874 ;;
12875 ;; Note that this is probably faster if we can put an insn between the
12876 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12877 ;; cases the insns below which don't use an intermediate CR field will
12878 ;; be used instead.
12879 (define_insn ""
12880 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12881 (match_operator:SI 1 "scc_comparison_operator"
12882 [(match_operand 2 "cc_reg_operand" "y")
12883 (const_int 0)]))]
12884 ""
12885 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12886 [(set (attr "type")
12887 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12888 (const_string "mfcrf")
12889 ]
12890 (const_string "mfcr")))
12891 (set_attr "length" "8")])
12893 ;; Same as above, but get the GT bit.
12894 (define_insn "move_from_CR_gt_bit"
12895 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12896 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12897 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12898 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12899 [(set_attr "type" "mfcr")
12900 (set_attr "length" "8")])
12902 ;; Same as above, but get the OV/ORDERED bit.
12903 (define_insn "move_from_CR_ov_bit"
12904 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12905 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12906 "TARGET_ISEL"
12907 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12908 [(set_attr "type" "mfcr")
12909 (set_attr "length" "8")])
12911 (define_insn ""
12912 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12913 (match_operator:DI 1 "scc_comparison_operator"
12914 [(match_operand 2 "cc_reg_operand" "y")
12915 (const_int 0)]))]
12916 "TARGET_POWERPC64"
12917 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12918 [(set (attr "type")
12919 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12920 (const_string "mfcrf")
12921 ]
12922 (const_string "mfcr")))
12923 (set_attr "length" "8")])
12925 (define_insn ""
12926 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12927 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12928 [(match_operand 2 "cc_reg_operand" "y,y")
12929 (const_int 0)])
12930 (const_int 0)))
12931 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12932 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12933 "TARGET_32BIT"
12934 "@
12935 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12936 #"
12937 [(set_attr "type" "delayed_compare")
12938 (set_attr "length" "8,16")])
12940 (define_split
12941 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12942 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12943 [(match_operand 2 "cc_reg_operand" "")
12944 (const_int 0)])
12945 (const_int 0)))
12946 (set (match_operand:SI 3 "gpc_reg_operand" "")
12947 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12948 "TARGET_32BIT && reload_completed"
12949 [(set (match_dup 3)
12950 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12951 (set (match_dup 0)
12952 (compare:CC (match_dup 3)
12953 (const_int 0)))]
12954 "")
12956 (define_insn ""
12957 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12958 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12959 [(match_operand 2 "cc_reg_operand" "y")
12960 (const_int 0)])
12961 (match_operand:SI 3 "const_int_operand" "n")))]
12962 ""
12963 "*
12964 {
12965 int is_bit = ccr_bit (operands[1], 1);
12966 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12967 int count;
12969 if (is_bit >= put_bit)
12970 count = is_bit - put_bit;
12971 else
12972 count = 32 - (put_bit - is_bit);
12974 operands[4] = GEN_INT (count);
12975 operands[5] = GEN_INT (put_bit);
12977 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12978 }"
12979 [(set (attr "type")
12980 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12981 (const_string "mfcrf")
12982 ]
12983 (const_string "mfcr")))
12984 (set_attr "length" "8")])
12986 (define_insn ""
12987 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12988 (compare:CC
12989 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12990 [(match_operand 2 "cc_reg_operand" "y,y")
12991 (const_int 0)])
12992 (match_operand:SI 3 "const_int_operand" "n,n"))
12993 (const_int 0)))
12994 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12995 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12996 (match_dup 3)))]
12997 ""
12998 "*
12999 {
13000 int is_bit = ccr_bit (operands[1], 1);
13001 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13002 int count;
13004 /* Force split for non-cc0 compare. */
13005 if (which_alternative == 1)
13006 return \"#\";
13008 if (is_bit >= put_bit)
13009 count = is_bit - put_bit;
13010 else
13011 count = 32 - (put_bit - is_bit);
13013 operands[5] = GEN_INT (count);
13014 operands[6] = GEN_INT (put_bit);
13016 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
13017 }"
13018 [(set_attr "type" "delayed_compare")
13019 (set_attr "length" "8,16")])
13021 (define_split
13022 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13023 (compare:CC
13024 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13025 [(match_operand 2 "cc_reg_operand" "")
13026 (const_int 0)])
13027 (match_operand:SI 3 "const_int_operand" ""))
13028 (const_int 0)))
13029 (set (match_operand:SI 4 "gpc_reg_operand" "")
13030 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13031 (match_dup 3)))]
13032 "reload_completed"
13033 [(set (match_dup 4)
13034 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13035 (match_dup 3)))
13036 (set (match_dup 0)
13037 (compare:CC (match_dup 4)
13038 (const_int 0)))]
13039 "")
13041 ;; There is a 3 cycle delay between consecutive mfcr instructions
13042 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13044 (define_peephole
13045 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13046 (match_operator:SI 1 "scc_comparison_operator"
13047 [(match_operand 2 "cc_reg_operand" "y")
13048 (const_int 0)]))
13049 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13050 (match_operator:SI 4 "scc_comparison_operator"
13051 [(match_operand 5 "cc_reg_operand" "y")
13052 (const_int 0)]))]
13053 "REGNO (operands[2]) != REGNO (operands[5])"
13054 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13055 [(set_attr "type" "mfcr")
13056 (set_attr "length" "12")])
13058 (define_peephole
13059 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13060 (match_operator:DI 1 "scc_comparison_operator"
13061 [(match_operand 2 "cc_reg_operand" "y")
13062 (const_int 0)]))
13063 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13064 (match_operator:DI 4 "scc_comparison_operator"
13065 [(match_operand 5 "cc_reg_operand" "y")
13066 (const_int 0)]))]
13067 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13068 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13069 [(set_attr "type" "mfcr")
13070 (set_attr "length" "12")])
13072 ;; There are some scc insns that can be done directly, without a compare.
13073 ;; These are faster because they don't involve the communications between
13074 ;; the FXU and branch units. In fact, we will be replacing all of the
13075 ;; integer scc insns here or in the portable methods in emit_store_flag.
13076 ;;
13077 ;; Also support (neg (scc ..)) since that construct is used to replace
13078 ;; branches, (plus (scc ..) ..) since that construct is common and
13079 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13080 ;; cases where it is no more expensive than (neg (scc ..)).
13082 ;; Have reload force a constant into a register for the simple insns that
13083 ;; otherwise won't accept constants. We do this because it is faster than
13084 ;; the cmp/mfcr sequence we would otherwise generate.
13086 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13087 (DI "rKJI")])
13089 (define_insn_and_split "*eq<mode>"
13090 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13091 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13092 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13093 "!TARGET_POWER"
13094 "#"
13095 "!TARGET_POWER"
13096 [(set (match_dup 0)
13097 (clz:GPR (match_dup 3)))
13098 (set (match_dup 0)
13099 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13100 {
13101 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13102 {
13103 /* Use output operand as intermediate. */
13104 operands[3] = operands[0];
13106 if (logical_operand (operands[2], <MODE>mode))
13107 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13108 gen_rtx_XOR (<MODE>mode,
13109 operands[1], operands[2])));
13110 else
13111 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13112 gen_rtx_PLUS (<MODE>mode, operands[1],
13113 negate_rtx (<MODE>mode,
13114 operands[2]))));
13115 }
13116 else
13117 operands[3] = operands[1];
13119 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13120 })
13122 (define_insn_and_split "*eq<mode>_compare"
13123 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13124 (compare:CC
13125 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13126 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13127 (const_int 0)))
13128 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13129 (eq:P (match_dup 1) (match_dup 2)))]
13130 "!TARGET_POWER && optimize_size"
13131 "#"
13132 "!TARGET_POWER && optimize_size"
13133 [(set (match_dup 0)
13134 (clz:P (match_dup 4)))
13135 (parallel [(set (match_dup 3)
13136 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13137 (const_int 0)))
13138 (set (match_dup 0)
13139 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13140 {
13141 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13142 {
13143 /* Use output operand as intermediate. */
13144 operands[4] = operands[0];
13146 if (logical_operand (operands[2], <MODE>mode))
13147 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13148 gen_rtx_XOR (<MODE>mode,
13149 operands[1], operands[2])));
13150 else
13151 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13152 gen_rtx_PLUS (<MODE>mode, operands[1],
13153 negate_rtx (<MODE>mode,
13154 operands[2]))));
13155 }
13156 else
13157 operands[4] = operands[1];
13159 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13160 })
13162 (define_insn "*eqsi_power"
13163 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
13164 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13165 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
13166 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
13167 "TARGET_POWER"
13168 "@
13169 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13170 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
13171 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13172 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13173 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
13174 [(set_attr "type" "three,two,three,three,three")
13175 (set_attr "length" "12,8,12,12,12")])
13177 ;; We have insns of the form shown by the first define_insn below. If
13178 ;; there is something inside the comparison operation, we must split it.
13179 (define_split
13180 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13181 (plus:SI (match_operator 1 "comparison_operator"
13182 [(match_operand:SI 2 "" "")
13183 (match_operand:SI 3
13184 "reg_or_cint_operand" "")])
13185 (match_operand:SI 4 "gpc_reg_operand" "")))
13186 (clobber (match_operand:SI 5 "register_operand" ""))]
13187 "! gpc_reg_operand (operands[2], SImode)"
13188 [(set (match_dup 5) (match_dup 2))
13189 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
13190 (match_dup 4)))])
13192 (define_insn "*plus_eqsi"
13193 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13194 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13195 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13196 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13197 "TARGET_32BIT"
13198 "@
13199 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13200 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
13201 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13202 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13203 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13204 [(set_attr "type" "three,two,three,three,three")
13205 (set_attr "length" "12,8,12,12,12")])
13207 (define_insn "*compare_plus_eqsi"
13208 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13209 (compare:CC
13210 (plus:SI
13211 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13212 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13213 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13214 (const_int 0)))
13215 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13216 "TARGET_32BIT && optimize_size"
13217 "@
13218 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13219 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
13220 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13221 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13222 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13223 #
13224 #
13225 #
13226 #
13227 #"
13228 [(set_attr "type" "compare")
13229 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13231 (define_split
13232 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13233 (compare:CC
13234 (plus:SI
13235 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13236 (match_operand:SI 2 "scc_eq_operand" ""))
13237 (match_operand:SI 3 "gpc_reg_operand" ""))
13238 (const_int 0)))
13239 (clobber (match_scratch:SI 4 ""))]
13240 "TARGET_32BIT && optimize_size && reload_completed"
13241 [(set (match_dup 4)
13242 (plus:SI (eq:SI (match_dup 1)
13243 (match_dup 2))
13244 (match_dup 3)))
13245 (set (match_dup 0)
13246 (compare:CC (match_dup 4)
13247 (const_int 0)))]
13248 "")
13250 (define_insn "*plus_eqsi_compare"
13251 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13252 (compare:CC
13253 (plus:SI
13254 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13255 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13256 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13257 (const_int 0)))
13258 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13259 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13260 "TARGET_32BIT && optimize_size"
13261 "@
13262 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13263 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
13264 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13265 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13266 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13267 #
13268 #
13269 #
13270 #
13271 #"
13272 [(set_attr "type" "compare")
13273 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13275 (define_split
13276 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13277 (compare:CC
13278 (plus:SI
13279 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13280 (match_operand:SI 2 "scc_eq_operand" ""))
13281 (match_operand:SI 3 "gpc_reg_operand" ""))
13282 (const_int 0)))
13283 (set (match_operand:SI 0 "gpc_reg_operand" "")
13284 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13285 "TARGET_32BIT && optimize_size && reload_completed"
13286 [(set (match_dup 0)
13287 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13288 (set (match_dup 4)
13289 (compare:CC (match_dup 0)
13290 (const_int 0)))]
13291 "")
13293 (define_insn "*neg_eq0<mode>"
13294 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13295 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13296 (const_int 0))))]
13297 ""
13298 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
13299 [(set_attr "type" "two")
13300 (set_attr "length" "8")])
13302 (define_insn_and_split "*neg_eq<mode>"
13303 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13304 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13305 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13306 ""
13307 "#"
13308 ""
13309 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13310 {
13311 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13312 {
13313 /* Use output operand as intermediate. */
13314 operands[3] = operands[0];
13316 if (logical_operand (operands[2], <MODE>mode))
13317 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13318 gen_rtx_XOR (<MODE>mode,
13319 operands[1], operands[2])));
13320 else
13321 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13322 gen_rtx_PLUS (<MODE>mode, operands[1],
13323 negate_rtx (<MODE>mode,
13324 operands[2]))));
13325 }
13326 else
13327 operands[3] = operands[1];
13328 })
13330 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
13331 ;; since it nabs/sr is just as fast.
13332 (define_insn "*ne0si"
13333 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13334 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13335 (const_int 31)))
13336 (clobber (match_scratch:SI 2 "=&r"))]
13337 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
13338 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
13339 [(set_attr "type" "two")
13340 (set_attr "length" "8")])
13342 (define_insn "*ne0di"
13343 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13344 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13345 (const_int 63)))
13346 (clobber (match_scratch:DI 2 "=&r"))]
13347 "TARGET_64BIT"
13348 "addic %2,%1,-1\;subfe %0,%2,%1"
13349 [(set_attr "type" "two")
13350 (set_attr "length" "8")])
13352 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
13353 (define_insn "*plus_ne0si"
13354 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13355 (plus:SI (lshiftrt:SI
13356 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13357 (const_int 31))
13358 (match_operand:SI 2 "gpc_reg_operand" "r")))
13359 (clobber (match_scratch:SI 3 "=&r"))]
13360 "TARGET_32BIT"
13361 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
13362 [(set_attr "type" "two")
13363 (set_attr "length" "8")])
13365 (define_insn "*plus_ne0di"
13366 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13367 (plus:DI (lshiftrt:DI
13368 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13369 (const_int 63))
13370 (match_operand:DI 2 "gpc_reg_operand" "r")))
13371 (clobber (match_scratch:DI 3 "=&r"))]
13372 "TARGET_64BIT"
13373 "addic %3,%1,-1\;addze %0,%2"
13374 [(set_attr "type" "two")
13375 (set_attr "length" "8")])
13377 (define_insn "*compare_plus_ne0si"
13378 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13379 (compare:CC
13380 (plus:SI (lshiftrt:SI
13381 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13382 (const_int 31))
13383 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13384 (const_int 0)))
13385 (clobber (match_scratch:SI 3 "=&r,&r"))
13386 (clobber (match_scratch:SI 4 "=X,&r"))]
13387 "TARGET_32BIT"
13388 "@
13389 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
13390 #"
13391 [(set_attr "type" "compare")
13392 (set_attr "length" "8,12")])
13394 (define_split
13395 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13396 (compare:CC
13397 (plus:SI (lshiftrt:SI
13398 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13399 (const_int 31))
13400 (match_operand:SI 2 "gpc_reg_operand" ""))
13401 (const_int 0)))
13402 (clobber (match_scratch:SI 3 ""))
13403 (clobber (match_scratch:SI 4 ""))]
13404 "TARGET_32BIT && reload_completed"
13405 [(parallel [(set (match_dup 3)
13406 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
13407 (const_int 31))
13408 (match_dup 2)))
13409 (clobber (match_dup 4))])
13410 (set (match_dup 0)
13411 (compare:CC (match_dup 3)
13412 (const_int 0)))]
13413 "")
13415 (define_insn "*compare_plus_ne0di"
13416 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13417 (compare:CC
13418 (plus:DI (lshiftrt:DI
13419 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13420 (const_int 63))
13421 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13422 (const_int 0)))
13423 (clobber (match_scratch:DI 3 "=&r,&r"))]
13424 "TARGET_64BIT"
13425 "@
13426 addic %3,%1,-1\;addze. %3,%2
13427 #"
13428 [(set_attr "type" "compare")
13429 (set_attr "length" "8,12")])
13431 (define_split
13432 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13433 (compare:CC
13434 (plus:DI (lshiftrt:DI
13435 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13436 (const_int 63))
13437 (match_operand:DI 2 "gpc_reg_operand" ""))
13438 (const_int 0)))
13439 (clobber (match_scratch:DI 3 ""))]
13440 "TARGET_64BIT && reload_completed"
13441 [(set (match_dup 3)
13442 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
13443 (const_int 63))
13444 (match_dup 2)))
13445 (set (match_dup 0)
13446 (compare:CC (match_dup 3)
13447 (const_int 0)))]
13448 "")
13450 (define_insn "*plus_ne0si_compare"
13451 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13452 (compare:CC
13453 (plus:SI (lshiftrt:SI
13454 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13455 (const_int 31))
13456 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13457 (const_int 0)))
13458 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13459 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13460 (match_dup 2)))
13461 (clobber (match_scratch:SI 3 "=&r,&r"))]
13462 "TARGET_32BIT"
13463 "@
13464 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
13465 #"
13466 [(set_attr "type" "compare")
13467 (set_attr "length" "8,12")])
13469 (define_split
13470 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13471 (compare:CC
13472 (plus:SI (lshiftrt:SI
13473 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13474 (const_int 31))
13475 (match_operand:SI 2 "gpc_reg_operand" ""))
13476 (const_int 0)))
13477 (set (match_operand:SI 0 "gpc_reg_operand" "")
13478 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13479 (match_dup 2)))
13480 (clobber (match_scratch:SI 3 ""))]
13481 "TARGET_32BIT && reload_completed"
13482 [(parallel [(set (match_dup 0)
13483 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13484 (match_dup 2)))
13485 (clobber (match_dup 3))])
13486 (set (match_dup 4)
13487 (compare:CC (match_dup 0)
13488 (const_int 0)))]
13489 "")
13491 (define_insn "*plus_ne0di_compare"
13492 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13493 (compare:CC
13494 (plus:DI (lshiftrt:DI
13495 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13496 (const_int 63))
13497 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13498 (const_int 0)))
13499 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13500 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13501 (match_dup 2)))
13502 (clobber (match_scratch:DI 3 "=&r,&r"))]
13503 "TARGET_64BIT"
13504 "@
13505 addic %3,%1,-1\;addze. %0,%2
13506 #"
13507 [(set_attr "type" "compare")
13508 (set_attr "length" "8,12")])
13510 (define_split
13511 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13512 (compare:CC
13513 (plus:DI (lshiftrt:DI
13514 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13515 (const_int 63))
13516 (match_operand:DI 2 "gpc_reg_operand" ""))
13517 (const_int 0)))
13518 (set (match_operand:DI 0 "gpc_reg_operand" "")
13519 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13520 (match_dup 2)))
13521 (clobber (match_scratch:DI 3 ""))]
13522 "TARGET_64BIT && reload_completed"
13523 [(parallel [(set (match_dup 0)
13524 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13525 (match_dup 2)))
13526 (clobber (match_dup 3))])
13527 (set (match_dup 4)
13528 (compare:CC (match_dup 0)
13529 (const_int 0)))]
13530 "")
13532 (define_insn ""
13533 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13534 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13535 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
13536 (clobber (match_scratch:SI 3 "=r,X"))]
13537 "TARGET_POWER"
13538 "@
13539 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
13540 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
13541 [(set_attr "length" "12")])
13543 (define_insn ""
13544 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13545 (compare:CC
13546 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13547 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13548 (const_int 0)))
13549 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
13550 (le:SI (match_dup 1) (match_dup 2)))
13551 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
13552 "TARGET_POWER"
13553 "@
13554 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13555 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
13556 #
13557 #"
13558 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
13559 (set_attr "length" "12,12,16,16")])
13561 (define_split
13562 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13563 (compare:CC
13564 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13565 (match_operand:SI 2 "reg_or_short_operand" ""))
13566 (const_int 0)))
13567 (set (match_operand:SI 0 "gpc_reg_operand" "")
13568 (le:SI (match_dup 1) (match_dup 2)))
13569 (clobber (match_scratch:SI 3 ""))]
13570 "TARGET_POWER && reload_completed"
13571 [(parallel [(set (match_dup 0)
13572 (le:SI (match_dup 1) (match_dup 2)))
13573 (clobber (match_dup 3))])
13574 (set (match_dup 4)
13575 (compare:CC (match_dup 0)
13576 (const_int 0)))]
13577 "")
13579 (define_insn ""
13580 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13581 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13582 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
13583 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13584 "TARGET_POWER"
13585 "@
13586 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13587 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
13588 [(set_attr "length" "12")])
13590 (define_insn ""
13591 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13592 (compare:CC
13593 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13594 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13595 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13596 (const_int 0)))
13597 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13598 "TARGET_POWER"
13599 "@
13600 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13601 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
13602 #
13603 #"
13604 [(set_attr "type" "compare")
13605 (set_attr "length" "12,12,16,16")])
13607 (define_split
13608 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13609 (compare:CC
13610 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13611 (match_operand:SI 2 "reg_or_short_operand" ""))
13612 (match_operand:SI 3 "gpc_reg_operand" ""))
13613 (const_int 0)))
13614 (clobber (match_scratch:SI 4 ""))]
13615 "TARGET_POWER && reload_completed"
13616 [(set (match_dup 4)
13617 (plus:SI (le:SI (match_dup 1) (match_dup 2))
13618 (match_dup 3)))
13619 (set (match_dup 0)
13620 (compare:CC (match_dup 4)
13621 (const_int 0)))]
13622 "")
13624 (define_insn ""
13625 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13626 (compare:CC
13627 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13628 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13629 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13630 (const_int 0)))
13631 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13632 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13633 "TARGET_POWER"
13634 "@
13635 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13636 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
13637 #
13638 #"
13639 [(set_attr "type" "compare")
13640 (set_attr "length" "12,12,16,16")])
13642 (define_split
13643 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13644 (compare:CC
13645 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13646 (match_operand:SI 2 "reg_or_short_operand" ""))
13647 (match_operand:SI 3 "gpc_reg_operand" ""))
13648 (const_int 0)))
13649 (set (match_operand:SI 0 "gpc_reg_operand" "")
13650 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13651 "TARGET_POWER && reload_completed"
13652 [(set (match_dup 0)
13653 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13654 (set (match_dup 4)
13655 (compare:CC (match_dup 0)
13656 (const_int 0)))]
13657 "")
13659 (define_insn ""
13660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13661 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13662 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
13663 "TARGET_POWER"
13664 "@
13665 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
13666 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
13667 [(set_attr "length" "12")])
13669 (define_insn "*leu<mode>"
13670 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13671 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13672 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13673 ""
13674 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13675 [(set_attr "type" "three")
13676 (set_attr "length" "12")])
13678 (define_insn "*leu<mode>_compare"
13679 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13680 (compare:CC
13681 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13682 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13683 (const_int 0)))
13684 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13685 (leu:P (match_dup 1) (match_dup 2)))]
13686 ""
13687 "@
13688 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13689 #"
13690 [(set_attr "type" "compare")
13691 (set_attr "length" "12,16")])
13693 (define_split
13694 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13695 (compare:CC
13696 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13697 (match_operand:P 2 "reg_or_short_operand" ""))
13698 (const_int 0)))
13699 (set (match_operand:P 0 "gpc_reg_operand" "")
13700 (leu:P (match_dup 1) (match_dup 2)))]
13701 "reload_completed"
13702 [(set (match_dup 0)
13703 (leu:P (match_dup 1) (match_dup 2)))
13704 (set (match_dup 3)
13705 (compare:CC (match_dup 0)
13706 (const_int 0)))]
13707 "")
13709 (define_insn "*plus_leu<mode>"
13710 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13711 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13712 (match_operand:P 2 "reg_or_short_operand" "rI"))
13713 (match_operand:P 3 "gpc_reg_operand" "r")))]
13714 ""
13715 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
13716 [(set_attr "type" "two")
13717 (set_attr "length" "8")])
13719 (define_insn ""
13720 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13721 (compare:CC
13722 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13723 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13724 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13725 (const_int 0)))
13726 (clobber (match_scratch:SI 4 "=&r,&r"))]
13727 "TARGET_32BIT"
13728 "@
13729 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
13730 #"
13731 [(set_attr "type" "compare")
13732 (set_attr "length" "8,12")])
13734 (define_split
13735 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13736 (compare:CC
13737 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13738 (match_operand:SI 2 "reg_or_short_operand" ""))
13739 (match_operand:SI 3 "gpc_reg_operand" ""))
13740 (const_int 0)))
13741 (clobber (match_scratch:SI 4 ""))]
13742 "TARGET_32BIT && reload_completed"
13743 [(set (match_dup 4)
13744 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13745 (match_dup 3)))
13746 (set (match_dup 0)
13747 (compare:CC (match_dup 4)
13748 (const_int 0)))]
13749 "")
13751 (define_insn ""
13752 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13753 (compare:CC
13754 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13755 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13756 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13757 (const_int 0)))
13758 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13759 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13760 "TARGET_32BIT"
13761 "@
13762 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
13763 #"
13764 [(set_attr "type" "compare")
13765 (set_attr "length" "8,12")])
13767 (define_split
13768 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13769 (compare:CC
13770 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13771 (match_operand:SI 2 "reg_or_short_operand" ""))
13772 (match_operand:SI 3 "gpc_reg_operand" ""))
13773 (const_int 0)))
13774 (set (match_operand:SI 0 "gpc_reg_operand" "")
13775 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13776 "TARGET_32BIT && reload_completed"
13777 [(set (match_dup 0)
13778 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13779 (set (match_dup 4)
13780 (compare:CC (match_dup 0)
13781 (const_int 0)))]
13782 "")
13784 (define_insn "*neg_leu<mode>"
13785 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13786 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13787 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13788 ""
13789 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
13790 [(set_attr "type" "three")
13791 (set_attr "length" "12")])
13793 (define_insn "*and_neg_leu<mode>"
13794 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13795 (and:P (neg:P
13796 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13797 (match_operand:P 2 "reg_or_short_operand" "rI")))
13798 (match_operand:P 3 "gpc_reg_operand" "r")))]
13799 ""
13800 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13801 [(set_attr "type" "three")
13802 (set_attr "length" "12")])
13804 (define_insn ""
13805 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13806 (compare:CC
13807 (and:SI (neg:SI
13808 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13809 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13810 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13811 (const_int 0)))
13812 (clobber (match_scratch:SI 4 "=&r,&r"))]
13813 "TARGET_32BIT"
13814 "@
13815 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13816 #"
13817 [(set_attr "type" "compare")
13818 (set_attr "length" "12,16")])
13820 (define_split
13821 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13822 (compare:CC
13823 (and:SI (neg:SI
13824 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13825 (match_operand:SI 2 "reg_or_short_operand" "")))
13826 (match_operand:SI 3 "gpc_reg_operand" ""))
13827 (const_int 0)))
13828 (clobber (match_scratch:SI 4 ""))]
13829 "TARGET_32BIT && reload_completed"
13830 [(set (match_dup 4)
13831 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13832 (match_dup 3)))
13833 (set (match_dup 0)
13834 (compare:CC (match_dup 4)
13835 (const_int 0)))]
13836 "")
13838 (define_insn ""
13839 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13840 (compare:CC
13841 (and:SI (neg:SI
13842 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13843 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13844 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13845 (const_int 0)))
13846 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13847 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13848 "TARGET_32BIT"
13849 "@
13850 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13851 #"
13852 [(set_attr "type" "compare")
13853 (set_attr "length" "12,16")])
13855 (define_split
13856 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13857 (compare:CC
13858 (and:SI (neg:SI
13859 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13860 (match_operand:SI 2 "reg_or_short_operand" "")))
13861 (match_operand:SI 3 "gpc_reg_operand" ""))
13862 (const_int 0)))
13863 (set (match_operand:SI 0 "gpc_reg_operand" "")
13864 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13865 "TARGET_32BIT && reload_completed"
13866 [(set (match_dup 0)
13867 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13868 (match_dup 3)))
13869 (set (match_dup 4)
13870 (compare:CC (match_dup 0)
13871 (const_int 0)))]
13872 "")
13874 (define_insn ""
13875 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13876 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13877 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13878 "TARGET_POWER"
13879 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13880 [(set_attr "length" "12")])
13882 (define_insn ""
13883 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13884 (compare:CC
13885 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13886 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13887 (const_int 0)))
13888 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13889 (lt:SI (match_dup 1) (match_dup 2)))]
13890 "TARGET_POWER"
13891 "@
13892 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13893 #"
13894 [(set_attr "type" "delayed_compare")
13895 (set_attr "length" "12,16")])
13897 (define_split
13898 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13899 (compare:CC
13900 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13901 (match_operand:SI 2 "reg_or_short_operand" ""))
13902 (const_int 0)))
13903 (set (match_operand:SI 0 "gpc_reg_operand" "")
13904 (lt:SI (match_dup 1) (match_dup 2)))]
13905 "TARGET_POWER && reload_completed"
13906 [(set (match_dup 0)
13907 (lt:SI (match_dup 1) (match_dup 2)))
13908 (set (match_dup 3)
13909 (compare:CC (match_dup 0)
13910 (const_int 0)))]
13911 "")
13913 (define_insn ""
13914 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13915 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13916 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13917 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13918 "TARGET_POWER"
13919 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13920 [(set_attr "length" "12")])
13922 (define_insn ""
13923 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13924 (compare:CC
13925 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13926 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13927 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13928 (const_int 0)))
13929 (clobber (match_scratch:SI 4 "=&r,&r"))]
13930 "TARGET_POWER"
13931 "@
13932 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13933 #"
13934 [(set_attr "type" "compare")
13935 (set_attr "length" "12,16")])
13937 (define_split
13938 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13939 (compare:CC
13940 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13941 (match_operand:SI 2 "reg_or_short_operand" ""))
13942 (match_operand:SI 3 "gpc_reg_operand" ""))
13943 (const_int 0)))
13944 (clobber (match_scratch:SI 4 ""))]
13945 "TARGET_POWER && reload_completed"
13946 [(set (match_dup 4)
13947 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13948 (match_dup 3)))
13949 (set (match_dup 0)
13950 (compare:CC (match_dup 4)
13951 (const_int 0)))]
13952 "")
13954 (define_insn ""
13955 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13956 (compare:CC
13957 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13958 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13959 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13960 (const_int 0)))
13961 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13962 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13963 "TARGET_POWER"
13964 "@
13965 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13966 #"
13967 [(set_attr "type" "compare")
13968 (set_attr "length" "12,16")])
13970 (define_split
13971 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13972 (compare:CC
13973 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13974 (match_operand:SI 2 "reg_or_short_operand" ""))
13975 (match_operand:SI 3 "gpc_reg_operand" ""))
13976 (const_int 0)))
13977 (set (match_operand:SI 0 "gpc_reg_operand" "")
13978 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13979 "TARGET_POWER && reload_completed"
13980 [(set (match_dup 0)
13981 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13982 (set (match_dup 4)
13983 (compare:CC (match_dup 0)
13984 (const_int 0)))]
13985 "")
13987 (define_insn ""
13988 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13989 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13990 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13991 "TARGET_POWER"
13992 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13993 [(set_attr "length" "12")])
13995 (define_insn_and_split "*ltu<mode>"
13996 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13997 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13998 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13999 ""
14000 "#"
14001 ""
14002 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14003 (set (match_dup 0) (neg:P (match_dup 0)))]
14004 "")
14006 (define_insn_and_split "*ltu<mode>_compare"
14007 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14008 (compare:CC
14009 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14010 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14011 (const_int 0)))
14012 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14013 (ltu:P (match_dup 1) (match_dup 2)))]
14014 ""
14015 "#"
14016 ""
14017 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14018 (parallel [(set (match_dup 3)
14019 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14020 (set (match_dup 0) (neg:P (match_dup 0)))])]
14021 "")
14023 (define_insn_and_split "*plus_ltu<mode>"
14024 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14025 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14026 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14027 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14028 ""
14029 "#"
14030 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14031 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14032 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14033 "")
14035 (define_insn_and_split "*plus_ltu<mode>_compare"
14036 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14037 (compare:CC
14038 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14039 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14040 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14041 (const_int 0)))
14042 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14043 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14044 ""
14045 "#"
14046 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14047 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14048 (parallel [(set (match_dup 4)
14049 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14050 (const_int 0)))
14051 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14052 "")
14054 (define_insn "*neg_ltu<mode>"
14055 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14056 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14057 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14058 ""
14059 "@
14060 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
14061 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
14062 [(set_attr "type" "two")
14063 (set_attr "length" "8")])
14065 (define_insn ""
14066 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14067 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14068 (match_operand:SI 2 "reg_or_short_operand" "rI")))
14069 (clobber (match_scratch:SI 3 "=r"))]
14070 "TARGET_POWER"
14071 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
14072 [(set_attr "length" "12")])
14074 (define_insn ""
14075 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14076 (compare:CC
14077 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14078 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14079 (const_int 0)))
14080 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14081 (ge:SI (match_dup 1) (match_dup 2)))
14082 (clobber (match_scratch:SI 3 "=r,r"))]
14083 "TARGET_POWER"
14084 "@
14085 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14086 #"
14087 [(set_attr "type" "compare")
14088 (set_attr "length" "12,16")])
14090 (define_split
14091 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14092 (compare:CC
14093 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14094 (match_operand:SI 2 "reg_or_short_operand" ""))
14095 (const_int 0)))
14096 (set (match_operand:SI 0 "gpc_reg_operand" "")
14097 (ge:SI (match_dup 1) (match_dup 2)))
14098 (clobber (match_scratch:SI 3 ""))]
14099 "TARGET_POWER && reload_completed"
14100 [(parallel [(set (match_dup 0)
14101 (ge:SI (match_dup 1) (match_dup 2)))
14102 (clobber (match_dup 3))])
14103 (set (match_dup 4)
14104 (compare:CC (match_dup 0)
14105 (const_int 0)))]
14106 "")
14108 (define_insn ""
14109 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14110 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14111 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14112 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14113 "TARGET_POWER"
14114 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
14115 [(set_attr "length" "12")])
14117 (define_insn ""
14118 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14119 (compare:CC
14120 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14121 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14122 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14123 (const_int 0)))
14124 (clobber (match_scratch:SI 4 "=&r,&r"))]
14125 "TARGET_POWER"
14126 "@
14127 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14128 #"
14129 [(set_attr "type" "compare")
14130 (set_attr "length" "12,16")])
14132 (define_split
14133 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14134 (compare:CC
14135 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14136 (match_operand:SI 2 "reg_or_short_operand" ""))
14137 (match_operand:SI 3 "gpc_reg_operand" ""))
14138 (const_int 0)))
14139 (clobber (match_scratch:SI 4 ""))]
14140 "TARGET_POWER && reload_completed"
14141 [(set (match_dup 4)
14142 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
14143 (match_dup 3)))
14144 (set (match_dup 0)
14145 (compare:CC (match_dup 4)
14146 (const_int 0)))]
14147 "")
14149 (define_insn ""
14150 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14151 (compare:CC
14152 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14153 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14154 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14155 (const_int 0)))
14156 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14157 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14158 "TARGET_POWER"
14159 "@
14160 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14161 #"
14162 [(set_attr "type" "compare")
14163 (set_attr "length" "12,16")])
14165 (define_split
14166 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14167 (compare:CC
14168 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14169 (match_operand:SI 2 "reg_or_short_operand" ""))
14170 (match_operand:SI 3 "gpc_reg_operand" ""))
14171 (const_int 0)))
14172 (set (match_operand:SI 0 "gpc_reg_operand" "")
14173 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14174 "TARGET_POWER && reload_completed"
14175 [(set (match_dup 0)
14176 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14177 (set (match_dup 4)
14178 (compare:CC (match_dup 0)
14179 (const_int 0)))]
14180 "")
14182 (define_insn ""
14183 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14184 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14185 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14186 "TARGET_POWER"
14187 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
14188 [(set_attr "length" "12")])
14190 (define_insn "*geu<mode>"
14191 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14192 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14193 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14194 ""
14195 "@
14196 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
14197 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14198 [(set_attr "type" "three")
14199 (set_attr "length" "12")])
14201 (define_insn "*geu<mode>_compare"
14202 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14203 (compare:CC
14204 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14205 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14206 (const_int 0)))
14207 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14208 (geu:P (match_dup 1) (match_dup 2)))]
14209 ""
14210 "@
14211 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14212 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14213 #
14214 #"
14215 [(set_attr "type" "compare")
14216 (set_attr "length" "12,12,16,16")])
14218 (define_split
14219 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14220 (compare:CC
14221 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14222 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14223 (const_int 0)))
14224 (set (match_operand:P 0 "gpc_reg_operand" "")
14225 (geu:P (match_dup 1) (match_dup 2)))]
14226 "reload_completed"
14227 [(set (match_dup 0)
14228 (geu:P (match_dup 1) (match_dup 2)))
14229 (set (match_dup 3)
14230 (compare:CC (match_dup 0)
14231 (const_int 0)))]
14232 "")
14234 (define_insn "*plus_geu<mode>"
14235 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14236 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14237 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14238 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14239 ""
14240 "@
14241 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
14242 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
14243 [(set_attr "type" "two")
14244 (set_attr "length" "8")])
14246 (define_insn ""
14247 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14248 (compare:CC
14249 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14250 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14251 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14252 (const_int 0)))
14253 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14254 "TARGET_32BIT"
14255 "@
14256 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
14257 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
14258 #
14259 #"
14260 [(set_attr "type" "compare")
14261 (set_attr "length" "8,8,12,12")])
14263 (define_split
14264 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14265 (compare:CC
14266 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14267 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14268 (match_operand:SI 3 "gpc_reg_operand" ""))
14269 (const_int 0)))
14270 (clobber (match_scratch:SI 4 ""))]
14271 "TARGET_32BIT && reload_completed"
14272 [(set (match_dup 4)
14273 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14274 (match_dup 3)))
14275 (set (match_dup 0)
14276 (compare:CC (match_dup 4)
14277 (const_int 0)))]
14278 "")
14280 (define_insn ""
14281 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14282 (compare:CC
14283 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14284 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14285 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14286 (const_int 0)))
14287 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14288 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14289 "TARGET_32BIT"
14290 "@
14291 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
14292 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
14293 #
14294 #"
14295 [(set_attr "type" "compare")
14296 (set_attr "length" "8,8,12,12")])
14298 (define_split
14299 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14300 (compare:CC
14301 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14302 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14303 (match_operand:SI 3 "gpc_reg_operand" ""))
14304 (const_int 0)))
14305 (set (match_operand:SI 0 "gpc_reg_operand" "")
14306 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14307 "TARGET_32BIT && reload_completed"
14308 [(set (match_dup 0)
14309 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14310 (set (match_dup 4)
14311 (compare:CC (match_dup 0)
14312 (const_int 0)))]
14313 "")
14315 (define_insn "*neg_geu<mode>"
14316 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14317 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14318 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14319 ""
14320 "@
14321 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
14322 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
14323 [(set_attr "type" "three")
14324 (set_attr "length" "12")])
14326 (define_insn "*and_neg_geu<mode>"
14327 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14328 (and:P (neg:P
14329 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14330 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14331 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14332 ""
14333 "@
14334 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
14335 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14336 [(set_attr "type" "three")
14337 (set_attr "length" "12")])
14339 (define_insn ""
14340 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14341 (compare:CC
14342 (and:SI (neg:SI
14343 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14344 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14345 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14346 (const_int 0)))
14347 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14348 "TARGET_32BIT"
14349 "@
14350 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14351 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14352 #
14353 #"
14354 [(set_attr "type" "compare")
14355 (set_attr "length" "12,12,16,16")])
14357 (define_split
14358 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14359 (compare:CC
14360 (and:SI (neg:SI
14361 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14362 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14363 (match_operand:SI 3 "gpc_reg_operand" ""))
14364 (const_int 0)))
14365 (clobber (match_scratch:SI 4 ""))]
14366 "TARGET_32BIT && reload_completed"
14367 [(set (match_dup 4)
14368 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14369 (match_dup 3)))
14370 (set (match_dup 0)
14371 (compare:CC (match_dup 4)
14372 (const_int 0)))]
14373 "")
14375 (define_insn ""
14376 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14377 (compare:CC
14378 (and:SI (neg:SI
14379 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14380 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14381 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14382 (const_int 0)))
14383 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14384 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14385 "TARGET_32BIT"
14386 "@
14387 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14388 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14389 #
14390 #"
14391 [(set_attr "type" "compare")
14392 (set_attr "length" "12,12,16,16")])
14394 (define_split
14395 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14396 (compare:CC
14397 (and:SI (neg:SI
14398 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14399 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14400 (match_operand:SI 3 "gpc_reg_operand" ""))
14401 (const_int 0)))
14402 (set (match_operand:SI 0 "gpc_reg_operand" "")
14403 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14404 "TARGET_32BIT && reload_completed"
14405 [(set (match_dup 0)
14406 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14407 (set (match_dup 4)
14408 (compare:CC (match_dup 0)
14409 (const_int 0)))]
14410 "")
14412 (define_insn ""
14413 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14414 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14415 (match_operand:SI 2 "reg_or_short_operand" "r")))]
14416 "TARGET_POWER"
14417 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14418 [(set_attr "length" "12")])
14420 (define_insn ""
14421 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14422 (compare:CC
14423 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14424 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14425 (const_int 0)))
14426 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14427 (gt:SI (match_dup 1) (match_dup 2)))]
14428 "TARGET_POWER"
14429 "@
14430 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14431 #"
14432 [(set_attr "type" "delayed_compare")
14433 (set_attr "length" "12,16")])
14435 (define_split
14436 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14437 (compare:CC
14438 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14439 (match_operand:SI 2 "reg_or_short_operand" ""))
14440 (const_int 0)))
14441 (set (match_operand:SI 0 "gpc_reg_operand" "")
14442 (gt:SI (match_dup 1) (match_dup 2)))]
14443 "TARGET_POWER && reload_completed"
14444 [(set (match_dup 0)
14445 (gt:SI (match_dup 1) (match_dup 2)))
14446 (set (match_dup 3)
14447 (compare:CC (match_dup 0)
14448 (const_int 0)))]
14449 "")
14451 (define_insn "*plus_gt0<mode>"
14452 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14453 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
14454 (const_int 0))
14455 (match_operand:P 2 "gpc_reg_operand" "r")))]
14456 ""
14457 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
14458 [(set_attr "type" "three")
14459 (set_attr "length" "12")])
14461 (define_insn ""
14462 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14463 (compare:CC
14464 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14465 (const_int 0))
14466 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14467 (const_int 0)))
14468 (clobber (match_scratch:SI 3 "=&r,&r"))]
14469 "TARGET_32BIT"
14470 "@
14471 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
14472 #"
14473 [(set_attr "type" "compare")
14474 (set_attr "length" "12,16")])
14476 (define_split
14477 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14478 (compare:CC
14479 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14480 (const_int 0))
14481 (match_operand:SI 2 "gpc_reg_operand" ""))
14482 (const_int 0)))
14483 (clobber (match_scratch:SI 3 ""))]
14484 "TARGET_32BIT && reload_completed"
14485 [(set (match_dup 3)
14486 (plus:SI (gt:SI (match_dup 1) (const_int 0))
14487 (match_dup 2)))
14488 (set (match_dup 0)
14489 (compare:CC (match_dup 3)
14490 (const_int 0)))]
14491 "")
14493 (define_insn ""
14494 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14495 (compare:CC
14496 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14497 (const_int 0))
14498 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14499 (const_int 0)))
14500 (clobber (match_scratch:DI 3 "=&r,&r"))]
14501 "TARGET_64BIT"
14502 "@
14503 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14504 #"
14505 [(set_attr "type" "compare")
14506 (set_attr "length" "12,16")])
14508 (define_split
14509 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14510 (compare:CC
14511 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14512 (const_int 0))
14513 (match_operand:DI 2 "gpc_reg_operand" ""))
14514 (const_int 0)))
14515 (clobber (match_scratch:DI 3 ""))]
14516 "TARGET_64BIT && reload_completed"
14517 [(set (match_dup 3)
14518 (plus:DI (gt:DI (match_dup 1) (const_int 0))
14519 (match_dup 2)))
14520 (set (match_dup 0)
14521 (compare:CC (match_dup 3)
14522 (const_int 0)))]
14523 "")
14525 (define_insn ""
14526 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14527 (compare:CC
14528 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14529 (const_int 0))
14530 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14531 (const_int 0)))
14532 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14533 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14534 "TARGET_32BIT"
14535 "@
14536 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
14537 #"
14538 [(set_attr "type" "compare")
14539 (set_attr "length" "12,16")])
14541 (define_split
14542 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14543 (compare:CC
14544 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14545 (const_int 0))
14546 (match_operand:SI 2 "gpc_reg_operand" ""))
14547 (const_int 0)))
14548 (set (match_operand:SI 0 "gpc_reg_operand" "")
14549 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14550 "TARGET_32BIT && reload_completed"
14551 [(set (match_dup 0)
14552 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14553 (set (match_dup 3)
14554 (compare:CC (match_dup 0)
14555 (const_int 0)))]
14556 "")
14558 (define_insn ""
14559 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14560 (compare:CC
14561 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14562 (const_int 0))
14563 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14564 (const_int 0)))
14565 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14566 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14567 "TARGET_64BIT"
14568 "@
14569 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14570 #"
14571 [(set_attr "type" "compare")
14572 (set_attr "length" "12,16")])
14574 (define_split
14575 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14576 (compare:CC
14577 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14578 (const_int 0))
14579 (match_operand:DI 2 "gpc_reg_operand" ""))
14580 (const_int 0)))
14581 (set (match_operand:DI 0 "gpc_reg_operand" "")
14582 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14583 "TARGET_64BIT && reload_completed"
14584 [(set (match_dup 0)
14585 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14586 (set (match_dup 3)
14587 (compare:CC (match_dup 0)
14588 (const_int 0)))]
14589 "")
14591 (define_insn ""
14592 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14593 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14594 (match_operand:SI 2 "reg_or_short_operand" "r"))
14595 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14596 "TARGET_POWER"
14597 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14598 [(set_attr "length" "12")])
14600 (define_insn ""
14601 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14602 (compare:CC
14603 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14604 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14605 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14606 (const_int 0)))
14607 (clobber (match_scratch:SI 4 "=&r,&r"))]
14608 "TARGET_POWER"
14609 "@
14610 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14611 #"
14612 [(set_attr "type" "compare")
14613 (set_attr "length" "12,16")])
14615 (define_split
14616 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14617 (compare:CC
14618 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14619 (match_operand:SI 2 "reg_or_short_operand" ""))
14620 (match_operand:SI 3 "gpc_reg_operand" ""))
14621 (const_int 0)))
14622 (clobber (match_scratch:SI 4 ""))]
14623 "TARGET_POWER && reload_completed"
14624 [(set (match_dup 4)
14625 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14626 (set (match_dup 0)
14627 (compare:CC (match_dup 4)
14628 (const_int 0)))]
14629 "")
14631 (define_insn ""
14632 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14633 (compare:CC
14634 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14635 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14636 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14637 (const_int 0)))
14638 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14639 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14640 "TARGET_POWER"
14641 "@
14642 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14643 #"
14644 [(set_attr "type" "compare")
14645 (set_attr "length" "12,16")])
14647 (define_split
14648 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14649 (compare:CC
14650 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14651 (match_operand:SI 2 "reg_or_short_operand" ""))
14652 (match_operand:SI 3 "gpc_reg_operand" ""))
14653 (const_int 0)))
14654 (set (match_operand:SI 0 "gpc_reg_operand" "")
14655 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14656 "TARGET_POWER && reload_completed"
14657 [(set (match_dup 0)
14658 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14659 (set (match_dup 4)
14660 (compare:CC (match_dup 0)
14661 (const_int 0)))]
14662 "")
14664 (define_insn ""
14665 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14666 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14667 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
14668 "TARGET_POWER"
14669 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14670 [(set_attr "length" "12")])
14672 (define_insn_and_split "*gtu<mode>"
14673 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14674 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14675 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14676 ""
14677 "#"
14678 ""
14679 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14680 (set (match_dup 0) (neg:P (match_dup 0)))]
14681 "")
14683 (define_insn_and_split "*gtu<mode>_compare"
14684 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14685 (compare:CC
14686 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14687 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14688 (const_int 0)))
14689 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14690 (gtu:P (match_dup 1) (match_dup 2)))]
14691 ""
14692 "#"
14693 ""
14694 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14695 (parallel [(set (match_dup 3)
14696 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14697 (set (match_dup 0) (neg:P (match_dup 0)))])]
14698 "")
14700 (define_insn_and_split "*plus_gtu<mode>"
14701 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14702 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14703 (match_operand:P 2 "reg_or_short_operand" "rI"))
14704 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14705 ""
14706 "#"
14707 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14708 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14709 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14710 "")
14712 (define_insn_and_split "*plus_gtu<mode>_compare"
14713 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14714 (compare:CC
14715 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14716 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14717 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14718 (const_int 0)))
14719 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14720 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14721 ""
14722 "#"
14723 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14724 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14725 (parallel [(set (match_dup 4)
14726 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14727 (const_int 0)))
14728 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14729 "")
14731 (define_insn "*neg_gtu<mode>"
14732 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14733 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14734 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14735 ""
14736 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
14737 [(set_attr "type" "two")
14738 (set_attr "length" "8")])
14740 \f
14741 ;; Define both directions of branch and return. If we need a reload
14742 ;; register, we'd rather use CR0 since it is much easier to copy a
14743 ;; register CC value to there.
14745 (define_insn ""
14746 [(set (pc)
14747 (if_then_else (match_operator 1 "branch_comparison_operator"
14748 [(match_operand 2
14749 "cc_reg_operand" "y")
14750 (const_int 0)])
14751 (label_ref (match_operand 0 "" ""))
14752 (pc)))]
14753 ""
14754 "*
14755 {
14756 return output_cbranch (operands[1], \"%l0\", 0, insn);
14757 }"
14758 [(set_attr "type" "branch")])
14760 (define_insn ""
14761 [(set (pc)
14762 (if_then_else (match_operator 0 "branch_comparison_operator"
14763 [(match_operand 1
14764 "cc_reg_operand" "y")
14765 (const_int 0)])
14766 (return)
14767 (pc)))]
14768 "direct_return ()"
14769 "*
14770 {
14771 return output_cbranch (operands[0], NULL, 0, insn);
14772 }"
14773 [(set_attr "type" "jmpreg")
14774 (set_attr "length" "4")])
14776 (define_insn ""
14777 [(set (pc)
14778 (if_then_else (match_operator 1 "branch_comparison_operator"
14779 [(match_operand 2
14780 "cc_reg_operand" "y")
14781 (const_int 0)])
14782 (pc)
14783 (label_ref (match_operand 0 "" ""))))]
14784 ""
14785 "*
14786 {
14787 return output_cbranch (operands[1], \"%l0\", 1, insn);
14788 }"
14789 [(set_attr "type" "branch")])
14791 (define_insn ""
14792 [(set (pc)
14793 (if_then_else (match_operator 0 "branch_comparison_operator"
14794 [(match_operand 1
14795 "cc_reg_operand" "y")
14796 (const_int 0)])
14797 (pc)
14798 (return)))]
14799 "direct_return ()"
14800 "*
14801 {
14802 return output_cbranch (operands[0], NULL, 1, insn);
14803 }"
14804 [(set_attr "type" "jmpreg")
14805 (set_attr "length" "4")])
14807 ;; Logic on condition register values.
14809 ; This pattern matches things like
14810 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14811 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14812 ; (const_int 1)))
14813 ; which are generated by the branch logic.
14814 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14816 (define_insn "*cceq_ior_compare"
14817 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14818 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14819 [(match_operator:SI 2
14820 "branch_positive_comparison_operator"
14821 [(match_operand 3
14822 "cc_reg_operand" "y,y")
14823 (const_int 0)])
14824 (match_operator:SI 4
14825 "branch_positive_comparison_operator"
14826 [(match_operand 5
14827 "cc_reg_operand" "0,y")
14828 (const_int 0)])])
14829 (const_int 1)))]
14830 ""
14831 "cr%q1 %E0,%j2,%j4"
14832 [(set_attr "type" "cr_logical,delayed_cr")])
14834 ; Why is the constant -1 here, but 1 in the previous pattern?
14835 ; Because ~1 has all but the low bit set.
14836 (define_insn ""
14837 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14838 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14839 [(not:SI (match_operator:SI 2
14840 "branch_positive_comparison_operator"
14841 [(match_operand 3
14842 "cc_reg_operand" "y,y")
14843 (const_int 0)]))
14844 (match_operator:SI 4
14845 "branch_positive_comparison_operator"
14846 [(match_operand 5
14847 "cc_reg_operand" "0,y")
14848 (const_int 0)])])
14849 (const_int -1)))]
14850 ""
14851 "cr%q1 %E0,%j2,%j4"
14852 [(set_attr "type" "cr_logical,delayed_cr")])
14854 (define_insn "*cceq_rev_compare"
14855 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14856 (compare:CCEQ (match_operator:SI 1
14857 "branch_positive_comparison_operator"
14858 [(match_operand 2
14859 "cc_reg_operand" "0,y")
14860 (const_int 0)])
14861 (const_int 0)))]
14862 ""
14863 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14864 [(set_attr "type" "cr_logical,delayed_cr")])
14866 ;; If we are comparing the result of two comparisons, this can be done
14867 ;; using creqv or crxor.
14869 (define_insn_and_split ""
14870 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14871 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14872 [(match_operand 2 "cc_reg_operand" "y")
14873 (const_int 0)])
14874 (match_operator 3 "branch_comparison_operator"
14875 [(match_operand 4 "cc_reg_operand" "y")
14876 (const_int 0)])))]
14877 ""
14878 "#"
14879 ""
14880 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14881 (match_dup 5)))]
14882 "
14883 {
14884 int positive_1, positive_2;
14886 positive_1 = branch_positive_comparison_operator (operands[1],
14887 GET_MODE (operands[1]));
14888 positive_2 = branch_positive_comparison_operator (operands[3],
14889 GET_MODE (operands[3]));
14891 if (! positive_1)
14892 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14893 GET_CODE (operands[1])),
14894 SImode,
14895 operands[2], const0_rtx);
14896 else if (GET_MODE (operands[1]) != SImode)
14897 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14898 operands[2], const0_rtx);
14900 if (! positive_2)
14901 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14902 GET_CODE (operands[3])),
14903 SImode,
14904 operands[4], const0_rtx);
14905 else if (GET_MODE (operands[3]) != SImode)
14906 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14907 operands[4], const0_rtx);
14909 if (positive_1 == positive_2)
14910 {
14911 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14912 operands[5] = constm1_rtx;
14913 }
14914 else
14915 {
14916 operands[5] = const1_rtx;
14917 }
14918 }")
14920 ;; Unconditional branch and return.
14922 (define_insn "jump"
14923 [(set (pc)
14924 (label_ref (match_operand 0 "" "")))]
14925 ""
14926 "b %l0"
14927 [(set_attr "type" "branch")])
14929 (define_insn "return"
14930 [(return)]
14931 "direct_return ()"
14932 "{br|blr}"
14933 [(set_attr "type" "jmpreg")])
14935 (define_expand "indirect_jump"
14936 [(set (pc) (match_operand 0 "register_operand" ""))])
14938 (define_insn "*indirect_jump<mode>"
14939 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14940 ""
14941 "@
14942 bctr
14943 {br|blr}"
14944 [(set_attr "type" "jmpreg")])
14946 ;; Table jump for switch statements:
14947 (define_expand "tablejump"
14948 [(use (match_operand 0 "" ""))
14949 (use (label_ref (match_operand 1 "" "")))]
14950 ""
14951 "
14952 {
14953 if (TARGET_32BIT)
14954 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14955 else
14956 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14957 DONE;
14958 }")
14960 (define_expand "tablejumpsi"
14961 [(set (match_dup 3)
14962 (plus:SI (match_operand:SI 0 "" "")
14963 (match_dup 2)))
14964 (parallel [(set (pc) (match_dup 3))
14965 (use (label_ref (match_operand 1 "" "")))])]
14966 "TARGET_32BIT"
14967 "
14968 { operands[0] = force_reg (SImode, operands[0]);
14969 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14970 operands[3] = gen_reg_rtx (SImode);
14971 }")
14973 (define_expand "tablejumpdi"
14974 [(set (match_dup 4)
14975 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14976 (set (match_dup 3)
14977 (plus:DI (match_dup 4)
14978 (match_dup 2)))
14979 (parallel [(set (pc) (match_dup 3))
14980 (use (label_ref (match_operand 1 "" "")))])]
14981 "TARGET_64BIT"
14982 "
14983 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14984 operands[3] = gen_reg_rtx (DImode);
14985 operands[4] = gen_reg_rtx (DImode);
14986 }")
14988 (define_insn "*tablejump<mode>_internal1"
14989 [(set (pc)
14990 (match_operand:P 0 "register_operand" "c,*l"))
14991 (use (label_ref (match_operand 1 "" "")))]
14992 ""
14993 "@
14994 bctr
14995 {br|blr}"
14996 [(set_attr "type" "jmpreg")])
14998 (define_insn "nop"
14999 [(const_int 0)]
15000 ""
15001 "{cror 0,0,0|nop}")
15002 \f
15003 ;; Define the subtract-one-and-jump insns, starting with the template
15004 ;; so loop.c knows what to generate.
15006 (define_expand "doloop_end"
15007 [(use (match_operand 0 "" "")) ; loop pseudo
15008 (use (match_operand 1 "" "")) ; iterations; zero if unknown
15009 (use (match_operand 2 "" "")) ; max iterations
15010 (use (match_operand 3 "" "")) ; loop level
15011 (use (match_operand 4 "" ""))] ; label
15012 ""
15013 "
15014 {
15015 /* Only use this on innermost loops. */
15016 if (INTVAL (operands[3]) > 1)
15017 FAIL;
15018 if (TARGET_64BIT)
15019 {
15020 if (GET_MODE (operands[0]) != DImode)
15021 FAIL;
15022 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
15023 }
15024 else
15025 {
15026 if (GET_MODE (operands[0]) != SImode)
15027 FAIL;
15028 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
15029 }
15030 DONE;
15031 }")
15033 (define_expand "ctr<mode>"
15034 [(parallel [(set (pc)
15035 (if_then_else (ne (match_operand:P 0 "register_operand" "")
15036 (const_int 1))
15037 (label_ref (match_operand 1 "" ""))
15038 (pc)))
15039 (set (match_dup 0)
15040 (plus:P (match_dup 0)
15041 (const_int -1)))
15042 (clobber (match_scratch:CC 2 ""))
15043 (clobber (match_scratch:P 3 ""))])]
15044 ""
15045 "")
15047 ;; We need to be able to do this for any operand, including MEM, or we
15048 ;; will cause reload to blow up since we don't allow output reloads on
15049 ;; JUMP_INSNs.
15050 ;; For the length attribute to be calculated correctly, the
15051 ;; label MUST be operand 0.
15053 (define_insn "*ctr<mode>_internal1"
15054 [(set (pc)
15055 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15056 (const_int 1))
15057 (label_ref (match_operand 0 "" ""))
15058 (pc)))
15059 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15060 (plus:P (match_dup 1)
15061 (const_int -1)))
15062 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15063 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15064 ""
15065 "*
15066 {
15067 if (which_alternative != 0)
15068 return \"#\";
15069 else if (get_attr_length (insn) == 4)
15070 return \"{bdn|bdnz} %l0\";
15071 else
15072 return \"bdz $+8\;b %l0\";
15073 }"
15074 [(set_attr "type" "branch")
15075 (set_attr "length" "*,12,16,16")])
15077 (define_insn "*ctr<mode>_internal2"
15078 [(set (pc)
15079 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15080 (const_int 1))
15081 (pc)
15082 (label_ref (match_operand 0 "" ""))))
15083 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15084 (plus:P (match_dup 1)
15085 (const_int -1)))
15086 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15087 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15088 ""
15089 "*
15090 {
15091 if (which_alternative != 0)
15092 return \"#\";
15093 else if (get_attr_length (insn) == 4)
15094 return \"bdz %l0\";
15095 else
15096 return \"{bdn|bdnz} $+8\;b %l0\";
15097 }"
15098 [(set_attr "type" "branch")
15099 (set_attr "length" "*,12,16,16")])
15101 ;; Similar but use EQ
15103 (define_insn "*ctr<mode>_internal5"
15104 [(set (pc)
15105 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15106 (const_int 1))
15107 (label_ref (match_operand 0 "" ""))
15108 (pc)))
15109 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15110 (plus:P (match_dup 1)
15111 (const_int -1)))
15112 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15113 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15114 ""
15115 "*
15116 {
15117 if (which_alternative != 0)
15118 return \"#\";
15119 else if (get_attr_length (insn) == 4)
15120 return \"bdz %l0\";
15121 else
15122 return \"{bdn|bdnz} $+8\;b %l0\";
15123 }"
15124 [(set_attr "type" "branch")
15125 (set_attr "length" "*,12,16,16")])
15127 (define_insn "*ctr<mode>_internal6"
15128 [(set (pc)
15129 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15130 (const_int 1))
15131 (pc)
15132 (label_ref (match_operand 0 "" ""))))
15133 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15134 (plus:P (match_dup 1)
15135 (const_int -1)))
15136 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15137 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15138 ""
15139 "*
15140 {
15141 if (which_alternative != 0)
15142 return \"#\";
15143 else if (get_attr_length (insn) == 4)
15144 return \"{bdn|bdnz} %l0\";
15145 else
15146 return \"bdz $+8\;b %l0\";
15147 }"
15148 [(set_attr "type" "branch")
15149 (set_attr "length" "*,12,16,16")])
15151 ;; Now the splitters if we could not allocate the CTR register
15153 (define_split
15154 [(set (pc)
15155 (if_then_else (match_operator 2 "comparison_operator"
15156 [(match_operand:P 1 "gpc_reg_operand" "")
15157 (const_int 1)])
15158 (match_operand 5 "" "")
15159 (match_operand 6 "" "")))
15160 (set (match_operand:P 0 "gpc_reg_operand" "")
15161 (plus:P (match_dup 1) (const_int -1)))
15162 (clobber (match_scratch:CC 3 ""))
15163 (clobber (match_scratch:P 4 ""))]
15164 "reload_completed"
15165 [(parallel [(set (match_dup 3)
15166 (compare:CC (plus:P (match_dup 1)
15167 (const_int -1))
15168 (const_int 0)))
15169 (set (match_dup 0)
15170 (plus:P (match_dup 1)
15171 (const_int -1)))])
15172 (set (pc) (if_then_else (match_dup 7)
15173 (match_dup 5)
15174 (match_dup 6)))]
15175 "
15176 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15177 operands[3], const0_rtx); }")
15179 (define_split
15180 [(set (pc)
15181 (if_then_else (match_operator 2 "comparison_operator"
15182 [(match_operand:P 1 "gpc_reg_operand" "")
15183 (const_int 1)])
15184 (match_operand 5 "" "")
15185 (match_operand 6 "" "")))
15186 (set (match_operand:P 0 "nonimmediate_operand" "")
15187 (plus:P (match_dup 1) (const_int -1)))
15188 (clobber (match_scratch:CC 3 ""))
15189 (clobber (match_scratch:P 4 ""))]
15190 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15191 [(parallel [(set (match_dup 3)
15192 (compare:CC (plus:P (match_dup 1)
15193 (const_int -1))
15194 (const_int 0)))
15195 (set (match_dup 4)
15196 (plus:P (match_dup 1)
15197 (const_int -1)))])
15198 (set (match_dup 0)
15199 (match_dup 4))
15200 (set (pc) (if_then_else (match_dup 7)
15201 (match_dup 5)
15202 (match_dup 6)))]
15203 "
15204 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15205 operands[3], const0_rtx); }")
15206 \f
15207 (define_insn "trap"
15208 [(trap_if (const_int 1) (const_int 0))]
15209 ""
15210 "{t 31,0,0|trap}"
15211 [(set_attr "type" "trap")])
15213 (define_expand "ctrap<mode>4"
15214 [(trap_if (match_operator 0 "ordered_comparison_operator"
15215 [(match_operand:GPR 1 "register_operand")
15216 (match_operand:GPR 2 "reg_or_short_operand")])
15217 (match_operand 3 "zero_constant" ""))]
15218 ""
15219 "")
15221 (define_insn ""
15222 [(trap_if (match_operator 0 "ordered_comparison_operator"
15223 [(match_operand:GPR 1 "register_operand" "r")
15224 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15225 (const_int 0))]
15226 ""
15227 "{t|t<wd>}%V0%I2 %1,%2"
15228 [(set_attr "type" "trap")])
15229 \f
15230 ;; Insns related to generating the function prologue and epilogue.
15232 (define_expand "prologue"
15233 [(use (const_int 0))]
15234 "TARGET_SCHED_PROLOG"
15235 "
15236 {
15237 rs6000_emit_prologue ();
15238 DONE;
15239 }")
15241 (define_insn "*movesi_from_cr_one"
15242 [(match_parallel 0 "mfcr_operation"
15243 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15244 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15245 (match_operand 3 "immediate_operand" "n")]
15246 UNSPEC_MOVESI_FROM_CR))])]
15247 "TARGET_MFCRF"
15248 "*
15249 {
15250 int mask = 0;
15251 int i;
15252 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15253 {
15254 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15255 operands[4] = GEN_INT (mask);
15256 output_asm_insn (\"mfcr %1,%4\", operands);
15257 }
15258 return \"\";
15259 }"
15260 [(set_attr "type" "mfcrf")])
15262 (define_insn "movesi_from_cr"
15263 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15264 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15265 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15266 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15267 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15268 UNSPEC_MOVESI_FROM_CR))]
15269 ""
15270 "mfcr %0"
15271 [(set_attr "type" "mfcr")])
15273 (define_insn "*stmw"
15274 [(match_parallel 0 "stmw_operation"
15275 [(set (match_operand:SI 1 "memory_operand" "=m")
15276 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15277 "TARGET_MULTIPLE"
15278 "{stm|stmw} %2,%1"
15279 [(set_attr "type" "store_ux")])
15281 (define_insn "*save_gpregs_<mode>"
15282 [(match_parallel 0 "any_parallel_operand"
15283 [(clobber (reg:P 65))
15284 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15285 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15286 (set (match_operand:P 3 "memory_operand" "=m")
15287 (match_operand:P 4 "gpc_reg_operand" "r"))])]
15288 ""
15289 "bl %1"
15290 [(set_attr "type" "branch")
15291 (set_attr "length" "4")])
15293 (define_insn "*save_fpregs_<mode>"
15294 [(match_parallel 0 "any_parallel_operand"
15295 [(clobber (reg:P 65))
15296 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15297 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15298 (set (match_operand:DF 3 "memory_operand" "=m")
15299 (match_operand:DF 4 "gpc_reg_operand" "d"))])]
15300 ""
15301 "bl %1"
15302 [(set_attr "type" "branch")
15303 (set_attr "length" "4")])
15305 ; These are to explain that changes to the stack pointer should
15306 ; not be moved over stores to stack memory.
15307 (define_insn "stack_tie"
15308 [(set (match_operand:BLK 0 "memory_operand" "+m")
15309 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
15310 ""
15311 ""
15312 [(set_attr "length" "0")])
15314 ; Like stack_tie, but depend on both fp and sp based memory.
15315 (define_insn "frame_tie"
15316 [(set (match_operand:BLK 0 "memory_operand" "+m")
15317 (unspec:BLK [(match_dup 0)
15318 (match_operand:BLK 1 "memory_operand" "m")] UNSPEC_TIE))]
15319 ""
15320 ""
15321 [(set_attr "length" "0")])
15324 (define_expand "epilogue"
15325 [(use (const_int 0))]
15326 "TARGET_SCHED_PROLOG"
15327 "
15328 {
15329 rs6000_emit_epilogue (FALSE);
15330 DONE;
15331 }")
15333 ; On some processors, doing the mtcrf one CC register at a time is
15334 ; faster (like on the 604e). On others, doing them all at once is
15335 ; faster; for instance, on the 601 and 750.
15337 (define_expand "movsi_to_cr_one"
15338 [(set (match_operand:CC 0 "cc_reg_operand" "")
15339 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15340 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15341 ""
15342 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15344 (define_insn "*movsi_to_cr"
15345 [(match_parallel 0 "mtcrf_operation"
15346 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15347 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15348 (match_operand 3 "immediate_operand" "n")]
15349 UNSPEC_MOVESI_TO_CR))])]
15350 ""
15351 "*
15352 {
15353 int mask = 0;
15354 int i;
15355 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15356 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15357 operands[4] = GEN_INT (mask);
15358 return \"mtcrf %4,%2\";
15359 }"
15360 [(set_attr "type" "mtcr")])
15362 (define_insn "*mtcrfsi"
15363 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15364 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15365 (match_operand 2 "immediate_operand" "n")]
15366 UNSPEC_MOVESI_TO_CR))]
15367 "GET_CODE (operands[0]) == REG
15368 && CR_REGNO_P (REGNO (operands[0]))
15369 && GET_CODE (operands[2]) == CONST_INT
15370 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15371 "mtcrf %R0,%1"
15372 [(set_attr "type" "mtcr")])
15374 ; The load-multiple instructions have similar properties.
15375 ; Note that "load_multiple" is a name known to the machine-independent
15376 ; code that actually corresponds to the PowerPC load-string.
15378 (define_insn "*lmw"
15379 [(match_parallel 0 "lmw_operation"
15380 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15381 (match_operand:SI 2 "memory_operand" "m"))])]
15382 "TARGET_MULTIPLE"
15383 "{lm|lmw} %1,%2"
15384 [(set_attr "type" "load_ux")
15385 (set_attr "cell_micro" "always")])
15387 (define_insn "*return_internal_<mode>"
15388 [(return)
15389 (use (match_operand:P 0 "register_operand" "lc"))]
15390 ""
15391 "b%T0"
15392 [(set_attr "type" "jmpreg")])
15394 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
15395 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
15397 (define_insn "*restore_gpregs_<mode>"
15398 [(match_parallel 0 "any_parallel_operand"
15399 [(clobber (match_operand:P 1 "register_operand" "=l"))
15400 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15401 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15402 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15403 (match_operand:P 5 "memory_operand" "m"))])]
15404 ""
15405 "bl %2"
15406 [(set_attr "type" "branch")
15407 (set_attr "length" "4")])
15409 (define_insn "*return_and_restore_gpregs_<mode>"
15410 [(match_parallel 0 "any_parallel_operand"
15411 [(return)
15412 (clobber (match_operand:P 1 "register_operand" "=l"))
15413 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15414 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15415 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15416 (match_operand:P 5 "memory_operand" "m"))])]
15417 ""
15418 "b %2"
15419 [(set_attr "type" "branch")
15420 (set_attr "length" "4")])
15422 (define_insn "*return_and_restore_fpregs_<mode>"
15423 [(match_parallel 0 "any_parallel_operand"
15424 [(return)
15425 (clobber (match_operand:P 1 "register_operand" "=l"))
15426 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15427 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15428 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
15429 (match_operand:DF 5 "memory_operand" "m"))])]
15430 ""
15431 "b %2"
15432 [(set_attr "type" "branch")
15433 (set_attr "length" "4")])
15435 (define_insn "*return_and_restore_fpregs_aix_<mode>"
15436 [(match_parallel 0 "any_parallel_operand"
15437 [(return)
15438 (use (match_operand:P 1 "register_operand" "l"))
15439 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15440 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15441 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
15442 (match_operand:DF 5 "memory_operand" "m"))])]
15443 ""
15444 "b %2"
15445 [(set_attr "type" "branch")
15446 (set_attr "length" "4")])
15448 ; This is used in compiling the unwind routines.
15449 (define_expand "eh_return"
15450 [(use (match_operand 0 "general_operand" ""))]
15451 ""
15452 "
15453 {
15454 if (TARGET_32BIT)
15455 emit_insn (gen_eh_set_lr_si (operands[0]));
15456 else
15457 emit_insn (gen_eh_set_lr_di (operands[0]));
15458 DONE;
15459 }")
15461 ; We can't expand this before we know where the link register is stored.
15462 (define_insn "eh_set_lr_<mode>"
15463 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
15464 UNSPECV_EH_RR)
15465 (clobber (match_scratch:P 1 "=&b"))]
15466 ""
15467 "#")
15469 (define_split
15470 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
15471 (clobber (match_scratch 1 ""))]
15472 "reload_completed"
15473 [(const_int 0)]
15474 "
15475 {
15476 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
15477 DONE;
15478 }")
15480 (define_insn "prefetch"
15481 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
15482 (match_operand:SI 1 "const_int_operand" "n")
15483 (match_operand:SI 2 "const_int_operand" "n"))]
15484 "TARGET_POWERPC"
15485 "*
15486 {
15487 if (GET_CODE (operands[0]) == REG)
15488 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
15489 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
15490 }"
15491 [(set_attr "type" "load")])
15492 \f
15493 (define_insn "bpermd_<mode>"
15494 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15495 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
15496 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
15497 "TARGET_POPCNTD"
15498 "bpermd %0,%1,%2"
15499 [(set_attr "type" "integer")])
15501 \f
15503 (include "sync.md")
15504 (include "vector.md")
15505 (include "vsx.md")
15506 (include "altivec.md")
15507 (include "spe.md")
15508 (include "dfp.md")
15509 (include "paired.md")