| blob | 2d73bd83aed70bd607707617e9eb87554e501cb2 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; REGNOS
27 ;;
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (CA_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
52 ;;
53 ;; UNSPEC usage
54 ;;
56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_PROBE_STACK 4) ; probe stack memory reference
59 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
60 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
61 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
62 (UNSPEC_MOVSI_GOT 8)
63 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
64 (UNSPEC_FCTIWZ 10)
65 (UNSPEC_FRIM 11)
66 (UNSPEC_FRIN 12)
67 (UNSPEC_FRIP 13)
68 (UNSPEC_FRIZ 14)
69 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
70 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
71 (UNSPEC_TLSGD 17)
72 (UNSPEC_TLSLD 18)
73 (UNSPEC_MOVESI_FROM_CR 19)
74 (UNSPEC_MOVESI_TO_CR 20)
75 (UNSPEC_TLSDTPREL 21)
76 (UNSPEC_TLSDTPRELHA 22)
77 (UNSPEC_TLSDTPRELLO 23)
78 (UNSPEC_TLSGOTDTPREL 24)
79 (UNSPEC_TLSTPREL 25)
80 (UNSPEC_TLSTPRELHA 26)
81 (UNSPEC_TLSTPRELLO 27)
82 (UNSPEC_TLSGOTTPREL 28)
83 (UNSPEC_TLSTLS 29)
84 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
85 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
86 (UNSPEC_STFIWX 32)
87 (UNSPEC_POPCNTB 33)
88 (UNSPEC_FRES 34)
89 (UNSPEC_SP_SET 35)
90 (UNSPEC_SP_TEST 36)
91 (UNSPEC_SYNC 37)
92 (UNSPEC_LWSYNC 38)
93 (UNSPEC_ISYNC 39)
94 (UNSPEC_SYNC_OP 40)
95 (UNSPEC_ATOMIC 41)
96 (UNSPEC_CMPXCHG 42)
97 (UNSPEC_XCHG 43)
98 (UNSPEC_AND 44)
99 (UNSPEC_DLMZB 45)
100 (UNSPEC_DLMZB_CR 46)
101 (UNSPEC_DLMZB_STRLEN 47)
102 (UNSPEC_RSQRT 48)
103 (UNSPEC_TOCREL 49)
104 (UNSPEC_MACHOPIC_OFFSET 50)
105 (UNSPEC_BPERM 51)
106 (UNSPEC_COPYSIGN 52)
107 (UNSPEC_PARITY 53)
108 (UNSPEC_FCTIW 54)
109 (UNSPEC_FCTID 55)
110 (UNSPEC_LFIWAX 56)
111 (UNSPEC_LFIWZX 57)
112 (UNSPEC_FCTIWUZ 58)
113 ])
115 ;;
116 ;; UNSPEC_VOLATILE usage
117 ;;
119 (define_constants
120 [(UNSPECV_BLOCK 0)
121 (UNSPECV_LL 1) ; load-locked
122 (UNSPECV_SC 2) ; store-conditional
123 (UNSPECV_PROBE_STACK_RANGE 3) ; probe range of stack addresses
124 (UNSPECV_EH_RR 9) ; eh_reg_restore
125 ])
126 \f
127 ;; Define an insn type attribute. This is used in function unit delay
128 ;; computations.
129 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
130 (const_string "integer"))
132 ;; Define floating point instruction sub-types for use with Xfpu.md
133 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
135 ;; Length (in bytes).
136 ; '(pc)' in the following doesn't include the instruction itself; it is
137 ; calculated as if the instruction had zero size.
138 (define_attr "length" ""
139 (if_then_else (eq_attr "type" "branch")
140 (if_then_else (and (ge (minus (match_dup 0) (pc))
141 (const_int -32768))
142 (lt (minus (match_dup 0) (pc))
143 (const_int 32764)))
144 (const_int 4)
145 (const_int 8))
146 (const_int 4)))
148 ;; Processor type -- this attribute must exactly match the processor_type
149 ;; enumeration in rs6000.h.
151 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
152 (const (symbol_ref "rs6000_cpu_attr")))
155 ;; If this instruction is microcoded on the CELL processor
156 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
157 (define_attr "cell_micro" "not,conditional,always"
158 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
159 (const_string "always")
160 (const_string "not")))
162 (automata_option "ndfa")
164 (include "rios1.md")
165 (include "rios2.md")
166 (include "rs64.md")
167 (include "mpc.md")
168 (include "40x.md")
169 (include "440.md")
170 (include "476.md")
171 (include "603.md")
172 (include "6xx.md")
173 (include "7xx.md")
174 (include "7450.md")
175 (include "8540.md")
176 (include "e300c2c3.md")
177 (include "e500mc.md")
178 (include "e500mc64.md")
179 (include "power4.md")
180 (include "power5.md")
181 (include "power6.md")
182 (include "power7.md")
183 (include "cell.md")
184 (include "xfpu.md")
185 (include "a2.md")
186 (include "titan.md")
188 (include "predicates.md")
189 (include "constraints.md")
191 (include "darwin.md")
193 \f
194 ;; Mode iterators
196 ; This mode iterator allows :GPR to be used to indicate the allowable size
197 ; of whole values in GPRs.
198 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
200 ; Any supported integer mode.
201 (define_mode_iterator INT [QI HI SI DI TI])
203 ; Any supported integer mode that fits in one register.
204 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
206 ; extend modes for DImode
207 (define_mode_iterator QHSI [QI HI SI])
209 ; SImode or DImode, even if DImode doesn't fit in GPRs.
210 (define_mode_iterator SDI [SI DI])
212 ; The size of a pointer. Also, the size of the value that a record-condition
213 ; (one with a '.') will compare; and the size used for arithmetic carries.
214 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
216 ; Any hardware-supported floating-point mode
217 (define_mode_iterator FP [
218 (SF "TARGET_HARD_FLOAT
219 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
220 (DF "TARGET_HARD_FLOAT
221 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
222 (TF "!TARGET_IEEEQUAD
223 && TARGET_HARD_FLOAT
224 && (TARGET_FPRS || TARGET_E500_DOUBLE)
225 && TARGET_LONG_DOUBLE_128")
226 (DD "TARGET_DFP")
227 (TD "TARGET_DFP")])
229 ; Any fma capable floating-point mode.
230 (define_mode_iterator FMA_F [
231 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
232 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
233 || VECTOR_UNIT_VSX_P (DFmode)")
234 (V2SF "TARGET_PAIRED_FLOAT")
235 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
236 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
237 ])
239 ; These modes do not fit in integer registers in 32-bit mode.
240 ; but on e500v2, the gpr are 64 bit registers
241 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
243 ; Iterator for reciprocal estimate instructions
244 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
246 ; Iterator for just SF/DF
247 (define_mode_iterator SFDF [SF DF])
249 ; Various instructions that come in SI and DI forms.
250 ; A generic w/d attribute, for things like cmpw/cmpd.
251 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
253 ; DImode bits
254 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
256 ;; ISEL/ISEL64 target selection
257 (define_mode_attr sel [(SI "") (DI "64")])
259 ;; Suffix for reload patterns
260 (define_mode_attr ptrsize [(SI "32bit")
261 (DI "64bit")])
263 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
264 (DI "TARGET_64BIT")])
266 (define_mode_attr mptrsize [(SI "si")
267 (DI "di")])
269 (define_mode_attr rreg [(SF "f")
270 (DF "ws")
271 (V4SF "wf")
272 (V2DF "wd")])
274 (define_mode_attr rreg2 [(SF "f")
275 (DF "d")])
277 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
278 (DF "TARGET_FCFID")])
280 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
281 (DF "TARGET_E500_DOUBLE")])
283 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
284 (DF "TARGET_DOUBLE_FLOAT")])
285 \f
286 ;; Start with fixed-point load and store insns. Here we put only the more
287 ;; complex forms. Basic data transfer is done later.
289 (define_expand "zero_extend<mode>di2"
290 [(set (match_operand:DI 0 "gpc_reg_operand" "")
291 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
292 "TARGET_POWERPC64"
293 "")
295 (define_insn "*zero_extend<mode>di2_internal1"
296 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
297 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
298 "TARGET_POWERPC64"
299 "@
300 l<wd>z%U1%X1 %0,%1
301 rldicl %0,%1,0,<dbits>"
302 [(set_attr "type" "load,*")])
304 (define_insn "*zero_extend<mode>di2_internal2"
305 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
306 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
307 (const_int 0)))
308 (clobber (match_scratch:DI 2 "=r,r"))]
309 "TARGET_64BIT"
310 "@
311 rldicl. %2,%1,0,<dbits>
312 #"
313 [(set_attr "type" "compare")
314 (set_attr "length" "4,8")])
316 (define_split
317 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
318 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
319 (const_int 0)))
320 (clobber (match_scratch:DI 2 ""))]
321 "TARGET_POWERPC64 && reload_completed"
322 [(set (match_dup 2)
323 (zero_extend:DI (match_dup 1)))
324 (set (match_dup 0)
325 (compare:CC (match_dup 2)
326 (const_int 0)))]
327 "")
329 (define_insn "*zero_extend<mode>di2_internal3"
330 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
331 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
332 (const_int 0)))
333 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
334 (zero_extend:DI (match_dup 1)))]
335 "TARGET_64BIT"
336 "@
337 rldicl. %0,%1,0,<dbits>
338 #"
339 [(set_attr "type" "compare")
340 (set_attr "length" "4,8")])
342 (define_split
343 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
344 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
345 (const_int 0)))
346 (set (match_operand:DI 0 "gpc_reg_operand" "")
347 (zero_extend:DI (match_dup 1)))]
348 "TARGET_POWERPC64 && reload_completed"
349 [(set (match_dup 0)
350 (zero_extend:DI (match_dup 1)))
351 (set (match_dup 2)
352 (compare:CC (match_dup 0)
353 (const_int 0)))]
354 "")
356 (define_insn "extendqidi2"
357 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
358 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
359 "TARGET_POWERPC64"
360 "extsb %0,%1"
361 [(set_attr "type" "exts")])
363 (define_insn ""
364 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
365 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
366 (const_int 0)))
367 (clobber (match_scratch:DI 2 "=r,r"))]
368 "TARGET_64BIT"
369 "@
370 extsb. %2,%1
371 #"
372 [(set_attr "type" "compare")
373 (set_attr "length" "4,8")])
375 (define_split
376 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
377 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
378 (const_int 0)))
379 (clobber (match_scratch:DI 2 ""))]
380 "TARGET_POWERPC64 && reload_completed"
381 [(set (match_dup 2)
382 (sign_extend:DI (match_dup 1)))
383 (set (match_dup 0)
384 (compare:CC (match_dup 2)
385 (const_int 0)))]
386 "")
388 (define_insn ""
389 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
390 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
391 (const_int 0)))
392 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
393 (sign_extend:DI (match_dup 1)))]
394 "TARGET_64BIT"
395 "@
396 extsb. %0,%1
397 #"
398 [(set_attr "type" "compare")
399 (set_attr "length" "4,8")])
401 (define_split
402 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
403 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
404 (const_int 0)))
405 (set (match_operand:DI 0 "gpc_reg_operand" "")
406 (sign_extend:DI (match_dup 1)))]
407 "TARGET_POWERPC64 && reload_completed"
408 [(set (match_dup 0)
409 (sign_extend:DI (match_dup 1)))
410 (set (match_dup 2)
411 (compare:CC (match_dup 0)
412 (const_int 0)))]
413 "")
415 (define_expand "extendhidi2"
416 [(set (match_operand:DI 0 "gpc_reg_operand" "")
417 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
418 "TARGET_POWERPC64"
419 "")
421 (define_insn ""
422 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
423 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
424 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
425 "@
426 lha%U1%X1 %0,%1
427 extsh %0,%1"
428 [(set_attr "type" "load_ext,exts")])
430 (define_insn ""
431 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
432 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
433 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
434 "extsh %0,%1"
435 [(set_attr "type" "exts")])
437 (define_insn ""
438 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
439 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
440 (const_int 0)))
441 (clobber (match_scratch:DI 2 "=r,r"))]
442 "TARGET_64BIT"
443 "@
444 extsh. %2,%1
445 #"
446 [(set_attr "type" "compare")
447 (set_attr "length" "4,8")])
449 (define_split
450 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
451 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
452 (const_int 0)))
453 (clobber (match_scratch:DI 2 ""))]
454 "TARGET_POWERPC64 && reload_completed"
455 [(set (match_dup 2)
456 (sign_extend:DI (match_dup 1)))
457 (set (match_dup 0)
458 (compare:CC (match_dup 2)
459 (const_int 0)))]
460 "")
462 (define_insn ""
463 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
464 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
465 (const_int 0)))
466 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
467 (sign_extend:DI (match_dup 1)))]
468 "TARGET_64BIT"
469 "@
470 extsh. %0,%1
471 #"
472 [(set_attr "type" "compare")
473 (set_attr "length" "4,8")])
475 (define_split
476 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
477 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
478 (const_int 0)))
479 (set (match_operand:DI 0 "gpc_reg_operand" "")
480 (sign_extend:DI (match_dup 1)))]
481 "TARGET_POWERPC64 && reload_completed"
482 [(set (match_dup 0)
483 (sign_extend:DI (match_dup 1)))
484 (set (match_dup 2)
485 (compare:CC (match_dup 0)
486 (const_int 0)))]
487 "")
489 (define_expand "extendsidi2"
490 [(set (match_operand:DI 0 "gpc_reg_operand" "")
491 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
492 "TARGET_POWERPC64"
493 "")
495 (define_insn ""
496 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
497 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
498 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
499 "@
500 lwa%U1%X1 %0,%1
501 extsw %0,%1"
502 [(set_attr "type" "load_ext,exts")])
504 (define_insn ""
505 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
506 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
507 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
508 "extsw %0,%1"
509 [(set_attr "type" "exts")])
511 (define_insn ""
512 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
513 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
514 (const_int 0)))
515 (clobber (match_scratch:DI 2 "=r,r"))]
516 "TARGET_64BIT"
517 "@
518 extsw. %2,%1
519 #"
520 [(set_attr "type" "compare")
521 (set_attr "length" "4,8")])
523 (define_split
524 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
525 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
526 (const_int 0)))
527 (clobber (match_scratch:DI 2 ""))]
528 "TARGET_POWERPC64 && reload_completed"
529 [(set (match_dup 2)
530 (sign_extend:DI (match_dup 1)))
531 (set (match_dup 0)
532 (compare:CC (match_dup 2)
533 (const_int 0)))]
534 "")
536 (define_insn ""
537 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
538 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
539 (const_int 0)))
540 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
541 (sign_extend:DI (match_dup 1)))]
542 "TARGET_64BIT"
543 "@
544 extsw. %0,%1
545 #"
546 [(set_attr "type" "compare")
547 (set_attr "length" "4,8")])
549 (define_split
550 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
551 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
552 (const_int 0)))
553 (set (match_operand:DI 0 "gpc_reg_operand" "")
554 (sign_extend:DI (match_dup 1)))]
555 "TARGET_POWERPC64 && reload_completed"
556 [(set (match_dup 0)
557 (sign_extend:DI (match_dup 1)))
558 (set (match_dup 2)
559 (compare:CC (match_dup 0)
560 (const_int 0)))]
561 "")
563 (define_expand "zero_extendqisi2"
564 [(set (match_operand:SI 0 "gpc_reg_operand" "")
565 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
566 ""
567 "")
569 (define_insn ""
570 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
571 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
572 ""
573 "@
574 lbz%U1%X1 %0,%1
575 {rlinm|rlwinm} %0,%1,0,0xff"
576 [(set_attr "type" "load,*")])
578 (define_insn ""
579 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
580 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
581 (const_int 0)))
582 (clobber (match_scratch:SI 2 "=r,r"))]
583 ""
584 "@
585 {andil.|andi.} %2,%1,0xff
586 #"
587 [(set_attr "type" "fast_compare,compare")
588 (set_attr "length" "4,8")])
590 (define_split
591 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
592 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
593 (const_int 0)))
594 (clobber (match_scratch:SI 2 ""))]
595 "reload_completed"
596 [(set (match_dup 2)
597 (zero_extend:SI (match_dup 1)))
598 (set (match_dup 0)
599 (compare:CC (match_dup 2)
600 (const_int 0)))]
601 "")
603 (define_insn ""
604 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
605 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
606 (const_int 0)))
607 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
608 (zero_extend:SI (match_dup 1)))]
609 ""
610 "@
611 {andil.|andi.} %0,%1,0xff
612 #"
613 [(set_attr "type" "fast_compare,compare")
614 (set_attr "length" "4,8")])
616 (define_split
617 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
618 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
619 (const_int 0)))
620 (set (match_operand:SI 0 "gpc_reg_operand" "")
621 (zero_extend:SI (match_dup 1)))]
622 "reload_completed"
623 [(set (match_dup 0)
624 (zero_extend:SI (match_dup 1)))
625 (set (match_dup 2)
626 (compare:CC (match_dup 0)
627 (const_int 0)))]
628 "")
630 (define_expand "extendqisi2"
631 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
632 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
633 ""
634 "
635 {
636 if (TARGET_POWERPC)
637 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
638 else if (TARGET_POWER)
639 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
640 else
641 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
642 DONE;
643 }")
645 (define_insn "extendqisi2_ppc"
646 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
647 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
648 "TARGET_POWERPC"
649 "extsb %0,%1"
650 [(set_attr "type" "exts")])
652 (define_insn ""
653 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
654 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
655 (const_int 0)))
656 (clobber (match_scratch:SI 2 "=r,r"))]
657 "TARGET_POWERPC"
658 "@
659 extsb. %2,%1
660 #"
661 [(set_attr "type" "compare")
662 (set_attr "length" "4,8")])
664 (define_split
665 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
666 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
667 (const_int 0)))
668 (clobber (match_scratch:SI 2 ""))]
669 "TARGET_POWERPC && reload_completed"
670 [(set (match_dup 2)
671 (sign_extend:SI (match_dup 1)))
672 (set (match_dup 0)
673 (compare:CC (match_dup 2)
674 (const_int 0)))]
675 "")
677 (define_insn ""
678 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
679 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
680 (const_int 0)))
681 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
682 (sign_extend:SI (match_dup 1)))]
683 "TARGET_POWERPC"
684 "@
685 extsb. %0,%1
686 #"
687 [(set_attr "type" "compare")
688 (set_attr "length" "4,8")])
690 (define_split
691 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
692 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
693 (const_int 0)))
694 (set (match_operand:SI 0 "gpc_reg_operand" "")
695 (sign_extend:SI (match_dup 1)))]
696 "TARGET_POWERPC && reload_completed"
697 [(set (match_dup 0)
698 (sign_extend:SI (match_dup 1)))
699 (set (match_dup 2)
700 (compare:CC (match_dup 0)
701 (const_int 0)))]
702 "")
704 (define_expand "extendqisi2_power"
705 [(parallel [(set (match_dup 2)
706 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
707 (const_int 24)))
708 (clobber (scratch:SI))])
709 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
710 (ashiftrt:SI (match_dup 2)
711 (const_int 24)))
712 (clobber (scratch:SI))])]
713 "TARGET_POWER"
714 "
715 { operands[1] = gen_lowpart (SImode, operands[1]);
716 operands[2] = gen_reg_rtx (SImode); }")
718 (define_expand "extendqisi2_no_power"
719 [(set (match_dup 2)
720 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
721 (const_int 24)))
722 (set (match_operand:SI 0 "gpc_reg_operand" "")
723 (ashiftrt:SI (match_dup 2)
724 (const_int 24)))]
725 "! TARGET_POWER && ! TARGET_POWERPC"
726 "
727 { operands[1] = gen_lowpart (SImode, operands[1]);
728 operands[2] = gen_reg_rtx (SImode); }")
730 (define_expand "zero_extendqihi2"
731 [(set (match_operand:HI 0 "gpc_reg_operand" "")
732 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
733 ""
734 "")
736 (define_insn ""
737 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
738 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
739 ""
740 "@
741 lbz%U1%X1 %0,%1
742 {rlinm|rlwinm} %0,%1,0,0xff"
743 [(set_attr "type" "load,*")])
745 (define_insn ""
746 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
747 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
748 (const_int 0)))
749 (clobber (match_scratch:HI 2 "=r,r"))]
750 ""
751 "@
752 {andil.|andi.} %2,%1,0xff
753 #"
754 [(set_attr "type" "fast_compare,compare")
755 (set_attr "length" "4,8")])
757 (define_split
758 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
759 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
760 (const_int 0)))
761 (clobber (match_scratch:HI 2 ""))]
762 "reload_completed"
763 [(set (match_dup 2)
764 (zero_extend:HI (match_dup 1)))
765 (set (match_dup 0)
766 (compare:CC (match_dup 2)
767 (const_int 0)))]
768 "")
770 (define_insn ""
771 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
772 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
773 (const_int 0)))
774 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
775 (zero_extend:HI (match_dup 1)))]
776 ""
777 "@
778 {andil.|andi.} %0,%1,0xff
779 #"
780 [(set_attr "type" "fast_compare,compare")
781 (set_attr "length" "4,8")])
783 (define_split
784 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
785 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
786 (const_int 0)))
787 (set (match_operand:HI 0 "gpc_reg_operand" "")
788 (zero_extend:HI (match_dup 1)))]
789 "reload_completed"
790 [(set (match_dup 0)
791 (zero_extend:HI (match_dup 1)))
792 (set (match_dup 2)
793 (compare:CC (match_dup 0)
794 (const_int 0)))]
795 "")
797 (define_expand "extendqihi2"
798 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
799 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
800 ""
801 "
802 {
803 if (TARGET_POWERPC)
804 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
805 else if (TARGET_POWER)
806 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
807 else
808 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
809 DONE;
810 }")
812 (define_insn "extendqihi2_ppc"
813 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
814 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
815 "TARGET_POWERPC"
816 "extsb %0,%1"
817 [(set_attr "type" "exts")])
819 (define_insn ""
820 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
821 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
822 (const_int 0)))
823 (clobber (match_scratch:HI 2 "=r,r"))]
824 "TARGET_POWERPC"
825 "@
826 extsb. %2,%1
827 #"
828 [(set_attr "type" "compare")
829 (set_attr "length" "4,8")])
831 (define_split
832 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
833 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
834 (const_int 0)))
835 (clobber (match_scratch:HI 2 ""))]
836 "TARGET_POWERPC && reload_completed"
837 [(set (match_dup 2)
838 (sign_extend:HI (match_dup 1)))
839 (set (match_dup 0)
840 (compare:CC (match_dup 2)
841 (const_int 0)))]
842 "")
844 (define_insn ""
845 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
846 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
847 (const_int 0)))
848 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
849 (sign_extend:HI (match_dup 1)))]
850 "TARGET_POWERPC"
851 "@
852 extsb. %0,%1
853 #"
854 [(set_attr "type" "compare")
855 (set_attr "length" "4,8")])
857 (define_split
858 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
859 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
860 (const_int 0)))
861 (set (match_operand:HI 0 "gpc_reg_operand" "")
862 (sign_extend:HI (match_dup 1)))]
863 "TARGET_POWERPC && reload_completed"
864 [(set (match_dup 0)
865 (sign_extend:HI (match_dup 1)))
866 (set (match_dup 2)
867 (compare:CC (match_dup 0)
868 (const_int 0)))]
869 "")
871 (define_expand "extendqihi2_power"
872 [(parallel [(set (match_dup 2)
873 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
874 (const_int 24)))
875 (clobber (scratch:SI))])
876 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
877 (ashiftrt:SI (match_dup 2)
878 (const_int 24)))
879 (clobber (scratch:SI))])]
880 "TARGET_POWER"
881 "
882 { operands[0] = gen_lowpart (SImode, operands[0]);
883 operands[1] = gen_lowpart (SImode, operands[1]);
884 operands[2] = gen_reg_rtx (SImode); }")
886 (define_expand "extendqihi2_no_power"
887 [(set (match_dup 2)
888 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
889 (const_int 24)))
890 (set (match_operand:HI 0 "gpc_reg_operand" "")
891 (ashiftrt:SI (match_dup 2)
892 (const_int 24)))]
893 "! TARGET_POWER && ! TARGET_POWERPC"
894 "
895 { operands[0] = gen_lowpart (SImode, operands[0]);
896 operands[1] = gen_lowpart (SImode, operands[1]);
897 operands[2] = gen_reg_rtx (SImode); }")
899 (define_expand "zero_extendhisi2"
900 [(set (match_operand:SI 0 "gpc_reg_operand" "")
901 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
902 ""
903 "")
905 (define_insn ""
906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
907 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
908 ""
909 "@
910 lhz%U1%X1 %0,%1
911 {rlinm|rlwinm} %0,%1,0,0xffff"
912 [(set_attr "type" "load,*")])
914 (define_insn ""
915 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
916 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
917 (const_int 0)))
918 (clobber (match_scratch:SI 2 "=r,r"))]
919 ""
920 "@
921 {andil.|andi.} %2,%1,0xffff
922 #"
923 [(set_attr "type" "fast_compare,compare")
924 (set_attr "length" "4,8")])
926 (define_split
927 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
928 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
929 (const_int 0)))
930 (clobber (match_scratch:SI 2 ""))]
931 "reload_completed"
932 [(set (match_dup 2)
933 (zero_extend:SI (match_dup 1)))
934 (set (match_dup 0)
935 (compare:CC (match_dup 2)
936 (const_int 0)))]
937 "")
939 (define_insn ""
940 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
941 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
942 (const_int 0)))
943 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
944 (zero_extend:SI (match_dup 1)))]
945 ""
946 "@
947 {andil.|andi.} %0,%1,0xffff
948 #"
949 [(set_attr "type" "fast_compare,compare")
950 (set_attr "length" "4,8")])
952 (define_split
953 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
954 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
955 (const_int 0)))
956 (set (match_operand:SI 0 "gpc_reg_operand" "")
957 (zero_extend:SI (match_dup 1)))]
958 "reload_completed"
959 [(set (match_dup 0)
960 (zero_extend:SI (match_dup 1)))
961 (set (match_dup 2)
962 (compare:CC (match_dup 0)
963 (const_int 0)))]
964 "")
966 (define_expand "extendhisi2"
967 [(set (match_operand:SI 0 "gpc_reg_operand" "")
968 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
969 ""
970 "")
972 (define_insn ""
973 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
974 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
975 "rs6000_gen_cell_microcode"
976 "@
977 lha%U1%X1 %0,%1
978 {exts|extsh} %0,%1"
979 [(set_attr "type" "load_ext,exts")])
981 (define_insn ""
982 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
983 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
984 "!rs6000_gen_cell_microcode"
985 "{exts|extsh} %0,%1"
986 [(set_attr "type" "exts")])
988 (define_insn ""
989 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
990 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
991 (const_int 0)))
992 (clobber (match_scratch:SI 2 "=r,r"))]
993 ""
994 "@
995 {exts.|extsh.} %2,%1
996 #"
997 [(set_attr "type" "compare")
998 (set_attr "length" "4,8")])
1000 (define_split
1001 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1002 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1003 (const_int 0)))
1004 (clobber (match_scratch:SI 2 ""))]
1005 "reload_completed"
1006 [(set (match_dup 2)
1007 (sign_extend:SI (match_dup 1)))
1008 (set (match_dup 0)
1009 (compare:CC (match_dup 2)
1010 (const_int 0)))]
1011 "")
1013 (define_insn ""
1014 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1015 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1016 (const_int 0)))
1017 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1018 (sign_extend:SI (match_dup 1)))]
1019 ""
1020 "@
1021 {exts.|extsh.} %0,%1
1022 #"
1023 [(set_attr "type" "compare")
1024 (set_attr "length" "4,8")])
1025 \f
1026 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1028 (define_insn "*macchwc"
1029 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1030 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1031 (match_operand:SI 2 "gpc_reg_operand" "r")
1032 (const_int 16))
1033 (sign_extend:SI
1034 (match_operand:HI 1 "gpc_reg_operand" "r")))
1035 (match_operand:SI 4 "gpc_reg_operand" "0"))
1036 (const_int 0)))
1037 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1038 (plus:SI (mult:SI (ashiftrt:SI
1039 (match_dup 2)
1040 (const_int 16))
1041 (sign_extend:SI
1042 (match_dup 1)))
1043 (match_dup 4)))]
1044 "TARGET_MULHW"
1045 "macchw. %0, %1, %2"
1046 [(set_attr "type" "imul3")])
1048 (define_insn "*macchw"
1049 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1050 (plus:SI (mult:SI (ashiftrt:SI
1051 (match_operand:SI 2 "gpc_reg_operand" "r")
1052 (const_int 16))
1053 (sign_extend:SI
1054 (match_operand:HI 1 "gpc_reg_operand" "r")))
1055 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1056 "TARGET_MULHW"
1057 "macchw %0, %1, %2"
1058 [(set_attr "type" "imul3")])
1060 (define_insn "*macchwuc"
1061 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1062 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1063 (match_operand:SI 2 "gpc_reg_operand" "r")
1064 (const_int 16))
1065 (zero_extend:SI
1066 (match_operand:HI 1 "gpc_reg_operand" "r")))
1067 (match_operand:SI 4 "gpc_reg_operand" "0"))
1068 (const_int 0)))
1069 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1070 (plus:SI (mult:SI (lshiftrt:SI
1071 (match_dup 2)
1072 (const_int 16))
1073 (zero_extend:SI
1074 (match_dup 1)))
1075 (match_dup 4)))]
1076 "TARGET_MULHW"
1077 "macchwu. %0, %1, %2"
1078 [(set_attr "type" "imul3")])
1080 (define_insn "*macchwu"
1081 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1082 (plus:SI (mult:SI (lshiftrt:SI
1083 (match_operand:SI 2 "gpc_reg_operand" "r")
1084 (const_int 16))
1085 (zero_extend:SI
1086 (match_operand:HI 1 "gpc_reg_operand" "r")))
1087 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1088 "TARGET_MULHW"
1089 "macchwu %0, %1, %2"
1090 [(set_attr "type" "imul3")])
1092 (define_insn "*machhwc"
1093 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1094 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1095 (match_operand:SI 1 "gpc_reg_operand" "%r")
1096 (const_int 16))
1097 (ashiftrt:SI
1098 (match_operand:SI 2 "gpc_reg_operand" "r")
1099 (const_int 16)))
1100 (match_operand:SI 4 "gpc_reg_operand" "0"))
1101 (const_int 0)))
1102 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1103 (plus:SI (mult:SI (ashiftrt:SI
1104 (match_dup 1)
1105 (const_int 16))
1106 (ashiftrt:SI
1107 (match_dup 2)
1108 (const_int 16)))
1109 (match_dup 4)))]
1110 "TARGET_MULHW"
1111 "machhw. %0, %1, %2"
1112 [(set_attr "type" "imul3")])
1114 (define_insn "*machhw"
1115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1116 (plus:SI (mult:SI (ashiftrt:SI
1117 (match_operand:SI 1 "gpc_reg_operand" "%r")
1118 (const_int 16))
1119 (ashiftrt:SI
1120 (match_operand:SI 2 "gpc_reg_operand" "r")
1121 (const_int 16)))
1122 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1123 "TARGET_MULHW"
1124 "machhw %0, %1, %2"
1125 [(set_attr "type" "imul3")])
1127 (define_insn "*machhwuc"
1128 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1129 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1130 (match_operand:SI 1 "gpc_reg_operand" "%r")
1131 (const_int 16))
1132 (lshiftrt:SI
1133 (match_operand:SI 2 "gpc_reg_operand" "r")
1134 (const_int 16)))
1135 (match_operand:SI 4 "gpc_reg_operand" "0"))
1136 (const_int 0)))
1137 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1138 (plus:SI (mult:SI (lshiftrt:SI
1139 (match_dup 1)
1140 (const_int 16))
1141 (lshiftrt:SI
1142 (match_dup 2)
1143 (const_int 16)))
1144 (match_dup 4)))]
1145 "TARGET_MULHW"
1146 "machhwu. %0, %1, %2"
1147 [(set_attr "type" "imul3")])
1149 (define_insn "*machhwu"
1150 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1151 (plus:SI (mult:SI (lshiftrt:SI
1152 (match_operand:SI 1 "gpc_reg_operand" "%r")
1153 (const_int 16))
1154 (lshiftrt:SI
1155 (match_operand:SI 2 "gpc_reg_operand" "r")
1156 (const_int 16)))
1157 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1158 "TARGET_MULHW"
1159 "machhwu %0, %1, %2"
1160 [(set_attr "type" "imul3")])
1162 (define_insn "*maclhwc"
1163 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1164 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1165 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1166 (sign_extend:SI
1167 (match_operand:HI 2 "gpc_reg_operand" "r")))
1168 (match_operand:SI 4 "gpc_reg_operand" "0"))
1169 (const_int 0)))
1170 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1171 (plus:SI (mult:SI (sign_extend:SI
1172 (match_dup 1))
1173 (sign_extend:SI
1174 (match_dup 2)))
1175 (match_dup 4)))]
1176 "TARGET_MULHW"
1177 "maclhw. %0, %1, %2"
1178 [(set_attr "type" "imul3")])
1180 (define_insn "*maclhw"
1181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1182 (plus:SI (mult:SI (sign_extend:SI
1183 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1184 (sign_extend:SI
1185 (match_operand:HI 2 "gpc_reg_operand" "r")))
1186 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1187 "TARGET_MULHW"
1188 "maclhw %0, %1, %2"
1189 [(set_attr "type" "imul3")])
1191 (define_insn "*maclhwuc"
1192 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1193 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1194 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1195 (zero_extend:SI
1196 (match_operand:HI 2 "gpc_reg_operand" "r")))
1197 (match_operand:SI 4 "gpc_reg_operand" "0"))
1198 (const_int 0)))
1199 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1200 (plus:SI (mult:SI (zero_extend:SI
1201 (match_dup 1))
1202 (zero_extend:SI
1203 (match_dup 2)))
1204 (match_dup 4)))]
1205 "TARGET_MULHW"
1206 "maclhwu. %0, %1, %2"
1207 [(set_attr "type" "imul3")])
1209 (define_insn "*maclhwu"
1210 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1211 (plus:SI (mult:SI (zero_extend:SI
1212 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1213 (zero_extend:SI
1214 (match_operand:HI 2 "gpc_reg_operand" "r")))
1215 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1216 "TARGET_MULHW"
1217 "maclhwu %0, %1, %2"
1218 [(set_attr "type" "imul3")])
1220 (define_insn "*nmacchwc"
1221 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1222 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1223 (mult:SI (ashiftrt:SI
1224 (match_operand:SI 2 "gpc_reg_operand" "r")
1225 (const_int 16))
1226 (sign_extend:SI
1227 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1228 (const_int 0)))
1229 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1230 (minus:SI (match_dup 4)
1231 (mult:SI (ashiftrt:SI
1232 (match_dup 2)
1233 (const_int 16))
1234 (sign_extend:SI
1235 (match_dup 1)))))]
1236 "TARGET_MULHW"
1237 "nmacchw. %0, %1, %2"
1238 [(set_attr "type" "imul3")])
1240 (define_insn "*nmacchw"
1241 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1242 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1243 (mult:SI (ashiftrt:SI
1244 (match_operand:SI 2 "gpc_reg_operand" "r")
1245 (const_int 16))
1246 (sign_extend:SI
1247 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1248 "TARGET_MULHW"
1249 "nmacchw %0, %1, %2"
1250 [(set_attr "type" "imul3")])
1252 (define_insn "*nmachhwc"
1253 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1254 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1255 (mult:SI (ashiftrt:SI
1256 (match_operand:SI 1 "gpc_reg_operand" "%r")
1257 (const_int 16))
1258 (ashiftrt:SI
1259 (match_operand:SI 2 "gpc_reg_operand" "r")
1260 (const_int 16))))
1261 (const_int 0)))
1262 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1263 (minus:SI (match_dup 4)
1264 (mult:SI (ashiftrt:SI
1265 (match_dup 1)
1266 (const_int 16))
1267 (ashiftrt:SI
1268 (match_dup 2)
1269 (const_int 16)))))]
1270 "TARGET_MULHW"
1271 "nmachhw. %0, %1, %2"
1272 [(set_attr "type" "imul3")])
1274 (define_insn "*nmachhw"
1275 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1276 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1277 (mult:SI (ashiftrt:SI
1278 (match_operand:SI 1 "gpc_reg_operand" "%r")
1279 (const_int 16))
1280 (ashiftrt:SI
1281 (match_operand:SI 2 "gpc_reg_operand" "r")
1282 (const_int 16)))))]
1283 "TARGET_MULHW"
1284 "nmachhw %0, %1, %2"
1285 [(set_attr "type" "imul3")])
1287 (define_insn "*nmaclhwc"
1288 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1289 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1290 (mult:SI (sign_extend:SI
1291 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1292 (sign_extend:SI
1293 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1294 (const_int 0)))
1295 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1296 (minus:SI (match_dup 4)
1297 (mult:SI (sign_extend:SI
1298 (match_dup 1))
1299 (sign_extend:SI
1300 (match_dup 2)))))]
1301 "TARGET_MULHW"
1302 "nmaclhw. %0, %1, %2"
1303 [(set_attr "type" "imul3")])
1305 (define_insn "*nmaclhw"
1306 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1307 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1308 (mult:SI (sign_extend:SI
1309 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1310 (sign_extend:SI
1311 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1312 "TARGET_MULHW"
1313 "nmaclhw %0, %1, %2"
1314 [(set_attr "type" "imul3")])
1316 (define_insn "*mulchwc"
1317 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1318 (compare:CC (mult:SI (ashiftrt:SI
1319 (match_operand:SI 2 "gpc_reg_operand" "r")
1320 (const_int 16))
1321 (sign_extend:SI
1322 (match_operand:HI 1 "gpc_reg_operand" "r")))
1323 (const_int 0)))
1324 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1325 (mult:SI (ashiftrt:SI
1326 (match_dup 2)
1327 (const_int 16))
1328 (sign_extend:SI
1329 (match_dup 1))))]
1330 "TARGET_MULHW"
1331 "mulchw. %0, %1, %2"
1332 [(set_attr "type" "imul3")])
1334 (define_insn "*mulchw"
1335 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1336 (mult:SI (ashiftrt:SI
1337 (match_operand:SI 2 "gpc_reg_operand" "r")
1338 (const_int 16))
1339 (sign_extend:SI
1340 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1341 "TARGET_MULHW"
1342 "mulchw %0, %1, %2"
1343 [(set_attr "type" "imul3")])
1345 (define_insn "*mulchwuc"
1346 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1347 (compare:CC (mult:SI (lshiftrt:SI
1348 (match_operand:SI 2 "gpc_reg_operand" "r")
1349 (const_int 16))
1350 (zero_extend:SI
1351 (match_operand:HI 1 "gpc_reg_operand" "r")))
1352 (const_int 0)))
1353 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1354 (mult:SI (lshiftrt:SI
1355 (match_dup 2)
1356 (const_int 16))
1357 (zero_extend:SI
1358 (match_dup 1))))]
1359 "TARGET_MULHW"
1360 "mulchwu. %0, %1, %2"
1361 [(set_attr "type" "imul3")])
1363 (define_insn "*mulchwu"
1364 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1365 (mult:SI (lshiftrt:SI
1366 (match_operand:SI 2 "gpc_reg_operand" "r")
1367 (const_int 16))
1368 (zero_extend:SI
1369 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1370 "TARGET_MULHW"
1371 "mulchwu %0, %1, %2"
1372 [(set_attr "type" "imul3")])
1374 (define_insn "*mulhhwc"
1375 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1376 (compare:CC (mult:SI (ashiftrt:SI
1377 (match_operand:SI 1 "gpc_reg_operand" "%r")
1378 (const_int 16))
1379 (ashiftrt:SI
1380 (match_operand:SI 2 "gpc_reg_operand" "r")
1381 (const_int 16)))
1382 (const_int 0)))
1383 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1384 (mult:SI (ashiftrt:SI
1385 (match_dup 1)
1386 (const_int 16))
1387 (ashiftrt:SI
1388 (match_dup 2)
1389 (const_int 16))))]
1390 "TARGET_MULHW"
1391 "mulhhw. %0, %1, %2"
1392 [(set_attr "type" "imul3")])
1394 (define_insn "*mulhhw"
1395 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1396 (mult:SI (ashiftrt:SI
1397 (match_operand:SI 1 "gpc_reg_operand" "%r")
1398 (const_int 16))
1399 (ashiftrt:SI
1400 (match_operand:SI 2 "gpc_reg_operand" "r")
1401 (const_int 16))))]
1402 "TARGET_MULHW"
1403 "mulhhw %0, %1, %2"
1404 [(set_attr "type" "imul3")])
1406 (define_insn "*mulhhwuc"
1407 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1408 (compare:CC (mult:SI (lshiftrt:SI
1409 (match_operand:SI 1 "gpc_reg_operand" "%r")
1410 (const_int 16))
1411 (lshiftrt:SI
1412 (match_operand:SI 2 "gpc_reg_operand" "r")
1413 (const_int 16)))
1414 (const_int 0)))
1415 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1416 (mult:SI (lshiftrt:SI
1417 (match_dup 1)
1418 (const_int 16))
1419 (lshiftrt:SI
1420 (match_dup 2)
1421 (const_int 16))))]
1422 "TARGET_MULHW"
1423 "mulhhwu. %0, %1, %2"
1424 [(set_attr "type" "imul3")])
1426 (define_insn "*mulhhwu"
1427 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1428 (mult:SI (lshiftrt:SI
1429 (match_operand:SI 1 "gpc_reg_operand" "%r")
1430 (const_int 16))
1431 (lshiftrt:SI
1432 (match_operand:SI 2 "gpc_reg_operand" "r")
1433 (const_int 16))))]
1434 "TARGET_MULHW"
1435 "mulhhwu %0, %1, %2"
1436 [(set_attr "type" "imul3")])
1438 (define_insn "*mullhwc"
1439 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1440 (compare:CC (mult:SI (sign_extend:SI
1441 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1442 (sign_extend:SI
1443 (match_operand:HI 2 "gpc_reg_operand" "r")))
1444 (const_int 0)))
1445 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1446 (mult:SI (sign_extend:SI
1447 (match_dup 1))
1448 (sign_extend:SI
1449 (match_dup 2))))]
1450 "TARGET_MULHW"
1451 "mullhw. %0, %1, %2"
1452 [(set_attr "type" "imul3")])
1454 (define_insn "*mullhw"
1455 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1456 (mult:SI (sign_extend:SI
1457 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1458 (sign_extend:SI
1459 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1460 "TARGET_MULHW"
1461 "mullhw %0, %1, %2"
1462 [(set_attr "type" "imul3")])
1464 (define_insn "*mullhwuc"
1465 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1466 (compare:CC (mult:SI (zero_extend:SI
1467 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1468 (zero_extend:SI
1469 (match_operand:HI 2 "gpc_reg_operand" "r")))
1470 (const_int 0)))
1471 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1472 (mult:SI (zero_extend:SI
1473 (match_dup 1))
1474 (zero_extend:SI
1475 (match_dup 2))))]
1476 "TARGET_MULHW"
1477 "mullhwu. %0, %1, %2"
1478 [(set_attr "type" "imul3")])
1480 (define_insn "*mullhwu"
1481 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1482 (mult:SI (zero_extend:SI
1483 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1484 (zero_extend:SI
1485 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1486 "TARGET_MULHW"
1487 "mullhwu %0, %1, %2"
1488 [(set_attr "type" "imul3")])
1489 \f
1490 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1491 (define_insn "dlmzb"
1492 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1493 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1494 (match_operand:SI 2 "gpc_reg_operand" "r")]
1495 UNSPEC_DLMZB_CR))
1496 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1497 (unspec:SI [(match_dup 1)
1498 (match_dup 2)]
1499 UNSPEC_DLMZB))]
1500 "TARGET_DLMZB"
1501 "dlmzb. %0, %1, %2")
1503 (define_expand "strlensi"
1504 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1505 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1506 (match_operand:QI 2 "const_int_operand" "")
1507 (match_operand 3 "const_int_operand" "")]
1508 UNSPEC_DLMZB_STRLEN))
1509 (clobber (match_scratch:CC 4 "=x"))]
1510 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1511 {
1512 rtx result = operands[0];
1513 rtx src = operands[1];
1514 rtx search_char = operands[2];
1515 rtx align = operands[3];
1516 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1517 rtx loop_label, end_label, mem, cr0, cond;
1518 if (search_char != const0_rtx
1519 || GET_CODE (align) != CONST_INT
1520 || INTVAL (align) < 8)
1521 FAIL;
1522 word1 = gen_reg_rtx (SImode);
1523 word2 = gen_reg_rtx (SImode);
1524 scratch_dlmzb = gen_reg_rtx (SImode);
1525 scratch_string = gen_reg_rtx (Pmode);
1526 loop_label = gen_label_rtx ();
1527 end_label = gen_label_rtx ();
1528 addr = force_reg (Pmode, XEXP (src, 0));
1529 emit_move_insn (scratch_string, addr);
1530 emit_label (loop_label);
1531 mem = change_address (src, SImode, scratch_string);
1532 emit_move_insn (word1, mem);
1533 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1534 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1535 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1536 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1537 emit_jump_insn (gen_rtx_SET (VOIDmode,
1538 pc_rtx,
1539 gen_rtx_IF_THEN_ELSE (VOIDmode,
1540 cond,
1541 gen_rtx_LABEL_REF
1542 (VOIDmode,
1543 end_label),
1544 pc_rtx)));
1545 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1546 emit_jump_insn (gen_rtx_SET (VOIDmode,
1547 pc_rtx,
1548 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1549 emit_barrier ();
1550 emit_label (end_label);
1551 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1552 emit_insn (gen_subsi3 (result, scratch_string, addr));
1553 emit_insn (gen_subsi3 (result, result, const1_rtx));
1554 DONE;
1555 })
1556 \f
1557 (define_split
1558 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1559 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1560 (const_int 0)))
1561 (set (match_operand:SI 0 "gpc_reg_operand" "")
1562 (sign_extend:SI (match_dup 1)))]
1563 "reload_completed"
1564 [(set (match_dup 0)
1565 (sign_extend:SI (match_dup 1)))
1566 (set (match_dup 2)
1567 (compare:CC (match_dup 0)
1568 (const_int 0)))]
1569 "")
1571 ;; Fixed-point arithmetic insns.
1573 (define_expand "add<mode>3"
1574 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1575 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1576 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1577 ""
1578 {
1579 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1580 {
1581 if (non_short_cint_operand (operands[2], DImode))
1582 FAIL;
1583 }
1584 else if (GET_CODE (operands[2]) == CONST_INT
1585 && ! add_operand (operands[2], <MODE>mode))
1586 {
1587 rtx tmp = ((!can_create_pseudo_p ()
1588 || rtx_equal_p (operands[0], operands[1]))
1589 ? operands[0] : gen_reg_rtx (<MODE>mode));
1591 HOST_WIDE_INT val = INTVAL (operands[2]);
1592 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1593 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1595 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1596 FAIL;
1598 /* The ordering here is important for the prolog expander.
1599 When space is allocated from the stack, adding 'low' first may
1600 produce a temporary deallocation (which would be bad). */
1601 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1602 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1603 DONE;
1604 }
1605 })
1607 ;; Discourage ai/addic because of carry but provide it in an alternative
1608 ;; allowing register zero as source.
1609 (define_insn "*add<mode>3_internal1"
1610 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1611 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1612 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1613 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1614 "@
1615 {cax|add} %0,%1,%2
1616 {cal %0,%2(%1)|addi %0,%1,%2}
1617 {ai|addic} %0,%1,%2
1618 {cau|addis} %0,%1,%v2"
1619 [(set_attr "length" "4,4,4,4")])
1621 (define_insn "addsi3_high"
1622 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1623 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1624 (high:SI (match_operand 2 "" ""))))]
1625 "TARGET_MACHO && !TARGET_64BIT"
1626 "{cau|addis} %0,%1,ha16(%2)"
1627 [(set_attr "length" "4")])
1629 (define_insn "*add<mode>3_internal2"
1630 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1631 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1632 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1633 (const_int 0)))
1634 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1635 ""
1636 "@
1637 {cax.|add.} %3,%1,%2
1638 {ai.|addic.} %3,%1,%2
1639 #
1640 #"
1641 [(set_attr "type" "fast_compare,compare,compare,compare")
1642 (set_attr "length" "4,4,8,8")])
1644 (define_split
1645 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1646 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1647 (match_operand:GPR 2 "reg_or_short_operand" ""))
1648 (const_int 0)))
1649 (clobber (match_scratch:GPR 3 ""))]
1650 "reload_completed"
1651 [(set (match_dup 3)
1652 (plus:GPR (match_dup 1)
1653 (match_dup 2)))
1654 (set (match_dup 0)
1655 (compare:CC (match_dup 3)
1656 (const_int 0)))]
1657 "")
1659 (define_insn "*add<mode>3_internal3"
1660 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1661 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1662 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1663 (const_int 0)))
1664 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1665 (plus:P (match_dup 1)
1666 (match_dup 2)))]
1667 ""
1668 "@
1669 {cax.|add.} %0,%1,%2
1670 {ai.|addic.} %0,%1,%2
1671 #
1672 #"
1673 [(set_attr "type" "fast_compare,compare,compare,compare")
1674 (set_attr "length" "4,4,8,8")])
1676 (define_split
1677 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1678 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1679 (match_operand:P 2 "reg_or_short_operand" ""))
1680 (const_int 0)))
1681 (set (match_operand:P 0 "gpc_reg_operand" "")
1682 (plus:P (match_dup 1) (match_dup 2)))]
1683 "reload_completed"
1684 [(set (match_dup 0)
1685 (plus:P (match_dup 1)
1686 (match_dup 2)))
1687 (set (match_dup 3)
1688 (compare:CC (match_dup 0)
1689 (const_int 0)))]
1690 "")
1692 ;; Split an add that we can't do in one insn into two insns, each of which
1693 ;; does one 16-bit part. This is used by combine. Note that the low-order
1694 ;; add should be last in case the result gets used in an address.
1696 (define_split
1697 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1698 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1699 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1700 ""
1701 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1702 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1703 {
1704 HOST_WIDE_INT val = INTVAL (operands[2]);
1705 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1706 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1708 operands[4] = GEN_INT (low);
1709 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1710 operands[3] = GEN_INT (rest);
1711 else if (can_create_pseudo_p ())
1712 {
1713 operands[3] = gen_reg_rtx (DImode);
1714 emit_move_insn (operands[3], operands[2]);
1715 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1716 DONE;
1717 }
1718 else
1719 FAIL;
1720 })
1722 (define_insn "one_cmpl<mode>2"
1723 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1724 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1725 ""
1726 "nor %0,%1,%1")
1728 (define_insn ""
1729 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1730 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1731 (const_int 0)))
1732 (clobber (match_scratch:P 2 "=r,r"))]
1733 ""
1734 "@
1735 nor. %2,%1,%1
1736 #"
1737 [(set_attr "type" "fast_compare,compare")
1738 (set_attr "length" "4,8")])
1740 (define_split
1741 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1742 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1743 (const_int 0)))
1744 (clobber (match_scratch:P 2 ""))]
1745 "reload_completed"
1746 [(set (match_dup 2)
1747 (not:P (match_dup 1)))
1748 (set (match_dup 0)
1749 (compare:CC (match_dup 2)
1750 (const_int 0)))]
1751 "")
1753 (define_insn ""
1754 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1755 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1756 (const_int 0)))
1757 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1758 (not:P (match_dup 1)))]
1759 ""
1760 "@
1761 nor. %0,%1,%1
1762 #"
1763 [(set_attr "type" "fast_compare,compare")
1764 (set_attr "length" "4,8")])
1766 (define_split
1767 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1768 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1769 (const_int 0)))
1770 (set (match_operand:P 0 "gpc_reg_operand" "")
1771 (not:P (match_dup 1)))]
1772 "reload_completed"
1773 [(set (match_dup 0)
1774 (not:P (match_dup 1)))
1775 (set (match_dup 2)
1776 (compare:CC (match_dup 0)
1777 (const_int 0)))]
1778 "")
1780 (define_insn ""
1781 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1782 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1783 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1784 "! TARGET_POWERPC"
1785 "{sf%I1|subf%I1c} %0,%2,%1")
1787 (define_insn ""
1788 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1789 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1790 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1791 "TARGET_POWERPC"
1792 "@
1793 subf %0,%2,%1
1794 subfic %0,%2,%1")
1796 (define_insn ""
1797 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1798 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1799 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1800 (const_int 0)))
1801 (clobber (match_scratch:SI 3 "=r,r"))]
1802 "! TARGET_POWERPC"
1803 "@
1804 {sf.|subfc.} %3,%2,%1
1805 #"
1806 [(set_attr "type" "compare")
1807 (set_attr "length" "4,8")])
1809 (define_insn ""
1810 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1811 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1812 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1813 (const_int 0)))
1814 (clobber (match_scratch:P 3 "=r,r"))]
1815 "TARGET_POWERPC"
1816 "@
1817 subf. %3,%2,%1
1818 #"
1819 [(set_attr "type" "fast_compare")
1820 (set_attr "length" "4,8")])
1822 (define_split
1823 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1824 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1825 (match_operand:P 2 "gpc_reg_operand" ""))
1826 (const_int 0)))
1827 (clobber (match_scratch:P 3 ""))]
1828 "reload_completed"
1829 [(set (match_dup 3)
1830 (minus:P (match_dup 1)
1831 (match_dup 2)))
1832 (set (match_dup 0)
1833 (compare:CC (match_dup 3)
1834 (const_int 0)))]
1835 "")
1837 (define_insn ""
1838 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1839 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1840 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1841 (const_int 0)))
1842 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1843 (minus:SI (match_dup 1) (match_dup 2)))]
1844 "! TARGET_POWERPC"
1845 "@
1846 {sf.|subfc.} %0,%2,%1
1847 #"
1848 [(set_attr "type" "compare")
1849 (set_attr "length" "4,8")])
1851 (define_insn ""
1852 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1853 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1854 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1855 (const_int 0)))
1856 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1857 (minus:P (match_dup 1)
1858 (match_dup 2)))]
1859 "TARGET_POWERPC"
1860 "@
1861 subf. %0,%2,%1
1862 #"
1863 [(set_attr "type" "fast_compare")
1864 (set_attr "length" "4,8")])
1866 (define_split
1867 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1868 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1869 (match_operand:P 2 "gpc_reg_operand" ""))
1870 (const_int 0)))
1871 (set (match_operand:P 0 "gpc_reg_operand" "")
1872 (minus:P (match_dup 1)
1873 (match_dup 2)))]
1874 "reload_completed"
1875 [(set (match_dup 0)
1876 (minus:P (match_dup 1)
1877 (match_dup 2)))
1878 (set (match_dup 3)
1879 (compare:CC (match_dup 0)
1880 (const_int 0)))]
1881 "")
1883 (define_expand "sub<mode>3"
1884 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1885 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1886 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1887 ""
1888 "
1889 {
1890 if (GET_CODE (operands[2]) == CONST_INT)
1891 {
1892 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1893 negate_rtx (<MODE>mode, operands[2])));
1894 DONE;
1895 }
1896 }")
1898 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1899 ;; instruction and some auxiliary computations. Then we just have a single
1900 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1901 ;; combine.
1903 (define_expand "sminsi3"
1904 [(set (match_dup 3)
1905 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1906 (match_operand:SI 2 "reg_or_short_operand" ""))
1907 (const_int 0)
1908 (minus:SI (match_dup 2) (match_dup 1))))
1909 (set (match_operand:SI 0 "gpc_reg_operand" "")
1910 (minus:SI (match_dup 2) (match_dup 3)))]
1911 "TARGET_POWER || TARGET_ISEL"
1912 "
1913 {
1914 if (TARGET_ISEL)
1915 {
1916 operands[2] = force_reg (SImode, operands[2]);
1917 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1918 DONE;
1919 }
1921 operands[3] = gen_reg_rtx (SImode);
1922 }")
1924 (define_split
1925 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1926 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1927 (match_operand:SI 2 "reg_or_short_operand" "")))
1928 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1929 "TARGET_POWER"
1930 [(set (match_dup 3)
1931 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1932 (const_int 0)
1933 (minus:SI (match_dup 2) (match_dup 1))))
1934 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1935 "")
1937 (define_expand "smaxsi3"
1938 [(set (match_dup 3)
1939 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1940 (match_operand:SI 2 "reg_or_short_operand" ""))
1941 (const_int 0)
1942 (minus:SI (match_dup 2) (match_dup 1))))
1943 (set (match_operand:SI 0 "gpc_reg_operand" "")
1944 (plus:SI (match_dup 3) (match_dup 1)))]
1945 "TARGET_POWER || TARGET_ISEL"
1946 "
1947 {
1948 if (TARGET_ISEL)
1949 {
1950 operands[2] = force_reg (SImode, operands[2]);
1951 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1952 DONE;
1953 }
1954 operands[3] = gen_reg_rtx (SImode);
1955 }")
1957 (define_split
1958 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1959 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1960 (match_operand:SI 2 "reg_or_short_operand" "")))
1961 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1962 "TARGET_POWER"
1963 [(set (match_dup 3)
1964 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1965 (const_int 0)
1966 (minus:SI (match_dup 2) (match_dup 1))))
1967 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1968 "")
1970 (define_expand "uminsi3"
1971 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1972 (match_dup 5)))
1973 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1974 (match_dup 5)))
1975 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1976 (const_int 0)
1977 (minus:SI (match_dup 4) (match_dup 3))))
1978 (set (match_operand:SI 0 "gpc_reg_operand" "")
1979 (minus:SI (match_dup 2) (match_dup 3)))]
1980 "TARGET_POWER || TARGET_ISEL"
1981 "
1982 {
1983 if (TARGET_ISEL)
1984 {
1985 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1986 DONE;
1987 }
1988 operands[3] = gen_reg_rtx (SImode);
1989 operands[4] = gen_reg_rtx (SImode);
1990 operands[5] = GEN_INT (-2147483647 - 1);
1991 }")
1993 (define_expand "umaxsi3"
1994 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1995 (match_dup 5)))
1996 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1997 (match_dup 5)))
1998 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1999 (const_int 0)
2000 (minus:SI (match_dup 4) (match_dup 3))))
2001 (set (match_operand:SI 0 "gpc_reg_operand" "")
2002 (plus:SI (match_dup 3) (match_dup 1)))]
2003 "TARGET_POWER || TARGET_ISEL"
2004 "
2005 {
2006 if (TARGET_ISEL)
2007 {
2008 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
2009 DONE;
2010 }
2011 operands[3] = gen_reg_rtx (SImode);
2012 operands[4] = gen_reg_rtx (SImode);
2013 operands[5] = GEN_INT (-2147483647 - 1);
2014 }")
2016 (define_insn ""
2017 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2018 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
2019 (match_operand:SI 2 "reg_or_short_operand" "rI"))
2020 (const_int 0)
2021 (minus:SI (match_dup 2) (match_dup 1))))]
2022 "TARGET_POWER"
2023 "doz%I2 %0,%1,%2")
2025 (define_insn ""
2026 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2027 (compare:CC
2028 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2029 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2030 (const_int 0)
2031 (minus:SI (match_dup 2) (match_dup 1)))
2032 (const_int 0)))
2033 (clobber (match_scratch:SI 3 "=r,r"))]
2034 "TARGET_POWER"
2035 "@
2036 doz%I2. %3,%1,%2
2037 #"
2038 [(set_attr "type" "delayed_compare")
2039 (set_attr "length" "4,8")])
2041 (define_split
2042 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2043 (compare:CC
2044 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2045 (match_operand:SI 2 "reg_or_short_operand" ""))
2046 (const_int 0)
2047 (minus:SI (match_dup 2) (match_dup 1)))
2048 (const_int 0)))
2049 (clobber (match_scratch:SI 3 ""))]
2050 "TARGET_POWER && reload_completed"
2051 [(set (match_dup 3)
2052 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2053 (const_int 0)
2054 (minus:SI (match_dup 2) (match_dup 1))))
2055 (set (match_dup 0)
2056 (compare:CC (match_dup 3)
2057 (const_int 0)))]
2058 "")
2060 (define_insn ""
2061 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2062 (compare:CC
2063 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2064 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2065 (const_int 0)
2066 (minus:SI (match_dup 2) (match_dup 1)))
2067 (const_int 0)))
2068 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2069 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2070 (const_int 0)
2071 (minus:SI (match_dup 2) (match_dup 1))))]
2072 "TARGET_POWER"
2073 "@
2074 doz%I2. %0,%1,%2
2075 #"
2076 [(set_attr "type" "delayed_compare")
2077 (set_attr "length" "4,8")])
2079 (define_split
2080 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2081 (compare:CC
2082 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2083 (match_operand:SI 2 "reg_or_short_operand" ""))
2084 (const_int 0)
2085 (minus:SI (match_dup 2) (match_dup 1)))
2086 (const_int 0)))
2087 (set (match_operand:SI 0 "gpc_reg_operand" "")
2088 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2089 (const_int 0)
2090 (minus:SI (match_dup 2) (match_dup 1))))]
2091 "TARGET_POWER && reload_completed"
2092 [(set (match_dup 0)
2093 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2094 (const_int 0)
2095 (minus:SI (match_dup 2) (match_dup 1))))
2096 (set (match_dup 3)
2097 (compare:CC (match_dup 0)
2098 (const_int 0)))]
2099 "")
2101 ;; We don't need abs with condition code because such comparisons should
2102 ;; never be done.
2103 (define_expand "abssi2"
2104 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2105 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2106 ""
2107 "
2108 {
2109 if (TARGET_ISEL)
2110 {
2111 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2112 DONE;
2113 }
2114 else if (! TARGET_POWER)
2115 {
2116 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2117 DONE;
2118 }
2119 }")
2121 (define_insn "*abssi2_power"
2122 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2123 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2124 "TARGET_POWER"
2125 "abs %0,%1")
2127 (define_insn_and_split "abs<mode>2_isel"
2128 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2129 (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
2130 (clobber (match_scratch:GPR 2 "=&b"))
2131 (clobber (match_scratch:CC 3 "=y"))]
2132 "TARGET_ISEL"
2133 "#"
2134 "&& reload_completed"
2135 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2136 (set (match_dup 3)
2137 (compare:CC (match_dup 1)
2138 (const_int 0)))
2139 (set (match_dup 0)
2140 (if_then_else:GPR (lt (match_dup 3)
2141 (const_int 0))
2142 (match_dup 2)
2143 (match_dup 1)))]
2144 "")
2146 (define_insn_and_split "nabs<mode>2_isel"
2147 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2148 (neg:GPR (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b"))))
2149 (clobber (match_scratch:GPR 2 "=&b"))
2150 (clobber (match_scratch:CC 3 "=y"))]
2151 "TARGET_ISEL"
2152 "#"
2153 "&& reload_completed"
2154 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2155 (set (match_dup 3)
2156 (compare:CC (match_dup 1)
2157 (const_int 0)))
2158 (set (match_dup 0)
2159 (if_then_else:GPR (lt (match_dup 3)
2160 (const_int 0))
2161 (match_dup 1)
2162 (match_dup 2)))]
2163 "")
2165 (define_insn_and_split "abssi2_nopower"
2166 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2167 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2168 (clobber (match_scratch:SI 2 "=&r,&r"))]
2169 "! TARGET_POWER && ! TARGET_ISEL"
2170 "#"
2171 "&& reload_completed"
2172 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2173 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2174 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2175 "")
2177 (define_insn "*nabs_power"
2178 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2179 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2180 "TARGET_POWER"
2181 "nabs %0,%1")
2183 (define_insn_and_split "*nabs_nopower"
2184 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2185 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2186 (clobber (match_scratch:SI 2 "=&r,&r"))]
2187 "! TARGET_POWER"
2188 "#"
2189 "&& reload_completed"
2190 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2191 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2192 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2193 "")
2195 (define_expand "neg<mode>2"
2196 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2197 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2198 ""
2199 "")
2201 (define_insn "*neg<mode>2_internal"
2202 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2203 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2204 ""
2205 "neg %0,%1")
2207 (define_insn ""
2208 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2209 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2210 (const_int 0)))
2211 (clobber (match_scratch:P 2 "=r,r"))]
2212 ""
2213 "@
2214 neg. %2,%1
2215 #"
2216 [(set_attr "type" "fast_compare")
2217 (set_attr "length" "4,8")])
2219 (define_split
2220 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2221 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2222 (const_int 0)))
2223 (clobber (match_scratch:P 2 ""))]
2224 "reload_completed"
2225 [(set (match_dup 2)
2226 (neg:P (match_dup 1)))
2227 (set (match_dup 0)
2228 (compare:CC (match_dup 2)
2229 (const_int 0)))]
2230 "")
2232 (define_insn ""
2233 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2234 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2235 (const_int 0)))
2236 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2237 (neg:P (match_dup 1)))]
2238 ""
2239 "@
2240 neg. %0,%1
2241 #"
2242 [(set_attr "type" "fast_compare")
2243 (set_attr "length" "4,8")])
2245 (define_split
2246 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2247 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2248 (const_int 0)))
2249 (set (match_operand:P 0 "gpc_reg_operand" "")
2250 (neg:P (match_dup 1)))]
2251 "reload_completed"
2252 [(set (match_dup 0)
2253 (neg:P (match_dup 1)))
2254 (set (match_dup 2)
2255 (compare:CC (match_dup 0)
2256 (const_int 0)))]
2257 "")
2259 (define_insn "clz<mode>2"
2260 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2261 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2262 ""
2263 "{cntlz|cntlz<wd>} %0,%1"
2264 [(set_attr "type" "cntlz")])
2266 (define_expand "ctz<mode>2"
2267 [(set (match_dup 2)
2268 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2269 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2270 (match_dup 2)))
2271 (clobber (scratch:CC))])
2272 (set (match_dup 4) (clz:GPR (match_dup 3)))
2273 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2274 (minus:GPR (match_dup 5) (match_dup 4)))]
2275 ""
2276 {
2277 operands[2] = gen_reg_rtx (<MODE>mode);
2278 operands[3] = gen_reg_rtx (<MODE>mode);
2279 operands[4] = gen_reg_rtx (<MODE>mode);
2280 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2281 })
2283 (define_expand "ffs<mode>2"
2284 [(set (match_dup 2)
2285 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2286 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2287 (match_dup 2)))
2288 (clobber (scratch:CC))])
2289 (set (match_dup 4) (clz:GPR (match_dup 3)))
2290 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2291 (minus:GPR (match_dup 5) (match_dup 4)))]
2292 ""
2293 {
2294 operands[2] = gen_reg_rtx (<MODE>mode);
2295 operands[3] = gen_reg_rtx (<MODE>mode);
2296 operands[4] = gen_reg_rtx (<MODE>mode);
2297 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2298 })
2300 (define_insn "popcntb<mode>2"
2301 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2302 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2303 UNSPEC_POPCNTB))]
2304 "TARGET_POPCNTB"
2305 "popcntb %0,%1")
2307 (define_insn "popcntd<mode>2"
2308 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2309 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2310 "TARGET_POPCNTD"
2311 "popcnt<wd> %0,%1")
2313 (define_expand "popcount<mode>2"
2314 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2315 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2316 "TARGET_POPCNTB || TARGET_POPCNTD"
2317 {
2318 rs6000_emit_popcount (operands[0], operands[1]);
2319 DONE;
2320 })
2322 (define_insn "parity<mode>2_cmpb"
2323 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2324 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2325 "TARGET_CMPB && TARGET_POPCNTB"
2326 "prty<wd> %0,%1")
2328 (define_expand "parity<mode>2"
2329 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2330 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2331 "TARGET_POPCNTB"
2332 {
2333 rs6000_emit_parity (operands[0], operands[1]);
2334 DONE;
2335 })
2337 ;; Since the hardware zeros the upper part of the register, save generating the
2338 ;; AND immediate if we are converting to unsigned
2339 (define_insn "*bswaphi2_extenddi"
2340 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2341 (zero_extend:DI
2342 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2343 "TARGET_POWERPC64"
2344 "lhbrx %0,%y1"
2345 [(set_attr "length" "4")
2346 (set_attr "type" "load")])
2348 (define_insn "*bswaphi2_extendsi"
2349 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2350 (zero_extend:SI
2351 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2352 "TARGET_POWERPC"
2353 "lhbrx %0,%y1"
2354 [(set_attr "length" "4")
2355 (set_attr "type" "load")])
2357 (define_expand "bswaphi2"
2358 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2359 (bswap:HI
2360 (match_operand:HI 1 "reg_or_mem_operand" "")))
2361 (clobber (match_scratch:SI 2 ""))])]
2362 ""
2363 {
2364 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2365 operands[1] = force_reg (HImode, operands[1]);
2366 })
2368 (define_insn "bswaphi2_internal"
2369 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2370 (bswap:HI
2371 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2372 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2373 "TARGET_POWERPC"
2374 "@
2375 lhbrx %0,%y1
2376 sthbrx %1,%y0
2377 #"
2378 [(set_attr "length" "4,4,12")
2379 (set_attr "type" "load,store,*")])
2381 (define_split
2382 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2383 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2384 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2385 "TARGET_POWERPC && reload_completed"
2386 [(set (match_dup 3)
2387 (zero_extract:SI (match_dup 4)
2388 (const_int 8)
2389 (const_int 16)))
2390 (set (match_dup 2)
2391 (and:SI (ashift:SI (match_dup 4)
2392 (const_int 8))
2393 (const_int 65280))) ;; 0xff00
2394 (set (match_dup 3)
2395 (ior:SI (match_dup 3)
2396 (match_dup 2)))]
2397 "
2398 {
2399 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2400 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2401 }")
2403 (define_insn "*bswapsi2_extenddi"
2404 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2405 (zero_extend:DI
2406 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2407 "TARGET_POWERPC64"
2408 "lwbrx %0,%y1"
2409 [(set_attr "length" "4")
2410 (set_attr "type" "load")])
2412 (define_expand "bswapsi2"
2413 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2414 (bswap:SI
2415 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2416 ""
2417 {
2418 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2419 operands[1] = force_reg (SImode, operands[1]);
2420 })
2422 (define_insn "*bswapsi2_internal"
2423 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2424 (bswap:SI
2425 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2426 ""
2427 "@
2428 {lbrx|lwbrx} %0,%y1
2429 {stbrx|stwbrx} %1,%y0
2430 #"
2431 [(set_attr "length" "4,4,12")
2432 (set_attr "type" "load,store,*")])
2434 (define_split
2435 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2436 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2437 "reload_completed"
2438 [(set (match_dup 0)
2439 (rotate:SI (match_dup 1) (const_int 8)))
2440 (set (zero_extract:SI (match_dup 0)
2441 (const_int 8)
2442 (const_int 0))
2443 (match_dup 1))
2444 (set (zero_extract:SI (match_dup 0)
2445 (const_int 8)
2446 (const_int 16))
2447 (rotate:SI (match_dup 1)
2448 (const_int 16)))]
2449 "")
2451 (define_expand "bswapdi2"
2452 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2453 (bswap:DI
2454 (match_operand:DI 1 "reg_or_mem_operand" "")))
2455 (clobber (match_scratch:DI 2 ""))
2456 (clobber (match_scratch:DI 3 ""))
2457 (clobber (match_scratch:DI 4 ""))])]
2458 ""
2459 {
2460 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2461 operands[1] = force_reg (DImode, operands[1]);
2463 if (!TARGET_POWERPC64)
2464 {
2465 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2466 that uses 64-bit registers needs the same scratch registers as 64-bit
2467 mode. */
2468 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2469 DONE;
2470 }
2471 })
2473 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2474 (define_insn "*bswapdi2_ldbrx"
2475 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2476 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2477 (clobber (match_scratch:DI 2 "=X,X,&r"))
2478 (clobber (match_scratch:DI 3 "=X,X,&r"))
2479 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2480 "TARGET_POWERPC64 && TARGET_LDBRX
2481 && (REG_P (operands[0]) || REG_P (operands[1]))"
2482 "@
2483 ldbrx %0,%y1
2484 stdbrx %1,%y0
2485 #"
2486 [(set_attr "length" "4,4,36")
2487 (set_attr "type" "load,store,*")])
2489 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2490 (define_insn "*bswapdi2_64bit"
2491 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2492 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2493 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2494 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2495 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2496 "TARGET_POWERPC64 && !TARGET_LDBRX
2497 && (REG_P (operands[0]) || REG_P (operands[1]))"
2498 "#"
2499 [(set_attr "length" "16,12,36")])
2501 (define_split
2502 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2503 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2504 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2505 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2506 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2507 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2508 [(const_int 0)]
2509 "
2510 {
2511 rtx dest = operands[0];
2512 rtx src = operands[1];
2513 rtx op2 = operands[2];
2514 rtx op3 = operands[3];
2515 rtx op4 = operands[4];
2516 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2517 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2518 rtx addr1;
2519 rtx addr2;
2520 rtx word_high;
2521 rtx word_low;
2523 addr1 = XEXP (src, 0);
2524 if (GET_CODE (addr1) == PLUS)
2525 {
2526 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2527 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2528 }
2529 else
2530 {
2531 emit_move_insn (op2, GEN_INT (4));
2532 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2533 }
2535 if (BYTES_BIG_ENDIAN)
2536 {
2537 word_high = change_address (src, SImode, addr1);
2538 word_low = change_address (src, SImode, addr2);
2539 }
2540 else
2541 {
2542 word_high = change_address (src, SImode, addr2);
2543 word_low = change_address (src, SImode, addr1);
2544 }
2546 emit_insn (gen_bswapsi2 (op3_32, word_low));
2547 emit_insn (gen_bswapsi2 (op4_32, word_high));
2548 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2549 emit_insn (gen_iordi3 (dest, dest, op4));
2550 }")
2552 (define_split
2553 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2554 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2555 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2556 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2557 (clobber (match_operand:DI 4 "" ""))]
2558 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2559 [(const_int 0)]
2560 "
2561 {
2562 rtx dest = operands[0];
2563 rtx src = operands[1];
2564 rtx op2 = operands[2];
2565 rtx op3 = operands[3];
2566 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2567 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2568 rtx addr1;
2569 rtx addr2;
2570 rtx word_high;
2571 rtx word_low;
2573 addr1 = XEXP (dest, 0);
2574 if (GET_CODE (addr1) == PLUS)
2575 {
2576 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2577 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2578 }
2579 else
2580 {
2581 emit_move_insn (op2, GEN_INT (4));
2582 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2583 }
2585 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2586 if (BYTES_BIG_ENDIAN)
2587 {
2588 word_high = change_address (dest, SImode, addr1);
2589 word_low = change_address (dest, SImode, addr2);
2590 emit_insn (gen_bswapsi2 (word_high, src_si));
2591 emit_insn (gen_bswapsi2 (word_low, op3_si));
2592 }
2593 else
2594 {
2595 word_high = change_address (dest, SImode, addr2);
2596 word_low = change_address (dest, SImode, addr1);
2597 emit_insn (gen_bswapsi2 (word_low, src_si));
2598 emit_insn (gen_bswapsi2 (word_high, op3_si));
2599 }
2600 }")
2602 (define_split
2603 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2604 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2605 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2606 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2607 (clobber (match_operand:DI 4 "" ""))]
2608 "TARGET_POWERPC64 && reload_completed"
2609 [(const_int 0)]
2610 "
2611 {
2612 rtx dest = operands[0];
2613 rtx src = operands[1];
2614 rtx op2 = operands[2];
2615 rtx op3 = operands[3];
2616 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2617 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2618 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2619 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2621 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2622 emit_insn (gen_bswapsi2 (dest_si, src_si));
2623 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2624 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2625 emit_insn (gen_iordi3 (dest, dest, op3));
2626 }")
2628 (define_insn "bswapdi2_32bit"
2629 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2630 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2631 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2632 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2633 "#"
2634 [(set_attr "length" "16,12,36")])
2636 (define_split
2637 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2638 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2639 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2640 "!TARGET_POWERPC64 && reload_completed"
2641 [(const_int 0)]
2642 "
2643 {
2644 rtx dest = operands[0];
2645 rtx src = operands[1];
2646 rtx op2 = operands[2];
2647 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2648 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2649 rtx addr1;
2650 rtx addr2;
2651 rtx word_high;
2652 rtx word_low;
2654 addr1 = XEXP (src, 0);
2655 if (GET_CODE (addr1) == PLUS)
2656 {
2657 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2658 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2659 }
2660 else
2661 {
2662 emit_move_insn (op2, GEN_INT (4));
2663 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2664 }
2666 if (BYTES_BIG_ENDIAN)
2667 {
2668 word_high = change_address (src, SImode, addr1);
2669 word_low = change_address (src, SImode, addr2);
2670 }
2671 else
2672 {
2673 word_high = change_address (src, SImode, addr2);
2674 word_low = change_address (src, SImode, addr1);
2675 }
2677 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2678 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2679 }")
2681 (define_split
2682 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2683 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2684 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2685 "!TARGET_POWERPC64 && reload_completed"
2686 [(const_int 0)]
2687 "
2688 {
2689 rtx dest = operands[0];
2690 rtx src = operands[1];
2691 rtx op2 = operands[2];
2692 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2693 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2694 rtx addr1;
2695 rtx addr2;
2696 rtx word_high;
2697 rtx word_low;
2699 addr1 = XEXP (dest, 0);
2700 if (GET_CODE (addr1) == PLUS)
2701 {
2702 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2703 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2704 }
2705 else
2706 {
2707 emit_move_insn (op2, GEN_INT (4));
2708 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2709 }
2711 if (BYTES_BIG_ENDIAN)
2712 {
2713 word_high = change_address (dest, SImode, addr1);
2714 word_low = change_address (dest, SImode, addr2);
2715 }
2716 else
2717 {
2718 word_high = change_address (dest, SImode, addr2);
2719 word_low = change_address (dest, SImode, addr1);
2720 }
2722 emit_insn (gen_bswapsi2 (word_high, src_low));
2723 emit_insn (gen_bswapsi2 (word_low, src_high));
2724 }")
2726 (define_split
2727 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2728 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2729 (clobber (match_operand:SI 2 "" ""))]
2730 "!TARGET_POWERPC64 && reload_completed"
2731 [(const_int 0)]
2732 "
2733 {
2734 rtx dest = operands[0];
2735 rtx src = operands[1];
2736 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2737 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2738 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2739 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2741 emit_insn (gen_bswapsi2 (dest_high, src_low));
2742 emit_insn (gen_bswapsi2 (dest_low, src_high));
2743 }")
2745 (define_expand "mulsi3"
2746 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2747 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2748 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2749 ""
2750 "
2751 {
2752 if (TARGET_POWER)
2753 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2754 else
2755 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2756 DONE;
2757 }")
2759 (define_insn "mulsi3_mq"
2760 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2761 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2762 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2763 (clobber (match_scratch:SI 3 "=q,q"))]
2764 "TARGET_POWER"
2765 "@
2766 {muls|mullw} %0,%1,%2
2767 {muli|mulli} %0,%1,%2"
2768 [(set (attr "type")
2769 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2770 (const_string "imul3")
2771 (match_operand:SI 2 "short_cint_operand" "")
2772 (const_string "imul2")]
2773 (const_string "imul")))])
2775 (define_insn "mulsi3_no_mq"
2776 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2777 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2778 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2779 "! TARGET_POWER"
2780 "@
2781 {muls|mullw} %0,%1,%2
2782 {muli|mulli} %0,%1,%2"
2783 [(set (attr "type")
2784 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2785 (const_string "imul3")
2786 (match_operand:SI 2 "short_cint_operand" "")
2787 (const_string "imul2")]
2788 (const_string "imul")))])
2790 (define_insn "*mulsi3_mq_internal1"
2791 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2792 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2793 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2794 (const_int 0)))
2795 (clobber (match_scratch:SI 3 "=r,r"))
2796 (clobber (match_scratch:SI 4 "=q,q"))]
2797 "TARGET_POWER"
2798 "@
2799 {muls.|mullw.} %3,%1,%2
2800 #"
2801 [(set_attr "type" "imul_compare")
2802 (set_attr "length" "4,8")])
2804 (define_split
2805 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2806 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2807 (match_operand:SI 2 "gpc_reg_operand" ""))
2808 (const_int 0)))
2809 (clobber (match_scratch:SI 3 ""))
2810 (clobber (match_scratch:SI 4 ""))]
2811 "TARGET_POWER && reload_completed"
2812 [(parallel [(set (match_dup 3)
2813 (mult:SI (match_dup 1) (match_dup 2)))
2814 (clobber (match_dup 4))])
2815 (set (match_dup 0)
2816 (compare:CC (match_dup 3)
2817 (const_int 0)))]
2818 "")
2820 (define_insn "*mulsi3_no_mq_internal1"
2821 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2822 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2823 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2824 (const_int 0)))
2825 (clobber (match_scratch:SI 3 "=r,r"))]
2826 "! TARGET_POWER"
2827 "@
2828 {muls.|mullw.} %3,%1,%2
2829 #"
2830 [(set_attr "type" "imul_compare")
2831 (set_attr "length" "4,8")])
2833 (define_split
2834 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2835 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2836 (match_operand:SI 2 "gpc_reg_operand" ""))
2837 (const_int 0)))
2838 (clobber (match_scratch:SI 3 ""))]
2839 "! TARGET_POWER && reload_completed"
2840 [(set (match_dup 3)
2841 (mult:SI (match_dup 1) (match_dup 2)))
2842 (set (match_dup 0)
2843 (compare:CC (match_dup 3)
2844 (const_int 0)))]
2845 "")
2847 (define_insn "*mulsi3_mq_internal2"
2848 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2849 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2850 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2851 (const_int 0)))
2852 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2853 (mult:SI (match_dup 1) (match_dup 2)))
2854 (clobber (match_scratch:SI 4 "=q,q"))]
2855 "TARGET_POWER"
2856 "@
2857 {muls.|mullw.} %0,%1,%2
2858 #"
2859 [(set_attr "type" "imul_compare")
2860 (set_attr "length" "4,8")])
2862 (define_split
2863 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2864 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2865 (match_operand:SI 2 "gpc_reg_operand" ""))
2866 (const_int 0)))
2867 (set (match_operand:SI 0 "gpc_reg_operand" "")
2868 (mult:SI (match_dup 1) (match_dup 2)))
2869 (clobber (match_scratch:SI 4 ""))]
2870 "TARGET_POWER && reload_completed"
2871 [(parallel [(set (match_dup 0)
2872 (mult:SI (match_dup 1) (match_dup 2)))
2873 (clobber (match_dup 4))])
2874 (set (match_dup 3)
2875 (compare:CC (match_dup 0)
2876 (const_int 0)))]
2877 "")
2879 (define_insn "*mulsi3_no_mq_internal2"
2880 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2881 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2882 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2883 (const_int 0)))
2884 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2885 (mult:SI (match_dup 1) (match_dup 2)))]
2886 "! TARGET_POWER"
2887 "@
2888 {muls.|mullw.} %0,%1,%2
2889 #"
2890 [(set_attr "type" "imul_compare")
2891 (set_attr "length" "4,8")])
2893 (define_split
2894 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2895 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2896 (match_operand:SI 2 "gpc_reg_operand" ""))
2897 (const_int 0)))
2898 (set (match_operand:SI 0 "gpc_reg_operand" "")
2899 (mult:SI (match_dup 1) (match_dup 2)))]
2900 "! TARGET_POWER && reload_completed"
2901 [(set (match_dup 0)
2902 (mult:SI (match_dup 1) (match_dup 2)))
2903 (set (match_dup 3)
2904 (compare:CC (match_dup 0)
2905 (const_int 0)))]
2906 "")
2908 ;; Operand 1 is divided by operand 2; quotient goes to operand
2909 ;; 0 and remainder to operand 3.
2910 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2912 (define_expand "divmodsi4"
2913 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2914 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2915 (match_operand:SI 2 "gpc_reg_operand" "")))
2916 (set (match_operand:SI 3 "register_operand" "")
2917 (mod:SI (match_dup 1) (match_dup 2)))])]
2918 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2919 "
2920 {
2921 if (! TARGET_POWER && ! TARGET_POWERPC)
2922 {
2923 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2924 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2925 emit_insn (gen_divss_call ());
2926 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2927 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2928 DONE;
2929 }
2930 }")
2932 (define_insn "*divmodsi4_internal"
2933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2934 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2935 (match_operand:SI 2 "gpc_reg_operand" "r")))
2936 (set (match_operand:SI 3 "register_operand" "=q")
2937 (mod:SI (match_dup 1) (match_dup 2)))]
2938 "TARGET_POWER"
2939 "divs %0,%1,%2"
2940 [(set_attr "type" "idiv")])
2942 (define_expand "udiv<mode>3"
2943 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2944 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2945 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2946 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2947 "
2948 {
2949 if (! TARGET_POWER && ! TARGET_POWERPC)
2950 {
2951 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2952 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2953 emit_insn (gen_quous_call ());
2954 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2955 DONE;
2956 }
2957 else if (TARGET_POWER)
2958 {
2959 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2960 DONE;
2961 }
2962 }")
2964 (define_insn "udivsi3_mq"
2965 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2966 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2967 (match_operand:SI 2 "gpc_reg_operand" "r")))
2968 (clobber (match_scratch:SI 3 "=q"))]
2969 "TARGET_POWERPC && TARGET_POWER"
2970 "divwu %0,%1,%2"
2971 [(set_attr "type" "idiv")])
2973 (define_insn "*udivsi3_no_mq"
2974 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2975 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2976 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2977 "TARGET_POWERPC && ! TARGET_POWER"
2978 "div<wd>u %0,%1,%2"
2979 [(set (attr "type")
2980 (cond [(match_operand:SI 0 "" "")
2981 (const_string "idiv")]
2982 (const_string "ldiv")))])
2985 ;; For powers of two we can do srai/aze for divide and then adjust for
2986 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2987 ;; used; for PowerPC, force operands into register and do a normal divide;
2988 ;; for AIX common-mode, use quoss call on register operands.
2989 (define_expand "div<mode>3"
2990 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2991 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2992 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2993 ""
2994 "
2995 {
2996 if (GET_CODE (operands[2]) == CONST_INT
2997 && INTVAL (operands[2]) > 0
2998 && exact_log2 (INTVAL (operands[2])) >= 0)
2999 ;
3000 else if (TARGET_POWERPC)
3001 {
3002 operands[2] = force_reg (<MODE>mode, operands[2]);
3003 if (TARGET_POWER)
3004 {
3005 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
3006 DONE;
3007 }
3008 }
3009 else if (TARGET_POWER)
3010 FAIL;
3011 else
3012 {
3013 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3014 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3015 emit_insn (gen_quoss_call ());
3016 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3017 DONE;
3018 }
3019 }")
3021 (define_insn "divsi3_mq"
3022 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3023 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3024 (match_operand:SI 2 "gpc_reg_operand" "r")))
3025 (clobber (match_scratch:SI 3 "=q"))]
3026 "TARGET_POWERPC && TARGET_POWER"
3027 "divw %0,%1,%2"
3028 [(set_attr "type" "idiv")])
3030 (define_insn "*div<mode>3_no_mq"
3031 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3032 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3033 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
3034 "TARGET_POWERPC && ! TARGET_POWER"
3035 "div<wd> %0,%1,%2"
3036 [(set (attr "type")
3037 (cond [(match_operand:SI 0 "" "")
3038 (const_string "idiv")]
3039 (const_string "ldiv")))])
3041 (define_expand "mod<mode>3"
3042 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
3043 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
3044 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
3045 ""
3046 "
3047 {
3048 int i;
3049 rtx temp1;
3050 rtx temp2;
3052 if (GET_CODE (operands[2]) != CONST_INT
3053 || INTVAL (operands[2]) <= 0
3054 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
3055 FAIL;
3057 temp1 = gen_reg_rtx (<MODE>mode);
3058 temp2 = gen_reg_rtx (<MODE>mode);
3060 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
3061 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
3062 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
3063 DONE;
3064 }")
3066 (define_insn ""
3067 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3068 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3069 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
3070 ""
3071 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
3072 [(set_attr "type" "two")
3073 (set_attr "length" "8")])
3075 (define_insn ""
3076 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3077 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3078 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3079 (const_int 0)))
3080 (clobber (match_scratch:P 3 "=r,r"))]
3081 ""
3082 "@
3083 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
3084 #"
3085 [(set_attr "type" "compare")
3086 (set_attr "length" "8,12")
3087 (set_attr "cell_micro" "not")])
3089 (define_split
3090 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3091 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3092 (match_operand:GPR 2 "exact_log2_cint_operand"
3093 ""))
3094 (const_int 0)))
3095 (clobber (match_scratch:GPR 3 ""))]
3096 "reload_completed"
3097 [(set (match_dup 3)
3098 (div:<MODE> (match_dup 1) (match_dup 2)))
3099 (set (match_dup 0)
3100 (compare:CC (match_dup 3)
3101 (const_int 0)))]
3102 "")
3104 (define_insn ""
3105 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3106 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3107 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3108 (const_int 0)))
3109 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
3110 (div:P (match_dup 1) (match_dup 2)))]
3111 ""
3112 "@
3113 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
3114 #"
3115 [(set_attr "type" "compare")
3116 (set_attr "length" "8,12")
3117 (set_attr "cell_micro" "not")])
3119 (define_split
3120 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3121 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3122 (match_operand:GPR 2 "exact_log2_cint_operand"
3123 ""))
3124 (const_int 0)))
3125 (set (match_operand:GPR 0 "gpc_reg_operand" "")
3126 (div:GPR (match_dup 1) (match_dup 2)))]
3127 "reload_completed"
3128 [(set (match_dup 0)
3129 (div:<MODE> (match_dup 1) (match_dup 2)))
3130 (set (match_dup 3)
3131 (compare:CC (match_dup 0)
3132 (const_int 0)))]
3133 "")
3135 (define_insn ""
3136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3137 (udiv:SI
3138 (plus:DI (ashift:DI
3139 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3140 (const_int 32))
3141 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
3142 (match_operand:SI 3 "gpc_reg_operand" "r")))
3143 (set (match_operand:SI 2 "register_operand" "=*q")
3144 (umod:SI
3145 (plus:DI (ashift:DI
3146 (zero_extend:DI (match_dup 1)) (const_int 32))
3147 (zero_extend:DI (match_dup 4)))
3148 (match_dup 3)))]
3149 "TARGET_POWER"
3150 "div %0,%1,%3"
3151 [(set_attr "type" "idiv")])
3153 ;; To do unsigned divide we handle the cases of the divisor looking like a
3154 ;; negative number. If it is a constant that is less than 2**31, we don't
3155 ;; have to worry about the branches. So make a few subroutines here.
3156 ;;
3157 ;; First comes the normal case.
3158 (define_expand "udivmodsi4_normal"
3159 [(set (match_dup 4) (const_int 0))
3160 (parallel [(set (match_operand:SI 0 "" "")
3161 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3162 (const_int 32))
3163 (zero_extend:DI (match_operand:SI 1 "" "")))
3164 (match_operand:SI 2 "" "")))
3165 (set (match_operand:SI 3 "" "")
3166 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3167 (const_int 32))
3168 (zero_extend:DI (match_dup 1)))
3169 (match_dup 2)))])]
3170 "TARGET_POWER"
3171 "
3172 { operands[4] = gen_reg_rtx (SImode); }")
3174 ;; This handles the branches.
3175 (define_expand "udivmodsi4_tests"
3176 [(set (match_operand:SI 0 "" "") (const_int 0))
3177 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
3178 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
3179 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
3180 (label_ref (match_operand:SI 4 "" "")) (pc)))
3181 (set (match_dup 0) (const_int 1))
3182 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
3183 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
3184 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
3185 (label_ref (match_dup 4)) (pc)))]
3186 "TARGET_POWER"
3187 "
3188 { operands[5] = gen_reg_rtx (CCUNSmode);
3189 operands[6] = gen_reg_rtx (CCmode);
3190 }")
3192 (define_expand "udivmodsi4"
3193 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3194 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
3195 (match_operand:SI 2 "reg_or_cint_operand" "")))
3196 (set (match_operand:SI 3 "gpc_reg_operand" "")
3197 (umod:SI (match_dup 1) (match_dup 2)))])]
3198 ""
3199 "
3200 {
3201 rtx label = 0;
3203 if (! TARGET_POWER)
3204 {
3205 if (! TARGET_POWERPC)
3206 {
3207 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3208 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3209 emit_insn (gen_divus_call ());
3210 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3211 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3212 DONE;
3213 }
3214 else
3215 FAIL;
3216 }
3218 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
3219 {
3220 operands[2] = force_reg (SImode, operands[2]);
3221 label = gen_label_rtx ();
3222 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
3223 operands[3], label));
3224 }
3225 else
3226 operands[2] = force_reg (SImode, operands[2]);
3228 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
3229 operands[3]));
3230 if (label)
3231 emit_label (label);
3233 DONE;
3234 }")
3236 ;; AIX architecture-independent common-mode multiply (DImode),
3237 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
3238 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
3239 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
3240 ;; assumed unused if generating common-mode, so ignore.
3241 (define_insn "mulh_call"
3242 [(set (reg:SI 3)
3243 (truncate:SI
3244 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
3245 (sign_extend:DI (reg:SI 4)))
3246 (const_int 32))))
3247 (clobber (reg:SI LR_REGNO))]
3248 "! TARGET_POWER && ! TARGET_POWERPC"
3249 "bla __mulh"
3250 [(set_attr "type" "imul")])
3252 (define_insn "mull_call"
3253 [(set (reg:DI 3)
3254 (mult:DI (sign_extend:DI (reg:SI 3))
3255 (sign_extend:DI (reg:SI 4))))
3256 (clobber (reg:SI LR_REGNO))
3257 (clobber (reg:SI 0))]
3258 "! TARGET_POWER && ! TARGET_POWERPC"
3259 "bla __mull"
3260 [(set_attr "type" "imul")])
3262 (define_insn "divss_call"
3263 [(set (reg:SI 3)
3264 (div:SI (reg:SI 3) (reg:SI 4)))
3265 (set (reg:SI 4)
3266 (mod:SI (reg:SI 3) (reg:SI 4)))
3267 (clobber (reg:SI LR_REGNO))
3268 (clobber (reg:SI 0))]
3269 "! TARGET_POWER && ! TARGET_POWERPC"
3270 "bla __divss"
3271 [(set_attr "type" "idiv")])
3273 (define_insn "divus_call"
3274 [(set (reg:SI 3)
3275 (udiv:SI (reg:SI 3) (reg:SI 4)))
3276 (set (reg:SI 4)
3277 (umod:SI (reg:SI 3) (reg:SI 4)))
3278 (clobber (reg:SI LR_REGNO))
3279 (clobber (reg:SI 0))
3280 (clobber (match_scratch:CC 0 "=x"))
3281 (clobber (reg:CC CR1_REGNO))]
3282 "! TARGET_POWER && ! TARGET_POWERPC"
3283 "bla __divus"
3284 [(set_attr "type" "idiv")])
3286 (define_insn "quoss_call"
3287 [(set (reg:SI 3)
3288 (div:SI (reg:SI 3) (reg:SI 4)))
3289 (clobber (reg:SI LR_REGNO))]
3290 "! TARGET_POWER && ! TARGET_POWERPC"
3291 "bla __quoss"
3292 [(set_attr "type" "idiv")])
3294 (define_insn "quous_call"
3295 [(set (reg:SI 3)
3296 (udiv:SI (reg:SI 3) (reg:SI 4)))
3297 (clobber (reg:SI LR_REGNO))
3298 (clobber (reg:SI 0))
3299 (clobber (match_scratch:CC 0 "=x"))
3300 (clobber (reg:CC CR1_REGNO))]
3301 "! TARGET_POWER && ! TARGET_POWERPC"
3302 "bla __quous"
3303 [(set_attr "type" "idiv")])
3304 \f
3305 ;; Logical instructions
3306 ;; The logical instructions are mostly combined by using match_operator,
3307 ;; but the plain AND insns are somewhat different because there is no
3308 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3309 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3311 (define_expand "andsi3"
3312 [(parallel
3313 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3314 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3315 (match_operand:SI 2 "and_operand" "")))
3316 (clobber (match_scratch:CC 3 ""))])]
3317 ""
3318 "")
3320 (define_insn "andsi3_mc"
3321 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3322 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3323 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3324 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3325 "rs6000_gen_cell_microcode"
3326 "@
3327 and %0,%1,%2
3328 {rlinm|rlwinm} %0,%1,0,%m2,%M2
3329 {andil.|andi.} %0,%1,%b2
3330 {andiu.|andis.} %0,%1,%u2"
3331 [(set_attr "type" "*,*,fast_compare,fast_compare")])
3333 (define_insn "andsi3_nomc"
3334 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3335 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3336 (match_operand:SI 2 "and_operand" "?r,T")))
3337 (clobber (match_scratch:CC 3 "=X,X"))]
3338 "!rs6000_gen_cell_microcode"
3339 "@
3340 and %0,%1,%2
3341 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3343 (define_insn "andsi3_internal0_nomc"
3344 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3345 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3346 (match_operand:SI 2 "and_operand" "?r,T")))]
3347 "!rs6000_gen_cell_microcode"
3348 "@
3349 and %0,%1,%2
3350 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3353 ;; Note to set cr's other than cr0 we do the and immediate and then
3354 ;; the test again -- this avoids a mfcr which on the higher end
3355 ;; machines causes an execution serialization
3357 (define_insn "*andsi3_internal2_mc"
3358 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3359 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3360 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3361 (const_int 0)))
3362 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3363 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3364 "TARGET_32BIT && rs6000_gen_cell_microcode"
3365 "@
3366 and. %3,%1,%2
3367 {andil.|andi.} %3,%1,%b2
3368 {andiu.|andis.} %3,%1,%u2
3369 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3370 #
3371 #
3372 #
3373 #"
3374 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3375 compare,compare,compare,compare")
3376 (set_attr "length" "4,4,4,4,8,8,8,8")])
3378 (define_insn "*andsi3_internal3_mc"
3379 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3380 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3381 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3382 (const_int 0)))
3383 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3384 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3385 "TARGET_64BIT && rs6000_gen_cell_microcode"
3386 "@
3387 #
3388 {andil.|andi.} %3,%1,%b2
3389 {andiu.|andis.} %3,%1,%u2
3390 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3391 #
3392 #
3393 #
3394 #"
3395 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3396 compare,compare,compare")
3397 (set_attr "length" "8,4,4,4,8,8,8,8")])
3399 (define_split
3400 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3401 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3402 (match_operand:GPR 2 "and_operand" ""))
3403 (const_int 0)))
3404 (clobber (match_scratch:GPR 3 ""))
3405 (clobber (match_scratch:CC 4 ""))]
3406 "reload_completed"
3407 [(parallel [(set (match_dup 3)
3408 (and:<MODE> (match_dup 1)
3409 (match_dup 2)))
3410 (clobber (match_dup 4))])
3411 (set (match_dup 0)
3412 (compare:CC (match_dup 3)
3413 (const_int 0)))]
3414 "")
3416 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3417 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3419 (define_split
3420 [(set (match_operand:CC 0 "cc_reg_operand" "")
3421 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3422 (match_operand:SI 2 "gpc_reg_operand" ""))
3423 (const_int 0)))
3424 (clobber (match_scratch:SI 3 ""))
3425 (clobber (match_scratch:CC 4 ""))]
3426 "TARGET_POWERPC64 && reload_completed"
3427 [(parallel [(set (match_dup 3)
3428 (and:SI (match_dup 1)
3429 (match_dup 2)))
3430 (clobber (match_dup 4))])
3431 (set (match_dup 0)
3432 (compare:CC (match_dup 3)
3433 (const_int 0)))]
3434 "")
3436 (define_insn "*andsi3_internal4"
3437 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3438 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3439 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3440 (const_int 0)))
3441 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3442 (and:SI (match_dup 1)
3443 (match_dup 2)))
3444 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3445 "TARGET_32BIT && rs6000_gen_cell_microcode"
3446 "@
3447 and. %0,%1,%2
3448 {andil.|andi.} %0,%1,%b2
3449 {andiu.|andis.} %0,%1,%u2
3450 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3451 #
3452 #
3453 #
3454 #"
3455 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3456 compare,compare,compare,compare")
3457 (set_attr "length" "4,4,4,4,8,8,8,8")])
3459 (define_insn "*andsi3_internal5_mc"
3460 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3461 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3462 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3463 (const_int 0)))
3464 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3465 (and:SI (match_dup 1)
3466 (match_dup 2)))
3467 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3468 "TARGET_64BIT && rs6000_gen_cell_microcode"
3469 "@
3470 #
3471 {andil.|andi.} %0,%1,%b2
3472 {andiu.|andis.} %0,%1,%u2
3473 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3474 #
3475 #
3476 #
3477 #"
3478 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3479 compare,compare,compare")
3480 (set_attr "length" "8,4,4,4,8,8,8,8")])
3482 (define_split
3483 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3484 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3485 (match_operand:SI 2 "and_operand" ""))
3486 (const_int 0)))
3487 (set (match_operand:SI 0 "gpc_reg_operand" "")
3488 (and:SI (match_dup 1)
3489 (match_dup 2)))
3490 (clobber (match_scratch:CC 4 ""))]
3491 "reload_completed"
3492 [(parallel [(set (match_dup 0)
3493 (and:SI (match_dup 1)
3494 (match_dup 2)))
3495 (clobber (match_dup 4))])
3496 (set (match_dup 3)
3497 (compare:CC (match_dup 0)
3498 (const_int 0)))]
3499 "")
3501 (define_split
3502 [(set (match_operand:CC 3 "cc_reg_operand" "")
3503 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3504 (match_operand:SI 2 "gpc_reg_operand" ""))
3505 (const_int 0)))
3506 (set (match_operand:SI 0 "gpc_reg_operand" "")
3507 (and:SI (match_dup 1)
3508 (match_dup 2)))
3509 (clobber (match_scratch:CC 4 ""))]
3510 "TARGET_POWERPC64 && reload_completed"
3511 [(parallel [(set (match_dup 0)
3512 (and:SI (match_dup 1)
3513 (match_dup 2)))
3514 (clobber (match_dup 4))])
3515 (set (match_dup 3)
3516 (compare:CC (match_dup 0)
3517 (const_int 0)))]
3518 "")
3520 ;; Handle the PowerPC64 rlwinm corner case
3522 (define_insn_and_split "*andsi3_internal6"
3523 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3524 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3525 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3526 "TARGET_POWERPC64"
3527 "#"
3528 "TARGET_POWERPC64"
3529 [(set (match_dup 0)
3530 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3531 (match_dup 4)))
3532 (set (match_dup 0)
3533 (rotate:SI (match_dup 0) (match_dup 5)))]
3534 "
3535 {
3536 int mb = extract_MB (operands[2]);
3537 int me = extract_ME (operands[2]);
3538 operands[3] = GEN_INT (me + 1);
3539 operands[5] = GEN_INT (32 - (me + 1));
3540 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3541 }"
3542 [(set_attr "length" "8")])
3544 (define_expand "iorsi3"
3545 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3546 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3547 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3548 ""
3549 "
3550 {
3551 if (GET_CODE (operands[2]) == CONST_INT
3552 && ! logical_operand (operands[2], SImode))
3553 {
3554 HOST_WIDE_INT value = INTVAL (operands[2]);
3555 rtx tmp = ((!can_create_pseudo_p ()
3556 || rtx_equal_p (operands[0], operands[1]))
3557 ? operands[0] : gen_reg_rtx (SImode));
3559 emit_insn (gen_iorsi3 (tmp, operands[1],
3560 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3561 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3562 DONE;
3563 }
3564 }")
3566 (define_expand "xorsi3"
3567 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3568 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3569 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3570 ""
3571 "
3572 {
3573 if (GET_CODE (operands[2]) == CONST_INT
3574 && ! logical_operand (operands[2], SImode))
3575 {
3576 HOST_WIDE_INT value = INTVAL (operands[2]);
3577 rtx tmp = ((!can_create_pseudo_p ()
3578 || rtx_equal_p (operands[0], operands[1]))
3579 ? operands[0] : gen_reg_rtx (SImode));
3581 emit_insn (gen_xorsi3 (tmp, operands[1],
3582 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3583 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3584 DONE;
3585 }
3586 }")
3588 (define_insn "*boolsi3_internal1"
3589 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3590 (match_operator:SI 3 "boolean_or_operator"
3591 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3592 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3593 ""
3594 "@
3595 %q3 %0,%1,%2
3596 {%q3il|%q3i} %0,%1,%b2
3597 {%q3iu|%q3is} %0,%1,%u2")
3599 (define_insn "*boolsi3_internal2"
3600 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3601 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3602 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3603 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3604 (const_int 0)))
3605 (clobber (match_scratch:SI 3 "=r,r"))]
3606 "TARGET_32BIT"
3607 "@
3608 %q4. %3,%1,%2
3609 #"
3610 [(set_attr "type" "fast_compare,compare")
3611 (set_attr "length" "4,8")])
3613 (define_split
3614 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3615 (compare:CC (match_operator:SI 4 "boolean_operator"
3616 [(match_operand:SI 1 "gpc_reg_operand" "")
3617 (match_operand:SI 2 "gpc_reg_operand" "")])
3618 (const_int 0)))
3619 (clobber (match_scratch:SI 3 ""))]
3620 "TARGET_32BIT && reload_completed"
3621 [(set (match_dup 3) (match_dup 4))
3622 (set (match_dup 0)
3623 (compare:CC (match_dup 3)
3624 (const_int 0)))]
3625 "")
3627 (define_insn "*boolsi3_internal3"
3628 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3629 (compare:CC (match_operator:SI 4 "boolean_operator"
3630 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3631 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3632 (const_int 0)))
3633 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3634 (match_dup 4))]
3635 "TARGET_32BIT"
3636 "@
3637 %q4. %0,%1,%2
3638 #"
3639 [(set_attr "type" "fast_compare,compare")
3640 (set_attr "length" "4,8")])
3642 (define_split
3643 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3644 (compare:CC (match_operator:SI 4 "boolean_operator"
3645 [(match_operand:SI 1 "gpc_reg_operand" "")
3646 (match_operand:SI 2 "gpc_reg_operand" "")])
3647 (const_int 0)))
3648 (set (match_operand:SI 0 "gpc_reg_operand" "")
3649 (match_dup 4))]
3650 "TARGET_32BIT && reload_completed"
3651 [(set (match_dup 0) (match_dup 4))
3652 (set (match_dup 3)
3653 (compare:CC (match_dup 0)
3654 (const_int 0)))]
3655 "")
3657 ;; Split a logical operation that we can't do in one insn into two insns,
3658 ;; each of which does one 16-bit part. This is used by combine.
3660 (define_split
3661 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3662 (match_operator:SI 3 "boolean_or_operator"
3663 [(match_operand:SI 1 "gpc_reg_operand" "")
3664 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3665 ""
3666 [(set (match_dup 0) (match_dup 4))
3667 (set (match_dup 0) (match_dup 5))]
3668 "
3669 {
3670 rtx i;
3671 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3672 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3673 operands[1], i);
3674 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3675 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3676 operands[0], i);
3677 }")
3679 (define_insn "*boolcsi3_internal1"
3680 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3681 (match_operator:SI 3 "boolean_operator"
3682 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3683 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3684 ""
3685 "%q3 %0,%2,%1")
3687 (define_insn "*boolcsi3_internal2"
3688 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3689 (compare:CC (match_operator:SI 4 "boolean_operator"
3690 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3691 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3692 (const_int 0)))
3693 (clobber (match_scratch:SI 3 "=r,r"))]
3694 "TARGET_32BIT"
3695 "@
3696 %q4. %3,%2,%1
3697 #"
3698 [(set_attr "type" "compare")
3699 (set_attr "length" "4,8")])
3701 (define_split
3702 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3703 (compare:CC (match_operator:SI 4 "boolean_operator"
3704 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3705 (match_operand:SI 2 "gpc_reg_operand" "")])
3706 (const_int 0)))
3707 (clobber (match_scratch:SI 3 ""))]
3708 "TARGET_32BIT && reload_completed"
3709 [(set (match_dup 3) (match_dup 4))
3710 (set (match_dup 0)
3711 (compare:CC (match_dup 3)
3712 (const_int 0)))]
3713 "")
3715 (define_insn "*boolcsi3_internal3"
3716 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3717 (compare:CC (match_operator:SI 4 "boolean_operator"
3718 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3719 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3720 (const_int 0)))
3721 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3722 (match_dup 4))]
3723 "TARGET_32BIT"
3724 "@
3725 %q4. %0,%2,%1
3726 #"
3727 [(set_attr "type" "compare")
3728 (set_attr "length" "4,8")])
3730 (define_split
3731 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3732 (compare:CC (match_operator:SI 4 "boolean_operator"
3733 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3734 (match_operand:SI 2 "gpc_reg_operand" "")])
3735 (const_int 0)))
3736 (set (match_operand:SI 0 "gpc_reg_operand" "")
3737 (match_dup 4))]
3738 "TARGET_32BIT && reload_completed"
3739 [(set (match_dup 0) (match_dup 4))
3740 (set (match_dup 3)
3741 (compare:CC (match_dup 0)
3742 (const_int 0)))]
3743 "")
3745 (define_insn "*boolccsi3_internal1"
3746 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3747 (match_operator:SI 3 "boolean_operator"
3748 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3749 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3750 ""
3751 "%q3 %0,%1,%2")
3753 (define_insn "*boolccsi3_internal2"
3754 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3755 (compare:CC (match_operator:SI 4 "boolean_operator"
3756 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3757 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3758 (const_int 0)))
3759 (clobber (match_scratch:SI 3 "=r,r"))]
3760 "TARGET_32BIT"
3761 "@
3762 %q4. %3,%1,%2
3763 #"
3764 [(set_attr "type" "fast_compare,compare")
3765 (set_attr "length" "4,8")])
3767 (define_split
3768 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3769 (compare:CC (match_operator:SI 4 "boolean_operator"
3770 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3771 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3772 (const_int 0)))
3773 (clobber (match_scratch:SI 3 ""))]
3774 "TARGET_32BIT && reload_completed"
3775 [(set (match_dup 3) (match_dup 4))
3776 (set (match_dup 0)
3777 (compare:CC (match_dup 3)
3778 (const_int 0)))]
3779 "")
3781 (define_insn "*boolccsi3_internal3"
3782 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3783 (compare:CC (match_operator:SI 4 "boolean_operator"
3784 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3785 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3786 (const_int 0)))
3787 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3788 (match_dup 4))]
3789 "TARGET_32BIT"
3790 "@
3791 %q4. %0,%1,%2
3792 #"
3793 [(set_attr "type" "fast_compare,compare")
3794 (set_attr "length" "4,8")])
3796 (define_split
3797 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3798 (compare:CC (match_operator:SI 4 "boolean_operator"
3799 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3800 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3801 (const_int 0)))
3802 (set (match_operand:SI 0 "gpc_reg_operand" "")
3803 (match_dup 4))]
3804 "TARGET_32BIT && reload_completed"
3805 [(set (match_dup 0) (match_dup 4))
3806 (set (match_dup 3)
3807 (compare:CC (match_dup 0)
3808 (const_int 0)))]
3809 "")
3811 ;; maskir insn. We need four forms because things might be in arbitrary
3812 ;; orders. Don't define forms that only set CR fields because these
3813 ;; would modify an input register.
3815 (define_insn "*maskir_internal1"
3816 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3817 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3818 (match_operand:SI 1 "gpc_reg_operand" "0"))
3819 (and:SI (match_dup 2)
3820 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3821 "TARGET_POWER"
3822 "maskir %0,%3,%2")
3824 (define_insn "*maskir_internal2"
3825 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3826 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3827 (match_operand:SI 1 "gpc_reg_operand" "0"))
3828 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3829 (match_dup 2))))]
3830 "TARGET_POWER"
3831 "maskir %0,%3,%2")
3833 (define_insn "*maskir_internal3"
3834 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3835 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3836 (match_operand:SI 3 "gpc_reg_operand" "r"))
3837 (and:SI (not:SI (match_dup 2))
3838 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3839 "TARGET_POWER"
3840 "maskir %0,%3,%2")
3842 (define_insn "*maskir_internal4"
3843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3844 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3845 (match_operand:SI 2 "gpc_reg_operand" "r"))
3846 (and:SI (not:SI (match_dup 2))
3847 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3848 "TARGET_POWER"
3849 "maskir %0,%3,%2")
3851 (define_insn "*maskir_internal5"
3852 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3853 (compare:CC
3854 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3855 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3856 (and:SI (match_dup 2)
3857 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3858 (const_int 0)))
3859 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3860 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3861 (and:SI (match_dup 2) (match_dup 3))))]
3862 "TARGET_POWER"
3863 "@
3864 maskir. %0,%3,%2
3865 #"
3866 [(set_attr "type" "compare")
3867 (set_attr "length" "4,8")])
3869 (define_split
3870 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3871 (compare:CC
3872 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3873 (match_operand:SI 1 "gpc_reg_operand" ""))
3874 (and:SI (match_dup 2)
3875 (match_operand:SI 3 "gpc_reg_operand" "")))
3876 (const_int 0)))
3877 (set (match_operand:SI 0 "gpc_reg_operand" "")
3878 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3879 (and:SI (match_dup 2) (match_dup 3))))]
3880 "TARGET_POWER && reload_completed"
3881 [(set (match_dup 0)
3882 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3883 (and:SI (match_dup 2) (match_dup 3))))
3884 (set (match_dup 4)
3885 (compare:CC (match_dup 0)
3886 (const_int 0)))]
3887 "")
3889 (define_insn "*maskir_internal6"
3890 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3891 (compare:CC
3892 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3893 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3894 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3895 (match_dup 2)))
3896 (const_int 0)))
3897 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3898 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3899 (and:SI (match_dup 3) (match_dup 2))))]
3900 "TARGET_POWER"
3901 "@
3902 maskir. %0,%3,%2
3903 #"
3904 [(set_attr "type" "compare")
3905 (set_attr "length" "4,8")])
3907 (define_split
3908 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3909 (compare:CC
3910 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3911 (match_operand:SI 1 "gpc_reg_operand" ""))
3912 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3913 (match_dup 2)))
3914 (const_int 0)))
3915 (set (match_operand:SI 0 "gpc_reg_operand" "")
3916 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3917 (and:SI (match_dup 3) (match_dup 2))))]
3918 "TARGET_POWER && reload_completed"
3919 [(set (match_dup 0)
3920 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3921 (and:SI (match_dup 3) (match_dup 2))))
3922 (set (match_dup 4)
3923 (compare:CC (match_dup 0)
3924 (const_int 0)))]
3925 "")
3927 (define_insn "*maskir_internal7"
3928 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3929 (compare:CC
3930 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3931 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3932 (and:SI (not:SI (match_dup 2))
3933 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3934 (const_int 0)))
3935 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3936 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3937 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3938 "TARGET_POWER"
3939 "@
3940 maskir. %0,%3,%2
3941 #"
3942 [(set_attr "type" "compare")
3943 (set_attr "length" "4,8")])
3945 (define_split
3946 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3947 (compare:CC
3948 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3949 (match_operand:SI 3 "gpc_reg_operand" ""))
3950 (and:SI (not:SI (match_dup 2))
3951 (match_operand:SI 1 "gpc_reg_operand" "")))
3952 (const_int 0)))
3953 (set (match_operand:SI 0 "gpc_reg_operand" "")
3954 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3955 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3956 "TARGET_POWER && reload_completed"
3957 [(set (match_dup 0)
3958 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3959 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3960 (set (match_dup 4)
3961 (compare:CC (match_dup 0)
3962 (const_int 0)))]
3963 "")
3965 (define_insn "*maskir_internal8"
3966 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3967 (compare:CC
3968 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3969 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3970 (and:SI (not:SI (match_dup 2))
3971 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3972 (const_int 0)))
3973 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3974 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3975 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3976 "TARGET_POWER"
3977 "@
3978 maskir. %0,%3,%2
3979 #"
3980 [(set_attr "type" "compare")
3981 (set_attr "length" "4,8")])
3983 (define_split
3984 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3985 (compare:CC
3986 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3987 (match_operand:SI 2 "gpc_reg_operand" ""))
3988 (and:SI (not:SI (match_dup 2))
3989 (match_operand:SI 1 "gpc_reg_operand" "")))
3990 (const_int 0)))
3991 (set (match_operand:SI 0 "gpc_reg_operand" "")
3992 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3993 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3994 "TARGET_POWER && reload_completed"
3995 [(set (match_dup 0)
3996 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3997 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3998 (set (match_dup 4)
3999 (compare:CC (match_dup 0)
4000 (const_int 0)))]
4001 "")
4002 \f
4003 ;; Rotate and shift insns, in all their variants. These support shifts,
4004 ;; field inserts and extracts, and various combinations thereof.
4005 (define_expand "insv"
4006 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
4007 (match_operand:SI 1 "const_int_operand" "")
4008 (match_operand:SI 2 "const_int_operand" ""))
4009 (match_operand 3 "gpc_reg_operand" ""))]
4010 ""
4011 "
4012 {
4013 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4014 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4015 compiler if the address of the structure is taken later. Likewise, do
4016 not handle invalid E500 subregs. */
4017 if (GET_CODE (operands[0]) == SUBREG
4018 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
4019 || ((TARGET_E500_DOUBLE || TARGET_SPE)
4020 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
4021 FAIL;
4023 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
4024 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
4025 else
4026 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
4027 DONE;
4028 }")
4030 (define_insn "insvsi"
4031 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4032 (match_operand:SI 1 "const_int_operand" "i")
4033 (match_operand:SI 2 "const_int_operand" "i"))
4034 (match_operand:SI 3 "gpc_reg_operand" "r"))]
4035 ""
4036 "*
4037 {
4038 int start = INTVAL (operands[2]) & 31;
4039 int size = INTVAL (operands[1]) & 31;
4041 operands[4] = GEN_INT (32 - start - size);
4042 operands[1] = GEN_INT (start + size - 1);
4043 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4044 }"
4045 [(set_attr "type" "insert_word")])
4047 (define_insn "*insvsi_internal1"
4048 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4049 (match_operand:SI 1 "const_int_operand" "i")
4050 (match_operand:SI 2 "const_int_operand" "i"))
4051 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4052 (match_operand:SI 4 "const_int_operand" "i")))]
4053 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4054 "*
4055 {
4056 int shift = INTVAL (operands[4]) & 31;
4057 int start = INTVAL (operands[2]) & 31;
4058 int size = INTVAL (operands[1]) & 31;
4060 operands[4] = GEN_INT (shift - start - size);
4061 operands[1] = GEN_INT (start + size - 1);
4062 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4063 }"
4064 [(set_attr "type" "insert_word")])
4066 (define_insn "*insvsi_internal2"
4067 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4068 (match_operand:SI 1 "const_int_operand" "i")
4069 (match_operand:SI 2 "const_int_operand" "i"))
4070 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4071 (match_operand:SI 4 "const_int_operand" "i")))]
4072 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4073 "*
4074 {
4075 int shift = INTVAL (operands[4]) & 31;
4076 int start = INTVAL (operands[2]) & 31;
4077 int size = INTVAL (operands[1]) & 31;
4079 operands[4] = GEN_INT (32 - shift - start - size);
4080 operands[1] = GEN_INT (start + size - 1);
4081 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4082 }"
4083 [(set_attr "type" "insert_word")])
4085 (define_insn "*insvsi_internal3"
4086 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4087 (match_operand:SI 1 "const_int_operand" "i")
4088 (match_operand:SI 2 "const_int_operand" "i"))
4089 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4090 (match_operand:SI 4 "const_int_operand" "i")))]
4091 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4092 "*
4093 {
4094 int shift = INTVAL (operands[4]) & 31;
4095 int start = INTVAL (operands[2]) & 31;
4096 int size = INTVAL (operands[1]) & 31;
4098 operands[4] = GEN_INT (32 - shift - start - size);
4099 operands[1] = GEN_INT (start + size - 1);
4100 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4101 }"
4102 [(set_attr "type" "insert_word")])
4104 (define_insn "*insvsi_internal4"
4105 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4106 (match_operand:SI 1 "const_int_operand" "i")
4107 (match_operand:SI 2 "const_int_operand" "i"))
4108 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4109 (match_operand:SI 4 "const_int_operand" "i")
4110 (match_operand:SI 5 "const_int_operand" "i")))]
4111 "INTVAL (operands[4]) >= INTVAL (operands[1])"
4112 "*
4113 {
4114 int extract_start = INTVAL (operands[5]) & 31;
4115 int extract_size = INTVAL (operands[4]) & 31;
4116 int insert_start = INTVAL (operands[2]) & 31;
4117 int insert_size = INTVAL (operands[1]) & 31;
4119 /* Align extract field with insert field */
4120 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
4121 operands[1] = GEN_INT (insert_start + insert_size - 1);
4122 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
4123 }"
4124 [(set_attr "type" "insert_word")])
4126 ;; combine patterns for rlwimi
4127 (define_insn "*insvsi_internal5"
4128 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4129 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4130 (match_operand:SI 1 "mask_operand" "i"))
4131 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4132 (match_operand:SI 2 "const_int_operand" "i"))
4133 (match_operand:SI 5 "mask_operand" "i"))))]
4134 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4135 "*
4136 {
4137 int me = extract_ME(operands[5]);
4138 int mb = extract_MB(operands[5]);
4139 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4140 operands[2] = GEN_INT(mb);
4141 operands[1] = GEN_INT(me);
4142 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4143 }"
4144 [(set_attr "type" "insert_word")])
4146 (define_insn "*insvsi_internal6"
4147 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4148 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4149 (match_operand:SI 2 "const_int_operand" "i"))
4150 (match_operand:SI 5 "mask_operand" "i"))
4151 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4152 (match_operand:SI 1 "mask_operand" "i"))))]
4153 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4154 "*
4155 {
4156 int me = extract_ME(operands[5]);
4157 int mb = extract_MB(operands[5]);
4158 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4159 operands[2] = GEN_INT(mb);
4160 operands[1] = GEN_INT(me);
4161 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4162 }"
4163 [(set_attr "type" "insert_word")])
4165 (define_insn "insvdi"
4166 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4167 (match_operand:SI 1 "const_int_operand" "i")
4168 (match_operand:SI 2 "const_int_operand" "i"))
4169 (match_operand:DI 3 "gpc_reg_operand" "r"))]
4170 "TARGET_POWERPC64"
4171 "*
4172 {
4173 int start = INTVAL (operands[2]) & 63;
4174 int size = INTVAL (operands[1]) & 63;
4176 operands[1] = GEN_INT (64 - start - size);
4177 return \"rldimi %0,%3,%H1,%H2\";
4178 }"
4179 [(set_attr "type" "insert_dword")])
4181 (define_insn "*insvdi_internal2"
4182 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4183 (match_operand:SI 1 "const_int_operand" "i")
4184 (match_operand:SI 2 "const_int_operand" "i"))
4185 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4186 (match_operand:SI 4 "const_int_operand" "i")))]
4187 "TARGET_POWERPC64
4188 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4189 "*
4190 {
4191 int shift = INTVAL (operands[4]) & 63;
4192 int start = (INTVAL (operands[2]) & 63) - 32;
4193 int size = INTVAL (operands[1]) & 63;
4195 operands[4] = GEN_INT (64 - shift - start - size);
4196 operands[2] = GEN_INT (start);
4197 operands[1] = GEN_INT (start + size - 1);
4198 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4199 }")
4201 (define_insn "*insvdi_internal3"
4202 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4203 (match_operand:SI 1 "const_int_operand" "i")
4204 (match_operand:SI 2 "const_int_operand" "i"))
4205 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4206 (match_operand:SI 4 "const_int_operand" "i")))]
4207 "TARGET_POWERPC64
4208 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4209 "*
4210 {
4211 int shift = INTVAL (operands[4]) & 63;
4212 int start = (INTVAL (operands[2]) & 63) - 32;
4213 int size = INTVAL (operands[1]) & 63;
4215 operands[4] = GEN_INT (64 - shift - start - size);
4216 operands[2] = GEN_INT (start);
4217 operands[1] = GEN_INT (start + size - 1);
4218 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4219 }")
4221 (define_expand "extzv"
4222 [(set (match_operand 0 "gpc_reg_operand" "")
4223 (zero_extract (match_operand 1 "gpc_reg_operand" "")
4224 (match_operand:SI 2 "const_int_operand" "")
4225 (match_operand:SI 3 "const_int_operand" "")))]
4226 ""
4227 "
4228 {
4229 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4230 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4231 compiler if the address of the structure is taken later. */
4232 if (GET_CODE (operands[0]) == SUBREG
4233 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
4234 FAIL;
4236 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
4237 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
4238 else
4239 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
4240 DONE;
4241 }")
4243 (define_insn "extzvsi"
4244 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4245 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4246 (match_operand:SI 2 "const_int_operand" "i")
4247 (match_operand:SI 3 "const_int_operand" "i")))]
4248 ""
4249 "*
4250 {
4251 int start = INTVAL (operands[3]) & 31;
4252 int size = INTVAL (operands[2]) & 31;
4254 if (start + size >= 32)
4255 operands[3] = const0_rtx;
4256 else
4257 operands[3] = GEN_INT (start + size);
4258 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
4259 }")
4261 (define_insn "*extzvsi_internal1"
4262 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4263 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4264 (match_operand:SI 2 "const_int_operand" "i,i")
4265 (match_operand:SI 3 "const_int_operand" "i,i"))
4266 (const_int 0)))
4267 (clobber (match_scratch:SI 4 "=r,r"))]
4268 ""
4269 "*
4270 {
4271 int start = INTVAL (operands[3]) & 31;
4272 int size = INTVAL (operands[2]) & 31;
4274 /* Force split for non-cc0 compare. */
4275 if (which_alternative == 1)
4276 return \"#\";
4278 /* If the bit-field being tested fits in the upper or lower half of a
4279 word, it is possible to use andiu. or andil. to test it. This is
4280 useful because the condition register set-use delay is smaller for
4281 andi[ul]. than for rlinm. This doesn't work when the starting bit
4282 position is 0 because the LT and GT bits may be set wrong. */
4284 if ((start > 0 && start + size <= 16) || start >= 16)
4285 {
4286 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
4287 - (1 << (16 - (start & 15) - size))));
4288 if (start < 16)
4289 return \"{andiu.|andis.} %4,%1,%3\";
4290 else
4291 return \"{andil.|andi.} %4,%1,%3\";
4292 }
4294 if (start + size >= 32)
4295 operands[3] = const0_rtx;
4296 else
4297 operands[3] = GEN_INT (start + size);
4298 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
4299 }"
4300 [(set_attr "type" "delayed_compare")
4301 (set_attr "length" "4,8")])
4303 (define_split
4304 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4305 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4306 (match_operand:SI 2 "const_int_operand" "")
4307 (match_operand:SI 3 "const_int_operand" ""))
4308 (const_int 0)))
4309 (clobber (match_scratch:SI 4 ""))]
4310 "reload_completed"
4311 [(set (match_dup 4)
4312 (zero_extract:SI (match_dup 1) (match_dup 2)
4313 (match_dup 3)))
4314 (set (match_dup 0)
4315 (compare:CC (match_dup 4)
4316 (const_int 0)))]
4317 "")
4319 (define_insn "*extzvsi_internal2"
4320 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4321 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4322 (match_operand:SI 2 "const_int_operand" "i,i")
4323 (match_operand:SI 3 "const_int_operand" "i,i"))
4324 (const_int 0)))
4325 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4326 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4327 ""
4328 "*
4329 {
4330 int start = INTVAL (operands[3]) & 31;
4331 int size = INTVAL (operands[2]) & 31;
4333 /* Force split for non-cc0 compare. */
4334 if (which_alternative == 1)
4335 return \"#\";
4337 /* Since we are using the output value, we can't ignore any need for
4338 a shift. The bit-field must end at the LSB. */
4339 if (start >= 16 && start + size == 32)
4340 {
4341 operands[3] = GEN_INT ((1 << size) - 1);
4342 return \"{andil.|andi.} %0,%1,%3\";
4343 }
4345 if (start + size >= 32)
4346 operands[3] = const0_rtx;
4347 else
4348 operands[3] = GEN_INT (start + size);
4349 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
4350 }"
4351 [(set_attr "type" "delayed_compare")
4352 (set_attr "length" "4,8")])
4354 (define_split
4355 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4356 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4357 (match_operand:SI 2 "const_int_operand" "")
4358 (match_operand:SI 3 "const_int_operand" ""))
4359 (const_int 0)))
4360 (set (match_operand:SI 0 "gpc_reg_operand" "")
4361 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4362 "reload_completed"
4363 [(set (match_dup 0)
4364 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
4365 (set (match_dup 4)
4366 (compare:CC (match_dup 0)
4367 (const_int 0)))]
4368 "")
4370 (define_insn "extzvdi"
4371 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4372 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4373 (match_operand:SI 2 "const_int_operand" "i")
4374 (match_operand:SI 3 "const_int_operand" "i")))]
4375 "TARGET_POWERPC64"
4376 "*
4377 {
4378 int start = INTVAL (operands[3]) & 63;
4379 int size = INTVAL (operands[2]) & 63;
4381 if (start + size >= 64)
4382 operands[3] = const0_rtx;
4383 else
4384 operands[3] = GEN_INT (start + size);
4385 operands[2] = GEN_INT (64 - size);
4386 return \"rldicl %0,%1,%3,%2\";
4387 }")
4389 (define_insn "*extzvdi_internal1"
4390 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
4391 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4392 (match_operand:SI 2 "const_int_operand" "i")
4393 (match_operand:SI 3 "const_int_operand" "i"))
4394 (const_int 0)))
4395 (clobber (match_scratch:DI 4 "=r"))]
4396 "TARGET_64BIT && rs6000_gen_cell_microcode"
4397 "*
4398 {
4399 int start = INTVAL (operands[3]) & 63;
4400 int size = INTVAL (operands[2]) & 63;
4402 if (start + size >= 64)
4403 operands[3] = const0_rtx;
4404 else
4405 operands[3] = GEN_INT (start + size);
4406 operands[2] = GEN_INT (64 - size);
4407 return \"rldicl. %4,%1,%3,%2\";
4408 }"
4409 [(set_attr "type" "compare")])
4411 (define_insn "*extzvdi_internal2"
4412 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
4413 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4414 (match_operand:SI 2 "const_int_operand" "i")
4415 (match_operand:SI 3 "const_int_operand" "i"))
4416 (const_int 0)))
4417 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4418 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
4419 "TARGET_64BIT && rs6000_gen_cell_microcode"
4420 "*
4421 {
4422 int start = INTVAL (operands[3]) & 63;
4423 int size = INTVAL (operands[2]) & 63;
4425 if (start + size >= 64)
4426 operands[3] = const0_rtx;
4427 else
4428 operands[3] = GEN_INT (start + size);
4429 operands[2] = GEN_INT (64 - size);
4430 return \"rldicl. %0,%1,%3,%2\";
4431 }"
4432 [(set_attr "type" "compare")])
4434 (define_insn "rotlsi3"
4435 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4436 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4437 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4438 ""
4439 "@
4440 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4441 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4442 [(set_attr "type" "var_shift_rotate,integer")])
4444 (define_insn "*rotlsi3_64"
4445 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4446 (zero_extend:DI
4447 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4448 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4449 "TARGET_64BIT"
4450 "@
4451 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4452 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4453 [(set_attr "type" "var_shift_rotate,integer")])
4455 (define_insn "*rotlsi3_internal2"
4456 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4457 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4458 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4459 (const_int 0)))
4460 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4461 ""
4462 "@
4463 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4464 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4465 #
4466 #"
4467 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4468 (set_attr "length" "4,4,8,8")])
4470 (define_split
4471 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4472 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4473 (match_operand:SI 2 "reg_or_cint_operand" ""))
4474 (const_int 0)))
4475 (clobber (match_scratch:SI 3 ""))]
4476 "reload_completed"
4477 [(set (match_dup 3)
4478 (rotate:SI (match_dup 1) (match_dup 2)))
4479 (set (match_dup 0)
4480 (compare:CC (match_dup 3)
4481 (const_int 0)))]
4482 "")
4484 (define_insn "*rotlsi3_internal3"
4485 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4486 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4487 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4488 (const_int 0)))
4489 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4490 (rotate:SI (match_dup 1) (match_dup 2)))]
4491 ""
4492 "@
4493 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4494 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4495 #
4496 #"
4497 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4498 (set_attr "length" "4,4,8,8")])
4500 (define_split
4501 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4502 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4503 (match_operand:SI 2 "reg_or_cint_operand" ""))
4504 (const_int 0)))
4505 (set (match_operand:SI 0 "gpc_reg_operand" "")
4506 (rotate:SI (match_dup 1) (match_dup 2)))]
4507 "reload_completed"
4508 [(set (match_dup 0)
4509 (rotate:SI (match_dup 1) (match_dup 2)))
4510 (set (match_dup 3)
4511 (compare:CC (match_dup 0)
4512 (const_int 0)))]
4513 "")
4515 (define_insn "*rotlsi3_internal4"
4516 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4517 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4518 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4519 (match_operand:SI 3 "mask_operand" "n,n")))]
4520 ""
4521 "@
4522 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4523 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4524 [(set_attr "type" "var_shift_rotate,integer")])
4526 (define_insn "*rotlsi3_internal5"
4527 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4528 (compare:CC (and:SI
4529 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4530 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4531 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4532 (const_int 0)))
4533 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4534 ""
4535 "@
4536 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4537 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4538 #
4539 #"
4540 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4541 (set_attr "length" "4,4,8,8")])
4543 (define_split
4544 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4545 (compare:CC (and:SI
4546 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4547 (match_operand:SI 2 "reg_or_cint_operand" ""))
4548 (match_operand:SI 3 "mask_operand" ""))
4549 (const_int 0)))
4550 (clobber (match_scratch:SI 4 ""))]
4551 "reload_completed"
4552 [(set (match_dup 4)
4553 (and:SI (rotate:SI (match_dup 1)
4554 (match_dup 2))
4555 (match_dup 3)))
4556 (set (match_dup 0)
4557 (compare:CC (match_dup 4)
4558 (const_int 0)))]
4559 "")
4561 (define_insn "*rotlsi3_internal6"
4562 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4563 (compare:CC (and:SI
4564 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4565 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4566 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4567 (const_int 0)))
4568 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4569 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4570 ""
4571 "@
4572 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4573 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4574 #
4575 #"
4576 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4577 (set_attr "length" "4,4,8,8")])
4579 (define_split
4580 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4581 (compare:CC (and:SI
4582 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4583 (match_operand:SI 2 "reg_or_cint_operand" ""))
4584 (match_operand:SI 3 "mask_operand" ""))
4585 (const_int 0)))
4586 (set (match_operand:SI 0 "gpc_reg_operand" "")
4587 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4588 "reload_completed"
4589 [(set (match_dup 0)
4590 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4591 (set (match_dup 4)
4592 (compare:CC (match_dup 0)
4593 (const_int 0)))]
4594 "")
4596 (define_insn "*rotlsi3_internal7"
4597 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4598 (zero_extend:SI
4599 (subreg:QI
4600 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4601 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4602 ""
4603 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4604 [(set (attr "cell_micro")
4605 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4606 (const_string "not")
4607 (const_string "always")))])
4609 (define_insn "*rotlsi3_internal8"
4610 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4611 (compare:CC (zero_extend:SI
4612 (subreg:QI
4613 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4614 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4615 (const_int 0)))
4616 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4617 ""
4618 "@
4619 {rlnm.|rlwnm.} %3,%1,%2,0xff
4620 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4621 #
4622 #"
4623 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4624 (set_attr "length" "4,4,8,8")])
4626 (define_split
4627 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4628 (compare:CC (zero_extend:SI
4629 (subreg:QI
4630 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4631 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4632 (const_int 0)))
4633 (clobber (match_scratch:SI 3 ""))]
4634 "reload_completed"
4635 [(set (match_dup 3)
4636 (zero_extend:SI (subreg:QI
4637 (rotate:SI (match_dup 1)
4638 (match_dup 2)) 0)))
4639 (set (match_dup 0)
4640 (compare:CC (match_dup 3)
4641 (const_int 0)))]
4642 "")
4644 (define_insn "*rotlsi3_internal9"
4645 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4646 (compare:CC (zero_extend:SI
4647 (subreg:QI
4648 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4649 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4650 (const_int 0)))
4651 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4652 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4653 ""
4654 "@
4655 {rlnm.|rlwnm.} %0,%1,%2,0xff
4656 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4657 #
4658 #"
4659 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4660 (set_attr "length" "4,4,8,8")])
4662 (define_split
4663 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4664 (compare:CC (zero_extend:SI
4665 (subreg:QI
4666 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4667 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4668 (const_int 0)))
4669 (set (match_operand:SI 0 "gpc_reg_operand" "")
4670 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4671 "reload_completed"
4672 [(set (match_dup 0)
4673 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4674 (set (match_dup 3)
4675 (compare:CC (match_dup 0)
4676 (const_int 0)))]
4677 "")
4679 (define_insn "*rotlsi3_internal10"
4680 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4681 (zero_extend:SI
4682 (subreg:HI
4683 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4684 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4685 ""
4686 "@
4687 {rlnm|rlwnm} %0,%1,%2,0xffff
4688 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4689 [(set_attr "type" "var_shift_rotate,integer")])
4692 (define_insn "*rotlsi3_internal11"
4693 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4694 (compare:CC (zero_extend:SI
4695 (subreg:HI
4696 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4697 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4698 (const_int 0)))
4699 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4700 ""
4701 "@
4702 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4703 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4704 #
4705 #"
4706 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4707 (set_attr "length" "4,4,8,8")])
4709 (define_split
4710 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4711 (compare:CC (zero_extend:SI
4712 (subreg:HI
4713 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4714 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4715 (const_int 0)))
4716 (clobber (match_scratch:SI 3 ""))]
4717 "reload_completed"
4718 [(set (match_dup 3)
4719 (zero_extend:SI (subreg:HI
4720 (rotate:SI (match_dup 1)
4721 (match_dup 2)) 0)))
4722 (set (match_dup 0)
4723 (compare:CC (match_dup 3)
4724 (const_int 0)))]
4725 "")
4727 (define_insn "*rotlsi3_internal12"
4728 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4729 (compare:CC (zero_extend:SI
4730 (subreg:HI
4731 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4732 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4733 (const_int 0)))
4734 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4735 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4736 ""
4737 "@
4738 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4739 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4740 #
4741 #"
4742 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4743 (set_attr "length" "4,4,8,8")])
4745 (define_split
4746 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4747 (compare:CC (zero_extend:SI
4748 (subreg:HI
4749 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4750 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4751 (const_int 0)))
4752 (set (match_operand:SI 0 "gpc_reg_operand" "")
4753 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4754 "reload_completed"
4755 [(set (match_dup 0)
4756 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4757 (set (match_dup 3)
4758 (compare:CC (match_dup 0)
4759 (const_int 0)))]
4760 "")
4762 ;; Note that we use "sle." instead of "sl." so that we can set
4763 ;; SHIFT_COUNT_TRUNCATED.
4765 (define_expand "ashlsi3"
4766 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4767 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4768 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4769 ""
4770 "
4771 {
4772 if (TARGET_POWER)
4773 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4774 else
4775 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4776 DONE;
4777 }")
4779 (define_insn "ashlsi3_power"
4780 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4781 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4782 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4783 (clobber (match_scratch:SI 3 "=q,X"))]
4784 "TARGET_POWER"
4785 "@
4786 sle %0,%1,%2
4787 {sli|slwi} %0,%1,%h2")
4789 (define_insn "ashlsi3_no_power"
4790 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4791 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4792 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4793 "! TARGET_POWER"
4794 "@
4795 {sl|slw} %0,%1,%2
4796 {sli|slwi} %0,%1,%h2"
4797 [(set_attr "type" "var_shift_rotate,shift")])
4799 (define_insn "*ashlsi3_64"
4800 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4801 (zero_extend:DI
4802 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4803 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4804 "TARGET_POWERPC64"
4805 "@
4806 {sl|slw} %0,%1,%2
4807 {sli|slwi} %0,%1,%h2"
4808 [(set_attr "type" "var_shift_rotate,shift")])
4810 (define_insn ""
4811 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4812 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4813 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4814 (const_int 0)))
4815 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4816 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4817 "TARGET_POWER"
4818 "@
4819 sle. %3,%1,%2
4820 {sli.|slwi.} %3,%1,%h2
4821 #
4822 #"
4823 [(set_attr "type" "delayed_compare")
4824 (set_attr "length" "4,4,8,8")])
4826 (define_split
4827 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4828 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4829 (match_operand:SI 2 "reg_or_cint_operand" ""))
4830 (const_int 0)))
4831 (clobber (match_scratch:SI 3 ""))
4832 (clobber (match_scratch:SI 4 ""))]
4833 "TARGET_POWER && reload_completed"
4834 [(parallel [(set (match_dup 3)
4835 (ashift:SI (match_dup 1) (match_dup 2)))
4836 (clobber (match_dup 4))])
4837 (set (match_dup 0)
4838 (compare:CC (match_dup 3)
4839 (const_int 0)))]
4840 "")
4842 (define_insn ""
4843 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4844 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4845 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4846 (const_int 0)))
4847 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4848 "! TARGET_POWER && TARGET_32BIT"
4849 "@
4850 {sl.|slw.} %3,%1,%2
4851 {sli.|slwi.} %3,%1,%h2
4852 #
4853 #"
4854 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4855 (set_attr "length" "4,4,8,8")])
4857 (define_split
4858 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4859 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4860 (match_operand:SI 2 "reg_or_cint_operand" ""))
4861 (const_int 0)))
4862 (clobber (match_scratch:SI 3 ""))]
4863 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4864 [(set (match_dup 3)
4865 (ashift:SI (match_dup 1) (match_dup 2)))
4866 (set (match_dup 0)
4867 (compare:CC (match_dup 3)
4868 (const_int 0)))]
4869 "")
4871 (define_insn ""
4872 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4873 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4874 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4875 (const_int 0)))
4876 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4877 (ashift:SI (match_dup 1) (match_dup 2)))
4878 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4879 "TARGET_POWER"
4880 "@
4881 sle. %0,%1,%2
4882 {sli.|slwi.} %0,%1,%h2
4883 #
4884 #"
4885 [(set_attr "type" "delayed_compare")
4886 (set_attr "length" "4,4,8,8")])
4888 (define_split
4889 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4890 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4891 (match_operand:SI 2 "reg_or_cint_operand" ""))
4892 (const_int 0)))
4893 (set (match_operand:SI 0 "gpc_reg_operand" "")
4894 (ashift:SI (match_dup 1) (match_dup 2)))
4895 (clobber (match_scratch:SI 4 ""))]
4896 "TARGET_POWER && reload_completed"
4897 [(parallel [(set (match_dup 0)
4898 (ashift:SI (match_dup 1) (match_dup 2)))
4899 (clobber (match_dup 4))])
4900 (set (match_dup 3)
4901 (compare:CC (match_dup 0)
4902 (const_int 0)))]
4903 "")
4905 (define_insn ""
4906 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4907 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4908 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4909 (const_int 0)))
4910 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4911 (ashift:SI (match_dup 1) (match_dup 2)))]
4912 "! TARGET_POWER && TARGET_32BIT"
4913 "@
4914 {sl.|slw.} %0,%1,%2
4915 {sli.|slwi.} %0,%1,%h2
4916 #
4917 #"
4918 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4919 (set_attr "length" "4,4,8,8")])
4921 (define_split
4922 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4923 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4924 (match_operand:SI 2 "reg_or_cint_operand" ""))
4925 (const_int 0)))
4926 (set (match_operand:SI 0 "gpc_reg_operand" "")
4927 (ashift:SI (match_dup 1) (match_dup 2)))]
4928 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4929 [(set (match_dup 0)
4930 (ashift:SI (match_dup 1) (match_dup 2)))
4931 (set (match_dup 3)
4932 (compare:CC (match_dup 0)
4933 (const_int 0)))]
4934 "")
4936 (define_insn "rlwinm"
4937 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4938 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4939 (match_operand:SI 2 "const_int_operand" "i"))
4940 (match_operand:SI 3 "mask_operand" "n")))]
4941 "includes_lshift_p (operands[2], operands[3])"
4942 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4944 (define_insn ""
4945 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4946 (compare:CC
4947 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4948 (match_operand:SI 2 "const_int_operand" "i,i"))
4949 (match_operand:SI 3 "mask_operand" "n,n"))
4950 (const_int 0)))
4951 (clobber (match_scratch:SI 4 "=r,r"))]
4952 "includes_lshift_p (operands[2], operands[3])"
4953 "@
4954 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4955 #"
4956 [(set_attr "type" "delayed_compare")
4957 (set_attr "length" "4,8")])
4959 (define_split
4960 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4961 (compare:CC
4962 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4963 (match_operand:SI 2 "const_int_operand" ""))
4964 (match_operand:SI 3 "mask_operand" ""))
4965 (const_int 0)))
4966 (clobber (match_scratch:SI 4 ""))]
4967 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4968 [(set (match_dup 4)
4969 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4970 (match_dup 3)))
4971 (set (match_dup 0)
4972 (compare:CC (match_dup 4)
4973 (const_int 0)))]
4974 "")
4976 (define_insn ""
4977 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4978 (compare:CC
4979 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4980 (match_operand:SI 2 "const_int_operand" "i,i"))
4981 (match_operand:SI 3 "mask_operand" "n,n"))
4982 (const_int 0)))
4983 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4984 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4985 "includes_lshift_p (operands[2], operands[3])"
4986 "@
4987 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4988 #"
4989 [(set_attr "type" "delayed_compare")
4990 (set_attr "length" "4,8")])
4992 (define_split
4993 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4994 (compare:CC
4995 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4996 (match_operand:SI 2 "const_int_operand" ""))
4997 (match_operand:SI 3 "mask_operand" ""))
4998 (const_int 0)))
4999 (set (match_operand:SI 0 "gpc_reg_operand" "")
5000 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5001 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
5002 [(set (match_dup 0)
5003 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5004 (set (match_dup 4)
5005 (compare:CC (match_dup 0)
5006 (const_int 0)))]
5007 "")
5009 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5010 ;; "sli x,x,0".
5011 (define_expand "lshrsi3"
5012 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
5013 (use (match_operand:SI 1 "gpc_reg_operand" ""))
5014 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
5015 ""
5016 "
5017 {
5018 if (TARGET_POWER)
5019 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
5020 else
5021 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
5022 DONE;
5023 }")
5025 (define_insn "lshrsi3_power"
5026 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5027 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5028 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
5029 (clobber (match_scratch:SI 3 "=q,X,X"))]
5030 "TARGET_POWER"
5031 "@
5032 sre %0,%1,%2
5033 mr %0,%1
5034 {s%A2i|s%A2wi} %0,%1,%h2")
5036 (define_insn "lshrsi3_no_power"
5037 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5038 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5039 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
5040 "! TARGET_POWER"
5041 "@
5042 mr %0,%1
5043 {sr|srw} %0,%1,%2
5044 {sri|srwi} %0,%1,%h2"
5045 [(set_attr "type" "integer,var_shift_rotate,shift")])
5047 (define_insn "*lshrsi3_64"
5048 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5049 (zero_extend:DI
5050 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5051 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5052 "TARGET_POWERPC64"
5053 "@
5054 {sr|srw} %0,%1,%2
5055 {sri|srwi} %0,%1,%h2"
5056 [(set_attr "type" "var_shift_rotate,shift")])
5058 (define_insn ""
5059 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5060 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5061 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5062 (const_int 0)))
5063 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
5064 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5065 "TARGET_POWER"
5066 "@
5067 sre. %3,%1,%2
5068 mr. %1,%1
5069 {s%A2i.|s%A2wi.} %3,%1,%h2
5070 #
5071 #
5072 #"
5073 [(set_attr "type" "delayed_compare")
5074 (set_attr "length" "4,4,4,8,8,8")])
5076 (define_split
5077 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5078 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5079 (match_operand:SI 2 "reg_or_cint_operand" ""))
5080 (const_int 0)))
5081 (clobber (match_scratch:SI 3 ""))
5082 (clobber (match_scratch:SI 4 ""))]
5083 "TARGET_POWER && reload_completed"
5084 [(parallel [(set (match_dup 3)
5085 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5086 (clobber (match_dup 4))])
5087 (set (match_dup 0)
5088 (compare:CC (match_dup 3)
5089 (const_int 0)))]
5090 "")
5092 (define_insn ""
5093 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5094 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5095 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5096 (const_int 0)))
5097 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
5098 "! TARGET_POWER && TARGET_32BIT"
5099 "@
5100 mr. %1,%1
5101 {sr.|srw.} %3,%1,%2
5102 {sri.|srwi.} %3,%1,%h2
5103 #
5104 #
5105 #"
5106 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5107 (set_attr "length" "4,4,4,8,8,8")])
5109 (define_split
5110 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5111 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5112 (match_operand:SI 2 "reg_or_cint_operand" ""))
5113 (const_int 0)))
5114 (clobber (match_scratch:SI 3 ""))]
5115 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5116 [(set (match_dup 3)
5117 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5118 (set (match_dup 0)
5119 (compare:CC (match_dup 3)
5120 (const_int 0)))]
5121 "")
5123 (define_insn ""
5124 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5125 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5126 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5127 (const_int 0)))
5128 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5129 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5130 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5131 "TARGET_POWER"
5132 "@
5133 sre. %0,%1,%2
5134 mr. %0,%1
5135 {s%A2i.|s%A2wi.} %0,%1,%h2
5136 #
5137 #
5138 #"
5139 [(set_attr "type" "delayed_compare")
5140 (set_attr "length" "4,4,4,8,8,8")])
5142 (define_split
5143 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5144 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5145 (match_operand:SI 2 "reg_or_cint_operand" ""))
5146 (const_int 0)))
5147 (set (match_operand:SI 0 "gpc_reg_operand" "")
5148 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5149 (clobber (match_scratch:SI 4 ""))]
5150 "TARGET_POWER && reload_completed"
5151 [(parallel [(set (match_dup 0)
5152 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5153 (clobber (match_dup 4))])
5154 (set (match_dup 3)
5155 (compare:CC (match_dup 0)
5156 (const_int 0)))]
5157 "")
5159 (define_insn ""
5160 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5161 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5162 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5163 (const_int 0)))
5164 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5165 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5166 "! TARGET_POWER && TARGET_32BIT"
5167 "@
5168 mr. %0,%1
5169 {sr.|srw.} %0,%1,%2
5170 {sri.|srwi.} %0,%1,%h2
5171 #
5172 #
5173 #"
5174 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5175 (set_attr "length" "4,4,4,8,8,8")])
5177 (define_split
5178 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5179 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5180 (match_operand:SI 2 "reg_or_cint_operand" ""))
5181 (const_int 0)))
5182 (set (match_operand:SI 0 "gpc_reg_operand" "")
5183 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5184 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5185 [(set (match_dup 0)
5186 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5187 (set (match_dup 3)
5188 (compare:CC (match_dup 0)
5189 (const_int 0)))]
5190 "")
5192 (define_insn ""
5193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5194 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5195 (match_operand:SI 2 "const_int_operand" "i"))
5196 (match_operand:SI 3 "mask_operand" "n")))]
5197 "includes_rshift_p (operands[2], operands[3])"
5198 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
5200 (define_insn ""
5201 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5202 (compare:CC
5203 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5204 (match_operand:SI 2 "const_int_operand" "i,i"))
5205 (match_operand:SI 3 "mask_operand" "n,n"))
5206 (const_int 0)))
5207 (clobber (match_scratch:SI 4 "=r,r"))]
5208 "includes_rshift_p (operands[2], operands[3])"
5209 "@
5210 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
5211 #"
5212 [(set_attr "type" "delayed_compare")
5213 (set_attr "length" "4,8")])
5215 (define_split
5216 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5217 (compare:CC
5218 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5219 (match_operand:SI 2 "const_int_operand" ""))
5220 (match_operand:SI 3 "mask_operand" ""))
5221 (const_int 0)))
5222 (clobber (match_scratch:SI 4 ""))]
5223 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5224 [(set (match_dup 4)
5225 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
5226 (match_dup 3)))
5227 (set (match_dup 0)
5228 (compare:CC (match_dup 4)
5229 (const_int 0)))]
5230 "")
5232 (define_insn ""
5233 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5234 (compare:CC
5235 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5236 (match_operand:SI 2 "const_int_operand" "i,i"))
5237 (match_operand:SI 3 "mask_operand" "n,n"))
5238 (const_int 0)))
5239 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5240 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5241 "includes_rshift_p (operands[2], operands[3])"
5242 "@
5243 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
5244 #"
5245 [(set_attr "type" "delayed_compare")
5246 (set_attr "length" "4,8")])
5248 (define_split
5249 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5250 (compare:CC
5251 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5252 (match_operand:SI 2 "const_int_operand" ""))
5253 (match_operand:SI 3 "mask_operand" ""))
5254 (const_int 0)))
5255 (set (match_operand:SI 0 "gpc_reg_operand" "")
5256 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5257 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5258 [(set (match_dup 0)
5259 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5260 (set (match_dup 4)
5261 (compare:CC (match_dup 0)
5262 (const_int 0)))]
5263 "")
5265 (define_insn ""
5266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5267 (zero_extend:SI
5268 (subreg:QI
5269 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5270 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5271 "includes_rshift_p (operands[2], GEN_INT (255))"
5272 "{rlinm|rlwinm} %0,%1,%s2,0xff")
5274 (define_insn ""
5275 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5276 (compare:CC
5277 (zero_extend:SI
5278 (subreg:QI
5279 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5280 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5281 (const_int 0)))
5282 (clobber (match_scratch:SI 3 "=r,r"))]
5283 "includes_rshift_p (operands[2], GEN_INT (255))"
5284 "@
5285 {rlinm.|rlwinm.} %3,%1,%s2,0xff
5286 #"
5287 [(set_attr "type" "delayed_compare")
5288 (set_attr "length" "4,8")])
5290 (define_split
5291 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5292 (compare:CC
5293 (zero_extend:SI
5294 (subreg:QI
5295 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5296 (match_operand:SI 2 "const_int_operand" "")) 0))
5297 (const_int 0)))
5298 (clobber (match_scratch:SI 3 ""))]
5299 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5300 [(set (match_dup 3)
5301 (zero_extend:SI (subreg:QI
5302 (lshiftrt:SI (match_dup 1)
5303 (match_dup 2)) 0)))
5304 (set (match_dup 0)
5305 (compare:CC (match_dup 3)
5306 (const_int 0)))]
5307 "")
5309 (define_insn ""
5310 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5311 (compare:CC
5312 (zero_extend:SI
5313 (subreg:QI
5314 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5315 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5316 (const_int 0)))
5317 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5318 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5319 "includes_rshift_p (operands[2], GEN_INT (255))"
5320 "@
5321 {rlinm.|rlwinm.} %0,%1,%s2,0xff
5322 #"
5323 [(set_attr "type" "delayed_compare")
5324 (set_attr "length" "4,8")])
5326 (define_split
5327 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5328 (compare:CC
5329 (zero_extend:SI
5330 (subreg:QI
5331 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5332 (match_operand:SI 2 "const_int_operand" "")) 0))
5333 (const_int 0)))
5334 (set (match_operand:SI 0 "gpc_reg_operand" "")
5335 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5336 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5337 [(set (match_dup 0)
5338 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5339 (set (match_dup 3)
5340 (compare:CC (match_dup 0)
5341 (const_int 0)))]
5342 "")
5344 (define_insn ""
5345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5346 (zero_extend:SI
5347 (subreg:HI
5348 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5349 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5350 "includes_rshift_p (operands[2], GEN_INT (65535))"
5351 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
5353 (define_insn ""
5354 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5355 (compare:CC
5356 (zero_extend:SI
5357 (subreg:HI
5358 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5359 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5360 (const_int 0)))
5361 (clobber (match_scratch:SI 3 "=r,r"))]
5362 "includes_rshift_p (operands[2], GEN_INT (65535))"
5363 "@
5364 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
5365 #"
5366 [(set_attr "type" "delayed_compare")
5367 (set_attr "length" "4,8")])
5369 (define_split
5370 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5371 (compare:CC
5372 (zero_extend:SI
5373 (subreg:HI
5374 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5375 (match_operand:SI 2 "const_int_operand" "")) 0))
5376 (const_int 0)))
5377 (clobber (match_scratch:SI 3 ""))]
5378 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5379 [(set (match_dup 3)
5380 (zero_extend:SI (subreg:HI
5381 (lshiftrt:SI (match_dup 1)
5382 (match_dup 2)) 0)))
5383 (set (match_dup 0)
5384 (compare:CC (match_dup 3)
5385 (const_int 0)))]
5386 "")
5388 (define_insn ""
5389 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5390 (compare:CC
5391 (zero_extend:SI
5392 (subreg:HI
5393 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5394 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5395 (const_int 0)))
5396 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5397 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5398 "includes_rshift_p (operands[2], GEN_INT (65535))"
5399 "@
5400 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
5401 #"
5402 [(set_attr "type" "delayed_compare")
5403 (set_attr "length" "4,8")])
5405 (define_split
5406 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5407 (compare:CC
5408 (zero_extend:SI
5409 (subreg:HI
5410 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5411 (match_operand:SI 2 "const_int_operand" "")) 0))
5412 (const_int 0)))
5413 (set (match_operand:SI 0 "gpc_reg_operand" "")
5414 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5415 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5416 [(set (match_dup 0)
5417 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5418 (set (match_dup 3)
5419 (compare:CC (match_dup 0)
5420 (const_int 0)))]
5421 "")
5423 (define_insn ""
5424 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5425 (const_int 1)
5426 (match_operand:SI 1 "gpc_reg_operand" "r"))
5427 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5428 (const_int 31)))]
5429 "TARGET_POWER"
5430 "rrib %0,%1,%2")
5432 (define_insn ""
5433 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5434 (const_int 1)
5435 (match_operand:SI 1 "gpc_reg_operand" "r"))
5436 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5437 (const_int 31)))]
5438 "TARGET_POWER"
5439 "rrib %0,%1,%2")
5441 (define_insn ""
5442 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5443 (const_int 1)
5444 (match_operand:SI 1 "gpc_reg_operand" "r"))
5445 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5446 (const_int 1)
5447 (const_int 0)))]
5448 "TARGET_POWER"
5449 "rrib %0,%1,%2")
5451 (define_expand "ashrsi3"
5452 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5453 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5454 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5455 ""
5456 "
5457 {
5458 if (TARGET_POWER)
5459 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
5460 else
5461 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
5462 DONE;
5463 }")
5465 (define_insn "ashrsi3_power"
5466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5467 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5468 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
5469 (clobber (match_scratch:SI 3 "=q,X"))]
5470 "TARGET_POWER"
5471 "@
5472 srea %0,%1,%2
5473 {srai|srawi} %0,%1,%h2"
5474 [(set_attr "type" "shift")])
5476 (define_insn "ashrsi3_no_power"
5477 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5478 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5479 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
5480 "! TARGET_POWER"
5481 "@
5482 {sra|sraw} %0,%1,%2
5483 {srai|srawi} %0,%1,%h2"
5484 [(set_attr "type" "var_shift_rotate,shift")])
5486 (define_insn "*ashrsi3_64"
5487 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5488 (sign_extend:DI
5489 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5490 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5491 "TARGET_POWERPC64"
5492 "@
5493 {sra|sraw} %0,%1,%2
5494 {srai|srawi} %0,%1,%h2"
5495 [(set_attr "type" "var_shift_rotate,shift")])
5497 (define_insn ""
5498 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5499 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5500 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5501 (const_int 0)))
5502 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5503 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5504 "TARGET_POWER"
5505 "@
5506 srea. %3,%1,%2
5507 {srai.|srawi.} %3,%1,%h2
5508 #
5509 #"
5510 [(set_attr "type" "delayed_compare")
5511 (set_attr "length" "4,4,8,8")])
5513 (define_split
5514 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5515 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5516 (match_operand:SI 2 "reg_or_cint_operand" ""))
5517 (const_int 0)))
5518 (clobber (match_scratch:SI 3 ""))
5519 (clobber (match_scratch:SI 4 ""))]
5520 "TARGET_POWER && reload_completed"
5521 [(parallel [(set (match_dup 3)
5522 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5523 (clobber (match_dup 4))])
5524 (set (match_dup 0)
5525 (compare:CC (match_dup 3)
5526 (const_int 0)))]
5527 "")
5529 (define_insn ""
5530 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5531 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5532 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5533 (const_int 0)))
5534 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5535 "! TARGET_POWER"
5536 "@
5537 {sra.|sraw.} %3,%1,%2
5538 {srai.|srawi.} %3,%1,%h2
5539 #
5540 #"
5541 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5542 (set_attr "length" "4,4,8,8")])
5544 (define_split
5545 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5546 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5547 (match_operand:SI 2 "reg_or_cint_operand" ""))
5548 (const_int 0)))
5549 (clobber (match_scratch:SI 3 ""))]
5550 "! TARGET_POWER && reload_completed"
5551 [(set (match_dup 3)
5552 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5553 (set (match_dup 0)
5554 (compare:CC (match_dup 3)
5555 (const_int 0)))]
5556 "")
5558 (define_insn ""
5559 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5560 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5561 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5562 (const_int 0)))
5563 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5564 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5565 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5566 "TARGET_POWER"
5567 "@
5568 srea. %0,%1,%2
5569 {srai.|srawi.} %0,%1,%h2
5570 #
5571 #"
5572 [(set_attr "type" "delayed_compare")
5573 (set_attr "length" "4,4,8,8")])
5575 (define_split
5576 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5577 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5578 (match_operand:SI 2 "reg_or_cint_operand" ""))
5579 (const_int 0)))
5580 (set (match_operand:SI 0 "gpc_reg_operand" "")
5581 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5582 (clobber (match_scratch:SI 4 ""))]
5583 "TARGET_POWER && reload_completed"
5584 [(parallel [(set (match_dup 0)
5585 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5586 (clobber (match_dup 4))])
5587 (set (match_dup 3)
5588 (compare:CC (match_dup 0)
5589 (const_int 0)))]
5590 "")
5592 (define_insn ""
5593 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5594 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5595 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5596 (const_int 0)))
5597 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5598 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5599 "! TARGET_POWER"
5600 "@
5601 {sra.|sraw.} %0,%1,%2
5602 {srai.|srawi.} %0,%1,%h2
5603 #
5604 #"
5605 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5606 (set_attr "length" "4,4,8,8")])
5607 \f
5608 ;; Builtins to replace a division to generate FRE reciprocal estimate
5609 ;; instructions and the necessary fixup instructions
5610 (define_expand "recip<mode>3"
5611 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5612 (match_operand:RECIPF 1 "gpc_reg_operand" "")
5613 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
5614 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
5615 {
5616 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
5617 DONE;
5618 })
5620 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
5621 ;; hardware division. This is only done before register allocation and with
5622 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
5623 (define_split
5624 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
5625 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
5626 (match_operand 2 "gpc_reg_operand" "")))]
5627 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5628 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
5629 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
5630 [(const_int 0)]
5631 {
5632 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
5633 DONE;
5634 })
5636 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5637 ;; appropriate fixup.
5638 (define_expand "rsqrt<mode>2"
5639 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5640 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5641 "RS6000_RECIP_HAVE_RSQRT_P (<MODE>mode)"
5642 {
5643 rs6000_emit_swrsqrt (operands[0], operands[1]);
5644 DONE;
5645 })
5646 \f
5647 (define_split
5648 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5649 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5650 (match_operand:SI 2 "reg_or_cint_operand" ""))
5651 (const_int 0)))
5652 (set (match_operand:SI 0 "gpc_reg_operand" "")
5653 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5654 "! TARGET_POWER && reload_completed"
5655 [(set (match_dup 0)
5656 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5657 (set (match_dup 3)
5658 (compare:CC (match_dup 0)
5659 (const_int 0)))]
5660 "")
5662 ;; Floating-point insns, excluding normal data motion.
5663 ;;
5664 ;; PowerPC has a full set of single-precision floating point instructions.
5665 ;;
5666 ;; For the POWER architecture, we pretend that we have both SFmode and
5667 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5668 ;; The only conversions we will do will be when storing to memory. In that
5669 ;; case, we will use the "frsp" instruction before storing.
5670 ;;
5671 ;; Note that when we store into a single-precision memory location, we need to
5672 ;; use the frsp insn first. If the register being stored isn't dead, we
5673 ;; need a scratch register for the frsp. But this is difficult when the store
5674 ;; is done by reload. It is not incorrect to do the frsp on the register in
5675 ;; this case, we just lose precision that we would have otherwise gotten but
5676 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5678 (define_expand "extendsfdf2"
5679 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5680 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5681 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5682 "")
5684 (define_insn_and_split "*extendsfdf2_fpr"
5685 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5686 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5687 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5688 "@
5689 #
5690 fmr %0,%1
5691 lfs%U1%X1 %0,%1"
5692 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5693 [(const_int 0)]
5694 {
5695 emit_note (NOTE_INSN_DELETED);
5696 DONE;
5697 }
5698 [(set_attr "type" "fp,fp,fpload")])
5700 (define_expand "truncdfsf2"
5701 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5702 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5703 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5704 "")
5706 (define_insn "*truncdfsf2_fpr"
5707 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5708 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5709 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5710 "frsp %0,%1"
5711 [(set_attr "type" "fp")])
5713 (define_insn "aux_truncdfsf2"
5714 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5715 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5716 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5717 "frsp %0,%1"
5718 [(set_attr "type" "fp")])
5720 (define_expand "negsf2"
5721 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5722 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5723 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5724 "")
5726 (define_insn "*negsf2"
5727 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5728 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5729 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5730 "fneg %0,%1"
5731 [(set_attr "type" "fp")])
5733 (define_expand "abssf2"
5734 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5735 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5736 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5737 "")
5739 (define_insn "*abssf2"
5740 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5741 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5742 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5743 "fabs %0,%1"
5744 [(set_attr "type" "fp")])
5746 (define_insn ""
5747 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5748 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5749 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5750 "fnabs %0,%1"
5751 [(set_attr "type" "fp")])
5753 (define_expand "addsf3"
5754 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5755 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5756 (match_operand:SF 2 "gpc_reg_operand" "")))]
5757 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5758 "")
5760 (define_insn ""
5761 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5762 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5763 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5764 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5765 "fadds %0,%1,%2"
5766 [(set_attr "type" "fp")
5767 (set_attr "fp_type" "fp_addsub_s")])
5769 (define_insn ""
5770 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5771 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5772 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5773 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5774 "{fa|fadd} %0,%1,%2"
5775 [(set_attr "type" "fp")])
5777 (define_expand "subsf3"
5778 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5779 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5780 (match_operand:SF 2 "gpc_reg_operand" "")))]
5781 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5782 "")
5784 (define_insn ""
5785 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5786 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5787 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5788 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5789 "fsubs %0,%1,%2"
5790 [(set_attr "type" "fp")
5791 (set_attr "fp_type" "fp_addsub_s")])
5793 (define_insn ""
5794 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5795 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5796 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5797 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5798 "{fs|fsub} %0,%1,%2"
5799 [(set_attr "type" "fp")])
5801 (define_expand "mulsf3"
5802 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5803 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5804 (match_operand:SF 2 "gpc_reg_operand" "")))]
5805 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5806 "")
5808 (define_insn ""
5809 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5810 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5811 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5812 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5813 "fmuls %0,%1,%2"
5814 [(set_attr "type" "fp")
5815 (set_attr "fp_type" "fp_mul_s")])
5817 (define_insn ""
5818 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5819 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5820 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5821 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5822 "{fm|fmul} %0,%1,%2"
5823 [(set_attr "type" "dmul")])
5825 (define_expand "divsf3"
5826 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5827 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5828 (match_operand:SF 2 "gpc_reg_operand" "")))]
5829 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5830 "")
5832 (define_insn ""
5833 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5834 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5835 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5836 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5837 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5838 "fdivs %0,%1,%2"
5839 [(set_attr "type" "sdiv")])
5841 (define_insn ""
5842 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5843 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5844 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5845 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5846 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5847 "{fd|fdiv} %0,%1,%2"
5848 [(set_attr "type" "ddiv")])
5850 (define_insn "fres"
5851 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5852 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5853 "TARGET_FRES"
5854 "fres %0,%1"
5855 [(set_attr "type" "fp")])
5857 ; builtin fmaf support
5858 (define_insn "*fmasf4_fpr"
5859 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5860 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5861 (match_operand:SF 2 "gpc_reg_operand" "f")
5862 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5863 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5864 {
5865 return (TARGET_POWERPC
5866 ? "fmadds %0,%1,%2,%3"
5867 : "{fma|fmadd} %0,%1,%2,%3");
5868 }
5869 [(set_attr "type" "fp")
5870 (set_attr "fp_type" "fp_maddsub_s")])
5872 (define_insn "*fmssf4_fpr"
5873 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5874 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5875 (match_operand:SF 2 "gpc_reg_operand" "f")
5876 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5877 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5878 {
5879 return (TARGET_POWERPC
5880 ? "fmsubs %0,%1,%2,%3"
5881 : "{fms|fmsub} %0,%1,%2,%3");
5882 }
5883 [(set_attr "type" "fp")
5884 (set_attr "fp_type" "fp_maddsub_s")])
5886 (define_insn "*nfmasf4_fpr"
5887 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5888 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5889 (match_operand:SF 2 "gpc_reg_operand" "f")
5890 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5891 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5892 {
5893 return (TARGET_POWERPC
5894 ? "fnmadds %0,%1,%2,%3"
5895 : "{fnma|fnmadd} %0,%1,%2,%3");
5896 }
5897 [(set_attr "type" "fp")
5898 (set_attr "fp_type" "fp_maddsub_s")])
5900 (define_insn "*nfmssf4_fpr"
5901 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5902 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5903 (match_operand:SF 2 "gpc_reg_operand" "f")
5904 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
5905 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5906 {
5907 return (TARGET_POWERPC
5908 ? "fnmsubs %0,%1,%2,%3"
5909 : "{fnms|fnmsub} %0,%1,%2,%3");
5910 }
5911 [(set_attr "type" "fp")
5912 (set_attr "fp_type" "fp_maddsub_s")])
5914 (define_expand "sqrtsf2"
5915 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5916 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5917 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5918 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5919 && !TARGET_SIMPLE_FPU"
5920 "")
5922 (define_insn ""
5923 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5924 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5925 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5926 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5927 "fsqrts %0,%1"
5928 [(set_attr "type" "ssqrt")])
5930 (define_insn ""
5931 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5932 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5933 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5934 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5935 "fsqrt %0,%1"
5936 [(set_attr "type" "dsqrt")])
5938 (define_insn "*rsqrtsf_internal1"
5939 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5940 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5941 UNSPEC_RSQRT))]
5942 "TARGET_FRSQRTES"
5943 "frsqrtes %0,%1"
5944 [(set_attr "type" "fp")])
5946 (define_expand "copysign<mode>3"
5947 [(set (match_dup 3)
5948 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5949 (set (match_dup 4)
5950 (neg:SFDF (abs:SFDF (match_dup 1))))
5951 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5952 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5953 (match_dup 5))
5954 (match_dup 3)
5955 (match_dup 4)))]
5956 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5957 && ((TARGET_PPC_GFXOPT
5958 && !HONOR_NANS (<MODE>mode)
5959 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5960 || TARGET_CMPB
5961 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5962 {
5963 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5964 {
5965 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5966 operands[2]));
5967 DONE;
5968 }
5970 operands[3] = gen_reg_rtx (<MODE>mode);
5971 operands[4] = gen_reg_rtx (<MODE>mode);
5972 operands[5] = CONST0_RTX (<MODE>mode);
5973 })
5975 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5976 ;; compiler from optimizing -0.0
5977 (define_insn "copysign<mode>3_fcpsgn"
5978 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5979 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
5980 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
5981 UNSPEC_COPYSIGN))]
5982 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5983 "fcpsgn %0,%2,%1"
5984 [(set_attr "type" "fp")])
5986 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5987 ;; fsel instruction and some auxiliary computations. Then we just have a
5988 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5989 ;; combine.
5990 (define_expand "smaxsf3"
5991 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5992 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5993 (match_operand:SF 2 "gpc_reg_operand" ""))
5994 (match_dup 1)
5995 (match_dup 2)))]
5996 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5997 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5998 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6000 (define_expand "sminsf3"
6001 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6002 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6003 (match_operand:SF 2 "gpc_reg_operand" ""))
6004 (match_dup 2)
6005 (match_dup 1)))]
6006 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6007 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6008 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6010 (define_split
6011 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6012 (match_operator:SF 3 "min_max_operator"
6013 [(match_operand:SF 1 "gpc_reg_operand" "")
6014 (match_operand:SF 2 "gpc_reg_operand" "")]))]
6015 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6016 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6017 [(const_int 0)]
6018 "
6019 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6020 operands[1], operands[2]);
6021 DONE;
6022 }")
6024 (define_expand "mov<mode>cc"
6025 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
6026 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6027 (match_operand:GPR 2 "gpc_reg_operand" "")
6028 (match_operand:GPR 3 "gpc_reg_operand" "")))]
6029 "TARGET_ISEL<sel>"
6030 "
6031 {
6032 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6033 DONE;
6034 else
6035 FAIL;
6036 }")
6038 ;; We use the BASE_REGS for the isel input operands because, if rA is
6039 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
6040 ;; because we may switch the operands and rB may end up being rA.
6041 ;;
6042 ;; We need 2 patterns: an unsigned and a signed pattern. We could
6043 ;; leave out the mode in operand 4 and use one pattern, but reload can
6044 ;; change the mode underneath our feet and then gets confused trying
6045 ;; to reload the value.
6046 (define_insn "isel_signed_<mode>"
6047 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
6048 (if_then_else:GPR
6049 (match_operator 1 "scc_comparison_operator"
6050 [(match_operand:CC 4 "cc_reg_operand" "y,y")
6051 (const_int 0)])
6052 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
6053 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
6054 "TARGET_ISEL<sel>"
6055 "*
6056 { return output_isel (operands); }"
6057 [(set_attr "type" "isel")
6058 (set_attr "length" "4")])
6060 (define_insn "isel_unsigned_<mode>"
6061 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
6062 (if_then_else:GPR
6063 (match_operator 1 "scc_comparison_operator"
6064 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
6065 (const_int 0)])
6066 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
6067 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
6068 "TARGET_ISEL<sel>"
6069 "*
6070 { return output_isel (operands); }"
6071 [(set_attr "type" "isel")
6072 (set_attr "length" "4")])
6074 ;; These patterns can be useful for combine; they let combine know that
6075 ;; isel can handle reversed comparisons so long as the operands are
6076 ;; registers.
6078 (define_insn "*isel_reversed_signed_<mode>"
6079 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6080 (if_then_else:GPR
6081 (match_operator 1 "scc_rev_comparison_operator"
6082 [(match_operand:CC 4 "cc_reg_operand" "y")
6083 (const_int 0)])
6084 (match_operand:GPR 2 "gpc_reg_operand" "b")
6085 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6086 "TARGET_ISEL<sel>"
6087 "*
6088 { return output_isel (operands); }"
6089 [(set_attr "type" "isel")
6090 (set_attr "length" "4")])
6092 (define_insn "*isel_reversed_unsigned_<mode>"
6093 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6094 (if_then_else:GPR
6095 (match_operator 1 "scc_rev_comparison_operator"
6096 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
6097 (const_int 0)])
6098 (match_operand:GPR 2 "gpc_reg_operand" "b")
6099 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6100 "TARGET_ISEL<sel>"
6101 "*
6102 { return output_isel (operands); }"
6103 [(set_attr "type" "isel")
6104 (set_attr "length" "4")])
6106 (define_expand "movsfcc"
6107 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6108 (if_then_else:SF (match_operand 1 "comparison_operator" "")
6109 (match_operand:SF 2 "gpc_reg_operand" "")
6110 (match_operand:SF 3 "gpc_reg_operand" "")))]
6111 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6112 "
6113 {
6114 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6115 DONE;
6116 else
6117 FAIL;
6118 }")
6120 (define_insn "*fselsfsf4"
6121 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6122 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6123 (match_operand:SF 4 "zero_fp_constant" "F"))
6124 (match_operand:SF 2 "gpc_reg_operand" "f")
6125 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6126 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6127 "fsel %0,%1,%2,%3"
6128 [(set_attr "type" "fp")])
6130 (define_insn "*fseldfsf4"
6131 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6132 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6133 (match_operand:DF 4 "zero_fp_constant" "F"))
6134 (match_operand:SF 2 "gpc_reg_operand" "f")
6135 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6136 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6137 "fsel %0,%1,%2,%3"
6138 [(set_attr "type" "fp")])
6140 (define_expand "negdf2"
6141 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6142 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6143 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6144 "")
6146 (define_insn "*negdf2_fpr"
6147 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6148 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6149 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6150 && !VECTOR_UNIT_VSX_P (DFmode)"
6151 "fneg %0,%1"
6152 [(set_attr "type" "fp")])
6154 (define_expand "absdf2"
6155 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6156 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6157 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6158 "")
6160 (define_insn "*absdf2_fpr"
6161 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6162 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6163 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6164 && !VECTOR_UNIT_VSX_P (DFmode)"
6165 "fabs %0,%1"
6166 [(set_attr "type" "fp")])
6168 (define_insn "*nabsdf2_fpr"
6169 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6170 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6171 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6172 && !VECTOR_UNIT_VSX_P (DFmode)"
6173 "fnabs %0,%1"
6174 [(set_attr "type" "fp")])
6176 (define_expand "adddf3"
6177 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6178 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6179 (match_operand:DF 2 "gpc_reg_operand" "")))]
6180 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6181 "")
6183 (define_insn "*adddf3_fpr"
6184 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6185 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6186 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6187 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6188 && !VECTOR_UNIT_VSX_P (DFmode)"
6189 "{fa|fadd} %0,%1,%2"
6190 [(set_attr "type" "fp")
6191 (set_attr "fp_type" "fp_addsub_d")])
6193 (define_expand "subdf3"
6194 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6195 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6196 (match_operand:DF 2 "gpc_reg_operand" "")))]
6197 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6198 "")
6200 (define_insn "*subdf3_fpr"
6201 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6202 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6203 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6204 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6205 && !VECTOR_UNIT_VSX_P (DFmode)"
6206 "{fs|fsub} %0,%1,%2"
6207 [(set_attr "type" "fp")
6208 (set_attr "fp_type" "fp_addsub_d")])
6210 (define_expand "muldf3"
6211 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6212 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
6213 (match_operand:DF 2 "gpc_reg_operand" "")))]
6214 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6215 "")
6217 (define_insn "*muldf3_fpr"
6218 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6219 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6220 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6221 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6222 && !VECTOR_UNIT_VSX_P (DFmode)"
6223 "{fm|fmul} %0,%1,%2"
6224 [(set_attr "type" "dmul")
6225 (set_attr "fp_type" "fp_mul_d")])
6227 (define_expand "divdf3"
6228 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6229 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
6230 (match_operand:DF 2 "gpc_reg_operand" "")))]
6231 "TARGET_HARD_FLOAT
6232 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
6233 && !TARGET_SIMPLE_FPU"
6234 "")
6236 (define_insn "*divdf3_fpr"
6237 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6238 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6239 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6240 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
6241 && !VECTOR_UNIT_VSX_P (DFmode)"
6242 "{fd|fdiv} %0,%1,%2"
6243 [(set_attr "type" "ddiv")])
6245 (define_insn "*fred_fpr"
6246 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6247 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
6248 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
6249 "fre %0,%1"
6250 [(set_attr "type" "fp")])
6252 (define_insn "*rsqrtdf_internal1"
6253 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6254 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
6255 UNSPEC_RSQRT))]
6256 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
6257 "frsqrte %0,%1"
6258 [(set_attr "type" "fp")])
6260 ; builtin fma support
6261 (define_insn "*fmadf4_fpr"
6262 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6263 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6264 (match_operand:DF 2 "gpc_reg_operand" "f")
6265 (match_operand:DF 3 "gpc_reg_operand" "f")))]
6266 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6267 && VECTOR_UNIT_NONE_P (DFmode)"
6268 "{fma|fmadd} %0,%1,%2,%3"
6269 [(set_attr "type" "fp")
6270 (set_attr "fp_type" "fp_maddsub_s")])
6272 (define_insn "*fmsdf4_fpr"
6273 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6274 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6275 (match_operand:DF 2 "gpc_reg_operand" "f")
6276 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
6277 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6278 && VECTOR_UNIT_NONE_P (DFmode)"
6279 "{fms|fmsub} %0,%1,%2,%3"
6280 [(set_attr "type" "fp")
6281 (set_attr "fp_type" "fp_maddsub_s")])
6283 (define_insn "*nfmadf4_fpr"
6284 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6285 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6286 (match_operand:DF 2 "gpc_reg_operand" "f")
6287 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
6288 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6289 && VECTOR_UNIT_NONE_P (DFmode)"
6290 "{fnma|fnmadd} %0,%1,%2,%3"
6291 [(set_attr "type" "fp")
6292 (set_attr "fp_type" "fp_maddsub_s")])
6294 (define_insn "*nfmsdf4_fpr"
6295 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6296 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6297 (match_operand:DF 2 "gpc_reg_operand" "f")
6298 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
6299 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6300 && VECTOR_UNIT_NONE_P (DFmode)"
6301 "{fnms|fnmsub} %0,%1,%2,%3"
6302 [(set_attr "type" "fp")
6303 (set_attr "fp_type" "fp_maddsub_s")])
6305 (define_expand "sqrtdf2"
6306 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6307 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6308 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6309 && TARGET_DOUBLE_FLOAT"
6310 "")
6312 (define_insn "*sqrtdf2_fpr"
6313 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6314 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6315 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6316 && TARGET_DOUBLE_FLOAT
6317 && !VECTOR_UNIT_VSX_P (DFmode)"
6318 "fsqrt %0,%1"
6319 [(set_attr "type" "dsqrt")])
6321 ;; The conditional move instructions allow us to perform max and min
6322 ;; operations even when
6324 (define_expand "smaxdf3"
6325 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6326 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6327 (match_operand:DF 2 "gpc_reg_operand" ""))
6328 (match_dup 1)
6329 (match_dup 2)))]
6330 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6331 && !flag_trapping_math"
6332 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6334 (define_expand "smindf3"
6335 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6336 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6337 (match_operand:DF 2 "gpc_reg_operand" ""))
6338 (match_dup 2)
6339 (match_dup 1)))]
6340 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6341 && !flag_trapping_math"
6342 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6344 (define_split
6345 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6346 (match_operator:DF 3 "min_max_operator"
6347 [(match_operand:DF 1 "gpc_reg_operand" "")
6348 (match_operand:DF 2 "gpc_reg_operand" "")]))]
6349 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6350 && !flag_trapping_math"
6351 [(const_int 0)]
6352 "
6353 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6354 operands[1], operands[2]);
6355 DONE;
6356 }")
6358 (define_expand "movdfcc"
6359 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6360 (if_then_else:DF (match_operand 1 "comparison_operator" "")
6361 (match_operand:DF 2 "gpc_reg_operand" "")
6362 (match_operand:DF 3 "gpc_reg_operand" "")))]
6363 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6364 "
6365 {
6366 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6367 DONE;
6368 else
6369 FAIL;
6370 }")
6372 (define_insn "*fseldfdf4"
6373 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6374 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6375 (match_operand:DF 4 "zero_fp_constant" "F"))
6376 (match_operand:DF 2 "gpc_reg_operand" "d")
6377 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6378 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6379 "fsel %0,%1,%2,%3"
6380 [(set_attr "type" "fp")])
6382 (define_insn "*fselsfdf4"
6383 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6384 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6385 (match_operand:SF 4 "zero_fp_constant" "F"))
6386 (match_operand:DF 2 "gpc_reg_operand" "d")
6387 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6388 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6389 "fsel %0,%1,%2,%3"
6390 [(set_attr "type" "fp")])
6391 \f
6392 ;; Conversions to and from floating-point.
6394 ; We don't define lfiwax/lfiwzx with the normal definition, because we
6395 ; don't want to support putting SImode in FPR registers.
6396 (define_insn "lfiwax"
6397 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6398 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
6399 UNSPEC_LFIWAX))]
6400 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
6401 "lfiwax %0,%y1"
6402 [(set_attr "type" "fpload")])
6404 ; This split must be run before register allocation because it allocates the
6405 ; memory slot that is needed to move values to/from the FPR. We don't allocate
6406 ; it earlier to allow for the combiner to merge insns together where it might
6407 ; not be needed and also in case the insns are deleted as dead code.
6409 (define_insn_and_split "floatsi<mode>2_lfiwax"
6410 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6411 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
6412 (clobber (match_scratch:DI 2 "=d"))]
6413 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
6414 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
6415 "#"
6416 ""
6417 [(pc)]
6418 "
6419 {
6420 rtx dest = operands[0];
6421 rtx src = operands[1];
6422 rtx tmp;
6424 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
6425 tmp = convert_to_mode (DImode, src, false);
6426 else
6427 {
6428 tmp = operands[2];
6429 if (GET_CODE (tmp) == SCRATCH)
6430 tmp = gen_reg_rtx (DImode);
6431 if (MEM_P (src))
6432 {
6433 src = rs6000_address_for_fpconvert (src);
6434 emit_insn (gen_lfiwax (tmp, src));
6435 }
6436 else
6437 {
6438 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6439 emit_move_insn (stack, src);
6440 emit_insn (gen_lfiwax (tmp, stack));
6441 }
6442 }
6443 emit_insn (gen_floatdi<mode>2 (dest, tmp));
6444 DONE;
6445 }"
6446 [(set_attr "length" "12")
6447 (set_attr "type" "fpload")])
6449 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
6450 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
6451 (float:SFDF
6452 (sign_extend:DI
6453 (match_operand:SI 1 "memory_operand" "Z,Z"))))
6454 (clobber (match_scratch:DI 2 "=0,d"))]
6455 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
6456 && <SI_CONVERT_FP>"
6457 "#"
6458 ""
6459 [(pc)]
6460 "
6461 {
6462 operands[1] = rs6000_address_for_fpconvert (operands[1]);
6463 if (GET_CODE (operands[2]) == SCRATCH)
6464 operands[2] = gen_reg_rtx (DImode);
6465 emit_insn (gen_lfiwax (operands[2], operands[1]));
6466 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
6467 DONE;
6468 }"
6469 [(set_attr "length" "8")
6470 (set_attr "type" "fpload")])
6472 (define_insn "lfiwzx"
6473 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6474 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
6475 UNSPEC_LFIWZX))]
6476 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
6477 "lfiwzx %0,%y1"
6478 [(set_attr "type" "fpload")])
6480 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
6481 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6482 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
6483 (clobber (match_scratch:DI 2 "=d"))]
6484 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
6485 && <SI_CONVERT_FP>"
6486 "#"
6487 ""
6488 [(pc)]
6489 "
6490 {
6491 rtx dest = operands[0];
6492 rtx src = operands[1];
6493 rtx tmp;
6495 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
6496 tmp = convert_to_mode (DImode, src, true);
6497 else
6498 {
6499 tmp = operands[2];
6500 if (GET_CODE (tmp) == SCRATCH)
6501 tmp = gen_reg_rtx (DImode);
6502 if (MEM_P (src))
6503 {
6504 src = rs6000_address_for_fpconvert (src);
6505 emit_insn (gen_lfiwzx (tmp, src));
6506 }
6507 else
6508 {
6509 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6510 emit_move_insn (stack, src);
6511 emit_insn (gen_lfiwzx (tmp, stack));
6512 }
6513 }
6514 emit_insn (gen_floatdi<mode>2 (dest, tmp));
6515 DONE;
6516 }"
6517 [(set_attr "length" "12")
6518 (set_attr "type" "fpload")])
6520 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
6521 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
6522 (unsigned_float:SFDF
6523 (zero_extend:DI
6524 (match_operand:SI 1 "memory_operand" "Z,Z"))))
6525 (clobber (match_scratch:DI 2 "=0,d"))]
6526 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
6527 && <SI_CONVERT_FP>"
6528 "#"
6529 ""
6530 [(pc)]
6531 "
6532 {
6533 operands[1] = rs6000_address_for_fpconvert (operands[1]);
6534 if (GET_CODE (operands[2]) == SCRATCH)
6535 operands[2] = gen_reg_rtx (DImode);
6536 emit_insn (gen_lfiwzx (operands[2], operands[1]));
6537 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
6538 DONE;
6539 }"
6540 [(set_attr "length" "8")
6541 (set_attr "type" "fpload")])
6543 ; For each of these conversions, there is a define_expand, a define_insn
6544 ; with a '#' template, and a define_split (with C code). The idea is
6545 ; to allow constant folding with the template of the define_insn,
6546 ; then to have the insns split later (between sched1 and final).
6548 (define_expand "floatsidf2"
6549 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6550 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
6551 (use (match_dup 2))
6552 (use (match_dup 3))
6553 (clobber (match_dup 4))
6554 (clobber (match_dup 5))
6555 (clobber (match_dup 6))])]
6556 "TARGET_HARD_FLOAT
6557 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6558 "
6559 {
6560 if (TARGET_E500_DOUBLE)
6561 {
6562 if (!REG_P (operands[1]))
6563 operands[1] = force_reg (SImode, operands[1]);
6564 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
6565 DONE;
6566 }
6567 else if (TARGET_LFIWAX && TARGET_FCFID)
6568 {
6569 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
6570 DONE;
6571 }
6572 else if (TARGET_FCFID)
6573 {
6574 rtx dreg = operands[1];
6575 if (!REG_P (dreg))
6576 dreg = force_reg (SImode, dreg);
6577 dreg = convert_to_mode (DImode, dreg, false);
6578 emit_insn (gen_floatdidf2 (operands[0], dreg));
6579 DONE;
6580 }
6582 if (!REG_P (operands[1]))
6583 operands[1] = force_reg (SImode, operands[1]);
6584 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6585 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
6586 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
6587 operands[5] = gen_reg_rtx (DFmode);
6588 operands[6] = gen_reg_rtx (SImode);
6589 }")
6591 (define_insn_and_split "*floatsidf2_internal"
6592 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6593 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6594 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6595 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6596 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6597 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6598 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
6599 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6600 "#"
6601 ""
6602 [(pc)]
6603 "
6604 {
6605 rtx lowword, highword;
6606 gcc_assert (MEM_P (operands[4]));
6607 highword = adjust_address (operands[4], SImode, 0);
6608 lowword = adjust_address (operands[4], SImode, 4);
6609 if (! WORDS_BIG_ENDIAN)
6610 {
6611 rtx tmp;
6612 tmp = highword; highword = lowword; lowword = tmp;
6613 }
6615 emit_insn (gen_xorsi3 (operands[6], operands[1],
6616 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
6617 emit_move_insn (lowword, operands[6]);
6618 emit_move_insn (highword, operands[2]);
6619 emit_move_insn (operands[5], operands[4]);
6620 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6621 DONE;
6622 }"
6623 [(set_attr "length" "24")
6624 (set_attr "type" "fp")])
6626 ;; If we don't have a direct conversion to single precision, don't enable this
6627 ;; conversion for 32-bit without fast math, because we don't have the insn to
6628 ;; generate the fixup swizzle to avoid double rounding problems.
6629 (define_expand "floatunssisf2"
6630 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6631 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6632 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6633 && (!TARGET_FPRS
6634 || (TARGET_FPRS
6635 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
6636 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6637 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6638 "
6639 {
6640 if (!TARGET_FPRS)
6641 {
6642 if (!REG_P (operands[1]))
6643 operands[1] = force_reg (SImode, operands[1]);
6644 }
6645 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
6646 {
6647 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
6648 DONE;
6649 }
6650 else
6651 {
6652 rtx dreg = operands[1];
6653 if (!REG_P (dreg))
6654 dreg = force_reg (SImode, dreg);
6655 dreg = convert_to_mode (DImode, dreg, true);
6656 emit_insn (gen_floatdisf2 (operands[0], dreg));
6657 DONE;
6658 }
6659 }")
6661 (define_expand "floatunssidf2"
6662 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6663 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
6664 (use (match_dup 2))
6665 (use (match_dup 3))
6666 (clobber (match_dup 4))
6667 (clobber (match_dup 5))])]
6668 "TARGET_HARD_FLOAT
6669 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6670 "
6671 {
6672 if (TARGET_E500_DOUBLE)
6673 {
6674 if (!REG_P (operands[1]))
6675 operands[1] = force_reg (SImode, operands[1]);
6676 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6677 DONE;
6678 }
6679 else if (TARGET_LFIWZX && TARGET_FCFID)
6680 {
6681 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
6682 DONE;
6683 }
6684 else if (TARGET_FCFID)
6685 {
6686 rtx dreg = operands[1];
6687 if (!REG_P (dreg))
6688 dreg = force_reg (SImode, dreg);
6689 dreg = convert_to_mode (DImode, dreg, true);
6690 emit_insn (gen_floatdidf2 (operands[0], dreg));
6691 DONE;
6692 }
6694 if (!REG_P (operands[1]))
6695 operands[1] = force_reg (SImode, operands[1]);
6696 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6697 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6698 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
6699 operands[5] = gen_reg_rtx (DFmode);
6700 }")
6702 (define_insn_and_split "*floatunssidf2_internal"
6703 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6704 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6705 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6706 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6707 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6708 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6709 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6710 && !(TARGET_FCFID && TARGET_POWERPC64)"
6711 "#"
6712 ""
6713 [(pc)]
6714 "
6715 {
6716 rtx lowword, highword;
6717 gcc_assert (MEM_P (operands[4]));
6718 highword = adjust_address (operands[4], SImode, 0);
6719 lowword = adjust_address (operands[4], SImode, 4);
6720 if (! WORDS_BIG_ENDIAN)
6721 {
6722 rtx tmp;
6723 tmp = highword; highword = lowword; lowword = tmp;
6724 }
6726 emit_move_insn (lowword, operands[1]);
6727 emit_move_insn (highword, operands[2]);
6728 emit_move_insn (operands[5], operands[4]);
6729 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6730 DONE;
6731 }"
6732 [(set_attr "length" "20")
6733 (set_attr "type" "fp")])
6735 (define_expand "fix_trunc<mode>si2"
6736 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6737 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6738 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT
6739 && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
6740 "
6741 {
6742 if (!<E500_CONVERT>)
6743 {
6744 rtx tmp, stack;
6746 if (TARGET_STFIWX)
6747 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6748 else
6749 {
6750 tmp = gen_reg_rtx (DImode);
6751 stack = rs6000_allocate_stack_temp (DImode, true, false);
6752 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
6753 tmp, stack));
6754 }
6755 DONE;
6756 }
6757 }")
6759 ; Like the convert to float patterns, this insn must be split before
6760 ; register allocation so that it can allocate the memory slot if it
6761 ; needed
6762 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
6763 [(set (match_operand:SI 0 "general_operand" "=rm")
6764 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6765 (clobber (match_scratch:DI 2 "=d"))]
6766 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6767 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
6768 && TARGET_STFIWX && can_create_pseudo_p ()"
6769 "#"
6770 ""
6771 [(pc)]
6772 {
6773 rtx dest = operands[0];
6774 rtx src = operands[1];
6775 rtx tmp = operands[2];
6777 if (GET_CODE (tmp) == SCRATCH)
6778 tmp = gen_reg_rtx (DImode);
6780 emit_insn (gen_fctiwz_<mode> (tmp, src));
6781 if (MEM_P (dest))
6782 {
6783 dest = rs6000_address_for_fpconvert (dest);
6784 emit_insn (gen_stfiwx (dest, tmp));
6785 DONE;
6786 }
6787 else if (TARGET_MFPGPR && TARGET_POWERPC64)
6788 {
6789 dest = gen_lowpart (DImode, dest);
6790 emit_move_insn (dest, tmp);
6791 DONE;
6792 }
6793 else
6794 {
6795 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6796 emit_insn (gen_stfiwx (stack, tmp));
6797 emit_move_insn (dest, stack);
6798 DONE;
6799 }
6800 }
6801 [(set_attr "length" "12")
6802 (set_attr "type" "fp")])
6804 (define_insn_and_split "fix_trunc<mode>si2_internal"
6805 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
6806 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
6807 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
6808 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
6809 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6810 && TARGET_DOUBLE_FLOAT"
6811 "#"
6812 ""
6813 [(pc)]
6814 "
6815 {
6816 rtx lowword;
6817 gcc_assert (MEM_P (operands[3]));
6818 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6820 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6821 emit_move_insn (operands[3], operands[2]);
6822 emit_move_insn (operands[0], lowword);
6823 DONE;
6824 }"
6825 [(set_attr "length" "16")
6826 (set_attr "type" "fp")])
6828 (define_expand "fix_trunc<mode>di2"
6829 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6830 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6831 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6832 && TARGET_FCFID"
6833 "")
6835 (define_insn "*fix_trunc<mode>di2_fctidz"
6836 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6837 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6838 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6839 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6840 "fctidz %0,%1"
6841 [(set_attr "type" "fp")])
6843 (define_expand "fixuns_trunc<mode>si2"
6844 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6845 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6846 "TARGET_HARD_FLOAT
6847 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6848 || <E500_CONVERT>)"
6849 "
6850 {
6851 if (!<E500_CONVERT>)
6852 {
6853 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6854 DONE;
6855 }
6856 }")
6858 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6859 [(set (match_operand:SI 0 "general_operand" "=rm")
6860 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6861 (clobber (match_scratch:DI 2 "=d"))]
6862 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6863 && TARGET_STFIWX && can_create_pseudo_p ()"
6864 "#"
6865 ""
6866 [(pc)]
6867 {
6868 rtx dest = operands[0];
6869 rtx src = operands[1];
6870 rtx tmp = operands[2];
6872 if (GET_CODE (tmp) == SCRATCH)
6873 tmp = gen_reg_rtx (DImode);
6875 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6876 if (MEM_P (dest))
6877 {
6878 dest = rs6000_address_for_fpconvert (dest);
6879 emit_insn (gen_stfiwx (dest, tmp));
6880 DONE;
6881 }
6882 else if (TARGET_MFPGPR && TARGET_POWERPC64)
6883 {
6884 dest = gen_lowpart (DImode, dest);
6885 emit_move_insn (dest, tmp);
6886 DONE;
6887 }
6888 else
6889 {
6890 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6891 emit_insn (gen_stfiwx (stack, tmp));
6892 emit_move_insn (dest, stack);
6893 DONE;
6894 }
6895 }
6896 [(set_attr "length" "12")
6897 (set_attr "type" "fp")])
6899 (define_expand "fixuns_trunc<mode>di2"
6900 [(set (match_operand:DI 0 "register_operand" "")
6901 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6902 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6903 "")
6905 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6906 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6907 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6908 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6909 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6910 "fctiduz %0,%1"
6911 [(set_attr "type" "fp")])
6913 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6914 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6915 ; because the first makes it clear that operand 0 is not live
6916 ; before the instruction.
6917 (define_insn "fctiwz_<mode>"
6918 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6919 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6920 UNSPEC_FCTIWZ))]
6921 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6922 && TARGET_DOUBLE_FLOAT"
6923 "{fcirz|fctiwz} %0,%1"
6924 [(set_attr "type" "fp")])
6926 (define_insn "fctiwuz_<mode>"
6927 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6928 (unspec:DI [(unsigned_fix:SI
6929 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6930 UNSPEC_FCTIWUZ))]
6931 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6932 "fctiwuz %0,%1"
6933 [(set_attr "type" "fp")])
6935 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6936 ;; since the friz instruction does not truncate the value if the floating
6937 ;; point value is < LONG_MIN or > LONG_MAX.
6938 (define_insn "*friz"
6939 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6940 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6941 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6942 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6943 && !flag_trapping_math && TARGET_FRIZ"
6944 "friz %0,%1"
6945 [(set_attr "type" "fp")])
6947 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6948 ;; load to properly sign extend the value, but at least doing a store, load
6949 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6950 ;; if we have 32-bit memory ops
6951 (define_insn_and_split "*round32<mode>2_fprs"
6952 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6953 (float:SFDF
6954 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6955 (clobber (match_scratch:DI 2 "=d"))
6956 (clobber (match_scratch:DI 3 "=d"))]
6957 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6958 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6959 && can_create_pseudo_p ()"
6960 "#"
6961 ""
6962 [(pc)]
6963 {
6964 rtx dest = operands[0];
6965 rtx src = operands[1];
6966 rtx tmp1 = operands[2];
6967 rtx tmp2 = operands[3];
6968 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6970 if (GET_CODE (tmp1) == SCRATCH)
6971 tmp1 = gen_reg_rtx (DImode);
6972 if (GET_CODE (tmp2) == SCRATCH)
6973 tmp2 = gen_reg_rtx (DImode);
6975 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6976 emit_insn (gen_stfiwx (stack, tmp1));
6977 emit_insn (gen_lfiwax (tmp2, stack));
6978 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6979 DONE;
6980 }
6981 [(set_attr "type" "fpload")
6982 (set_attr "length" "16")])
6984 (define_insn_and_split "*roundu32<mode>2_fprs"
6985 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6986 (unsigned_float:SFDF
6987 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6988 (clobber (match_scratch:DI 2 "=d"))
6989 (clobber (match_scratch:DI 3 "=d"))]
6990 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6991 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
6992 && can_create_pseudo_p ()"
6993 "#"
6994 ""
6995 [(pc)]
6996 {
6997 rtx dest = operands[0];
6998 rtx src = operands[1];
6999 rtx tmp1 = operands[2];
7000 rtx tmp2 = operands[3];
7001 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
7003 if (GET_CODE (tmp1) == SCRATCH)
7004 tmp1 = gen_reg_rtx (DImode);
7005 if (GET_CODE (tmp2) == SCRATCH)
7006 tmp2 = gen_reg_rtx (DImode);
7008 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
7009 emit_insn (gen_stfiwx (stack, tmp1));
7010 emit_insn (gen_lfiwzx (tmp2, stack));
7011 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
7012 DONE;
7013 }
7014 [(set_attr "type" "fpload")
7015 (set_attr "length" "16")])
7017 ;; No VSX equivalent to fctid
7018 (define_insn "lrint<mode>di2"
7019 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
7020 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7021 UNSPEC_FCTID))]
7022 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7023 "fctid %0,%1"
7024 [(set_attr "type" "fp")])
7026 (define_expand "btrunc<mode>2"
7027 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7028 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7029 UNSPEC_FRIZ))]
7030 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7031 "")
7033 (define_insn "*btrunc<mode>2_fpr"
7034 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7035 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7036 UNSPEC_FRIZ))]
7037 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7038 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7039 "friz %0,%1"
7040 [(set_attr "type" "fp")])
7042 (define_expand "ceil<mode>2"
7043 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7044 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7045 UNSPEC_FRIP))]
7046 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7047 "")
7049 (define_insn "*ceil<mode>2_fpr"
7050 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7051 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7052 UNSPEC_FRIP))]
7053 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7054 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7055 "frip %0,%1"
7056 [(set_attr "type" "fp")])
7058 (define_expand "floor<mode>2"
7059 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7060 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7061 UNSPEC_FRIM))]
7062 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7063 "")
7065 (define_insn "*floor<mode>2_fpr"
7066 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7067 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7068 UNSPEC_FRIM))]
7069 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7070 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7071 "frim %0,%1"
7072 [(set_attr "type" "fp")])
7074 ;; No VSX equivalent to frin
7075 (define_insn "round<mode>2"
7076 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7077 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7078 UNSPEC_FRIN))]
7079 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7080 "frin %0,%1"
7081 [(set_attr "type" "fp")])
7083 ; An UNSPEC is used so we don't have to support SImode in FP registers.
7084 (define_insn "stfiwx"
7085 [(set (match_operand:SI 0 "memory_operand" "=Z")
7086 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
7087 UNSPEC_STFIWX))]
7088 "TARGET_PPC_GFXOPT"
7089 "stfiwx %1,%y0"
7090 [(set_attr "type" "fpstore")])
7092 ;; If we don't have a direct conversion to single precision, don't enable this
7093 ;; conversion for 32-bit without fast math, because we don't have the insn to
7094 ;; generate the fixup swizzle to avoid double rounding problems.
7095 (define_expand "floatsisf2"
7096 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7097 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
7098 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
7099 && (!TARGET_FPRS
7100 || (TARGET_FPRS
7101 && ((TARGET_FCFIDS && TARGET_LFIWAX)
7102 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
7103 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
7104 "
7105 {
7106 if (!TARGET_FPRS)
7107 {
7108 if (!REG_P (operands[1]))
7109 operands[1] = force_reg (SImode, operands[1]);
7110 }
7111 else if (TARGET_FCFIDS && TARGET_LFIWAX)
7112 {
7113 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
7114 DONE;
7115 }
7116 else if (TARGET_FCFID && TARGET_LFIWAX)
7117 {
7118 rtx dfreg = gen_reg_rtx (DFmode);
7119 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
7120 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
7121 DONE;
7122 }
7123 else
7124 {
7125 rtx dreg = operands[1];
7126 if (!REG_P (dreg))
7127 dreg = force_reg (SImode, dreg);
7128 dreg = convert_to_mode (DImode, dreg, false);
7129 emit_insn (gen_floatdisf2 (operands[0], dreg));
7130 DONE;
7131 }
7132 }")
7134 (define_expand "floatdidf2"
7135 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7136 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
7137 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
7138 "")
7140 (define_insn "*floatdidf2_fpr"
7141 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7142 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7143 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
7144 && !VECTOR_UNIT_VSX_P (DFmode)"
7145 "fcfid %0,%1"
7146 [(set_attr "type" "fp")])
7148 ; Allow the combiner to merge source memory operands to the conversion so that
7149 ; the optimizer/register allocator doesn't try to load the value too early in a
7150 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
7151 ; hit. We will split after reload to avoid the trip through the GPRs
7153 (define_insn_and_split "*floatdidf2_mem"
7154 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7155 (float:DF (match_operand:DI 1 "memory_operand" "m")))
7156 (clobber (match_scratch:DI 2 "=d"))]
7157 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
7158 "#"
7159 "&& reload_completed"
7160 [(set (match_dup 2) (match_dup 1))
7161 (set (match_dup 0) (float:DF (match_dup 2)))]
7162 ""
7163 [(set_attr "length" "8")
7164 (set_attr "type" "fpload")])
7166 (define_expand "floatunsdidf2"
7167 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7168 (unsigned_float:DF
7169 (match_operand:DI 1 "gpc_reg_operand" "")))]
7170 "TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode)"
7171 "")
7173 (define_insn "*floatunsdidf2_fcfidu"
7174 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7175 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7176 "TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
7177 "fcfidu %0,%1"
7178 [(set_attr "type" "fp")
7179 (set_attr "length" "4")])
7181 (define_insn_and_split "*floatunsdidf2_mem"
7182 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7183 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
7184 (clobber (match_scratch:DI 2 "=d"))]
7185 "TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode)"
7186 "#"
7187 "&& reload_completed"
7188 [(set (match_dup 2) (match_dup 1))
7189 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
7190 ""
7191 [(set_attr "length" "8")
7192 (set_attr "type" "fpload")])
7194 (define_expand "floatdisf2"
7195 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7196 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
7197 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7198 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
7199 "
7200 {
7201 if (!TARGET_FCFIDS)
7202 {
7203 rtx val = operands[1];
7204 if (!flag_unsafe_math_optimizations)
7205 {
7206 rtx label = gen_label_rtx ();
7207 val = gen_reg_rtx (DImode);
7208 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
7209 emit_label (label);
7210 }
7211 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
7212 DONE;
7213 }
7214 }")
7216 (define_insn "floatdisf2_fcfids"
7217 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7218 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7219 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7220 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
7221 "fcfids %0,%1"
7222 [(set_attr "type" "fp")])
7224 (define_insn_and_split "*floatdisf2_mem"
7225 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7226 (float:SF (match_operand:DI 1 "memory_operand" "m")))
7227 (clobber (match_scratch:DI 2 "=f"))]
7228 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7229 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
7230 "#"
7231 "&& reload_completed"
7232 [(pc)]
7233 "
7234 {
7235 emit_move_insn (operands[2], operands[1]);
7236 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
7237 DONE;
7238 }"
7239 [(set_attr "length" "8")])
7241 ;; This is not IEEE compliant if rounding mode is "round to nearest".
7242 ;; If the DI->DF conversion is inexact, then it's possible to suffer
7243 ;; from double rounding.
7244 ;; Instead of creating a new cpu type for two FP operations, just use fp
7245 (define_insn_and_split "floatdisf2_internal1"
7246 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7247 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
7248 (clobber (match_scratch:DF 2 "=d"))]
7249 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
7250 "#"
7251 "&& reload_completed"
7252 [(set (match_dup 2)
7253 (float:DF (match_dup 1)))
7254 (set (match_dup 0)
7255 (float_truncate:SF (match_dup 2)))]
7256 ""
7257 [(set_attr "length" "8")
7258 (set_attr "type" "fp")])
7260 ;; Twiddles bits to avoid double rounding.
7261 ;; Bits that might be truncated when converting to DFmode are replaced
7262 ;; by a bit that won't be lost at that stage, but is below the SFmode
7263 ;; rounding position.
7264 (define_expand "floatdisf2_internal2"
7265 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
7266 (const_int 53)))
7267 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
7268 (const_int 2047)))
7269 (clobber (scratch:CC))])
7270 (set (match_dup 3) (plus:DI (match_dup 3)
7271 (const_int 1)))
7272 (set (match_dup 0) (plus:DI (match_dup 0)
7273 (const_int 2047)))
7274 (set (match_dup 4) (compare:CCUNS (match_dup 3)
7275 (const_int 2)))
7276 (set (match_dup 0) (ior:DI (match_dup 0)
7277 (match_dup 1)))
7278 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
7279 (const_int -2048)))
7280 (clobber (scratch:CC))])
7281 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
7282 (label_ref (match_operand:DI 2 "" ""))
7283 (pc)))
7284 (set (match_dup 0) (match_dup 1))]
7285 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
7286 "
7287 {
7288 operands[3] = gen_reg_rtx (DImode);
7289 operands[4] = gen_reg_rtx (CCUNSmode);
7290 }")
7292 (define_expand "floatunsdisf2"
7293 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7294 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
7295 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7296 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7297 "")
7299 (define_insn "floatunsdisf2_fcfidus"
7300 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7301 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7302 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7303 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7304 "fcfidus %0,%1"
7305 [(set_attr "type" "fp")])
7307 (define_insn_and_split "*floatunsdisf2_mem"
7308 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7309 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
7310 (clobber (match_scratch:DI 2 "=f"))]
7311 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7312 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7313 "#"
7314 "&& reload_completed"
7315 [(pc)]
7316 "
7317 {
7318 emit_move_insn (operands[2], operands[1]);
7319 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
7320 DONE;
7321 }"
7322 [(set_attr "length" "8")
7323 (set_attr "type" "fpload")])
7324 \f
7325 ;; Define the DImode operations that can be done in a small number
7326 ;; of instructions. The & constraints are to prevent the register
7327 ;; allocator from allocating registers that overlap with the inputs
7328 ;; (for example, having an input in 7,8 and an output in 6,7). We
7329 ;; also allow for the output being the same as one of the inputs.
7331 (define_insn "*adddi3_noppc64"
7332 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
7333 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
7334 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
7335 "! TARGET_POWERPC64"
7336 "*
7337 {
7338 if (WORDS_BIG_ENDIAN)
7339 return (GET_CODE (operands[2])) != CONST_INT
7340 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
7341 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
7342 else
7343 return (GET_CODE (operands[2])) != CONST_INT
7344 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
7345 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
7346 }"
7347 [(set_attr "type" "two")
7348 (set_attr "length" "8")])
7350 (define_insn "*subdi3_noppc64"
7351 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
7352 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
7353 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
7354 "! TARGET_POWERPC64"
7355 "*
7356 {
7357 if (WORDS_BIG_ENDIAN)
7358 return (GET_CODE (operands[1]) != CONST_INT)
7359 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
7360 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
7361 else
7362 return (GET_CODE (operands[1]) != CONST_INT)
7363 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
7364 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
7365 }"
7366 [(set_attr "type" "two")
7367 (set_attr "length" "8")])
7369 (define_insn "*negdi2_noppc64"
7370 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7371 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
7372 "! TARGET_POWERPC64"
7373 "*
7374 {
7375 return (WORDS_BIG_ENDIAN)
7376 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
7377 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
7378 }"
7379 [(set_attr "type" "two")
7380 (set_attr "length" "8")])
7382 (define_expand "mulsidi3"
7383 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7384 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7385 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7386 "! TARGET_POWERPC64"
7387 "
7388 {
7389 if (! TARGET_POWER && ! TARGET_POWERPC)
7390 {
7391 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7392 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7393 emit_insn (gen_mull_call ());
7394 if (WORDS_BIG_ENDIAN)
7395 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
7396 else
7397 {
7398 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
7399 gen_rtx_REG (SImode, 3));
7400 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
7401 gen_rtx_REG (SImode, 4));
7402 }
7403 DONE;
7404 }
7405 else if (TARGET_POWER)
7406 {
7407 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
7408 DONE;
7409 }
7410 }")
7412 (define_insn "mulsidi3_mq"
7413 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7414 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7415 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7416 (clobber (match_scratch:SI 3 "=q"))]
7417 "TARGET_POWER"
7418 "mul %0,%1,%2\;mfmq %L0"
7419 [(set_attr "type" "imul")
7420 (set_attr "length" "8")])
7422 (define_insn "*mulsidi3_no_mq"
7423 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7424 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7425 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7426 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7427 "*
7428 {
7429 return (WORDS_BIG_ENDIAN)
7430 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
7431 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
7432 }"
7433 [(set_attr "type" "imul")
7434 (set_attr "length" "8")])
7436 (define_split
7437 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7438 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7439 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7440 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7441 [(set (match_dup 3)
7442 (truncate:SI
7443 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
7444 (sign_extend:DI (match_dup 2)))
7445 (const_int 32))))
7446 (set (match_dup 4)
7447 (mult:SI (match_dup 1)
7448 (match_dup 2)))]
7449 "
7450 {
7451 int endian = (WORDS_BIG_ENDIAN == 0);
7452 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7453 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7454 }")
7456 (define_expand "umulsidi3"
7457 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7458 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7459 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7460 "TARGET_POWERPC && ! TARGET_POWERPC64"
7461 "
7462 {
7463 if (TARGET_POWER)
7464 {
7465 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
7466 DONE;
7467 }
7468 }")
7470 (define_insn "umulsidi3_mq"
7471 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7472 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7473 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7474 (clobber (match_scratch:SI 3 "=q"))]
7475 "TARGET_POWERPC && TARGET_POWER"
7476 "*
7477 {
7478 return (WORDS_BIG_ENDIAN)
7479 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7480 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7481 }"
7482 [(set_attr "type" "imul")
7483 (set_attr "length" "8")])
7485 (define_insn "*umulsidi3_no_mq"
7486 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7487 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7488 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7489 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7490 "*
7491 {
7492 return (WORDS_BIG_ENDIAN)
7493 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7494 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7495 }"
7496 [(set_attr "type" "imul")
7497 (set_attr "length" "8")])
7499 (define_split
7500 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7501 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7502 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7503 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7504 [(set (match_dup 3)
7505 (truncate:SI
7506 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
7507 (zero_extend:DI (match_dup 2)))
7508 (const_int 32))))
7509 (set (match_dup 4)
7510 (mult:SI (match_dup 1)
7511 (match_dup 2)))]
7512 "
7513 {
7514 int endian = (WORDS_BIG_ENDIAN == 0);
7515 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7516 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7517 }")
7519 (define_expand "smulsi3_highpart"
7520 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7521 (truncate:SI
7522 (lshiftrt:DI (mult:DI (sign_extend:DI
7523 (match_operand:SI 1 "gpc_reg_operand" ""))
7524 (sign_extend:DI
7525 (match_operand:SI 2 "gpc_reg_operand" "")))
7526 (const_int 32))))]
7527 ""
7528 "
7529 {
7530 if (! TARGET_POWER && ! TARGET_POWERPC)
7531 {
7532 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7533 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7534 emit_insn (gen_mulh_call ());
7535 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
7536 DONE;
7537 }
7538 else if (TARGET_POWER)
7539 {
7540 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7541 DONE;
7542 }
7543 }")
7545 (define_insn "smulsi3_highpart_mq"
7546 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7547 (truncate:SI
7548 (lshiftrt:DI (mult:DI (sign_extend:DI
7549 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7550 (sign_extend:DI
7551 (match_operand:SI 2 "gpc_reg_operand" "r")))
7552 (const_int 32))))
7553 (clobber (match_scratch:SI 3 "=q"))]
7554 "TARGET_POWER"
7555 "mul %0,%1,%2"
7556 [(set_attr "type" "imul")])
7558 (define_insn "*smulsi3_highpart_no_mq"
7559 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7560 (truncate:SI
7561 (lshiftrt:DI (mult:DI (sign_extend:DI
7562 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7563 (sign_extend:DI
7564 (match_operand:SI 2 "gpc_reg_operand" "r")))
7565 (const_int 32))))]
7566 "TARGET_POWERPC && ! TARGET_POWER"
7567 "mulhw %0,%1,%2"
7568 [(set_attr "type" "imul")])
7570 (define_expand "umulsi3_highpart"
7571 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7572 (truncate:SI
7573 (lshiftrt:DI (mult:DI (zero_extend:DI
7574 (match_operand:SI 1 "gpc_reg_operand" ""))
7575 (zero_extend:DI
7576 (match_operand:SI 2 "gpc_reg_operand" "")))
7577 (const_int 32))))]
7578 "TARGET_POWERPC"
7579 "
7580 {
7581 if (TARGET_POWER)
7582 {
7583 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7584 DONE;
7585 }
7586 }")
7588 (define_insn "umulsi3_highpart_mq"
7589 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7590 (truncate:SI
7591 (lshiftrt:DI (mult:DI (zero_extend:DI
7592 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7593 (zero_extend:DI
7594 (match_operand:SI 2 "gpc_reg_operand" "r")))
7595 (const_int 32))))
7596 (clobber (match_scratch:SI 3 "=q"))]
7597 "TARGET_POWERPC && TARGET_POWER"
7598 "mulhwu %0,%1,%2"
7599 [(set_attr "type" "imul")])
7601 (define_insn "*umulsi3_highpart_no_mq"
7602 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7603 (truncate:SI
7604 (lshiftrt:DI (mult:DI (zero_extend:DI
7605 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7606 (zero_extend:DI
7607 (match_operand:SI 2 "gpc_reg_operand" "r")))
7608 (const_int 32))))]
7609 "TARGET_POWERPC && ! TARGET_POWER"
7610 "mulhwu %0,%1,%2"
7611 [(set_attr "type" "imul")])
7613 ;; If operands 0 and 2 are in the same register, we have a problem. But
7614 ;; operands 0 and 1 (the usual case) can be in the same register. That's
7615 ;; why we have the strange constraints below.
7616 (define_insn "ashldi3_power"
7617 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7618 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7619 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7620 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7621 "TARGET_POWER"
7622 "@
7623 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
7624 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7625 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7626 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
7627 [(set_attr "length" "8")])
7629 (define_insn "lshrdi3_power"
7630 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7631 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7632 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7633 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7634 "TARGET_POWER"
7635 "@
7636 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
7637 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7638 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7639 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
7640 [(set_attr "length" "8")])
7642 ;; Shift by a variable amount is too complex to be worth open-coding. We
7643 ;; just handle shifts by constants.
7644 (define_insn "ashrdi3_power"
7645 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7646 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7647 (match_operand:SI 2 "const_int_operand" "M,i")))
7648 (clobber (match_scratch:SI 3 "=X,q"))]
7649 "TARGET_POWER"
7650 "@
7651 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7652 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
7653 [(set_attr "type" "shift")
7654 (set_attr "length" "8")])
7656 (define_insn "ashrdi3_no_power"
7657 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
7658 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7659 (match_operand:SI 2 "const_int_operand" "M,i")))]
7660 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
7661 "@
7662 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7663 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
7664 [(set_attr "type" "two,three")
7665 (set_attr "length" "8,12")])
7667 (define_insn "*ashrdisi3_noppc64"
7668 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7669 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7670 (const_int 32)) 4))]
7671 "TARGET_32BIT && !TARGET_POWERPC64"
7672 "*
7673 {
7674 if (REGNO (operands[0]) == REGNO (operands[1]))
7675 return \"\";
7676 else
7677 return \"mr %0,%1\";
7678 }"
7679 [(set_attr "length" "4")])
7681 \f
7682 ;; PowerPC64 DImode operations.
7684 (define_expand "absdi2"
7685 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7686 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
7687 "TARGET_POWERPC64"
7688 "
7689 {
7690 if (TARGET_ISEL)
7691 emit_insn (gen_absdi2_isel (operands[0], operands[1]));
7692 else
7693 emit_insn (gen_absdi2_internal (operands[0], operands[1]));
7694 DONE;
7695 }")
7697 (define_insn_and_split "absdi2_internal"
7698 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7699 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
7700 (clobber (match_scratch:DI 2 "=&r,&r"))]
7701 "TARGET_POWERPC64 && !TARGET_ISEL"
7702 "#"
7703 "&& reload_completed"
7704 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7705 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7706 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
7707 "")
7709 (define_insn_and_split "*nabsdi2"
7710 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7711 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
7712 (clobber (match_scratch:DI 2 "=&r,&r"))]
7713 "TARGET_POWERPC64 && !TARGET_ISEL"
7714 "#"
7715 "&& reload_completed"
7716 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7717 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7718 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7719 "")
7721 (define_insn "muldi3"
7722 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7723 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7724 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
7725 "TARGET_POWERPC64"
7726 "@
7727 mulld %0,%1,%2
7728 mulli %0,%1,%2"
7729 [(set (attr "type")
7730 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
7731 (const_string "imul3")
7732 (match_operand:SI 2 "short_cint_operand" "")
7733 (const_string "imul2")]
7734 (const_string "lmul")))])
7736 (define_insn "*muldi3_internal1"
7737 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7738 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7739 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7740 (const_int 0)))
7741 (clobber (match_scratch:DI 3 "=r,r"))]
7742 "TARGET_POWERPC64"
7743 "@
7744 mulld. %3,%1,%2
7745 #"
7746 [(set_attr "type" "lmul_compare")
7747 (set_attr "length" "4,8")])
7749 (define_split
7750 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7751 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7752 (match_operand:DI 2 "gpc_reg_operand" ""))
7753 (const_int 0)))
7754 (clobber (match_scratch:DI 3 ""))]
7755 "TARGET_POWERPC64 && reload_completed"
7756 [(set (match_dup 3)
7757 (mult:DI (match_dup 1) (match_dup 2)))
7758 (set (match_dup 0)
7759 (compare:CC (match_dup 3)
7760 (const_int 0)))]
7761 "")
7763 (define_insn "*muldi3_internal2"
7764 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7765 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7766 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7767 (const_int 0)))
7768 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7769 (mult:DI (match_dup 1) (match_dup 2)))]
7770 "TARGET_POWERPC64"
7771 "@
7772 mulld. %0,%1,%2
7773 #"
7774 [(set_attr "type" "lmul_compare")
7775 (set_attr "length" "4,8")])
7777 (define_split
7778 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7779 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7780 (match_operand:DI 2 "gpc_reg_operand" ""))
7781 (const_int 0)))
7782 (set (match_operand:DI 0 "gpc_reg_operand" "")
7783 (mult:DI (match_dup 1) (match_dup 2)))]
7784 "TARGET_POWERPC64 && reload_completed"
7785 [(set (match_dup 0)
7786 (mult:DI (match_dup 1) (match_dup 2)))
7787 (set (match_dup 3)
7788 (compare:CC (match_dup 0)
7789 (const_int 0)))]
7790 "")
7792 (define_insn "smuldi3_highpart"
7793 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7794 (truncate:DI
7795 (lshiftrt:TI (mult:TI (sign_extend:TI
7796 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7797 (sign_extend:TI
7798 (match_operand:DI 2 "gpc_reg_operand" "r")))
7799 (const_int 64))))]
7800 "TARGET_POWERPC64"
7801 "mulhd %0,%1,%2"
7802 [(set_attr "type" "lmul")])
7804 (define_insn "umuldi3_highpart"
7805 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7806 (truncate:DI
7807 (lshiftrt:TI (mult:TI (zero_extend:TI
7808 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7809 (zero_extend:TI
7810 (match_operand:DI 2 "gpc_reg_operand" "r")))
7811 (const_int 64))))]
7812 "TARGET_POWERPC64"
7813 "mulhdu %0,%1,%2"
7814 [(set_attr "type" "lmul")])
7816 (define_insn "rotldi3"
7817 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7818 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7819 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7820 "TARGET_POWERPC64"
7821 "@
7822 rldcl %0,%1,%2,0
7823 rldicl %0,%1,%H2,0"
7824 [(set_attr "type" "var_shift_rotate,integer")])
7826 (define_insn "*rotldi3_internal2"
7827 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7828 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7829 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7830 (const_int 0)))
7831 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7832 "TARGET_64BIT"
7833 "@
7834 rldcl. %3,%1,%2,0
7835 rldicl. %3,%1,%H2,0
7836 #
7837 #"
7838 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7839 (set_attr "length" "4,4,8,8")])
7841 (define_split
7842 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7843 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7844 (match_operand:DI 2 "reg_or_cint_operand" ""))
7845 (const_int 0)))
7846 (clobber (match_scratch:DI 3 ""))]
7847 "TARGET_POWERPC64 && reload_completed"
7848 [(set (match_dup 3)
7849 (rotate:DI (match_dup 1) (match_dup 2)))
7850 (set (match_dup 0)
7851 (compare:CC (match_dup 3)
7852 (const_int 0)))]
7853 "")
7855 (define_insn "*rotldi3_internal3"
7856 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7857 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7858 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7859 (const_int 0)))
7860 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7861 (rotate:DI (match_dup 1) (match_dup 2)))]
7862 "TARGET_64BIT"
7863 "@
7864 rldcl. %0,%1,%2,0
7865 rldicl. %0,%1,%H2,0
7866 #
7867 #"
7868 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7869 (set_attr "length" "4,4,8,8")])
7871 (define_split
7872 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7873 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7874 (match_operand:DI 2 "reg_or_cint_operand" ""))
7875 (const_int 0)))
7876 (set (match_operand:DI 0 "gpc_reg_operand" "")
7877 (rotate:DI (match_dup 1) (match_dup 2)))]
7878 "TARGET_POWERPC64 && reload_completed"
7879 [(set (match_dup 0)
7880 (rotate:DI (match_dup 1) (match_dup 2)))
7881 (set (match_dup 3)
7882 (compare:CC (match_dup 0)
7883 (const_int 0)))]
7884 "")
7886 (define_insn "*rotldi3_internal4"
7887 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7888 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7889 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7890 (match_operand:DI 3 "mask64_operand" "n,n")))]
7891 "TARGET_POWERPC64"
7892 "@
7893 rldc%B3 %0,%1,%2,%S3
7894 rldic%B3 %0,%1,%H2,%S3"
7895 [(set_attr "type" "var_shift_rotate,integer")])
7897 (define_insn "*rotldi3_internal5"
7898 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7899 (compare:CC (and:DI
7900 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7901 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7902 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7903 (const_int 0)))
7904 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7905 "TARGET_64BIT"
7906 "@
7907 rldc%B3. %4,%1,%2,%S3
7908 rldic%B3. %4,%1,%H2,%S3
7909 #
7910 #"
7911 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7912 (set_attr "length" "4,4,8,8")])
7914 (define_split
7915 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7916 (compare:CC (and:DI
7917 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7918 (match_operand:DI 2 "reg_or_cint_operand" ""))
7919 (match_operand:DI 3 "mask64_operand" ""))
7920 (const_int 0)))
7921 (clobber (match_scratch:DI 4 ""))]
7922 "TARGET_POWERPC64 && reload_completed"
7923 [(set (match_dup 4)
7924 (and:DI (rotate:DI (match_dup 1)
7925 (match_dup 2))
7926 (match_dup 3)))
7927 (set (match_dup 0)
7928 (compare:CC (match_dup 4)
7929 (const_int 0)))]
7930 "")
7932 (define_insn "*rotldi3_internal6"
7933 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
7934 (compare:CC (and:DI
7935 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7936 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7937 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7938 (const_int 0)))
7939 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7940 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7941 "TARGET_64BIT"
7942 "@
7943 rldc%B3. %0,%1,%2,%S3
7944 rldic%B3. %0,%1,%H2,%S3
7945 #
7946 #"
7947 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7948 (set_attr "length" "4,4,8,8")])
7950 (define_split
7951 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7952 (compare:CC (and:DI
7953 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7954 (match_operand:DI 2 "reg_or_cint_operand" ""))
7955 (match_operand:DI 3 "mask64_operand" ""))
7956 (const_int 0)))
7957 (set (match_operand:DI 0 "gpc_reg_operand" "")
7958 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7959 "TARGET_POWERPC64 && reload_completed"
7960 [(set (match_dup 0)
7961 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7962 (set (match_dup 4)
7963 (compare:CC (match_dup 0)
7964 (const_int 0)))]
7965 "")
7967 (define_insn "*rotldi3_internal7"
7968 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7969 (zero_extend:DI
7970 (subreg:QI
7971 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7972 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7973 "TARGET_POWERPC64"
7974 "@
7975 rldcl %0,%1,%2,56
7976 rldicl %0,%1,%H2,56"
7977 [(set_attr "type" "var_shift_rotate,integer")])
7979 (define_insn "*rotldi3_internal8"
7980 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7981 (compare:CC (zero_extend:DI
7982 (subreg:QI
7983 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7984 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7985 (const_int 0)))
7986 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7987 "TARGET_64BIT"
7988 "@
7989 rldcl. %3,%1,%2,56
7990 rldicl. %3,%1,%H2,56
7991 #
7992 #"
7993 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7994 (set_attr "length" "4,4,8,8")])
7996 (define_split
7997 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7998 (compare:CC (zero_extend:DI
7999 (subreg:QI
8000 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8001 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8002 (const_int 0)))
8003 (clobber (match_scratch:DI 3 ""))]
8004 "TARGET_POWERPC64 && reload_completed"
8005 [(set (match_dup 3)
8006 (zero_extend:DI (subreg:QI
8007 (rotate:DI (match_dup 1)
8008 (match_dup 2)) 0)))
8009 (set (match_dup 0)
8010 (compare:CC (match_dup 3)
8011 (const_int 0)))]
8012 "")
8014 (define_insn "*rotldi3_internal9"
8015 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8016 (compare:CC (zero_extend:DI
8017 (subreg:QI
8018 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8019 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8020 (const_int 0)))
8021 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8022 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8023 "TARGET_64BIT"
8024 "@
8025 rldcl. %0,%1,%2,56
8026 rldicl. %0,%1,%H2,56
8027 #
8028 #"
8029 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8030 (set_attr "length" "4,4,8,8")])
8032 (define_split
8033 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8034 (compare:CC (zero_extend:DI
8035 (subreg:QI
8036 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8037 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8038 (const_int 0)))
8039 (set (match_operand:DI 0 "gpc_reg_operand" "")
8040 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8041 "TARGET_POWERPC64 && reload_completed"
8042 [(set (match_dup 0)
8043 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8044 (set (match_dup 3)
8045 (compare:CC (match_dup 0)
8046 (const_int 0)))]
8047 "")
8049 (define_insn "*rotldi3_internal10"
8050 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8051 (zero_extend:DI
8052 (subreg:HI
8053 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8054 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
8055 "TARGET_POWERPC64"
8056 "@
8057 rldcl %0,%1,%2,48
8058 rldicl %0,%1,%H2,48"
8059 [(set_attr "type" "var_shift_rotate,integer")])
8061 (define_insn "*rotldi3_internal11"
8062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8063 (compare:CC (zero_extend:DI
8064 (subreg:HI
8065 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8066 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8067 (const_int 0)))
8068 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8069 "TARGET_64BIT"
8070 "@
8071 rldcl. %3,%1,%2,48
8072 rldicl. %3,%1,%H2,48
8073 #
8074 #"
8075 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8076 (set_attr "length" "4,4,8,8")])
8078 (define_split
8079 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8080 (compare:CC (zero_extend:DI
8081 (subreg:HI
8082 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8083 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8084 (const_int 0)))
8085 (clobber (match_scratch:DI 3 ""))]
8086 "TARGET_POWERPC64 && reload_completed"
8087 [(set (match_dup 3)
8088 (zero_extend:DI (subreg:HI
8089 (rotate:DI (match_dup 1)
8090 (match_dup 2)) 0)))
8091 (set (match_dup 0)
8092 (compare:CC (match_dup 3)
8093 (const_int 0)))]
8094 "")
8096 (define_insn "*rotldi3_internal12"
8097 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8098 (compare:CC (zero_extend:DI
8099 (subreg:HI
8100 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8101 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8102 (const_int 0)))
8103 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8104 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8105 "TARGET_64BIT"
8106 "@
8107 rldcl. %0,%1,%2,48
8108 rldicl. %0,%1,%H2,48
8109 #
8110 #"
8111 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8112 (set_attr "length" "4,4,8,8")])
8114 (define_split
8115 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8116 (compare:CC (zero_extend:DI
8117 (subreg:HI
8118 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8119 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8120 (const_int 0)))
8121 (set (match_operand:DI 0 "gpc_reg_operand" "")
8122 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8123 "TARGET_POWERPC64 && reload_completed"
8124 [(set (match_dup 0)
8125 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8126 (set (match_dup 3)
8127 (compare:CC (match_dup 0)
8128 (const_int 0)))]
8129 "")
8131 (define_insn "*rotldi3_internal13"
8132 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8133 (zero_extend:DI
8134 (subreg:SI
8135 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8136 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
8137 "TARGET_POWERPC64"
8138 "@
8139 rldcl %0,%1,%2,32
8140 rldicl %0,%1,%H2,32"
8141 [(set_attr "type" "var_shift_rotate,integer")])
8143 (define_insn "*rotldi3_internal14"
8144 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8145 (compare:CC (zero_extend:DI
8146 (subreg:SI
8147 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8148 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8149 (const_int 0)))
8150 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8151 "TARGET_64BIT"
8152 "@
8153 rldcl. %3,%1,%2,32
8154 rldicl. %3,%1,%H2,32
8155 #
8156 #"
8157 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8158 (set_attr "length" "4,4,8,8")])
8160 (define_split
8161 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8162 (compare:CC (zero_extend:DI
8163 (subreg:SI
8164 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8165 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8166 (const_int 0)))
8167 (clobber (match_scratch:DI 3 ""))]
8168 "TARGET_POWERPC64 && reload_completed"
8169 [(set (match_dup 3)
8170 (zero_extend:DI (subreg:SI
8171 (rotate:DI (match_dup 1)
8172 (match_dup 2)) 0)))
8173 (set (match_dup 0)
8174 (compare:CC (match_dup 3)
8175 (const_int 0)))]
8176 "")
8178 (define_insn "*rotldi3_internal15"
8179 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8180 (compare:CC (zero_extend:DI
8181 (subreg:SI
8182 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8183 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8184 (const_int 0)))
8185 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8186 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8187 "TARGET_64BIT"
8188 "@
8189 rldcl. %0,%1,%2,32
8190 rldicl. %0,%1,%H2,32
8191 #
8192 #"
8193 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8194 (set_attr "length" "4,4,8,8")])
8196 (define_split
8197 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8198 (compare:CC (zero_extend:DI
8199 (subreg:SI
8200 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8201 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8202 (const_int 0)))
8203 (set (match_operand:DI 0 "gpc_reg_operand" "")
8204 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8205 "TARGET_POWERPC64 && reload_completed"
8206 [(set (match_dup 0)
8207 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8208 (set (match_dup 3)
8209 (compare:CC (match_dup 0)
8210 (const_int 0)))]
8211 "")
8213 (define_expand "ashldi3"
8214 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8215 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8216 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8217 "TARGET_POWERPC64 || TARGET_POWER"
8218 "
8219 {
8220 if (TARGET_POWERPC64)
8221 ;
8222 else if (TARGET_POWER)
8223 {
8224 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
8225 DONE;
8226 }
8227 else
8228 FAIL;
8229 }")
8231 (define_insn "*ashldi3_internal1"
8232 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8233 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8234 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8235 "TARGET_POWERPC64"
8236 "@
8237 sld %0,%1,%2
8238 sldi %0,%1,%H2"
8239 [(set_attr "type" "var_shift_rotate,shift")])
8241 (define_insn "*ashldi3_internal2"
8242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8243 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8244 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8245 (const_int 0)))
8246 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8247 "TARGET_64BIT"
8248 "@
8249 sld. %3,%1,%2
8250 sldi. %3,%1,%H2
8251 #
8252 #"
8253 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8254 (set_attr "length" "4,4,8,8")])
8256 (define_split
8257 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8258 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8259 (match_operand:SI 2 "reg_or_cint_operand" ""))
8260 (const_int 0)))
8261 (clobber (match_scratch:DI 3 ""))]
8262 "TARGET_POWERPC64 && reload_completed"
8263 [(set (match_dup 3)
8264 (ashift:DI (match_dup 1) (match_dup 2)))
8265 (set (match_dup 0)
8266 (compare:CC (match_dup 3)
8267 (const_int 0)))]
8268 "")
8270 (define_insn "*ashldi3_internal3"
8271 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8272 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8273 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8274 (const_int 0)))
8275 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8276 (ashift:DI (match_dup 1) (match_dup 2)))]
8277 "TARGET_64BIT"
8278 "@
8279 sld. %0,%1,%2
8280 sldi. %0,%1,%H2
8281 #
8282 #"
8283 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8284 (set_attr "length" "4,4,8,8")])
8286 (define_split
8287 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8288 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8289 (match_operand:SI 2 "reg_or_cint_operand" ""))
8290 (const_int 0)))
8291 (set (match_operand:DI 0 "gpc_reg_operand" "")
8292 (ashift:DI (match_dup 1) (match_dup 2)))]
8293 "TARGET_POWERPC64 && reload_completed"
8294 [(set (match_dup 0)
8295 (ashift:DI (match_dup 1) (match_dup 2)))
8296 (set (match_dup 3)
8297 (compare:CC (match_dup 0)
8298 (const_int 0)))]
8299 "")
8301 (define_insn "*ashldi3_internal4"
8302 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8303 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
8304 (match_operand:SI 2 "const_int_operand" "i"))
8305 (match_operand:DI 3 "const_int_operand" "n")))]
8306 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
8307 "rldic %0,%1,%H2,%W3")
8309 (define_insn "ashldi3_internal5"
8310 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8311 (compare:CC
8312 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8313 (match_operand:SI 2 "const_int_operand" "i,i"))
8314 (match_operand:DI 3 "const_int_operand" "n,n"))
8315 (const_int 0)))
8316 (clobber (match_scratch:DI 4 "=r,r"))]
8317 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
8318 "@
8319 rldic. %4,%1,%H2,%W3
8320 #"
8321 [(set_attr "type" "compare")
8322 (set_attr "length" "4,8")])
8324 (define_split
8325 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8326 (compare:CC
8327 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8328 (match_operand:SI 2 "const_int_operand" ""))
8329 (match_operand:DI 3 "const_int_operand" ""))
8330 (const_int 0)))
8331 (clobber (match_scratch:DI 4 ""))]
8332 "TARGET_POWERPC64 && reload_completed
8333 && includes_rldic_lshift_p (operands[2], operands[3])"
8334 [(set (match_dup 4)
8335 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8336 (match_dup 3)))
8337 (set (match_dup 0)
8338 (compare:CC (match_dup 4)
8339 (const_int 0)))]
8340 "")
8342 (define_insn "*ashldi3_internal6"
8343 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
8344 (compare:CC
8345 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8346 (match_operand:SI 2 "const_int_operand" "i,i"))
8347 (match_operand:DI 3 "const_int_operand" "n,n"))
8348 (const_int 0)))
8349 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8350 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8351 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
8352 "@
8353 rldic. %0,%1,%H2,%W3
8354 #"
8355 [(set_attr "type" "compare")
8356 (set_attr "length" "4,8")])
8358 (define_split
8359 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8360 (compare:CC
8361 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8362 (match_operand:SI 2 "const_int_operand" ""))
8363 (match_operand:DI 3 "const_int_operand" ""))
8364 (const_int 0)))
8365 (set (match_operand:DI 0 "gpc_reg_operand" "")
8366 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8367 "TARGET_POWERPC64 && reload_completed
8368 && includes_rldic_lshift_p (operands[2], operands[3])"
8369 [(set (match_dup 0)
8370 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8371 (match_dup 3)))
8372 (set (match_dup 4)
8373 (compare:CC (match_dup 0)
8374 (const_int 0)))]
8375 "")
8377 (define_insn "*ashldi3_internal7"
8378 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8379 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
8380 (match_operand:SI 2 "const_int_operand" "i"))
8381 (match_operand:DI 3 "mask64_operand" "n")))]
8382 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
8383 "rldicr %0,%1,%H2,%S3")
8385 (define_insn "ashldi3_internal8"
8386 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8387 (compare:CC
8388 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8389 (match_operand:SI 2 "const_int_operand" "i,i"))
8390 (match_operand:DI 3 "mask64_operand" "n,n"))
8391 (const_int 0)))
8392 (clobber (match_scratch:DI 4 "=r,r"))]
8393 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
8394 "@
8395 rldicr. %4,%1,%H2,%S3
8396 #"
8397 [(set_attr "type" "compare")
8398 (set_attr "length" "4,8")])
8400 (define_split
8401 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8402 (compare:CC
8403 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8404 (match_operand:SI 2 "const_int_operand" ""))
8405 (match_operand:DI 3 "mask64_operand" ""))
8406 (const_int 0)))
8407 (clobber (match_scratch:DI 4 ""))]
8408 "TARGET_POWERPC64 && reload_completed
8409 && includes_rldicr_lshift_p (operands[2], operands[3])"
8410 [(set (match_dup 4)
8411 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8412 (match_dup 3)))
8413 (set (match_dup 0)
8414 (compare:CC (match_dup 4)
8415 (const_int 0)))]
8416 "")
8418 (define_insn "*ashldi3_internal9"
8419 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
8420 (compare:CC
8421 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8422 (match_operand:SI 2 "const_int_operand" "i,i"))
8423 (match_operand:DI 3 "mask64_operand" "n,n"))
8424 (const_int 0)))
8425 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8426 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8427 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
8428 "@
8429 rldicr. %0,%1,%H2,%S3
8430 #"
8431 [(set_attr "type" "compare")
8432 (set_attr "length" "4,8")])
8434 (define_split
8435 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8436 (compare:CC
8437 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8438 (match_operand:SI 2 "const_int_operand" ""))
8439 (match_operand:DI 3 "mask64_operand" ""))
8440 (const_int 0)))
8441 (set (match_operand:DI 0 "gpc_reg_operand" "")
8442 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8443 "TARGET_POWERPC64 && reload_completed
8444 && includes_rldicr_lshift_p (operands[2], operands[3])"
8445 [(set (match_dup 0)
8446 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8447 (match_dup 3)))
8448 (set (match_dup 4)
8449 (compare:CC (match_dup 0)
8450 (const_int 0)))]
8451 "")
8453 (define_expand "lshrdi3"
8454 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8455 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8456 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8457 "TARGET_POWERPC64 || TARGET_POWER"
8458 "
8459 {
8460 if (TARGET_POWERPC64)
8461 ;
8462 else if (TARGET_POWER)
8463 {
8464 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
8465 DONE;
8466 }
8467 else
8468 FAIL;
8469 }")
8471 (define_insn "*lshrdi3_internal1"
8472 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8473 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8474 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8475 "TARGET_POWERPC64"
8476 "@
8477 srd %0,%1,%2
8478 srdi %0,%1,%H2"
8479 [(set_attr "type" "var_shift_rotate,shift")])
8481 (define_insn "*lshrdi3_internal2"
8482 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8483 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8484 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8485 (const_int 0)))
8486 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8487 "TARGET_64BIT "
8488 "@
8489 srd. %3,%1,%2
8490 srdi. %3,%1,%H2
8491 #
8492 #"
8493 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8494 (set_attr "length" "4,4,8,8")])
8496 (define_split
8497 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8498 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8499 (match_operand:SI 2 "reg_or_cint_operand" ""))
8500 (const_int 0)))
8501 (clobber (match_scratch:DI 3 ""))]
8502 "TARGET_POWERPC64 && reload_completed"
8503 [(set (match_dup 3)
8504 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8505 (set (match_dup 0)
8506 (compare:CC (match_dup 3)
8507 (const_int 0)))]
8508 "")
8510 (define_insn "*lshrdi3_internal3"
8511 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8512 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8513 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8514 (const_int 0)))
8515 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8516 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8517 "TARGET_64BIT"
8518 "@
8519 srd. %0,%1,%2
8520 srdi. %0,%1,%H2
8521 #
8522 #"
8523 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8524 (set_attr "length" "4,4,8,8")])
8526 (define_split
8527 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8528 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8529 (match_operand:SI 2 "reg_or_cint_operand" ""))
8530 (const_int 0)))
8531 (set (match_operand:DI 0 "gpc_reg_operand" "")
8532 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8533 "TARGET_POWERPC64 && reload_completed"
8534 [(set (match_dup 0)
8535 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8536 (set (match_dup 3)
8537 (compare:CC (match_dup 0)
8538 (const_int 0)))]
8539 "")
8541 (define_expand "ashrdi3"
8542 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8543 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8544 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8545 "WORDS_BIG_ENDIAN"
8546 "
8547 {
8548 if (TARGET_POWERPC64)
8549 ;
8550 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
8551 {
8552 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
8553 DONE;
8554 }
8555 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
8556 && WORDS_BIG_ENDIAN)
8557 {
8558 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
8559 DONE;
8560 }
8561 else
8562 FAIL;
8563 }")
8565 (define_insn "*ashrdi3_internal1"
8566 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8567 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8568 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8569 "TARGET_POWERPC64"
8570 "@
8571 srad %0,%1,%2
8572 sradi %0,%1,%H2"
8573 [(set_attr "type" "var_shift_rotate,shift")])
8575 (define_insn "*ashrdi3_internal2"
8576 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8577 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8578 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8579 (const_int 0)))
8580 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8581 "TARGET_64BIT"
8582 "@
8583 srad. %3,%1,%2
8584 sradi. %3,%1,%H2
8585 #
8586 #"
8587 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8588 (set_attr "length" "4,4,8,8")])
8590 (define_split
8591 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8592 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8593 (match_operand:SI 2 "reg_or_cint_operand" ""))
8594 (const_int 0)))
8595 (clobber (match_scratch:DI 3 ""))]
8596 "TARGET_POWERPC64 && reload_completed"
8597 [(set (match_dup 3)
8598 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8599 (set (match_dup 0)
8600 (compare:CC (match_dup 3)
8601 (const_int 0)))]
8602 "")
8604 (define_insn "*ashrdi3_internal3"
8605 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8606 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8607 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8608 (const_int 0)))
8609 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8610 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8611 "TARGET_64BIT"
8612 "@
8613 srad. %0,%1,%2
8614 sradi. %0,%1,%H2
8615 #
8616 #"
8617 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8618 (set_attr "length" "4,4,8,8")])
8620 (define_split
8621 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8622 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8623 (match_operand:SI 2 "reg_or_cint_operand" ""))
8624 (const_int 0)))
8625 (set (match_operand:DI 0 "gpc_reg_operand" "")
8626 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8627 "TARGET_POWERPC64 && reload_completed"
8628 [(set (match_dup 0)
8629 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8630 (set (match_dup 3)
8631 (compare:CC (match_dup 0)
8632 (const_int 0)))]
8633 "")
8635 (define_expand "anddi3"
8636 [(parallel
8637 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8638 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8639 (match_operand:DI 2 "and64_2_operand" "")))
8640 (clobber (match_scratch:CC 3 ""))])]
8641 "TARGET_POWERPC64"
8642 "")
8644 (define_insn "anddi3_mc"
8645 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8646 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8647 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8648 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8649 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8650 "@
8651 and %0,%1,%2
8652 rldic%B2 %0,%1,0,%S2
8653 rlwinm %0,%1,0,%m2,%M2
8654 andi. %0,%1,%b2
8655 andis. %0,%1,%u2
8656 #"
8657 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8658 (set_attr "length" "4,4,4,4,4,8")])
8660 (define_insn "anddi3_nomc"
8661 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8662 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8663 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8664 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8665 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8666 "@
8667 and %0,%1,%2
8668 rldic%B2 %0,%1,0,%S2
8669 rlwinm %0,%1,0,%m2,%M2
8670 #"
8671 [(set_attr "length" "4,4,4,8")])
8673 (define_split
8674 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8675 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8676 (match_operand:DI 2 "mask64_2_operand" "")))
8677 (clobber (match_scratch:CC 3 ""))]
8678 "TARGET_POWERPC64
8679 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8680 && !mask_operand (operands[2], DImode)
8681 && !mask64_operand (operands[2], DImode)"
8682 [(set (match_dup 0)
8683 (and:DI (rotate:DI (match_dup 1)
8684 (match_dup 4))
8685 (match_dup 5)))
8686 (set (match_dup 0)
8687 (and:DI (rotate:DI (match_dup 0)
8688 (match_dup 6))
8689 (match_dup 7)))]
8690 {
8691 build_mask64_2_operands (operands[2], &operands[4]);
8692 })
8694 (define_insn "*anddi3_internal2_mc"
8695 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8696 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8697 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8698 (const_int 0)))
8699 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8700 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8701 "TARGET_64BIT && rs6000_gen_cell_microcode"
8702 "@
8703 and. %3,%1,%2
8704 rldic%B2. %3,%1,0,%S2
8705 rlwinm. %3,%1,0,%m2,%M2
8706 andi. %3,%1,%b2
8707 andis. %3,%1,%u2
8708 #
8709 #
8710 #
8711 #
8712 #
8713 #
8714 #"
8715 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8716 fast_compare,compare,compare,compare,compare,compare,\
8717 compare,compare")
8718 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8720 (define_split
8721 [(set (match_operand:CC 0 "cc_reg_operand" "")
8722 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8723 (match_operand:DI 2 "mask64_2_operand" ""))
8724 (const_int 0)))
8725 (clobber (match_scratch:DI 3 ""))
8726 (clobber (match_scratch:CC 4 ""))]
8727 "TARGET_64BIT && reload_completed
8728 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8729 && !mask_operand (operands[2], DImode)
8730 && !mask64_operand (operands[2], DImode)"
8731 [(set (match_dup 3)
8732 (and:DI (rotate:DI (match_dup 1)
8733 (match_dup 5))
8734 (match_dup 6)))
8735 (parallel [(set (match_dup 0)
8736 (compare:CC (and:DI (rotate:DI (match_dup 3)
8737 (match_dup 7))
8738 (match_dup 8))
8739 (const_int 0)))
8740 (clobber (match_dup 3))])]
8741 "
8742 {
8743 build_mask64_2_operands (operands[2], &operands[5]);
8744 }")
8746 (define_insn "*anddi3_internal3_mc"
8747 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8748 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8749 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8750 (const_int 0)))
8751 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8752 (and:DI (match_dup 1) (match_dup 2)))
8753 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8754 "TARGET_64BIT && rs6000_gen_cell_microcode"
8755 "@
8756 and. %0,%1,%2
8757 rldic%B2. %0,%1,0,%S2
8758 rlwinm. %0,%1,0,%m2,%M2
8759 andi. %0,%1,%b2
8760 andis. %0,%1,%u2
8761 #
8762 #
8763 #
8764 #
8765 #
8766 #
8767 #"
8768 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8769 fast_compare,compare,compare,compare,compare,compare,\
8770 compare,compare")
8771 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8773 (define_split
8774 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8775 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8776 (match_operand:DI 2 "and64_2_operand" ""))
8777 (const_int 0)))
8778 (set (match_operand:DI 0 "gpc_reg_operand" "")
8779 (and:DI (match_dup 1) (match_dup 2)))
8780 (clobber (match_scratch:CC 4 ""))]
8781 "TARGET_64BIT && reload_completed"
8782 [(parallel [(set (match_dup 0)
8783 (and:DI (match_dup 1) (match_dup 2)))
8784 (clobber (match_dup 4))])
8785 (set (match_dup 3)
8786 (compare:CC (match_dup 0)
8787 (const_int 0)))]
8788 "")
8790 (define_split
8791 [(set (match_operand:CC 3 "cc_reg_operand" "")
8792 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8793 (match_operand:DI 2 "mask64_2_operand" ""))
8794 (const_int 0)))
8795 (set (match_operand:DI 0 "gpc_reg_operand" "")
8796 (and:DI (match_dup 1) (match_dup 2)))
8797 (clobber (match_scratch:CC 4 ""))]
8798 "TARGET_64BIT && reload_completed
8799 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8800 && !mask_operand (operands[2], DImode)
8801 && !mask64_operand (operands[2], DImode)"
8802 [(set (match_dup 0)
8803 (and:DI (rotate:DI (match_dup 1)
8804 (match_dup 5))
8805 (match_dup 6)))
8806 (parallel [(set (match_dup 3)
8807 (compare:CC (and:DI (rotate:DI (match_dup 0)
8808 (match_dup 7))
8809 (match_dup 8))
8810 (const_int 0)))
8811 (set (match_dup 0)
8812 (and:DI (rotate:DI (match_dup 0)
8813 (match_dup 7))
8814 (match_dup 8)))])]
8815 "
8816 {
8817 build_mask64_2_operands (operands[2], &operands[5]);
8818 }")
8820 (define_expand "iordi3"
8821 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8822 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8823 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8824 "TARGET_POWERPC64"
8825 "
8826 {
8827 if (non_logical_cint_operand (operands[2], DImode))
8828 {
8829 HOST_WIDE_INT value;
8830 rtx tmp = ((!can_create_pseudo_p ()
8831 || rtx_equal_p (operands[0], operands[1]))
8832 ? operands[0] : gen_reg_rtx (DImode));
8834 if (GET_CODE (operands[2]) == CONST_INT)
8835 {
8836 value = INTVAL (operands[2]);
8837 emit_insn (gen_iordi3 (tmp, operands[1],
8838 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8839 }
8840 else
8841 {
8842 value = CONST_DOUBLE_LOW (operands[2]);
8843 emit_insn (gen_iordi3 (tmp, operands[1],
8844 immed_double_const (value
8845 & (~ (HOST_WIDE_INT) 0xffff),
8846 0, DImode)));
8847 }
8849 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8850 DONE;
8851 }
8852 }")
8854 (define_expand "xordi3"
8855 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8856 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8857 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8858 "TARGET_POWERPC64"
8859 "
8860 {
8861 if (non_logical_cint_operand (operands[2], DImode))
8862 {
8863 HOST_WIDE_INT value;
8864 rtx tmp = ((!can_create_pseudo_p ()
8865 || rtx_equal_p (operands[0], operands[1]))
8866 ? operands[0] : gen_reg_rtx (DImode));
8868 if (GET_CODE (operands[2]) == CONST_INT)
8869 {
8870 value = INTVAL (operands[2]);
8871 emit_insn (gen_xordi3 (tmp, operands[1],
8872 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8873 }
8874 else
8875 {
8876 value = CONST_DOUBLE_LOW (operands[2]);
8877 emit_insn (gen_xordi3 (tmp, operands[1],
8878 immed_double_const (value
8879 & (~ (HOST_WIDE_INT) 0xffff),
8880 0, DImode)));
8881 }
8883 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8884 DONE;
8885 }
8886 }")
8888 (define_insn "*booldi3_internal1"
8889 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8890 (match_operator:DI 3 "boolean_or_operator"
8891 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8892 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8893 "TARGET_POWERPC64"
8894 "@
8895 %q3 %0,%1,%2
8896 %q3i %0,%1,%b2
8897 %q3is %0,%1,%u2")
8899 (define_insn "*booldi3_internal2"
8900 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8901 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8902 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8903 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8904 (const_int 0)))
8905 (clobber (match_scratch:DI 3 "=r,r"))]
8906 "TARGET_64BIT"
8907 "@
8908 %q4. %3,%1,%2
8909 #"
8910 [(set_attr "type" "fast_compare,compare")
8911 (set_attr "length" "4,8")])
8913 (define_split
8914 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8915 (compare:CC (match_operator:DI 4 "boolean_operator"
8916 [(match_operand:DI 1 "gpc_reg_operand" "")
8917 (match_operand:DI 2 "gpc_reg_operand" "")])
8918 (const_int 0)))
8919 (clobber (match_scratch:DI 3 ""))]
8920 "TARGET_POWERPC64 && reload_completed"
8921 [(set (match_dup 3) (match_dup 4))
8922 (set (match_dup 0)
8923 (compare:CC (match_dup 3)
8924 (const_int 0)))]
8925 "")
8927 (define_insn "*booldi3_internal3"
8928 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8929 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8930 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8931 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8932 (const_int 0)))
8933 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8934 (match_dup 4))]
8935 "TARGET_64BIT"
8936 "@
8937 %q4. %0,%1,%2
8938 #"
8939 [(set_attr "type" "fast_compare,compare")
8940 (set_attr "length" "4,8")])
8942 (define_split
8943 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8944 (compare:CC (match_operator:DI 4 "boolean_operator"
8945 [(match_operand:DI 1 "gpc_reg_operand" "")
8946 (match_operand:DI 2 "gpc_reg_operand" "")])
8947 (const_int 0)))
8948 (set (match_operand:DI 0 "gpc_reg_operand" "")
8949 (match_dup 4))]
8950 "TARGET_POWERPC64 && reload_completed"
8951 [(set (match_dup 0) (match_dup 4))
8952 (set (match_dup 3)
8953 (compare:CC (match_dup 0)
8954 (const_int 0)))]
8955 "")
8957 ;; Split a logical operation that we can't do in one insn into two insns,
8958 ;; each of which does one 16-bit part. This is used by combine.
8960 (define_split
8961 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8962 (match_operator:DI 3 "boolean_or_operator"
8963 [(match_operand:DI 1 "gpc_reg_operand" "")
8964 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8965 "TARGET_POWERPC64"
8966 [(set (match_dup 0) (match_dup 4))
8967 (set (match_dup 0) (match_dup 5))]
8968 "
8969 {
8970 rtx i3,i4;
8972 if (GET_CODE (operands[2]) == CONST_DOUBLE)
8973 {
8974 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
8975 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
8976 0, DImode);
8977 i4 = GEN_INT (value & 0xffff);
8978 }
8979 else
8980 {
8981 i3 = GEN_INT (INTVAL (operands[2])
8982 & (~ (HOST_WIDE_INT) 0xffff));
8983 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8984 }
8985 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8986 operands[1], i3);
8987 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8988 operands[0], i4);
8989 }")
8991 (define_insn "*boolcdi3_internal1"
8992 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8993 (match_operator:DI 3 "boolean_operator"
8994 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8995 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8996 "TARGET_POWERPC64"
8997 "%q3 %0,%2,%1")
8999 (define_insn "*boolcdi3_internal2"
9000 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
9001 (compare:CC (match_operator:DI 4 "boolean_operator"
9002 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
9003 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
9004 (const_int 0)))
9005 (clobber (match_scratch:DI 3 "=r,r"))]
9006 "TARGET_64BIT"
9007 "@
9008 %q4. %3,%2,%1
9009 #"
9010 [(set_attr "type" "fast_compare,compare")
9011 (set_attr "length" "4,8")])
9013 (define_split
9014 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9015 (compare:CC (match_operator:DI 4 "boolean_operator"
9016 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9017 (match_operand:DI 2 "gpc_reg_operand" "")])
9018 (const_int 0)))
9019 (clobber (match_scratch:DI 3 ""))]
9020 "TARGET_POWERPC64 && reload_completed"
9021 [(set (match_dup 3) (match_dup 4))
9022 (set (match_dup 0)
9023 (compare:CC (match_dup 3)
9024 (const_int 0)))]
9025 "")
9027 (define_insn "*boolcdi3_internal3"
9028 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9029 (compare:CC (match_operator:DI 4 "boolean_operator"
9030 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
9031 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
9032 (const_int 0)))
9033 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
9034 (match_dup 4))]
9035 "TARGET_64BIT"
9036 "@
9037 %q4. %0,%2,%1
9038 #"
9039 [(set_attr "type" "fast_compare,compare")
9040 (set_attr "length" "4,8")])
9042 (define_split
9043 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9044 (compare:CC (match_operator:DI 4 "boolean_operator"
9045 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9046 (match_operand:DI 2 "gpc_reg_operand" "")])
9047 (const_int 0)))
9048 (set (match_operand:DI 0 "gpc_reg_operand" "")
9049 (match_dup 4))]
9050 "TARGET_POWERPC64 && reload_completed"
9051 [(set (match_dup 0) (match_dup 4))
9052 (set (match_dup 3)
9053 (compare:CC (match_dup 0)
9054 (const_int 0)))]
9055 "")
9057 (define_insn "*boolccdi3_internal1"
9058 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9059 (match_operator:DI 3 "boolean_operator"
9060 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
9061 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
9062 "TARGET_POWERPC64"
9063 "%q3 %0,%1,%2")
9065 (define_insn "*boolccdi3_internal2"
9066 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
9067 (compare:CC (match_operator:DI 4 "boolean_operator"
9068 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
9069 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
9070 (const_int 0)))
9071 (clobber (match_scratch:DI 3 "=r,r"))]
9072 "TARGET_64BIT"
9073 "@
9074 %q4. %3,%1,%2
9075 #"
9076 [(set_attr "type" "fast_compare,compare")
9077 (set_attr "length" "4,8")])
9079 (define_split
9080 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9081 (compare:CC (match_operator:DI 4 "boolean_operator"
9082 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9083 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
9084 (const_int 0)))
9085 (clobber (match_scratch:DI 3 ""))]
9086 "TARGET_POWERPC64 && reload_completed"
9087 [(set (match_dup 3) (match_dup 4))
9088 (set (match_dup 0)
9089 (compare:CC (match_dup 3)
9090 (const_int 0)))]
9091 "")
9093 (define_insn "*boolccdi3_internal3"
9094 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9095 (compare:CC (match_operator:DI 4 "boolean_operator"
9096 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
9097 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
9098 (const_int 0)))
9099 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
9100 (match_dup 4))]
9101 "TARGET_64BIT"
9102 "@
9103 %q4. %0,%1,%2
9104 #"
9105 [(set_attr "type" "fast_compare,compare")
9106 (set_attr "length" "4,8")])
9108 (define_split
9109 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9110 (compare:CC (match_operator:DI 4 "boolean_operator"
9111 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9112 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
9113 (const_int 0)))
9114 (set (match_operand:DI 0 "gpc_reg_operand" "")
9115 (match_dup 4))]
9116 "TARGET_POWERPC64 && reload_completed"
9117 [(set (match_dup 0) (match_dup 4))
9118 (set (match_dup 3)
9119 (compare:CC (match_dup 0)
9120 (const_int 0)))]
9121 "")
9123 (define_expand "smindi3"
9124 [(match_operand:DI 0 "gpc_reg_operand" "")
9125 (match_operand:DI 1 "gpc_reg_operand" "")
9126 (match_operand:DI 2 "gpc_reg_operand" "")]
9127 "TARGET_ISEL64"
9128 "
9129 {
9130 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
9131 DONE;
9132 }")
9134 (define_expand "smaxdi3"
9135 [(match_operand:DI 0 "gpc_reg_operand" "")
9136 (match_operand:DI 1 "gpc_reg_operand" "")
9137 (match_operand:DI 2 "gpc_reg_operand" "")]
9138 "TARGET_ISEL64"
9139 "
9140 {
9141 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
9142 DONE;
9143 }")
9145 (define_expand "umindi3"
9146 [(match_operand:DI 0 "gpc_reg_operand" "")
9147 (match_operand:DI 1 "gpc_reg_operand" "")
9148 (match_operand:DI 2 "gpc_reg_operand" "")]
9149 "TARGET_ISEL64"
9150 "
9151 {
9152 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
9153 DONE;
9154 }")
9156 (define_expand "umaxdi3"
9157 [(match_operand:DI 0 "gpc_reg_operand" "")
9158 (match_operand:DI 1 "gpc_reg_operand" "")
9159 (match_operand:DI 2 "gpc_reg_operand" "")]
9160 "TARGET_ISEL64"
9161 "
9162 {
9163 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
9164 DONE;
9165 }")
9167 \f
9168 ;; Now define ways of moving data around.
9170 ;; Set up a register with a value from the GOT table
9172 (define_expand "movsi_got"
9173 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9174 (unspec:SI [(match_operand:SI 1 "got_operand" "")
9175 (match_dup 2)] UNSPEC_MOVSI_GOT))]
9176 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
9177 "
9178 {
9179 if (GET_CODE (operands[1]) == CONST)
9180 {
9181 rtx offset = const0_rtx;
9182 HOST_WIDE_INT value;
9184 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
9185 value = INTVAL (offset);
9186 if (value != 0)
9187 {
9188 rtx tmp = (!can_create_pseudo_p ()
9189 ? operands[0]
9190 : gen_reg_rtx (Pmode));
9191 emit_insn (gen_movsi_got (tmp, operands[1]));
9192 emit_insn (gen_addsi3 (operands[0], tmp, offset));
9193 DONE;
9194 }
9195 }
9197 operands[2] = rs6000_got_register (operands[1]);
9198 }")
9200 (define_insn "*movsi_got_internal"
9201 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9202 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
9203 (match_operand:SI 2 "gpc_reg_operand" "b")]
9204 UNSPEC_MOVSI_GOT))]
9205 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
9206 "{l|lwz} %0,%a1@got(%2)"
9207 [(set_attr "type" "load")])
9209 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
9210 ;; didn't get allocated to a hard register.
9211 (define_split
9212 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9213 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
9214 (match_operand:SI 2 "memory_operand" "")]
9215 UNSPEC_MOVSI_GOT))]
9216 "DEFAULT_ABI == ABI_V4
9217 && flag_pic == 1
9218 && (reload_in_progress || reload_completed)"
9219 [(set (match_dup 0) (match_dup 2))
9220 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
9221 UNSPEC_MOVSI_GOT))]
9222 "")
9224 ;; For SI, we special-case integers that can't be loaded in one insn. We
9225 ;; do the load 16-bits at a time. We could do this by loading from memory,
9226 ;; and this is even supposed to be faster, but it is simpler not to get
9227 ;; integers in the TOC.
9228 (define_insn "movsi_low"
9229 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9230 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9231 (match_operand 2 "" ""))))]
9232 "TARGET_MACHO && ! TARGET_64BIT"
9233 "{l|lwz} %0,lo16(%2)(%1)"
9234 [(set_attr "type" "load")
9235 (set_attr "length" "4")])
9237 (define_insn "*movsi_internal1"
9238 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
9239 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
9240 "!TARGET_SINGLE_FPU &&
9241 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
9242 "@
9243 mr %0,%1
9244 {cal|la} %0,%a1
9245 {l%U1%X1|lwz%U1%X1} %0,%1
9246 {st%U0%X0|stw%U0%X0} %1,%0
9247 {lil|li} %0,%1
9248 {liu|lis} %0,%v1
9249 #
9250 {cal|la} %0,%a1
9251 mf%1 %0
9252 mt%0 %1
9253 mt%0 %1
9254 mt%0 %1
9255 {cror 0,0,0|nop}"
9256 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
9257 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
9259 (define_insn "*movsi_internal1_single"
9260 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
9261 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
9262 "TARGET_SINGLE_FPU &&
9263 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
9264 "@
9265 mr %0,%1
9266 {cal|la} %0,%a1
9267 {l%U1%X1|lwz%U1%X1} %0,%1
9268 {st%U0%X0|stw%U0%X0} %1,%0
9269 {lil|li} %0,%1
9270 {liu|lis} %0,%v1
9271 #
9272 {cal|la} %0,%a1
9273 mf%1 %0
9274 mt%0 %1
9275 mt%0 %1
9276 mt%0 %1
9277 {cror 0,0,0|nop}
9278 stfs%U0%X0 %1, %0
9279 lfs%U1%X1 %0, %1"
9280 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
9281 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
9283 ;; Split a load of a large constant into the appropriate two-insn
9284 ;; sequence.
9286 (define_split
9287 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9288 (match_operand:SI 1 "const_int_operand" ""))]
9289 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
9290 && (INTVAL (operands[1]) & 0xffff) != 0"
9291 [(set (match_dup 0)
9292 (match_dup 2))
9293 (set (match_dup 0)
9294 (ior:SI (match_dup 0)
9295 (match_dup 3)))]
9296 "
9297 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
9299 if (tem == operands[0])
9300 DONE;
9301 else
9302 FAIL;
9303 }")
9305 (define_insn "*mov<mode>_internal2"
9306 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
9307 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
9308 (const_int 0)))
9309 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
9310 ""
9311 "@
9312 {cmpi|cmp<wd>i} %2,%0,0
9313 mr. %0,%1
9314 #"
9315 [(set_attr "type" "cmp,compare,cmp")
9316 (set_attr "length" "4,4,8")])
9318 (define_split
9319 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9320 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9321 (const_int 0)))
9322 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
9323 "reload_completed"
9324 [(set (match_dup 0) (match_dup 1))
9325 (set (match_dup 2)
9326 (compare:CC (match_dup 0)
9327 (const_int 0)))]
9328 "")
9329 \f
9330 (define_insn "*movhi_internal"
9331 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
9332 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
9333 "gpc_reg_operand (operands[0], HImode)
9334 || gpc_reg_operand (operands[1], HImode)"
9335 "@
9336 mr %0,%1
9337 lhz%U1%X1 %0,%1
9338 sth%U0%X0 %1,%0
9339 {lil|li} %0,%w1
9340 mf%1 %0
9341 mt%0 %1
9342 mt%0 %1
9343 {cror 0,0,0|nop}"
9344 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
9346 (define_expand "mov<mode>"
9347 [(set (match_operand:INT 0 "general_operand" "")
9348 (match_operand:INT 1 "any_operand" ""))]
9349 ""
9350 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9352 (define_insn "*movqi_internal"
9353 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
9354 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
9355 "gpc_reg_operand (operands[0], QImode)
9356 || gpc_reg_operand (operands[1], QImode)"
9357 "@
9358 mr %0,%1
9359 lbz%U1%X1 %0,%1
9360 stb%U0%X0 %1,%0
9361 {lil|li} %0,%1
9362 mf%1 %0
9363 mt%0 %1
9364 mt%0 %1
9365 {cror 0,0,0|nop}"
9366 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
9367 \f
9368 ;; Here is how to move condition codes around. When we store CC data in
9369 ;; an integer register or memory, we store just the high-order 4 bits.
9370 ;; This lets us not shift in the most common case of CR0.
9371 (define_expand "movcc"
9372 [(set (match_operand:CC 0 "nonimmediate_operand" "")
9373 (match_operand:CC 1 "nonimmediate_operand" ""))]
9374 ""
9375 "")
9377 (define_insn "*movcc_internal1"
9378 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
9379 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
9380 "register_operand (operands[0], CCmode)
9381 || register_operand (operands[1], CCmode)"
9382 "@
9383 mcrf %0,%1
9384 mtcrf 128,%1
9385 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
9386 crxor %0,%0,%0
9387 mfcr %0%Q1
9388 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
9389 mr %0,%1
9390 {lil|li} %0,%1
9391 mf%1 %0
9392 mt%0 %1
9393 mt%0 %1
9394 {l%U1%X1|lwz%U1%X1} %0,%1
9395 {st%U0%U1|stw%U0%U1} %1,%0"
9396 [(set (attr "type")
9397 (cond [(eq_attr "alternative" "0,3")
9398 (const_string "cr_logical")
9399 (eq_attr "alternative" "1,2")
9400 (const_string "mtcr")
9401 (eq_attr "alternative" "6,7,9")
9402 (const_string "integer")
9403 (eq_attr "alternative" "8")
9404 (const_string "mfjmpr")
9405 (eq_attr "alternative" "10")
9406 (const_string "mtjmpr")
9407 (eq_attr "alternative" "11")
9408 (const_string "load")
9409 (eq_attr "alternative" "12")
9410 (const_string "store")
9411 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
9412 (const_string "mfcrf")
9413 ]
9414 (const_string "mfcr")))
9415 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
9416 \f
9417 ;; For floating-point, we normally deal with the floating-point registers
9418 ;; unless -msoft-float is used. The sole exception is that parameter passing
9419 ;; can produce floating-point values in fixed-point registers. Unless the
9420 ;; value is a simple constant or already in memory, we deal with this by
9421 ;; allocating memory and copying the value explicitly via that memory location.
9422 (define_expand "movsf"
9423 [(set (match_operand:SF 0 "nonimmediate_operand" "")
9424 (match_operand:SF 1 "any_operand" ""))]
9425 ""
9426 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
9428 (define_split
9429 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9430 (match_operand:SF 1 "const_double_operand" ""))]
9431 "reload_completed
9432 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9433 || (GET_CODE (operands[0]) == SUBREG
9434 && GET_CODE (SUBREG_REG (operands[0])) == REG
9435 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9436 [(set (match_dup 2) (match_dup 3))]
9437 "
9438 {
9439 long l;
9440 REAL_VALUE_TYPE rv;
9442 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9443 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
9445 if (! TARGET_POWERPC64)
9446 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
9447 else
9448 operands[2] = gen_lowpart (SImode, operands[0]);
9450 operands[3] = gen_int_mode (l, SImode);
9451 }")
9453 (define_insn "*movsf_hardfloat"
9454 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
9455 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
9456 "(gpc_reg_operand (operands[0], SFmode)
9457 || gpc_reg_operand (operands[1], SFmode))
9458 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9459 "@
9460 mr %0,%1
9461 {l%U1%X1|lwz%U1%X1} %0,%1
9462 {st%U0%X0|stw%U0%X0} %1,%0
9463 fmr %0,%1
9464 lfs%U1%X1 %0,%1
9465 stfs%U0%X0 %1,%0
9466 mt%0 %1
9467 mt%0 %1
9468 mf%1 %0
9469 {cror 0,0,0|nop}
9470 #
9471 #"
9472 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
9473 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
9475 (define_insn "*movsf_softfloat"
9476 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
9477 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
9478 "(gpc_reg_operand (operands[0], SFmode)
9479 || gpc_reg_operand (operands[1], SFmode))
9480 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9481 "@
9482 mr %0,%1
9483 mt%0 %1
9484 mt%0 %1
9485 mf%1 %0
9486 {l%U1%X1|lwz%U1%X1} %0,%1
9487 {st%U0%X0|stw%U0%X0} %1,%0
9488 {lil|li} %0,%1
9489 {liu|lis} %0,%v1
9490 {cal|la} %0,%a1
9491 #
9492 #
9493 {cror 0,0,0|nop}"
9494 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
9495 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
9497 \f
9498 (define_expand "movdf"
9499 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9500 (match_operand:DF 1 "any_operand" ""))]
9501 ""
9502 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
9504 (define_split
9505 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9506 (match_operand:DF 1 "const_int_operand" ""))]
9507 "! TARGET_POWERPC64 && reload_completed
9508 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9509 || (GET_CODE (operands[0]) == SUBREG
9510 && GET_CODE (SUBREG_REG (operands[0])) == REG
9511 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9512 [(set (match_dup 2) (match_dup 4))
9513 (set (match_dup 3) (match_dup 1))]
9514 "
9515 {
9516 int endian = (WORDS_BIG_ENDIAN == 0);
9517 HOST_WIDE_INT value = INTVAL (operands[1]);
9519 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9520 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9521 #if HOST_BITS_PER_WIDE_INT == 32
9522 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9523 #else
9524 operands[4] = GEN_INT (value >> 32);
9525 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9526 #endif
9527 }")
9529 (define_split
9530 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9531 (match_operand:DF 1 "const_double_operand" ""))]
9532 "! TARGET_POWERPC64 && reload_completed
9533 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9534 || (GET_CODE (operands[0]) == SUBREG
9535 && GET_CODE (SUBREG_REG (operands[0])) == REG
9536 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9537 [(set (match_dup 2) (match_dup 4))
9538 (set (match_dup 3) (match_dup 5))]
9539 "
9540 {
9541 int endian = (WORDS_BIG_ENDIAN == 0);
9542 long l[2];
9543 REAL_VALUE_TYPE rv;
9545 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9546 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9548 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9549 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9550 operands[4] = gen_int_mode (l[endian], SImode);
9551 operands[5] = gen_int_mode (l[1 - endian], SImode);
9552 }")
9554 (define_split
9555 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9556 (match_operand:DF 1 "const_double_operand" ""))]
9557 "TARGET_POWERPC64 && reload_completed
9558 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9559 || (GET_CODE (operands[0]) == SUBREG
9560 && GET_CODE (SUBREG_REG (operands[0])) == REG
9561 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9562 [(set (match_dup 2) (match_dup 3))]
9563 "
9564 {
9565 int endian = (WORDS_BIG_ENDIAN == 0);
9566 long l[2];
9567 REAL_VALUE_TYPE rv;
9568 #if HOST_BITS_PER_WIDE_INT >= 64
9569 HOST_WIDE_INT val;
9570 #endif
9572 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9573 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9575 operands[2] = gen_lowpart (DImode, operands[0]);
9576 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9577 #if HOST_BITS_PER_WIDE_INT >= 64
9578 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9579 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9581 operands[3] = gen_int_mode (val, DImode);
9582 #else
9583 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
9584 #endif
9585 }")
9587 ;; Don't have reload use general registers to load a constant. First,
9588 ;; it might not work if the output operand is the equivalent of
9589 ;; a non-offsettable memref, but also it is less efficient than loading
9590 ;; the constant into an FP register, since it will probably be used there.
9591 ;; The "??" is a kludge until we can figure out a more reasonable way
9592 ;; of handling these non-offsettable values.
9593 (define_insn "*movdf_hardfloat32"
9594 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
9595 (match_operand:DF 1 "input_operand" "r,m,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
9596 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9597 && (gpc_reg_operand (operands[0], DFmode)
9598 || gpc_reg_operand (operands[1], DFmode))"
9599 "*
9600 {
9601 switch (which_alternative)
9602 {
9603 default:
9604 gcc_unreachable ();
9605 case 0:
9606 case 1:
9607 case 2:
9608 return \"#\";
9609 case 3:
9610 case 4:
9611 return \"xxlor %x0,%x1,%x1\";
9612 case 5:
9613 case 6:
9614 return \"lxsd%U1x %x0,%y1\";
9615 case 7:
9616 case 8:
9617 return \"stxsd%U0x %x1,%y0\";
9618 case 9:
9619 return \"fmr %0,%1\";
9620 case 10:
9621 return \"lfd%U1%X1 %0,%1\";
9622 case 11:
9623 return \"stfd%U0%X0 %1,%0\";
9624 case 12:
9625 return \"xxlxor %x0,%x0,%x0\";
9626 case 13:
9627 case 14:
9628 case 15:
9629 return \"#\";
9630 }
9631 }"
9632 [(set_attr "type" "two,load,store,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
9633 (set_attr "length" "8,16,16,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9635 (define_insn "*movdf_softfloat32"
9636 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
9637 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
9638 "! TARGET_POWERPC64
9639 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9640 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9641 && (gpc_reg_operand (operands[0], DFmode)
9642 || gpc_reg_operand (operands[1], DFmode))"
9643 "#"
9644 [(set_attr "type" "two,load,store,*,*,*")
9645 (set_attr "length" "8,8,8,8,12,16")])
9647 ; ld/std require word-aligned displacements -> 'Y' constraint.
9648 ; List Y->r and r->Y before r->r for reload.
9649 (define_insn "*movdf_hardfloat64_mfpgpr"
9650 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r,r,d")
9651 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
9652 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9653 && TARGET_DOUBLE_FLOAT
9654 && (gpc_reg_operand (operands[0], DFmode)
9655 || gpc_reg_operand (operands[1], DFmode))"
9656 "@
9657 std%U0%X0 %1,%0
9658 ld%U1%X1 %0,%1
9659 mr %0,%1
9660 xxlor %x0,%x1,%x1
9661 xxlor %x0,%x1,%x1
9662 lxsd%U1x %x0,%y1
9663 lxsd%U1x %x0,%y1
9664 stxsd%U0x %x1,%y0
9665 stxsd%U0x %x1,%y0
9666 fmr %0,%1
9667 lfd%U1%X1 %0,%1
9668 stfd%U0%X0 %1,%0
9669 xxlxor %x0,%x0,%x0
9670 mt%0 %1
9671 mf%1 %0
9672 {cror 0,0,0|nop}
9673 #
9674 #
9675 #
9676 mftgpr %0,%1
9677 mffgpr %0,%1"
9678 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
9679 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9681 ; ld/std require word-aligned displacements -> 'Y' constraint.
9682 ; List Y->r and r->Y before r->r for reload.
9683 (define_insn "*movdf_hardfloat64"
9684 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r")
9685 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
9686 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9687 && TARGET_DOUBLE_FLOAT
9688 && (gpc_reg_operand (operands[0], DFmode)
9689 || gpc_reg_operand (operands[1], DFmode))"
9690 "@
9691 std%U0%X0 %1,%0
9692 ld%U1%X1 %0,%1
9693 mr %0,%1
9694 xxlor %x0,%x1,%x1
9695 xxlor %x0,%x1,%x1
9696 lxsd%U1x %x0,%y1
9697 lxsd%U1x %x0,%y1
9698 stxsd%U0x %x1,%y0
9699 stxsd%U0x %x1,%y0
9700 fmr %0,%1
9701 lfd%U1%X1 %0,%1
9702 stfd%U0%X0 %1,%0
9703 xxlxor %x0,%x0,%x0
9704 mt%0 %1
9705 mf%1 %0
9706 {cror 0,0,0|nop}
9707 #
9708 #
9709 #"
9710 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
9711 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9713 (define_insn "*movdf_softfloat64"
9714 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
9715 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
9716 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9717 && (gpc_reg_operand (operands[0], DFmode)
9718 || gpc_reg_operand (operands[1], DFmode))"
9719 "@
9720 ld%U1%X1 %0,%1
9721 std%U0%X0 %1,%0
9722 mr %0,%1
9723 mt%0 %1
9724 mf%1 %0
9725 #
9726 #
9727 #
9728 {cror 0,0,0|nop}"
9729 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
9730 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9731 \f
9732 (define_expand "movtf"
9733 [(set (match_operand:TF 0 "general_operand" "")
9734 (match_operand:TF 1 "any_operand" ""))]
9735 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
9736 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
9738 ; It's important to list the o->f and f->o moves before f->f because
9739 ; otherwise reload, given m->f, will try to pick f->f and reload it,
9740 ; which doesn't make progress. Likewise r->Y must be before r->r.
9741 (define_insn_and_split "*movtf_internal"
9742 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
9743 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
9744 "!TARGET_IEEEQUAD
9745 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
9746 && (gpc_reg_operand (operands[0], TFmode)
9747 || gpc_reg_operand (operands[1], TFmode))"
9748 "#"
9749 "&& reload_completed"
9750 [(pc)]
9751 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9752 [(set_attr "length" "8,8,8,20,20,16")])
9754 (define_insn_and_split "*movtf_softfloat"
9755 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
9756 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
9757 "!TARGET_IEEEQUAD
9758 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
9759 && (gpc_reg_operand (operands[0], TFmode)
9760 || gpc_reg_operand (operands[1], TFmode))"
9761 "#"
9762 "&& reload_completed"
9763 [(pc)]
9764 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9765 [(set_attr "length" "20,20,16")])
9767 (define_expand "extenddftf2"
9768 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9769 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9770 "!TARGET_IEEEQUAD
9771 && TARGET_HARD_FLOAT
9772 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9773 && TARGET_LONG_DOUBLE_128"
9774 {
9775 if (TARGET_E500_DOUBLE)
9776 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9777 else
9778 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9779 DONE;
9780 })
9782 (define_expand "extenddftf2_fprs"
9783 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9784 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9785 (use (match_dup 2))])]
9786 "!TARGET_IEEEQUAD
9787 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9788 && TARGET_LONG_DOUBLE_128"
9789 {
9790 operands[2] = CONST0_RTX (DFmode);
9791 /* Generate GOT reference early for SVR4 PIC. */
9792 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9793 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9794 })
9796 (define_insn_and_split "*extenddftf2_internal"
9797 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
9798 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
9799 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
9800 "!TARGET_IEEEQUAD
9801 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9802 && TARGET_LONG_DOUBLE_128"
9803 "#"
9804 "&& reload_completed"
9805 [(pc)]
9806 {
9807 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9808 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9809 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9810 operands[1]);
9811 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9812 operands[2]);
9813 DONE;
9814 })
9816 (define_expand "extendsftf2"
9817 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9818 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9819 "!TARGET_IEEEQUAD
9820 && TARGET_HARD_FLOAT
9821 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9822 && TARGET_LONG_DOUBLE_128"
9823 {
9824 rtx tmp = gen_reg_rtx (DFmode);
9825 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9826 emit_insn (gen_extenddftf2 (operands[0], tmp));
9827 DONE;
9828 })
9830 (define_expand "trunctfdf2"
9831 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9832 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9833 "!TARGET_IEEEQUAD
9834 && TARGET_HARD_FLOAT
9835 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9836 && TARGET_LONG_DOUBLE_128"
9837 "")
9839 (define_insn_and_split "trunctfdf2_internal1"
9840 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9841 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9842 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9843 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9844 "@
9845 #
9846 fmr %0,%1"
9847 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9848 [(const_int 0)]
9849 {
9850 emit_note (NOTE_INSN_DELETED);
9851 DONE;
9852 }
9853 [(set_attr "type" "fp")])
9855 (define_insn "trunctfdf2_internal2"
9856 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9857 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9858 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9859 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9860 && TARGET_LONG_DOUBLE_128"
9861 "fadd %0,%1,%L1"
9862 [(set_attr "type" "fp")
9863 (set_attr "fp_type" "fp_addsub_d")])
9865 (define_expand "trunctfsf2"
9866 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9867 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9868 "!TARGET_IEEEQUAD
9869 && TARGET_HARD_FLOAT
9870 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9871 && TARGET_LONG_DOUBLE_128"
9872 {
9873 if (TARGET_E500_DOUBLE)
9874 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9875 else
9876 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9877 DONE;
9878 })
9880 (define_insn_and_split "trunctfsf2_fprs"
9881 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9882 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9883 (clobber (match_scratch:DF 2 "=d"))]
9884 "!TARGET_IEEEQUAD
9885 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9886 && TARGET_LONG_DOUBLE_128"
9887 "#"
9888 "&& reload_completed"
9889 [(set (match_dup 2)
9890 (float_truncate:DF (match_dup 1)))
9891 (set (match_dup 0)
9892 (float_truncate:SF (match_dup 2)))]
9893 "")
9895 (define_expand "floatsitf2"
9896 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9897 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9898 "!TARGET_IEEEQUAD
9899 && TARGET_HARD_FLOAT
9900 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9901 && TARGET_LONG_DOUBLE_128"
9902 {
9903 rtx tmp = gen_reg_rtx (DFmode);
9904 expand_float (tmp, operands[1], false);
9905 emit_insn (gen_extenddftf2 (operands[0], tmp));
9906 DONE;
9907 })
9909 ; fadd, but rounding towards zero.
9910 ; This is probably not the optimal code sequence.
9911 (define_insn "fix_trunc_helper"
9912 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9913 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9914 UNSPEC_FIX_TRUNC_TF))
9915 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9916 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9917 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9918 [(set_attr "type" "fp")
9919 (set_attr "length" "20")])
9921 (define_expand "fix_trunctfsi2"
9922 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9923 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9924 "!TARGET_IEEEQUAD
9925 && (TARGET_POWER2 || TARGET_POWERPC)
9926 && TARGET_HARD_FLOAT
9927 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9928 && TARGET_LONG_DOUBLE_128"
9929 {
9930 if (TARGET_E500_DOUBLE)
9931 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9932 else
9933 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9934 DONE;
9935 })
9937 (define_expand "fix_trunctfsi2_fprs"
9938 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9939 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9940 (clobber (match_dup 2))
9941 (clobber (match_dup 3))
9942 (clobber (match_dup 4))
9943 (clobber (match_dup 5))])]
9944 "!TARGET_IEEEQUAD
9945 && (TARGET_POWER2 || TARGET_POWERPC)
9946 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9947 {
9948 operands[2] = gen_reg_rtx (DFmode);
9949 operands[3] = gen_reg_rtx (DFmode);
9950 operands[4] = gen_reg_rtx (DImode);
9951 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
9952 })
9954 (define_insn_and_split "*fix_trunctfsi2_internal"
9955 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9956 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9957 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9958 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9959 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9960 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9961 "!TARGET_IEEEQUAD
9962 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9963 "#"
9964 ""
9965 [(pc)]
9966 {
9967 rtx lowword;
9968 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9970 gcc_assert (MEM_P (operands[5]));
9971 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9973 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
9974 emit_move_insn (operands[5], operands[4]);
9975 emit_move_insn (operands[0], lowword);
9976 DONE;
9977 })
9979 (define_expand "negtf2"
9980 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9981 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9982 "!TARGET_IEEEQUAD
9983 && TARGET_HARD_FLOAT
9984 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9985 && TARGET_LONG_DOUBLE_128"
9986 "")
9988 (define_insn "negtf2_internal"
9989 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9990 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9991 "!TARGET_IEEEQUAD
9992 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9993 "*
9994 {
9995 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9996 return \"fneg %L0,%L1\;fneg %0,%1\";
9997 else
9998 return \"fneg %0,%1\;fneg %L0,%L1\";
9999 }"
10000 [(set_attr "type" "fp")
10001 (set_attr "length" "8")])
10003 (define_expand "abstf2"
10004 [(set (match_operand:TF 0 "gpc_reg_operand" "")
10005 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
10006 "!TARGET_IEEEQUAD
10007 && TARGET_HARD_FLOAT
10008 && (TARGET_FPRS || TARGET_E500_DOUBLE)
10009 && TARGET_LONG_DOUBLE_128"
10010 "
10011 {
10012 rtx label = gen_label_rtx ();
10013 if (TARGET_E500_DOUBLE)
10014 {
10015 if (flag_finite_math_only && !flag_trapping_math)
10016 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
10017 else
10018 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
10019 }
10020 else
10021 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
10022 emit_label (label);
10023 DONE;
10024 }")
10026 (define_expand "abstf2_internal"
10027 [(set (match_operand:TF 0 "gpc_reg_operand" "")
10028 (match_operand:TF 1 "gpc_reg_operand" ""))
10029 (set (match_dup 3) (match_dup 5))
10030 (set (match_dup 5) (abs:DF (match_dup 5)))
10031 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
10032 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
10033 (label_ref (match_operand 2 "" ""))
10034 (pc)))
10035 (set (match_dup 6) (neg:DF (match_dup 6)))]
10036 "!TARGET_IEEEQUAD
10037 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10038 && TARGET_LONG_DOUBLE_128"
10039 "
10040 {
10041 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
10042 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
10043 operands[3] = gen_reg_rtx (DFmode);
10044 operands[4] = gen_reg_rtx (CCFPmode);
10045 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
10046 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
10047 }")
10048 \f
10049 ;; Next come the multi-word integer load and store and the load and store
10050 ;; multiple insns.
10052 ; List r->r after r->"o<>", otherwise reload will try to reload a
10053 ; non-offsettable address by using r->r which won't make progress.
10054 (define_insn "*movdi_internal32"
10055 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r")
10056 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
10057 "! TARGET_POWERPC64
10058 && (gpc_reg_operand (operands[0], DImode)
10059 || gpc_reg_operand (operands[1], DImode))"
10060 "@
10061 #
10062 #
10063 #
10064 fmr %0,%1
10065 lfd%U1%X1 %0,%1
10066 stfd%U0%X0 %1,%0
10067 #"
10068 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
10070 (define_split
10071 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10072 (match_operand:DI 1 "const_int_operand" ""))]
10073 "! TARGET_POWERPC64 && reload_completed"
10074 [(set (match_dup 2) (match_dup 4))
10075 (set (match_dup 3) (match_dup 1))]
10076 "
10077 {
10078 HOST_WIDE_INT value = INTVAL (operands[1]);
10079 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10080 DImode);
10081 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10082 DImode);
10083 #if HOST_BITS_PER_WIDE_INT == 32
10084 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
10085 #else
10086 operands[4] = GEN_INT (value >> 32);
10087 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
10088 #endif
10089 }")
10091 (define_split
10092 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
10093 (match_operand:DIFD 1 "input_operand" ""))]
10094 "reload_completed && !TARGET_POWERPC64
10095 && gpr_or_gpr_p (operands[0], operands[1])"
10096 [(pc)]
10097 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10099 (define_insn "*movdi_mfpgpr"
10100 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
10101 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
10102 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
10103 && (gpc_reg_operand (operands[0], DImode)
10104 || gpc_reg_operand (operands[1], DImode))"
10105 "@
10106 mr %0,%1
10107 ld%U1%X1 %0,%1
10108 std%U0%X0 %1,%0
10109 li %0,%1
10110 lis %0,%v1
10111 #
10112 {cal|la} %0,%a1
10113 fmr %0,%1
10114 lfd%U1%X1 %0,%1
10115 stfd%U0%X0 %1,%0
10116 mf%1 %0
10117 mt%0 %1
10118 {cror 0,0,0|nop}
10119 mftgpr %0,%1
10120 mffgpr %0,%1"
10121 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
10122 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
10124 (define_insn "*movdi_internal64"
10125 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
10126 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
10127 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
10128 && (gpc_reg_operand (operands[0], DImode)
10129 || gpc_reg_operand (operands[1], DImode))"
10130 "@
10131 mr %0,%1
10132 ld%U1%X1 %0,%1
10133 std%U0%X0 %1,%0
10134 li %0,%1
10135 lis %0,%v1
10136 #
10137 {cal|la} %0,%a1
10138 fmr %0,%1
10139 lfd%U1%X1 %0,%1
10140 stfd%U0%X0 %1,%0
10141 mf%1 %0
10142 mt%0 %1
10143 {cror 0,0,0|nop}"
10144 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
10145 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
10147 ;; immediate value valid for a single instruction hiding in a const_double
10148 (define_insn ""
10149 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10150 (match_operand:DI 1 "const_double_operand" "F"))]
10151 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
10152 && GET_CODE (operands[1]) == CONST_DOUBLE
10153 && num_insns_constant (operands[1], DImode) == 1"
10154 "*
10155 {
10156 return ((unsigned HOST_WIDE_INT)
10157 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
10158 ? \"li %0,%1\" : \"lis %0,%v1\";
10159 }")
10161 ;; Generate all one-bits and clear left or right.
10162 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
10163 (define_split
10164 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10165 (match_operand:DI 1 "mask64_operand" ""))]
10166 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10167 [(set (match_dup 0) (const_int -1))
10168 (set (match_dup 0)
10169 (and:DI (rotate:DI (match_dup 0)
10170 (const_int 0))
10171 (match_dup 1)))]
10172 "")
10174 ;; Split a load of a large constant into the appropriate five-instruction
10175 ;; sequence. Handle anything in a constant number of insns.
10176 ;; When non-easy constants can go in the TOC, this should use
10177 ;; easy_fp_constant predicate.
10178 (define_split
10179 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10180 (match_operand:DI 1 "const_int_operand" ""))]
10181 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10182 [(set (match_dup 0) (match_dup 2))
10183 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10184 "
10185 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10187 if (tem == operands[0])
10188 DONE;
10189 else
10190 FAIL;
10191 }")
10193 (define_split
10194 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10195 (match_operand:DI 1 "const_double_operand" ""))]
10196 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10197 [(set (match_dup 0) (match_dup 2))
10198 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10199 "
10200 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10202 if (tem == operands[0])
10203 DONE;
10204 else
10205 FAIL;
10206 }")
10207 \f
10208 ;; TImode is similar, except that we usually want to compute the address into
10209 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
10210 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
10212 ;; We say that MQ is clobbered in the last alternative because the first
10213 ;; alternative would never get used otherwise since it would need a reload
10214 ;; while the 2nd alternative would not. We put memory cases first so they
10215 ;; are preferred. Otherwise, we'd try to reload the output instead of
10216 ;; giving the SCRATCH mq.
10218 (define_insn "*movti_power"
10219 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
10220 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
10221 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
10222 "TARGET_POWER && ! TARGET_POWERPC64
10223 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
10224 "*
10225 {
10226 switch (which_alternative)
10227 {
10228 default:
10229 gcc_unreachable ();
10231 case 0:
10232 if (TARGET_STRING)
10233 return \"{stsi|stswi} %1,%P0,16\";
10234 case 1:
10235 case 2:
10236 return \"#\";
10237 case 3:
10238 /* If the address is not used in the output, we can use lsi. Otherwise,
10239 fall through to generating four loads. */
10240 if (TARGET_STRING
10241 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10242 return \"{lsi|lswi} %0,%P1,16\";
10243 /* ... fall through ... */
10244 case 4:
10245 case 5:
10246 return \"#\";
10247 }
10248 }"
10249 [(set_attr "type" "store,store,*,load,load,*")])
10251 (define_insn "*movti_string"
10252 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
10253 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
10254 "! TARGET_POWER && ! TARGET_POWERPC64
10255 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
10256 "*
10257 {
10258 switch (which_alternative)
10259 {
10260 default:
10261 gcc_unreachable ();
10262 case 0:
10263 if (TARGET_STRING)
10264 return \"{stsi|stswi} %1,%P0,16\";
10265 case 1:
10266 case 2:
10267 return \"#\";
10268 case 3:
10269 /* If the address is not used in the output, we can use lsi. Otherwise,
10270 fall through to generating four loads. */
10271 if (TARGET_STRING
10272 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10273 return \"{lsi|lswi} %0,%P1,16\";
10274 /* ... fall through ... */
10275 case 4:
10276 case 5:
10277 return \"#\";
10278 }
10279 }"
10280 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
10281 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
10282 (const_string "always")
10283 (const_string "conditional")))])
10285 (define_insn "*movti_ppc64"
10286 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
10287 (match_operand:TI 1 "input_operand" "r,r,m"))]
10288 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
10289 || gpc_reg_operand (operands[1], TImode)))
10290 && VECTOR_MEM_NONE_P (TImode)"
10291 "#"
10292 [(set_attr "type" "*,store,load")])
10294 (define_split
10295 [(set (match_operand:TI 0 "gpc_reg_operand" "")
10296 (match_operand:TI 1 "const_double_operand" ""))]
10297 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
10298 [(set (match_dup 2) (match_dup 4))
10299 (set (match_dup 3) (match_dup 5))]
10300 "
10301 {
10302 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10303 TImode);
10304 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10305 TImode);
10306 if (GET_CODE (operands[1]) == CONST_DOUBLE)
10307 {
10308 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
10309 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
10310 }
10311 else if (GET_CODE (operands[1]) == CONST_INT)
10312 {
10313 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
10314 operands[5] = operands[1];
10315 }
10316 else
10317 FAIL;
10318 }")
10320 (define_split
10321 [(set (match_operand:TI 0 "nonimmediate_operand" "")
10322 (match_operand:TI 1 "input_operand" ""))]
10323 "reload_completed && VECTOR_MEM_NONE_P (TImode)
10324 && gpr_or_gpr_p (operands[0], operands[1])"
10325 [(pc)]
10326 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10327 \f
10328 (define_expand "load_multiple"
10329 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10330 (match_operand:SI 1 "" ""))
10331 (use (match_operand:SI 2 "" ""))])]
10332 "TARGET_STRING && !TARGET_POWERPC64"
10333 "
10334 {
10335 int regno;
10336 int count;
10337 rtx op1;
10338 int i;
10340 /* Support only loading a constant number of fixed-point registers from
10341 memory and only bother with this if more than two; the machine
10342 doesn't support more than eight. */
10343 if (GET_CODE (operands[2]) != CONST_INT
10344 || INTVAL (operands[2]) <= 2
10345 || INTVAL (operands[2]) > 8
10346 || GET_CODE (operands[1]) != MEM
10347 || GET_CODE (operands[0]) != REG
10348 || REGNO (operands[0]) >= 32)
10349 FAIL;
10351 count = INTVAL (operands[2]);
10352 regno = REGNO (operands[0]);
10354 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10355 op1 = replace_equiv_address (operands[1],
10356 force_reg (SImode, XEXP (operands[1], 0)));
10358 for (i = 0; i < count; i++)
10359 XVECEXP (operands[3], 0, i)
10360 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
10361 adjust_address_nv (op1, SImode, i * 4));
10362 }")
10364 (define_insn "*ldmsi8"
10365 [(match_parallel 0 "load_multiple_operation"
10366 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10367 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10368 (set (match_operand:SI 3 "gpc_reg_operand" "")
10369 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10370 (set (match_operand:SI 4 "gpc_reg_operand" "")
10371 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10372 (set (match_operand:SI 5 "gpc_reg_operand" "")
10373 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10374 (set (match_operand:SI 6 "gpc_reg_operand" "")
10375 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10376 (set (match_operand:SI 7 "gpc_reg_operand" "")
10377 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10378 (set (match_operand:SI 8 "gpc_reg_operand" "")
10379 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
10380 (set (match_operand:SI 9 "gpc_reg_operand" "")
10381 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
10382 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10383 "*
10384 { return rs6000_output_load_multiple (operands); }"
10385 [(set_attr "type" "load_ux")
10386 (set_attr "length" "32")])
10388 (define_insn "*ldmsi7"
10389 [(match_parallel 0 "load_multiple_operation"
10390 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10391 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10392 (set (match_operand:SI 3 "gpc_reg_operand" "")
10393 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10394 (set (match_operand:SI 4 "gpc_reg_operand" "")
10395 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10396 (set (match_operand:SI 5 "gpc_reg_operand" "")
10397 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10398 (set (match_operand:SI 6 "gpc_reg_operand" "")
10399 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10400 (set (match_operand:SI 7 "gpc_reg_operand" "")
10401 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10402 (set (match_operand:SI 8 "gpc_reg_operand" "")
10403 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
10404 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10405 "*
10406 { return rs6000_output_load_multiple (operands); }"
10407 [(set_attr "type" "load_ux")
10408 (set_attr "length" "32")])
10410 (define_insn "*ldmsi6"
10411 [(match_parallel 0 "load_multiple_operation"
10412 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10413 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10414 (set (match_operand:SI 3 "gpc_reg_operand" "")
10415 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10416 (set (match_operand:SI 4 "gpc_reg_operand" "")
10417 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10418 (set (match_operand:SI 5 "gpc_reg_operand" "")
10419 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10420 (set (match_operand:SI 6 "gpc_reg_operand" "")
10421 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10422 (set (match_operand:SI 7 "gpc_reg_operand" "")
10423 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
10424 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10425 "*
10426 { return rs6000_output_load_multiple (operands); }"
10427 [(set_attr "type" "load_ux")
10428 (set_attr "length" "32")])
10430 (define_insn "*ldmsi5"
10431 [(match_parallel 0 "load_multiple_operation"
10432 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10433 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10434 (set (match_operand:SI 3 "gpc_reg_operand" "")
10435 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10436 (set (match_operand:SI 4 "gpc_reg_operand" "")
10437 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10438 (set (match_operand:SI 5 "gpc_reg_operand" "")
10439 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10440 (set (match_operand:SI 6 "gpc_reg_operand" "")
10441 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10442 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10443 "*
10444 { return rs6000_output_load_multiple (operands); }"
10445 [(set_attr "type" "load_ux")
10446 (set_attr "length" "32")])
10448 (define_insn "*ldmsi4"
10449 [(match_parallel 0 "load_multiple_operation"
10450 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10451 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10452 (set (match_operand:SI 3 "gpc_reg_operand" "")
10453 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10454 (set (match_operand:SI 4 "gpc_reg_operand" "")
10455 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10456 (set (match_operand:SI 5 "gpc_reg_operand" "")
10457 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10458 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10459 "*
10460 { return rs6000_output_load_multiple (operands); }"
10461 [(set_attr "type" "load_ux")
10462 (set_attr "length" "32")])
10464 (define_insn "*ldmsi3"
10465 [(match_parallel 0 "load_multiple_operation"
10466 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10467 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10468 (set (match_operand:SI 3 "gpc_reg_operand" "")
10469 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10470 (set (match_operand:SI 4 "gpc_reg_operand" "")
10471 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10472 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10473 "*
10474 { return rs6000_output_load_multiple (operands); }"
10475 [(set_attr "type" "load_ux")
10476 (set_attr "length" "32")])
10478 (define_expand "store_multiple"
10479 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10480 (match_operand:SI 1 "" ""))
10481 (clobber (scratch:SI))
10482 (use (match_operand:SI 2 "" ""))])]
10483 "TARGET_STRING && !TARGET_POWERPC64"
10484 "
10485 {
10486 int regno;
10487 int count;
10488 rtx to;
10489 rtx op0;
10490 int i;
10492 /* Support only storing a constant number of fixed-point registers to
10493 memory and only bother with this if more than two; the machine
10494 doesn't support more than eight. */
10495 if (GET_CODE (operands[2]) != CONST_INT
10496 || INTVAL (operands[2]) <= 2
10497 || INTVAL (operands[2]) > 8
10498 || GET_CODE (operands[0]) != MEM
10499 || GET_CODE (operands[1]) != REG
10500 || REGNO (operands[1]) >= 32)
10501 FAIL;
10503 count = INTVAL (operands[2]);
10504 regno = REGNO (operands[1]);
10506 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10507 to = force_reg (SImode, XEXP (operands[0], 0));
10508 op0 = replace_equiv_address (operands[0], to);
10510 XVECEXP (operands[3], 0, 0)
10511 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10512 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10513 gen_rtx_SCRATCH (SImode));
10515 for (i = 1; i < count; i++)
10516 XVECEXP (operands[3], 0, i + 1)
10517 = gen_rtx_SET (VOIDmode,
10518 adjust_address_nv (op0, SImode, i * 4),
10519 gen_rtx_REG (SImode, regno + i));
10520 }")
10522 (define_insn "*stmsi8"
10523 [(match_parallel 0 "store_multiple_operation"
10524 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10525 (match_operand:SI 2 "gpc_reg_operand" "r"))
10526 (clobber (match_scratch:SI 3 "=X"))
10527 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10528 (match_operand:SI 4 "gpc_reg_operand" "r"))
10529 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10530 (match_operand:SI 5 "gpc_reg_operand" "r"))
10531 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10532 (match_operand:SI 6 "gpc_reg_operand" "r"))
10533 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10534 (match_operand:SI 7 "gpc_reg_operand" "r"))
10535 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10536 (match_operand:SI 8 "gpc_reg_operand" "r"))
10537 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10538 (match_operand:SI 9 "gpc_reg_operand" "r"))
10539 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10540 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10541 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10542 "{stsi|stswi} %2,%1,%O0"
10543 [(set_attr "type" "store_ux")
10544 (set_attr "cell_micro" "always")])
10546 (define_insn "*stmsi7"
10547 [(match_parallel 0 "store_multiple_operation"
10548 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10549 (match_operand:SI 2 "gpc_reg_operand" "r"))
10550 (clobber (match_scratch:SI 3 "=X"))
10551 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10552 (match_operand:SI 4 "gpc_reg_operand" "r"))
10553 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10554 (match_operand:SI 5 "gpc_reg_operand" "r"))
10555 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10556 (match_operand:SI 6 "gpc_reg_operand" "r"))
10557 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10558 (match_operand:SI 7 "gpc_reg_operand" "r"))
10559 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10560 (match_operand:SI 8 "gpc_reg_operand" "r"))
10561 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10562 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10563 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10564 "{stsi|stswi} %2,%1,%O0"
10565 [(set_attr "type" "store_ux")
10566 (set_attr "cell_micro" "always")])
10568 (define_insn "*stmsi6"
10569 [(match_parallel 0 "store_multiple_operation"
10570 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10571 (match_operand:SI 2 "gpc_reg_operand" "r"))
10572 (clobber (match_scratch:SI 3 "=X"))
10573 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10574 (match_operand:SI 4 "gpc_reg_operand" "r"))
10575 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10576 (match_operand:SI 5 "gpc_reg_operand" "r"))
10577 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10578 (match_operand:SI 6 "gpc_reg_operand" "r"))
10579 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10580 (match_operand:SI 7 "gpc_reg_operand" "r"))
10581 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10582 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10583 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10584 "{stsi|stswi} %2,%1,%O0"
10585 [(set_attr "type" "store_ux")
10586 (set_attr "cell_micro" "always")])
10588 (define_insn "*stmsi5"
10589 [(match_parallel 0 "store_multiple_operation"
10590 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10591 (match_operand:SI 2 "gpc_reg_operand" "r"))
10592 (clobber (match_scratch:SI 3 "=X"))
10593 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10594 (match_operand:SI 4 "gpc_reg_operand" "r"))
10595 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10596 (match_operand:SI 5 "gpc_reg_operand" "r"))
10597 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10598 (match_operand:SI 6 "gpc_reg_operand" "r"))
10599 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10600 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10601 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10602 "{stsi|stswi} %2,%1,%O0"
10603 [(set_attr "type" "store_ux")
10604 (set_attr "cell_micro" "always")])
10606 (define_insn "*stmsi4"
10607 [(match_parallel 0 "store_multiple_operation"
10608 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10609 (match_operand:SI 2 "gpc_reg_operand" "r"))
10610 (clobber (match_scratch:SI 3 "=X"))
10611 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10612 (match_operand:SI 4 "gpc_reg_operand" "r"))
10613 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10614 (match_operand:SI 5 "gpc_reg_operand" "r"))
10615 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10616 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10617 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10618 "{stsi|stswi} %2,%1,%O0"
10619 [(set_attr "type" "store_ux")
10620 (set_attr "cell_micro" "always")])
10622 (define_insn "*stmsi3"
10623 [(match_parallel 0 "store_multiple_operation"
10624 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10625 (match_operand:SI 2 "gpc_reg_operand" "r"))
10626 (clobber (match_scratch:SI 3 "=X"))
10627 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10628 (match_operand:SI 4 "gpc_reg_operand" "r"))
10629 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10630 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10631 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10632 "{stsi|stswi} %2,%1,%O0"
10633 [(set_attr "type" "store_ux")
10634 (set_attr "cell_micro" "always")])
10636 (define_insn "*stmsi8_power"
10637 [(match_parallel 0 "store_multiple_operation"
10638 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10639 (match_operand:SI 2 "gpc_reg_operand" "r"))
10640 (clobber (match_scratch:SI 3 "=q"))
10641 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10642 (match_operand:SI 4 "gpc_reg_operand" "r"))
10643 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10644 (match_operand:SI 5 "gpc_reg_operand" "r"))
10645 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10646 (match_operand:SI 6 "gpc_reg_operand" "r"))
10647 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10648 (match_operand:SI 7 "gpc_reg_operand" "r"))
10649 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10650 (match_operand:SI 8 "gpc_reg_operand" "r"))
10651 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10652 (match_operand:SI 9 "gpc_reg_operand" "r"))
10653 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10654 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10655 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10656 "{stsi|stswi} %2,%1,%O0"
10657 [(set_attr "type" "store_ux")
10658 (set_attr "cell_micro" "always")])
10660 (define_insn "*stmsi7_power"
10661 [(match_parallel 0 "store_multiple_operation"
10662 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10663 (match_operand:SI 2 "gpc_reg_operand" "r"))
10664 (clobber (match_scratch:SI 3 "=q"))
10665 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10666 (match_operand:SI 4 "gpc_reg_operand" "r"))
10667 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10668 (match_operand:SI 5 "gpc_reg_operand" "r"))
10669 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10670 (match_operand:SI 6 "gpc_reg_operand" "r"))
10671 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10672 (match_operand:SI 7 "gpc_reg_operand" "r"))
10673 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10674 (match_operand:SI 8 "gpc_reg_operand" "r"))
10675 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10676 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10677 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10678 "{stsi|stswi} %2,%1,%O0"
10679 [(set_attr "type" "store_ux")
10680 (set_attr "cell_micro" "always")])
10682 (define_insn "*stmsi6_power"
10683 [(match_parallel 0 "store_multiple_operation"
10684 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10685 (match_operand:SI 2 "gpc_reg_operand" "r"))
10686 (clobber (match_scratch:SI 3 "=q"))
10687 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10688 (match_operand:SI 4 "gpc_reg_operand" "r"))
10689 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10690 (match_operand:SI 5 "gpc_reg_operand" "r"))
10691 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10692 (match_operand:SI 6 "gpc_reg_operand" "r"))
10693 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10694 (match_operand:SI 7 "gpc_reg_operand" "r"))
10695 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10696 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10697 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10698 "{stsi|stswi} %2,%1,%O0"
10699 [(set_attr "type" "store_ux")
10700 (set_attr "cell_micro" "always")])
10702 (define_insn "*stmsi5_power"
10703 [(match_parallel 0 "store_multiple_operation"
10704 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10705 (match_operand:SI 2 "gpc_reg_operand" "r"))
10706 (clobber (match_scratch:SI 3 "=q"))
10707 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10708 (match_operand:SI 4 "gpc_reg_operand" "r"))
10709 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10710 (match_operand:SI 5 "gpc_reg_operand" "r"))
10711 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10712 (match_operand:SI 6 "gpc_reg_operand" "r"))
10713 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10714 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10715 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10716 "{stsi|stswi} %2,%1,%O0"
10717 [(set_attr "type" "store_ux")
10718 (set_attr "cell_micro" "always")])
10720 (define_insn "*stmsi4_power"
10721 [(match_parallel 0 "store_multiple_operation"
10722 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10723 (match_operand:SI 2 "gpc_reg_operand" "r"))
10724 (clobber (match_scratch:SI 3 "=q"))
10725 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10726 (match_operand:SI 4 "gpc_reg_operand" "r"))
10727 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10728 (match_operand:SI 5 "gpc_reg_operand" "r"))
10729 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10730 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10731 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10732 "{stsi|stswi} %2,%1,%O0"
10733 [(set_attr "type" "store_ux")
10734 (set_attr "cell_micro" "always")])
10736 (define_insn "*stmsi3_power"
10737 [(match_parallel 0 "store_multiple_operation"
10738 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10739 (match_operand:SI 2 "gpc_reg_operand" "r"))
10740 (clobber (match_scratch:SI 3 "=q"))
10741 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10742 (match_operand:SI 4 "gpc_reg_operand" "r"))
10743 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10744 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10745 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10746 "{stsi|stswi} %2,%1,%O0"
10747 [(set_attr "type" "store_ux")
10748 (set_attr "cell_micro" "always")])
10749 \f
10750 (define_expand "setmemsi"
10751 [(parallel [(set (match_operand:BLK 0 "" "")
10752 (match_operand 2 "const_int_operand" ""))
10753 (use (match_operand:SI 1 "" ""))
10754 (use (match_operand:SI 3 "" ""))])]
10755 ""
10756 "
10757 {
10758 /* If value to set is not zero, use the library routine. */
10759 if (operands[2] != const0_rtx)
10760 FAIL;
10762 if (expand_block_clear (operands))
10763 DONE;
10764 else
10765 FAIL;
10766 }")
10768 ;; String/block move insn.
10769 ;; Argument 0 is the destination
10770 ;; Argument 1 is the source
10771 ;; Argument 2 is the length
10772 ;; Argument 3 is the alignment
10774 (define_expand "movmemsi"
10775 [(parallel [(set (match_operand:BLK 0 "" "")
10776 (match_operand:BLK 1 "" ""))
10777 (use (match_operand:SI 2 "" ""))
10778 (use (match_operand:SI 3 "" ""))])]
10779 ""
10780 "
10781 {
10782 if (expand_block_move (operands))
10783 DONE;
10784 else
10785 FAIL;
10786 }")
10788 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10789 ;; register allocator doesn't have a clue about allocating 8 word registers.
10790 ;; rD/rS = r5 is preferred, efficient form.
10791 (define_expand "movmemsi_8reg"
10792 [(parallel [(set (match_operand 0 "" "")
10793 (match_operand 1 "" ""))
10794 (use (match_operand 2 "" ""))
10795 (use (match_operand 3 "" ""))
10796 (clobber (reg:SI 5))
10797 (clobber (reg:SI 6))
10798 (clobber (reg:SI 7))
10799 (clobber (reg:SI 8))
10800 (clobber (reg:SI 9))
10801 (clobber (reg:SI 10))
10802 (clobber (reg:SI 11))
10803 (clobber (reg:SI 12))
10804 (clobber (match_scratch:SI 4 ""))])]
10805 "TARGET_STRING"
10806 "")
10808 (define_insn ""
10809 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10810 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10811 (use (match_operand:SI 2 "immediate_operand" "i"))
10812 (use (match_operand:SI 3 "immediate_operand" "i"))
10813 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10814 (clobber (reg:SI 6))
10815 (clobber (reg:SI 7))
10816 (clobber (reg:SI 8))
10817 (clobber (reg:SI 9))
10818 (clobber (reg:SI 10))
10819 (clobber (reg:SI 11))
10820 (clobber (reg:SI 12))
10821 (clobber (match_scratch:SI 5 "=q"))]
10822 "TARGET_STRING && TARGET_POWER
10823 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10824 || INTVAL (operands[2]) == 0)
10825 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10826 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10827 && REGNO (operands[4]) == 5"
10828 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10829 [(set_attr "type" "store_ux")
10830 (set_attr "cell_micro" "always")
10831 (set_attr "length" "8")])
10833 (define_insn ""
10834 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10835 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10836 (use (match_operand:SI 2 "immediate_operand" "i"))
10837 (use (match_operand:SI 3 "immediate_operand" "i"))
10838 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10839 (clobber (reg:SI 6))
10840 (clobber (reg:SI 7))
10841 (clobber (reg:SI 8))
10842 (clobber (reg:SI 9))
10843 (clobber (reg:SI 10))
10844 (clobber (reg:SI 11))
10845 (clobber (reg:SI 12))
10846 (clobber (match_scratch:SI 5 "=X"))]
10847 "TARGET_STRING && ! TARGET_POWER
10848 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10849 || INTVAL (operands[2]) == 0)
10850 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10851 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10852 && REGNO (operands[4]) == 5"
10853 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10854 [(set_attr "type" "store_ux")
10855 (set_attr "cell_micro" "always")
10856 (set_attr "length" "8")])
10858 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10859 ;; register allocator doesn't have a clue about allocating 6 word registers.
10860 ;; rD/rS = r5 is preferred, efficient form.
10861 (define_expand "movmemsi_6reg"
10862 [(parallel [(set (match_operand 0 "" "")
10863 (match_operand 1 "" ""))
10864 (use (match_operand 2 "" ""))
10865 (use (match_operand 3 "" ""))
10866 (clobber (reg:SI 5))
10867 (clobber (reg:SI 6))
10868 (clobber (reg:SI 7))
10869 (clobber (reg:SI 8))
10870 (clobber (reg:SI 9))
10871 (clobber (reg:SI 10))
10872 (clobber (match_scratch:SI 4 ""))])]
10873 "TARGET_STRING"
10874 "")
10876 (define_insn ""
10877 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10878 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10879 (use (match_operand:SI 2 "immediate_operand" "i"))
10880 (use (match_operand:SI 3 "immediate_operand" "i"))
10881 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10882 (clobber (reg:SI 6))
10883 (clobber (reg:SI 7))
10884 (clobber (reg:SI 8))
10885 (clobber (reg:SI 9))
10886 (clobber (reg:SI 10))
10887 (clobber (match_scratch:SI 5 "=q"))]
10888 "TARGET_STRING && TARGET_POWER
10889 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
10890 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10891 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10892 && REGNO (operands[4]) == 5"
10893 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10894 [(set_attr "type" "store_ux")
10895 (set_attr "cell_micro" "always")
10896 (set_attr "length" "8")])
10898 (define_insn ""
10899 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10900 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10901 (use (match_operand:SI 2 "immediate_operand" "i"))
10902 (use (match_operand:SI 3 "immediate_operand" "i"))
10903 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10904 (clobber (reg:SI 6))
10905 (clobber (reg:SI 7))
10906 (clobber (reg:SI 8))
10907 (clobber (reg:SI 9))
10908 (clobber (reg:SI 10))
10909 (clobber (match_scratch:SI 5 "=X"))]
10910 "TARGET_STRING && ! TARGET_POWER
10911 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10912 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10913 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10914 && REGNO (operands[4]) == 5"
10915 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10916 [(set_attr "type" "store_ux")
10917 (set_attr "cell_micro" "always")
10918 (set_attr "length" "8")])
10920 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10921 ;; problems with TImode.
10922 ;; rD/rS = r5 is preferred, efficient form.
10923 (define_expand "movmemsi_4reg"
10924 [(parallel [(set (match_operand 0 "" "")
10925 (match_operand 1 "" ""))
10926 (use (match_operand 2 "" ""))
10927 (use (match_operand 3 "" ""))
10928 (clobber (reg:SI 5))
10929 (clobber (reg:SI 6))
10930 (clobber (reg:SI 7))
10931 (clobber (reg:SI 8))
10932 (clobber (match_scratch:SI 4 ""))])]
10933 "TARGET_STRING"
10934 "")
10936 (define_insn ""
10937 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10938 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10939 (use (match_operand:SI 2 "immediate_operand" "i"))
10940 (use (match_operand:SI 3 "immediate_operand" "i"))
10941 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10942 (clobber (reg:SI 6))
10943 (clobber (reg:SI 7))
10944 (clobber (reg:SI 8))
10945 (clobber (match_scratch:SI 5 "=q"))]
10946 "TARGET_STRING && TARGET_POWER
10947 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10948 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10949 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10950 && REGNO (operands[4]) == 5"
10951 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10952 [(set_attr "type" "store_ux")
10953 (set_attr "cell_micro" "always")
10954 (set_attr "length" "8")])
10956 (define_insn ""
10957 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10958 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10959 (use (match_operand:SI 2 "immediate_operand" "i"))
10960 (use (match_operand:SI 3 "immediate_operand" "i"))
10961 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10962 (clobber (reg:SI 6))
10963 (clobber (reg:SI 7))
10964 (clobber (reg:SI 8))
10965 (clobber (match_scratch:SI 5 "=X"))]
10966 "TARGET_STRING && ! TARGET_POWER
10967 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10968 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10969 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10970 && REGNO (operands[4]) == 5"
10971 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10972 [(set_attr "type" "store_ux")
10973 (set_attr "cell_micro" "always")
10974 (set_attr "length" "8")])
10976 ;; Move up to 8 bytes at a time.
10977 (define_expand "movmemsi_2reg"
10978 [(parallel [(set (match_operand 0 "" "")
10979 (match_operand 1 "" ""))
10980 (use (match_operand 2 "" ""))
10981 (use (match_operand 3 "" ""))
10982 (clobber (match_scratch:DI 4 ""))
10983 (clobber (match_scratch:SI 5 ""))])]
10984 "TARGET_STRING && ! TARGET_POWERPC64"
10985 "")
10987 (define_insn ""
10988 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10989 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10990 (use (match_operand:SI 2 "immediate_operand" "i"))
10991 (use (match_operand:SI 3 "immediate_operand" "i"))
10992 (clobber (match_scratch:DI 4 "=&r"))
10993 (clobber (match_scratch:SI 5 "=q"))]
10994 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
10995 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10996 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10997 [(set_attr "type" "store_ux")
10998 (set_attr "cell_micro" "always")
10999 (set_attr "length" "8")])
11001 (define_insn ""
11002 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11003 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11004 (use (match_operand:SI 2 "immediate_operand" "i"))
11005 (use (match_operand:SI 3 "immediate_operand" "i"))
11006 (clobber (match_scratch:DI 4 "=&r"))
11007 (clobber (match_scratch:SI 5 "=X"))]
11008 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
11009 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
11010 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11011 [(set_attr "type" "store_ux")
11012 (set_attr "cell_micro" "always")
11013 (set_attr "length" "8")])
11015 ;; Move up to 4 bytes at a time.
11016 (define_expand "movmemsi_1reg"
11017 [(parallel [(set (match_operand 0 "" "")
11018 (match_operand 1 "" ""))
11019 (use (match_operand 2 "" ""))
11020 (use (match_operand 3 "" ""))
11021 (clobber (match_scratch:SI 4 ""))
11022 (clobber (match_scratch:SI 5 ""))])]
11023 "TARGET_STRING"
11024 "")
11026 (define_insn ""
11027 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11028 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11029 (use (match_operand:SI 2 "immediate_operand" "i"))
11030 (use (match_operand:SI 3 "immediate_operand" "i"))
11031 (clobber (match_scratch:SI 4 "=&r"))
11032 (clobber (match_scratch:SI 5 "=q"))]
11033 "TARGET_STRING && TARGET_POWER
11034 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
11035 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11036 [(set_attr "type" "store_ux")
11037 (set_attr "cell_micro" "always")
11038 (set_attr "length" "8")])
11040 (define_insn ""
11041 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
11042 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
11043 (use (match_operand:SI 2 "immediate_operand" "i"))
11044 (use (match_operand:SI 3 "immediate_operand" "i"))
11045 (clobber (match_scratch:SI 4 "=&r"))
11046 (clobber (match_scratch:SI 5 "=X"))]
11047 "TARGET_STRING && ! TARGET_POWER
11048 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
11049 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11050 [(set_attr "type" "store_ux")
11051 (set_attr "cell_micro" "always")
11052 (set_attr "length" "8")])
11053 \f
11054 ;; Define insns that do load or store with update. Some of these we can
11055 ;; get by using pre-decrement or pre-increment, but the hardware can also
11056 ;; do cases where the increment is not the size of the object.
11057 ;;
11058 ;; In all these cases, we use operands 0 and 1 for the register being
11059 ;; incremented because those are the operands that local-alloc will
11060 ;; tie and these are the pair most likely to be tieable (and the ones
11061 ;; that will benefit the most).
11063 (define_insn "*movdi_update1"
11064 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
11065 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
11066 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
11067 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
11068 (plus:DI (match_dup 1) (match_dup 2)))]
11069 "TARGET_POWERPC64 && TARGET_UPDATE
11070 && (!avoiding_indexed_address_p (DImode)
11071 || !gpc_reg_operand (operands[2], DImode))"
11072 "@
11073 ldux %3,%0,%2
11074 ldu %3,%2(%0)"
11075 [(set_attr "type" "load_ux,load_u")])
11077 (define_insn "movdi_<mode>_update"
11078 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
11079 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
11080 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
11081 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
11082 (plus:P (match_dup 1) (match_dup 2)))]
11083 "TARGET_POWERPC64 && TARGET_UPDATE
11084 && (!avoiding_indexed_address_p (Pmode)
11085 || !gpc_reg_operand (operands[2], Pmode)
11086 || (REG_P (operands[0])
11087 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
11088 "@
11089 stdux %3,%0,%2
11090 stdu %3,%2(%0)"
11091 [(set_attr "type" "store_ux,store_u")])
11093 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
11094 ;; needed for stack allocation, even if the user passes -mno-update.
11095 (define_insn "movdi_<mode>_update_stack"
11096 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
11097 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
11098 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
11099 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
11100 (plus:P (match_dup 1) (match_dup 2)))]
11101 "TARGET_POWERPC64"
11102 "@
11103 stdux %3,%0,%2
11104 stdu %3,%2(%0)"
11105 [(set_attr "type" "store_ux,store_u")])
11107 (define_insn "*movsi_update1"
11108 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11109 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11110 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11111 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11112 (plus:SI (match_dup 1) (match_dup 2)))]
11113 "TARGET_UPDATE
11114 && (!avoiding_indexed_address_p (SImode)
11115 || !gpc_reg_operand (operands[2], SImode))"
11116 "@
11117 {lux|lwzux} %3,%0,%2
11118 {lu|lwzu} %3,%2(%0)"
11119 [(set_attr "type" "load_ux,load_u")])
11121 (define_insn "*movsi_update2"
11122 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
11123 (sign_extend:DI
11124 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
11125 (match_operand:DI 2 "gpc_reg_operand" "r")))))
11126 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
11127 (plus:DI (match_dup 1) (match_dup 2)))]
11128 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
11129 && !avoiding_indexed_address_p (DImode)"
11130 "lwaux %3,%0,%2"
11131 [(set_attr "type" "load_ext_ux")])
11133 (define_insn "movsi_update"
11134 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11135 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11136 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11137 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11138 (plus:SI (match_dup 1) (match_dup 2)))]
11139 "TARGET_UPDATE
11140 && (!avoiding_indexed_address_p (SImode)
11141 || !gpc_reg_operand (operands[2], SImode)
11142 || (REG_P (operands[0])
11143 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
11144 "@
11145 {stux|stwux} %3,%0,%2
11146 {stu|stwu} %3,%2(%0)"
11147 [(set_attr "type" "store_ux,store_u")])
11149 ;; This is an unconditional pattern; needed for stack allocation, even
11150 ;; if the user passes -mno-update.
11151 (define_insn "movsi_update_stack"
11152 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11153 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11154 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11155 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11156 (plus:SI (match_dup 1) (match_dup 2)))]
11157 ""
11158 "@
11159 {stux|stwux} %3,%0,%2
11160 {stu|stwu} %3,%2(%0)"
11161 [(set_attr "type" "store_ux,store_u")])
11163 (define_insn "*movhi_update1"
11164 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
11165 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11166 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11167 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11168 (plus:SI (match_dup 1) (match_dup 2)))]
11169 "TARGET_UPDATE
11170 && (!avoiding_indexed_address_p (SImode)
11171 || !gpc_reg_operand (operands[2], SImode))"
11172 "@
11173 lhzux %3,%0,%2
11174 lhzu %3,%2(%0)"
11175 [(set_attr "type" "load_ux,load_u")])
11177 (define_insn "*movhi_update2"
11178 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11179 (zero_extend:SI
11180 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11181 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11182 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11183 (plus:SI (match_dup 1) (match_dup 2)))]
11184 "TARGET_UPDATE
11185 && (!avoiding_indexed_address_p (SImode)
11186 || !gpc_reg_operand (operands[2], SImode))"
11187 "@
11188 lhzux %3,%0,%2
11189 lhzu %3,%2(%0)"
11190 [(set_attr "type" "load_ux,load_u")])
11192 (define_insn "*movhi_update3"
11193 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11194 (sign_extend:SI
11195 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11196 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11197 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11198 (plus:SI (match_dup 1) (match_dup 2)))]
11199 "TARGET_UPDATE && rs6000_gen_cell_microcode
11200 && (!avoiding_indexed_address_p (SImode)
11201 || !gpc_reg_operand (operands[2], SImode))"
11202 "@
11203 lhaux %3,%0,%2
11204 lhau %3,%2(%0)"
11205 [(set_attr "type" "load_ext_ux,load_ext_u")])
11207 (define_insn "*movhi_update4"
11208 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11209 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11210 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
11211 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11212 (plus:SI (match_dup 1) (match_dup 2)))]
11213 "TARGET_UPDATE
11214 && (!avoiding_indexed_address_p (SImode)
11215 || !gpc_reg_operand (operands[2], SImode))"
11216 "@
11217 sthux %3,%0,%2
11218 sthu %3,%2(%0)"
11219 [(set_attr "type" "store_ux,store_u")])
11221 (define_insn "*movqi_update1"
11222 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
11223 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11224 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11225 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11226 (plus:SI (match_dup 1) (match_dup 2)))]
11227 "TARGET_UPDATE
11228 && (!avoiding_indexed_address_p (SImode)
11229 || !gpc_reg_operand (operands[2], SImode))"
11230 "@
11231 lbzux %3,%0,%2
11232 lbzu %3,%2(%0)"
11233 [(set_attr "type" "load_ux,load_u")])
11235 (define_insn "*movqi_update2"
11236 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11237 (zero_extend:SI
11238 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11239 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11240 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11241 (plus:SI (match_dup 1) (match_dup 2)))]
11242 "TARGET_UPDATE
11243 && (!avoiding_indexed_address_p (SImode)
11244 || !gpc_reg_operand (operands[2], SImode))"
11245 "@
11246 lbzux %3,%0,%2
11247 lbzu %3,%2(%0)"
11248 [(set_attr "type" "load_ux,load_u")])
11250 (define_insn "*movqi_update3"
11251 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11252 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11253 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
11254 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11255 (plus:SI (match_dup 1) (match_dup 2)))]
11256 "TARGET_UPDATE
11257 && (!avoiding_indexed_address_p (SImode)
11258 || !gpc_reg_operand (operands[2], SImode))"
11259 "@
11260 stbux %3,%0,%2
11261 stbu %3,%2(%0)"
11262 [(set_attr "type" "store_ux,store_u")])
11264 (define_insn "*movsf_update1"
11265 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
11266 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11267 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11268 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11269 (plus:SI (match_dup 1) (match_dup 2)))]
11270 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11271 && (!avoiding_indexed_address_p (SImode)
11272 || !gpc_reg_operand (operands[2], SImode))"
11273 "@
11274 lfsux %3,%0,%2
11275 lfsu %3,%2(%0)"
11276 [(set_attr "type" "fpload_ux,fpload_u")])
11278 (define_insn "*movsf_update2"
11279 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11280 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11281 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
11282 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11283 (plus:SI (match_dup 1) (match_dup 2)))]
11284 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11285 && (!avoiding_indexed_address_p (SImode)
11286 || !gpc_reg_operand (operands[2], SImode))"
11287 "@
11288 stfsux %3,%0,%2
11289 stfsu %3,%2(%0)"
11290 [(set_attr "type" "fpstore_ux,fpstore_u")])
11292 (define_insn "*movsf_update3"
11293 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
11294 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11295 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11296 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11297 (plus:SI (match_dup 1) (match_dup 2)))]
11298 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11299 && (!avoiding_indexed_address_p (SImode)
11300 || !gpc_reg_operand (operands[2], SImode))"
11301 "@
11302 {lux|lwzux} %3,%0,%2
11303 {lu|lwzu} %3,%2(%0)"
11304 [(set_attr "type" "load_ux,load_u")])
11306 (define_insn "*movsf_update4"
11307 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11308 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11309 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
11310 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11311 (plus:SI (match_dup 1) (match_dup 2)))]
11312 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11313 && (!avoiding_indexed_address_p (SImode)
11314 || !gpc_reg_operand (operands[2], SImode))"
11315 "@
11316 {stux|stwux} %3,%0,%2
11317 {stu|stwu} %3,%2(%0)"
11318 [(set_attr "type" "store_ux,store_u")])
11320 (define_insn "*movdf_update1"
11321 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
11322 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11323 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11324 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11325 (plus:SI (match_dup 1) (match_dup 2)))]
11326 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11327 && (!avoiding_indexed_address_p (SImode)
11328 || !gpc_reg_operand (operands[2], SImode))"
11329 "@
11330 lfdux %3,%0,%2
11331 lfdu %3,%2(%0)"
11332 [(set_attr "type" "fpload_ux,fpload_u")])
11334 (define_insn "*movdf_update2"
11335 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11336 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11337 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
11338 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11339 (plus:SI (match_dup 1) (match_dup 2)))]
11340 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11341 && (!avoiding_indexed_address_p (SImode)
11342 || !gpc_reg_operand (operands[2], SImode))"
11343 "@
11344 stfdux %3,%0,%2
11345 stfdu %3,%2(%0)"
11346 [(set_attr "type" "fpstore_ux,fpstore_u")])
11348 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
11350 (define_insn "*lfq_power2"
11351 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
11352 (match_operand:V2DF 1 "memory_operand" ""))]
11353 "TARGET_POWER2
11354 && TARGET_HARD_FLOAT && TARGET_FPRS"
11355 "lfq%U1%X1 %0,%1")
11357 (define_peephole2
11358 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11359 (match_operand:DF 1 "memory_operand" ""))
11360 (set (match_operand:DF 2 "gpc_reg_operand" "")
11361 (match_operand:DF 3 "memory_operand" ""))]
11362 "TARGET_POWER2
11363 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11364 && registers_ok_for_quad_peep (operands[0], operands[2])
11365 && mems_ok_for_quad_peep (operands[1], operands[3])"
11366 [(set (match_dup 0)
11367 (match_dup 1))]
11368 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
11369 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
11371 (define_insn "*stfq_power2"
11372 [(set (match_operand:V2DF 0 "memory_operand" "")
11373 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
11374 "TARGET_POWER2
11375 && TARGET_HARD_FLOAT && TARGET_FPRS"
11376 "stfq%U0%X0 %1,%0")
11379 (define_peephole2
11380 [(set (match_operand:DF 0 "memory_operand" "")
11381 (match_operand:DF 1 "gpc_reg_operand" ""))
11382 (set (match_operand:DF 2 "memory_operand" "")
11383 (match_operand:DF 3 "gpc_reg_operand" ""))]
11384 "TARGET_POWER2
11385 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11386 && registers_ok_for_quad_peep (operands[1], operands[3])
11387 && mems_ok_for_quad_peep (operands[0], operands[2])"
11388 [(set (match_dup 0)
11389 (match_dup 1))]
11390 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
11391 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
11393 ;; After inserting conditional returns we can sometimes have
11394 ;; unnecessary register moves. Unfortunately we cannot have a
11395 ;; modeless peephole here, because some single SImode sets have early
11396 ;; clobber outputs. Although those sets expand to multi-ppc-insn
11397 ;; sequences, using get_attr_length here will smash the operands
11398 ;; array. Neither is there an early_cobbler_p predicate.
11399 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
11400 (define_peephole2
11401 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11402 (match_operand:DF 1 "any_operand" ""))
11403 (set (match_operand:DF 2 "gpc_reg_operand" "")
11404 (match_dup 0))]
11405 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
11406 && peep2_reg_dead_p (2, operands[0])"
11407 [(set (match_dup 2) (match_dup 1))])
11409 (define_peephole2
11410 [(set (match_operand:SF 0 "gpc_reg_operand" "")
11411 (match_operand:SF 1 "any_operand" ""))
11412 (set (match_operand:SF 2 "gpc_reg_operand" "")
11413 (match_dup 0))]
11414 "peep2_reg_dead_p (2, operands[0])"
11415 [(set (match_dup 2) (match_dup 1))])
11417 \f
11418 ;; TLS support.
11420 ;; Mode attributes for different ABIs.
11421 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
11422 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
11423 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
11424 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
11426 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
11427 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11428 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11429 (match_operand 4 "" "g")))
11430 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11431 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11432 UNSPEC_TLSGD)
11433 (clobber (reg:SI LR_REGNO))]
11434 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11435 {
11436 if (TARGET_CMODEL != CMODEL_SMALL)
11437 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;bl %z3\;%.";
11438 else
11439 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;%.";
11440 }
11441 "&& TARGET_TLS_MARKERS"
11442 [(set (match_dup 0)
11443 (unspec:TLSmode [(match_dup 1)
11444 (match_dup 2)]
11445 UNSPEC_TLSGD))
11446 (parallel [(set (match_dup 0)
11447 (call (mem:TLSmode (match_dup 3))
11448 (match_dup 4)))
11449 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11450 (clobber (reg:SI LR_REGNO))])]
11451 ""
11452 [(set_attr "type" "two")
11453 (set (attr "length")
11454 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11455 (const_int 16)
11456 (const_int 12)))])
11458 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
11459 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11460 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11461 (match_operand 4 "" "g")))
11462 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11463 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11464 UNSPEC_TLSGD)
11465 (clobber (reg:SI LR_REGNO))]
11466 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11467 {
11468 if (flag_pic)
11469 {
11470 if (TARGET_SECURE_PLT && flag_pic == 2)
11471 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11472 else
11473 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11474 }
11475 else
11476 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11477 }
11478 "&& TARGET_TLS_MARKERS"
11479 [(set (match_dup 0)
11480 (unspec:TLSmode [(match_dup 1)
11481 (match_dup 2)]
11482 UNSPEC_TLSGD))
11483 (parallel [(set (match_dup 0)
11484 (call (mem:TLSmode (match_dup 3))
11485 (match_dup 4)))
11486 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11487 (clobber (reg:SI LR_REGNO))])]
11488 ""
11489 [(set_attr "type" "two")
11490 (set_attr "length" "8")])
11492 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
11493 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11494 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11495 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11496 UNSPEC_TLSGD))]
11497 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11498 "addi %0,%1,%2@got@tlsgd"
11499 "&& TARGET_CMODEL != CMODEL_SMALL"
11500 [(set (match_dup 3)
11501 (plus:TLSmode (match_dup 1)
11502 (high:TLSmode
11503 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD))))
11504 (set (match_dup 0)
11505 (lo_sum:TLSmode (match_dup 3)
11506 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
11507 "
11508 {
11509 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11510 }"
11511 [(set (attr "length")
11512 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11513 (const_int 8)
11514 (const_int 4)))])
11516 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
11517 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11518 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11519 (high:TLSmode
11520 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11521 UNSPEC_TLSGD))))]
11522 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11523 "addis %0,%1,%2@got@tlsgd@ha"
11524 [(set_attr "length" "4")])
11526 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
11527 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11528 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11529 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11530 UNSPEC_TLSGD)))]
11531 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11532 "addi %0,%1,%2@got@tlsgd@l"
11533 [(set_attr "length" "4")])
11535 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11536 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11537 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11538 (match_operand 2 "" "g")))
11539 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11540 UNSPEC_TLSGD)
11541 (clobber (reg:SI LR_REGNO))]
11542 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11543 "bl %z1(%3@tlsgd)\;%."
11544 [(set_attr "type" "branch")
11545 (set_attr "length" "8")])
11547 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11548 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11549 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11550 (match_operand 2 "" "g")))
11551 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11552 UNSPEC_TLSGD)
11553 (clobber (reg:SI LR_REGNO))]
11554 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11555 {
11556 if (flag_pic)
11557 {
11558 if (TARGET_SECURE_PLT && flag_pic == 2)
11559 return "bl %z1+32768(%3@tlsgd)@plt";
11560 return "bl %z1(%3@tlsgd)@plt";
11561 }
11562 return "bl %z1(%3@tlsgd)";
11563 }
11564 [(set_attr "type" "branch")
11565 (set_attr "length" "4")])
11567 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11568 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11569 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11570 (match_operand 3 "" "g")))
11571 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11572 UNSPEC_TLSLD)
11573 (clobber (reg:SI LR_REGNO))]
11574 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11575 {
11576 if (TARGET_CMODEL != CMODEL_SMALL)
11577 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;bl %z2\;%.";
11578 else
11579 return "addi %0,%1,%&@got@tlsld\;bl %z2\;%.";
11580 }
11581 "&& TARGET_TLS_MARKERS"
11582 [(set (match_dup 0)
11583 (unspec:TLSmode [(match_dup 1)]
11584 UNSPEC_TLSLD))
11585 (parallel [(set (match_dup 0)
11586 (call (mem:TLSmode (match_dup 2))
11587 (match_dup 3)))
11588 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11589 (clobber (reg:SI LR_REGNO))])]
11590 ""
11591 [(set_attr "type" "two")
11592 (set (attr "length")
11593 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11594 (const_int 16)
11595 (const_int 12)))])
11597 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11598 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11599 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11600 (match_operand 3 "" "g")))
11601 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11602 UNSPEC_TLSLD)
11603 (clobber (reg:SI LR_REGNO))]
11604 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11605 {
11606 if (flag_pic)
11607 {
11608 if (TARGET_SECURE_PLT && flag_pic == 2)
11609 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11610 else
11611 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11612 }
11613 else
11614 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11615 }
11616 "&& TARGET_TLS_MARKERS"
11617 [(set (match_dup 0)
11618 (unspec:TLSmode [(match_dup 1)]
11619 UNSPEC_TLSLD))
11620 (parallel [(set (match_dup 0)
11621 (call (mem:TLSmode (match_dup 2))
11622 (match_dup 3)))
11623 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11624 (clobber (reg:SI LR_REGNO))])]
11625 ""
11626 [(set_attr "length" "8")])
11628 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
11629 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11630 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11631 UNSPEC_TLSLD))]
11632 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11633 "addi %0,%1,%&@got@tlsld"
11634 "&& TARGET_CMODEL != CMODEL_SMALL"
11635 [(set (match_dup 2)
11636 (plus:TLSmode (match_dup 1)
11637 (high:TLSmode
11638 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD))))
11639 (set (match_dup 0)
11640 (lo_sum:TLSmode (match_dup 2)
11641 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11642 "
11643 {
11644 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11645 }"
11646 [(set (attr "length")
11647 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11648 (const_int 8)
11649 (const_int 4)))])
11651 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
11652 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11653 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11654 (high:TLSmode
11655 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD))))]
11656 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11657 "addis %0,%1,%&@got@tlsld@ha"
11658 [(set_attr "length" "4")])
11660 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
11661 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11662 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11663 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11664 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11665 "addi %0,%1,%&@got@tlsld@l"
11666 [(set_attr "length" "4")])
11668 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11669 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11670 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11671 (match_operand 2 "" "g")))
11672 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11673 (clobber (reg:SI LR_REGNO))]
11674 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11675 "bl %z1(%&@tlsld)\;%."
11676 [(set_attr "type" "branch")
11677 (set_attr "length" "8")])
11679 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11680 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11681 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11682 (match_operand 2 "" "g")))
11683 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11684 (clobber (reg:SI LR_REGNO))]
11685 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11686 {
11687 if (flag_pic)
11688 {
11689 if (TARGET_SECURE_PLT && flag_pic == 2)
11690 return "bl %z1+32768(%&@tlsld)@plt";
11691 return "bl %z1(%&@tlsld)@plt";
11692 }
11693 return "bl %z1(%&@tlsld)";
11694 }
11695 [(set_attr "type" "branch")
11696 (set_attr "length" "4")])
11698 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11699 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11700 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11701 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11702 UNSPEC_TLSDTPREL))]
11703 "HAVE_AS_TLS"
11704 "addi %0,%1,%2@dtprel")
11706 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11707 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11708 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11709 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11710 UNSPEC_TLSDTPRELHA))]
11711 "HAVE_AS_TLS"
11712 "addis %0,%1,%2@dtprel@ha")
11714 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11715 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11716 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11717 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11718 UNSPEC_TLSDTPRELLO))]
11719 "HAVE_AS_TLS"
11720 "addi %0,%1,%2@dtprel@l")
11722 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11723 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11724 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11725 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11726 UNSPEC_TLSGOTDTPREL))]
11727 "HAVE_AS_TLS"
11728 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
11729 "&& TARGET_CMODEL != CMODEL_SMALL"
11730 [(set (match_dup 3)
11731 (plus:TLSmode (match_dup 1)
11732 (high:TLSmode
11733 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL))))
11734 (set (match_dup 0)
11735 (lo_sum:TLSmode (match_dup 3)
11736 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
11737 "
11738 {
11739 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11740 }"
11741 [(set (attr "length")
11742 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11743 (const_int 8)
11744 (const_int 4)))])
11746 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
11747 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11748 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11749 (high:TLSmode
11750 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11751 UNSPEC_TLSGOTDTPREL))))]
11752 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11753 "addis %0,%1,%2@got@dtprel@ha"
11754 [(set_attr "length" "4")])
11756 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
11757 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11758 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11759 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11760 UNSPEC_TLSGOTDTPREL)))]
11761 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11762 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
11763 [(set_attr "length" "4")])
11765 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11766 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11767 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11768 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11769 UNSPEC_TLSTPREL))]
11770 "HAVE_AS_TLS"
11771 "addi %0,%1,%2@tprel")
11773 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11774 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11775 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11776 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11777 UNSPEC_TLSTPRELHA))]
11778 "HAVE_AS_TLS"
11779 "addis %0,%1,%2@tprel@ha")
11781 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11782 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11783 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11784 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11785 UNSPEC_TLSTPRELLO))]
11786 "HAVE_AS_TLS"
11787 "addi %0,%1,%2@tprel@l")
11789 ;; "b" output constraint here and on tls_tls input to support linker tls
11790 ;; optimization. The linker may edit the instructions emitted by a
11791 ;; tls_got_tprel/tls_tls pair to addis,addi.
11792 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11793 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11794 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11795 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11796 UNSPEC_TLSGOTTPREL))]
11797 "HAVE_AS_TLS"
11798 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
11799 "&& TARGET_CMODEL != CMODEL_SMALL"
11800 [(set (match_dup 3)
11801 (plus:TLSmode (match_dup 1)
11802 (high:TLSmode
11803 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL))))
11804 (set (match_dup 0)
11805 (lo_sum:TLSmode (match_dup 3)
11806 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
11807 "
11808 {
11809 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11810 }"
11811 [(set (attr "length")
11812 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11813 (const_int 8)
11814 (const_int 4)))])
11816 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
11817 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11818 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11819 (high:TLSmode
11820 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11821 UNSPEC_TLSGOTTPREL))))]
11822 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11823 "addis %0,%1,%2@got@tprel@ha"
11824 [(set_attr "length" "4")])
11826 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
11827 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11828 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11829 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11830 UNSPEC_TLSGOTTPREL)))]
11831 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11832 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
11833 [(set_attr "length" "4")])
11835 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11836 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11837 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11838 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11839 UNSPEC_TLSTLS))]
11840 "HAVE_AS_TLS"
11841 "add %0,%1,%2@tls")
11842 \f
11843 ;; Next come insns related to the calling sequence.
11844 ;;
11845 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11846 ;; We move the back-chain and decrement the stack pointer.
11848 (define_expand "allocate_stack"
11849 [(set (match_operand 0 "gpc_reg_operand" "")
11850 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11851 (set (reg 1)
11852 (minus (reg 1) (match_dup 1)))]
11853 ""
11854 "
11855 { rtx chain = gen_reg_rtx (Pmode);
11856 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11857 rtx neg_op0;
11858 rtx insn, par, set, mem;
11860 emit_move_insn (chain, stack_bot);
11862 /* Check stack bounds if necessary. */
11863 if (crtl->limit_stack)
11864 {
11865 rtx available;
11866 available = expand_binop (Pmode, sub_optab,
11867 stack_pointer_rtx, stack_limit_rtx,
11868 NULL_RTX, 1, OPTAB_WIDEN);
11869 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11870 }
11872 if (GET_CODE (operands[1]) != CONST_INT
11873 || INTVAL (operands[1]) < -32767
11874 || INTVAL (operands[1]) > 32768)
11875 {
11876 neg_op0 = gen_reg_rtx (Pmode);
11877 if (TARGET_32BIT)
11878 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11879 else
11880 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11881 }
11882 else
11883 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11885 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11886 : gen_movdi_di_update_stack))
11887 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11888 chain));
11889 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11890 it now and set the alias set/attributes. The above gen_*_update
11891 calls will generate a PARALLEL with the MEM set being the first
11892 operation. */
11893 par = PATTERN (insn);
11894 gcc_assert (GET_CODE (par) == PARALLEL);
11895 set = XVECEXP (par, 0, 0);
11896 gcc_assert (GET_CODE (set) == SET);
11897 mem = SET_DEST (set);
11898 gcc_assert (MEM_P (mem));
11899 MEM_NOTRAP_P (mem) = 1;
11900 set_mem_alias_set (mem, get_frame_alias_set ());
11902 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11903 DONE;
11904 }")
11906 ;; These patterns say how to save and restore the stack pointer. We need not
11907 ;; save the stack pointer at function level since we are careful to
11908 ;; preserve the backchain. At block level, we have to restore the backchain
11909 ;; when we restore the stack pointer.
11910 ;;
11911 ;; For nonlocal gotos, we must save both the stack pointer and its
11912 ;; backchain and restore both. Note that in the nonlocal case, the
11913 ;; save area is a memory location.
11915 (define_expand "save_stack_function"
11916 [(match_operand 0 "any_operand" "")
11917 (match_operand 1 "any_operand" "")]
11918 ""
11919 "DONE;")
11921 (define_expand "restore_stack_function"
11922 [(match_operand 0 "any_operand" "")
11923 (match_operand 1 "any_operand" "")]
11924 ""
11925 "DONE;")
11927 ;; Adjust stack pointer (op0) to a new value (op1).
11928 ;; First copy old stack backchain to new location, and ensure that the
11929 ;; scheduler won't reorder the sp assignment before the backchain write.
11930 (define_expand "restore_stack_block"
11931 [(set (match_dup 2) (match_dup 3))
11932 (set (match_dup 4) (match_dup 2))
11933 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
11934 (set (match_operand 0 "register_operand" "")
11935 (match_operand 1 "register_operand" ""))]
11936 ""
11937 "
11938 {
11939 operands[1] = force_reg (Pmode, operands[1]);
11940 operands[2] = gen_reg_rtx (Pmode);
11941 operands[3] = gen_frame_mem (Pmode, operands[0]);
11942 operands[4] = gen_frame_mem (Pmode, operands[1]);
11943 operands[5] = gen_frame_mem (BLKmode, operands[0]);
11944 }")
11946 (define_expand "save_stack_nonlocal"
11947 [(set (match_dup 3) (match_dup 4))
11948 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11949 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11950 ""
11951 "
11952 {
11953 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11955 /* Copy the backchain to the first word, sp to the second. */
11956 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11957 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11958 operands[3] = gen_reg_rtx (Pmode);
11959 operands[4] = gen_frame_mem (Pmode, operands[1]);
11960 }")
11962 (define_expand "restore_stack_nonlocal"
11963 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11964 (set (match_dup 3) (match_dup 4))
11965 (set (match_dup 5) (match_dup 2))
11966 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
11967 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11968 ""
11969 "
11970 {
11971 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11973 /* Restore the backchain from the first word, sp from the second. */
11974 operands[2] = gen_reg_rtx (Pmode);
11975 operands[3] = gen_reg_rtx (Pmode);
11976 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11977 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11978 operands[5] = gen_frame_mem (Pmode, operands[3]);
11979 operands[6] = gen_frame_mem (BLKmode, operands[0]);
11980 }")
11981 \f
11982 ;; TOC register handling.
11984 ;; Code to initialize the TOC register...
11986 (define_insn "load_toc_aix_si"
11987 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11988 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11989 (use (reg:SI 2))])]
11990 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11991 "*
11992 {
11993 char buf[30];
11994 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11995 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11996 operands[2] = gen_rtx_REG (Pmode, 2);
11997 return \"{l|lwz} %0,%1(%2)\";
11998 }"
11999 [(set_attr "type" "load")])
12001 (define_insn "load_toc_aix_di"
12002 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12003 (unspec:DI [(const_int 0)] UNSPEC_TOC))
12004 (use (reg:DI 2))])]
12005 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
12006 "*
12007 {
12008 char buf[30];
12009 #ifdef TARGET_RELOCATABLE
12010 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
12011 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
12012 #else
12013 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
12014 #endif
12015 if (TARGET_ELF)
12016 strcat (buf, \"@toc\");
12017 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12018 operands[2] = gen_rtx_REG (Pmode, 2);
12019 return \"ld %0,%1(%2)\";
12020 }"
12021 [(set_attr "type" "load")])
12023 (define_insn "load_toc_v4_pic_si"
12024 [(set (reg:SI LR_REGNO)
12025 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
12026 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
12027 "bl _GLOBAL_OFFSET_TABLE_@local-4"
12028 [(set_attr "type" "branch")
12029 (set_attr "length" "4")])
12031 (define_insn "load_toc_v4_PIC_1"
12032 [(set (reg:SI LR_REGNO)
12033 (match_operand:SI 0 "immediate_operand" "s"))
12034 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
12035 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
12036 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
12037 "bcl 20,31,%0\\n%0:"
12038 [(set_attr "type" "branch")
12039 (set_attr "length" "4")])
12041 (define_insn "load_toc_v4_PIC_1b"
12042 [(set (reg:SI LR_REGNO)
12043 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
12044 (label_ref (match_operand 1 "" ""))]
12045 UNSPEC_TOCPTR))
12046 (match_dup 1)]
12047 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12048 "bcl 20,31,$+8\;.long %0-$"
12049 [(set_attr "type" "branch")
12050 (set_attr "length" "8")])
12052 (define_insn "load_toc_v4_PIC_2"
12053 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12054 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12055 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
12056 (match_operand:SI 3 "immediate_operand" "s")))))]
12057 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12058 "{l|lwz} %0,%2-%3(%1)"
12059 [(set_attr "type" "load")])
12061 (define_insn "load_toc_v4_PIC_3b"
12062 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12063 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12064 (high:SI
12065 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
12066 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
12067 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
12068 "{cau|addis} %0,%1,%2-%3@ha")
12070 (define_insn "load_toc_v4_PIC_3c"
12071 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12072 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12073 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
12074 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
12075 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
12076 "{cal %0,%2-%3@l(%1)|addi %0,%1,%2-%3@l}")
12078 ;; If the TOC is shared over a translation unit, as happens with all
12079 ;; the kinds of PIC that we support, we need to restore the TOC
12080 ;; pointer only when jumping over units of translation.
12081 ;; On Darwin, we need to reload the picbase.
12083 (define_expand "builtin_setjmp_receiver"
12084 [(use (label_ref (match_operand 0 "" "")))]
12085 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12086 || (TARGET_TOC && TARGET_MINIMAL_TOC)
12087 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
12088 "
12089 {
12090 #if TARGET_MACHO
12091 if (DEFAULT_ABI == ABI_DARWIN)
12092 {
12093 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
12094 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
12095 rtx tmplabrtx;
12096 char tmplab[20];
12098 crtl->uses_pic_offset_table = 1;
12099 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
12100 CODE_LABEL_NUMBER (operands[0]));
12101 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
12103 emit_insn (gen_load_macho_picbase (tmplabrtx));
12104 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
12105 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
12106 }
12107 else
12108 #endif
12109 rs6000_emit_load_toc_table (FALSE);
12110 DONE;
12111 }")
12113 ;; Elf specific ways of loading addresses for non-PIC code.
12114 ;; The output of this could be r0, but we make a very strong
12115 ;; preference for a base register because it will usually
12116 ;; be needed there.
12117 (define_insn "elf_high"
12118 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
12119 (high:SI (match_operand 1 "" "")))]
12120 "TARGET_ELF && ! TARGET_64BIT"
12121 "{liu|lis} %0,%1@ha")
12123 (define_insn "elf_low"
12124 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12125 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
12126 (match_operand 2 "" "")))]
12127 "TARGET_ELF && ! TARGET_64BIT"
12128 "@
12129 {cal|la} %0,%2@l(%1)
12130 {ai|addic} %0,%1,%K2")
12132 ;; Largetoc support
12133 (define_insn "largetoc_high"
12134 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
12135 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
12136 (high:DI (match_operand:DI 2 "" ""))))]
12137 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12138 "{cau|addis} %0,%1,%2@ha")
12140 (define_insn "largetoc_low"
12141 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12142 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
12143 (match_operand:DI 2 "" "")))]
12144 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12145 "{cal %0,%2@l(%1)|addi %0,%1,%2@l}")
12146 \f
12147 ;; A function pointer under AIX is a pointer to a data area whose first word
12148 ;; contains the actual address of the function, whose second word contains a
12149 ;; pointer to its TOC, and whose third word contains a value to place in the
12150 ;; static chain register (r11). Note that if we load the static chain, our
12151 ;; "trampoline" need not have any executable code.
12153 (define_expand "call_indirect_aix32"
12154 [(set (match_dup 2)
12155 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
12156 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
12157 (reg:SI 2))
12158 (set (reg:SI 11)
12159 (mem:SI (plus:SI (match_dup 0)
12160 (const_int 8))))
12161 (parallel [(call (mem:SI (match_dup 2))
12162 (match_operand 1 "" ""))
12163 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
12164 (use (reg:SI 11))
12165 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12166 (clobber (reg:SI LR_REGNO))])]
12167 "TARGET_32BIT"
12168 "
12169 { operands[2] = gen_reg_rtx (SImode); }")
12171 (define_expand "call_indirect_aix64"
12172 [(set (match_dup 2)
12173 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
12174 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
12175 (reg:DI 2))
12176 (set (reg:DI 11)
12177 (mem:DI (plus:DI (match_dup 0)
12178 (const_int 16))))
12179 (parallel [(call (mem:SI (match_dup 2))
12180 (match_operand 1 "" ""))
12181 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
12182 (use (reg:DI 11))
12183 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12184 (clobber (reg:SI LR_REGNO))])]
12185 "TARGET_64BIT"
12186 "
12187 { operands[2] = gen_reg_rtx (DImode); }")
12189 (define_expand "call_value_indirect_aix32"
12190 [(set (match_dup 3)
12191 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12192 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
12193 (reg:SI 2))
12194 (set (reg:SI 11)
12195 (mem:SI (plus:SI (match_dup 1)
12196 (const_int 8))))
12197 (parallel [(set (match_operand 0 "" "")
12198 (call (mem:SI (match_dup 3))
12199 (match_operand 2 "" "")))
12200 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
12201 (use (reg:SI 11))
12202 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12203 (clobber (reg:SI LR_REGNO))])]
12204 "TARGET_32BIT"
12205 "
12206 { operands[3] = gen_reg_rtx (SImode); }")
12208 (define_expand "call_value_indirect_aix64"
12209 [(set (match_dup 3)
12210 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12211 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
12212 (reg:DI 2))
12213 (set (reg:DI 11)
12214 (mem:DI (plus:DI (match_dup 1)
12215 (const_int 16))))
12216 (parallel [(set (match_operand 0 "" "")
12217 (call (mem:SI (match_dup 3))
12218 (match_operand 2 "" "")))
12219 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
12220 (use (reg:DI 11))
12221 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12222 (clobber (reg:SI LR_REGNO))])]
12223 "TARGET_64BIT"
12224 "
12225 { operands[3] = gen_reg_rtx (DImode); }")
12227 ;; Now the definitions for the call and call_value insns
12228 (define_expand "call"
12229 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12230 (match_operand 1 "" ""))
12231 (use (match_operand 2 "" ""))
12232 (clobber (reg:SI LR_REGNO))])]
12233 ""
12234 "
12235 {
12236 #if TARGET_MACHO
12237 if (MACHOPIC_INDIRECT)
12238 operands[0] = machopic_indirect_call_target (operands[0]);
12239 #endif
12241 gcc_assert (GET_CODE (operands[0]) == MEM);
12242 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12244 operands[0] = XEXP (operands[0], 0);
12246 if (GET_CODE (operands[0]) != SYMBOL_REF
12247 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
12248 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
12249 {
12250 if (INTVAL (operands[2]) & CALL_LONG)
12251 operands[0] = rs6000_longcall_ref (operands[0]);
12253 switch (DEFAULT_ABI)
12254 {
12255 case ABI_V4:
12256 case ABI_DARWIN:
12257 operands[0] = force_reg (Pmode, operands[0]);
12258 break;
12260 case ABI_AIX:
12261 /* AIX function pointers are really pointers to a three word
12262 area. */
12263 emit_call_insn (TARGET_32BIT
12264 ? gen_call_indirect_aix32 (force_reg (SImode,
12265 operands[0]),
12266 operands[1])
12267 : gen_call_indirect_aix64 (force_reg (DImode,
12268 operands[0]),
12269 operands[1]));
12270 DONE;
12272 default:
12273 gcc_unreachable ();
12274 }
12275 }
12276 }")
12278 (define_expand "call_value"
12279 [(parallel [(set (match_operand 0 "" "")
12280 (call (mem:SI (match_operand 1 "address_operand" ""))
12281 (match_operand 2 "" "")))
12282 (use (match_operand 3 "" ""))
12283 (clobber (reg:SI LR_REGNO))])]
12284 ""
12285 "
12286 {
12287 #if TARGET_MACHO
12288 if (MACHOPIC_INDIRECT)
12289 operands[1] = machopic_indirect_call_target (operands[1]);
12290 #endif
12292 gcc_assert (GET_CODE (operands[1]) == MEM);
12293 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12295 operands[1] = XEXP (operands[1], 0);
12297 if (GET_CODE (operands[1]) != SYMBOL_REF
12298 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
12299 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
12300 {
12301 if (INTVAL (operands[3]) & CALL_LONG)
12302 operands[1] = rs6000_longcall_ref (operands[1]);
12304 switch (DEFAULT_ABI)
12305 {
12306 case ABI_V4:
12307 case ABI_DARWIN:
12308 operands[1] = force_reg (Pmode, operands[1]);
12309 break;
12311 case ABI_AIX:
12312 /* AIX function pointers are really pointers to a three word
12313 area. */
12314 emit_call_insn (TARGET_32BIT
12315 ? gen_call_value_indirect_aix32 (operands[0],
12316 force_reg (SImode,
12317 operands[1]),
12318 operands[2])
12319 : gen_call_value_indirect_aix64 (operands[0],
12320 force_reg (DImode,
12321 operands[1]),
12322 operands[2]));
12323 DONE;
12325 default:
12326 gcc_unreachable ();
12327 }
12328 }
12329 }")
12331 ;; Call to function in current module. No TOC pointer reload needed.
12332 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12333 ;; either the function was not prototyped, or it was prototyped as a
12334 ;; variable argument function. It is > 0 if FP registers were passed
12335 ;; and < 0 if they were not.
12337 (define_insn "*call_local32"
12338 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12339 (match_operand 1 "" "g,g"))
12340 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12341 (clobber (reg:SI LR_REGNO))]
12342 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12343 "*
12344 {
12345 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12346 output_asm_insn (\"crxor 6,6,6\", operands);
12348 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12349 output_asm_insn (\"creqv 6,6,6\", operands);
12351 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12352 }"
12353 [(set_attr "type" "branch")
12354 (set_attr "length" "4,8")])
12356 (define_insn "*call_local64"
12357 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12358 (match_operand 1 "" "g,g"))
12359 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12360 (clobber (reg:SI LR_REGNO))]
12361 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12362 "*
12363 {
12364 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12365 output_asm_insn (\"crxor 6,6,6\", operands);
12367 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12368 output_asm_insn (\"creqv 6,6,6\", operands);
12370 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12371 }"
12372 [(set_attr "type" "branch")
12373 (set_attr "length" "4,8")])
12375 (define_insn "*call_value_local32"
12376 [(set (match_operand 0 "" "")
12377 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12378 (match_operand 2 "" "g,g")))
12379 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12380 (clobber (reg:SI LR_REGNO))]
12381 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12382 "*
12383 {
12384 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12385 output_asm_insn (\"crxor 6,6,6\", operands);
12387 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12388 output_asm_insn (\"creqv 6,6,6\", operands);
12390 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12391 }"
12392 [(set_attr "type" "branch")
12393 (set_attr "length" "4,8")])
12396 (define_insn "*call_value_local64"
12397 [(set (match_operand 0 "" "")
12398 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12399 (match_operand 2 "" "g,g")))
12400 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12401 (clobber (reg:SI LR_REGNO))]
12402 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12403 "*
12404 {
12405 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12406 output_asm_insn (\"crxor 6,6,6\", operands);
12408 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12409 output_asm_insn (\"creqv 6,6,6\", operands);
12411 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12412 }"
12413 [(set_attr "type" "branch")
12414 (set_attr "length" "4,8")])
12416 ;; Call to function which may be in another module. Restore the TOC
12417 ;; pointer (r2) after the call unless this is System V.
12418 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12419 ;; either the function was not prototyped, or it was prototyped as a
12420 ;; variable argument function. It is > 0 if FP registers were passed
12421 ;; and < 0 if they were not.
12423 (define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
12424 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
12425 (match_operand 1 "" "g,g"))
12426 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
12427 (use (reg:SI 11))
12428 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12429 (clobber (reg:SI LR_REGNO))]
12430 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
12431 "#"
12432 "&& reload_completed"
12433 [(set (reg:SI 2)
12434 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
12435 (parallel [(call (mem:SI (match_dup 0))
12436 (match_dup 1))
12437 (use (reg:SI 2))
12438 (use (reg:SI 11))
12439 (set (reg:SI 2)
12440 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12441 (clobber (reg:SI LR_REGNO))])]
12442 ""
12443 [(set_attr "type" "jmpreg")
12444 (set_attr "length" "12")])
12446 (define_insn "*call_indirect_nonlocal_aix32"
12447 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
12448 (match_operand 1 "" "g,g"))
12449 (use (reg:SI 2))
12450 (use (reg:SI 11))
12451 (set (reg:SI 2)
12452 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12453 (clobber (reg:SI LR_REGNO))]
12454 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12455 "b%T0l\;{l|lwz} 2,20(1)"
12456 [(set_attr "type" "jmpreg")
12457 (set_attr "length" "8")])
12459 (define_insn "*call_nonlocal_aix32"
12460 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12461 (match_operand 1 "" "g"))
12462 (use (match_operand:SI 2 "immediate_operand" "O"))
12463 (clobber (reg:SI LR_REGNO))]
12464 "TARGET_32BIT
12465 && DEFAULT_ABI == ABI_AIX
12466 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12467 "bl %z0\;%."
12468 [(set_attr "type" "branch")
12469 (set_attr "length" "8")])
12471 (define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
12472 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
12473 (match_operand 1 "" "g,g"))
12474 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
12475 (const_int 8))))
12476 (use (reg:DI 11))
12477 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12478 (clobber (reg:SI LR_REGNO))]
12479 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
12480 "#"
12481 "&& reload_completed"
12482 [(set (reg:DI 2)
12483 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
12484 (parallel [(call (mem:SI (match_dup 0))
12485 (match_dup 1))
12486 (use (reg:DI 2))
12487 (use (reg:DI 11))
12488 (set (reg:DI 2)
12489 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12490 (clobber (reg:SI LR_REGNO))])]
12491 ""
12492 [(set_attr "type" "jmpreg")
12493 (set_attr "length" "12")])
12495 (define_insn "*call_indirect_nonlocal_aix64"
12496 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
12497 (match_operand 1 "" "g,g"))
12498 (use (reg:DI 2))
12499 (use (reg:DI 11))
12500 (set (reg:DI 2)
12501 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12502 (clobber (reg:SI LR_REGNO))]
12503 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12504 "b%T0l\;ld 2,40(1)"
12505 [(set_attr "type" "jmpreg")
12506 (set_attr "length" "8")])
12508 (define_insn "*call_nonlocal_aix64"
12509 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12510 (match_operand 1 "" "g"))
12511 (use (match_operand:SI 2 "immediate_operand" "O"))
12512 (clobber (reg:SI LR_REGNO))]
12513 "TARGET_64BIT
12514 && DEFAULT_ABI == ABI_AIX
12515 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12516 "bl %z0\;%."
12517 [(set_attr "type" "branch")
12518 (set_attr "length" "8")])
12520 (define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
12521 [(set (match_operand 0 "" "")
12522 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
12523 (match_operand 2 "" "g,g")))
12524 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
12525 (const_int 4))))
12526 (use (reg:SI 11))
12527 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12528 (clobber (reg:SI LR_REGNO))]
12529 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
12530 "#"
12531 "&& reload_completed"
12532 [(set (reg:SI 2)
12533 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
12534 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
12535 (match_dup 2)))
12536 (use (reg:SI 2))
12537 (use (reg:SI 11))
12538 (set (reg:SI 2)
12539 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12540 (clobber (reg:SI LR_REGNO))])]
12541 ""
12542 [(set_attr "type" "jmpreg")
12543 (set_attr "length" "12")])
12545 (define_insn "*call_value_indirect_nonlocal_aix32"
12546 [(set (match_operand 0 "" "")
12547 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
12548 (match_operand 2 "" "g,g")))
12549 (use (reg:SI 2))
12550 (use (reg:SI 11))
12551 (set (reg:SI 2)
12552 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12553 (clobber (reg:SI LR_REGNO))]
12554 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12555 "b%T1l\;{l|lwz} 2,20(1)"
12556 [(set_attr "type" "jmpreg")
12557 (set_attr "length" "8")])
12559 (define_insn "*call_value_nonlocal_aix32"
12560 [(set (match_operand 0 "" "")
12561 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12562 (match_operand 2 "" "g")))
12563 (use (match_operand:SI 3 "immediate_operand" "O"))
12564 (clobber (reg:SI LR_REGNO))]
12565 "TARGET_32BIT
12566 && DEFAULT_ABI == ABI_AIX
12567 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12568 "bl %z1\;%."
12569 [(set_attr "type" "branch")
12570 (set_attr "length" "8")])
12572 (define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
12573 [(set (match_operand 0 "" "")
12574 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
12575 (match_operand 2 "" "g,g")))
12576 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
12577 (const_int 8))))
12578 (use (reg:DI 11))
12579 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12580 (clobber (reg:SI LR_REGNO))]
12581 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
12582 "#"
12583 "&& reload_completed"
12584 [(set (reg:DI 2)
12585 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
12586 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
12587 (match_dup 2)))
12588 (use (reg:DI 2))
12589 (use (reg:DI 11))
12590 (set (reg:DI 2)
12591 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12592 (clobber (reg:SI LR_REGNO))])]
12593 ""
12594 [(set_attr "type" "jmpreg")
12595 (set_attr "length" "12")])
12597 (define_insn "*call_value_indirect_nonlocal_aix64"
12598 [(set (match_operand 0 "" "")
12599 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
12600 (match_operand 2 "" "g,g")))
12601 (use (reg:DI 2))
12602 (use (reg:DI 11))
12603 (set (reg:DI 2)
12604 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12605 (clobber (reg:SI LR_REGNO))]
12606 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12607 "b%T1l\;ld 2,40(1)"
12608 [(set_attr "type" "jmpreg")
12609 (set_attr "length" "8")])
12611 (define_insn "*call_value_nonlocal_aix64"
12612 [(set (match_operand 0 "" "")
12613 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12614 (match_operand 2 "" "g")))
12615 (use (match_operand:SI 3 "immediate_operand" "O"))
12616 (clobber (reg:SI LR_REGNO))]
12617 "TARGET_64BIT
12618 && DEFAULT_ABI == ABI_AIX
12619 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12620 "bl %z1\;%."
12621 [(set_attr "type" "branch")
12622 (set_attr "length" "8")])
12624 ;; A function pointer under System V is just a normal pointer
12625 ;; operands[0] is the function pointer
12626 ;; operands[1] is the stack size to clean up
12627 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12628 ;; which indicates how to set cr1
12630 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12631 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12632 (match_operand 1 "" "g,g,g,g"))
12633 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12634 (clobber (reg:SI LR_REGNO))]
12635 "DEFAULT_ABI == ABI_V4
12636 || DEFAULT_ABI == ABI_DARWIN"
12637 {
12638 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12639 output_asm_insn ("crxor 6,6,6", operands);
12641 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12642 output_asm_insn ("creqv 6,6,6", operands);
12644 return "b%T0l";
12645 }
12646 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12647 (set_attr "length" "4,4,8,8")])
12649 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12650 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12651 (match_operand 1 "" "g,g"))
12652 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12653 (clobber (reg:SI LR_REGNO))]
12654 "(DEFAULT_ABI == ABI_DARWIN
12655 || (DEFAULT_ABI == ABI_V4
12656 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12657 {
12658 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12659 output_asm_insn ("crxor 6,6,6", operands);
12661 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12662 output_asm_insn ("creqv 6,6,6", operands);
12664 #if TARGET_MACHO
12665 return output_call(insn, operands, 0, 2);
12666 #else
12667 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12668 {
12669 gcc_assert (!TARGET_SECURE_PLT);
12670 return "bl %z0@plt";
12671 }
12672 else
12673 return "bl %z0";
12674 #endif
12675 }
12676 "DEFAULT_ABI == ABI_V4
12677 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12678 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12679 [(parallel [(call (mem:SI (match_dup 0))
12680 (match_dup 1))
12681 (use (match_dup 2))
12682 (use (match_dup 3))
12683 (clobber (reg:SI LR_REGNO))])]
12684 {
12685 operands[3] = pic_offset_table_rtx;
12686 }
12687 [(set_attr "type" "branch,branch")
12688 (set_attr "length" "4,8")])
12690 (define_insn "*call_nonlocal_sysv_secure<mode>"
12691 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12692 (match_operand 1 "" "g,g"))
12693 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12694 (use (match_operand:SI 3 "register_operand" "r,r"))
12695 (clobber (reg:SI LR_REGNO))]
12696 "(DEFAULT_ABI == ABI_V4
12697 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12698 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12699 {
12700 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12701 output_asm_insn ("crxor 6,6,6", operands);
12703 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12704 output_asm_insn ("creqv 6,6,6", operands);
12706 if (flag_pic == 2)
12707 /* The magic 32768 offset here and in the other sysv call insns
12708 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12709 See sysv4.h:toc_section. */
12710 return "bl %z0+32768@plt";
12711 else
12712 return "bl %z0@plt";
12713 }
12714 [(set_attr "type" "branch,branch")
12715 (set_attr "length" "4,8")])
12717 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12718 [(set (match_operand 0 "" "")
12719 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12720 (match_operand 2 "" "g,g,g,g")))
12721 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12722 (clobber (reg:SI LR_REGNO))]
12723 "DEFAULT_ABI == ABI_V4
12724 || DEFAULT_ABI == ABI_DARWIN"
12725 {
12726 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12727 output_asm_insn ("crxor 6,6,6", operands);
12729 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12730 output_asm_insn ("creqv 6,6,6", operands);
12732 return "b%T1l";
12733 }
12734 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12735 (set_attr "length" "4,4,8,8")])
12737 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12738 [(set (match_operand 0 "" "")
12739 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12740 (match_operand 2 "" "g,g")))
12741 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12742 (clobber (reg:SI LR_REGNO))]
12743 "(DEFAULT_ABI == ABI_DARWIN
12744 || (DEFAULT_ABI == ABI_V4
12745 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12746 {
12747 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12748 output_asm_insn ("crxor 6,6,6", operands);
12750 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12751 output_asm_insn ("creqv 6,6,6", operands);
12753 #if TARGET_MACHO
12754 return output_call(insn, operands, 1, 3);
12755 #else
12756 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12757 {
12758 gcc_assert (!TARGET_SECURE_PLT);
12759 return "bl %z1@plt";
12760 }
12761 else
12762 return "bl %z1";
12763 #endif
12764 }
12765 "DEFAULT_ABI == ABI_V4
12766 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12767 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12768 [(parallel [(set (match_dup 0)
12769 (call (mem:SI (match_dup 1))
12770 (match_dup 2)))
12771 (use (match_dup 3))
12772 (use (match_dup 4))
12773 (clobber (reg:SI LR_REGNO))])]
12774 {
12775 operands[4] = pic_offset_table_rtx;
12776 }
12777 [(set_attr "type" "branch,branch")
12778 (set_attr "length" "4,8")])
12780 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12781 [(set (match_operand 0 "" "")
12782 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12783 (match_operand 2 "" "g,g")))
12784 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12785 (use (match_operand:SI 4 "register_operand" "r,r"))
12786 (clobber (reg:SI LR_REGNO))]
12787 "(DEFAULT_ABI == ABI_V4
12788 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12789 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12790 {
12791 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12792 output_asm_insn ("crxor 6,6,6", operands);
12794 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12795 output_asm_insn ("creqv 6,6,6", operands);
12797 if (flag_pic == 2)
12798 return "bl %z1+32768@plt";
12799 else
12800 return "bl %z1@plt";
12801 }
12802 [(set_attr "type" "branch,branch")
12803 (set_attr "length" "4,8")])
12805 ;; Call subroutine returning any type.
12806 (define_expand "untyped_call"
12807 [(parallel [(call (match_operand 0 "" "")
12808 (const_int 0))
12809 (match_operand 1 "" "")
12810 (match_operand 2 "" "")])]
12811 ""
12812 "
12813 {
12814 int i;
12816 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12818 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12819 {
12820 rtx set = XVECEXP (operands[2], 0, i);
12821 emit_move_insn (SET_DEST (set), SET_SRC (set));
12822 }
12824 /* The optimizer does not know that the call sets the function value
12825 registers we stored in the result block. We avoid problems by
12826 claiming that all hard registers are used and clobbered at this
12827 point. */
12828 emit_insn (gen_blockage ());
12830 DONE;
12831 }")
12833 ;; sibling call patterns
12834 (define_expand "sibcall"
12835 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12836 (match_operand 1 "" ""))
12837 (use (match_operand 2 "" ""))
12838 (use (reg:SI LR_REGNO))
12839 (return)])]
12840 ""
12841 "
12842 {
12843 #if TARGET_MACHO
12844 if (MACHOPIC_INDIRECT)
12845 operands[0] = machopic_indirect_call_target (operands[0]);
12846 #endif
12848 gcc_assert (GET_CODE (operands[0]) == MEM);
12849 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12851 operands[0] = XEXP (operands[0], 0);
12852 }")
12854 ;; this and similar patterns must be marked as using LR, otherwise
12855 ;; dataflow will try to delete the store into it. This is true
12856 ;; even when the actual reg to jump to is in CTR, when LR was
12857 ;; saved and restored around the PIC-setting BCL.
12858 (define_insn "*sibcall_local32"
12859 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12860 (match_operand 1 "" "g,g"))
12861 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12862 (use (reg:SI LR_REGNO))
12863 (return)]
12864 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12865 "*
12866 {
12867 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12868 output_asm_insn (\"crxor 6,6,6\", operands);
12870 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12871 output_asm_insn (\"creqv 6,6,6\", operands);
12873 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12874 }"
12875 [(set_attr "type" "branch")
12876 (set_attr "length" "4,8")])
12878 (define_insn "*sibcall_local64"
12879 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12880 (match_operand 1 "" "g,g"))
12881 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12882 (use (reg:SI LR_REGNO))
12883 (return)]
12884 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12885 "*
12886 {
12887 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12888 output_asm_insn (\"crxor 6,6,6\", operands);
12890 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12891 output_asm_insn (\"creqv 6,6,6\", operands);
12893 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12894 }"
12895 [(set_attr "type" "branch")
12896 (set_attr "length" "4,8")])
12898 (define_insn "*sibcall_value_local32"
12899 [(set (match_operand 0 "" "")
12900 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12901 (match_operand 2 "" "g,g")))
12902 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12903 (use (reg:SI LR_REGNO))
12904 (return)]
12905 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12906 "*
12907 {
12908 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12909 output_asm_insn (\"crxor 6,6,6\", operands);
12911 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12912 output_asm_insn (\"creqv 6,6,6\", operands);
12914 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12915 }"
12916 [(set_attr "type" "branch")
12917 (set_attr "length" "4,8")])
12920 (define_insn "*sibcall_value_local64"
12921 [(set (match_operand 0 "" "")
12922 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12923 (match_operand 2 "" "g,g")))
12924 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12925 (use (reg:SI LR_REGNO))
12926 (return)]
12927 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12928 "*
12929 {
12930 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12931 output_asm_insn (\"crxor 6,6,6\", operands);
12933 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12934 output_asm_insn (\"creqv 6,6,6\", operands);
12936 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12937 }"
12938 [(set_attr "type" "branch")
12939 (set_attr "length" "4,8")])
12941 (define_insn "*sibcall_nonlocal_aix32"
12942 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12943 (match_operand 1 "" "g"))
12944 (use (match_operand:SI 2 "immediate_operand" "O"))
12945 (use (reg:SI LR_REGNO))
12946 (return)]
12947 "TARGET_32BIT
12948 && DEFAULT_ABI == ABI_AIX
12949 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12950 "b %z0"
12951 [(set_attr "type" "branch")
12952 (set_attr "length" "4")])
12954 (define_insn "*sibcall_nonlocal_aix64"
12955 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12956 (match_operand 1 "" "g"))
12957 (use (match_operand:SI 2 "immediate_operand" "O"))
12958 (use (reg:SI LR_REGNO))
12959 (return)]
12960 "TARGET_64BIT
12961 && DEFAULT_ABI == ABI_AIX
12962 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12963 "b %z0"
12964 [(set_attr "type" "branch")
12965 (set_attr "length" "4")])
12967 (define_insn "*sibcall_value_nonlocal_aix32"
12968 [(set (match_operand 0 "" "")
12969 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12970 (match_operand 2 "" "g")))
12971 (use (match_operand:SI 3 "immediate_operand" "O"))
12972 (use (reg:SI LR_REGNO))
12973 (return)]
12974 "TARGET_32BIT
12975 && DEFAULT_ABI == ABI_AIX
12976 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12977 "b %z1"
12978 [(set_attr "type" "branch")
12979 (set_attr "length" "4")])
12981 (define_insn "*sibcall_value_nonlocal_aix64"
12982 [(set (match_operand 0 "" "")
12983 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12984 (match_operand 2 "" "g")))
12985 (use (match_operand:SI 3 "immediate_operand" "O"))
12986 (use (reg:SI LR_REGNO))
12987 (return)]
12988 "TARGET_64BIT
12989 && DEFAULT_ABI == ABI_AIX
12990 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12991 "b %z1"
12992 [(set_attr "type" "branch")
12993 (set_attr "length" "4")])
12995 (define_insn "*sibcall_nonlocal_sysv<mode>"
12996 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12997 (match_operand 1 "" ""))
12998 (use (match_operand 2 "immediate_operand" "O,n"))
12999 (use (reg:SI LR_REGNO))
13000 (return)]
13001 "(DEFAULT_ABI == ABI_DARWIN
13002 || DEFAULT_ABI == ABI_V4)
13003 && (INTVAL (operands[2]) & CALL_LONG) == 0"
13004 "*
13005 {
13006 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
13007 output_asm_insn (\"crxor 6,6,6\", operands);
13009 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
13010 output_asm_insn (\"creqv 6,6,6\", operands);
13012 if (DEFAULT_ABI == ABI_V4 && flag_pic)
13013 {
13014 gcc_assert (!TARGET_SECURE_PLT);
13015 return \"b %z0@plt\";
13016 }
13017 else
13018 return \"b %z0\";
13019 }"
13020 [(set_attr "type" "branch,branch")
13021 (set_attr "length" "4,8")])
13023 (define_expand "sibcall_value"
13024 [(parallel [(set (match_operand 0 "register_operand" "")
13025 (call (mem:SI (match_operand 1 "address_operand" ""))
13026 (match_operand 2 "" "")))
13027 (use (match_operand 3 "" ""))
13028 (use (reg:SI LR_REGNO))
13029 (return)])]
13030 ""
13031 "
13032 {
13033 #if TARGET_MACHO
13034 if (MACHOPIC_INDIRECT)
13035 operands[1] = machopic_indirect_call_target (operands[1]);
13036 #endif
13038 gcc_assert (GET_CODE (operands[1]) == MEM);
13039 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
13041 operands[1] = XEXP (operands[1], 0);
13042 }")
13044 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
13045 [(set (match_operand 0 "" "")
13046 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
13047 (match_operand 2 "" "")))
13048 (use (match_operand:SI 3 "immediate_operand" "O,n"))
13049 (use (reg:SI LR_REGNO))
13050 (return)]
13051 "(DEFAULT_ABI == ABI_DARWIN
13052 || DEFAULT_ABI == ABI_V4)
13053 && (INTVAL (operands[3]) & CALL_LONG) == 0"
13054 "*
13055 {
13056 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
13057 output_asm_insn (\"crxor 6,6,6\", operands);
13059 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
13060 output_asm_insn (\"creqv 6,6,6\", operands);
13062 if (DEFAULT_ABI == ABI_V4 && flag_pic)
13063 {
13064 gcc_assert (!TARGET_SECURE_PLT);
13065 return \"b %z1@plt\";
13066 }
13067 else
13068 return \"b %z1\";
13069 }"
13070 [(set_attr "type" "branch,branch")
13071 (set_attr "length" "4,8")])
13073 (define_expand "sibcall_epilogue"
13074 [(use (const_int 0))]
13075 "TARGET_SCHED_PROLOG"
13076 "
13077 {
13078 rs6000_emit_epilogue (TRUE);
13079 DONE;
13080 }")
13082 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13083 ;; all of memory. This blocks insns from being moved across this point.
13085 (define_insn "blockage"
13086 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
13087 ""
13088 "")
13090 (define_insn "probe_stack"
13091 [(set (match_operand 0 "memory_operand" "=m")
13092 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
13093 ""
13094 "{st%U0%X0|stw%U0%X0} 0,%0"
13095 [(set_attr "type" "store")
13096 (set_attr "length" "4")])
13098 (define_insn "probe_stack_range<P:mode>"
13099 [(set (match_operand:P 0 "register_operand" "=r")
13100 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
13101 (match_operand:P 2 "register_operand" "r")]
13102 UNSPECV_PROBE_STACK_RANGE))]
13103 ""
13104 "* return output_probe_stack_range (operands[0], operands[2]);"
13105 [(set_attr "type" "three")])
13106 \f
13107 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
13108 ;; signed & unsigned, and one type of branch.
13109 ;;
13110 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
13111 ;; insns, and branches.
13113 (define_expand "cbranch<mode>4"
13114 [(use (match_operator 0 "rs6000_cbranch_operator"
13115 [(match_operand:GPR 1 "gpc_reg_operand" "")
13116 (match_operand:GPR 2 "reg_or_short_operand" "")]))
13117 (use (match_operand 3 ""))]
13118 ""
13119 "
13120 {
13121 /* Take care of the possibility that operands[2] might be negative but
13122 this might be a logical operation. That insn doesn't exist. */
13123 if (GET_CODE (operands[2]) == CONST_INT
13124 && INTVAL (operands[2]) < 0)
13125 {
13126 operands[2] = force_reg (<MODE>mode, operands[2]);
13127 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
13128 GET_MODE (operands[0]),
13129 operands[1], operands[2]);
13130 }
13132 rs6000_emit_cbranch (<MODE>mode, operands);
13133 DONE;
13134 }")
13136 (define_expand "cbranch<mode>4"
13137 [(use (match_operator 0 "rs6000_cbranch_operator"
13138 [(match_operand:FP 1 "gpc_reg_operand" "")
13139 (match_operand:FP 2 "gpc_reg_operand" "")]))
13140 (use (match_operand 3 ""))]
13141 ""
13142 "
13143 {
13144 rs6000_emit_cbranch (<MODE>mode, operands);
13145 DONE;
13146 }")
13148 (define_expand "cstore<mode>4"
13149 [(use (match_operator 1 "rs6000_cbranch_operator"
13150 [(match_operand:GPR 2 "gpc_reg_operand" "")
13151 (match_operand:GPR 3 "reg_or_short_operand" "")]))
13152 (clobber (match_operand:SI 0 "register_operand"))]
13153 ""
13154 "
13155 {
13156 /* Take care of the possibility that operands[3] might be negative but
13157 this might be a logical operation. That insn doesn't exist. */
13158 if (GET_CODE (operands[3]) == CONST_INT
13159 && INTVAL (operands[3]) < 0)
13160 {
13161 operands[3] = force_reg (<MODE>mode, operands[3]);
13162 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
13163 GET_MODE (operands[1]),
13164 operands[2], operands[3]);
13165 }
13167 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
13168 For SEQ, likewise, except that comparisons with zero should be done
13169 with an scc insns. However, due to the order that combine see the
13170 resulting insns, we must, in fact, allow SEQ for integers. Fail in
13171 the cases we don't want to handle or are best handled by portable
13172 code. */
13173 if (GET_CODE (operands[1]) == NE)
13174 FAIL;
13175 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
13176 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
13177 && operands[3] == const0_rtx)
13178 FAIL;
13179 rs6000_emit_sCOND (<MODE>mode, operands);
13180 DONE;
13181 }")
13183 (define_expand "cstore<mode>4"
13184 [(use (match_operator 1 "rs6000_cbranch_operator"
13185 [(match_operand:FP 2 "gpc_reg_operand" "")
13186 (match_operand:FP 3 "gpc_reg_operand" "")]))
13187 (clobber (match_operand:SI 0 "register_operand"))]
13188 ""
13189 "
13190 {
13191 rs6000_emit_sCOND (<MODE>mode, operands);
13192 DONE;
13193 }")
13196 (define_expand "stack_protect_set"
13197 [(match_operand 0 "memory_operand" "")
13198 (match_operand 1 "memory_operand" "")]
13199 ""
13200 {
13201 #ifdef TARGET_THREAD_SSP_OFFSET
13202 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
13203 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
13204 operands[1] = gen_rtx_MEM (Pmode, addr);
13205 #endif
13206 if (TARGET_64BIT)
13207 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
13208 else
13209 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
13210 DONE;
13211 })
13213 (define_insn "stack_protect_setsi"
13214 [(set (match_operand:SI 0 "memory_operand" "=m")
13215 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13216 (set (match_scratch:SI 2 "=&r") (const_int 0))]
13217 "TARGET_32BIT"
13218 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
13219 [(set_attr "type" "three")
13220 (set_attr "length" "12")])
13222 (define_insn "stack_protect_setdi"
13223 [(set (match_operand:DI 0 "memory_operand" "=m")
13224 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13225 (set (match_scratch:DI 2 "=&r") (const_int 0))]
13226 "TARGET_64BIT"
13227 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
13228 [(set_attr "type" "three")
13229 (set_attr "length" "12")])
13231 (define_expand "stack_protect_test"
13232 [(match_operand 0 "memory_operand" "")
13233 (match_operand 1 "memory_operand" "")
13234 (match_operand 2 "" "")]
13235 ""
13236 {
13237 rtx test, op0, op1;
13238 #ifdef TARGET_THREAD_SSP_OFFSET
13239 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
13240 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
13241 operands[1] = gen_rtx_MEM (Pmode, addr);
13242 #endif
13243 op0 = operands[0];
13244 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
13245 test = gen_rtx_EQ (VOIDmode, op0, op1);
13246 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
13247 DONE;
13248 })
13250 (define_insn "stack_protect_testsi"
13251 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13252 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
13253 (match_operand:SI 2 "memory_operand" "m,m")]
13254 UNSPEC_SP_TEST))
13255 (set (match_scratch:SI 4 "=r,r") (const_int 0))
13256 (clobber (match_scratch:SI 3 "=&r,&r"))]
13257 "TARGET_32BIT"
13258 "@
13259 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
13260 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
13261 [(set_attr "length" "16,20")])
13263 (define_insn "stack_protect_testdi"
13264 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13265 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
13266 (match_operand:DI 2 "memory_operand" "m,m")]
13267 UNSPEC_SP_TEST))
13268 (set (match_scratch:DI 4 "=r,r") (const_int 0))
13269 (clobber (match_scratch:DI 3 "=&r,&r"))]
13270 "TARGET_64BIT"
13271 "@
13272 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
13273 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
13274 [(set_attr "length" "16,20")])
13276 \f
13277 ;; Here are the actual compare insns.
13278 (define_insn "*cmp<mode>_internal1"
13279 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13280 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
13281 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
13282 ""
13283 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
13284 [(set_attr "type" "cmp")])
13286 ;; If we are comparing a register for equality with a large constant,
13287 ;; we can do this with an XOR followed by a compare. But this is profitable
13288 ;; only if the large constant is only used for the comparison (and in this
13289 ;; case we already have a register to reuse as scratch).
13290 ;;
13291 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
13292 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
13294 (define_peephole2
13295 [(set (match_operand:SI 0 "register_operand")
13296 (match_operand:SI 1 "logical_const_operand" ""))
13297 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
13298 [(match_dup 0)
13299 (match_operand:SI 2 "logical_const_operand" "")]))
13300 (set (match_operand:CC 4 "cc_reg_operand" "")
13301 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
13302 (match_dup 0)))
13303 (set (pc)
13304 (if_then_else (match_operator 6 "equality_operator"
13305 [(match_dup 4) (const_int 0)])
13306 (match_operand 7 "" "")
13307 (match_operand 8 "" "")))]
13308 "peep2_reg_dead_p (3, operands[0])
13309 && peep2_reg_dead_p (4, operands[4])"
13310 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
13311 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
13312 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
13314 {
13315 /* Get the constant we are comparing against, and see what it looks like
13316 when sign-extended from 16 to 32 bits. Then see what constant we could
13317 XOR with SEXTC to get the sign-extended value. */
13318 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
13319 SImode,
13320 operands[1], operands[2]);
13321 HOST_WIDE_INT c = INTVAL (cnst);
13322 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
13323 HOST_WIDE_INT xorv = c ^ sextc;
13325 operands[9] = GEN_INT (xorv);
13326 operands[10] = GEN_INT (sextc);
13327 })
13329 (define_insn "*cmpsi_internal2"
13330 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13331 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13332 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
13333 ""
13334 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
13335 [(set_attr "type" "cmp")])
13337 (define_insn "*cmpdi_internal2"
13338 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13339 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
13340 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
13341 ""
13342 "cmpld%I2 %0,%1,%b2"
13343 [(set_attr "type" "cmp")])
13345 ;; The following two insns don't exist as single insns, but if we provide
13346 ;; them, we can swap an add and compare, which will enable us to overlap more
13347 ;; of the required delay between a compare and branch. We generate code for
13348 ;; them by splitting.
13350 (define_insn ""
13351 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13352 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
13353 (match_operand:SI 2 "short_cint_operand" "i")))
13354 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13355 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13356 ""
13357 "#"
13358 [(set_attr "length" "8")])
13360 (define_insn ""
13361 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
13362 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13363 (match_operand:SI 2 "u_short_cint_operand" "i")))
13364 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13365 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13366 ""
13367 "#"
13368 [(set_attr "length" "8")])
13370 (define_split
13371 [(set (match_operand:CC 3 "cc_reg_operand" "")
13372 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
13373 (match_operand:SI 2 "short_cint_operand" "")))
13374 (set (match_operand:SI 0 "gpc_reg_operand" "")
13375 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13376 ""
13377 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
13378 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13380 (define_split
13381 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
13382 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
13383 (match_operand:SI 2 "u_short_cint_operand" "")))
13384 (set (match_operand:SI 0 "gpc_reg_operand" "")
13385 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13386 ""
13387 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
13388 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13390 (define_insn "*cmpsf_internal1"
13391 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13392 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
13393 (match_operand:SF 2 "gpc_reg_operand" "f")))]
13394 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
13395 "fcmpu %0,%1,%2"
13396 [(set_attr "type" "fpcompare")])
13398 (define_insn "*cmpdf_internal1"
13399 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13400 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
13401 (match_operand:DF 2 "gpc_reg_operand" "d")))]
13402 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
13403 && !VECTOR_UNIT_VSX_P (DFmode)"
13404 "fcmpu %0,%1,%2"
13405 [(set_attr "type" "fpcompare")])
13407 ;; Only need to compare second words if first words equal
13408 (define_insn "*cmptf_internal1"
13409 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13410 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13411 (match_operand:TF 2 "gpc_reg_operand" "d")))]
13412 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
13413 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13414 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
13415 [(set_attr "type" "fpcompare")
13416 (set_attr "length" "12")])
13418 (define_insn_and_split "*cmptf_internal2"
13419 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13420 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13421 (match_operand:TF 2 "gpc_reg_operand" "d")))
13422 (clobber (match_scratch:DF 3 "=d"))
13423 (clobber (match_scratch:DF 4 "=d"))
13424 (clobber (match_scratch:DF 5 "=d"))
13425 (clobber (match_scratch:DF 6 "=d"))
13426 (clobber (match_scratch:DF 7 "=d"))
13427 (clobber (match_scratch:DF 8 "=d"))
13428 (clobber (match_scratch:DF 9 "=d"))
13429 (clobber (match_scratch:DF 10 "=d"))
13430 (clobber (match_scratch:GPR 11 "=b"))]
13431 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
13432 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13433 "#"
13434 "&& reload_completed"
13435 [(set (match_dup 3) (match_dup 14))
13436 (set (match_dup 4) (match_dup 15))
13437 (set (match_dup 9) (abs:DF (match_dup 5)))
13438 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
13439 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
13440 (label_ref (match_dup 12))
13441 (pc)))
13442 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
13443 (set (pc) (label_ref (match_dup 13)))
13444 (match_dup 12)
13445 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
13446 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
13447 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
13448 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
13449 (match_dup 13)]
13450 {
13451 REAL_VALUE_TYPE rv;
13452 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
13453 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
13455 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
13456 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
13457 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
13458 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
13459 operands[12] = gen_label_rtx ();
13460 operands[13] = gen_label_rtx ();
13461 real_inf (&rv);
13462 operands[14] = force_const_mem (DFmode,
13463 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
13464 operands[15] = force_const_mem (DFmode,
13465 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
13466 DFmode));
13467 if (TARGET_TOC)
13468 {
13469 rtx tocref;
13470 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
13471 operands[14] = gen_const_mem (DFmode, tocref);
13472 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
13473 operands[15] = gen_const_mem (DFmode, tocref);
13474 set_mem_alias_set (operands[14], get_TOC_alias_set ());
13475 set_mem_alias_set (operands[15], get_TOC_alias_set ());
13476 }
13477 })
13478 \f
13479 ;; Now we have the scc insns. We can do some combinations because of the
13480 ;; way the machine works.
13481 ;;
13482 ;; Note that this is probably faster if we can put an insn between the
13483 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
13484 ;; cases the insns below which don't use an intermediate CR field will
13485 ;; be used instead.
13486 (define_insn ""
13487 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13488 (match_operator:SI 1 "scc_comparison_operator"
13489 [(match_operand 2 "cc_reg_operand" "y")
13490 (const_int 0)]))]
13491 ""
13492 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
13493 [(set (attr "type")
13494 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13495 (const_string "mfcrf")
13496 ]
13497 (const_string "mfcr")))
13498 (set_attr "length" "8")])
13500 ;; Same as above, but get the GT bit.
13501 (define_insn "move_from_CR_gt_bit"
13502 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13503 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
13504 "TARGET_HARD_FLOAT && !TARGET_FPRS"
13505 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
13506 [(set_attr "type" "mfcr")
13507 (set_attr "length" "8")])
13509 ;; Same as above, but get the OV/ORDERED bit.
13510 (define_insn "move_from_CR_ov_bit"
13511 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13512 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
13513 "TARGET_ISEL"
13514 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
13515 [(set_attr "type" "mfcr")
13516 (set_attr "length" "8")])
13518 (define_insn ""
13519 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13520 (match_operator:DI 1 "scc_comparison_operator"
13521 [(match_operand 2 "cc_reg_operand" "y")
13522 (const_int 0)]))]
13523 "TARGET_POWERPC64"
13524 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
13525 [(set (attr "type")
13526 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13527 (const_string "mfcrf")
13528 ]
13529 (const_string "mfcr")))
13530 (set_attr "length" "8")])
13532 (define_insn ""
13533 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13534 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13535 [(match_operand 2 "cc_reg_operand" "y,y")
13536 (const_int 0)])
13537 (const_int 0)))
13538 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
13539 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13540 "TARGET_32BIT"
13541 "@
13542 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
13543 #"
13544 [(set_attr "type" "delayed_compare")
13545 (set_attr "length" "8,16")])
13547 (define_split
13548 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13549 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13550 [(match_operand 2 "cc_reg_operand" "")
13551 (const_int 0)])
13552 (const_int 0)))
13553 (set (match_operand:SI 3 "gpc_reg_operand" "")
13554 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13555 "TARGET_32BIT && reload_completed"
13556 [(set (match_dup 3)
13557 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
13558 (set (match_dup 0)
13559 (compare:CC (match_dup 3)
13560 (const_int 0)))]
13561 "")
13563 (define_insn ""
13564 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13565 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13566 [(match_operand 2 "cc_reg_operand" "y")
13567 (const_int 0)])
13568 (match_operand:SI 3 "const_int_operand" "n")))]
13569 ""
13570 "*
13571 {
13572 int is_bit = ccr_bit (operands[1], 1);
13573 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13574 int count;
13576 if (is_bit >= put_bit)
13577 count = is_bit - put_bit;
13578 else
13579 count = 32 - (put_bit - is_bit);
13581 operands[4] = GEN_INT (count);
13582 operands[5] = GEN_INT (put_bit);
13584 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
13585 }"
13586 [(set (attr "type")
13587 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13588 (const_string "mfcrf")
13589 ]
13590 (const_string "mfcr")))
13591 (set_attr "length" "8")])
13593 (define_insn ""
13594 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13595 (compare:CC
13596 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13597 [(match_operand 2 "cc_reg_operand" "y,y")
13598 (const_int 0)])
13599 (match_operand:SI 3 "const_int_operand" "n,n"))
13600 (const_int 0)))
13601 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13602 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13603 (match_dup 3)))]
13604 ""
13605 "*
13606 {
13607 int is_bit = ccr_bit (operands[1], 1);
13608 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13609 int count;
13611 /* Force split for non-cc0 compare. */
13612 if (which_alternative == 1)
13613 return \"#\";
13615 if (is_bit >= put_bit)
13616 count = is_bit - put_bit;
13617 else
13618 count = 32 - (put_bit - is_bit);
13620 operands[5] = GEN_INT (count);
13621 operands[6] = GEN_INT (put_bit);
13623 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
13624 }"
13625 [(set_attr "type" "delayed_compare")
13626 (set_attr "length" "8,16")])
13628 (define_split
13629 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13630 (compare:CC
13631 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13632 [(match_operand 2 "cc_reg_operand" "")
13633 (const_int 0)])
13634 (match_operand:SI 3 "const_int_operand" ""))
13635 (const_int 0)))
13636 (set (match_operand:SI 4 "gpc_reg_operand" "")
13637 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13638 (match_dup 3)))]
13639 "reload_completed"
13640 [(set (match_dup 4)
13641 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13642 (match_dup 3)))
13643 (set (match_dup 0)
13644 (compare:CC (match_dup 4)
13645 (const_int 0)))]
13646 "")
13648 ;; There is a 3 cycle delay between consecutive mfcr instructions
13649 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13651 (define_peephole
13652 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13653 (match_operator:SI 1 "scc_comparison_operator"
13654 [(match_operand 2 "cc_reg_operand" "y")
13655 (const_int 0)]))
13656 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13657 (match_operator:SI 4 "scc_comparison_operator"
13658 [(match_operand 5 "cc_reg_operand" "y")
13659 (const_int 0)]))]
13660 "REGNO (operands[2]) != REGNO (operands[5])"
13661 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13662 [(set_attr "type" "mfcr")
13663 (set_attr "length" "12")])
13665 (define_peephole
13666 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13667 (match_operator:DI 1 "scc_comparison_operator"
13668 [(match_operand 2 "cc_reg_operand" "y")
13669 (const_int 0)]))
13670 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13671 (match_operator:DI 4 "scc_comparison_operator"
13672 [(match_operand 5 "cc_reg_operand" "y")
13673 (const_int 0)]))]
13674 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13675 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13676 [(set_attr "type" "mfcr")
13677 (set_attr "length" "12")])
13679 ;; There are some scc insns that can be done directly, without a compare.
13680 ;; These are faster because they don't involve the communications between
13681 ;; the FXU and branch units. In fact, we will be replacing all of the
13682 ;; integer scc insns here or in the portable methods in emit_store_flag.
13683 ;;
13684 ;; Also support (neg (scc ..)) since that construct is used to replace
13685 ;; branches, (plus (scc ..) ..) since that construct is common and
13686 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13687 ;; cases where it is no more expensive than (neg (scc ..)).
13689 ;; Have reload force a constant into a register for the simple insns that
13690 ;; otherwise won't accept constants. We do this because it is faster than
13691 ;; the cmp/mfcr sequence we would otherwise generate.
13693 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13694 (DI "rKJI")])
13696 (define_insn_and_split "*eq<mode>"
13697 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13698 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13699 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13700 "!TARGET_POWER"
13701 "#"
13702 "!TARGET_POWER"
13703 [(set (match_dup 0)
13704 (clz:GPR (match_dup 3)))
13705 (set (match_dup 0)
13706 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13707 {
13708 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13709 {
13710 /* Use output operand as intermediate. */
13711 operands[3] = operands[0];
13713 if (logical_operand (operands[2], <MODE>mode))
13714 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13715 gen_rtx_XOR (<MODE>mode,
13716 operands[1], operands[2])));
13717 else
13718 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13719 gen_rtx_PLUS (<MODE>mode, operands[1],
13720 negate_rtx (<MODE>mode,
13721 operands[2]))));
13722 }
13723 else
13724 operands[3] = operands[1];
13726 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13727 })
13729 (define_insn_and_split "*eq<mode>_compare"
13730 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13731 (compare:CC
13732 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13733 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13734 (const_int 0)))
13735 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13736 (eq:P (match_dup 1) (match_dup 2)))]
13737 "!TARGET_POWER && optimize_size"
13738 "#"
13739 "!TARGET_POWER && optimize_size"
13740 [(set (match_dup 0)
13741 (clz:P (match_dup 4)))
13742 (parallel [(set (match_dup 3)
13743 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13744 (const_int 0)))
13745 (set (match_dup 0)
13746 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13747 {
13748 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13749 {
13750 /* Use output operand as intermediate. */
13751 operands[4] = operands[0];
13753 if (logical_operand (operands[2], <MODE>mode))
13754 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13755 gen_rtx_XOR (<MODE>mode,
13756 operands[1], operands[2])));
13757 else
13758 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13759 gen_rtx_PLUS (<MODE>mode, operands[1],
13760 negate_rtx (<MODE>mode,
13761 operands[2]))));
13762 }
13763 else
13764 operands[4] = operands[1];
13766 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13767 })
13769 (define_insn "*eqsi_power"
13770 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
13771 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13772 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
13773 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
13774 "TARGET_POWER"
13775 "@
13776 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13777 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
13778 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13779 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13780 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
13781 [(set_attr "type" "three,two,three,three,three")
13782 (set_attr "length" "12,8,12,12,12")])
13784 ;; We have insns of the form shown by the first define_insn below. If
13785 ;; there is something inside the comparison operation, we must split it.
13786 (define_split
13787 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13788 (plus:SI (match_operator 1 "comparison_operator"
13789 [(match_operand:SI 2 "" "")
13790 (match_operand:SI 3
13791 "reg_or_cint_operand" "")])
13792 (match_operand:SI 4 "gpc_reg_operand" "")))
13793 (clobber (match_operand:SI 5 "register_operand" ""))]
13794 "! gpc_reg_operand (operands[2], SImode)"
13795 [(set (match_dup 5) (match_dup 2))
13796 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
13797 (match_dup 4)))])
13799 (define_insn "*plus_eqsi"
13800 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13801 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13802 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13803 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13804 "TARGET_32BIT"
13805 "@
13806 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13807 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
13808 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13809 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13810 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13811 [(set_attr "type" "three,two,three,three,three")
13812 (set_attr "length" "12,8,12,12,12")])
13814 (define_insn "*compare_plus_eqsi"
13815 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13816 (compare:CC
13817 (plus:SI
13818 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13819 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13820 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13821 (const_int 0)))
13822 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13823 "TARGET_32BIT && optimize_size"
13824 "@
13825 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13826 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
13827 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13828 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13829 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13830 #
13831 #
13832 #
13833 #
13834 #"
13835 [(set_attr "type" "compare")
13836 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13838 (define_split
13839 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13840 (compare:CC
13841 (plus:SI
13842 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13843 (match_operand:SI 2 "scc_eq_operand" ""))
13844 (match_operand:SI 3 "gpc_reg_operand" ""))
13845 (const_int 0)))
13846 (clobber (match_scratch:SI 4 ""))]
13847 "TARGET_32BIT && optimize_size && reload_completed"
13848 [(set (match_dup 4)
13849 (plus:SI (eq:SI (match_dup 1)
13850 (match_dup 2))
13851 (match_dup 3)))
13852 (set (match_dup 0)
13853 (compare:CC (match_dup 4)
13854 (const_int 0)))]
13855 "")
13857 (define_insn "*plus_eqsi_compare"
13858 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13859 (compare:CC
13860 (plus:SI
13861 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13862 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13863 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13864 (const_int 0)))
13865 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13866 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13867 "TARGET_32BIT && optimize_size"
13868 "@
13869 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13870 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
13871 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13872 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13873 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13874 #
13875 #
13876 #
13877 #
13878 #"
13879 [(set_attr "type" "compare")
13880 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13882 (define_split
13883 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13884 (compare:CC
13885 (plus:SI
13886 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13887 (match_operand:SI 2 "scc_eq_operand" ""))
13888 (match_operand:SI 3 "gpc_reg_operand" ""))
13889 (const_int 0)))
13890 (set (match_operand:SI 0 "gpc_reg_operand" "")
13891 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13892 "TARGET_32BIT && optimize_size && reload_completed"
13893 [(set (match_dup 0)
13894 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13895 (set (match_dup 4)
13896 (compare:CC (match_dup 0)
13897 (const_int 0)))]
13898 "")
13900 (define_insn "*neg_eq0<mode>"
13901 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13902 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13903 (const_int 0))))]
13904 ""
13905 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
13906 [(set_attr "type" "two")
13907 (set_attr "length" "8")])
13909 (define_insn_and_split "*neg_eq<mode>"
13910 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13911 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13912 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13913 ""
13914 "#"
13915 ""
13916 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13917 {
13918 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13919 {
13920 /* Use output operand as intermediate. */
13921 operands[3] = operands[0];
13923 if (logical_operand (operands[2], <MODE>mode))
13924 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13925 gen_rtx_XOR (<MODE>mode,
13926 operands[1], operands[2])));
13927 else
13928 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13929 gen_rtx_PLUS (<MODE>mode, operands[1],
13930 negate_rtx (<MODE>mode,
13931 operands[2]))));
13932 }
13933 else
13934 operands[3] = operands[1];
13935 })
13937 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
13938 ;; since it nabs/sr is just as fast.
13939 (define_insn "*ne0si"
13940 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13941 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13942 (const_int 31)))
13943 (clobber (match_scratch:SI 2 "=&r"))]
13944 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
13945 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
13946 [(set_attr "type" "two")
13947 (set_attr "length" "8")])
13949 (define_insn "*ne0di"
13950 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13951 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13952 (const_int 63)))
13953 (clobber (match_scratch:DI 2 "=&r"))]
13954 "TARGET_64BIT"
13955 "addic %2,%1,-1\;subfe %0,%2,%1"
13956 [(set_attr "type" "two")
13957 (set_attr "length" "8")])
13959 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
13960 (define_insn "*plus_ne0si"
13961 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13962 (plus:SI (lshiftrt:SI
13963 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13964 (const_int 31))
13965 (match_operand:SI 2 "gpc_reg_operand" "r")))
13966 (clobber (match_scratch:SI 3 "=&r"))]
13967 "TARGET_32BIT"
13968 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
13969 [(set_attr "type" "two")
13970 (set_attr "length" "8")])
13972 (define_insn "*plus_ne0di"
13973 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13974 (plus:DI (lshiftrt:DI
13975 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13976 (const_int 63))
13977 (match_operand:DI 2 "gpc_reg_operand" "r")))
13978 (clobber (match_scratch:DI 3 "=&r"))]
13979 "TARGET_64BIT"
13980 "addic %3,%1,-1\;addze %0,%2"
13981 [(set_attr "type" "two")
13982 (set_attr "length" "8")])
13984 (define_insn "*compare_plus_ne0si"
13985 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13986 (compare:CC
13987 (plus:SI (lshiftrt:SI
13988 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13989 (const_int 31))
13990 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13991 (const_int 0)))
13992 (clobber (match_scratch:SI 3 "=&r,&r"))
13993 (clobber (match_scratch:SI 4 "=X,&r"))]
13994 "TARGET_32BIT"
13995 "@
13996 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
13997 #"
13998 [(set_attr "type" "compare")
13999 (set_attr "length" "8,12")])
14001 (define_split
14002 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14003 (compare:CC
14004 (plus:SI (lshiftrt:SI
14005 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
14006 (const_int 31))
14007 (match_operand:SI 2 "gpc_reg_operand" ""))
14008 (const_int 0)))
14009 (clobber (match_scratch:SI 3 ""))
14010 (clobber (match_scratch:SI 4 ""))]
14011 "TARGET_32BIT && reload_completed"
14012 [(parallel [(set (match_dup 3)
14013 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
14014 (const_int 31))
14015 (match_dup 2)))
14016 (clobber (match_dup 4))])
14017 (set (match_dup 0)
14018 (compare:CC (match_dup 3)
14019 (const_int 0)))]
14020 "")
14022 (define_insn "*compare_plus_ne0di"
14023 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14024 (compare:CC
14025 (plus:DI (lshiftrt:DI
14026 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
14027 (const_int 63))
14028 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14029 (const_int 0)))
14030 (clobber (match_scratch:DI 3 "=&r,&r"))]
14031 "TARGET_64BIT"
14032 "@
14033 addic %3,%1,-1\;addze. %3,%2
14034 #"
14035 [(set_attr "type" "compare")
14036 (set_attr "length" "8,12")])
14038 (define_split
14039 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14040 (compare:CC
14041 (plus:DI (lshiftrt:DI
14042 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
14043 (const_int 63))
14044 (match_operand:DI 2 "gpc_reg_operand" ""))
14045 (const_int 0)))
14046 (clobber (match_scratch:DI 3 ""))]
14047 "TARGET_64BIT && reload_completed"
14048 [(set (match_dup 3)
14049 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
14050 (const_int 63))
14051 (match_dup 2)))
14052 (set (match_dup 0)
14053 (compare:CC (match_dup 3)
14054 (const_int 0)))]
14055 "")
14057 (define_insn "*plus_ne0si_compare"
14058 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14059 (compare:CC
14060 (plus:SI (lshiftrt:SI
14061 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
14062 (const_int 31))
14063 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14064 (const_int 0)))
14065 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14066 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14067 (match_dup 2)))
14068 (clobber (match_scratch:SI 3 "=&r,&r"))]
14069 "TARGET_32BIT"
14070 "@
14071 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
14072 #"
14073 [(set_attr "type" "compare")
14074 (set_attr "length" "8,12")])
14076 (define_split
14077 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14078 (compare:CC
14079 (plus:SI (lshiftrt:SI
14080 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
14081 (const_int 31))
14082 (match_operand:SI 2 "gpc_reg_operand" ""))
14083 (const_int 0)))
14084 (set (match_operand:SI 0 "gpc_reg_operand" "")
14085 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14086 (match_dup 2)))
14087 (clobber (match_scratch:SI 3 ""))]
14088 "TARGET_32BIT && reload_completed"
14089 [(parallel [(set (match_dup 0)
14090 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14091 (match_dup 2)))
14092 (clobber (match_dup 3))])
14093 (set (match_dup 4)
14094 (compare:CC (match_dup 0)
14095 (const_int 0)))]
14096 "")
14098 (define_insn "*plus_ne0di_compare"
14099 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14100 (compare:CC
14101 (plus:DI (lshiftrt:DI
14102 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
14103 (const_int 63))
14104 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14105 (const_int 0)))
14106 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
14107 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14108 (match_dup 2)))
14109 (clobber (match_scratch:DI 3 "=&r,&r"))]
14110 "TARGET_64BIT"
14111 "@
14112 addic %3,%1,-1\;addze. %0,%2
14113 #"
14114 [(set_attr "type" "compare")
14115 (set_attr "length" "8,12")])
14117 (define_split
14118 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
14119 (compare:CC
14120 (plus:DI (lshiftrt:DI
14121 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
14122 (const_int 63))
14123 (match_operand:DI 2 "gpc_reg_operand" ""))
14124 (const_int 0)))
14125 (set (match_operand:DI 0 "gpc_reg_operand" "")
14126 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14127 (match_dup 2)))
14128 (clobber (match_scratch:DI 3 ""))]
14129 "TARGET_64BIT && reload_completed"
14130 [(parallel [(set (match_dup 0)
14131 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14132 (match_dup 2)))
14133 (clobber (match_dup 3))])
14134 (set (match_dup 4)
14135 (compare:CC (match_dup 0)
14136 (const_int 0)))]
14137 "")
14139 (define_insn ""
14140 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14141 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14142 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
14143 (clobber (match_scratch:SI 3 "=r,X"))]
14144 "TARGET_POWER"
14145 "@
14146 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
14147 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
14148 [(set_attr "length" "12")])
14150 (define_insn ""
14151 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14152 (compare:CC
14153 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14154 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14155 (const_int 0)))
14156 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
14157 (le:SI (match_dup 1) (match_dup 2)))
14158 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
14159 "TARGET_POWER"
14160 "@
14161 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14162 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
14163 #
14164 #"
14165 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
14166 (set_attr "length" "12,12,16,16")])
14168 (define_split
14169 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14170 (compare:CC
14171 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14172 (match_operand:SI 2 "reg_or_short_operand" ""))
14173 (const_int 0)))
14174 (set (match_operand:SI 0 "gpc_reg_operand" "")
14175 (le:SI (match_dup 1) (match_dup 2)))
14176 (clobber (match_scratch:SI 3 ""))]
14177 "TARGET_POWER && reload_completed"
14178 [(parallel [(set (match_dup 0)
14179 (le:SI (match_dup 1) (match_dup 2)))
14180 (clobber (match_dup 3))])
14181 (set (match_dup 4)
14182 (compare:CC (match_dup 0)
14183 (const_int 0)))]
14184 "")
14186 (define_insn ""
14187 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14188 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14189 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
14190 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
14191 "TARGET_POWER"
14192 "@
14193 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
14194 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
14195 [(set_attr "length" "12")])
14197 (define_insn ""
14198 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14199 (compare:CC
14200 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14201 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14202 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14203 (const_int 0)))
14204 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14205 "TARGET_POWER"
14206 "@
14207 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14208 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
14209 #
14210 #"
14211 [(set_attr "type" "compare")
14212 (set_attr "length" "12,12,16,16")])
14214 (define_split
14215 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14216 (compare:CC
14217 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14218 (match_operand:SI 2 "reg_or_short_operand" ""))
14219 (match_operand:SI 3 "gpc_reg_operand" ""))
14220 (const_int 0)))
14221 (clobber (match_scratch:SI 4 ""))]
14222 "TARGET_POWER && reload_completed"
14223 [(set (match_dup 4)
14224 (plus:SI (le:SI (match_dup 1) (match_dup 2))
14225 (match_dup 3)))
14226 (set (match_dup 0)
14227 (compare:CC (match_dup 4)
14228 (const_int 0)))]
14229 "")
14231 (define_insn ""
14232 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14233 (compare:CC
14234 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14235 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14236 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14237 (const_int 0)))
14238 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14239 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14240 "TARGET_POWER"
14241 "@
14242 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14243 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
14244 #
14245 #"
14246 [(set_attr "type" "compare")
14247 (set_attr "length" "12,12,16,16")])
14249 (define_split
14250 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14251 (compare:CC
14252 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14253 (match_operand:SI 2 "reg_or_short_operand" ""))
14254 (match_operand:SI 3 "gpc_reg_operand" ""))
14255 (const_int 0)))
14256 (set (match_operand:SI 0 "gpc_reg_operand" "")
14257 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14258 "TARGET_POWER && reload_completed"
14259 [(set (match_dup 0)
14260 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14261 (set (match_dup 4)
14262 (compare:CC (match_dup 0)
14263 (const_int 0)))]
14264 "")
14266 (define_insn ""
14267 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14268 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14269 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
14270 "TARGET_POWER"
14271 "@
14272 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
14273 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
14274 [(set_attr "length" "12")])
14276 (define_insn "*leu<mode>"
14277 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14278 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14279 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14280 ""
14281 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14282 [(set_attr "type" "three")
14283 (set_attr "length" "12")])
14285 (define_insn "*leu<mode>_compare"
14286 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14287 (compare:CC
14288 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14289 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14290 (const_int 0)))
14291 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14292 (leu:P (match_dup 1) (match_dup 2)))]
14293 ""
14294 "@
14295 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14296 #"
14297 [(set_attr "type" "compare")
14298 (set_attr "length" "12,16")])
14300 (define_split
14301 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14302 (compare:CC
14303 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
14304 (match_operand:P 2 "reg_or_short_operand" ""))
14305 (const_int 0)))
14306 (set (match_operand:P 0 "gpc_reg_operand" "")
14307 (leu:P (match_dup 1) (match_dup 2)))]
14308 "reload_completed"
14309 [(set (match_dup 0)
14310 (leu:P (match_dup 1) (match_dup 2)))
14311 (set (match_dup 3)
14312 (compare:CC (match_dup 0)
14313 (const_int 0)))]
14314 "")
14316 (define_insn "*plus_leu<mode>"
14317 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14318 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14319 (match_operand:P 2 "reg_or_short_operand" "rI"))
14320 (match_operand:P 3 "gpc_reg_operand" "r")))]
14321 ""
14322 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
14323 [(set_attr "type" "two")
14324 (set_attr "length" "8")])
14326 (define_insn ""
14327 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14328 (compare:CC
14329 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14330 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14331 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14332 (const_int 0)))
14333 (clobber (match_scratch:SI 4 "=&r,&r"))]
14334 "TARGET_32BIT"
14335 "@
14336 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
14337 #"
14338 [(set_attr "type" "compare")
14339 (set_attr "length" "8,12")])
14341 (define_split
14342 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14343 (compare:CC
14344 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14345 (match_operand:SI 2 "reg_or_short_operand" ""))
14346 (match_operand:SI 3 "gpc_reg_operand" ""))
14347 (const_int 0)))
14348 (clobber (match_scratch:SI 4 ""))]
14349 "TARGET_32BIT && reload_completed"
14350 [(set (match_dup 4)
14351 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
14352 (match_dup 3)))
14353 (set (match_dup 0)
14354 (compare:CC (match_dup 4)
14355 (const_int 0)))]
14356 "")
14358 (define_insn ""
14359 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14360 (compare:CC
14361 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14362 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14363 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14364 (const_int 0)))
14365 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14366 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14367 "TARGET_32BIT"
14368 "@
14369 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
14370 #"
14371 [(set_attr "type" "compare")
14372 (set_attr "length" "8,12")])
14374 (define_split
14375 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14376 (compare:CC
14377 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14378 (match_operand:SI 2 "reg_or_short_operand" ""))
14379 (match_operand:SI 3 "gpc_reg_operand" ""))
14380 (const_int 0)))
14381 (set (match_operand:SI 0 "gpc_reg_operand" "")
14382 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14383 "TARGET_32BIT && reload_completed"
14384 [(set (match_dup 0)
14385 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14386 (set (match_dup 4)
14387 (compare:CC (match_dup 0)
14388 (const_int 0)))]
14389 "")
14391 (define_insn "*neg_leu<mode>"
14392 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14393 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14394 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14395 ""
14396 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
14397 [(set_attr "type" "three")
14398 (set_attr "length" "12")])
14400 (define_insn "*and_neg_leu<mode>"
14401 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14402 (and:P (neg:P
14403 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14404 (match_operand:P 2 "reg_or_short_operand" "rI")))
14405 (match_operand:P 3 "gpc_reg_operand" "r")))]
14406 ""
14407 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14408 [(set_attr "type" "three")
14409 (set_attr "length" "12")])
14411 (define_insn ""
14412 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14413 (compare:CC
14414 (and:SI (neg:SI
14415 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14416 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14417 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14418 (const_int 0)))
14419 (clobber (match_scratch:SI 4 "=&r,&r"))]
14420 "TARGET_32BIT"
14421 "@
14422 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14423 #"
14424 [(set_attr "type" "compare")
14425 (set_attr "length" "12,16")])
14427 (define_split
14428 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14429 (compare:CC
14430 (and:SI (neg:SI
14431 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14432 (match_operand:SI 2 "reg_or_short_operand" "")))
14433 (match_operand:SI 3 "gpc_reg_operand" ""))
14434 (const_int 0)))
14435 (clobber (match_scratch:SI 4 ""))]
14436 "TARGET_32BIT && reload_completed"
14437 [(set (match_dup 4)
14438 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14439 (match_dup 3)))
14440 (set (match_dup 0)
14441 (compare:CC (match_dup 4)
14442 (const_int 0)))]
14443 "")
14445 (define_insn ""
14446 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14447 (compare:CC
14448 (and:SI (neg:SI
14449 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14450 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14451 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14452 (const_int 0)))
14453 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14454 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14455 "TARGET_32BIT"
14456 "@
14457 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14458 #"
14459 [(set_attr "type" "compare")
14460 (set_attr "length" "12,16")])
14462 (define_split
14463 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14464 (compare:CC
14465 (and:SI (neg:SI
14466 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14467 (match_operand:SI 2 "reg_or_short_operand" "")))
14468 (match_operand:SI 3 "gpc_reg_operand" ""))
14469 (const_int 0)))
14470 (set (match_operand:SI 0 "gpc_reg_operand" "")
14471 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14472 "TARGET_32BIT && reload_completed"
14473 [(set (match_dup 0)
14474 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14475 (match_dup 3)))
14476 (set (match_dup 4)
14477 (compare:CC (match_dup 0)
14478 (const_int 0)))]
14479 "")
14481 (define_insn ""
14482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14483 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14484 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
14485 "TARGET_POWER"
14486 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14487 [(set_attr "length" "12")])
14489 (define_insn ""
14490 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14491 (compare:CC
14492 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14493 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14494 (const_int 0)))
14495 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14496 (lt:SI (match_dup 1) (match_dup 2)))]
14497 "TARGET_POWER"
14498 "@
14499 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14500 #"
14501 [(set_attr "type" "delayed_compare")
14502 (set_attr "length" "12,16")])
14504 (define_split
14505 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14506 (compare:CC
14507 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14508 (match_operand:SI 2 "reg_or_short_operand" ""))
14509 (const_int 0)))
14510 (set (match_operand:SI 0 "gpc_reg_operand" "")
14511 (lt:SI (match_dup 1) (match_dup 2)))]
14512 "TARGET_POWER && reload_completed"
14513 [(set (match_dup 0)
14514 (lt:SI (match_dup 1) (match_dup 2)))
14515 (set (match_dup 3)
14516 (compare:CC (match_dup 0)
14517 (const_int 0)))]
14518 "")
14520 (define_insn ""
14521 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14522 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14523 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14524 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14525 "TARGET_POWER"
14526 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14527 [(set_attr "length" "12")])
14529 (define_insn ""
14530 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14531 (compare:CC
14532 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14533 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14534 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14535 (const_int 0)))
14536 (clobber (match_scratch:SI 4 "=&r,&r"))]
14537 "TARGET_POWER"
14538 "@
14539 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14540 #"
14541 [(set_attr "type" "compare")
14542 (set_attr "length" "12,16")])
14544 (define_split
14545 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14546 (compare:CC
14547 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14548 (match_operand:SI 2 "reg_or_short_operand" ""))
14549 (match_operand:SI 3 "gpc_reg_operand" ""))
14550 (const_int 0)))
14551 (clobber (match_scratch:SI 4 ""))]
14552 "TARGET_POWER && reload_completed"
14553 [(set (match_dup 4)
14554 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
14555 (match_dup 3)))
14556 (set (match_dup 0)
14557 (compare:CC (match_dup 4)
14558 (const_int 0)))]
14559 "")
14561 (define_insn ""
14562 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14563 (compare:CC
14564 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14565 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14566 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14567 (const_int 0)))
14568 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14569 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14570 "TARGET_POWER"
14571 "@
14572 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14573 #"
14574 [(set_attr "type" "compare")
14575 (set_attr "length" "12,16")])
14577 (define_split
14578 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14579 (compare:CC
14580 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14581 (match_operand:SI 2 "reg_or_short_operand" ""))
14582 (match_operand:SI 3 "gpc_reg_operand" ""))
14583 (const_int 0)))
14584 (set (match_operand:SI 0 "gpc_reg_operand" "")
14585 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14586 "TARGET_POWER && reload_completed"
14587 [(set (match_dup 0)
14588 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14589 (set (match_dup 4)
14590 (compare:CC (match_dup 0)
14591 (const_int 0)))]
14592 "")
14594 (define_insn ""
14595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14596 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14597 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14598 "TARGET_POWER"
14599 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14600 [(set_attr "length" "12")])
14602 (define_insn_and_split "*ltu<mode>"
14603 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14604 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14605 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14606 ""
14607 "#"
14608 ""
14609 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14610 (set (match_dup 0) (neg:P (match_dup 0)))]
14611 "")
14613 (define_insn_and_split "*ltu<mode>_compare"
14614 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14615 (compare:CC
14616 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14617 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14618 (const_int 0)))
14619 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14620 (ltu:P (match_dup 1) (match_dup 2)))]
14621 ""
14622 "#"
14623 ""
14624 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14625 (parallel [(set (match_dup 3)
14626 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14627 (set (match_dup 0) (neg:P (match_dup 0)))])]
14628 "")
14630 (define_insn_and_split "*plus_ltu<mode>"
14631 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14632 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14633 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14634 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14635 ""
14636 "#"
14637 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14638 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14639 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14640 "")
14642 (define_insn_and_split "*plus_ltu<mode>_compare"
14643 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14644 (compare:CC
14645 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14646 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14647 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14648 (const_int 0)))
14649 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14650 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14651 ""
14652 "#"
14653 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14654 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14655 (parallel [(set (match_dup 4)
14656 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14657 (const_int 0)))
14658 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14659 "")
14661 (define_insn "*neg_ltu<mode>"
14662 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14663 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14664 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14665 ""
14666 "@
14667 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
14668 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
14669 [(set_attr "type" "two")
14670 (set_attr "length" "8")])
14672 (define_insn ""
14673 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14674 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14675 (match_operand:SI 2 "reg_or_short_operand" "rI")))
14676 (clobber (match_scratch:SI 3 "=r"))]
14677 "TARGET_POWER"
14678 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
14679 [(set_attr "length" "12")])
14681 (define_insn ""
14682 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14683 (compare:CC
14684 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14685 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14686 (const_int 0)))
14687 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14688 (ge:SI (match_dup 1) (match_dup 2)))
14689 (clobber (match_scratch:SI 3 "=r,r"))]
14690 "TARGET_POWER"
14691 "@
14692 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14693 #"
14694 [(set_attr "type" "compare")
14695 (set_attr "length" "12,16")])
14697 (define_split
14698 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14699 (compare:CC
14700 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14701 (match_operand:SI 2 "reg_or_short_operand" ""))
14702 (const_int 0)))
14703 (set (match_operand:SI 0 "gpc_reg_operand" "")
14704 (ge:SI (match_dup 1) (match_dup 2)))
14705 (clobber (match_scratch:SI 3 ""))]
14706 "TARGET_POWER && reload_completed"
14707 [(parallel [(set (match_dup 0)
14708 (ge:SI (match_dup 1) (match_dup 2)))
14709 (clobber (match_dup 3))])
14710 (set (match_dup 4)
14711 (compare:CC (match_dup 0)
14712 (const_int 0)))]
14713 "")
14715 (define_insn ""
14716 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14717 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14718 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14719 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14720 "TARGET_POWER"
14721 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
14722 [(set_attr "length" "12")])
14724 (define_insn ""
14725 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14726 (compare:CC
14727 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14728 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14729 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14730 (const_int 0)))
14731 (clobber (match_scratch:SI 4 "=&r,&r"))]
14732 "TARGET_POWER"
14733 "@
14734 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14735 #"
14736 [(set_attr "type" "compare")
14737 (set_attr "length" "12,16")])
14739 (define_split
14740 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14741 (compare:CC
14742 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14743 (match_operand:SI 2 "reg_or_short_operand" ""))
14744 (match_operand:SI 3 "gpc_reg_operand" ""))
14745 (const_int 0)))
14746 (clobber (match_scratch:SI 4 ""))]
14747 "TARGET_POWER && reload_completed"
14748 [(set (match_dup 4)
14749 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
14750 (match_dup 3)))
14751 (set (match_dup 0)
14752 (compare:CC (match_dup 4)
14753 (const_int 0)))]
14754 "")
14756 (define_insn ""
14757 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14758 (compare:CC
14759 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14760 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14761 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14762 (const_int 0)))
14763 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14764 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14765 "TARGET_POWER"
14766 "@
14767 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14768 #"
14769 [(set_attr "type" "compare")
14770 (set_attr "length" "12,16")])
14772 (define_split
14773 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14774 (compare:CC
14775 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14776 (match_operand:SI 2 "reg_or_short_operand" ""))
14777 (match_operand:SI 3 "gpc_reg_operand" ""))
14778 (const_int 0)))
14779 (set (match_operand:SI 0 "gpc_reg_operand" "")
14780 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14781 "TARGET_POWER && reload_completed"
14782 [(set (match_dup 0)
14783 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14784 (set (match_dup 4)
14785 (compare:CC (match_dup 0)
14786 (const_int 0)))]
14787 "")
14789 (define_insn ""
14790 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14791 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14792 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14793 "TARGET_POWER"
14794 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
14795 [(set_attr "length" "12")])
14797 (define_insn "*geu<mode>"
14798 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14799 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14800 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14801 ""
14802 "@
14803 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
14804 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14805 [(set_attr "type" "three")
14806 (set_attr "length" "12")])
14808 (define_insn "*geu<mode>_compare"
14809 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14810 (compare:CC
14811 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14812 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14813 (const_int 0)))
14814 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14815 (geu:P (match_dup 1) (match_dup 2)))]
14816 ""
14817 "@
14818 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14819 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14820 #
14821 #"
14822 [(set_attr "type" "compare")
14823 (set_attr "length" "12,12,16,16")])
14825 (define_split
14826 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14827 (compare:CC
14828 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14829 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14830 (const_int 0)))
14831 (set (match_operand:P 0 "gpc_reg_operand" "")
14832 (geu:P (match_dup 1) (match_dup 2)))]
14833 "reload_completed"
14834 [(set (match_dup 0)
14835 (geu:P (match_dup 1) (match_dup 2)))
14836 (set (match_dup 3)
14837 (compare:CC (match_dup 0)
14838 (const_int 0)))]
14839 "")
14841 (define_insn "*plus_geu<mode>"
14842 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14843 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14844 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14845 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14846 ""
14847 "@
14848 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
14849 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
14850 [(set_attr "type" "two")
14851 (set_attr "length" "8")])
14853 (define_insn ""
14854 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14855 (compare:CC
14856 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14857 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14858 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14859 (const_int 0)))
14860 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14861 "TARGET_32BIT"
14862 "@
14863 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
14864 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
14865 #
14866 #"
14867 [(set_attr "type" "compare")
14868 (set_attr "length" "8,8,12,12")])
14870 (define_split
14871 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14872 (compare:CC
14873 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14874 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14875 (match_operand:SI 3 "gpc_reg_operand" ""))
14876 (const_int 0)))
14877 (clobber (match_scratch:SI 4 ""))]
14878 "TARGET_32BIT && reload_completed"
14879 [(set (match_dup 4)
14880 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14881 (match_dup 3)))
14882 (set (match_dup 0)
14883 (compare:CC (match_dup 4)
14884 (const_int 0)))]
14885 "")
14887 (define_insn ""
14888 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14889 (compare:CC
14890 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14891 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14892 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14893 (const_int 0)))
14894 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14895 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14896 "TARGET_32BIT"
14897 "@
14898 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
14899 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
14900 #
14901 #"
14902 [(set_attr "type" "compare")
14903 (set_attr "length" "8,8,12,12")])
14905 (define_split
14906 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14907 (compare:CC
14908 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14909 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14910 (match_operand:SI 3 "gpc_reg_operand" ""))
14911 (const_int 0)))
14912 (set (match_operand:SI 0 "gpc_reg_operand" "")
14913 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14914 "TARGET_32BIT && reload_completed"
14915 [(set (match_dup 0)
14916 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14917 (set (match_dup 4)
14918 (compare:CC (match_dup 0)
14919 (const_int 0)))]
14920 "")
14922 (define_insn "*neg_geu<mode>"
14923 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14924 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14925 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14926 ""
14927 "@
14928 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
14929 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
14930 [(set_attr "type" "three")
14931 (set_attr "length" "12")])
14933 (define_insn "*and_neg_geu<mode>"
14934 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14935 (and:P (neg:P
14936 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14937 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14938 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14939 ""
14940 "@
14941 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
14942 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14943 [(set_attr "type" "three")
14944 (set_attr "length" "12")])
14946 (define_insn ""
14947 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14948 (compare:CC
14949 (and:SI (neg:SI
14950 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14951 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14952 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14953 (const_int 0)))
14954 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14955 "TARGET_32BIT"
14956 "@
14957 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14958 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14959 #
14960 #"
14961 [(set_attr "type" "compare")
14962 (set_attr "length" "12,12,16,16")])
14964 (define_split
14965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14966 (compare:CC
14967 (and:SI (neg:SI
14968 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14969 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14970 (match_operand:SI 3 "gpc_reg_operand" ""))
14971 (const_int 0)))
14972 (clobber (match_scratch:SI 4 ""))]
14973 "TARGET_32BIT && reload_completed"
14974 [(set (match_dup 4)
14975 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14976 (match_dup 3)))
14977 (set (match_dup 0)
14978 (compare:CC (match_dup 4)
14979 (const_int 0)))]
14980 "")
14982 (define_insn ""
14983 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14984 (compare:CC
14985 (and:SI (neg:SI
14986 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14987 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14988 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14989 (const_int 0)))
14990 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14991 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14992 "TARGET_32BIT"
14993 "@
14994 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14995 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14996 #
14997 #"
14998 [(set_attr "type" "compare")
14999 (set_attr "length" "12,12,16,16")])
15001 (define_split
15002 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
15003 (compare:CC
15004 (and:SI (neg:SI
15005 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
15006 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
15007 (match_operand:SI 3 "gpc_reg_operand" ""))
15008 (const_int 0)))
15009 (set (match_operand:SI 0 "gpc_reg_operand" "")
15010 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
15011 "TARGET_32BIT && reload_completed"
15012 [(set (match_dup 0)
15013 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
15014 (set (match_dup 4)
15015 (compare:CC (match_dup 0)
15016 (const_int 0)))]
15017 "")
15019 (define_insn ""
15020 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15021 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15022 (match_operand:SI 2 "reg_or_short_operand" "r")))]
15023 "TARGET_POWER"
15024 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
15025 [(set_attr "length" "12")])
15027 (define_insn ""
15028 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15029 (compare:CC
15030 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15031 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15032 (const_int 0)))
15033 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
15034 (gt:SI (match_dup 1) (match_dup 2)))]
15035 "TARGET_POWER"
15036 "@
15037 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
15038 #"
15039 [(set_attr "type" "delayed_compare")
15040 (set_attr "length" "12,16")])
15042 (define_split
15043 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
15044 (compare:CC
15045 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15046 (match_operand:SI 2 "reg_or_short_operand" ""))
15047 (const_int 0)))
15048 (set (match_operand:SI 0 "gpc_reg_operand" "")
15049 (gt:SI (match_dup 1) (match_dup 2)))]
15050 "TARGET_POWER && reload_completed"
15051 [(set (match_dup 0)
15052 (gt:SI (match_dup 1) (match_dup 2)))
15053 (set (match_dup 3)
15054 (compare:CC (match_dup 0)
15055 (const_int 0)))]
15056 "")
15058 (define_insn "*plus_gt0<mode>"
15059 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
15060 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
15061 (const_int 0))
15062 (match_operand:P 2 "gpc_reg_operand" "r")))]
15063 ""
15064 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
15065 [(set_attr "type" "three")
15066 (set_attr "length" "12")])
15068 (define_insn ""
15069 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15070 (compare:CC
15071 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15072 (const_int 0))
15073 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
15074 (const_int 0)))
15075 (clobber (match_scratch:SI 3 "=&r,&r"))]
15076 "TARGET_32BIT"
15077 "@
15078 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
15079 #"
15080 [(set_attr "type" "compare")
15081 (set_attr "length" "12,16")])
15083 (define_split
15084 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
15085 (compare:CC
15086 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15087 (const_int 0))
15088 (match_operand:SI 2 "gpc_reg_operand" ""))
15089 (const_int 0)))
15090 (clobber (match_scratch:SI 3 ""))]
15091 "TARGET_32BIT && reload_completed"
15092 [(set (match_dup 3)
15093 (plus:SI (gt:SI (match_dup 1) (const_int 0))
15094 (match_dup 2)))
15095 (set (match_dup 0)
15096 (compare:CC (match_dup 3)
15097 (const_int 0)))]
15098 "")
15100 (define_insn ""
15101 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15102 (compare:CC
15103 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
15104 (const_int 0))
15105 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
15106 (const_int 0)))
15107 (clobber (match_scratch:DI 3 "=&r,&r"))]
15108 "TARGET_64BIT"
15109 "@
15110 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
15111 #"
15112 [(set_attr "type" "compare")
15113 (set_attr "length" "12,16")])
15115 (define_split
15116 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
15117 (compare:CC
15118 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
15119 (const_int 0))
15120 (match_operand:DI 2 "gpc_reg_operand" ""))
15121 (const_int 0)))
15122 (clobber (match_scratch:DI 3 ""))]
15123 "TARGET_64BIT && reload_completed"
15124 [(set (match_dup 3)
15125 (plus:DI (gt:DI (match_dup 1) (const_int 0))
15126 (match_dup 2)))
15127 (set (match_dup 0)
15128 (compare:CC (match_dup 3)
15129 (const_int 0)))]
15130 "")
15132 (define_insn ""
15133 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15134 (compare:CC
15135 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15136 (const_int 0))
15137 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
15138 (const_int 0)))
15139 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
15140 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
15141 "TARGET_32BIT"
15142 "@
15143 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
15144 #"
15145 [(set_attr "type" "compare")
15146 (set_attr "length" "12,16")])
15148 (define_split
15149 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
15150 (compare:CC
15151 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15152 (const_int 0))
15153 (match_operand:SI 2 "gpc_reg_operand" ""))
15154 (const_int 0)))
15155 (set (match_operand:SI 0 "gpc_reg_operand" "")
15156 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
15157 "TARGET_32BIT && reload_completed"
15158 [(set (match_dup 0)
15159 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
15160 (set (match_dup 3)
15161 (compare:CC (match_dup 0)
15162 (const_int 0)))]
15163 "")
15165 (define_insn ""
15166 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15167 (compare:CC
15168 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
15169 (const_int 0))
15170 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
15171 (const_int 0)))
15172 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
15173 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
15174 "TARGET_64BIT"
15175 "@
15176 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
15177 #"
15178 [(set_attr "type" "compare")
15179 (set_attr "length" "12,16")])
15181 (define_split
15182 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
15183 (compare:CC
15184 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
15185 (const_int 0))
15186 (match_operand:DI 2 "gpc_reg_operand" ""))
15187 (const_int 0)))
15188 (set (match_operand:DI 0 "gpc_reg_operand" "")
15189 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
15190 "TARGET_64BIT && reload_completed"
15191 [(set (match_dup 0)
15192 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
15193 (set (match_dup 3)
15194 (compare:CC (match_dup 0)
15195 (const_int 0)))]
15196 "")
15198 (define_insn ""
15199 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
15200 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15201 (match_operand:SI 2 "reg_or_short_operand" "r"))
15202 (match_operand:SI 3 "gpc_reg_operand" "r")))]
15203 "TARGET_POWER"
15204 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
15205 [(set_attr "length" "12")])
15207 (define_insn ""
15208 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15209 (compare:CC
15210 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15211 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15212 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
15213 (const_int 0)))
15214 (clobber (match_scratch:SI 4 "=&r,&r"))]
15215 "TARGET_POWER"
15216 "@
15217 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
15218 #"
15219 [(set_attr "type" "compare")
15220 (set_attr "length" "12,16")])
15222 (define_split
15223 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
15224 (compare:CC
15225 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15226 (match_operand:SI 2 "reg_or_short_operand" ""))
15227 (match_operand:SI 3 "gpc_reg_operand" ""))
15228 (const_int 0)))
15229 (clobber (match_scratch:SI 4 ""))]
15230 "TARGET_POWER && reload_completed"
15231 [(set (match_dup 4)
15232 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
15233 (set (match_dup 0)
15234 (compare:CC (match_dup 4)
15235 (const_int 0)))]
15236 "")
15238 (define_insn ""
15239 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
15240 (compare:CC
15241 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15242 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15243 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
15244 (const_int 0)))
15245 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
15246 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
15247 "TARGET_POWER"
15248 "@
15249 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
15250 #"
15251 [(set_attr "type" "compare")
15252 (set_attr "length" "12,16")])
15254 (define_split
15255 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
15256 (compare:CC
15257 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15258 (match_operand:SI 2 "reg_or_short_operand" ""))
15259 (match_operand:SI 3 "gpc_reg_operand" ""))
15260 (const_int 0)))
15261 (set (match_operand:SI 0 "gpc_reg_operand" "")
15262 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
15263 "TARGET_POWER && reload_completed"
15264 [(set (match_dup 0)
15265 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
15266 (set (match_dup 4)
15267 (compare:CC (match_dup 0)
15268 (const_int 0)))]
15269 "")
15271 (define_insn ""
15272 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15273 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15274 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
15275 "TARGET_POWER"
15276 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
15277 [(set_attr "length" "12")])
15279 (define_insn_and_split "*gtu<mode>"
15280 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15281 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15282 (match_operand:P 2 "reg_or_short_operand" "rI")))]
15283 ""
15284 "#"
15285 ""
15286 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15287 (set (match_dup 0) (neg:P (match_dup 0)))]
15288 "")
15290 (define_insn_and_split "*gtu<mode>_compare"
15291 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15292 (compare:CC
15293 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
15294 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
15295 (const_int 0)))
15296 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
15297 (gtu:P (match_dup 1) (match_dup 2)))]
15298 ""
15299 "#"
15300 ""
15301 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15302 (parallel [(set (match_dup 3)
15303 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
15304 (set (match_dup 0) (neg:P (match_dup 0)))])]
15305 "")
15307 (define_insn_and_split "*plus_gtu<mode>"
15308 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
15309 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15310 (match_operand:P 2 "reg_or_short_operand" "rI"))
15311 (match_operand:P 3 "reg_or_short_operand" "rI")))]
15312 ""
15313 "#"
15314 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
15315 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15316 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
15317 "")
15319 (define_insn_and_split "*plus_gtu<mode>_compare"
15320 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
15321 (compare:CC
15322 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
15323 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
15324 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
15325 (const_int 0)))
15326 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
15327 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
15328 ""
15329 "#"
15330 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
15331 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15332 (parallel [(set (match_dup 4)
15333 (compare:CC (minus:P (match_dup 3) (match_dup 0))
15334 (const_int 0)))
15335 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
15336 "")
15338 (define_insn "*neg_gtu<mode>"
15339 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15340 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15341 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
15342 ""
15343 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
15344 [(set_attr "type" "two")
15345 (set_attr "length" "8")])
15347 \f
15348 ;; Define both directions of branch and return. If we need a reload
15349 ;; register, we'd rather use CR0 since it is much easier to copy a
15350 ;; register CC value to there.
15352 (define_insn ""
15353 [(set (pc)
15354 (if_then_else (match_operator 1 "branch_comparison_operator"
15355 [(match_operand 2
15356 "cc_reg_operand" "y")
15357 (const_int 0)])
15358 (label_ref (match_operand 0 "" ""))
15359 (pc)))]
15360 ""
15361 "*
15362 {
15363 return output_cbranch (operands[1], \"%l0\", 0, insn);
15364 }"
15365 [(set_attr "type" "branch")])
15367 (define_insn ""
15368 [(set (pc)
15369 (if_then_else (match_operator 0 "branch_comparison_operator"
15370 [(match_operand 1
15371 "cc_reg_operand" "y")
15372 (const_int 0)])
15373 (return)
15374 (pc)))]
15375 "direct_return ()"
15376 "*
15377 {
15378 return output_cbranch (operands[0], NULL, 0, insn);
15379 }"
15380 [(set_attr "type" "jmpreg")
15381 (set_attr "length" "4")])
15383 (define_insn ""
15384 [(set (pc)
15385 (if_then_else (match_operator 1 "branch_comparison_operator"
15386 [(match_operand 2
15387 "cc_reg_operand" "y")
15388 (const_int 0)])
15389 (pc)
15390 (label_ref (match_operand 0 "" ""))))]
15391 ""
15392 "*
15393 {
15394 return output_cbranch (operands[1], \"%l0\", 1, insn);
15395 }"
15396 [(set_attr "type" "branch")])
15398 (define_insn ""
15399 [(set (pc)
15400 (if_then_else (match_operator 0 "branch_comparison_operator"
15401 [(match_operand 1
15402 "cc_reg_operand" "y")
15403 (const_int 0)])
15404 (pc)
15405 (return)))]
15406 "direct_return ()"
15407 "*
15408 {
15409 return output_cbranch (operands[0], NULL, 1, insn);
15410 }"
15411 [(set_attr "type" "jmpreg")
15412 (set_attr "length" "4")])
15414 ;; Logic on condition register values.
15416 ; This pattern matches things like
15417 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
15418 ; (eq:SI (reg:CCFP 68) (const_int 0)))
15419 ; (const_int 1)))
15420 ; which are generated by the branch logic.
15421 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
15423 (define_insn "*cceq_ior_compare"
15424 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15425 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
15426 [(match_operator:SI 2
15427 "branch_positive_comparison_operator"
15428 [(match_operand 3
15429 "cc_reg_operand" "y,y")
15430 (const_int 0)])
15431 (match_operator:SI 4
15432 "branch_positive_comparison_operator"
15433 [(match_operand 5
15434 "cc_reg_operand" "0,y")
15435 (const_int 0)])])
15436 (const_int 1)))]
15437 ""
15438 "cr%q1 %E0,%j2,%j4"
15439 [(set_attr "type" "cr_logical,delayed_cr")])
15441 ; Why is the constant -1 here, but 1 in the previous pattern?
15442 ; Because ~1 has all but the low bit set.
15443 (define_insn ""
15444 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15445 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
15446 [(not:SI (match_operator:SI 2
15447 "branch_positive_comparison_operator"
15448 [(match_operand 3
15449 "cc_reg_operand" "y,y")
15450 (const_int 0)]))
15451 (match_operator:SI 4
15452 "branch_positive_comparison_operator"
15453 [(match_operand 5
15454 "cc_reg_operand" "0,y")
15455 (const_int 0)])])
15456 (const_int -1)))]
15457 ""
15458 "cr%q1 %E0,%j2,%j4"
15459 [(set_attr "type" "cr_logical,delayed_cr")])
15461 (define_insn "*cceq_rev_compare"
15462 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15463 (compare:CCEQ (match_operator:SI 1
15464 "branch_positive_comparison_operator"
15465 [(match_operand 2
15466 "cc_reg_operand" "0,y")
15467 (const_int 0)])
15468 (const_int 0)))]
15469 ""
15470 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
15471 [(set_attr "type" "cr_logical,delayed_cr")])
15473 ;; If we are comparing the result of two comparisons, this can be done
15474 ;; using creqv or crxor.
15476 (define_insn_and_split ""
15477 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
15478 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
15479 [(match_operand 2 "cc_reg_operand" "y")
15480 (const_int 0)])
15481 (match_operator 3 "branch_comparison_operator"
15482 [(match_operand 4 "cc_reg_operand" "y")
15483 (const_int 0)])))]
15484 ""
15485 "#"
15486 ""
15487 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
15488 (match_dup 5)))]
15489 "
15490 {
15491 int positive_1, positive_2;
15493 positive_1 = branch_positive_comparison_operator (operands[1],
15494 GET_MODE (operands[1]));
15495 positive_2 = branch_positive_comparison_operator (operands[3],
15496 GET_MODE (operands[3]));
15498 if (! positive_1)
15499 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
15500 GET_CODE (operands[1])),
15501 SImode,
15502 operands[2], const0_rtx);
15503 else if (GET_MODE (operands[1]) != SImode)
15504 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
15505 operands[2], const0_rtx);
15507 if (! positive_2)
15508 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
15509 GET_CODE (operands[3])),
15510 SImode,
15511 operands[4], const0_rtx);
15512 else if (GET_MODE (operands[3]) != SImode)
15513 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
15514 operands[4], const0_rtx);
15516 if (positive_1 == positive_2)
15517 {
15518 operands[1] = gen_rtx_NOT (SImode, operands[1]);
15519 operands[5] = constm1_rtx;
15520 }
15521 else
15522 {
15523 operands[5] = const1_rtx;
15524 }
15525 }")
15527 ;; Unconditional branch and return.
15529 (define_insn "jump"
15530 [(set (pc)
15531 (label_ref (match_operand 0 "" "")))]
15532 ""
15533 "b %l0"
15534 [(set_attr "type" "branch")])
15536 (define_insn "return"
15537 [(return)]
15538 "direct_return ()"
15539 "{br|blr}"
15540 [(set_attr "type" "jmpreg")])
15542 (define_expand "indirect_jump"
15543 [(set (pc) (match_operand 0 "register_operand" ""))])
15545 (define_insn "*indirect_jump<mode>"
15546 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
15547 ""
15548 "@
15549 bctr
15550 {br|blr}"
15551 [(set_attr "type" "jmpreg")])
15553 ;; Table jump for switch statements:
15554 (define_expand "tablejump"
15555 [(use (match_operand 0 "" ""))
15556 (use (label_ref (match_operand 1 "" "")))]
15557 ""
15558 "
15559 {
15560 if (TARGET_32BIT)
15561 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
15562 else
15563 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
15564 DONE;
15565 }")
15567 (define_expand "tablejumpsi"
15568 [(set (match_dup 3)
15569 (plus:SI (match_operand:SI 0 "" "")
15570 (match_dup 2)))
15571 (parallel [(set (pc) (match_dup 3))
15572 (use (label_ref (match_operand 1 "" "")))])]
15573 "TARGET_32BIT"
15574 "
15575 { operands[0] = force_reg (SImode, operands[0]);
15576 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
15577 operands[3] = gen_reg_rtx (SImode);
15578 }")
15580 (define_expand "tablejumpdi"
15581 [(set (match_dup 4)
15582 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
15583 (set (match_dup 3)
15584 (plus:DI (match_dup 4)
15585 (match_dup 2)))
15586 (parallel [(set (pc) (match_dup 3))
15587 (use (label_ref (match_operand 1 "" "")))])]
15588 "TARGET_64BIT"
15589 "
15590 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
15591 operands[3] = gen_reg_rtx (DImode);
15592 operands[4] = gen_reg_rtx (DImode);
15593 }")
15595 (define_insn "*tablejump<mode>_internal1"
15596 [(set (pc)
15597 (match_operand:P 0 "register_operand" "c,*l"))
15598 (use (label_ref (match_operand 1 "" "")))]
15599 ""
15600 "@
15601 bctr
15602 {br|blr}"
15603 [(set_attr "type" "jmpreg")])
15605 (define_insn "nop"
15606 [(const_int 0)]
15607 ""
15608 "{cror 0,0,0|nop}")
15609 \f
15610 ;; Define the subtract-one-and-jump insns, starting with the template
15611 ;; so loop.c knows what to generate.
15613 (define_expand "doloop_end"
15614 [(use (match_operand 0 "" "")) ; loop pseudo
15615 (use (match_operand 1 "" "")) ; iterations; zero if unknown
15616 (use (match_operand 2 "" "")) ; max iterations
15617 (use (match_operand 3 "" "")) ; loop level
15618 (use (match_operand 4 "" ""))] ; label
15619 ""
15620 "
15621 {
15622 /* Only use this on innermost loops. */
15623 if (INTVAL (operands[3]) > 1)
15624 FAIL;
15625 if (TARGET_64BIT)
15626 {
15627 if (GET_MODE (operands[0]) != DImode)
15628 FAIL;
15629 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
15630 }
15631 else
15632 {
15633 if (GET_MODE (operands[0]) != SImode)
15634 FAIL;
15635 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
15636 }
15637 DONE;
15638 }")
15640 (define_expand "ctr<mode>"
15641 [(parallel [(set (pc)
15642 (if_then_else (ne (match_operand:P 0 "register_operand" "")
15643 (const_int 1))
15644 (label_ref (match_operand 1 "" ""))
15645 (pc)))
15646 (set (match_dup 0)
15647 (plus:P (match_dup 0)
15648 (const_int -1)))
15649 (clobber (match_scratch:CC 2 ""))
15650 (clobber (match_scratch:P 3 ""))])]
15651 ""
15652 "")
15654 ;; We need to be able to do this for any operand, including MEM, or we
15655 ;; will cause reload to blow up since we don't allow output reloads on
15656 ;; JUMP_INSNs.
15657 ;; For the length attribute to be calculated correctly, the
15658 ;; label MUST be operand 0.
15660 (define_insn "*ctr<mode>_internal1"
15661 [(set (pc)
15662 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15663 (const_int 1))
15664 (label_ref (match_operand 0 "" ""))
15665 (pc)))
15666 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15667 (plus:P (match_dup 1)
15668 (const_int -1)))
15669 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15670 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15671 ""
15672 "*
15673 {
15674 if (which_alternative != 0)
15675 return \"#\";
15676 else if (get_attr_length (insn) == 4)
15677 return \"{bdn|bdnz} %l0\";
15678 else
15679 return \"bdz $+8\;b %l0\";
15680 }"
15681 [(set_attr "type" "branch")
15682 (set_attr "length" "*,12,16,16")])
15684 (define_insn "*ctr<mode>_internal2"
15685 [(set (pc)
15686 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15687 (const_int 1))
15688 (pc)
15689 (label_ref (match_operand 0 "" ""))))
15690 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15691 (plus:P (match_dup 1)
15692 (const_int -1)))
15693 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15694 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15695 ""
15696 "*
15697 {
15698 if (which_alternative != 0)
15699 return \"#\";
15700 else if (get_attr_length (insn) == 4)
15701 return \"bdz %l0\";
15702 else
15703 return \"{bdn|bdnz} $+8\;b %l0\";
15704 }"
15705 [(set_attr "type" "branch")
15706 (set_attr "length" "*,12,16,16")])
15708 ;; Similar but use EQ
15710 (define_insn "*ctr<mode>_internal5"
15711 [(set (pc)
15712 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15713 (const_int 1))
15714 (label_ref (match_operand 0 "" ""))
15715 (pc)))
15716 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15717 (plus:P (match_dup 1)
15718 (const_int -1)))
15719 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15720 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15721 ""
15722 "*
15723 {
15724 if (which_alternative != 0)
15725 return \"#\";
15726 else if (get_attr_length (insn) == 4)
15727 return \"bdz %l0\";
15728 else
15729 return \"{bdn|bdnz} $+8\;b %l0\";
15730 }"
15731 [(set_attr "type" "branch")
15732 (set_attr "length" "*,12,16,16")])
15734 (define_insn "*ctr<mode>_internal6"
15735 [(set (pc)
15736 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15737 (const_int 1))
15738 (pc)
15739 (label_ref (match_operand 0 "" ""))))
15740 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15741 (plus:P (match_dup 1)
15742 (const_int -1)))
15743 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15744 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15745 ""
15746 "*
15747 {
15748 if (which_alternative != 0)
15749 return \"#\";
15750 else if (get_attr_length (insn) == 4)
15751 return \"{bdn|bdnz} %l0\";
15752 else
15753 return \"bdz $+8\;b %l0\";
15754 }"
15755 [(set_attr "type" "branch")
15756 (set_attr "length" "*,12,16,16")])
15758 ;; Now the splitters if we could not allocate the CTR register
15760 (define_split
15761 [(set (pc)
15762 (if_then_else (match_operator 2 "comparison_operator"
15763 [(match_operand:P 1 "gpc_reg_operand" "")
15764 (const_int 1)])
15765 (match_operand 5 "" "")
15766 (match_operand 6 "" "")))
15767 (set (match_operand:P 0 "gpc_reg_operand" "")
15768 (plus:P (match_dup 1) (const_int -1)))
15769 (clobber (match_scratch:CC 3 ""))
15770 (clobber (match_scratch:P 4 ""))]
15771 "reload_completed"
15772 [(parallel [(set (match_dup 3)
15773 (compare:CC (plus:P (match_dup 1)
15774 (const_int -1))
15775 (const_int 0)))
15776 (set (match_dup 0)
15777 (plus:P (match_dup 1)
15778 (const_int -1)))])
15779 (set (pc) (if_then_else (match_dup 7)
15780 (match_dup 5)
15781 (match_dup 6)))]
15782 "
15783 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15784 operands[3], const0_rtx); }")
15786 (define_split
15787 [(set (pc)
15788 (if_then_else (match_operator 2 "comparison_operator"
15789 [(match_operand:P 1 "gpc_reg_operand" "")
15790 (const_int 1)])
15791 (match_operand 5 "" "")
15792 (match_operand 6 "" "")))
15793 (set (match_operand:P 0 "nonimmediate_operand" "")
15794 (plus:P (match_dup 1) (const_int -1)))
15795 (clobber (match_scratch:CC 3 ""))
15796 (clobber (match_scratch:P 4 ""))]
15797 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15798 [(parallel [(set (match_dup 3)
15799 (compare:CC (plus:P (match_dup 1)
15800 (const_int -1))
15801 (const_int 0)))
15802 (set (match_dup 4)
15803 (plus:P (match_dup 1)
15804 (const_int -1)))])
15805 (set (match_dup 0)
15806 (match_dup 4))
15807 (set (pc) (if_then_else (match_dup 7)
15808 (match_dup 5)
15809 (match_dup 6)))]
15810 "
15811 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15812 operands[3], const0_rtx); }")
15813 \f
15814 (define_insn "trap"
15815 [(trap_if (const_int 1) (const_int 0))]
15816 ""
15817 "{t 31,0,0|trap}"
15818 [(set_attr "type" "trap")])
15820 (define_expand "ctrap<mode>4"
15821 [(trap_if (match_operator 0 "ordered_comparison_operator"
15822 [(match_operand:GPR 1 "register_operand")
15823 (match_operand:GPR 2 "reg_or_short_operand")])
15824 (match_operand 3 "zero_constant" ""))]
15825 ""
15826 "")
15828 (define_insn ""
15829 [(trap_if (match_operator 0 "ordered_comparison_operator"
15830 [(match_operand:GPR 1 "register_operand" "r")
15831 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15832 (const_int 0))]
15833 ""
15834 "{t|t<wd>}%V0%I2 %1,%2"
15835 [(set_attr "type" "trap")])
15836 \f
15837 ;; Insns related to generating the function prologue and epilogue.
15839 (define_expand "prologue"
15840 [(use (const_int 0))]
15841 "TARGET_SCHED_PROLOG"
15842 "
15843 {
15844 rs6000_emit_prologue ();
15845 DONE;
15846 }")
15848 (define_insn "*movesi_from_cr_one"
15849 [(match_parallel 0 "mfcr_operation"
15850 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15851 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15852 (match_operand 3 "immediate_operand" "n")]
15853 UNSPEC_MOVESI_FROM_CR))])]
15854 "TARGET_MFCRF"
15855 "*
15856 {
15857 int mask = 0;
15858 int i;
15859 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15860 {
15861 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15862 operands[4] = GEN_INT (mask);
15863 output_asm_insn (\"mfcr %1,%4\", operands);
15864 }
15865 return \"\";
15866 }"
15867 [(set_attr "type" "mfcrf")])
15869 (define_insn "movesi_from_cr"
15870 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15871 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15872 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15873 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15874 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15875 UNSPEC_MOVESI_FROM_CR))]
15876 ""
15877 "mfcr %0"
15878 [(set_attr "type" "mfcr")])
15880 (define_insn "*stmw"
15881 [(match_parallel 0 "stmw_operation"
15882 [(set (match_operand:SI 1 "memory_operand" "=m")
15883 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15884 "TARGET_MULTIPLE"
15885 "{stm|stmw} %2,%1"
15886 [(set_attr "type" "store_ux")])
15888 (define_insn "*save_gpregs_<mode>"
15889 [(match_parallel 0 "any_parallel_operand"
15890 [(clobber (reg:P 65))
15891 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15892 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15893 (set (match_operand:P 3 "memory_operand" "=m")
15894 (match_operand:P 4 "gpc_reg_operand" "r"))])]
15895 ""
15896 "bl %1"
15897 [(set_attr "type" "branch")
15898 (set_attr "length" "4")])
15900 (define_insn "*save_fpregs_<mode>"
15901 [(match_parallel 0 "any_parallel_operand"
15902 [(clobber (reg:P 65))
15903 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15904 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15905 (set (match_operand:DF 3 "memory_operand" "=m")
15906 (match_operand:DF 4 "gpc_reg_operand" "d"))])]
15907 ""
15908 "bl %1"
15909 [(set_attr "type" "branch")
15910 (set_attr "length" "4")])
15912 ; These are to explain that changes to the stack pointer should
15913 ; not be moved over stores to stack memory.
15914 (define_insn "stack_tie"
15915 [(set (match_operand:BLK 0 "memory_operand" "+m")
15916 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
15917 ""
15918 ""
15919 [(set_attr "length" "0")])
15921 ; Like stack_tie, but depend on both fp and sp based memory.
15922 (define_insn "frame_tie"
15923 [(set (match_operand:BLK 0 "memory_operand" "+m")
15924 (unspec:BLK [(match_dup 0)
15925 (match_operand:BLK 1 "memory_operand" "m")] UNSPEC_TIE))]
15926 ""
15927 ""
15928 [(set_attr "length" "0")])
15931 (define_expand "epilogue"
15932 [(use (const_int 0))]
15933 "TARGET_SCHED_PROLOG"
15934 "
15935 {
15936 rs6000_emit_epilogue (FALSE);
15937 DONE;
15938 }")
15940 ; On some processors, doing the mtcrf one CC register at a time is
15941 ; faster (like on the 604e). On others, doing them all at once is
15942 ; faster; for instance, on the 601 and 750.
15944 (define_expand "movsi_to_cr_one"
15945 [(set (match_operand:CC 0 "cc_reg_operand" "")
15946 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15947 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15948 ""
15949 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15951 (define_insn "*movsi_to_cr"
15952 [(match_parallel 0 "mtcrf_operation"
15953 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15954 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15955 (match_operand 3 "immediate_operand" "n")]
15956 UNSPEC_MOVESI_TO_CR))])]
15957 ""
15958 "*
15959 {
15960 int mask = 0;
15961 int i;
15962 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15963 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15964 operands[4] = GEN_INT (mask);
15965 return \"mtcrf %4,%2\";
15966 }"
15967 [(set_attr "type" "mtcr")])
15969 (define_insn "*mtcrfsi"
15970 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15971 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15972 (match_operand 2 "immediate_operand" "n")]
15973 UNSPEC_MOVESI_TO_CR))]
15974 "GET_CODE (operands[0]) == REG
15975 && CR_REGNO_P (REGNO (operands[0]))
15976 && GET_CODE (operands[2]) == CONST_INT
15977 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15978 "mtcrf %R0,%1"
15979 [(set_attr "type" "mtcr")])
15981 ; The load-multiple instructions have similar properties.
15982 ; Note that "load_multiple" is a name known to the machine-independent
15983 ; code that actually corresponds to the PowerPC load-string.
15985 (define_insn "*lmw"
15986 [(match_parallel 0 "lmw_operation"
15987 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15988 (match_operand:SI 2 "memory_operand" "m"))])]
15989 "TARGET_MULTIPLE"
15990 "{lm|lmw} %1,%2"
15991 [(set_attr "type" "load_ux")
15992 (set_attr "cell_micro" "always")])
15994 (define_insn "*return_internal_<mode>"
15995 [(return)
15996 (use (match_operand:P 0 "register_operand" "lc"))]
15997 ""
15998 "b%T0"
15999 [(set_attr "type" "jmpreg")])
16001 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
16002 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
16004 (define_insn "*restore_gpregs_<mode>"
16005 [(match_parallel 0 "any_parallel_operand"
16006 [(clobber (match_operand:P 1 "register_operand" "=l"))
16007 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16008 (use (match_operand:P 3 "gpc_reg_operand" "r"))
16009 (set (match_operand:P 4 "gpc_reg_operand" "=r")
16010 (match_operand:P 5 "memory_operand" "m"))])]
16011 ""
16012 "bl %2"
16013 [(set_attr "type" "branch")
16014 (set_attr "length" "4")])
16016 (define_insn "*return_and_restore_gpregs_<mode>"
16017 [(match_parallel 0 "any_parallel_operand"
16018 [(return)
16019 (clobber (match_operand:P 1 "register_operand" "=l"))
16020 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16021 (use (match_operand:P 3 "gpc_reg_operand" "r"))
16022 (set (match_operand:P 4 "gpc_reg_operand" "=r")
16023 (match_operand:P 5 "memory_operand" "m"))])]
16024 ""
16025 "b %2"
16026 [(set_attr "type" "branch")
16027 (set_attr "length" "4")])
16029 (define_insn "*return_and_restore_fpregs_<mode>"
16030 [(match_parallel 0 "any_parallel_operand"
16031 [(return)
16032 (clobber (match_operand:P 1 "register_operand" "=l"))
16033 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16034 (use (match_operand:P 3 "gpc_reg_operand" "r"))
16035 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
16036 (match_operand:DF 5 "memory_operand" "m"))])]
16037 ""
16038 "b %2"
16039 [(set_attr "type" "branch")
16040 (set_attr "length" "4")])
16042 (define_insn "*return_and_restore_fpregs_aix_<mode>"
16043 [(match_parallel 0 "any_parallel_operand"
16044 [(return)
16045 (use (match_operand:P 1 "register_operand" "l"))
16046 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16047 (use (match_operand:P 3 "gpc_reg_operand" "r"))
16048 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
16049 (match_operand:DF 5 "memory_operand" "m"))])]
16050 ""
16051 "b %2"
16052 [(set_attr "type" "branch")
16053 (set_attr "length" "4")])
16055 ; This is used in compiling the unwind routines.
16056 (define_expand "eh_return"
16057 [(use (match_operand 0 "general_operand" ""))]
16058 ""
16059 "
16060 {
16061 if (TARGET_32BIT)
16062 emit_insn (gen_eh_set_lr_si (operands[0]));
16063 else
16064 emit_insn (gen_eh_set_lr_di (operands[0]));
16065 DONE;
16066 }")
16068 ; We can't expand this before we know where the link register is stored.
16069 (define_insn "eh_set_lr_<mode>"
16070 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
16071 UNSPECV_EH_RR)
16072 (clobber (match_scratch:P 1 "=&b"))]
16073 ""
16074 "#")
16076 (define_split
16077 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
16078 (clobber (match_scratch 1 ""))]
16079 "reload_completed"
16080 [(const_int 0)]
16081 "
16082 {
16083 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
16084 DONE;
16085 }")
16087 (define_insn "prefetch"
16088 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
16089 (match_operand:SI 1 "const_int_operand" "n")
16090 (match_operand:SI 2 "const_int_operand" "n"))]
16091 "TARGET_POWERPC"
16092 "*
16093 {
16094 if (GET_CODE (operands[0]) == REG)
16095 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
16096 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
16097 }"
16098 [(set_attr "type" "load")])
16099 \f
16100 (define_insn "bpermd_<mode>"
16101 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
16102 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
16103 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
16104 "TARGET_POPCNTD"
16105 "bpermd %0,%1,%2"
16106 [(set_attr "type" "integer")])
16108 \f
16109 ;; Builtin fma support. Handle
16110 ;; Note that the conditions for expansion are in the FMA_F iterator.
16112 (define_expand "fma<mode>4"
16113 [(set (match_operand:FMA_F 0 "register_operand" "")
16114 (fma:FMA_F
16115 (match_operand:FMA_F 1 "register_operand" "")
16116 (match_operand:FMA_F 2 "register_operand" "")
16117 (match_operand:FMA_F 3 "register_operand" "")))]
16118 ""
16119 "")
16121 ; Altivec only has fma and nfms.
16122 (define_expand "fms<mode>4"
16123 [(set (match_operand:FMA_F 0 "register_operand" "")
16124 (fma:FMA_F
16125 (match_operand:FMA_F 1 "register_operand" "")
16126 (match_operand:FMA_F 2 "register_operand" "")
16127 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
16128 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16129 "")
16131 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
16132 (define_expand "fnma<mode>4"
16133 [(set (match_operand:FMA_F 0 "register_operand" "")
16134 (neg:FMA_F
16135 (fma:FMA_F
16136 (match_operand:FMA_F 1 "register_operand" "")
16137 (match_operand:FMA_F 2 "register_operand" "")
16138 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
16139 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
16140 "")
16142 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
16143 (define_expand "fnms<mode>4"
16144 [(set (match_operand:FMA_F 0 "register_operand" "")
16145 (neg:FMA_F
16146 (fma:FMA_F
16147 (match_operand:FMA_F 1 "register_operand" "")
16148 (match_operand:FMA_F 2 "register_operand" "")
16149 (match_operand:FMA_F 3 "register_operand" ""))))]
16150 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16151 "")
16153 ; Not an official optab name, but used from builtins.
16154 (define_expand "nfma<mode>4"
16155 [(set (match_operand:FMA_F 0 "register_operand" "")
16156 (neg:FMA_F
16157 (fma:FMA_F
16158 (match_operand:FMA_F 1 "register_operand" "")
16159 (match_operand:FMA_F 2 "register_operand" "")
16160 (match_operand:FMA_F 3 "register_operand" ""))))]
16161 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16162 "")
16164 ; Not an official optab name, but used from builtins.
16165 (define_expand "nfms<mode>4"
16166 [(set (match_operand:FMA_F 0 "register_operand" "")
16167 (neg:FMA_F
16168 (fma:FMA_F
16169 (match_operand:FMA_F 1 "register_operand" "")
16170 (match_operand:FMA_F 2 "register_operand" "")
16171 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
16172 ""
16173 "")
16175 \f
16177 (include "sync.md")
16178 (include "vector.md")
16179 (include "vsx.md")
16180 (include "altivec.md")
16181 (include "spe.md")
16182 (include "dfp.md")
16183 (include "paired.md")