1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 ;; 2009 Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
68 ; GOT/PLT and lt-relative accesses
69 (UNSPEC_LTREL_OFFSET 100)
70 (UNSPEC_LTREL_BASE 101)
71 (UNSPEC_POOL_OFFSET 102)
79 (UNSPEC_RELOAD_BASE 210)
80 (UNSPEC_MAIN_BASE 211)
88 ; TLS relocation specifiers
93 (UNSPEC_GOTNTPOFF 504)
94 (UNSPEC_INDNTPOFF 505)
97 (UNSPEC_TLSLDM_NTPOFF 511)
104 ; Stack Smashing Protector
108 ; Copy sign instructions
109 (UNSPEC_COPYSIGN 800)
111 ; Test Data Class (TDC)
112 (UNSPEC_TDC_INSN 900)
116 ;; UNSPEC_VOLATILE usage
124 (UNSPECV_TPF_PROLOGUE 20)
125 (UNSPECV_TPF_EPILOGUE 21)
129 (UNSPECV_POOL_SECTION 201)
130 (UNSPECV_POOL_ALIGN 202)
131 (UNSPECV_POOL_ENTRY 203)
132 (UNSPECV_MAIN_POOL 300)
145 ; Registers with special meaning
149 ; Sibling call register.
151 ; Literal pool base register.
153 ; Return address register.
155 ; Condition code register.
157 ; Thread local storage pointer register.
161 ; Hardware register names
165 ; General purpose registers
167 ; Floating point registers.
173 ;; PFPO GPR0 argument format
178 ; PFPO operation type
179 (PFPO_CONVERT 0x1000000)
181 (PFPO_OP_TYPE_SF 0x5)
182 (PFPO_OP_TYPE_DF 0x6)
183 (PFPO_OP_TYPE_TF 0x7)
184 (PFPO_OP_TYPE_SD 0x8)
185 (PFPO_OP_TYPE_DD 0x9)
186 (PFPO_OP_TYPE_TD 0xa)
187 ; Bitposition of operand types
188 (PFPO_OP0_TYPE_SHIFT 16)
189 (PFPO_OP1_TYPE_SHIFT 8)
193 ;; Instruction operand type as used in the Principles of Operation.
194 ;; Used to determine defaults for length and other attribute values.
196 (define_attr "op_type"
197 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
200 ;; Instruction type attribute used for scheduling.
202 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
203 cs,vs,store,sem,idiv,
204 imulhi,imulsi,imuldi,
205 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
206 floadtf,floaddf,floadsf,fstoredf,fstoresf,
207 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
208 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
209 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
210 itoftf, itofdf, itofsf, itofdd, itoftd,
211 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
212 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
214 (cond [(eq_attr "op_type" "NN") (const_string "other")
215 (eq_attr "op_type" "SS") (const_string "cs")]
216 (const_string "integer")))
218 ;; Another attribute used for scheduling purposes:
219 ;; agen: Instruction uses the address generation unit
220 ;; reg: Instruction does not use the agen unit
222 (define_attr "atype" "agen,reg"
223 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
225 (const_string "agen")))
227 ;; Properties concerning Z10 execution grouping and value forwarding.
228 ;; z10_super: instruction is superscalar.
229 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
230 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
231 ;; target register. It can forward this value to a second instruction that reads
232 ;; the same register if that second instruction is issued in the same group.
233 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
234 ;; instruction in the S pipe writes to the register, then the T instruction
235 ;; can immediately read the new value.
236 ;; z10_fr: union of Z10_fwd and z10_rec.
237 ;; z10_c: second operand of instruction is a register and read with complemented bits.
239 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
242 (define_attr "z10prop" "none,
243 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
244 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
246 z10_fr, z10_fr_A3, z10_fr_E1,
248 (const_string "none"))
253 (define_attr "length" ""
254 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
255 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
259 ;; Processor type. This attribute must exactly match the processor_type
260 ;; enumeration in s390.h. The current machine description does not
261 ;; distinguish between g5 and g6, but there are differences between the two
262 ;; CPUs could in theory be modeled.
264 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
265 (const (symbol_ref "s390_tune_attr")))
267 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
268 (const_string "standard"))
270 (define_attr "enabled" ""
271 (cond [(eq_attr "cpu_facility" "standard")
274 (and (eq_attr "cpu_facility" "ieee")
275 (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0)))
278 (and (eq_attr "cpu_facility" "zarch")
279 (ne (symbol_ref "TARGET_ZARCH") (const_int 0)))
282 (and (eq_attr "cpu_facility" "longdisp")
283 (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0)))
286 (and (eq_attr "cpu_facility" "extimm")
287 (ne (symbol_ref "TARGET_EXTIMM") (const_int 0)))
290 (and (eq_attr "cpu_facility" "dfp")
291 (ne (symbol_ref "TARGET_DFP") (const_int 0)))
294 (and (eq_attr "cpu_facility" "z10")
295 (ne (symbol_ref "TARGET_Z10") (const_int 0)))
299 ;; Pipeline description for z900. For lack of anything better,
300 ;; this description is also used for the g5 and g6.
303 ;; Pipeline description for z990, z9-109 and z9-ec.
306 ;; Pipeline description for z10
310 (include "predicates.md")
312 ;; Constraint definitions
313 (include "constraints.md")
320 ;; These mode iterators allow floating point patterns to be generated from the
322 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
323 (SD "TARGET_HARD_DFP")])
324 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
325 (define_mode_iterator FPALL [TF DF SF TD DD SD])
326 (define_mode_iterator BFP [TF DF SF])
327 (define_mode_iterator DFP [TD DD])
328 (define_mode_iterator DFP_ALL [TD DD SD])
329 (define_mode_iterator DSF [DF SF])
330 (define_mode_iterator SD_SF [SF SD])
331 (define_mode_iterator DD_DF [DF DD])
332 (define_mode_iterator TD_TF [TF TD])
334 ;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated
335 ;; from the same template.
336 (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI])
338 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
339 ;; from the same template.
340 (define_mode_iterator GPR [(DI "TARGET_64BIT") SI])
341 (define_mode_iterator DSI [DI SI])
343 ;; These mode iterators allow :P to be used for patterns that operate on
344 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
345 (define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
346 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
348 ;; This mode iterator allows the QI and HI patterns to be defined from
349 ;; the same template.
350 (define_mode_iterator HQI [HI QI])
352 ;; This mode iterator allows the integer patterns to be defined from the
354 (define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI])
355 (define_mode_iterator INTALL [TI DI SI HI QI])
357 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
358 ;; the same template.
359 (define_code_iterator SHIFT [ashift lshiftrt])
361 ;; This iterator and attribute allow to combine most atomic operations.
362 (define_code_iterator ATOMIC [and ior xor plus minus mult])
363 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
364 (plus "add") (minus "sub") (mult "nand")])
366 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
367 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
368 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
370 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
371 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
373 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
375 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
376 ;; Likewise for "<RXe>".
377 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
378 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
380 ;; The decimal floating point variants of add, sub, div and mul support 3
381 ;; fp register operands. The following attributes allow to merge the bfp and
382 ;; dfp variants in a single insn definition.
384 ;; This attribute is used to set op_type accordingly.
385 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
386 (DD "RRR") (SD "RRR")])
388 ;; This attribute is used in the operand constraint list in order to have the
389 ;; first and the second operand match for bfp modes.
390 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
392 ;; This attribute is used in the operand list of the instruction to have an
393 ;; additional operand for the dfp instructions.
394 (define_mode_attr op1 [(TF "") (DF "") (SF "")
395 (TD "%1,") (DD "%1,") (SD "%1,")])
398 ;; This attribute is used in the operand constraint list
399 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
400 ;; TFmode values are represented by a fp register pair. Since the
401 ;; sign bit instructions only handle single source and target fp registers
402 ;; these instructions can only be used for TFmode values if the source and
403 ;; target operand uses the same fp register.
404 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
406 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
407 ;; This is used to disable the memory alternative in TFmode patterns.
408 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
410 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
411 ;; within instruction mnemonics.
412 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
414 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
415 ;; modes and to an empty string for bfp modes.
416 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
418 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
419 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
420 ;; version only operates on one register.
421 (define_mode_attr d0 [(DI "d") (SI "0")])
423 ;; In combination with d0 this allows to combine instructions of which the 31bit
424 ;; version only operates on one register. The DImode version needs an additional
425 ;; register for the assembler output.
426 (define_mode_attr 1 [(DI "%1,") (SI "")])
428 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
429 ;; 'ashift' and "srdl" in 'lshiftrt'.
430 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
432 ;; In SHIFT templates, this attribute holds the correct standard name for the
433 ;; pattern itself and the corresponding function calls.
434 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
436 ;; This attribute handles differences in the instruction 'type' and will result
437 ;; in "RRE" for DImode and "RR" for SImode.
438 (define_mode_attr E [(DI "E") (SI "")])
440 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
441 ;; to result in "RXY" for DImode and "RX" for SImode.
442 (define_mode_attr Y [(DI "Y") (SI "")])
444 ;; This attribute handles differences in the instruction 'type' and will result
445 ;; in "RSE" for TImode and "RS" for DImode.
446 (define_mode_attr TE [(TI "E") (DI "")])
448 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
449 ;; and "lcr" in SImode.
450 (define_mode_attr g [(DI "g") (SI "")])
452 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
453 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
454 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
455 ;; variant for long displacements.
456 (define_mode_attr y [(DI "g") (SI "y")])
458 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
459 ;; and "cds" in DImode.
460 (define_mode_attr tg [(TI "g") (DI "")])
462 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
463 ;; and "cfdbr" in SImode.
464 (define_mode_attr gf [(DI "g") (SI "f")])
466 ;; ICM mask required to load MODE value into the lowest subreg
467 ;; of a SImode register.
468 (define_mode_attr icm_lo [(HI "3") (QI "1")])
470 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
471 ;; HImode and "llgc" in QImode.
472 (define_mode_attr hc [(HI "h") (QI "c")])
474 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
476 (define_mode_attr DBL [(DI "TI") (SI "DI")])
478 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
479 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
480 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
482 ;; Maximum unsigned integer that fits in MODE.
483 (define_mode_attr max_uint [(HI "65535") (QI "255")])
486 ;;- Compare instructions.
489 ; Test-under-Mask instructions
491 (define_insn "*tmqi_mem"
492 [(set (reg CC_REGNUM)
493 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
494 (match_operand:QI 1 "immediate_operand" "n,n"))
495 (match_operand:QI 2 "immediate_operand" "n,n")))]
496 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
500 [(set_attr "op_type" "SI,SIY")
501 (set_attr "z10prop" "z10_super,z10_super")])
503 (define_insn "*tmdi_reg"
504 [(set (reg CC_REGNUM)
505 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
506 (match_operand:DI 1 "immediate_operand"
507 "N0HD0,N1HD0,N2HD0,N3HD0"))
508 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
510 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
511 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
517 [(set_attr "op_type" "RI")
518 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
520 (define_insn "*tmsi_reg"
521 [(set (reg CC_REGNUM)
522 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
523 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
524 (match_operand:SI 2 "immediate_operand" "n,n")))]
525 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
526 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
530 [(set_attr "op_type" "RI")
531 (set_attr "z10prop" "z10_super,z10_super")])
533 (define_insn "*tm<mode>_full"
534 [(set (reg CC_REGNUM)
535 (compare (match_operand:HQI 0 "register_operand" "d")
536 (match_operand:HQI 1 "immediate_operand" "n")))]
537 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
539 [(set_attr "op_type" "RI")
540 (set_attr "z10prop" "z10_super")])
544 ; Load-and-Test instructions
547 ; tst(di|si) instruction pattern(s).
549 (define_insn "*tstdi_sign"
550 [(set (reg CC_REGNUM)
554 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
555 (const_int 32)) (const_int 32))
556 (match_operand:DI 1 "const0_operand" "")))
557 (set (match_operand:DI 2 "register_operand" "=d,d")
558 (sign_extend:DI (match_dup 0)))]
559 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
562 [(set_attr "op_type" "RRE,RXY")
563 (set_attr "cpu_facility" "*,z10")
564 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
567 (define_insn "*tst<mode>_extimm"
568 [(set (reg CC_REGNUM)
569 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
570 (match_operand:GPR 1 "const0_operand" "")))
571 (set (match_operand:GPR 2 "register_operand" "=d,d")
573 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
577 [(set_attr "op_type" "RR<E>,RXY")
578 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
581 (define_insn "*tst<mode>_cconly_extimm"
582 [(set (reg CC_REGNUM)
583 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
584 (match_operand:GPR 1 "const0_operand" "")))
585 (clobber (match_scratch:GPR 2 "=X,d"))]
586 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
590 [(set_attr "op_type" "RR<E>,RXY")
591 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
593 (define_insn "*tstdi"
594 [(set (reg CC_REGNUM)
595 (compare (match_operand:DI 0 "register_operand" "d")
596 (match_operand:DI 1 "const0_operand" "")))
597 (set (match_operand:DI 2 "register_operand" "=d")
599 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
601 [(set_attr "op_type" "RRE")
602 (set_attr "z10prop" "z10_fr_E1")])
604 (define_insn "*tstsi"
605 [(set (reg CC_REGNUM)
606 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
607 (match_operand:SI 1 "const0_operand" "")))
608 (set (match_operand:SI 2 "register_operand" "=d,d,d")
610 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
615 [(set_attr "op_type" "RR,RS,RSY")
616 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
618 (define_insn "*tstsi_cconly"
619 [(set (reg CC_REGNUM)
620 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
621 (match_operand:SI 1 "const0_operand" "")))
622 (clobber (match_scratch:SI 2 "=X,d,d"))]
623 "s390_match_ccmode(insn, CCSmode)"
628 [(set_attr "op_type" "RR,RS,RSY")
629 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
631 (define_insn "*tstdi_cconly_31"
632 [(set (reg CC_REGNUM)
633 (compare (match_operand:DI 0 "register_operand" "d")
634 (match_operand:DI 1 "const0_operand" "")))]
635 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
637 [(set_attr "op_type" "RS")
638 (set_attr "atype" "reg")])
641 (define_insn "*tst<mode>_cconly2"
642 [(set (reg CC_REGNUM)
643 (compare (match_operand:GPR 0 "register_operand" "d")
644 (match_operand:GPR 1 "const0_operand" "")))]
645 "s390_match_ccmode(insn, CCSmode)"
647 [(set_attr "op_type" "RR<E>")
648 (set_attr "z10prop" "z10_fr_E1")])
650 ; tst(hi|qi) instruction pattern(s).
652 (define_insn "*tst<mode>CCT"
653 [(set (reg CC_REGNUM)
654 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
655 (match_operand:HQI 1 "const0_operand" "")))
656 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
658 "s390_match_ccmode(insn, CCTmode)"
661 icmy\t%2,<icm_lo>,%S0
663 [(set_attr "op_type" "RS,RSY,RI")
664 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
666 (define_insn "*tsthiCCT_cconly"
667 [(set (reg CC_REGNUM)
668 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
669 (match_operand:HI 1 "const0_operand" "")))
670 (clobber (match_scratch:HI 2 "=d,d,X"))]
671 "s390_match_ccmode(insn, CCTmode)"
676 [(set_attr "op_type" "RS,RSY,RI")
677 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
679 (define_insn "*tstqiCCT_cconly"
680 [(set (reg CC_REGNUM)
681 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
682 (match_operand:QI 1 "const0_operand" "")))]
683 "s390_match_ccmode(insn, CCTmode)"
688 [(set_attr "op_type" "SI,SIY,RI")
689 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
691 (define_insn "*tst<mode>"
692 [(set (reg CC_REGNUM)
693 (compare (match_operand:HQI 0 "s_operand" "Q,S")
694 (match_operand:HQI 1 "const0_operand" "")))
695 (set (match_operand:HQI 2 "register_operand" "=d,d")
697 "s390_match_ccmode(insn, CCSmode)"
700 icmy\t%2,<icm_lo>,%S0"
701 [(set_attr "op_type" "RS,RSY")
702 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
704 (define_insn "*tst<mode>_cconly"
705 [(set (reg CC_REGNUM)
706 (compare (match_operand:HQI 0 "s_operand" "Q,S")
707 (match_operand:HQI 1 "const0_operand" "")))
708 (clobber (match_scratch:HQI 2 "=d,d"))]
709 "s390_match_ccmode(insn, CCSmode)"
712 icmy\t%2,<icm_lo>,%S0"
713 [(set_attr "op_type" "RS,RSY")
714 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
717 ; Compare (equality) instructions
719 (define_insn "*cmpdi_cct"
720 [(set (reg CC_REGNUM)
721 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
722 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
723 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
730 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
731 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
733 (define_insn "*cmpsi_cct"
734 [(set (reg CC_REGNUM)
735 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
736 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
737 "s390_match_ccmode (insn, CCTmode)"
745 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
746 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
748 ; Compare (signed) instructions
750 (define_insn "*cmpdi_ccs_sign"
751 [(set (reg CC_REGNUM)
752 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
754 (match_operand:DI 0 "register_operand" "d, d,d")))]
755 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
760 [(set_attr "op_type" "RRE,RXY,RIL")
761 (set_attr "z10prop" "z10_c,*,*")
762 (set_attr "type" "*,*,larl")])
766 (define_insn "*cmpsi_ccs_sign"
767 [(set (reg CC_REGNUM)
768 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
769 (match_operand:SI 0 "register_operand" "d,d,d")))]
770 "s390_match_ccmode(insn, CCSRmode)"
775 [(set_attr "op_type" "RX,RXY,RIL")
776 (set_attr "cpu_facility" "*,*,z10")
777 (set_attr "type" "*,*,larl")])
779 (define_insn "*cmphi_ccs_z10"
780 [(set (reg CC_REGNUM)
781 (compare (match_operand:HI 0 "s_operand" "Q")
782 (match_operand:HI 1 "immediate_operand" "K")))]
783 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
785 [(set_attr "op_type" "SIL")])
787 (define_insn "*cmpdi_ccs_signhi_rl"
788 [(set (reg CC_REGNUM)
789 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
790 (match_operand:GPR 0 "register_operand" "d,d")))]
791 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
795 [(set_attr "op_type" "RXY,RIL")
796 (set_attr "type" "*,larl")])
798 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
799 (define_insn "*cmp<mode>_ccs"
800 [(set (reg CC_REGNUM)
801 (compare (match_operand:GPR 0 "nonimmediate_operand"
803 (match_operand:GPR 1 "general_operand"
805 "s390_match_ccmode(insn, CCSmode)"
814 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
815 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
816 (set_attr "type" "*,*,*,*,*,*,larl")
817 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
820 ; Compare (unsigned) instructions
822 (define_insn "*cmpsi_ccu_zerohi_rlsi"
823 [(set (reg CC_REGNUM)
824 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
825 "larl_operand" "X")))
826 (match_operand:SI 0 "register_operand" "d")))]
827 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
829 [(set_attr "op_type" "RIL")
830 (set_attr "type" "larl")
831 (set_attr "z10prop" "z10_super")])
834 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
835 [(set (reg CC_REGNUM)
836 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
837 "larl_operand" "X")))
838 (match_operand:GPR 0 "register_operand" "d")))]
839 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
841 [(set_attr "op_type" "RIL")
842 (set_attr "type" "larl")
843 (set_attr "z10prop" "z10_super")])
845 (define_insn "*cmpdi_ccu_zero"
846 [(set (reg CC_REGNUM)
847 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
849 (match_operand:DI 0 "register_operand" "d, d,d")))]
850 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
855 [(set_attr "op_type" "RRE,RXY,RIL")
856 (set_attr "cpu_facility" "*,*,z10")
857 (set_attr "type" "*,*,larl")
858 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
860 (define_insn "*cmpdi_ccu"
861 [(set (reg CC_REGNUM)
862 (compare (match_operand:DI 0 "nonimmediate_operand"
864 (match_operand:DI 1 "general_operand"
865 "d,Op,b,D,RT,BQ,Q")))]
866 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
875 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
876 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
877 (set_attr "type" "*,*,larl,*,*,*,*")
878 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
880 (define_insn "*cmpsi_ccu"
881 [(set (reg CC_REGNUM)
882 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
883 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
884 "s390_match_ccmode (insn, CCUmode)"
894 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
895 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
896 (set_attr "type" "*,*,larl,*,*,*,*,*")
897 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
899 (define_insn "*cmphi_ccu"
900 [(set (reg CC_REGNUM)
901 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
902 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
903 "s390_match_ccmode (insn, CCUmode)
904 && !register_operand (operands[1], HImode)"
911 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
912 (set_attr "cpu_facility" "*,*,z10,*,*")
913 (set_attr "z10prop" "*,*,z10_super,*,*")])
915 (define_insn "*cmpqi_ccu"
916 [(set (reg CC_REGNUM)
917 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
918 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
919 "s390_match_ccmode (insn, CCUmode)
920 && !register_operand (operands[1], QImode)"
928 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
929 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
932 ; Block compare (CLC) instruction patterns.
935 [(set (reg CC_REGNUM)
936 (compare (match_operand:BLK 0 "memory_operand" "Q")
937 (match_operand:BLK 1 "memory_operand" "Q")))
938 (use (match_operand 2 "const_int_operand" "n"))]
939 "s390_match_ccmode (insn, CCUmode)
940 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
941 "clc\t%O0(%2,%R0),%S1"
942 [(set_attr "op_type" "SS")])
945 [(set (reg CC_REGNUM)
946 (compare (match_operand 0 "memory_operand" "")
947 (match_operand 1 "memory_operand" "")))]
949 && s390_match_ccmode (insn, CCUmode)
950 && GET_MODE (operands[0]) == GET_MODE (operands[1])
951 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
953 [(set (match_dup 0) (match_dup 1))
954 (use (match_dup 2))])]
956 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
957 operands[0] = adjust_address (operands[0], BLKmode, 0);
958 operands[1] = adjust_address (operands[1], BLKmode, 0);
960 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
961 operands[0], operands[1]);
962 operands[0] = SET_DEST (PATTERN (curr_insn));
966 ; (TF|DF|SF|TD|DD|SD) instructions
968 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
969 (define_insn "*cmp<mode>_ccs_0"
970 [(set (reg CC_REGNUM)
971 (compare (match_operand:FP 0 "register_operand" "f")
972 (match_operand:FP 1 "const0_operand" "")))]
973 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
974 "lt<xde><bt>r\t%0,%0"
975 [(set_attr "op_type" "RRE")
976 (set_attr "type" "fsimp<mode>")])
978 ; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr
979 (define_insn "*cmp<mode>_ccs"
980 [(set (reg CC_REGNUM)
981 (compare (match_operand:FP 0 "register_operand" "f,f")
982 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
983 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
987 [(set_attr "op_type" "RRE,RXE")
988 (set_attr "type" "fsimp<mode>")])
991 ; Compare and Branch instructions
993 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
994 ; The following instructions do a complementary access of their second
995 ; operand (z01 only): crj_c, cgrjc, cr, cgr
996 (define_insn "*cmp_and_br_signed_<mode>"
998 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
999 [(match_operand:GPR 1 "register_operand" "d,d")
1000 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1001 (label_ref (match_operand 3 "" ""))
1003 (clobber (reg:CC CC_REGNUM))]
1006 if (get_attr_length (insn) == 6)
1007 return which_alternative ?
1008 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1010 return which_alternative ?
1011 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1013 [(set_attr "op_type" "RIE")
1014 (set_attr "type" "branch")
1015 (set_attr "z10prop" "z10_super_c,z10_super")
1016 (set (attr "length")
1017 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1018 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1019 ; 10 byte for cgr/jg
1021 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1022 ; The following instructions do a complementary access of their second
1023 ; operand (z10 only): clrj, clgrj, clr, clgr
1024 (define_insn "*cmp_and_br_unsigned_<mode>"
1026 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1027 [(match_operand:GPR 1 "register_operand" "d,d")
1028 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1029 (label_ref (match_operand 3 "" ""))
1031 (clobber (reg:CC CC_REGNUM))]
1034 if (get_attr_length (insn) == 6)
1035 return which_alternative ?
1036 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1038 return which_alternative ?
1039 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1041 [(set_attr "op_type" "RIE")
1042 (set_attr "type" "branch")
1043 (set_attr "z10prop" "z10_super_c,z10_super")
1044 (set (attr "length")
1045 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1046 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1047 ; 10 byte for clgr/jg
1049 ; And now the same two patterns as above but with a negated CC mask.
1051 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1052 ; The following instructions do a complementary access of their second
1053 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1054 (define_insn "*icmp_and_br_signed_<mode>"
1056 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1057 [(match_operand:GPR 1 "register_operand" "d,d")
1058 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1060 (label_ref (match_operand 3 "" ""))))
1061 (clobber (reg:CC CC_REGNUM))]
1064 if (get_attr_length (insn) == 6)
1065 return which_alternative ?
1066 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1068 return which_alternative ?
1069 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1071 [(set_attr "op_type" "RIE")
1072 (set_attr "type" "branch")
1073 (set_attr "z10prop" "z10_super_c,z10_super")
1074 (set (attr "length")
1075 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1076 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1077 ; 10 byte for cgr/jg
1079 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1080 ; The following instructions do a complementary access of their second
1081 ; operand (z10 only): clrj, clgrj, clr, clgr
1082 (define_insn "*icmp_and_br_unsigned_<mode>"
1084 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1085 [(match_operand:GPR 1 "register_operand" "d,d")
1086 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1088 (label_ref (match_operand 3 "" ""))))
1089 (clobber (reg:CC CC_REGNUM))]
1092 if (get_attr_length (insn) == 6)
1093 return which_alternative ?
1094 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1096 return which_alternative ?
1097 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1099 [(set_attr "op_type" "RIE")
1100 (set_attr "type" "branch")
1101 (set_attr "z10prop" "z10_super_c,z10_super")
1102 (set (attr "length")
1103 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1104 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1105 ; 10 byte for clgr/jg
1108 ;;- Move instructions.
1112 ; movti instruction pattern(s).
1115 (define_insn "movti"
1116 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1117 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1124 [(set_attr "op_type" "RSY,RSY,*,*")
1125 (set_attr "type" "lm,stm,*,*")])
1128 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1129 (match_operand:TI 1 "general_operand" ""))]
1130 "TARGET_64BIT && reload_completed
1131 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1132 [(set (match_dup 2) (match_dup 4))
1133 (set (match_dup 3) (match_dup 5))]
1135 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1136 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1137 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1138 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1142 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1143 (match_operand:TI 1 "general_operand" ""))]
1144 "TARGET_64BIT && reload_completed
1145 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1146 [(set (match_dup 2) (match_dup 4))
1147 (set (match_dup 3) (match_dup 5))]
1149 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1150 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1151 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1152 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1156 [(set (match_operand:TI 0 "register_operand" "")
1157 (match_operand:TI 1 "memory_operand" ""))]
1158 "TARGET_64BIT && reload_completed
1159 && !s_operand (operands[1], VOIDmode)"
1160 [(set (match_dup 0) (match_dup 1))]
1162 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1163 s390_load_address (addr, XEXP (operands[1], 0));
1164 operands[1] = replace_equiv_address (operands[1], addr);
1169 ; Patterns used for secondary reloads
1172 ; z10 provides move instructions accepting larl memory operands.
1173 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1174 ; These patterns are also used for unaligned SI and DI accesses.
1176 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1177 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1178 (match_operand:INTALL 1 "register_operand" "=d")
1179 (match_operand:P 2 "register_operand" "=&a")])]
1182 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1186 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1187 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1188 (match_operand:INTALL 1 "memory_operand" "")
1189 (match_operand:P 2 "register_operand" "=a")])]
1192 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1196 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1197 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1198 (match_operand:FPALL 1 "register_operand" "=d")
1199 (match_operand:P 2 "register_operand" "=&a")])]
1202 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1206 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1207 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1208 (match_operand:FPALL 1 "memory_operand" "")
1209 (match_operand:P 2 "register_operand" "=a")])]
1212 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1216 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1217 [(parallel [(match_operand:P 0 "register_operand" "=d")
1218 (match_operand:P 1 "larl_operand" "")
1219 (match_operand:P 2 "register_operand" "=a")])]
1222 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1226 ; Handles loading a PLUS (load address) expression
1228 (define_expand "reload<mode>_plus"
1229 [(parallel [(match_operand:P 0 "register_operand" "=a")
1230 (match_operand:P 1 "s390_plus_operand" "")
1231 (match_operand:P 2 "register_operand" "=&a")])]
1234 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1238 ; Handles assessing a non-offsetable memory address
1240 (define_expand "reload<mode>_nonoffmem_in"
1241 [(parallel [(match_operand 0 "register_operand" "")
1242 (match_operand 1 "" "")
1243 (match_operand:P 2 "register_operand" "=&a")])]
1246 gcc_assert (MEM_P (operands[1]));
1247 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1248 operands[1] = replace_equiv_address (operands[1], operands[2]);
1249 emit_move_insn (operands[0], operands[1]);
1253 (define_expand "reload<mode>_nonoffmem_out"
1254 [(parallel [(match_operand 0 "" "")
1255 (match_operand 1 "register_operand" "")
1256 (match_operand:P 2 "register_operand" "=&a")])]
1259 gcc_assert (MEM_P (operands[0]));
1260 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1261 operands[0] = replace_equiv_address (operands[0], operands[2]);
1262 emit_move_insn (operands[0], operands[1]);
1266 (define_expand "reload<mode>_PIC_addr"
1267 [(parallel [(match_operand 0 "register_operand" "=d")
1268 (match_operand 1 "larl_operand" "")
1269 (match_operand:P 2 "register_operand" "=a")])]
1272 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1273 emit_move_insn (operands[0], new_rtx);
1277 ; movdi instruction pattern(s).
1280 (define_expand "movdi"
1281 [(set (match_operand:DI 0 "general_operand" "")
1282 (match_operand:DI 1 "general_operand" ""))]
1285 /* Handle symbolic constants. */
1287 && (SYMBOLIC_CONST (operands[1])
1288 || (GET_CODE (operands[1]) == PLUS
1289 && XEXP (operands[1], 0) == pic_offset_table_rtx
1290 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1291 emit_symbolic_move (operands);
1294 (define_insn "*movdi_larl"
1295 [(set (match_operand:DI 0 "register_operand" "=d")
1296 (match_operand:DI 1 "larl_operand" "X"))]
1298 && !FP_REG_P (operands[0])"
1300 [(set_attr "op_type" "RIL")
1301 (set_attr "type" "larl")
1302 (set_attr "z10prop" "z10_super_A1")])
1304 (define_insn "*movdi_64"
1305 [(set (match_operand:DI 0 "nonimmediate_operand"
1306 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1307 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1308 (match_operand:DI 1 "general_operand"
1309 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1310 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1339 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1340 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1341 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1342 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1344 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1345 z10,*,*,*,*,*,longdisp,*,longdisp,
1347 (set_attr "z10prop" "z10_fwd_A1,
1376 [(set (match_operand:DI 0 "register_operand" "")
1377 (match_operand:DI 1 "register_operand" ""))]
1378 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
1379 [(set (match_dup 2) (match_dup 3))
1380 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1381 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1382 "operands[2] = gen_lowpart (SImode, operands[0]);
1383 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1386 [(set (match_operand:DI 0 "register_operand" "")
1387 (match_operand:DI 1 "register_operand" ""))]
1388 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1389 && dead_or_set_p (insn, operands[1])"
1390 [(set (match_dup 3) (match_dup 2))
1391 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1392 (set (match_dup 4) (match_dup 2))]
1393 "operands[2] = gen_lowpart (SImode, operands[1]);
1394 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1397 [(set (match_operand:DI 0 "register_operand" "")
1398 (match_operand:DI 1 "register_operand" ""))]
1399 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1400 && !dead_or_set_p (insn, operands[1])"
1401 [(set (match_dup 3) (match_dup 2))
1402 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1403 (set (match_dup 4) (match_dup 2))
1404 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1405 "operands[2] = gen_lowpart (SImode, operands[1]);
1406 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1408 (define_insn "*movdi_31"
1409 [(set (match_operand:DI 0 "nonimmediate_operand"
1410 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1411 (match_operand:DI 1 "general_operand"
1412 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1427 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1428 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1429 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1431 ; For a load from a symbol ref we can use one of the target registers
1432 ; together with larl to load the address.
1434 [(set (match_operand:DI 0 "register_operand" "")
1435 (match_operand:DI 1 "memory_operand" ""))]
1436 "!TARGET_64BIT && reload_completed && TARGET_Z10
1437 && larl_operand (XEXP (operands[1], 0), SImode)"
1438 [(set (match_dup 2) (match_dup 3))
1439 (set (match_dup 0) (match_dup 1))]
1441 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1442 operands[3] = XEXP (operands[1], 0);
1443 operands[1] = replace_equiv_address (operands[1], operands[2]);
1447 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1448 (match_operand:DI 1 "general_operand" ""))]
1449 "!TARGET_64BIT && reload_completed
1450 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1451 [(set (match_dup 2) (match_dup 4))
1452 (set (match_dup 3) (match_dup 5))]
1454 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1455 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1456 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1457 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1461 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1462 (match_operand:DI 1 "general_operand" ""))]
1463 "!TARGET_64BIT && reload_completed
1464 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1465 [(set (match_dup 2) (match_dup 4))
1466 (set (match_dup 3) (match_dup 5))]
1468 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1469 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1470 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1471 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1475 [(set (match_operand:DI 0 "register_operand" "")
1476 (match_operand:DI 1 "memory_operand" ""))]
1477 "!TARGET_64BIT && reload_completed
1478 && !FP_REG_P (operands[0])
1479 && !s_operand (operands[1], VOIDmode)"
1480 [(set (match_dup 0) (match_dup 1))]
1482 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1483 s390_load_address (addr, XEXP (operands[1], 0));
1484 operands[1] = replace_equiv_address (operands[1], addr);
1488 [(set (match_operand:DI 0 "register_operand" "")
1489 (mem:DI (match_operand 1 "address_operand" "")))]
1491 && !FP_REG_P (operands[0])
1492 && GET_CODE (operands[1]) == SYMBOL_REF
1493 && CONSTANT_POOL_ADDRESS_P (operands[1])
1494 && get_pool_mode (operands[1]) == DImode
1495 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1496 [(set (match_dup 0) (match_dup 2))]
1497 "operands[2] = get_pool_constant (operands[1]);")
1499 (define_insn "*la_64"
1500 [(set (match_operand:DI 0 "register_operand" "=d,d")
1501 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1506 [(set_attr "op_type" "RX,RXY")
1507 (set_attr "type" "la")
1508 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1512 [(set (match_operand:DI 0 "register_operand" "")
1513 (match_operand:QI 1 "address_operand" ""))
1514 (clobber (reg:CC CC_REGNUM))])]
1516 && preferred_la_operand_p (operands[1], const0_rtx)"
1517 [(set (match_dup 0) (match_dup 1))]
1521 [(set (match_operand:DI 0 "register_operand" "")
1522 (match_operand:DI 1 "register_operand" ""))
1525 (plus:DI (match_dup 0)
1526 (match_operand:DI 2 "nonmemory_operand" "")))
1527 (clobber (reg:CC CC_REGNUM))])]
1529 && !reg_overlap_mentioned_p (operands[0], operands[2])
1530 && preferred_la_operand_p (operands[1], operands[2])"
1531 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1535 ; movsi instruction pattern(s).
1538 (define_expand "movsi"
1539 [(set (match_operand:SI 0 "general_operand" "")
1540 (match_operand:SI 1 "general_operand" ""))]
1543 /* Handle symbolic constants. */
1545 && (SYMBOLIC_CONST (operands[1])
1546 || (GET_CODE (operands[1]) == PLUS
1547 && XEXP (operands[1], 0) == pic_offset_table_rtx
1548 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1549 emit_symbolic_move (operands);
1552 (define_insn "*movsi_larl"
1553 [(set (match_operand:SI 0 "register_operand" "=d")
1554 (match_operand:SI 1 "larl_operand" "X"))]
1555 "!TARGET_64BIT && TARGET_CPU_ZARCH
1556 && !FP_REG_P (operands[0])"
1558 [(set_attr "op_type" "RIL")
1559 (set_attr "type" "larl")
1560 (set_attr "z10prop" "z10_fwd_A1")])
1562 (define_insn "*movsi_zarch"
1563 [(set (match_operand:SI 0 "nonimmediate_operand"
1564 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1565 (match_operand:SI 1 "general_operand"
1566 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1591 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1592 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1593 (set_attr "type" "*,
1615 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1616 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1617 (set_attr "z10prop" "z10_fwd_A1,
1640 (define_insn "*movsi_esa"
1641 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1642 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1656 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1657 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1658 (set_attr "z10prop" "z10_fwd_A1,
1672 [(set (match_operand:SI 0 "register_operand" "")
1673 (mem:SI (match_operand 1 "address_operand" "")))]
1674 "!FP_REG_P (operands[0])
1675 && GET_CODE (operands[1]) == SYMBOL_REF
1676 && CONSTANT_POOL_ADDRESS_P (operands[1])
1677 && get_pool_mode (operands[1]) == SImode
1678 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1679 [(set (match_dup 0) (match_dup 2))]
1680 "operands[2] = get_pool_constant (operands[1]);")
1682 (define_insn "*la_31"
1683 [(set (match_operand:SI 0 "register_operand" "=d,d")
1684 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1685 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1689 [(set_attr "op_type" "RX,RXY")
1690 (set_attr "type" "la")
1691 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1695 [(set (match_operand:SI 0 "register_operand" "")
1696 (match_operand:QI 1 "address_operand" ""))
1697 (clobber (reg:CC CC_REGNUM))])]
1699 && preferred_la_operand_p (operands[1], const0_rtx)"
1700 [(set (match_dup 0) (match_dup 1))]
1704 [(set (match_operand:SI 0 "register_operand" "")
1705 (match_operand:SI 1 "register_operand" ""))
1708 (plus:SI (match_dup 0)
1709 (match_operand:SI 2 "nonmemory_operand" "")))
1710 (clobber (reg:CC CC_REGNUM))])]
1712 && !reg_overlap_mentioned_p (operands[0], operands[2])
1713 && preferred_la_operand_p (operands[1], operands[2])"
1714 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1717 (define_insn "*la_31_and"
1718 [(set (match_operand:SI 0 "register_operand" "=d,d")
1719 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1720 (const_int 2147483647)))]
1725 [(set_attr "op_type" "RX,RXY")
1726 (set_attr "type" "la")
1727 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1729 (define_insn_and_split "*la_31_and_cc"
1730 [(set (match_operand:SI 0 "register_operand" "=d")
1731 (and:SI (match_operand:QI 1 "address_operand" "p")
1732 (const_int 2147483647)))
1733 (clobber (reg:CC CC_REGNUM))]
1736 "&& reload_completed"
1738 (and:SI (match_dup 1) (const_int 2147483647)))]
1740 [(set_attr "op_type" "RX")
1741 (set_attr "type" "la")])
1743 (define_insn "force_la_31"
1744 [(set (match_operand:SI 0 "register_operand" "=d,d")
1745 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1746 (use (const_int 0))]
1751 [(set_attr "op_type" "RX")
1752 (set_attr "type" "la")
1753 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1756 ; movhi instruction pattern(s).
1759 (define_expand "movhi"
1760 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1761 (match_operand:HI 1 "general_operand" ""))]
1764 /* Make it explicit that loading a register from memory
1765 always sign-extends (at least) to SImode. */
1766 if (optimize && can_create_pseudo_p ()
1767 && register_operand (operands[0], VOIDmode)
1768 && GET_CODE (operands[1]) == MEM)
1770 rtx tmp = gen_reg_rtx (SImode);
1771 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1772 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1773 operands[1] = gen_lowpart (HImode, tmp);
1777 (define_insn "*movhi"
1778 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1779 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1791 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1792 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1793 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1794 (set_attr "z10prop" "z10_fr_E1,
1805 [(set (match_operand:HI 0 "register_operand" "")
1806 (mem:HI (match_operand 1 "address_operand" "")))]
1807 "GET_CODE (operands[1]) == SYMBOL_REF
1808 && CONSTANT_POOL_ADDRESS_P (operands[1])
1809 && get_pool_mode (operands[1]) == HImode
1810 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1811 [(set (match_dup 0) (match_dup 2))]
1812 "operands[2] = get_pool_constant (operands[1]);")
1815 ; movqi instruction pattern(s).
1818 (define_expand "movqi"
1819 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1820 (match_operand:QI 1 "general_operand" ""))]
1823 /* On z/Architecture, zero-extending from memory to register
1824 is just as fast as a QImode load. */
1825 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1826 && register_operand (operands[0], VOIDmode)
1827 && GET_CODE (operands[1]) == MEM)
1829 rtx tmp = gen_reg_rtx (word_mode);
1830 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1831 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1832 operands[1] = gen_lowpart (QImode, tmp);
1836 (define_insn "*movqi"
1837 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S")
1838 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))]
1849 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY")
1850 (set_attr "type" "lr,*,*,*,store,store,store,store")
1851 (set_attr "z10prop" "z10_fr_E1,
1861 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1862 (mem:QI (match_operand 1 "address_operand" "")))]
1863 "GET_CODE (operands[1]) == SYMBOL_REF
1864 && CONSTANT_POOL_ADDRESS_P (operands[1])
1865 && get_pool_mode (operands[1]) == QImode
1866 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1867 [(set (match_dup 0) (match_dup 2))]
1868 "operands[2] = get_pool_constant (operands[1]);")
1871 ; movstrictqi instruction pattern(s).
1874 (define_insn "*movstrictqi"
1875 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1876 (match_operand:QI 1 "memory_operand" "R,T"))]
1881 [(set_attr "op_type" "RX,RXY")
1882 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1885 ; movstricthi instruction pattern(s).
1888 (define_insn "*movstricthi"
1889 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1890 (match_operand:HI 1 "memory_operand" "Q,S"))
1891 (clobber (reg:CC CC_REGNUM))]
1896 [(set_attr "op_type" "RS,RSY")
1897 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1900 ; movstrictsi instruction pattern(s).
1903 (define_insn "movstrictsi"
1904 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1905 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1912 [(set_attr "op_type" "RR,RX,RXY,RRE")
1913 (set_attr "type" "lr,load,load,*")
1914 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1917 ; mov(tf|td) instruction pattern(s).
1920 (define_expand "mov<mode>"
1921 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1922 (match_operand:TD_TF 1 "general_operand" ""))]
1926 (define_insn "*mov<mode>_64"
1927 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1928 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1939 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
1940 (set_attr "type" "fhex,fsimptf,*,*,lm,stm,*,*")])
1942 (define_insn "*mov<mode>_31"
1943 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
1944 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
1951 [(set_attr "op_type" "RRE,RRE,*,*")
1952 (set_attr "type" "fhex,fsimptf,*,*")])
1954 ; TFmode in GPRs splitters
1957 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1958 (match_operand:TD_TF 1 "general_operand" ""))]
1959 "TARGET_64BIT && reload_completed
1960 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
1961 [(set (match_dup 2) (match_dup 4))
1962 (set (match_dup 3) (match_dup 5))]
1964 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
1965 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
1966 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
1967 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
1971 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1972 (match_operand:TD_TF 1 "general_operand" ""))]
1973 "TARGET_64BIT && reload_completed
1974 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
1975 [(set (match_dup 2) (match_dup 4))
1976 (set (match_dup 3) (match_dup 5))]
1978 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
1979 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
1980 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
1981 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
1985 [(set (match_operand:TD_TF 0 "register_operand" "")
1986 (match_operand:TD_TF 1 "memory_operand" ""))]
1987 "TARGET_64BIT && reload_completed
1988 && !FP_REG_P (operands[0])
1989 && !s_operand (operands[1], VOIDmode)"
1990 [(set (match_dup 0) (match_dup 1))]
1992 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
1993 s390_load_address (addr, XEXP (operands[1], 0));
1994 operands[1] = replace_equiv_address (operands[1], addr);
1997 ; TFmode in BFPs splitters
2000 [(set (match_operand:TD_TF 0 "register_operand" "")
2001 (match_operand:TD_TF 1 "memory_operand" ""))]
2002 "reload_completed && offsettable_memref_p (operands[1])
2003 && FP_REG_P (operands[0])"
2004 [(set (match_dup 2) (match_dup 4))
2005 (set (match_dup 3) (match_dup 5))]
2007 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2009 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2011 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2012 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2016 [(set (match_operand:TD_TF 0 "memory_operand" "")
2017 (match_operand:TD_TF 1 "register_operand" ""))]
2018 "reload_completed && offsettable_memref_p (operands[0])
2019 && FP_REG_P (operands[1])"
2020 [(set (match_dup 2) (match_dup 4))
2021 (set (match_dup 3) (match_dup 5))]
2023 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2024 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2025 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2027 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2032 ; mov(df|dd) instruction pattern(s).
2035 (define_expand "mov<mode>"
2036 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2037 (match_operand:DD_DF 1 "general_operand" ""))]
2041 (define_insn "*mov<mode>_64dfp"
2042 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2043 "=f,f,f,d,f,f,R,T,d, d,RT")
2044 (match_operand:DD_DF 1 "general_operand"
2045 " G,f,d,f,R,T,f,f,d,RT, d"))]
2046 "TARGET_64BIT && TARGET_DFP"
2059 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
2060 (set_attr "type" "fhex,floaddf,floaddf,floaddf,floaddf,floaddf,
2061 fstoredf,fstoredf,lr,load,store")
2062 (set_attr "z10prop" "*,
2075 (define_insn "*mov<mode>_64"
2076 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
2077 (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
2089 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
2090 (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
2091 fstore<mode>,fstore<mode>,lr,load,store")
2092 (set_attr "z10prop" "*,
2102 (define_insn "*mov<mode>_31"
2103 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2104 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2105 (match_operand:DD_DF 1 "general_operand"
2106 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2121 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2122 (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
2123 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
2126 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2127 (match_operand:DD_DF 1 "general_operand" ""))]
2128 "!TARGET_64BIT && reload_completed
2129 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2130 [(set (match_dup 2) (match_dup 4))
2131 (set (match_dup 3) (match_dup 5))]
2133 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2134 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2135 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2136 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2140 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2141 (match_operand:DD_DF 1 "general_operand" ""))]
2142 "!TARGET_64BIT && reload_completed
2143 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2144 [(set (match_dup 2) (match_dup 4))
2145 (set (match_dup 3) (match_dup 5))]
2147 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2148 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2149 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2150 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2154 [(set (match_operand:DD_DF 0 "register_operand" "")
2155 (match_operand:DD_DF 1 "memory_operand" ""))]
2156 "!TARGET_64BIT && reload_completed
2157 && !FP_REG_P (operands[0])
2158 && !s_operand (operands[1], VOIDmode)"
2159 [(set (match_dup 0) (match_dup 1))]
2161 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2162 s390_load_address (addr, XEXP (operands[1], 0));
2163 operands[1] = replace_equiv_address (operands[1], addr);
2167 ; mov(sf|sd) instruction pattern(s).
2170 (define_insn "mov<mode>"
2171 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2172 "=f,f,f,f,R,T,d,d,d,R,T")
2173 (match_operand:SD_SF 1 "general_operand"
2174 " G,f,R,T,f,f,d,R,T,d,d"))]
2188 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
2189 (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
2190 fstore<mode>,fstore<mode>,lr,load,load,store,store")
2191 (set_attr "z10prop" "*,
2204 ; movcc instruction pattern
2207 (define_insn "movcc"
2208 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2209 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2219 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2220 (set_attr "type" "lr,*,*,store,store,load,load")
2221 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")])
2224 ; Block move (MVC) patterns.
2228 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2229 (match_operand:BLK 1 "memory_operand" "Q"))
2230 (use (match_operand 2 "const_int_operand" "n"))]
2231 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2232 "mvc\t%O0(%2,%R0),%S1"
2233 [(set_attr "op_type" "SS")])
2237 [(set (match_operand:BLK 0 "memory_operand" "")
2238 (match_operand:BLK 1 "memory_operand" ""))
2239 (use (match_operand 2 "const_int_operand" ""))])
2241 [(set (match_operand:BLK 3 "memory_operand" "")
2242 (match_operand:BLK 4 "memory_operand" ""))
2243 (use (match_operand 5 "const_int_operand" ""))])]
2244 "s390_offset_p (operands[0], operands[3], operands[2])
2245 && s390_offset_p (operands[1], operands[4], operands[2])
2246 && !s390_overlap_p (operands[0], operands[1],
2247 INTVAL (operands[2]) + INTVAL (operands[5]))
2248 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2250 [(set (match_dup 6) (match_dup 7))
2251 (use (match_dup 8))])]
2252 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2253 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2254 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2258 ; load_multiple pattern(s).
2260 ; ??? Due to reload problems with replacing registers inside match_parallel
2261 ; we currently support load_multiple/store_multiple only after reload.
2264 (define_expand "load_multiple"
2265 [(match_par_dup 3 [(set (match_operand 0 "" "")
2266 (match_operand 1 "" ""))
2267 (use (match_operand 2 "" ""))])]
2270 enum machine_mode mode;
2276 /* Support only loading a constant number of fixed-point registers from
2277 memory and only bother with this if more than two */
2278 if (GET_CODE (operands[2]) != CONST_INT
2279 || INTVAL (operands[2]) < 2
2280 || INTVAL (operands[2]) > 16
2281 || GET_CODE (operands[1]) != MEM
2282 || GET_CODE (operands[0]) != REG
2283 || REGNO (operands[0]) >= 16)
2286 count = INTVAL (operands[2]);
2287 regno = REGNO (operands[0]);
2288 mode = GET_MODE (operands[0]);
2289 if (mode != SImode && mode != word_mode)
2292 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2293 if (!can_create_pseudo_p ())
2295 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2297 from = XEXP (operands[1], 0);
2300 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2301 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2302 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2304 from = XEXP (XEXP (operands[1], 0), 0);
2305 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2312 from = force_reg (Pmode, XEXP (operands[1], 0));
2316 for (i = 0; i < count; i++)
2317 XVECEXP (operands[3], 0, i)
2318 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2319 change_address (operands[1], mode,
2320 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
2323 (define_insn "*load_multiple_di"
2324 [(match_parallel 0 "load_multiple_operation"
2325 [(set (match_operand:DI 1 "register_operand" "=r")
2326 (match_operand:DI 2 "s_operand" "QS"))])]
2327 "reload_completed && word_mode == DImode"
2329 int words = XVECLEN (operands[0], 0);
2330 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2331 return "lmg\t%1,%0,%S2";
2333 [(set_attr "op_type" "RSY")
2334 (set_attr "type" "lm")])
2336 (define_insn "*load_multiple_si"
2337 [(match_parallel 0 "load_multiple_operation"
2338 [(set (match_operand:SI 1 "register_operand" "=r,r")
2339 (match_operand:SI 2 "s_operand" "Q,S"))])]
2342 int words = XVECLEN (operands[0], 0);
2343 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2344 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2346 [(set_attr "op_type" "RS,RSY")
2347 (set_attr "type" "lm")])
2350 ; store multiple pattern(s).
2353 (define_expand "store_multiple"
2354 [(match_par_dup 3 [(set (match_operand 0 "" "")
2355 (match_operand 1 "" ""))
2356 (use (match_operand 2 "" ""))])]
2359 enum machine_mode mode;
2365 /* Support only storing a constant number of fixed-point registers to
2366 memory and only bother with this if more than two. */
2367 if (GET_CODE (operands[2]) != CONST_INT
2368 || INTVAL (operands[2]) < 2
2369 || INTVAL (operands[2]) > 16
2370 || GET_CODE (operands[0]) != MEM
2371 || GET_CODE (operands[1]) != REG
2372 || REGNO (operands[1]) >= 16)
2375 count = INTVAL (operands[2]);
2376 regno = REGNO (operands[1]);
2377 mode = GET_MODE (operands[1]);
2378 if (mode != SImode && mode != word_mode)
2381 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2383 if (!can_create_pseudo_p ())
2385 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2387 to = XEXP (operands[0], 0);
2390 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2391 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2392 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2394 to = XEXP (XEXP (operands[0], 0), 0);
2395 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2402 to = force_reg (Pmode, XEXP (operands[0], 0));
2406 for (i = 0; i < count; i++)
2407 XVECEXP (operands[3], 0, i)
2408 = gen_rtx_SET (VOIDmode,
2409 change_address (operands[0], mode,
2410 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
2411 gen_rtx_REG (mode, regno + i));
2414 (define_insn "*store_multiple_di"
2415 [(match_parallel 0 "store_multiple_operation"
2416 [(set (match_operand:DI 1 "s_operand" "=QS")
2417 (match_operand:DI 2 "register_operand" "r"))])]
2418 "reload_completed && word_mode == DImode"
2420 int words = XVECLEN (operands[0], 0);
2421 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2422 return "stmg\t%2,%0,%S1";
2424 [(set_attr "op_type" "RSY")
2425 (set_attr "type" "stm")])
2428 (define_insn "*store_multiple_si"
2429 [(match_parallel 0 "store_multiple_operation"
2430 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2431 (match_operand:SI 2 "register_operand" "r,r"))])]
2434 int words = XVECLEN (operands[0], 0);
2435 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2436 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2438 [(set_attr "op_type" "RS,RSY")
2439 (set_attr "type" "stm")])
2442 ;; String instructions.
2445 (define_insn "*execute_rl"
2446 [(match_parallel 0 ""
2447 [(unspec [(match_operand 1 "register_operand" "a")
2448 (match_operand 2 "" "")
2449 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2450 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2451 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2453 [(set_attr "op_type" "RIL")
2454 (set_attr "type" "cs")])
2456 (define_insn "*execute"
2457 [(match_parallel 0 ""
2458 [(unspec [(match_operand 1 "register_operand" "a")
2459 (match_operand:BLK 2 "memory_operand" "R")
2460 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2461 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2462 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2464 [(set_attr "op_type" "RX")
2465 (set_attr "type" "cs")])
2469 ; strlenM instruction pattern(s).
2472 (define_expand "strlen<mode>"
2473 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2476 (unspec:P [(const_int 0)
2477 (match_operand:BLK 1 "memory_operand" "")
2479 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2480 (clobber (scratch:P))
2481 (clobber (reg:CC CC_REGNUM))])
2483 [(set (match_operand:P 0 "register_operand" "")
2484 (minus:P (match_dup 4) (match_dup 5)))
2485 (clobber (reg:CC CC_REGNUM))])]
2488 operands[4] = gen_reg_rtx (Pmode);
2489 operands[5] = gen_reg_rtx (Pmode);
2490 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2491 operands[1] = replace_equiv_address (operands[1], operands[5]);
2494 (define_insn "*strlen<mode>"
2495 [(set (match_operand:P 0 "register_operand" "=a")
2496 (unspec:P [(match_operand:P 2 "general_operand" "0")
2497 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2499 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2500 (clobber (match_scratch:P 1 "=a"))
2501 (clobber (reg:CC CC_REGNUM))]
2503 "srst\t%0,%1\;jo\t.-4"
2504 [(set_attr "length" "8")
2505 (set_attr "type" "vs")])
2508 ; cmpstrM instruction pattern(s).
2511 (define_expand "cmpstrsi"
2512 [(set (reg:SI 0) (const_int 0))
2514 [(clobber (match_operand 3 "" ""))
2515 (clobber (match_dup 4))
2516 (set (reg:CCU CC_REGNUM)
2517 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2518 (match_operand:BLK 2 "memory_operand" "")))
2521 [(set (match_operand:SI 0 "register_operand" "=d")
2522 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2523 (clobber (reg:CC CC_REGNUM))])]
2526 /* As the result of CMPINT is inverted compared to what we need,
2527 we have to swap the operands. */
2528 rtx op1 = operands[2];
2529 rtx op2 = operands[1];
2530 rtx addr1 = gen_reg_rtx (Pmode);
2531 rtx addr2 = gen_reg_rtx (Pmode);
2533 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2534 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2535 operands[1] = replace_equiv_address_nv (op1, addr1);
2536 operands[2] = replace_equiv_address_nv (op2, addr2);
2537 operands[3] = addr1;
2538 operands[4] = addr2;
2541 (define_insn "*cmpstr<mode>"
2542 [(clobber (match_operand:P 0 "register_operand" "=d"))
2543 (clobber (match_operand:P 1 "register_operand" "=d"))
2544 (set (reg:CCU CC_REGNUM)
2545 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2546 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2549 "clst\t%0,%1\;jo\t.-4"
2550 [(set_attr "length" "8")
2551 (set_attr "type" "vs")])
2554 ; movstr instruction pattern.
2557 (define_expand "movstr"
2558 [(set (reg:SI 0) (const_int 0))
2560 [(clobber (match_dup 3))
2561 (set (match_operand:BLK 1 "memory_operand" "")
2562 (match_operand:BLK 2 "memory_operand" ""))
2563 (set (match_operand 0 "register_operand" "")
2564 (unspec [(match_dup 1)
2566 (reg:SI 0)] UNSPEC_MVST))
2567 (clobber (reg:CC CC_REGNUM))])]
2570 rtx addr1 = gen_reg_rtx (Pmode);
2571 rtx addr2 = gen_reg_rtx (Pmode);
2573 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2574 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2575 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2576 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2577 operands[3] = addr2;
2580 (define_insn "*movstr"
2581 [(clobber (match_operand:P 2 "register_operand" "=d"))
2582 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2583 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2584 (set (match_operand:P 0 "register_operand" "=d")
2585 (unspec [(mem:BLK (match_dup 1))
2586 (mem:BLK (match_dup 3))
2587 (reg:SI 0)] UNSPEC_MVST))
2588 (clobber (reg:CC CC_REGNUM))]
2590 "mvst\t%1,%2\;jo\t.-4"
2591 [(set_attr "length" "8")
2592 (set_attr "type" "vs")])
2596 ; movmemM instruction pattern(s).
2599 (define_expand "movmem<mode>"
2600 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2601 (match_operand:BLK 1 "memory_operand" "")) ; source
2602 (use (match_operand:GPR 2 "general_operand" "")) ; count
2603 (match_operand 3 "" "")]
2605 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2607 ; Move a block that is up to 256 bytes in length.
2608 ; The block length is taken as (operands[2] % 256) + 1.
2610 (define_expand "movmem_short"
2612 [(set (match_operand:BLK 0 "memory_operand" "")
2613 (match_operand:BLK 1 "memory_operand" ""))
2614 (use (match_operand 2 "nonmemory_operand" ""))
2615 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2616 (clobber (match_dup 3))])]
2618 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2620 (define_insn "*movmem_short"
2621 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2622 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2623 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2624 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2625 (clobber (match_scratch 4 "=X,X,X,&a"))]
2626 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2627 && GET_MODE (operands[4]) == Pmode"
2629 [(set_attr "type" "cs")
2630 (set_attr "cpu_facility" "*,*,z10,*")])
2633 [(set (match_operand:BLK 0 "memory_operand" "")
2634 (match_operand:BLK 1 "memory_operand" ""))
2635 (use (match_operand 2 "const_int_operand" ""))
2636 (use (match_operand 3 "immediate_operand" ""))
2637 (clobber (scratch))]
2640 [(set (match_dup 0) (match_dup 1))
2641 (use (match_dup 2))])]
2642 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2645 [(set (match_operand:BLK 0 "memory_operand" "")
2646 (match_operand:BLK 1 "memory_operand" ""))
2647 (use (match_operand 2 "register_operand" ""))
2648 (use (match_operand 3 "memory_operand" ""))
2649 (clobber (scratch))]
2652 [(unspec [(match_dup 2) (match_dup 3)
2653 (const_int 0)] UNSPEC_EXECUTE)
2654 (set (match_dup 0) (match_dup 1))
2655 (use (const_int 1))])]
2659 [(set (match_operand:BLK 0 "memory_operand" "")
2660 (match_operand:BLK 1 "memory_operand" ""))
2661 (use (match_operand 2 "register_operand" ""))
2662 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2663 (clobber (scratch))]
2664 "TARGET_Z10 && reload_completed"
2666 [(unspec [(match_dup 2) (const_int 0)
2667 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2668 (set (match_dup 0) (match_dup 1))
2669 (use (const_int 1))])]
2670 "operands[3] = gen_label_rtx ();")
2673 [(set (match_operand:BLK 0 "memory_operand" "")
2674 (match_operand:BLK 1 "memory_operand" ""))
2675 (use (match_operand 2 "register_operand" ""))
2676 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2677 (clobber (match_operand 3 "register_operand" ""))]
2678 "reload_completed && TARGET_CPU_ZARCH"
2679 [(set (match_dup 3) (label_ref (match_dup 4)))
2681 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2682 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2683 (set (match_dup 0) (match_dup 1))
2684 (use (const_int 1))])]
2685 "operands[4] = gen_label_rtx ();")
2687 ; Move a block of arbitrary length.
2689 (define_expand "movmem_long"
2691 [(clobber (match_dup 2))
2692 (clobber (match_dup 3))
2693 (set (match_operand:BLK 0 "memory_operand" "")
2694 (match_operand:BLK 1 "memory_operand" ""))
2695 (use (match_operand 2 "general_operand" ""))
2697 (clobber (reg:CC CC_REGNUM))])]
2700 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2701 rtx reg0 = gen_reg_rtx (dword_mode);
2702 rtx reg1 = gen_reg_rtx (dword_mode);
2703 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2704 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2705 rtx len0 = gen_lowpart (Pmode, reg0);
2706 rtx len1 = gen_lowpart (Pmode, reg1);
2708 emit_clobber (reg0);
2709 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2710 emit_move_insn (len0, operands[2]);
2712 emit_clobber (reg1);
2713 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2714 emit_move_insn (len1, operands[2]);
2716 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2717 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2722 (define_insn "*movmem_long"
2723 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2724 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2725 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2726 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2729 (clobber (reg:CC CC_REGNUM))]
2731 "mvcle\t%0,%1,0\;jo\t.-4"
2732 [(set_attr "length" "8")
2733 (set_attr "type" "vs")])
2740 (define_expand "signbit<mode>2"
2741 [(set (reg:CCZ CC_REGNUM)
2742 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2745 (set (match_operand:SI 0 "register_operand" "=d")
2746 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2749 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2752 (define_expand "isinf<mode>2"
2753 [(set (reg:CCZ CC_REGNUM)
2754 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2757 (set (match_operand:SI 0 "register_operand" "=d")
2758 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2761 operands[2] = GEN_INT (S390_TDC_INFINITY);
2764 ; This insn is used to generate all variants of the Test Data Class
2765 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2766 ; is the register to be tested and the second one is the bit mask
2767 ; specifying the required test(s).
2769 (define_insn "*TDC_insn_<mode>"
2770 [(set (reg:CCZ CC_REGNUM)
2771 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2772 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2774 "t<_d>c<xde><bt>\t%0,%1"
2775 [(set_attr "op_type" "RXE")
2776 (set_attr "type" "fsimp<mode>")])
2778 (define_insn_and_split "*ccz_to_int"
2779 [(set (match_operand:SI 0 "register_operand" "=d")
2780 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2781 UNSPEC_CCZ_TO_INT))]
2785 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2789 ; setmemM instruction pattern(s).
2792 (define_expand "setmem<mode>"
2793 [(set (match_operand:BLK 0 "memory_operand" "")
2794 (match_operand:QI 2 "general_operand" ""))
2795 (use (match_operand:GPR 1 "general_operand" ""))
2796 (match_operand 3 "" "")]
2798 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2800 ; Clear a block that is up to 256 bytes in length.
2801 ; The block length is taken as (operands[1] % 256) + 1.
2803 (define_expand "clrmem_short"
2805 [(set (match_operand:BLK 0 "memory_operand" "")
2807 (use (match_operand 1 "nonmemory_operand" ""))
2808 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2809 (clobber (match_dup 2))
2810 (clobber (reg:CC CC_REGNUM))])]
2812 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2814 (define_insn "*clrmem_short"
2815 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2817 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2818 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2819 (clobber (match_scratch 3 "=X,X,X,&a"))
2820 (clobber (reg:CC CC_REGNUM))]
2821 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2822 && GET_MODE (operands[3]) == Pmode"
2824 [(set_attr "type" "cs")
2825 (set_attr "cpu_facility" "*,*,z10,*")])
2828 [(set (match_operand:BLK 0 "memory_operand" "")
2830 (use (match_operand 1 "const_int_operand" ""))
2831 (use (match_operand 2 "immediate_operand" ""))
2833 (clobber (reg:CC CC_REGNUM))]
2836 [(set (match_dup 0) (const_int 0))
2838 (clobber (reg:CC CC_REGNUM))])]
2839 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2842 [(set (match_operand:BLK 0 "memory_operand" "")
2844 (use (match_operand 1 "register_operand" ""))
2845 (use (match_operand 2 "memory_operand" ""))
2847 (clobber (reg:CC CC_REGNUM))]
2850 [(unspec [(match_dup 1) (match_dup 2)
2851 (const_int 0)] UNSPEC_EXECUTE)
2852 (set (match_dup 0) (const_int 0))
2854 (clobber (reg:CC CC_REGNUM))])]
2858 [(set (match_operand:BLK 0 "memory_operand" "")
2860 (use (match_operand 1 "register_operand" ""))
2861 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2863 (clobber (reg:CC CC_REGNUM))]
2864 "TARGET_Z10 && reload_completed"
2866 [(unspec [(match_dup 1) (const_int 0)
2867 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2868 (set (match_dup 0) (const_int 0))
2870 (clobber (reg:CC CC_REGNUM))])]
2871 "operands[3] = gen_label_rtx ();")
2874 [(set (match_operand:BLK 0 "memory_operand" "")
2876 (use (match_operand 1 "register_operand" ""))
2877 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2878 (clobber (match_operand 2 "register_operand" ""))
2879 (clobber (reg:CC CC_REGNUM))]
2880 "reload_completed && TARGET_CPU_ZARCH"
2881 [(set (match_dup 2) (label_ref (match_dup 3)))
2883 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2884 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2885 (set (match_dup 0) (const_int 0))
2887 (clobber (reg:CC CC_REGNUM))])]
2888 "operands[3] = gen_label_rtx ();")
2890 ; Initialize a block of arbitrary length with (operands[2] % 256).
2892 (define_expand "setmem_long"
2894 [(clobber (match_dup 1))
2895 (set (match_operand:BLK 0 "memory_operand" "")
2896 (match_operand 2 "shift_count_or_setmem_operand" ""))
2897 (use (match_operand 1 "general_operand" ""))
2899 (clobber (reg:CC CC_REGNUM))])]
2902 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2903 rtx reg0 = gen_reg_rtx (dword_mode);
2904 rtx reg1 = gen_reg_rtx (dword_mode);
2905 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2906 rtx len0 = gen_lowpart (Pmode, reg0);
2908 emit_clobber (reg0);
2909 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2910 emit_move_insn (len0, operands[1]);
2912 emit_move_insn (reg1, const0_rtx);
2914 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2919 (define_insn "*setmem_long"
2920 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2921 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2922 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2924 (use (match_operand:<DBL> 1 "register_operand" "d"))
2925 (clobber (reg:CC CC_REGNUM))]
2927 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2928 [(set_attr "length" "8")
2929 (set_attr "type" "vs")])
2931 (define_insn "*setmem_long_and"
2932 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2933 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2934 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2935 (match_operand 4 "const_int_operand" "n")))
2937 (use (match_operand:<DBL> 1 "register_operand" "d"))
2938 (clobber (reg:CC CC_REGNUM))]
2939 "(INTVAL (operands[4]) & 255) == 255"
2940 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2941 [(set_attr "length" "8")
2942 (set_attr "type" "vs")])
2944 ; cmpmemM instruction pattern(s).
2947 (define_expand "cmpmemsi"
2948 [(set (match_operand:SI 0 "register_operand" "")
2949 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2950 (match_operand:BLK 2 "memory_operand" "") ) )
2951 (use (match_operand:SI 3 "general_operand" ""))
2952 (use (match_operand:SI 4 "" ""))]
2954 "s390_expand_cmpmem (operands[0], operands[1],
2955 operands[2], operands[3]); DONE;")
2957 ; Compare a block that is up to 256 bytes in length.
2958 ; The block length is taken as (operands[2] % 256) + 1.
2960 (define_expand "cmpmem_short"
2962 [(set (reg:CCU CC_REGNUM)
2963 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2964 (match_operand:BLK 1 "memory_operand" "")))
2965 (use (match_operand 2 "nonmemory_operand" ""))
2966 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2967 (clobber (match_dup 3))])]
2969 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2971 (define_insn "*cmpmem_short"
2972 [(set (reg:CCU CC_REGNUM)
2973 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
2974 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
2975 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2976 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2977 (clobber (match_scratch 4 "=X,X,X,&a"))]
2978 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2979 && GET_MODE (operands[4]) == Pmode"
2981 [(set_attr "type" "cs")
2982 (set_attr "cpu_facility" "*,*,z10,*")])
2985 [(set (reg:CCU CC_REGNUM)
2986 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2987 (match_operand:BLK 1 "memory_operand" "")))
2988 (use (match_operand 2 "const_int_operand" ""))
2989 (use (match_operand 3 "immediate_operand" ""))
2990 (clobber (scratch))]
2993 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2994 (use (match_dup 2))])]
2995 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2998 [(set (reg:CCU CC_REGNUM)
2999 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3000 (match_operand:BLK 1 "memory_operand" "")))
3001 (use (match_operand 2 "register_operand" ""))
3002 (use (match_operand 3 "memory_operand" ""))
3003 (clobber (scratch))]
3006 [(unspec [(match_dup 2) (match_dup 3)
3007 (const_int 0)] UNSPEC_EXECUTE)
3008 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3009 (use (const_int 1))])]
3013 [(set (reg:CCU CC_REGNUM)
3014 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3015 (match_operand:BLK 1 "memory_operand" "")))
3016 (use (match_operand 2 "register_operand" ""))
3017 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3018 (clobber (scratch))]
3019 "TARGET_Z10 && reload_completed"
3021 [(unspec [(match_dup 2) (const_int 0)
3022 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3023 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3024 (use (const_int 1))])]
3025 "operands[4] = gen_label_rtx ();")
3028 [(set (reg:CCU CC_REGNUM)
3029 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3030 (match_operand:BLK 1 "memory_operand" "")))
3031 (use (match_operand 2 "register_operand" ""))
3032 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3033 (clobber (match_operand 3 "register_operand" ""))]
3034 "reload_completed && TARGET_CPU_ZARCH"
3035 [(set (match_dup 3) (label_ref (match_dup 4)))
3037 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3038 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3039 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3040 (use (const_int 1))])]
3041 "operands[4] = gen_label_rtx ();")
3043 ; Compare a block of arbitrary length.
3045 (define_expand "cmpmem_long"
3047 [(clobber (match_dup 2))
3048 (clobber (match_dup 3))
3049 (set (reg:CCU CC_REGNUM)
3050 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3051 (match_operand:BLK 1 "memory_operand" "")))
3052 (use (match_operand 2 "general_operand" ""))
3053 (use (match_dup 3))])]
3056 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
3057 rtx reg0 = gen_reg_rtx (dword_mode);
3058 rtx reg1 = gen_reg_rtx (dword_mode);
3059 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
3060 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
3061 rtx len0 = gen_lowpart (Pmode, reg0);
3062 rtx len1 = gen_lowpart (Pmode, reg1);
3064 emit_clobber (reg0);
3065 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3066 emit_move_insn (len0, operands[2]);
3068 emit_clobber (reg1);
3069 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3070 emit_move_insn (len1, operands[2]);
3072 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3073 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3078 (define_insn "*cmpmem_long"
3079 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3080 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3081 (set (reg:CCU CC_REGNUM)
3082 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3083 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3085 (use (match_dup 3))]
3087 "clcle\t%0,%1,0\;jo\t.-4"
3088 [(set_attr "length" "8")
3089 (set_attr "type" "vs")])
3091 ; Convert CCUmode condition code to integer.
3092 ; Result is zero if EQ, positive if LTU, negative if GTU.
3094 (define_insn_and_split "cmpint"
3095 [(set (match_operand:SI 0 "register_operand" "=d")
3096 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3098 (clobber (reg:CC CC_REGNUM))]
3102 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3104 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3105 (clobber (reg:CC CC_REGNUM))])])
3107 (define_insn_and_split "*cmpint_cc"
3108 [(set (reg CC_REGNUM)
3109 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3112 (set (match_operand:SI 0 "register_operand" "=d")
3113 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3114 "s390_match_ccmode (insn, CCSmode)"
3116 "&& reload_completed"
3117 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3119 [(set (match_dup 2) (match_dup 3))
3120 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3122 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3123 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3124 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3127 (define_insn_and_split "*cmpint_sign"
3128 [(set (match_operand:DI 0 "register_operand" "=d")
3129 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3130 UNSPEC_CCU_TO_INT)))
3131 (clobber (reg:CC CC_REGNUM))]
3134 "&& reload_completed"
3135 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3137 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3138 (clobber (reg:CC CC_REGNUM))])])
3140 (define_insn_and_split "*cmpint_sign_cc"
3141 [(set (reg CC_REGNUM)
3142 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3143 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3144 UNSPEC_CCU_TO_INT) 0)
3145 (const_int 32)) (const_int 32))
3147 (set (match_operand:DI 0 "register_operand" "=d")
3148 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3149 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
3151 "&& reload_completed"
3152 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3154 [(set (match_dup 2) (match_dup 3))
3155 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3157 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3158 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3159 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3164 ;;- Conversion instructions.
3167 (define_insn "*sethighpartsi"
3168 [(set (match_operand:SI 0 "register_operand" "=d,d")
3169 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3170 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3171 (clobber (reg:CC CC_REGNUM))]
3176 [(set_attr "op_type" "RS,RSY")
3177 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3179 (define_insn "*sethighpartdi_64"
3180 [(set (match_operand:DI 0 "register_operand" "=d")
3181 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3182 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3183 (clobber (reg:CC CC_REGNUM))]
3186 [(set_attr "op_type" "RSY")
3187 (set_attr "z10prop" "z10_super")])
3189 (define_insn "*sethighpartdi_31"
3190 [(set (match_operand:DI 0 "register_operand" "=d,d")
3191 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3192 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3193 (clobber (reg:CC CC_REGNUM))]
3198 [(set_attr "op_type" "RS,RSY")
3199 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3202 (define_insn_and_split "*extzv<mode>"
3203 [(set (match_operand:GPR 0 "register_operand" "=d")
3204 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3205 (match_operand 2 "const_int_operand" "n")
3207 (clobber (reg:CC CC_REGNUM))]
3208 "INTVAL (operands[2]) > 0
3209 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3211 "&& reload_completed"
3213 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3214 (clobber (reg:CC CC_REGNUM))])
3215 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3217 int bitsize = INTVAL (operands[2]);
3218 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3219 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3221 operands[1] = adjust_address (operands[1], BLKmode, 0);
3222 set_mem_size (operands[1], GEN_INT (size));
3223 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3224 operands[3] = GEN_INT (mask);
3227 (define_insn_and_split "*extv<mode>"
3228 [(set (match_operand:GPR 0 "register_operand" "=d")
3229 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3230 (match_operand 2 "const_int_operand" "n")
3232 (clobber (reg:CC CC_REGNUM))]
3233 "INTVAL (operands[2]) > 0
3234 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3236 "&& reload_completed"
3238 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3239 (clobber (reg:CC CC_REGNUM))])
3241 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3242 (clobber (reg:CC CC_REGNUM))])]
3244 int bitsize = INTVAL (operands[2]);
3245 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3246 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3248 operands[1] = adjust_address (operands[1], BLKmode, 0);
3249 set_mem_size (operands[1], GEN_INT (size));
3250 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3251 operands[3] = GEN_INT (mask);
3255 ; insv instruction patterns
3258 (define_expand "insv"
3259 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3260 (match_operand 1 "const_int_operand" "")
3261 (match_operand 2 "const_int_operand" ""))
3262 (match_operand 3 "general_operand" ""))]
3265 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3270 (define_insn "*insv<mode>_z10"
3271 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3272 (match_operand 1 "const_int_operand" "I")
3273 (match_operand 2 "const_int_operand" "I"))
3274 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3275 (clobber (reg:CC CC_REGNUM))]
3277 && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
3278 GET_MODE_BITSIZE (<MODE>mode)"
3280 int start = INTVAL (operands[2]);
3281 int size = INTVAL (operands[1]);
3282 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
3284 operands[2] = GEN_INT (offset + start); /* start bit position */
3285 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
3286 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
3287 start - size); /* left shift count */
3289 return "risbg\t%0,%3,%b2,%b1,%b4";
3291 [(set_attr "op_type" "RIE")
3292 (set_attr "z10prop" "z10_super_E1")])
3294 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3295 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3296 (define_insn "*insv<mode>_z10_noshift"
3297 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3298 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3299 (match_operand 2 "const_int_operand" "n"))
3300 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3301 (match_operand 4 "const_int_operand" "n"))))
3302 (clobber (reg:CC CC_REGNUM))]
3304 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3305 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
3306 && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
3312 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3313 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3315 operands[5] = GEN_INT (64 - start - size); /* start bit position */
3316 operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
3317 operands[7] = const0_rtx; /* left shift count */
3319 return "risbg\t%0,%1,%b5,%b6,%b7";
3321 [(set_attr "op_type" "RIE")
3322 (set_attr "z10prop" "z10_super_E1")])
3324 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3325 (define_insn "*insv<mode>_or_z10_noshift"
3326 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3327 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3328 (match_operand 2 "const_int_operand" "n"))
3329 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3330 (clobber (reg:CC CC_REGNUM))]
3332 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3333 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
3338 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3339 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3341 operands[4] = GEN_INT (64 - start - size); /* start bit position */
3342 operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
3343 operands[6] = const0_rtx; /* left shift count */
3345 return "rosbg\t%0,%1,%b4,%b5,%b6";
3347 [(set_attr "op_type" "RIE")])
3349 (define_insn "*insv<mode>_mem_reg"
3350 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
3351 (match_operand 1 "const_int_operand" "n,n")
3353 (match_operand:P 2 "register_operand" "d,d"))]
3354 "INTVAL (operands[1]) > 0
3355 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3356 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3358 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3360 operands[1] = GEN_INT ((1ul << size) - 1);
3361 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3362 : "stcmy\t%2,%1,%S0";
3364 [(set_attr "op_type" "RS,RSY")
3365 (set_attr "z10prop" "z10_super,z10_super")])
3367 (define_insn "*insvdi_mem_reghigh"
3368 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3369 (match_operand 1 "const_int_operand" "n")
3371 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3374 && INTVAL (operands[1]) > 0
3375 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3376 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3378 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3380 operands[1] = GEN_INT ((1ul << size) - 1);
3381 return "stcmh\t%2,%1,%S0";
3383 [(set_attr "op_type" "RSY")
3384 (set_attr "z10prop" "z10_super")])
3386 (define_insn "*insv<mode>_reg_imm"
3387 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3389 (match_operand 1 "const_int_operand" "n"))
3390 (match_operand:P 2 "const_int_operand" "n"))]
3392 && INTVAL (operands[1]) >= 0
3393 && INTVAL (operands[1]) < BITS_PER_WORD
3394 && INTVAL (operands[1]) % 16 == 0"
3396 switch (BITS_PER_WORD - INTVAL (operands[1]))
3398 case 64: return "iihh\t%0,%x2"; break;
3399 case 48: return "iihl\t%0,%x2"; break;
3400 case 32: return "iilh\t%0,%x2"; break;
3401 case 16: return "iill\t%0,%x2"; break;
3402 default: gcc_unreachable();
3405 [(set_attr "op_type" "RI")
3406 (set_attr "z10prop" "z10_super_E1")])
3408 ; Update the left-most 32 bit of a DI.
3409 (define_insn "*insv_h_di_reg_extimm"
3410 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3413 (match_operand:DI 1 "const_int_operand" "n"))]
3416 [(set_attr "op_type" "RIL")
3417 (set_attr "z10prop" "z10_fwd_E1")])
3419 ; Update the right-most 32 bit of a DI, or the whole of a SI.
3420 (define_insn "*insv_l<mode>_reg_extimm"
3421 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3423 (match_operand 1 "const_int_operand" "n"))
3424 (match_operand:P 2 "const_int_operand" "n"))]
3426 && BITS_PER_WORD - INTVAL (operands[1]) == 32"
3428 [(set_attr "op_type" "RIL")
3429 (set_attr "z10prop" "z10_fwd_A1")])
3432 ; extendsidi2 instruction pattern(s).
3435 (define_expand "extendsidi2"
3436 [(set (match_operand:DI 0 "register_operand" "")
3437 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3442 emit_clobber (operands[0]);
3443 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3444 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3445 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3450 (define_insn "*extendsidi2"
3451 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3452 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3458 [(set_attr "op_type" "RRE,RXY,RIL")
3459 (set_attr "type" "*,*,larl")
3460 (set_attr "cpu_facility" "*,*,z10")
3461 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3464 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3467 (define_expand "extend<HQI:mode><DSI:mode>2"
3468 [(set (match_operand:DSI 0 "register_operand" "")
3469 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3472 if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
3474 rtx tmp = gen_reg_rtx (SImode);
3475 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3476 emit_insn (gen_extendsidi2 (operands[0], tmp));
3479 else if (!TARGET_EXTIMM)
3481 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
3482 GET_MODE_BITSIZE (<HQI:MODE>mode));
3484 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3485 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3486 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3492 ; extendhidi2 instruction pattern(s).
3495 (define_insn "*extendhidi2_extimm"
3496 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3497 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3498 "TARGET_64BIT && TARGET_EXTIMM"
3503 [(set_attr "op_type" "RRE,RXY,RIL")
3504 (set_attr "type" "*,*,larl")
3505 (set_attr "cpu_facility" "extimm,extimm,z10")
3506 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3508 (define_insn "*extendhidi2"
3509 [(set (match_operand:DI 0 "register_operand" "=d")
3510 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3513 [(set_attr "op_type" "RXY")
3514 (set_attr "z10prop" "z10_super_E1")])
3517 ; extendhisi2 instruction pattern(s).
3520 (define_insn "*extendhisi2_extimm"
3521 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3522 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3529 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3530 (set_attr "type" "*,*,*,larl")
3531 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3532 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3534 (define_insn "*extendhisi2"
3535 [(set (match_operand:SI 0 "register_operand" "=d,d")
3536 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3541 [(set_attr "op_type" "RX,RXY")
3542 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3545 ; extendqi(si|di)2 instruction pattern(s).
3548 ; lbr, lgbr, lb, lgb
3549 (define_insn "*extendqi<mode>2_extimm"
3550 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3551 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3556 [(set_attr "op_type" "RRE,RXY")
3557 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3560 (define_insn "*extendqi<mode>2"
3561 [(set (match_operand:GPR 0 "register_operand" "=d")
3562 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3563 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3565 [(set_attr "op_type" "RXY")
3566 (set_attr "z10prop" "z10_super_E1")])
3568 (define_insn_and_split "*extendqi<mode>2_short_displ"
3569 [(set (match_operand:GPR 0 "register_operand" "=d")
3570 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3571 (clobber (reg:CC CC_REGNUM))]
3572 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3574 "&& reload_completed"
3576 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3577 (clobber (reg:CC CC_REGNUM))])
3579 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3580 (clobber (reg:CC CC_REGNUM))])]
3582 operands[1] = adjust_address (operands[1], BLKmode, 0);
3583 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
3584 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
3585 - GET_MODE_BITSIZE (QImode));
3589 ; zero_extendsidi2 instruction pattern(s).
3592 (define_expand "zero_extendsidi2"
3593 [(set (match_operand:DI 0 "register_operand" "")
3594 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3599 emit_clobber (operands[0]);
3600 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3601 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3606 (define_insn "*zero_extendsidi2"
3607 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3608 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3614 [(set_attr "op_type" "RRE,RXY,RIL")
3615 (set_attr "type" "*,*,larl")
3616 (set_attr "cpu_facility" "*,*,z10")
3617 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3620 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3623 (define_insn "*llgt_sidi"
3624 [(set (match_operand:DI 0 "register_operand" "=d")
3625 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3626 (const_int 2147483647)))]
3629 [(set_attr "op_type" "RXE")
3630 (set_attr "z10prop" "z10_super_E1")])
3632 (define_insn_and_split "*llgt_sidi_split"
3633 [(set (match_operand:DI 0 "register_operand" "=d")
3634 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3635 (const_int 2147483647)))
3636 (clobber (reg:CC CC_REGNUM))]
3639 "&& reload_completed"
3641 (and:DI (subreg:DI (match_dup 1) 0)
3642 (const_int 2147483647)))]
3645 (define_insn "*llgt_sisi"
3646 [(set (match_operand:SI 0 "register_operand" "=d,d")
3647 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3648 (const_int 2147483647)))]
3653 [(set_attr "op_type" "RRE,RXE")
3654 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3656 (define_insn "*llgt_didi"
3657 [(set (match_operand:DI 0 "register_operand" "=d,d")
3658 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3659 (const_int 2147483647)))]
3664 [(set_attr "op_type" "RRE,RXE")
3665 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3668 [(set (match_operand:GPR 0 "register_operand" "")
3669 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3670 (const_int 2147483647)))
3671 (clobber (reg:CC CC_REGNUM))]
3672 "TARGET_ZARCH && reload_completed"
3674 (and:GPR (match_dup 1)
3675 (const_int 2147483647)))]
3679 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3682 (define_expand "zero_extend<mode>di2"
3683 [(set (match_operand:DI 0 "register_operand" "")
3684 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3689 rtx tmp = gen_reg_rtx (SImode);
3690 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3691 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3694 else if (!TARGET_EXTIMM)
3696 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3697 GET_MODE_BITSIZE(<MODE>mode));
3698 operands[1] = gen_lowpart (DImode, operands[1]);
3699 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3700 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3705 (define_expand "zero_extend<mode>si2"
3706 [(set (match_operand:SI 0 "register_operand" "")
3707 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3712 operands[1] = gen_lowpart (SImode, operands[1]);
3713 emit_insn (gen_andsi3 (operands[0], operands[1],
3714 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3720 (define_insn "*zero_extendhi<mode>2_z10"
3721 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3722 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3728 [(set_attr "op_type" "RXY,RRE,RIL")
3729 (set_attr "type" "*,*,larl")
3730 (set_attr "cpu_facility" "*,*,z10")
3731 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3733 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3734 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3735 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3736 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3741 [(set_attr "op_type" "RRE,RXY")
3742 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3745 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3746 [(set (match_operand:GPR 0 "register_operand" "=d")
3747 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3748 "TARGET_ZARCH && !TARGET_EXTIMM"
3750 [(set_attr "op_type" "RXY")
3751 (set_attr "z10prop" "z10_fwd_A3")])
3753 (define_insn_and_split "*zero_extendhisi2_31"
3754 [(set (match_operand:SI 0 "register_operand" "=&d")
3755 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3756 (clobber (reg:CC CC_REGNUM))]
3759 "&& reload_completed"
3760 [(set (match_dup 0) (const_int 0))
3762 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3763 (clobber (reg:CC CC_REGNUM))])]
3764 "operands[2] = gen_lowpart (HImode, operands[0]);")
3766 (define_insn_and_split "*zero_extendqisi2_31"
3767 [(set (match_operand:SI 0 "register_operand" "=&d")
3768 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
3771 "&& reload_completed"
3772 [(set (match_dup 0) (const_int 0))
3773 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3774 "operands[2] = gen_lowpart (QImode, operands[0]);")
3777 ; zero_extendqihi2 instruction pattern(s).
3780 (define_expand "zero_extendqihi2"
3781 [(set (match_operand:HI 0 "register_operand" "")
3782 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3783 "TARGET_ZARCH && !TARGET_EXTIMM"
3785 operands[1] = gen_lowpart (HImode, operands[1]);
3786 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3790 (define_insn "*zero_extendqihi2_64"
3791 [(set (match_operand:HI 0 "register_operand" "=d")
3792 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3793 "TARGET_ZARCH && !TARGET_EXTIMM"
3795 [(set_attr "op_type" "RXY")
3796 (set_attr "z10prop" "z10_fwd_A3")])
3798 (define_insn_and_split "*zero_extendqihi2_31"
3799 [(set (match_operand:HI 0 "register_operand" "=&d")
3800 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3803 "&& reload_completed"
3804 [(set (match_dup 0) (const_int 0))
3805 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3806 "operands[2] = gen_lowpart (QImode, operands[0]);")
3809 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3812 (define_expand "fixuns_truncdddi2"
3814 [(set (match_operand:DI 0 "register_operand" "")
3815 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3816 (clobber (match_scratch:TD 2 "=f"))])]
3820 rtx label1 = gen_label_rtx ();
3821 rtx label2 = gen_label_rtx ();
3822 rtx temp = gen_reg_rtx (TDmode);
3823 REAL_VALUE_TYPE cmp, sub;
3825 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3826 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3828 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3829 solution is doing the check and the subtraction in TD mode and using a
3830 TD -> DI convert afterwards. */
3831 emit_insn (gen_extendddtd2 (temp, operands[1]));
3832 temp = force_reg (TDmode, temp);
3833 emit_cmp_and_jump_insns (temp,
3834 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3835 LT, NULL_RTX, VOIDmode, 0, label1);
3836 emit_insn (gen_subtd3 (temp, temp,
3837 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3838 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3841 emit_label (label1);
3842 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3843 emit_label (label2);
3847 (define_expand "fixuns_trunctddi2"
3848 [(set (match_operand:DI 0 "register_operand" "")
3849 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
3852 rtx label1 = gen_label_rtx ();
3853 rtx label2 = gen_label_rtx ();
3854 rtx temp = gen_reg_rtx (TDmode);
3855 REAL_VALUE_TYPE cmp, sub;
3857 operands[1] = force_reg (TDmode, operands[1]);
3858 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3859 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3861 emit_cmp_and_jump_insns (operands[1],
3862 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3863 LT, NULL_RTX, VOIDmode, 0, label1);
3864 emit_insn (gen_subtd3 (temp, operands[1],
3865 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3866 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3869 emit_label (label1);
3870 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3871 emit_label (label2);
3876 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2
3877 ; instruction pattern(s).
3880 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
3881 [(set (match_operand:GPR 0 "register_operand" "")
3882 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
3885 rtx label1 = gen_label_rtx ();
3886 rtx label2 = gen_label_rtx ();
3887 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
3888 REAL_VALUE_TYPE cmp, sub;
3890 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
3891 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
3892 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
3894 emit_cmp_and_jump_insns (operands[1],
3895 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
3896 LT, NULL_RTX, VOIDmode, 0, label1);
3897 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
3898 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
3899 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
3903 emit_label (label1);
3904 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
3905 operands[1], GEN_INT (5)));
3906 emit_label (label2);
3910 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
3911 [(set (match_operand:GPR 0 "register_operand" "")
3912 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
3915 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
3920 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
3921 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
3922 [(set (match_operand:GPR 0 "register_operand" "=d")
3923 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
3924 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3925 (clobber (reg:CC CC_REGNUM))]
3927 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
3928 [(set_attr "op_type" "RRE")
3929 (set_attr "type" "ftoi")])
3933 ; fix_trunc(td|dd)di2 instruction pattern(s).
3936 (define_expand "fix_trunc<mode>di2"
3937 [(set (match_operand:DI 0 "register_operand" "")
3938 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
3939 "TARGET_64BIT && TARGET_HARD_DFP"
3941 operands[1] = force_reg (<MODE>mode, operands[1]);
3942 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
3948 (define_insn "fix_trunc<DFP:mode>di2_dfp"
3949 [(set (match_operand:DI 0 "register_operand" "=d")
3950 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
3951 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3952 (clobber (reg:CC CC_REGNUM))]
3953 "TARGET_64BIT && TARGET_HARD_DFP"
3954 "cg<DFP:xde>tr\t%0,%h2,%1"
3955 [(set_attr "op_type" "RRF")
3956 (set_attr "type" "ftoidfp")])
3960 ; fix_trunctf(si|di)2 instruction pattern(s).
3963 (define_expand "fix_trunctf<mode>2"
3964 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
3965 (fix:GPR (match_operand:TF 1 "register_operand" "")))
3966 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3967 (clobber (reg:CC CC_REGNUM))])]
3973 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
3976 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
3977 (define_insn "floatdi<mode>2"
3978 [(set (match_operand:FP 0 "register_operand" "=f")
3979 (float:FP (match_operand:DI 1 "register_operand" "d")))]
3980 "TARGET_64BIT && TARGET_HARD_FLOAT"
3981 "c<xde>g<bt>r\t%0,%1"
3982 [(set_attr "op_type" "RRE")
3983 (set_attr "type" "itof<mode>" )])
3985 ; cxfbr, cdfbr, cefbr
3986 (define_insn "floatsi<mode>2"
3987 [(set (match_operand:BFP 0 "register_operand" "=f")
3988 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
3991 [(set_attr "op_type" "RRE")
3992 (set_attr "type" "itof<mode>" )])
3996 ; truncdfsf2 instruction pattern(s).
3999 (define_insn "truncdfsf2"
4000 [(set (match_operand:SF 0 "register_operand" "=f")
4001 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4004 [(set_attr "op_type" "RRE")
4005 (set_attr "type" "ftruncdf")])
4008 ; trunctf(df|sf)2 instruction pattern(s).
4012 (define_insn "trunctf<mode>2"
4013 [(set (match_operand:DSF 0 "register_operand" "=f")
4014 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4015 (clobber (match_scratch:TF 2 "=f"))]
4017 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4018 [(set_attr "length" "6")
4019 (set_attr "type" "ftrunctf")])
4022 ; trunctddd2 and truncddsd2 instruction pattern(s).
4025 (define_insn "trunctddd2"
4026 [(set (match_operand:DD 0 "register_operand" "=f")
4027 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4028 (clobber (match_scratch:TD 2 "=f"))]
4030 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4031 [(set_attr "length" "6")
4032 (set_attr "type" "ftruncdd")])
4034 (define_insn "truncddsd2"
4035 [(set (match_operand:SD 0 "register_operand" "=f")
4036 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4039 [(set_attr "op_type" "RRF")
4040 (set_attr "type" "ftruncsd")])
4043 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4046 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4047 (define_insn "extend<DSF:mode><BFP:mode>2"
4048 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4049 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4051 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4053 l<BFP:xde><DSF:xde>br\t%0,%1
4054 l<BFP:xde><DSF:xde>b\t%0,%1"
4055 [(set_attr "op_type" "RRE,RXE")
4056 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4059 ; extendddtd2 and extendsddd2 instruction pattern(s).
4062 (define_insn "extendddtd2"
4063 [(set (match_operand:TD 0 "register_operand" "=f")
4064 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4067 [(set_attr "op_type" "RRF")
4068 (set_attr "type" "fsimptf")])
4070 (define_insn "extendsddd2"
4071 [(set (match_operand:DD 0 "register_operand" "=f")
4072 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4075 [(set_attr "op_type" "RRF")
4076 (set_attr "type" "fsimptf")])
4078 ; Binary <-> Decimal floating point trunc patterns
4081 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4082 [(set (reg:DFP_ALL FPR0_REGNUM)
4083 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4084 (use (reg:SI GPR0_REGNUM))
4085 (clobber (reg:CC CC_REGNUM))]
4089 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4090 [(set (reg:BFP FPR0_REGNUM)
4091 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4092 (use (reg:SI GPR0_REGNUM))
4093 (clobber (reg:CC CC_REGNUM))]
4097 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4098 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4099 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4101 [(set (reg:DFP_ALL FPR0_REGNUM)
4102 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4103 (use (reg:SI GPR0_REGNUM))
4104 (clobber (reg:CC CC_REGNUM))])
4105 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4106 (reg:DFP_ALL FPR0_REGNUM))]
4108 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4110 HOST_WIDE_INT flags;
4112 flags = (PFPO_CONVERT |
4113 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4114 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4116 operands[2] = GEN_INT (flags);
4119 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4120 [(set (reg:DFP_ALL FPR2_REGNUM)
4121 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4122 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4124 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4125 (use (reg:SI GPR0_REGNUM))
4126 (clobber (reg:CC CC_REGNUM))])
4127 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4129 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4131 HOST_WIDE_INT flags;
4133 flags = (PFPO_CONVERT |
4134 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4135 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4137 operands[2] = GEN_INT (flags);
4141 ; Binary <-> Decimal floating point extend patterns
4144 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4145 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4146 (use (reg:SI GPR0_REGNUM))
4147 (clobber (reg:CC CC_REGNUM))]
4151 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4152 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4153 (use (reg:SI GPR0_REGNUM))
4154 (clobber (reg:CC CC_REGNUM))]
4158 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4159 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4160 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4162 [(set (reg:DFP_ALL FPR0_REGNUM)
4163 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4164 (use (reg:SI GPR0_REGNUM))
4165 (clobber (reg:CC CC_REGNUM))])
4166 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4167 (reg:DFP_ALL FPR0_REGNUM))]
4169 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4171 HOST_WIDE_INT flags;
4173 flags = (PFPO_CONVERT |
4174 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4175 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4177 operands[2] = GEN_INT (flags);
4180 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4181 [(set (reg:DFP_ALL FPR2_REGNUM)
4182 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4183 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4185 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4186 (use (reg:SI GPR0_REGNUM))
4187 (clobber (reg:CC CC_REGNUM))])
4188 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4190 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4192 HOST_WIDE_INT flags;
4194 flags = (PFPO_CONVERT |
4195 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4196 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4198 operands[2] = GEN_INT (flags);
4203 ;; ARITHMETIC OPERATIONS
4205 ; arithmetic operations set the ConditionCode,
4206 ; because of unpredictable Bits in Register for Halfword and Byte
4207 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4210 ;;- Add instructions.
4214 ; addti3 instruction pattern(s).
4217 (define_insn_and_split "addti3"
4218 [(set (match_operand:TI 0 "register_operand" "=&d")
4219 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4220 (match_operand:TI 2 "general_operand" "do") ) )
4221 (clobber (reg:CC CC_REGNUM))]
4224 "&& reload_completed"
4226 [(set (reg:CCL1 CC_REGNUM)
4227 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4229 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4231 [(set (match_dup 3) (plus:DI
4232 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4233 (match_dup 4)) (match_dup 5)))
4234 (clobber (reg:CC CC_REGNUM))])]
4235 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4236 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4237 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4238 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4239 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4240 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4243 ; adddi3 instruction pattern(s).
4246 (define_expand "adddi3"
4248 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4249 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4250 (match_operand:DI 2 "general_operand" "")))
4251 (clobber (reg:CC CC_REGNUM))])]
4255 (define_insn "*adddi3_sign"
4256 [(set (match_operand:DI 0 "register_operand" "=d,d")
4257 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4258 (match_operand:DI 1 "register_operand" "0,0")))
4259 (clobber (reg:CC CC_REGNUM))]
4264 [(set_attr "op_type" "RRE,RXY")])
4266 (define_insn "*adddi3_zero_cc"
4267 [(set (reg CC_REGNUM)
4268 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4269 (match_operand:DI 1 "register_operand" "0,0"))
4271 (set (match_operand:DI 0 "register_operand" "=d,d")
4272 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4273 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4277 [(set_attr "op_type" "RRE,RXY")
4278 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4280 (define_insn "*adddi3_zero_cconly"
4281 [(set (reg CC_REGNUM)
4282 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4283 (match_operand:DI 1 "register_operand" "0,0"))
4285 (clobber (match_scratch:DI 0 "=d,d"))]
4286 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4290 [(set_attr "op_type" "RRE,RXY")
4291 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4293 (define_insn "*adddi3_zero"
4294 [(set (match_operand:DI 0 "register_operand" "=d,d")
4295 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4296 (match_operand:DI 1 "register_operand" "0,0")))
4297 (clobber (reg:CC CC_REGNUM))]
4302 [(set_attr "op_type" "RRE,RXY")
4303 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4305 (define_insn_and_split "*adddi3_31z"
4306 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4307 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4308 (match_operand:DI 2 "general_operand" "do") ) )
4309 (clobber (reg:CC CC_REGNUM))]
4310 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4312 "&& reload_completed"
4314 [(set (reg:CCL1 CC_REGNUM)
4315 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4317 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4319 [(set (match_dup 3) (plus:SI
4320 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4321 (match_dup 4)) (match_dup 5)))
4322 (clobber (reg:CC CC_REGNUM))])]
4323 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4324 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4325 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4326 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4327 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4328 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4330 (define_insn_and_split "*adddi3_31"
4331 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4332 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4333 (match_operand:DI 2 "general_operand" "do") ) )
4334 (clobber (reg:CC CC_REGNUM))]
4337 "&& reload_completed"
4339 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4340 (clobber (reg:CC CC_REGNUM))])
4342 [(set (reg:CCL1 CC_REGNUM)
4343 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4345 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4347 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4349 (label_ref (match_dup 9))))
4351 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4352 (clobber (reg:CC CC_REGNUM))])
4354 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4355 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4356 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4357 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4358 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4359 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4360 operands[9] = gen_label_rtx ();")
4363 ; addsi3 instruction pattern(s).
4366 (define_expand "addsi3"
4368 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4369 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4370 (match_operand:SI 2 "general_operand" "")))
4371 (clobber (reg:CC CC_REGNUM))])]
4375 (define_insn "*addsi3_sign"
4376 [(set (match_operand:SI 0 "register_operand" "=d,d")
4377 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4378 (match_operand:SI 1 "register_operand" "0,0")))
4379 (clobber (reg:CC CC_REGNUM))]
4384 [(set_attr "op_type" "RX,RXY")])
4387 ; add(di|si)3 instruction pattern(s).
4390 ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4391 (define_insn "*add<mode>3"
4392 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS")
4393 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
4394 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) )
4395 (clobber (reg:CC CC_REGNUM))]
4405 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY")
4406 (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10")
4407 (set_attr "z10prop" "z10_super_E1,
4415 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4416 (define_insn "*add<mode>3_carry1_cc"
4417 [(set (reg CC_REGNUM)
4418 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4419 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4421 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d")
4422 (plus:GPR (match_dup 1) (match_dup 2)))]
4423 "s390_match_ccmode (insn, CCL1mode)"
4431 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4432 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4433 (set_attr "z10prop" "z10_super_E1,
4440 ; alr, al, aly, algr, alg
4441 (define_insn "*add<mode>3_carry1_cconly"
4442 [(set (reg CC_REGNUM)
4443 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4444 (match_operand:GPR 2 "general_operand" "d,R,T"))
4446 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4447 "s390_match_ccmode (insn, CCL1mode)"
4452 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4453 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4455 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4456 (define_insn "*add<mode>3_carry2_cc"
4457 [(set (reg CC_REGNUM)
4458 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4459 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4461 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4462 (plus:GPR (match_dup 1) (match_dup 2)))]
4463 "s390_match_ccmode (insn, CCL1mode)"
4471 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4472 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4473 (set_attr "z10prop" "z10_super_E1,
4480 ; alr, al, aly, algr, alg
4481 (define_insn "*add<mode>3_carry2_cconly"
4482 [(set (reg CC_REGNUM)
4483 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4484 (match_operand:GPR 2 "general_operand" "d,R,T"))
4486 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4487 "s390_match_ccmode (insn, CCL1mode)"
4492 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4493 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4495 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4496 (define_insn "*add<mode>3_cc"
4497 [(set (reg CC_REGNUM)
4498 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4499 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4501 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4502 (plus:GPR (match_dup 1) (match_dup 2)))]
4503 "s390_match_ccmode (insn, CCLmode)"
4511 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4512 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4513 (set_attr "z10prop" "z10_super_E1,
4520 ; alr, al, aly, algr, alg
4521 (define_insn "*add<mode>3_cconly"
4522 [(set (reg CC_REGNUM)
4523 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4524 (match_operand:GPR 2 "general_operand" "d,R,T"))
4526 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4527 "s390_match_ccmode (insn, CCLmode)"
4532 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4533 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4535 ; alr, al, aly, algr, alg
4536 (define_insn "*add<mode>3_cconly2"
4537 [(set (reg CC_REGNUM)
4538 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4539 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
4540 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4541 "s390_match_ccmode(insn, CCLmode)"
4546 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4547 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4549 ; ahi, afi, aghi, agfi, asi, agsi
4550 (define_insn "*add<mode>3_imm_cc"
4551 [(set (reg CC_REGNUM)
4552 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0")
4553 (match_operand:GPR 2 "const_int_operand" "K,Os,C"))
4555 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS")
4556 (plus:GPR (match_dup 1) (match_dup 2)))]
4557 "s390_match_ccmode (insn, CCAmode)
4558 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4559 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4560 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
4561 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
4566 [(set_attr "op_type" "RI,RIL,SIY")
4567 (set_attr "cpu_facility" "*,extimm,z10")
4568 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4571 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4574 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4575 (define_insn "add<mode>3"
4576 [(set (match_operand:FP 0 "register_operand" "=f, f")
4577 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4578 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4579 (clobber (reg:CC CC_REGNUM))]
4582 a<xde><bt>r\t%0,<op1>%2
4584 [(set_attr "op_type" "<RRer>,RXE")
4585 (set_attr "type" "fsimp<mode>")])
4587 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4588 (define_insn "*add<mode>3_cc"
4589 [(set (reg CC_REGNUM)
4590 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4591 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4592 (match_operand:FP 3 "const0_operand" "")))
4593 (set (match_operand:FP 0 "register_operand" "=f,f")
4594 (plus:FP (match_dup 1) (match_dup 2)))]
4595 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4597 a<xde><bt>r\t%0,<op1>%2
4599 [(set_attr "op_type" "<RRer>,RXE")
4600 (set_attr "type" "fsimp<mode>")])
4602 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4603 (define_insn "*add<mode>3_cconly"
4604 [(set (reg CC_REGNUM)
4605 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4606 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4607 (match_operand:FP 3 "const0_operand" "")))
4608 (clobber (match_scratch:FP 0 "=f,f"))]
4609 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4611 a<xde><bt>r\t%0,<op1>%2
4613 [(set_attr "op_type" "<RRer>,RXE")
4614 (set_attr "type" "fsimp<mode>")])
4618 ;;- Subtract instructions.
4622 ; subti3 instruction pattern(s).
4625 (define_insn_and_split "subti3"
4626 [(set (match_operand:TI 0 "register_operand" "=&d")
4627 (minus:TI (match_operand:TI 1 "register_operand" "0")
4628 (match_operand:TI 2 "general_operand" "do") ) )
4629 (clobber (reg:CC CC_REGNUM))]
4632 "&& reload_completed"
4634 [(set (reg:CCL2 CC_REGNUM)
4635 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4637 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4639 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4640 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4641 (clobber (reg:CC CC_REGNUM))])]
4642 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4643 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4644 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4645 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4646 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4647 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4650 ; subdi3 instruction pattern(s).
4653 (define_expand "subdi3"
4655 [(set (match_operand:DI 0 "register_operand" "")
4656 (minus:DI (match_operand:DI 1 "register_operand" "")
4657 (match_operand:DI 2 "general_operand" "")))
4658 (clobber (reg:CC CC_REGNUM))])]
4662 (define_insn "*subdi3_sign"
4663 [(set (match_operand:DI 0 "register_operand" "=d,d")
4664 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4665 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4666 (clobber (reg:CC CC_REGNUM))]
4671 [(set_attr "op_type" "RRE,RXY")
4672 (set_attr "z10prop" "z10_c,*")])
4674 (define_insn "*subdi3_zero_cc"
4675 [(set (reg CC_REGNUM)
4676 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4677 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4679 (set (match_operand:DI 0 "register_operand" "=d,d")
4680 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4681 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4685 [(set_attr "op_type" "RRE,RXY")
4686 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4688 (define_insn "*subdi3_zero_cconly"
4689 [(set (reg CC_REGNUM)
4690 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4691 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4693 (clobber (match_scratch:DI 0 "=d,d"))]
4694 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4698 [(set_attr "op_type" "RRE,RXY")
4699 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4701 (define_insn "*subdi3_zero"
4702 [(set (match_operand:DI 0 "register_operand" "=d,d")
4703 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4704 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4705 (clobber (reg:CC CC_REGNUM))]
4710 [(set_attr "op_type" "RRE,RXY")
4711 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4713 (define_insn_and_split "*subdi3_31z"
4714 [(set (match_operand:DI 0 "register_operand" "=&d")
4715 (minus:DI (match_operand:DI 1 "register_operand" "0")
4716 (match_operand:DI 2 "general_operand" "do") ) )
4717 (clobber (reg:CC CC_REGNUM))]
4718 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4720 "&& reload_completed"
4722 [(set (reg:CCL2 CC_REGNUM)
4723 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4725 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4727 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4728 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4729 (clobber (reg:CC CC_REGNUM))])]
4730 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4731 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4732 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4733 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4734 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4735 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4737 (define_insn_and_split "*subdi3_31"
4738 [(set (match_operand:DI 0 "register_operand" "=&d")
4739 (minus:DI (match_operand:DI 1 "register_operand" "0")
4740 (match_operand:DI 2 "general_operand" "do") ) )
4741 (clobber (reg:CC CC_REGNUM))]
4744 "&& reload_completed"
4746 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4747 (clobber (reg:CC CC_REGNUM))])
4749 [(set (reg:CCL2 CC_REGNUM)
4750 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4752 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4754 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4756 (label_ref (match_dup 9))))
4758 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4759 (clobber (reg:CC CC_REGNUM))])
4761 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4762 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4763 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4764 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4765 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4766 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4767 operands[9] = gen_label_rtx ();")
4770 ; subsi3 instruction pattern(s).
4773 (define_expand "subsi3"
4775 [(set (match_operand:SI 0 "register_operand" "")
4776 (minus:SI (match_operand:SI 1 "register_operand" "")
4777 (match_operand:SI 2 "general_operand" "")))
4778 (clobber (reg:CC CC_REGNUM))])]
4782 (define_insn "*subsi3_sign"
4783 [(set (match_operand:SI 0 "register_operand" "=d,d")
4784 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4785 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4786 (clobber (reg:CC CC_REGNUM))]
4791 [(set_attr "op_type" "RX,RXY")])
4794 ; sub(di|si)3 instruction pattern(s).
4797 ; sr, s, sy, sgr, sg
4798 (define_insn "*sub<mode>3"
4799 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4800 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4801 (match_operand:GPR 2 "general_operand" "d,R,T") ) )
4802 (clobber (reg:CC CC_REGNUM))]
4808 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4809 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4811 ; slr, sl, sly, slgr, slg
4812 (define_insn "*sub<mode>3_borrow_cc"
4813 [(set (reg CC_REGNUM)
4814 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4815 (match_operand:GPR 2 "general_operand" "d,R,T"))
4817 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4818 (minus:GPR (match_dup 1) (match_dup 2)))]
4819 "s390_match_ccmode (insn, CCL2mode)"
4824 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4825 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4827 ; slr, sl, sly, slgr, slg
4828 (define_insn "*sub<mode>3_borrow_cconly"
4829 [(set (reg CC_REGNUM)
4830 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4831 (match_operand:GPR 2 "general_operand" "d,R,T"))
4833 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4834 "s390_match_ccmode (insn, CCL2mode)"
4839 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4840 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4842 ; slr, sl, sly, slgr, slg
4843 (define_insn "*sub<mode>3_cc"
4844 [(set (reg CC_REGNUM)
4845 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4846 (match_operand:GPR 2 "general_operand" "d,R,T"))
4848 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4849 (minus:GPR (match_dup 1) (match_dup 2)))]
4850 "s390_match_ccmode (insn, CCLmode)"
4855 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4856 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4858 ; slr, sl, sly, slgr, slg
4859 (define_insn "*sub<mode>3_cc2"
4860 [(set (reg CC_REGNUM)
4861 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4862 (match_operand:GPR 2 "general_operand" "d,R,T")))
4863 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4864 (minus:GPR (match_dup 1) (match_dup 2)))]
4865 "s390_match_ccmode (insn, CCL3mode)"
4870 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4871 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4873 ; slr, sl, sly, slgr, slg
4874 (define_insn "*sub<mode>3_cconly"
4875 [(set (reg CC_REGNUM)
4876 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4877 (match_operand:GPR 2 "general_operand" "d,R,T"))
4879 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4880 "s390_match_ccmode (insn, CCLmode)"
4885 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4886 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4889 ; slr, sl, sly, slgr, slg
4890 (define_insn "*sub<mode>3_cconly2"
4891 [(set (reg CC_REGNUM)
4892 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4893 (match_operand:GPR 2 "general_operand" "d,R,T")))
4894 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4895 "s390_match_ccmode (insn, CCL3mode)"
4900 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4901 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4905 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
4908 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4909 (define_insn "sub<mode>3"
4910 [(set (match_operand:FP 0 "register_operand" "=f, f")
4911 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
4912 (match_operand:FP 2 "general_operand" "f,<Rf>")))
4913 (clobber (reg:CC CC_REGNUM))]
4916 s<xde><bt>r\t%0,<op1>%2
4918 [(set_attr "op_type" "<RRer>,RXE")
4919 (set_attr "type" "fsimp<mode>")])
4921 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4922 (define_insn "*sub<mode>3_cc"
4923 [(set (reg CC_REGNUM)
4924 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4925 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4926 (match_operand:FP 3 "const0_operand" "")))
4927 (set (match_operand:FP 0 "register_operand" "=f,f")
4928 (minus:FP (match_dup 1) (match_dup 2)))]
4929 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4931 s<xde><bt>r\t%0,<op1>%2
4933 [(set_attr "op_type" "<RRer>,RXE")
4934 (set_attr "type" "fsimp<mode>")])
4936 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4937 (define_insn "*sub<mode>3_cconly"
4938 [(set (reg CC_REGNUM)
4939 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4940 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4941 (match_operand:FP 3 "const0_operand" "")))
4942 (clobber (match_scratch:FP 0 "=f,f"))]
4943 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4945 s<xde><bt>r\t%0,<op1>%2
4947 [(set_attr "op_type" "<RRer>,RXE")
4948 (set_attr "type" "fsimp<mode>")])
4952 ;;- Conditional add/subtract instructions.
4956 ; add(di|si)cc instruction pattern(s).
4959 ; the following 4 patterns are used when the result of an add with
4960 ; carry is checked for an overflow condition
4962 ; op1 + op2 + c < op1
4964 ; alcr, alc, alcgr, alcg
4965 (define_insn "*add<mode>3_alc_carry1_cc"
4966 [(set (reg CC_REGNUM)
4968 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4969 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4970 (match_operand:GPR 2 "general_operand" "d,RT"))
4972 (set (match_operand:GPR 0 "register_operand" "=d,d")
4973 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
4974 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4978 [(set_attr "op_type" "RRE,RXY")])
4980 ; alcr, alc, alcgr, alcg
4981 (define_insn "*add<mode>3_alc_carry1_cconly"
4982 [(set (reg CC_REGNUM)
4984 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4985 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4986 (match_operand:GPR 2 "general_operand" "d,RT"))
4988 (clobber (match_scratch:GPR 0 "=d,d"))]
4989 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4993 [(set_attr "op_type" "RRE,RXY")])
4995 ; op1 + op2 + c < op2
4997 ; alcr, alc, alcgr, alcg
4998 (define_insn "*add<mode>3_alc_carry2_cc"
4999 [(set (reg CC_REGNUM)
5001 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5002 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5003 (match_operand:GPR 2 "general_operand" "d,RT"))
5005 (set (match_operand:GPR 0 "register_operand" "=d,d")
5006 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5007 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5011 [(set_attr "op_type" "RRE,RXY")])
5013 ; alcr, alc, alcgr, alcg
5014 (define_insn "*add<mode>3_alc_carry2_cconly"
5015 [(set (reg CC_REGNUM)
5017 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5018 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5019 (match_operand:GPR 2 "general_operand" "d,RT"))
5021 (clobber (match_scratch:GPR 0 "=d,d"))]
5022 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5026 [(set_attr "op_type" "RRE,RXY")])
5028 ; alcr, alc, alcgr, alcg
5029 (define_insn "*add<mode>3_alc_cc"
5030 [(set (reg CC_REGNUM)
5032 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5033 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5034 (match_operand:GPR 2 "general_operand" "d,RT"))
5036 (set (match_operand:GPR 0 "register_operand" "=d,d")
5037 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5038 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5042 [(set_attr "op_type" "RRE,RXY")])
5044 ; alcr, alc, alcgr, alcg
5045 (define_insn "*add<mode>3_alc"
5046 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5047 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5048 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5049 (match_operand:GPR 2 "general_operand" "d,RT")))
5050 (clobber (reg:CC CC_REGNUM))]
5055 [(set_attr "op_type" "RRE,RXY")])
5057 ; slbr, slb, slbgr, slbg
5058 (define_insn "*sub<mode>3_slb_cc"
5059 [(set (reg CC_REGNUM)
5061 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5062 (match_operand:GPR 2 "general_operand" "d,RT"))
5063 (match_operand:GPR 3 "s390_slb_comparison" ""))
5065 (set (match_operand:GPR 0 "register_operand" "=d,d")
5066 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5067 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5071 [(set_attr "op_type" "RRE,RXY")
5072 (set_attr "z10prop" "z10_c,*")])
5074 ; slbr, slb, slbgr, slbg
5075 (define_insn "*sub<mode>3_slb"
5076 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5077 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5078 (match_operand:GPR 2 "general_operand" "d,RT"))
5079 (match_operand:GPR 3 "s390_slb_comparison" "")))
5080 (clobber (reg:CC CC_REGNUM))]
5085 [(set_attr "op_type" "RRE,RXY")
5086 (set_attr "z10prop" "z10_c,*")])
5088 (define_expand "add<mode>cc"
5089 [(match_operand:GPR 0 "register_operand" "")
5090 (match_operand 1 "comparison_operator" "")
5091 (match_operand:GPR 2 "register_operand" "")
5092 (match_operand:GPR 3 "const_int_operand" "")]
5094 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5095 XEXP (operands[1], 0), XEXP (operands[1], 1),
5096 operands[0], operands[2],
5097 operands[3])) FAIL; DONE;")
5100 ; scond instruction pattern(s).
5103 (define_insn_and_split "*scond<mode>"
5104 [(set (match_operand:GPR 0 "register_operand" "=&d")
5105 (match_operand:GPR 1 "s390_alc_comparison" ""))
5106 (clobber (reg:CC CC_REGNUM))]
5109 "&& reload_completed"
5110 [(set (match_dup 0) (const_int 0))
5112 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5114 (clobber (reg:CC CC_REGNUM))])]
5117 (define_insn_and_split "*scond<mode>_neg"
5118 [(set (match_operand:GPR 0 "register_operand" "=&d")
5119 (match_operand:GPR 1 "s390_slb_comparison" ""))
5120 (clobber (reg:CC CC_REGNUM))]
5123 "&& reload_completed"
5124 [(set (match_dup 0) (const_int 0))
5126 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5128 (clobber (reg:CC CC_REGNUM))])
5130 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5131 (clobber (reg:CC CC_REGNUM))])]
5135 (define_expand "cstore<mode>4"
5136 [(set (match_operand:SI 0 "register_operand" "")
5137 (match_operator:SI 1 "s390_scond_operator"
5138 [(match_operand:GPR 2 "register_operand" "")
5139 (match_operand:GPR 3 "general_operand" "")]))]
5141 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5142 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5144 (define_expand "cstorecc4"
5146 [(set (match_operand:SI 0 "register_operand" "")
5147 (match_operator:SI 1 "s390_eqne_operator"
5148 [(match_operand:CCZ1 2 "register_operand")
5149 (match_operand 3 "const0_operand")]))
5150 (clobber (reg:CC CC_REGNUM))])]
5152 "emit_insn (gen_sne (operands[0], operands[2]));
5153 if (GET_CODE (operands[1]) == EQ)
5154 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5157 (define_insn_and_split "sne"
5158 [(set (match_operand:SI 0 "register_operand" "=d")
5159 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5161 (clobber (reg:CC CC_REGNUM))]
5166 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5167 (clobber (reg:CC CC_REGNUM))])])
5171 ;;- Multiply instructions.
5175 ; muldi3 instruction pattern(s).
5178 (define_insn "*muldi3_sign"
5179 [(set (match_operand:DI 0 "register_operand" "=d,d")
5180 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5181 (match_operand:DI 1 "register_operand" "0,0")))]
5186 [(set_attr "op_type" "RRE,RXY")
5187 (set_attr "type" "imuldi")])
5189 (define_insn "muldi3"
5190 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5191 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5192 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5199 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5200 (set_attr "type" "imuldi")
5201 (set_attr "cpu_facility" "*,*,*,z10")])
5204 ; mulsi3 instruction pattern(s).
5207 (define_insn "*mulsi3_sign"
5208 [(set (match_operand:SI 0 "register_operand" "=d,d")
5209 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5210 (match_operand:SI 1 "register_operand" "0,0")))]
5215 [(set_attr "op_type" "RX,RXY")
5216 (set_attr "type" "imulhi")
5217 (set_attr "cpu_facility" "*,z10")])
5219 (define_insn "mulsi3"
5220 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5221 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5222 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5230 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5231 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5232 (set_attr "cpu_facility" "*,*,*,*,z10")])
5235 ; mulsidi3 instruction pattern(s).
5238 (define_insn "mulsidi3"
5239 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5240 (mult:DI (sign_extend:DI
5241 (match_operand:SI 1 "register_operand" "%0,0,0"))
5243 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5249 [(set_attr "op_type" "RR,RX,RXY")
5250 (set_attr "type" "imulsi")
5251 (set_attr "cpu_facility" "*,*,z10")])
5254 ; umulsidi3 instruction pattern(s).
5257 (define_insn "umulsidi3"
5258 [(set (match_operand:DI 0 "register_operand" "=d,d")
5259 (mult:DI (zero_extend:DI
5260 (match_operand:SI 1 "register_operand" "%0,0"))
5262 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
5263 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5267 [(set_attr "op_type" "RRE,RXY")
5268 (set_attr "type" "imulsi")])
5271 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5274 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5275 (define_insn "mul<mode>3"
5276 [(set (match_operand:FP 0 "register_operand" "=f,f")
5277 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5278 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5281 m<xdee><bt>r\t%0,<op1>%2
5283 [(set_attr "op_type" "<RRer>,RXE")
5284 (set_attr "type" "fmul<mode>")])
5286 ; madbr, maebr, maxb, madb, maeb
5287 (define_insn "*fmadd<mode>"
5288 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5289 (plus:DSF (mult:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5290 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5291 (match_operand:DSF 3 "register_operand" "0,0")))]
5292 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5296 [(set_attr "op_type" "RRE,RXE")
5297 (set_attr "type" "fmul<mode>")])
5299 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5300 (define_insn "*fmsub<mode>"
5301 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5302 (minus:DSF (mult:DSF (match_operand:DSF 1 "nonimmediate_operand" "f,f")
5303 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5304 (match_operand:DSF 3 "register_operand" "0,0")))]
5305 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5309 [(set_attr "op_type" "RRE,RXE")
5310 (set_attr "type" "fmul<mode>")])
5313 ;;- Divide and modulo instructions.
5317 ; divmoddi4 instruction pattern(s).
5320 (define_expand "divmoddi4"
5321 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5322 (div:DI (match_operand:DI 1 "register_operand" "")
5323 (match_operand:DI 2 "general_operand" "")))
5324 (set (match_operand:DI 3 "general_operand" "")
5325 (mod:DI (match_dup 1) (match_dup 2)))])
5326 (clobber (match_dup 4))]
5329 rtx insn, div_equal, mod_equal;
5331 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5332 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5334 operands[4] = gen_reg_rtx(TImode);
5335 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5337 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5338 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5340 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5341 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5346 (define_insn "divmodtidi3"
5347 [(set (match_operand:TI 0 "register_operand" "=d,d")
5351 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5352 (match_operand:DI 2 "general_operand" "d,RT")))
5354 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5359 [(set_attr "op_type" "RRE,RXY")
5360 (set_attr "type" "idiv")])
5362 (define_insn "divmodtisi3"
5363 [(set (match_operand:TI 0 "register_operand" "=d,d")
5367 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5369 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5372 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5377 [(set_attr "op_type" "RRE,RXY")
5378 (set_attr "type" "idiv")])
5381 ; udivmoddi4 instruction pattern(s).
5384 (define_expand "udivmoddi4"
5385 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5386 (udiv:DI (match_operand:DI 1 "general_operand" "")
5387 (match_operand:DI 2 "nonimmediate_operand" "")))
5388 (set (match_operand:DI 3 "general_operand" "")
5389 (umod:DI (match_dup 1) (match_dup 2)))])
5390 (clobber (match_dup 4))]
5393 rtx insn, div_equal, mod_equal, equal;
5395 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5396 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5397 equal = gen_rtx_IOR (TImode,
5398 gen_rtx_ASHIFT (TImode,
5399 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5401 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5403 operands[4] = gen_reg_rtx(TImode);
5404 emit_clobber (operands[4]);
5405 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5406 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5408 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5409 set_unique_reg_note (insn, REG_EQUAL, equal);
5411 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5412 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5414 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5415 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5420 (define_insn "udivmodtidi3"
5421 [(set (match_operand:TI 0 "register_operand" "=d,d")
5426 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5428 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5432 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5437 [(set_attr "op_type" "RRE,RXY")
5438 (set_attr "type" "idiv")])
5441 ; divmodsi4 instruction pattern(s).
5444 (define_expand "divmodsi4"
5445 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5446 (div:SI (match_operand:SI 1 "general_operand" "")
5447 (match_operand:SI 2 "nonimmediate_operand" "")))
5448 (set (match_operand:SI 3 "general_operand" "")
5449 (mod:SI (match_dup 1) (match_dup 2)))])
5450 (clobber (match_dup 4))]
5453 rtx insn, div_equal, mod_equal, equal;
5455 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5456 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5457 equal = gen_rtx_IOR (DImode,
5458 gen_rtx_ASHIFT (DImode,
5459 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5461 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5463 operands[4] = gen_reg_rtx(DImode);
5464 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5466 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5467 set_unique_reg_note (insn, REG_EQUAL, equal);
5469 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5470 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5472 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5473 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5478 (define_insn "divmoddisi3"
5479 [(set (match_operand:DI 0 "register_operand" "=d,d")
5484 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5486 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5490 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5495 [(set_attr "op_type" "RR,RX")
5496 (set_attr "type" "idiv")])
5499 ; udivsi3 and umodsi3 instruction pattern(s).
5502 (define_expand "udivmodsi4"
5503 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5504 (udiv:SI (match_operand:SI 1 "general_operand" "")
5505 (match_operand:SI 2 "nonimmediate_operand" "")))
5506 (set (match_operand:SI 3 "general_operand" "")
5507 (umod:SI (match_dup 1) (match_dup 2)))])
5508 (clobber (match_dup 4))]
5509 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5511 rtx insn, div_equal, mod_equal, equal;
5513 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5514 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5515 equal = gen_rtx_IOR (DImode,
5516 gen_rtx_ASHIFT (DImode,
5517 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5519 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5521 operands[4] = gen_reg_rtx(DImode);
5522 emit_clobber (operands[4]);
5523 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5524 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5526 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5527 set_unique_reg_note (insn, REG_EQUAL, equal);
5529 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5530 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5532 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5533 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5538 (define_insn "udivmoddisi3"
5539 [(set (match_operand:DI 0 "register_operand" "=d,d")
5544 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5546 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5550 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5551 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5555 [(set_attr "op_type" "RRE,RXY")
5556 (set_attr "type" "idiv")])
5558 (define_expand "udivsi3"
5559 [(set (match_operand:SI 0 "register_operand" "=d")
5560 (udiv:SI (match_operand:SI 1 "general_operand" "")
5561 (match_operand:SI 2 "general_operand" "")))
5562 (clobber (match_dup 3))]
5563 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5565 rtx insn, udiv_equal, umod_equal, equal;
5567 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5568 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5569 equal = gen_rtx_IOR (DImode,
5570 gen_rtx_ASHIFT (DImode,
5571 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5573 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5575 operands[3] = gen_reg_rtx (DImode);
5577 if (CONSTANT_P (operands[2]))
5579 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5581 rtx label1 = gen_label_rtx ();
5583 operands[1] = make_safe_from (operands[1], operands[0]);
5584 emit_move_insn (operands[0], const0_rtx);
5585 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5587 emit_move_insn (operands[0], const1_rtx);
5588 emit_label (label1);
5592 operands[2] = force_reg (SImode, operands[2]);
5593 operands[2] = make_safe_from (operands[2], operands[0]);
5595 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5596 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5598 set_unique_reg_note (insn, REG_EQUAL, equal);
5600 insn = emit_move_insn (operands[0],
5601 gen_lowpart (SImode, operands[3]));
5602 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5607 rtx label1 = gen_label_rtx ();
5608 rtx label2 = gen_label_rtx ();
5609 rtx label3 = gen_label_rtx ();
5611 operands[1] = force_reg (SImode, operands[1]);
5612 operands[1] = make_safe_from (operands[1], operands[0]);
5613 operands[2] = force_reg (SImode, operands[2]);
5614 operands[2] = make_safe_from (operands[2], operands[0]);
5616 emit_move_insn (operands[0], const0_rtx);
5617 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5619 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5621 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5623 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5624 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5626 set_unique_reg_note (insn, REG_EQUAL, equal);
5628 insn = emit_move_insn (operands[0],
5629 gen_lowpart (SImode, operands[3]));
5630 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5633 emit_label (label1);
5634 emit_move_insn (operands[0], operands[1]);
5636 emit_label (label2);
5637 emit_move_insn (operands[0], const1_rtx);
5638 emit_label (label3);
5640 emit_move_insn (operands[0], operands[0]);
5644 (define_expand "umodsi3"
5645 [(set (match_operand:SI 0 "register_operand" "=d")
5646 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5647 (match_operand:SI 2 "nonimmediate_operand" "")))
5648 (clobber (match_dup 3))]
5649 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5651 rtx insn, udiv_equal, umod_equal, equal;
5653 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5654 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5655 equal = gen_rtx_IOR (DImode,
5656 gen_rtx_ASHIFT (DImode,
5657 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5659 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5661 operands[3] = gen_reg_rtx (DImode);
5663 if (CONSTANT_P (operands[2]))
5665 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5667 rtx label1 = gen_label_rtx ();
5669 operands[1] = make_safe_from (operands[1], operands[0]);
5670 emit_move_insn (operands[0], operands[1]);
5671 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
5673 emit_insn (gen_abssi2 (operands[0], operands[2]));
5674 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5675 emit_label (label1);
5679 operands[2] = force_reg (SImode, operands[2]);
5680 operands[2] = make_safe_from (operands[2], operands[0]);
5682 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5683 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5685 set_unique_reg_note (insn, REG_EQUAL, equal);
5687 insn = emit_move_insn (operands[0],
5688 gen_highpart (SImode, operands[3]));
5689 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5694 rtx label1 = gen_label_rtx ();
5695 rtx label2 = gen_label_rtx ();
5696 rtx label3 = gen_label_rtx ();
5698 operands[1] = force_reg (SImode, operands[1]);
5699 operands[1] = make_safe_from (operands[1], operands[0]);
5700 operands[2] = force_reg (SImode, operands[2]);
5701 operands[2] = make_safe_from (operands[2], operands[0]);
5703 emit_move_insn(operands[0], operands[1]);
5704 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5706 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5708 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5710 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5711 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5713 set_unique_reg_note (insn, REG_EQUAL, equal);
5715 insn = emit_move_insn (operands[0],
5716 gen_highpart (SImode, operands[3]));
5717 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5720 emit_label (label1);
5721 emit_move_insn (operands[0], const0_rtx);
5723 emit_label (label2);
5724 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5725 emit_label (label3);
5731 ; div(df|sf)3 instruction pattern(s).
5734 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
5735 (define_insn "div<mode>3"
5736 [(set (match_operand:FP 0 "register_operand" "=f,f")
5737 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5738 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5741 d<xde><bt>r\t%0,<op1>%2
5743 [(set_attr "op_type" "<RRer>,RXE")
5744 (set_attr "type" "fdiv<mode>")])
5748 ;;- And instructions.
5751 (define_expand "and<mode>3"
5752 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5753 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5754 (match_operand:INT 2 "general_operand" "")))
5755 (clobber (reg:CC CC_REGNUM))]
5757 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5760 ; anddi3 instruction pattern(s).
5763 (define_insn "*anddi3_cc"
5764 [(set (reg CC_REGNUM)
5765 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5766 (match_operand:DI 2 "general_operand" "d,RT"))
5768 (set (match_operand:DI 0 "register_operand" "=d,d")
5769 (and:DI (match_dup 1) (match_dup 2)))]
5770 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5774 [(set_attr "op_type" "RRE,RXY")
5775 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5777 (define_insn "*anddi3_cconly"
5778 [(set (reg CC_REGNUM)
5779 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5780 (match_operand:DI 2 "general_operand" "d,RT"))
5782 (clobber (match_scratch:DI 0 "=d,d"))]
5783 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5784 /* Do not steal TM patterns. */
5785 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5789 [(set_attr "op_type" "RRE,RXY")
5790 (set_attr "z10prop" "z10_super_E1, z10_super_E1")])
5792 (define_insn "*anddi3"
5793 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5794 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5795 "%d,o,0,0,0,0,0,0,0,0,0,0")
5796 (match_operand:DI 2 "general_operand"
5797 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
5798 (clobber (reg:CC CC_REGNUM))]
5799 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5813 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
5814 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*")
5815 (set_attr "z10prop" "*,
5829 [(set (match_operand:DI 0 "s_operand" "")
5830 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5831 (clobber (reg:CC CC_REGNUM))]
5834 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5835 (clobber (reg:CC CC_REGNUM))])]
5836 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5840 ; andsi3 instruction pattern(s).
5843 (define_insn "*andsi3_cc"
5844 [(set (reg CC_REGNUM)
5845 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5846 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5848 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5849 (and:SI (match_dup 1) (match_dup 2)))]
5850 "s390_match_ccmode(insn, CCTmode)"
5856 [(set_attr "op_type" "RIL,RR,RX,RXY")
5857 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5859 (define_insn "*andsi3_cconly"
5860 [(set (reg CC_REGNUM)
5861 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5862 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5864 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5865 "s390_match_ccmode(insn, CCTmode)
5866 /* Do not steal TM patterns. */
5867 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5873 [(set_attr "op_type" "RIL,RR,RX,RXY")
5874 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5876 (define_insn "*andsi3_zarch"
5877 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5878 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5879 "%d,o,0,0,0,0,0,0,0,0")
5880 (match_operand:SI 2 "general_operand"
5881 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5882 (clobber (reg:CC CC_REGNUM))]
5883 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5895 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")
5896 (set_attr "z10prop" "*,
5907 (define_insn "*andsi3_esa"
5908 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5909 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5910 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5911 (clobber (reg:CC CC_REGNUM))]
5912 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5918 [(set_attr "op_type" "RR,RX,SI,SS")
5919 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
5923 [(set (match_operand:SI 0 "s_operand" "")
5924 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5925 (clobber (reg:CC CC_REGNUM))]
5928 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5929 (clobber (reg:CC CC_REGNUM))])]
5930 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5933 ; andhi3 instruction pattern(s).
5936 (define_insn "*andhi3_zarch"
5937 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5938 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5939 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5940 (clobber (reg:CC CC_REGNUM))]
5941 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5947 [(set_attr "op_type" "RR,RI,SI,SS")
5948 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")
5951 (define_insn "*andhi3_esa"
5952 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5953 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5954 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5955 (clobber (reg:CC CC_REGNUM))]
5956 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5961 [(set_attr "op_type" "RR,SI,SS")
5962 (set_attr "z10prop" "z10_super_E1,*,*")
5966 [(set (match_operand:HI 0 "s_operand" "")
5967 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5968 (clobber (reg:CC CC_REGNUM))]
5971 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5972 (clobber (reg:CC CC_REGNUM))])]
5973 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5976 ; andqi3 instruction pattern(s).
5979 (define_insn "*andqi3_zarch"
5980 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5981 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5982 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5983 (clobber (reg:CC CC_REGNUM))]
5984 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5991 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
5992 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
5994 (define_insn "*andqi3_esa"
5995 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5996 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5997 (match_operand:QI 2 "general_operand" "d,n,Q")))
5998 (clobber (reg:CC CC_REGNUM))]
5999 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6004 [(set_attr "op_type" "RR,SI,SS")
6005 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6008 ; Block and (NC) patterns.
6012 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6013 (and:BLK (match_dup 0)
6014 (match_operand:BLK 1 "memory_operand" "Q")))
6015 (use (match_operand 2 "const_int_operand" "n"))
6016 (clobber (reg:CC CC_REGNUM))]
6017 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6018 "nc\t%O0(%2,%R0),%S1"
6019 [(set_attr "op_type" "SS")])
6022 [(set (match_operand 0 "memory_operand" "")
6024 (match_operand 1 "memory_operand" "")))
6025 (clobber (reg:CC CC_REGNUM))]
6027 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6028 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6030 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6032 (clobber (reg:CC CC_REGNUM))])]
6034 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6035 operands[0] = adjust_address (operands[0], BLKmode, 0);
6036 operands[1] = adjust_address (operands[1], BLKmode, 0);
6041 [(set (match_operand:BLK 0 "memory_operand" "")
6042 (and:BLK (match_dup 0)
6043 (match_operand:BLK 1 "memory_operand" "")))
6044 (use (match_operand 2 "const_int_operand" ""))
6045 (clobber (reg:CC CC_REGNUM))])
6047 [(set (match_operand:BLK 3 "memory_operand" "")
6048 (and:BLK (match_dup 3)
6049 (match_operand:BLK 4 "memory_operand" "")))
6050 (use (match_operand 5 "const_int_operand" ""))
6051 (clobber (reg:CC CC_REGNUM))])]
6052 "s390_offset_p (operands[0], operands[3], operands[2])
6053 && s390_offset_p (operands[1], operands[4], operands[2])
6054 && !s390_overlap_p (operands[0], operands[1],
6055 INTVAL (operands[2]) + INTVAL (operands[5]))
6056 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6058 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6060 (clobber (reg:CC CC_REGNUM))])]
6061 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6062 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6063 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6067 ;;- Bit set (inclusive or) instructions.
6070 (define_expand "ior<mode>3"
6071 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6072 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6073 (match_operand:INT 2 "general_operand" "")))
6074 (clobber (reg:CC CC_REGNUM))]
6076 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6079 ; iordi3 instruction pattern(s).
6082 (define_insn "*iordi3_cc"
6083 [(set (reg CC_REGNUM)
6084 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6085 (match_operand:DI 2 "general_operand" "d,RT"))
6087 (set (match_operand:DI 0 "register_operand" "=d,d")
6088 (ior:DI (match_dup 1) (match_dup 2)))]
6089 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6093 [(set_attr "op_type" "RRE,RXY")
6094 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6096 (define_insn "*iordi3_cconly"
6097 [(set (reg CC_REGNUM)
6098 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6099 (match_operand:DI 2 "general_operand" "d,RT"))
6101 (clobber (match_scratch:DI 0 "=d,d"))]
6102 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6106 [(set_attr "op_type" "RRE,RXY")
6107 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6109 (define_insn "*iordi3"
6110 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
6111 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
6112 (match_operand:DI 2 "general_operand"
6113 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
6114 (clobber (reg:CC CC_REGNUM))]
6115 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
6127 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
6128 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*")
6129 (set_attr "z10prop" "z10_super_E1,
6141 [(set (match_operand:DI 0 "s_operand" "")
6142 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6143 (clobber (reg:CC CC_REGNUM))]
6146 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6147 (clobber (reg:CC CC_REGNUM))])]
6148 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6151 ; iorsi3 instruction pattern(s).
6154 (define_insn "*iorsi3_cc"
6155 [(set (reg CC_REGNUM)
6156 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6157 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6159 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6160 (ior:SI (match_dup 1) (match_dup 2)))]
6161 "s390_match_ccmode(insn, CCTmode)"
6167 [(set_attr "op_type" "RIL,RR,RX,RXY")
6168 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6170 (define_insn "*iorsi3_cconly"
6171 [(set (reg CC_REGNUM)
6172 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6173 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6175 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6176 "s390_match_ccmode(insn, CCTmode)"
6182 [(set_attr "op_type" "RIL,RR,RX,RXY")
6183 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6185 (define_insn "*iorsi3_zarch"
6186 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
6187 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
6188 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
6189 (clobber (reg:CC CC_REGNUM))]
6190 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6200 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")
6201 (set_attr "z10prop" "z10_super_E1,
6210 (define_insn "*iorsi3_esa"
6211 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6212 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6213 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6214 (clobber (reg:CC CC_REGNUM))]
6215 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6221 [(set_attr "op_type" "RR,RX,SI,SS")
6222 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6225 [(set (match_operand:SI 0 "s_operand" "")
6226 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6227 (clobber (reg:CC CC_REGNUM))]
6230 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6231 (clobber (reg:CC CC_REGNUM))])]
6232 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6235 ; iorhi3 instruction pattern(s).
6238 (define_insn "*iorhi3_zarch"
6239 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6240 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6241 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
6242 (clobber (reg:CC CC_REGNUM))]
6243 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6249 [(set_attr "op_type" "RR,RI,SI,SS")
6250 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6252 (define_insn "*iorhi3_esa"
6253 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6254 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6255 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6256 (clobber (reg:CC CC_REGNUM))]
6257 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6262 [(set_attr "op_type" "RR,SI,SS")
6263 (set_attr "z10prop" "z10_super_E1,*,*")])
6266 [(set (match_operand:HI 0 "s_operand" "")
6267 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6268 (clobber (reg:CC CC_REGNUM))]
6271 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6272 (clobber (reg:CC CC_REGNUM))])]
6273 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6276 ; iorqi3 instruction pattern(s).
6279 (define_insn "*iorqi3_zarch"
6280 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6281 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6282 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
6283 (clobber (reg:CC CC_REGNUM))]
6284 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6291 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
6292 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6294 (define_insn "*iorqi3_esa"
6295 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6296 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6297 (match_operand:QI 2 "general_operand" "d,n,Q")))
6298 (clobber (reg:CC CC_REGNUM))]
6299 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6304 [(set_attr "op_type" "RR,SI,SS")
6305 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6308 ; Block inclusive or (OC) patterns.
6312 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6313 (ior:BLK (match_dup 0)
6314 (match_operand:BLK 1 "memory_operand" "Q")))
6315 (use (match_operand 2 "const_int_operand" "n"))
6316 (clobber (reg:CC CC_REGNUM))]
6317 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6318 "oc\t%O0(%2,%R0),%S1"
6319 [(set_attr "op_type" "SS")])
6322 [(set (match_operand 0 "memory_operand" "")
6324 (match_operand 1 "memory_operand" "")))
6325 (clobber (reg:CC CC_REGNUM))]
6327 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6328 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6330 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6332 (clobber (reg:CC CC_REGNUM))])]
6334 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6335 operands[0] = adjust_address (operands[0], BLKmode, 0);
6336 operands[1] = adjust_address (operands[1], BLKmode, 0);
6341 [(set (match_operand:BLK 0 "memory_operand" "")
6342 (ior:BLK (match_dup 0)
6343 (match_operand:BLK 1 "memory_operand" "")))
6344 (use (match_operand 2 "const_int_operand" ""))
6345 (clobber (reg:CC CC_REGNUM))])
6347 [(set (match_operand:BLK 3 "memory_operand" "")
6348 (ior:BLK (match_dup 3)
6349 (match_operand:BLK 4 "memory_operand" "")))
6350 (use (match_operand 5 "const_int_operand" ""))
6351 (clobber (reg:CC CC_REGNUM))])]
6352 "s390_offset_p (operands[0], operands[3], operands[2])
6353 && s390_offset_p (operands[1], operands[4], operands[2])
6354 && !s390_overlap_p (operands[0], operands[1],
6355 INTVAL (operands[2]) + INTVAL (operands[5]))
6356 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6358 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6360 (clobber (reg:CC CC_REGNUM))])]
6361 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6362 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6363 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6367 ;;- Xor instructions.
6370 (define_expand "xor<mode>3"
6371 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6372 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6373 (match_operand:INT 2 "general_operand" "")))
6374 (clobber (reg:CC CC_REGNUM))]
6376 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6379 ; xordi3 instruction pattern(s).
6382 (define_insn "*xordi3_cc"
6383 [(set (reg CC_REGNUM)
6384 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6385 (match_operand:DI 2 "general_operand" "d,RT"))
6387 (set (match_operand:DI 0 "register_operand" "=d,d")
6388 (xor:DI (match_dup 1) (match_dup 2)))]
6389 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6393 [(set_attr "op_type" "RRE,RXY")
6394 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6396 (define_insn "*xordi3_cconly"
6397 [(set (reg CC_REGNUM)
6398 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6399 (match_operand:DI 2 "general_operand" "d,RT"))
6401 (clobber (match_scratch:DI 0 "=d,d"))]
6402 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6406 [(set_attr "op_type" "RRE,RXY")
6407 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6409 (define_insn "*xordi3"
6410 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6411 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6412 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
6413 (clobber (reg:CC CC_REGNUM))]
6414 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
6422 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")
6423 (set_attr "cpu_facility" "extimm,extimm,*,*,*,*")
6424 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6427 [(set (match_operand:DI 0 "s_operand" "")
6428 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6429 (clobber (reg:CC CC_REGNUM))]
6432 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6433 (clobber (reg:CC CC_REGNUM))])]
6434 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6437 ; xorsi3 instruction pattern(s).
6440 (define_insn "*xorsi3_cc"
6441 [(set (reg CC_REGNUM)
6442 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6443 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6445 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6446 (xor:SI (match_dup 1) (match_dup 2)))]
6447 "s390_match_ccmode(insn, CCTmode)"
6453 [(set_attr "op_type" "RIL,RR,RX,RXY")
6454 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6456 (define_insn "*xorsi3_cconly"
6457 [(set (reg CC_REGNUM)
6458 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6459 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6461 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6462 "s390_match_ccmode(insn, CCTmode)"
6468 [(set_attr "op_type" "RIL,RR,RX,RXY")
6469 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6471 (define_insn "*xorsi3"
6472 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6473 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6474 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
6475 (clobber (reg:CC CC_REGNUM))]
6476 "s390_logical_operator_ok_p (operands)"
6484 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")
6485 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6488 [(set (match_operand:SI 0 "s_operand" "")
6489 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6490 (clobber (reg:CC CC_REGNUM))]
6493 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6494 (clobber (reg:CC CC_REGNUM))])]
6495 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6498 ; xorhi3 instruction pattern(s).
6501 (define_insn "*xorhi3"
6502 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6503 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6504 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
6505 (clobber (reg:CC CC_REGNUM))]
6506 "s390_logical_operator_ok_p (operands)"
6512 [(set_attr "op_type" "RIL,RR,SI,SS")
6513 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6516 [(set (match_operand:HI 0 "s_operand" "")
6517 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6518 (clobber (reg:CC CC_REGNUM))]
6521 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6522 (clobber (reg:CC CC_REGNUM))])]
6523 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6526 ; xorqi3 instruction pattern(s).
6529 (define_insn "*xorqi3"
6530 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6531 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6532 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
6533 (clobber (reg:CC CC_REGNUM))]
6534 "s390_logical_operator_ok_p (operands)"
6541 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")
6542 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6546 ; Block exclusive or (XC) patterns.
6550 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6551 (xor:BLK (match_dup 0)
6552 (match_operand:BLK 1 "memory_operand" "Q")))
6553 (use (match_operand 2 "const_int_operand" "n"))
6554 (clobber (reg:CC CC_REGNUM))]
6555 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6556 "xc\t%O0(%2,%R0),%S1"
6557 [(set_attr "op_type" "SS")])
6560 [(set (match_operand 0 "memory_operand" "")
6562 (match_operand 1 "memory_operand" "")))
6563 (clobber (reg:CC CC_REGNUM))]
6565 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6566 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6568 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6570 (clobber (reg:CC CC_REGNUM))])]
6572 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6573 operands[0] = adjust_address (operands[0], BLKmode, 0);
6574 operands[1] = adjust_address (operands[1], BLKmode, 0);
6579 [(set (match_operand:BLK 0 "memory_operand" "")
6580 (xor:BLK (match_dup 0)
6581 (match_operand:BLK 1 "memory_operand" "")))
6582 (use (match_operand 2 "const_int_operand" ""))
6583 (clobber (reg:CC CC_REGNUM))])
6585 [(set (match_operand:BLK 3 "memory_operand" "")
6586 (xor:BLK (match_dup 3)
6587 (match_operand:BLK 4 "memory_operand" "")))
6588 (use (match_operand 5 "const_int_operand" ""))
6589 (clobber (reg:CC CC_REGNUM))])]
6590 "s390_offset_p (operands[0], operands[3], operands[2])
6591 && s390_offset_p (operands[1], operands[4], operands[2])
6592 && !s390_overlap_p (operands[0], operands[1],
6593 INTVAL (operands[2]) + INTVAL (operands[5]))
6594 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6596 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6598 (clobber (reg:CC CC_REGNUM))])]
6599 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6600 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6601 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6604 ; Block xor (XC) patterns with src == dest.
6607 (define_insn "*xc_zero"
6608 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6610 (use (match_operand 1 "const_int_operand" "n"))
6611 (clobber (reg:CC CC_REGNUM))]
6612 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6613 "xc\t%O0(%1,%R0),%S0"
6614 [(set_attr "op_type" "SS")])
6618 [(set (match_operand:BLK 0 "memory_operand" "")
6620 (use (match_operand 1 "const_int_operand" ""))
6621 (clobber (reg:CC CC_REGNUM))])
6623 [(set (match_operand:BLK 2 "memory_operand" "")
6625 (use (match_operand 3 "const_int_operand" ""))
6626 (clobber (reg:CC CC_REGNUM))])]
6627 "s390_offset_p (operands[0], operands[2], operands[1])
6628 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6630 [(set (match_dup 4) (const_int 0))
6632 (clobber (reg:CC CC_REGNUM))])]
6633 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6634 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6638 ;;- Negate instructions.
6642 ; neg(di|si)2 instruction pattern(s).
6645 (define_expand "neg<mode>2"
6647 [(set (match_operand:DSI 0 "register_operand" "=d")
6648 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
6649 (clobber (reg:CC CC_REGNUM))])]
6653 (define_insn "*negdi2_sign_cc"
6654 [(set (reg CC_REGNUM)
6655 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6656 (match_operand:SI 1 "register_operand" "d") 0)
6657 (const_int 32)) (const_int 32)))
6659 (set (match_operand:DI 0 "register_operand" "=d")
6660 (neg:DI (sign_extend:DI (match_dup 1))))]
6661 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6663 [(set_attr "op_type" "RRE")
6664 (set_attr "z10prop" "z10_c")])
6666 (define_insn "*negdi2_sign"
6667 [(set (match_operand:DI 0 "register_operand" "=d")
6668 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6669 (clobber (reg:CC CC_REGNUM))]
6672 [(set_attr "op_type" "RRE")
6673 (set_attr "z10prop" "z10_c")])
6676 (define_insn "*neg<mode>2_cc"
6677 [(set (reg CC_REGNUM)
6678 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6680 (set (match_operand:GPR 0 "register_operand" "=d")
6681 (neg:GPR (match_dup 1)))]
6682 "s390_match_ccmode (insn, CCAmode)"
6684 [(set_attr "op_type" "RR<E>")
6685 (set_attr "z10prop" "z10_super_c_E1")])
6688 (define_insn "*neg<mode>2_cconly"
6689 [(set (reg CC_REGNUM)
6690 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6692 (clobber (match_scratch:GPR 0 "=d"))]
6693 "s390_match_ccmode (insn, CCAmode)"
6695 [(set_attr "op_type" "RR<E>")
6696 (set_attr "z10prop" "z10_super_c_E1")])
6699 (define_insn "*neg<mode>2"
6700 [(set (match_operand:GPR 0 "register_operand" "=d")
6701 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
6702 (clobber (reg:CC CC_REGNUM))]
6705 [(set_attr "op_type" "RR<E>")
6706 (set_attr "z10prop" "z10_super_c_E1")])
6708 (define_insn_and_split "*negdi2_31"
6709 [(set (match_operand:DI 0 "register_operand" "=d")
6710 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6711 (clobber (reg:CC CC_REGNUM))]
6714 "&& reload_completed"
6716 [(set (match_dup 2) (neg:SI (match_dup 3)))
6717 (clobber (reg:CC CC_REGNUM))])
6719 [(set (reg:CCAP CC_REGNUM)
6720 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
6721 (set (match_dup 4) (neg:SI (match_dup 5)))])
6723 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
6725 (label_ref (match_dup 6))))
6727 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6728 (clobber (reg:CC CC_REGNUM))])
6730 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6731 operands[3] = operand_subword (operands[1], 0, 0, DImode);
6732 operands[4] = operand_subword (operands[0], 1, 0, DImode);
6733 operands[5] = operand_subword (operands[1], 1, 0, DImode);
6734 operands[6] = gen_label_rtx ();")
6737 ; neg(df|sf)2 instruction pattern(s).
6740 (define_expand "neg<mode>2"
6742 [(set (match_operand:BFP 0 "register_operand" "=f")
6743 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6744 (clobber (reg:CC CC_REGNUM))])]
6748 ; lcxbr, lcdbr, lcebr
6749 (define_insn "*neg<mode>2_cc"
6750 [(set (reg CC_REGNUM)
6751 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6752 (match_operand:BFP 2 "const0_operand" "")))
6753 (set (match_operand:BFP 0 "register_operand" "=f")
6754 (neg:BFP (match_dup 1)))]
6755 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6757 [(set_attr "op_type" "RRE")
6758 (set_attr "type" "fsimp<mode>")])
6760 ; lcxbr, lcdbr, lcebr
6761 (define_insn "*neg<mode>2_cconly"
6762 [(set (reg CC_REGNUM)
6763 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6764 (match_operand:BFP 2 "const0_operand" "")))
6765 (clobber (match_scratch:BFP 0 "=f"))]
6766 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6768 [(set_attr "op_type" "RRE")
6769 (set_attr "type" "fsimp<mode>")])
6772 (define_insn "*neg<mode>2_nocc"
6773 [(set (match_operand:FP 0 "register_operand" "=f")
6774 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6777 [(set_attr "op_type" "RRE")
6778 (set_attr "type" "fsimp<mode>")])
6780 ; lcxbr, lcdbr, lcebr
6781 (define_insn "*neg<mode>2"
6782 [(set (match_operand:BFP 0 "register_operand" "=f")
6783 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6784 (clobber (reg:CC CC_REGNUM))]
6787 [(set_attr "op_type" "RRE")
6788 (set_attr "type" "fsimp<mode>")])
6792 ;;- Absolute value instructions.
6796 ; abs(di|si)2 instruction pattern(s).
6799 (define_insn "*absdi2_sign_cc"
6800 [(set (reg CC_REGNUM)
6801 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6802 (match_operand:SI 1 "register_operand" "d") 0)
6803 (const_int 32)) (const_int 32)))
6805 (set (match_operand:DI 0 "register_operand" "=d")
6806 (abs:DI (sign_extend:DI (match_dup 1))))]
6807 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6809 [(set_attr "op_type" "RRE")
6810 (set_attr "z10prop" "z10_c")])
6812 (define_insn "*absdi2_sign"
6813 [(set (match_operand:DI 0 "register_operand" "=d")
6814 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6815 (clobber (reg:CC CC_REGNUM))]
6818 [(set_attr "op_type" "RRE")
6819 (set_attr "z10prop" "z10_c")])
6822 (define_insn "*abs<mode>2_cc"
6823 [(set (reg CC_REGNUM)
6824 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6826 (set (match_operand:GPR 0 "register_operand" "=d")
6827 (abs:GPR (match_dup 1)))]
6828 "s390_match_ccmode (insn, CCAmode)"
6830 [(set_attr "op_type" "RR<E>")
6831 (set_attr "z10prop" "z10_c")])
6834 (define_insn "*abs<mode>2_cconly"
6835 [(set (reg CC_REGNUM)
6836 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6838 (clobber (match_scratch:GPR 0 "=d"))]
6839 "s390_match_ccmode (insn, CCAmode)"
6841 [(set_attr "op_type" "RR<E>")
6842 (set_attr "z10prop" "z10_c")])
6845 (define_insn "abs<mode>2"
6846 [(set (match_operand:GPR 0 "register_operand" "=d")
6847 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6848 (clobber (reg:CC CC_REGNUM))]
6851 [(set_attr "op_type" "RR<E>")
6852 (set_attr "z10prop" "z10_c")])
6855 ; abs(df|sf)2 instruction pattern(s).
6858 (define_expand "abs<mode>2"
6860 [(set (match_operand:BFP 0 "register_operand" "=f")
6861 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6862 (clobber (reg:CC CC_REGNUM))])]
6866 ; lpxbr, lpdbr, lpebr
6867 (define_insn "*abs<mode>2_cc"
6868 [(set (reg CC_REGNUM)
6869 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6870 (match_operand:BFP 2 "const0_operand" "")))
6871 (set (match_operand:BFP 0 "register_operand" "=f")
6872 (abs:BFP (match_dup 1)))]
6873 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6875 [(set_attr "op_type" "RRE")
6876 (set_attr "type" "fsimp<mode>")])
6878 ; lpxbr, lpdbr, lpebr
6879 (define_insn "*abs<mode>2_cconly"
6880 [(set (reg CC_REGNUM)
6881 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6882 (match_operand:BFP 2 "const0_operand" "")))
6883 (clobber (match_scratch:BFP 0 "=f"))]
6884 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6886 [(set_attr "op_type" "RRE")
6887 (set_attr "type" "fsimp<mode>")])
6890 (define_insn "*abs<mode>2_nocc"
6891 [(set (match_operand:FP 0 "register_operand" "=f")
6892 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6895 [(set_attr "op_type" "RRE")
6896 (set_attr "type" "fsimp<mode>")])
6898 ; lpxbr, lpdbr, lpebr
6899 (define_insn "*abs<mode>2"
6900 [(set (match_operand:BFP 0 "register_operand" "=f")
6901 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6902 (clobber (reg:CC CC_REGNUM))]
6905 [(set_attr "op_type" "RRE")
6906 (set_attr "type" "fsimp<mode>")])
6910 ;;- Negated absolute value instructions
6917 (define_insn "*negabsdi2_sign_cc"
6918 [(set (reg CC_REGNUM)
6919 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6920 (match_operand:SI 1 "register_operand" "d") 0)
6921 (const_int 32)) (const_int 32))))
6923 (set (match_operand:DI 0 "register_operand" "=d")
6924 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6925 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6927 [(set_attr "op_type" "RRE")
6928 (set_attr "z10prop" "z10_c")])
6930 (define_insn "*negabsdi2_sign"
6931 [(set (match_operand:DI 0 "register_operand" "=d")
6932 (neg:DI (abs:DI (sign_extend:DI
6933 (match_operand:SI 1 "register_operand" "d")))))
6934 (clobber (reg:CC CC_REGNUM))]
6937 [(set_attr "op_type" "RRE")
6938 (set_attr "z10prop" "z10_c")])
6941 (define_insn "*negabs<mode>2_cc"
6942 [(set (reg CC_REGNUM)
6943 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6945 (set (match_operand:GPR 0 "register_operand" "=d")
6946 (neg:GPR (abs:GPR (match_dup 1))))]
6947 "s390_match_ccmode (insn, CCAmode)"
6949 [(set_attr "op_type" "RR<E>")
6950 (set_attr "z10prop" "z10_c")])
6953 (define_insn "*negabs<mode>2_cconly"
6954 [(set (reg CC_REGNUM)
6955 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6957 (clobber (match_scratch:GPR 0 "=d"))]
6958 "s390_match_ccmode (insn, CCAmode)"
6960 [(set_attr "op_type" "RR<E>")
6961 (set_attr "z10prop" "z10_c")])
6964 (define_insn "*negabs<mode>2"
6965 [(set (match_operand:GPR 0 "register_operand" "=d")
6966 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6967 (clobber (reg:CC CC_REGNUM))]
6970 [(set_attr "op_type" "RR<E>")
6971 (set_attr "z10prop" "z10_c")])
6977 ; lnxbr, lndbr, lnebr
6978 (define_insn "*negabs<mode>2_cc"
6979 [(set (reg CC_REGNUM)
6980 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6981 (match_operand:BFP 2 "const0_operand" "")))
6982 (set (match_operand:BFP 0 "register_operand" "=f")
6983 (neg:BFP (abs:BFP (match_dup 1))))]
6984 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6986 [(set_attr "op_type" "RRE")
6987 (set_attr "type" "fsimp<mode>")])
6989 ; lnxbr, lndbr, lnebr
6990 (define_insn "*negabs<mode>2_cconly"
6991 [(set (reg CC_REGNUM)
6992 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6993 (match_operand:BFP 2 "const0_operand" "")))
6994 (clobber (match_scratch:BFP 0 "=f"))]
6995 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6997 [(set_attr "op_type" "RRE")
6998 (set_attr "type" "fsimp<mode>")])
7001 (define_insn "*negabs<mode>2_nocc"
7002 [(set (match_operand:FP 0 "register_operand" "=f")
7003 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7006 [(set_attr "op_type" "RRE")
7007 (set_attr "type" "fsimp<mode>")])
7009 ; lnxbr, lndbr, lnebr
7010 (define_insn "*negabs<mode>2"
7011 [(set (match_operand:BFP 0 "register_operand" "=f")
7012 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7013 (clobber (reg:CC CC_REGNUM))]
7016 [(set_attr "op_type" "RRE")
7017 (set_attr "type" "fsimp<mode>")])
7020 ;;- Copy sign instructions
7024 (define_insn "copysign<mode>3"
7025 [(set (match_operand:FP 0 "register_operand" "=f")
7026 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
7027 (match_operand:FP 2 "register_operand" "f")]
7031 [(set_attr "op_type" "RRF")
7032 (set_attr "type" "fsimp<mode>")])
7035 ;;- Square root instructions.
7039 ; sqrt(df|sf)2 instruction pattern(s).
7042 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7043 (define_insn "sqrt<mode>2"
7044 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7045 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7050 [(set_attr "op_type" "RRE,RXE")
7051 (set_attr "type" "fsqrt<mode>")])
7055 ;;- One complement instructions.
7059 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7062 (define_expand "one_cmpl<mode>2"
7064 [(set (match_operand:INT 0 "register_operand" "")
7065 (xor:INT (match_operand:INT 1 "register_operand" "")
7067 (clobber (reg:CC CC_REGNUM))])]
7073 ;; Find leftmost bit instructions.
7076 (define_expand "clzdi2"
7077 [(set (match_operand:DI 0 "register_operand" "=d")
7078 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7079 "TARGET_EXTIMM && TARGET_64BIT"
7081 rtx insn, clz_equal;
7082 rtx wide_reg = gen_reg_rtx (TImode);
7083 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7085 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7087 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7089 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7090 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7095 (define_insn "clztidi2"
7096 [(set (match_operand:TI 0 "register_operand" "=d")
7100 (xor:DI (match_operand:DI 1 "register_operand" "d")
7101 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7102 (subreg:SI (clz:DI (match_dup 1)) 4))))
7105 (zero_extend:TI (clz:DI (match_dup 1)))))
7106 (clobber (reg:CC CC_REGNUM))]
7107 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7108 == (unsigned HOST_WIDE_INT) 1 << 63
7109 && TARGET_EXTIMM && TARGET_64BIT"
7111 [(set_attr "op_type" "RRE")])
7115 ;;- Rotate instructions.
7119 ; rotl(di|si)3 instruction pattern(s).
7123 (define_insn "rotl<mode>3"
7124 [(set (match_operand:GPR 0 "register_operand" "=d")
7125 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7126 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7129 [(set_attr "op_type" "RSE")
7130 (set_attr "atype" "reg")
7131 (set_attr "z10prop" "z10_super_E1")])
7134 (define_insn "*rotl<mode>3_and"
7135 [(set (match_operand:GPR 0 "register_operand" "=d")
7136 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7137 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7138 (match_operand:SI 3 "const_int_operand" "n"))))]
7139 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7141 [(set_attr "op_type" "RSE")
7142 (set_attr "atype" "reg")
7143 (set_attr "z10prop" "z10_super_E1")])
7147 ;;- Shift instructions.
7151 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7154 (define_expand "<shift><mode>3"
7155 [(set (match_operand:DSI 0 "register_operand" "")
7156 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7157 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7162 (define_insn "*<shift>di3_31"
7163 [(set (match_operand:DI 0 "register_operand" "=d")
7164 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7165 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7168 [(set_attr "op_type" "RS")
7169 (set_attr "atype" "reg")])
7171 ; sll, srl, sllg, srlg
7172 (define_insn "*<shift><mode>3"
7173 [(set (match_operand:GPR 0 "register_operand" "=d")
7174 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7175 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7177 "s<lr>l<g>\t%0,<1>%Y2"
7178 [(set_attr "op_type" "RS<E>")
7179 (set_attr "atype" "reg")
7180 (set_attr "z10prop" "z10_super_E1")])
7183 (define_insn "*<shift>di3_31_and"
7184 [(set (match_operand:DI 0 "register_operand" "=d")
7185 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7186 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7187 (match_operand:SI 3 "const_int_operand" "n"))))]
7188 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
7190 [(set_attr "op_type" "RS")
7191 (set_attr "atype" "reg")])
7193 ; sll, srl, sllg, srlg
7194 (define_insn "*<shift><mode>3_and"
7195 [(set (match_operand:GPR 0 "register_operand" "=d")
7196 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7197 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7198 (match_operand:SI 3 "const_int_operand" "n"))))]
7199 "(INTVAL (operands[3]) & 63) == 63"
7200 "s<lr>l<g>\t%0,<1>%Y2"
7201 [(set_attr "op_type" "RS<E>")
7202 (set_attr "atype" "reg")
7203 (set_attr "z10prop" "z10_super_E1")])
7206 ; ashr(di|si)3 instruction pattern(s).
7209 (define_expand "ashr<mode>3"
7211 [(set (match_operand:DSI 0 "register_operand" "")
7212 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7213 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7214 (clobber (reg:CC CC_REGNUM))])]
7218 (define_insn "*ashrdi3_cc_31"
7219 [(set (reg CC_REGNUM)
7220 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7221 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7223 (set (match_operand:DI 0 "register_operand" "=d")
7224 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7225 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
7227 [(set_attr "op_type" "RS")
7228 (set_attr "atype" "reg")])
7230 (define_insn "*ashrdi3_cconly_31"
7231 [(set (reg CC_REGNUM)
7232 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7233 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7235 (clobber (match_scratch:DI 0 "=d"))]
7236 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
7238 [(set_attr "op_type" "RS")
7239 (set_attr "atype" "reg")])
7241 (define_insn "*ashrdi3_31"
7242 [(set (match_operand:DI 0 "register_operand" "=d")
7243 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7244 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7245 (clobber (reg:CC CC_REGNUM))]
7248 [(set_attr "op_type" "RS")
7249 (set_attr "atype" "reg")])
7252 (define_insn "*ashr<mode>3_cc"
7253 [(set (reg CC_REGNUM)
7254 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7255 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7257 (set (match_operand:GPR 0 "register_operand" "=d")
7258 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7259 "s390_match_ccmode(insn, CCSmode)"
7261 [(set_attr "op_type" "RS<E>")
7262 (set_attr "atype" "reg")
7263 (set_attr "z10prop" "z10_super_E1")])
7266 (define_insn "*ashr<mode>3_cconly"
7267 [(set (reg CC_REGNUM)
7268 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7269 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7271 (clobber (match_scratch:GPR 0 "=d"))]
7272 "s390_match_ccmode(insn, CCSmode)"
7274 [(set_attr "op_type" "RS<E>")
7275 (set_attr "atype" "reg")
7276 (set_attr "z10prop" "z10_super_E1")])
7279 (define_insn "*ashr<mode>3"
7280 [(set (match_operand:GPR 0 "register_operand" "=d")
7281 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7282 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7283 (clobber (reg:CC CC_REGNUM))]
7286 [(set_attr "op_type" "RS<E>")
7287 (set_attr "atype" "reg")
7288 (set_attr "z10prop" "z10_super_E1")])
7291 ; shift pattern with implicit ANDs
7293 (define_insn "*ashrdi3_cc_31_and"
7294 [(set (reg CC_REGNUM)
7295 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7296 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7297 (match_operand:SI 3 "const_int_operand" "n")))
7299 (set (match_operand:DI 0 "register_operand" "=d")
7300 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7301 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
7302 && (INTVAL (operands[3]) & 63) == 63"
7304 [(set_attr "op_type" "RS")
7305 (set_attr "atype" "reg")])
7307 (define_insn "*ashrdi3_cconly_31_and"
7308 [(set (reg CC_REGNUM)
7309 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7310 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7311 (match_operand:SI 3 "const_int_operand" "n")))
7313 (clobber (match_scratch:DI 0 "=d"))]
7314 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
7315 && (INTVAL (operands[3]) & 63) == 63"
7317 [(set_attr "op_type" "RS")
7318 (set_attr "atype" "reg")])
7320 (define_insn "*ashrdi3_31_and"
7321 [(set (match_operand:DI 0 "register_operand" "=d")
7322 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7323 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7324 (match_operand:SI 3 "const_int_operand" "n"))))
7325 (clobber (reg:CC CC_REGNUM))]
7326 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
7328 [(set_attr "op_type" "RS")
7329 (set_attr "atype" "reg")])
7332 (define_insn "*ashr<mode>3_cc_and"
7333 [(set (reg CC_REGNUM)
7334 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7335 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7336 (match_operand:SI 3 "const_int_operand" "n")))
7338 (set (match_operand:GPR 0 "register_operand" "=d")
7339 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7340 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7342 [(set_attr "op_type" "RS<E>")
7343 (set_attr "atype" "reg")
7344 (set_attr "z10prop" "z10_super_E1")])
7347 (define_insn "*ashr<mode>3_cconly_and"
7348 [(set (reg CC_REGNUM)
7349 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7350 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7351 (match_operand:SI 3 "const_int_operand" "n")))
7353 (clobber (match_scratch:GPR 0 "=d"))]
7354 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7356 [(set_attr "op_type" "RS<E>")
7357 (set_attr "atype" "reg")
7358 (set_attr "z10prop" "z10_super_E1")])
7361 (define_insn "*ashr<mode>3_and"
7362 [(set (match_operand:GPR 0 "register_operand" "=d")
7363 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7364 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7365 (match_operand:SI 3 "const_int_operand" "n"))))
7366 (clobber (reg:CC CC_REGNUM))]
7367 "(INTVAL (operands[3]) & 63) == 63"
7369 [(set_attr "op_type" "RS<E>")
7370 (set_attr "atype" "reg")
7371 (set_attr "z10prop" "z10_super_E1")])
7375 ;; Branch instruction patterns.
7378 (define_expand "cbranch<mode>4"
7380 (if_then_else (match_operator 0 "comparison_operator"
7381 [(match_operand:GPR 1 "register_operand" "")
7382 (match_operand:GPR 2 "general_operand" "")])
7383 (label_ref (match_operand 3 "" ""))
7386 "s390_emit_jump (operands[3],
7387 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7390 (define_expand "cbranch<mode>4"
7392 (if_then_else (match_operator 0 "comparison_operator"
7393 [(match_operand:FP 1 "register_operand" "")
7394 (match_operand:FP 2 "general_operand" "")])
7395 (label_ref (match_operand 3 "" ""))
7398 "s390_emit_jump (operands[3],
7399 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7402 (define_expand "cbranchcc4"
7404 (if_then_else (match_operator 0 "s390_eqne_operator"
7405 [(match_operand 1 "cc_reg_operand" "")
7406 (match_operand 2 "const0_operand" "")])
7407 (label_ref (match_operand 3 "" ""))
7410 "s390_emit_jump (operands[3],
7411 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7417 ;;- Conditional jump instructions.
7420 (define_insn "*cjump_64"
7423 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7424 (label_ref (match_operand 0 "" ""))
7428 if (get_attr_length (insn) == 4)
7431 return "jg%C1\t%l0";
7433 [(set_attr "op_type" "RI")
7434 (set_attr "type" "branch")
7435 (set (attr "length")
7436 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7437 (const_int 4) (const_int 6)))])
7439 (define_insn "*cjump_31"
7442 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7443 (label_ref (match_operand 0 "" ""))
7447 gcc_assert (get_attr_length (insn) == 4);
7450 [(set_attr "op_type" "RI")
7451 (set_attr "type" "branch")
7452 (set (attr "length")
7453 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7454 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7455 (const_int 4) (const_int 6))
7456 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7457 (const_int 4) (const_int 8))))])
7459 (define_insn "*cjump_long"
7462 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7463 (match_operand 0 "address_operand" "ZQZR")
7467 if (get_attr_op_type (insn) == OP_TYPE_RR)
7472 [(set (attr "op_type")
7473 (if_then_else (match_operand 0 "register_operand" "")
7474 (const_string "RR") (const_string "RX")))
7475 (set_attr "type" "branch")
7476 (set_attr "atype" "agen")])
7480 ;;- Negated conditional jump instructions.
7483 (define_insn "*icjump_64"
7486 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7488 (label_ref (match_operand 0 "" ""))))]
7491 if (get_attr_length (insn) == 4)
7494 return "jg%D1\t%l0";
7496 [(set_attr "op_type" "RI")
7497 (set_attr "type" "branch")
7498 (set (attr "length")
7499 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7500 (const_int 4) (const_int 6)))])
7502 (define_insn "*icjump_31"
7505 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7507 (label_ref (match_operand 0 "" ""))))]
7510 gcc_assert (get_attr_length (insn) == 4);
7513 [(set_attr "op_type" "RI")
7514 (set_attr "type" "branch")
7515 (set (attr "length")
7516 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7517 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7518 (const_int 4) (const_int 6))
7519 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7520 (const_int 4) (const_int 8))))])
7522 (define_insn "*icjump_long"
7525 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7527 (match_operand 0 "address_operand" "ZQZR")))]
7530 if (get_attr_op_type (insn) == OP_TYPE_RR)
7535 [(set (attr "op_type")
7536 (if_then_else (match_operand 0 "register_operand" "")
7537 (const_string "RR") (const_string "RX")))
7538 (set_attr "type" "branch")
7539 (set_attr "atype" "agen")])
7542 ;;- Trap instructions.
7546 [(trap_if (const_int 1) (const_int 0))]
7549 [(set_attr "op_type" "RI")
7550 (set_attr "type" "branch")])
7552 (define_expand "ctrap<mode>4"
7553 [(trap_if (match_operator 0 "comparison_operator"
7554 [(match_operand:GPR 1 "register_operand" "")
7555 (match_operand:GPR 2 "general_operand" "")])
7556 (match_operand 3 "const0_operand" ""))]
7559 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7560 operands[1], operands[2]);
7561 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7565 (define_expand "ctrap<mode>4"
7566 [(trap_if (match_operator 0 "comparison_operator"
7567 [(match_operand:FP 1 "register_operand" "")
7568 (match_operand:FP 2 "general_operand" "")])
7569 (match_operand 3 "const0_operand" ""))]
7572 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7573 operands[1], operands[2]);
7574 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7578 (define_insn "condtrap"
7579 [(trap_if (match_operator 0 "s390_comparison"
7580 [(match_operand 1 "cc_reg_operand" "c")
7585 [(set_attr "op_type" "RI")
7586 (set_attr "type" "branch")])
7588 ; crt, cgrt, cit, cgit
7589 (define_insn "*cmp_and_trap_signed_int<mode>"
7590 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
7591 [(match_operand:GPR 1 "register_operand" "d,d")
7592 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
7598 [(set_attr "op_type" "RRF,RIE")
7599 (set_attr "type" "branch")
7600 (set_attr "z10prop" "z10_super_c,z10_super")])
7602 ; clrt, clgrt, clfit, clgit
7603 (define_insn "*cmp_and_trap_unsigned_int<mode>"
7604 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
7605 [(match_operand:GPR 1 "register_operand" "d,d")
7606 (match_operand:GPR 2 "nonmemory_operand" "d,D")])
7611 cl<gf>it%C0\t%1,%x2"
7612 [(set_attr "op_type" "RRF,RIE")
7613 (set_attr "type" "branch")
7614 (set_attr "z10prop" "z10_super_c,z10_super")])
7617 ;;- Loop instructions.
7619 ;; This is all complicated by the fact that since this is a jump insn
7620 ;; we must handle our own output reloads.
7624 ; This splitter will be matched by combine and has to add the 2 moves
7625 ; necessary to load the compare and the increment values into a
7626 ; register pair as needed by brxle.
7628 (define_insn_and_split "*brx_stage1_<GPR:mode>"
7631 (match_operator 6 "s390_brx_operator"
7632 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
7633 (match_operand:GPR 2 "general_operand" ""))
7634 (match_operand:GPR 3 "register_operand" "")])
7635 (label_ref (match_operand 0 "" ""))
7637 (set (match_operand:GPR 4 "nonimmediate_operand" "")
7638 (plus:GPR (match_dup 1) (match_dup 2)))
7639 (clobber (match_scratch:GPR 5 ""))]
7642 "!reload_completed && !reload_in_progress"
7643 [(set (match_dup 7) (match_dup 2)) ; the increment
7644 (set (match_dup 8) (match_dup 3)) ; the comparison value
7645 (parallel [(set (pc)
7648 [(plus:GPR (match_dup 1) (match_dup 7))
7650 (label_ref (match_dup 0))
7653 (plus:GPR (match_dup 1) (match_dup 7)))
7654 (clobber (match_dup 5))
7655 (clobber (reg:CC CC_REGNUM))])]
7657 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
7658 operands[7] = gen_lowpart (<GPR:MODE>mode,
7659 gen_highpart (word_mode, dreg));
7660 operands[8] = gen_lowpart (<GPR:MODE>mode,
7661 gen_lowpart (word_mode, dreg));
7666 (define_insn_and_split "*brxg_64bit"
7669 (match_operator 5 "s390_brx_operator"
7670 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
7671 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
7672 (subreg:DI (match_dup 2) 8)])
7673 (label_ref (match_operand 0 "" ""))
7675 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
7676 (plus:DI (match_dup 1)
7677 (subreg:DI (match_dup 2) 0)))
7678 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
7679 (clobber (reg:CC CC_REGNUM))]
7682 if (which_alternative != 0)
7684 else if (get_attr_length (insn) == 6)
7685 return "brx%E5g\t%1,%2,%l0";
7687 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
7689 "&& reload_completed
7690 && (!REG_P (operands[3])
7691 || !rtx_equal_p (operands[1], operands[3]))"
7692 [(set (match_dup 4) (match_dup 1))
7693 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
7694 (clobber (reg:CC CC_REGNUM))])
7695 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
7696 (set (match_dup 3) (match_dup 4))
7697 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
7698 (label_ref (match_dup 0))
7701 [(set_attr "op_type" "RIE")
7702 (set_attr "type" "branch")
7703 (set (attr "length")
7704 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7705 (const_int 6) (const_int 16)))])
7709 (define_insn_and_split "*brx_64bit"
7712 (match_operator 5 "s390_brx_operator"
7713 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
7714 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
7715 (subreg:SI (match_dup 2) 12)])
7716 (label_ref (match_operand 0 "" ""))
7718 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
7719 (plus:SI (match_dup 1)
7720 (subreg:SI (match_dup 2) 4)))
7721 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
7722 (clobber (reg:CC CC_REGNUM))]
7725 if (which_alternative != 0)
7727 else if (get_attr_length (insn) == 6)
7728 return "brx%C5\t%1,%2,%l0";
7730 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
7732 "&& reload_completed
7733 && (!REG_P (operands[3])
7734 || !rtx_equal_p (operands[1], operands[3]))"
7735 [(set (match_dup 4) (match_dup 1))
7736 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
7737 (clobber (reg:CC CC_REGNUM))])
7738 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
7739 (set (match_dup 3) (match_dup 4))
7740 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
7741 (label_ref (match_dup 0))
7744 [(set_attr "op_type" "RSI")
7745 (set_attr "type" "branch")
7746 (set (attr "length")
7747 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7748 (const_int 6) (const_int 14)))])
7752 (define_insn_and_split "*brx_31bit"
7755 (match_operator 5 "s390_brx_operator"
7756 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
7757 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
7758 (subreg:SI (match_dup 2) 4)])
7759 (label_ref (match_operand 0 "" ""))
7761 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
7762 (plus:SI (match_dup 1)
7763 (subreg:SI (match_dup 2) 0)))
7764 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
7765 (clobber (reg:CC CC_REGNUM))]
7766 "!TARGET_64BIT && TARGET_CPU_ZARCH"
7768 if (which_alternative != 0)
7770 else if (get_attr_length (insn) == 6)
7771 return "brx%C5\t%1,%2,%l0";
7773 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
7775 "&& reload_completed
7776 && (!REG_P (operands[3])
7777 || !rtx_equal_p (operands[1], operands[3]))"
7778 [(set (match_dup 4) (match_dup 1))
7779 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
7780 (clobber (reg:CC CC_REGNUM))])
7781 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
7782 (set (match_dup 3) (match_dup 4))
7783 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
7784 (label_ref (match_dup 0))
7787 [(set_attr "op_type" "RSI")
7788 (set_attr "type" "branch")
7789 (set (attr "length")
7790 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7791 (const_int 6) (const_int 14)))])
7796 (define_expand "doloop_end"
7797 [(use (match_operand 0 "" "")) ; loop pseudo
7798 (use (match_operand 1 "" "")) ; iterations; zero if unknown
7799 (use (match_operand 2 "" "")) ; max iterations
7800 (use (match_operand 3 "" "")) ; loop level
7801 (use (match_operand 4 "" ""))] ; label
7804 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
7805 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
7806 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
7807 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
7808 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
7809 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
7816 (define_insn_and_split "doloop_si64"
7819 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7821 (label_ref (match_operand 0 "" ""))
7823 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7824 (plus:SI (match_dup 1) (const_int -1)))
7825 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7826 (clobber (reg:CC CC_REGNUM))]
7829 if (which_alternative != 0)
7831 else if (get_attr_length (insn) == 4)
7832 return "brct\t%1,%l0";
7834 return "ahi\t%1,-1\;jgne\t%l0";
7836 "&& reload_completed
7837 && (! REG_P (operands[2])
7838 || ! rtx_equal_p (operands[1], operands[2]))"
7839 [(set (match_dup 3) (match_dup 1))
7840 (parallel [(set (reg:CCAN CC_REGNUM)
7841 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7843 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7844 (set (match_dup 2) (match_dup 3))
7845 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7846 (label_ref (match_dup 0))
7849 [(set_attr "op_type" "RI")
7850 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7851 ; hurt us in the (rare) case of ahi.
7852 (set_attr "z10prop" "z10_super_E1")
7853 (set_attr "type" "branch")
7854 (set (attr "length")
7855 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7856 (const_int 4) (const_int 10)))])
7858 (define_insn_and_split "doloop_si31"
7861 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7863 (label_ref (match_operand 0 "" ""))
7865 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7866 (plus:SI (match_dup 1) (const_int -1)))
7867 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7868 (clobber (reg:CC CC_REGNUM))]
7871 if (which_alternative != 0)
7873 else if (get_attr_length (insn) == 4)
7874 return "brct\t%1,%l0";
7878 "&& reload_completed
7879 && (! REG_P (operands[2])
7880 || ! rtx_equal_p (operands[1], operands[2]))"
7881 [(set (match_dup 3) (match_dup 1))
7882 (parallel [(set (reg:CCAN CC_REGNUM)
7883 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7885 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7886 (set (match_dup 2) (match_dup 3))
7887 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7888 (label_ref (match_dup 0))
7891 [(set_attr "op_type" "RI")
7892 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7893 ; hurt us in the (rare) case of ahi.
7894 (set_attr "z10prop" "z10_super_E1")
7895 (set_attr "type" "branch")
7896 (set (attr "length")
7897 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7898 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7899 (const_int 4) (const_int 6))
7900 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7901 (const_int 4) (const_int 8))))])
7903 (define_insn "*doloop_si_long"
7906 (ne (match_operand:SI 1 "register_operand" "d")
7908 (match_operand 0 "address_operand" "ZQZR")
7910 (set (match_operand:SI 2 "register_operand" "=1")
7911 (plus:SI (match_dup 1) (const_int -1)))
7912 (clobber (match_scratch:SI 3 "=X"))
7913 (clobber (reg:CC CC_REGNUM))]
7916 if (get_attr_op_type (insn) == OP_TYPE_RR)
7917 return "bctr\t%1,%0";
7919 return "bct\t%1,%a0";
7921 [(set (attr "op_type")
7922 (if_then_else (match_operand 0 "register_operand" "")
7923 (const_string "RR") (const_string "RX")))
7924 (set_attr "type" "branch")
7925 (set_attr "atype" "agen")
7926 (set_attr "z10prop" "z10_c")])
7928 (define_insn_and_split "doloop_di"
7931 (ne (match_operand:DI 1 "register_operand" "d,d,d")
7933 (label_ref (match_operand 0 "" ""))
7935 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
7936 (plus:DI (match_dup 1) (const_int -1)))
7937 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
7938 (clobber (reg:CC CC_REGNUM))]
7941 if (which_alternative != 0)
7943 else if (get_attr_length (insn) == 4)
7944 return "brctg\t%1,%l0";
7946 return "aghi\t%1,-1\;jgne\t%l0";
7948 "&& reload_completed
7949 && (! REG_P (operands[2])
7950 || ! rtx_equal_p (operands[1], operands[2]))"
7951 [(set (match_dup 3) (match_dup 1))
7952 (parallel [(set (reg:CCAN CC_REGNUM)
7953 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
7955 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
7956 (set (match_dup 2) (match_dup 3))
7957 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7958 (label_ref (match_dup 0))
7961 [(set_attr "op_type" "RI")
7962 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7963 ; hurt us in the (rare) case of ahi.
7964 (set_attr "z10prop" "z10_super_E1")
7965 (set_attr "type" "branch")
7966 (set (attr "length")
7967 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7968 (const_int 4) (const_int 10)))])
7971 ;;- Unconditional jump instructions.
7975 ; jump instruction pattern(s).
7978 (define_expand "jump"
7979 [(match_operand 0 "" "")]
7981 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
7983 (define_insn "*jump64"
7984 [(set (pc) (label_ref (match_operand 0 "" "")))]
7987 if (get_attr_length (insn) == 4)
7992 [(set_attr "op_type" "RI")
7993 (set_attr "type" "branch")
7994 (set (attr "length")
7995 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7996 (const_int 4) (const_int 6)))])
7998 (define_insn "*jump31"
7999 [(set (pc) (label_ref (match_operand 0 "" "")))]
8002 gcc_assert (get_attr_length (insn) == 4);
8005 [(set_attr "op_type" "RI")
8006 (set_attr "type" "branch")
8007 (set (attr "length")
8008 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
8009 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8010 (const_int 4) (const_int 6))
8011 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8012 (const_int 4) (const_int 8))))])
8015 ; indirect-jump instruction pattern(s).
8018 (define_insn "indirect_jump"
8019 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8022 if (get_attr_op_type (insn) == OP_TYPE_RR)
8027 [(set (attr "op_type")
8028 (if_then_else (match_operand 0 "register_operand" "")
8029 (const_string "RR") (const_string "RX")))
8030 (set_attr "type" "branch")
8031 (set_attr "atype" "agen")])
8034 ; casesi instruction pattern(s).
8037 (define_insn "casesi_jump"
8038 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8039 (use (label_ref (match_operand 1 "" "")))]
8042 if (get_attr_op_type (insn) == OP_TYPE_RR)
8047 [(set (attr "op_type")
8048 (if_then_else (match_operand 0 "register_operand" "")
8049 (const_string "RR") (const_string "RX")))
8050 (set_attr "type" "branch")
8051 (set_attr "atype" "agen")])
8053 (define_expand "casesi"
8054 [(match_operand:SI 0 "general_operand" "")
8055 (match_operand:SI 1 "general_operand" "")
8056 (match_operand:SI 2 "general_operand" "")
8057 (label_ref (match_operand 3 "" ""))
8058 (label_ref (match_operand 4 "" ""))]
8061 rtx index = gen_reg_rtx (SImode);
8062 rtx base = gen_reg_rtx (Pmode);
8063 rtx target = gen_reg_rtx (Pmode);
8065 emit_move_insn (index, operands[0]);
8066 emit_insn (gen_subsi3 (index, index, operands[1]));
8067 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8070 if (Pmode != SImode)
8071 index = convert_to_mode (Pmode, index, 1);
8072 if (GET_CODE (index) != REG)
8073 index = copy_to_mode_reg (Pmode, index);
8076 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8078 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8080 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8082 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8083 emit_move_insn (target, index);
8086 target = gen_rtx_PLUS (Pmode, base, target);
8087 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8094 ;;- Jump to subroutine.
8099 ; untyped call instruction pattern(s).
8102 ;; Call subroutine returning any type.
8103 (define_expand "untyped_call"
8104 [(parallel [(call (match_operand 0 "" "")
8106 (match_operand 1 "" "")
8107 (match_operand 2 "" "")])]
8112 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8114 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8116 rtx set = XVECEXP (operands[2], 0, i);
8117 emit_move_insn (SET_DEST (set), SET_SRC (set));
8120 /* The optimizer does not know that the call sets the function value
8121 registers we stored in the result block. We avoid problems by
8122 claiming that all hard registers are used and clobbered at this
8124 emit_insn (gen_blockage ());
8129 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8130 ;; all of memory. This blocks insns from being moved across this point.
8132 (define_insn "blockage"
8133 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8136 [(set_attr "type" "none")
8137 (set_attr "length" "0")])
8143 (define_expand "sibcall"
8144 [(call (match_operand 0 "" "")
8145 (match_operand 1 "" ""))]
8148 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8152 (define_insn "*sibcall_br"
8153 [(call (mem:QI (reg SIBCALL_REGNUM))
8154 (match_operand 0 "const_int_operand" "n"))]
8155 "SIBLING_CALL_P (insn)
8156 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8158 [(set_attr "op_type" "RR")
8159 (set_attr "type" "branch")
8160 (set_attr "atype" "agen")])
8162 (define_insn "*sibcall_brc"
8163 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8164 (match_operand 1 "const_int_operand" "n"))]
8165 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8167 [(set_attr "op_type" "RI")
8168 (set_attr "type" "branch")])
8170 (define_insn "*sibcall_brcl"
8171 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8172 (match_operand 1 "const_int_operand" "n"))]
8173 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8175 [(set_attr "op_type" "RIL")
8176 (set_attr "type" "branch")])
8179 ; sibcall_value patterns
8182 (define_expand "sibcall_value"
8183 [(set (match_operand 0 "" "")
8184 (call (match_operand 1 "" "")
8185 (match_operand 2 "" "")))]
8188 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8192 (define_insn "*sibcall_value_br"
8193 [(set (match_operand 0 "" "")
8194 (call (mem:QI (reg SIBCALL_REGNUM))
8195 (match_operand 1 "const_int_operand" "n")))]
8196 "SIBLING_CALL_P (insn)
8197 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8199 [(set_attr "op_type" "RR")
8200 (set_attr "type" "branch")
8201 (set_attr "atype" "agen")])
8203 (define_insn "*sibcall_value_brc"
8204 [(set (match_operand 0 "" "")
8205 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8206 (match_operand 2 "const_int_operand" "n")))]
8207 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8209 [(set_attr "op_type" "RI")
8210 (set_attr "type" "branch")])
8212 (define_insn "*sibcall_value_brcl"
8213 [(set (match_operand 0 "" "")
8214 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8215 (match_operand 2 "const_int_operand" "n")))]
8216 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8218 [(set_attr "op_type" "RIL")
8219 (set_attr "type" "branch")])
8223 ; call instruction pattern(s).
8226 (define_expand "call"
8227 [(call (match_operand 0 "" "")
8228 (match_operand 1 "" ""))
8229 (use (match_operand 2 "" ""))]
8232 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8233 gen_rtx_REG (Pmode, RETURN_REGNUM));
8237 (define_insn "*bras"
8238 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8239 (match_operand 1 "const_int_operand" "n"))
8240 (clobber (match_operand 2 "register_operand" "=r"))]
8241 "!SIBLING_CALL_P (insn)
8242 && TARGET_SMALL_EXEC
8243 && GET_MODE (operands[2]) == Pmode"
8245 [(set_attr "op_type" "RI")
8246 (set_attr "type" "jsr")])
8248 (define_insn "*brasl"
8249 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8250 (match_operand 1 "const_int_operand" "n"))
8251 (clobber (match_operand 2 "register_operand" "=r"))]
8252 "!SIBLING_CALL_P (insn)
8254 && GET_MODE (operands[2]) == Pmode"
8256 [(set_attr "op_type" "RIL")
8257 (set_attr "type" "jsr")])
8259 (define_insn "*basr"
8260 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8261 (match_operand 1 "const_int_operand" "n"))
8262 (clobber (match_operand 2 "register_operand" "=r"))]
8263 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8265 if (get_attr_op_type (insn) == OP_TYPE_RR)
8266 return "basr\t%2,%0";
8268 return "bas\t%2,%a0";
8270 [(set (attr "op_type")
8271 (if_then_else (match_operand 0 "register_operand" "")
8272 (const_string "RR") (const_string "RX")))
8273 (set_attr "type" "jsr")
8274 (set_attr "atype" "agen")])
8277 ; call_value instruction pattern(s).
8280 (define_expand "call_value"
8281 [(set (match_operand 0 "" "")
8282 (call (match_operand 1 "" "")
8283 (match_operand 2 "" "")))
8284 (use (match_operand 3 "" ""))]
8287 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8288 gen_rtx_REG (Pmode, RETURN_REGNUM));
8292 (define_insn "*bras_r"
8293 [(set (match_operand 0 "" "")
8294 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8295 (match_operand:SI 2 "const_int_operand" "n")))
8296 (clobber (match_operand 3 "register_operand" "=r"))]
8297 "!SIBLING_CALL_P (insn)
8298 && TARGET_SMALL_EXEC
8299 && GET_MODE (operands[3]) == Pmode"
8301 [(set_attr "op_type" "RI")
8302 (set_attr "type" "jsr")])
8304 (define_insn "*brasl_r"
8305 [(set (match_operand 0 "" "")
8306 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8307 (match_operand 2 "const_int_operand" "n")))
8308 (clobber (match_operand 3 "register_operand" "=r"))]
8309 "!SIBLING_CALL_P (insn)
8311 && GET_MODE (operands[3]) == Pmode"
8313 [(set_attr "op_type" "RIL")
8314 (set_attr "type" "jsr")])
8316 (define_insn "*basr_r"
8317 [(set (match_operand 0 "" "")
8318 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8319 (match_operand 2 "const_int_operand" "n")))
8320 (clobber (match_operand 3 "register_operand" "=r"))]
8321 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8323 if (get_attr_op_type (insn) == OP_TYPE_RR)
8324 return "basr\t%3,%1";
8326 return "bas\t%3,%a1";
8328 [(set (attr "op_type")
8329 (if_then_else (match_operand 1 "register_operand" "")
8330 (const_string "RR") (const_string "RX")))
8331 (set_attr "type" "jsr")
8332 (set_attr "atype" "agen")])
8335 ;;- Thread-local storage support.
8338 (define_expand "get_tp_64"
8339 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
8343 (define_expand "get_tp_31"
8344 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
8348 (define_expand "set_tp_64"
8349 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
8350 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
8354 (define_expand "set_tp_31"
8355 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
8356 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
8360 (define_insn "*set_tp"
8361 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8364 [(set_attr "type" "none")
8365 (set_attr "length" "0")])
8367 (define_insn "*tls_load_64"
8368 [(set (match_operand:DI 0 "register_operand" "=d")
8369 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8370 (match_operand:DI 2 "" "")]
8374 [(set_attr "op_type" "RXE")
8375 (set_attr "z10prop" "z10_fwd_A3")])
8377 (define_insn "*tls_load_31"
8378 [(set (match_operand:SI 0 "register_operand" "=d,d")
8379 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8380 (match_operand:SI 2 "" "")]
8386 [(set_attr "op_type" "RX,RXY")
8387 (set_attr "type" "load")
8388 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8390 (define_insn "*bras_tls"
8391 [(set (match_operand 0 "" "")
8392 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8393 (match_operand 2 "const_int_operand" "n")))
8394 (clobber (match_operand 3 "register_operand" "=r"))
8395 (use (match_operand 4 "" ""))]
8396 "!SIBLING_CALL_P (insn)
8397 && TARGET_SMALL_EXEC
8398 && GET_MODE (operands[3]) == Pmode"
8400 [(set_attr "op_type" "RI")
8401 (set_attr "type" "jsr")])
8403 (define_insn "*brasl_tls"
8404 [(set (match_operand 0 "" "")
8405 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8406 (match_operand 2 "const_int_operand" "n")))
8407 (clobber (match_operand 3 "register_operand" "=r"))
8408 (use (match_operand 4 "" ""))]
8409 "!SIBLING_CALL_P (insn)
8411 && GET_MODE (operands[3]) == Pmode"
8413 [(set_attr "op_type" "RIL")
8414 (set_attr "type" "jsr")])
8416 (define_insn "*basr_tls"
8417 [(set (match_operand 0 "" "")
8418 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8419 (match_operand 2 "const_int_operand" "n")))
8420 (clobber (match_operand 3 "register_operand" "=r"))
8421 (use (match_operand 4 "" ""))]
8422 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8424 if (get_attr_op_type (insn) == OP_TYPE_RR)
8425 return "basr\t%3,%1%J4";
8427 return "bas\t%3,%a1%J4";
8429 [(set (attr "op_type")
8430 (if_then_else (match_operand 1 "register_operand" "")
8431 (const_string "RR") (const_string "RX")))
8432 (set_attr "type" "jsr")
8433 (set_attr "atype" "agen")])
8436 ;;- Atomic operations
8440 ; memory barrier pattern.
8443 (define_expand "memory_barrier"
8445 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8448 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8449 MEM_VOLATILE_P (operands[0]) = 1;
8452 (define_insn "*memory_barrier"
8453 [(set (match_operand:BLK 0 "" "")
8454 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8457 [(set_attr "op_type" "RR")])
8459 ; Although bcr is superscalar on Z10, this variant will never become part of
8460 ; an execution group.
8463 ; compare and swap patterns.
8466 (define_expand "sync_compare_and_swap<mode>"
8468 [(set (match_operand:TDSI 0 "register_operand" "")
8469 (match_operand:TDSI 1 "memory_operand" ""))
8471 (unspec_volatile:TDSI
8473 (match_operand:TDSI 2 "register_operand" "")
8474 (match_operand:TDSI 3 "register_operand" "")]
8476 (set (reg:CCZ1 CC_REGNUM)
8477 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8480 (define_expand "sync_compare_and_swap<mode>"
8482 [(set (match_operand:HQI 0 "register_operand" "")
8483 (match_operand:HQI 1 "memory_operand" ""))
8485 (unspec_volatile:HQI
8487 (match_operand:HQI 2 "general_operand" "")
8488 (match_operand:HQI 3 "general_operand" "")]
8490 (clobber (reg:CC CC_REGNUM))])]
8492 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
8493 operands[2], operands[3]); DONE;")
8496 (define_insn "*sync_compare_and_swap<mode>"
8497 [(set (match_operand:DP 0 "register_operand" "=r")
8498 (match_operand:DP 1 "memory_operand" "+Q"))
8502 (match_operand:DP 2 "register_operand" "0")
8503 (match_operand:DP 3 "register_operand" "r")]
8505 (set (reg:CCZ1 CC_REGNUM)
8506 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8508 "cds<tg>\t%0,%3,%S1"
8509 [(set_attr "op_type" "RS<TE>")
8510 (set_attr "type" "sem")])
8513 (define_insn "*sync_compare_and_swap<mode>"
8514 [(set (match_operand:GPR 0 "register_operand" "=r")
8515 (match_operand:GPR 1 "memory_operand" "+Q"))
8517 (unspec_volatile:GPR
8519 (match_operand:GPR 2 "register_operand" "0")
8520 (match_operand:GPR 3 "register_operand" "r")]
8522 (set (reg:CCZ1 CC_REGNUM)
8523 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8526 [(set_attr "op_type" "RS<E>")
8527 (set_attr "type" "sem")])
8531 ; Other atomic instruction patterns.
8534 (define_expand "sync_lock_test_and_set<mode>"
8535 [(match_operand:HQI 0 "register_operand")
8536 (match_operand:HQI 1 "memory_operand")
8537 (match_operand:HQI 2 "general_operand")]
8539 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
8540 operands[2], false); DONE;")
8542 (define_expand "sync_<atomic><mode>"
8543 [(set (match_operand:HQI 0 "memory_operand")
8544 (ATOMIC:HQI (match_dup 0)
8545 (match_operand:HQI 1 "general_operand")))]
8547 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
8548 operands[1], false); DONE;")
8550 (define_expand "sync_old_<atomic><mode>"
8551 [(set (match_operand:HQI 0 "register_operand")
8552 (match_operand:HQI 1 "memory_operand"))
8554 (ATOMIC:HQI (match_dup 1)
8555 (match_operand:HQI 2 "general_operand")))]
8557 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8558 operands[2], false); DONE;")
8560 (define_expand "sync_new_<atomic><mode>"
8561 [(set (match_operand:HQI 0 "register_operand")
8562 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
8563 (match_operand:HQI 2 "general_operand")))
8564 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
8566 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8567 operands[2], true); DONE;")
8570 ;;- Miscellaneous instructions.
8574 ; allocate stack instruction pattern(s).
8577 (define_expand "allocate_stack"
8578 [(match_operand 0 "general_operand" "")
8579 (match_operand 1 "general_operand" "")]
8582 rtx temp = gen_reg_rtx (Pmode);
8584 emit_move_insn (temp, s390_back_chain_rtx ());
8585 anti_adjust_stack (operands[1]);
8586 emit_move_insn (s390_back_chain_rtx (), temp);
8588 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
8594 ; setjmp instruction pattern.
8597 (define_expand "builtin_setjmp_receiver"
8598 [(match_operand 0 "" "")]
8601 emit_insn (s390_load_got ());
8602 emit_use (pic_offset_table_rtx);
8606 ;; These patterns say how to save and restore the stack pointer. We need not
8607 ;; save the stack pointer at function level since we are careful to
8608 ;; preserve the backchain. At block level, we have to restore the backchain
8609 ;; when we restore the stack pointer.
8611 ;; For nonlocal gotos, we must save both the stack pointer and its
8612 ;; backchain and restore both. Note that in the nonlocal case, the
8613 ;; save area is a memory location.
8615 (define_expand "save_stack_function"
8616 [(match_operand 0 "general_operand" "")
8617 (match_operand 1 "general_operand" "")]
8621 (define_expand "restore_stack_function"
8622 [(match_operand 0 "general_operand" "")
8623 (match_operand 1 "general_operand" "")]
8627 (define_expand "restore_stack_block"
8628 [(match_operand 0 "register_operand" "")
8629 (match_operand 1 "register_operand" "")]
8632 rtx temp = gen_reg_rtx (Pmode);
8634 emit_move_insn (temp, s390_back_chain_rtx ());
8635 emit_move_insn (operands[0], operands[1]);
8636 emit_move_insn (s390_back_chain_rtx (), temp);
8641 (define_expand "save_stack_nonlocal"
8642 [(match_operand 0 "memory_operand" "")
8643 (match_operand 1 "register_operand" "")]
8646 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
8647 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8649 /* Copy the backchain to the first word, sp to the second and the
8650 literal pool base to the third. */
8652 if (TARGET_BACKCHAIN)
8654 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
8655 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
8658 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
8659 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
8664 (define_expand "restore_stack_nonlocal"
8665 [(match_operand 0 "register_operand" "")
8666 (match_operand 1 "memory_operand" "")]
8669 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
8670 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8671 rtx temp = NULL_RTX;
8673 /* Restore the backchain from the first word, sp from the second and the
8674 literal pool base from the third. */
8676 if (TARGET_BACKCHAIN)
8677 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
8679 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
8680 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
8683 emit_move_insn (s390_back_chain_rtx (), temp);
8689 (define_expand "exception_receiver"
8693 s390_set_has_landing_pad_p (true);
8698 ; nop instruction pattern(s).
8705 [(set_attr "op_type" "RR")
8706 (set_attr "z10prop" "z10_fr_E1")])
8712 [(set_attr "op_type" "RR")])
8716 ; Special literal pool access instruction pattern(s).
8719 (define_insn "*pool_entry"
8720 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
8721 UNSPECV_POOL_ENTRY)]
8724 enum machine_mode mode = GET_MODE (PATTERN (insn));
8725 unsigned int align = GET_MODE_BITSIZE (mode);
8726 s390_output_pool_entry (operands[0], mode, align);
8729 [(set (attr "length")
8730 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
8732 (define_insn "pool_align"
8733 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
8734 UNSPECV_POOL_ALIGN)]
8737 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8739 (define_insn "pool_section_start"
8740 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
8743 [(set_attr "length" "0")])
8745 (define_insn "pool_section_end"
8746 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
8749 [(set_attr "length" "0")])
8751 (define_insn "main_base_31_small"
8752 [(set (match_operand 0 "register_operand" "=a")
8753 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8754 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8756 [(set_attr "op_type" "RR")
8757 (set_attr "type" "la")])
8759 (define_insn "main_base_31_large"
8760 [(set (match_operand 0 "register_operand" "=a")
8761 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
8762 (set (pc) (label_ref (match_operand 2 "" "")))]
8763 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8765 [(set_attr "op_type" "RI")])
8767 (define_insn "main_base_64"
8768 [(set (match_operand 0 "register_operand" "=a")
8769 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8770 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8772 [(set_attr "op_type" "RIL")
8773 (set_attr "type" "larl")
8774 (set_attr "z10prop" "z10_fwd_A1")])
8776 (define_insn "main_pool"
8777 [(set (match_operand 0 "register_operand" "=a")
8778 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
8779 "GET_MODE (operands[0]) == Pmode"
8784 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
8785 (const_string "larl") (const_string "la")))])
8787 (define_insn "reload_base_31"
8788 [(set (match_operand 0 "register_operand" "=a")
8789 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8790 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8791 "basr\t%0,0\;la\t%0,%1-.(%0)"
8792 [(set_attr "length" "6")
8793 (set_attr "type" "la")])
8795 (define_insn "reload_base_64"
8796 [(set (match_operand 0 "register_operand" "=a")
8797 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8798 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8800 [(set_attr "op_type" "RIL")
8801 (set_attr "type" "larl")
8802 (set_attr "z10prop" "z10_fwd_A1")])
8805 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
8810 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8813 ;; Insns related to generating the function prologue and epilogue.
8817 (define_expand "prologue"
8818 [(use (const_int 0))]
8820 "s390_emit_prologue (); DONE;")
8822 (define_expand "epilogue"
8823 [(use (const_int 1))]
8825 "s390_emit_epilogue (false); DONE;")
8827 (define_expand "sibcall_epilogue"
8828 [(use (const_int 0))]
8830 "s390_emit_epilogue (true); DONE;")
8832 (define_insn "*return"
8834 (use (match_operand 0 "register_operand" "a"))]
8835 "GET_MODE (operands[0]) == Pmode"
8837 [(set_attr "op_type" "RR")
8838 (set_attr "type" "jsr")
8839 (set_attr "atype" "agen")])
8842 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
8843 ;; pointer. This is used for compatibility.
8845 (define_expand "ptr_extend"
8846 [(set (match_operand:DI 0 "register_operand" "=r")
8847 (match_operand:SI 1 "register_operand" "r"))]
8850 emit_insn (gen_anddi3 (operands[0],
8851 gen_lowpart (DImode, operands[1]),
8852 GEN_INT (0x7fffffff)));
8856 ;; Instruction definition to expand eh_return macro to support
8857 ;; swapping in special linkage return addresses.
8859 (define_expand "eh_return"
8860 [(use (match_operand 0 "register_operand" ""))]
8863 s390_emit_tpf_eh_return (operands[0]);
8868 ; Stack Protector Patterns
8871 (define_expand "stack_protect_set"
8872 [(set (match_operand 0 "memory_operand" "")
8873 (match_operand 1 "memory_operand" ""))]
8876 #ifdef TARGET_THREAD_SSP_OFFSET
8878 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8879 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8882 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
8884 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
8889 (define_insn "stack_protect_set<mode>"
8890 [(set (match_operand:DSI 0 "memory_operand" "=Q")
8891 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
8893 "mvc\t%O0(%G0,%R0),%S1"
8894 [(set_attr "op_type" "SS")])
8896 (define_expand "stack_protect_test"
8897 [(set (reg:CC CC_REGNUM)
8898 (compare (match_operand 0 "memory_operand" "")
8899 (match_operand 1 "memory_operand" "")))
8900 (match_operand 2 "" "")]
8904 #ifdef TARGET_THREAD_SSP_OFFSET
8906 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8907 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8910 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
8912 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
8914 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
8915 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
8916 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
8920 (define_insn "stack_protect_test<mode>"
8921 [(set (reg:CCZ CC_REGNUM)
8922 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
8923 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
8925 "clc\t%O0(%G0,%R0),%S1"
8926 [(set_attr "op_type" "SS")])
8928 ; This is used in s390_emit_prologue in order to prevent insns
8929 ; adjusting the stack pointer to be moved over insns writing stack
8930 ; slots using a copy of the stack pointer in a different register.
8931 (define_insn "stack_tie"
8932 [(set (match_operand:BLK 0 "memory_operand" "+m")
8933 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
8936 [(set_attr "length" "0")])
8940 ; Data prefetch patterns
8943 (define_insn "prefetch"
8944 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
8945 (match_operand:SI 1 "const_int_operand" " n,n")
8946 (match_operand:SI 2 "const_int_operand" " n,n"))]
8949 switch (which_alternative)
8952 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
8954 if (larl_operand (operands[0], Pmode))
8955 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
8958 /* This might be reached for symbolic operands with an odd
8959 addend. We simply omit the prefetch for such rare cases. */
8964 [(set_attr "type" "load,larl")
8965 (set_attr "op_type" "RXY,RIL")
8966 (set_attr "z10prop" "z10_super")])
8970 ; Byte swap instructions
8973 (define_insn "bswap<mode>2"
8974 [(set (match_operand:GPR 0 "register_operand" "=d, d")
8975 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
8980 [(set_attr "type" "*,load")
8981 (set_attr "op_type" "RRE,RXY")
8982 (set_attr "z10prop" "z10_super")])