1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 ;; 2009, 2010 Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
68 ; GOT/PLT and lt-relative accesses
69 (UNSPEC_LTREL_OFFSET 100)
70 (UNSPEC_LTREL_BASE 101)
71 (UNSPEC_POOL_OFFSET 102)
79 (UNSPEC_RELOAD_BASE 210)
80 (UNSPEC_MAIN_BASE 211)
88 ; TLS relocation specifiers
93 (UNSPEC_GOTNTPOFF 504)
94 (UNSPEC_INDNTPOFF 505)
97 (UNSPEC_TLSLDM_NTPOFF 511)
104 ; Stack Smashing Protector
108 ; Test Data Class (TDC)
109 (UNSPEC_TDC_INSN 800)
113 ;; UNSPEC_VOLATILE usage
121 (UNSPECV_TPF_PROLOGUE 20)
122 (UNSPECV_TPF_EPILOGUE 21)
126 (UNSPECV_POOL_SECTION 201)
127 (UNSPECV_POOL_ALIGN 202)
128 (UNSPECV_POOL_ENTRY 203)
129 (UNSPECV_MAIN_POOL 300)
142 ; Registers with special meaning
146 ; Sibling call register.
148 ; Literal pool base register.
150 ; Return address register.
152 ; Condition code register.
154 ; Thread local storage pointer register.
158 ; Hardware register names
162 ; General purpose registers
164 ; Floating point registers.
170 ;; PFPO GPR0 argument format
175 ; PFPO operation type
176 (PFPO_CONVERT 0x1000000)
178 (PFPO_OP_TYPE_SF 0x5)
179 (PFPO_OP_TYPE_DF 0x6)
180 (PFPO_OP_TYPE_TF 0x7)
181 (PFPO_OP_TYPE_SD 0x8)
182 (PFPO_OP_TYPE_DD 0x9)
183 (PFPO_OP_TYPE_TD 0xa)
184 ; Bitposition of operand types
185 (PFPO_OP0_TYPE_SHIFT 16)
186 (PFPO_OP1_TYPE_SHIFT 8)
190 ;; Instruction operand type as used in the Principles of Operation.
191 ;; Used to determine defaults for length and other attribute values.
193 (define_attr "op_type"
194 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
197 ;; Instruction type attribute used for scheduling.
199 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
200 cs,vs,store,sem,idiv,
201 imulhi,imulsi,imuldi,
202 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
203 floadtf,floaddf,floadsf,fstoredf,fstoresf,
204 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
205 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
206 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
207 itoftf, itofdf, itofsf, itofdd, itoftd,
208 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
209 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
211 (cond [(eq_attr "op_type" "NN") (const_string "other")
212 (eq_attr "op_type" "SS") (const_string "cs")]
213 (const_string "integer")))
215 ;; Another attribute used for scheduling purposes:
216 ;; agen: Instruction uses the address generation unit
217 ;; reg: Instruction does not use the agen unit
219 (define_attr "atype" "agen,reg"
220 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
222 (const_string "agen")))
224 ;; Properties concerning Z10 execution grouping and value forwarding.
225 ;; z10_super: instruction is superscalar.
226 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
227 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
228 ;; target register. It can forward this value to a second instruction that reads
229 ;; the same register if that second instruction is issued in the same group.
230 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
231 ;; instruction in the S pipe writes to the register, then the T instruction
232 ;; can immediately read the new value.
233 ;; z10_fr: union of Z10_fwd and z10_rec.
234 ;; z10_c: second operand of instruction is a register and read with complemented bits.
236 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
239 (define_attr "z10prop" "none,
240 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
241 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
243 z10_fr, z10_fr_A3, z10_fr_E1,
245 (const_string "none"))
250 (define_attr "length" ""
251 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
252 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
256 ;; Processor type. This attribute must exactly match the processor_type
257 ;; enumeration in s390.h. The current machine description does not
258 ;; distinguish between g5 and g6, but there are differences between the two
259 ;; CPUs could in theory be modeled.
261 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
262 (const (symbol_ref "s390_tune_attr")))
264 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
265 (const_string "standard"))
267 (define_attr "enabled" ""
268 (cond [(eq_attr "cpu_facility" "standard")
271 (and (eq_attr "cpu_facility" "ieee")
272 (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0)))
275 (and (eq_attr "cpu_facility" "zarch")
276 (ne (symbol_ref "TARGET_ZARCH") (const_int 0)))
279 (and (eq_attr "cpu_facility" "longdisp")
280 (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0)))
283 (and (eq_attr "cpu_facility" "extimm")
284 (ne (symbol_ref "TARGET_EXTIMM") (const_int 0)))
287 (and (eq_attr "cpu_facility" "dfp")
288 (ne (symbol_ref "TARGET_DFP") (const_int 0)))
291 (and (eq_attr "cpu_facility" "z10")
292 (ne (symbol_ref "TARGET_Z10") (const_int 0)))
296 ;; Pipeline description for z900. For lack of anything better,
297 ;; this description is also used for the g5 and g6.
300 ;; Pipeline description for z990, z9-109 and z9-ec.
303 ;; Pipeline description for z10
307 (include "predicates.md")
309 ;; Constraint definitions
310 (include "constraints.md")
317 ;; These mode iterators allow floating point patterns to be generated from the
319 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
320 (SD "TARGET_HARD_DFP")])
321 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
322 (define_mode_iterator FPALL [TF DF SF TD DD SD])
323 (define_mode_iterator BFP [TF DF SF])
324 (define_mode_iterator DFP [TD DD])
325 (define_mode_iterator DFP_ALL [TD DD SD])
326 (define_mode_iterator DSF [DF SF])
327 (define_mode_iterator SD_SF [SF SD])
328 (define_mode_iterator DD_DF [DF DD])
329 (define_mode_iterator TD_TF [TF TD])
331 ;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated
332 ;; from the same template.
333 (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI])
335 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
336 ;; from the same template.
337 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
338 (define_mode_iterator DSI [DI SI])
340 ;; These mode iterators allow :P to be used for patterns that operate on
341 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
342 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
344 ;; These macros refer to the actual word_mode of the configuration. This is equal
345 ;; to Pmode except on 31-bit machines in zarch mode.
346 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
347 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
349 ;; This mode iterator allows the QI and HI patterns to be defined from
350 ;; the same template.
351 (define_mode_iterator HQI [HI QI])
353 ;; This mode iterator allows the integer patterns to be defined from the
355 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
356 (define_mode_iterator INTALL [TI DI SI HI QI])
358 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
359 ;; the same template.
360 (define_code_iterator SHIFT [ashift lshiftrt])
362 ;; This iterator and attribute allow to combine most atomic operations.
363 (define_code_iterator ATOMIC [and ior xor plus minus mult])
364 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
365 (plus "add") (minus "sub") (mult "nand")])
367 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
368 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
369 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
371 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
372 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
374 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
376 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
377 ;; Likewise for "<RXe>".
378 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
379 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
381 ;; The decimal floating point variants of add, sub, div and mul support 3
382 ;; fp register operands. The following attributes allow to merge the bfp and
383 ;; dfp variants in a single insn definition.
385 ;; This attribute is used to set op_type accordingly.
386 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
387 (DD "RRR") (SD "RRR")])
389 ;; This attribute is used in the operand constraint list in order to have the
390 ;; first and the second operand match for bfp modes.
391 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
393 ;; This attribute is used in the operand list of the instruction to have an
394 ;; additional operand for the dfp instructions.
395 (define_mode_attr op1 [(TF "") (DF "") (SF "")
396 (TD "%1,") (DD "%1,") (SD "%1,")])
399 ;; This attribute is used in the operand constraint list
400 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
401 ;; TFmode values are represented by a fp register pair. Since the
402 ;; sign bit instructions only handle single source and target fp registers
403 ;; these instructions can only be used for TFmode values if the source and
404 ;; target operand uses the same fp register.
405 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
407 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
408 ;; This is used to disable the memory alternative in TFmode patterns.
409 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
411 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
412 ;; within instruction mnemonics.
413 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
415 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
416 ;; modes and to an empty string for bfp modes.
417 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
419 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
420 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
421 ;; version only operates on one register.
422 (define_mode_attr d0 [(DI "d") (SI "0")])
424 ;; In combination with d0 this allows to combine instructions of which the 31bit
425 ;; version only operates on one register. The DImode version needs an additional
426 ;; register for the assembler output.
427 (define_mode_attr 1 [(DI "%1,") (SI "")])
429 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
430 ;; 'ashift' and "srdl" in 'lshiftrt'.
431 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
433 ;; In SHIFT templates, this attribute holds the correct standard name for the
434 ;; pattern itself and the corresponding function calls.
435 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
437 ;; This attribute handles differences in the instruction 'type' and will result
438 ;; in "RRE" for DImode and "RR" for SImode.
439 (define_mode_attr E [(DI "E") (SI "")])
441 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
442 ;; to result in "RXY" for DImode and "RX" for SImode.
443 (define_mode_attr Y [(DI "Y") (SI "")])
445 ;; This attribute handles differences in the instruction 'type' and will result
446 ;; in "RSE" for TImode and "RS" for DImode.
447 (define_mode_attr TE [(TI "E") (DI "")])
449 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
450 ;; and "lcr" in SImode.
451 (define_mode_attr g [(DI "g") (SI "")])
453 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
454 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
455 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
456 ;; variant for long displacements.
457 (define_mode_attr y [(DI "g") (SI "y")])
459 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
460 ;; and "cds" in DImode.
461 (define_mode_attr tg [(TI "g") (DI "")])
463 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
464 ;; and "cfdbr" in SImode.
465 (define_mode_attr gf [(DI "g") (SI "f")])
467 ;; ICM mask required to load MODE value into the lowest subreg
468 ;; of a SImode register.
469 (define_mode_attr icm_lo [(HI "3") (QI "1")])
471 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
472 ;; HImode and "llgc" in QImode.
473 (define_mode_attr hc [(HI "h") (QI "c")])
475 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
477 (define_mode_attr DBL [(DI "TI") (SI "DI")])
479 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
480 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
481 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
483 ;; Maximum unsigned integer that fits in MODE.
484 (define_mode_attr max_uint [(HI "65535") (QI "255")])
487 ;;- Compare instructions.
490 ; Test-under-Mask instructions
492 (define_insn "*tmqi_mem"
493 [(set (reg CC_REGNUM)
494 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
495 (match_operand:QI 1 "immediate_operand" "n,n"))
496 (match_operand:QI 2 "immediate_operand" "n,n")))]
497 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
501 [(set_attr "op_type" "SI,SIY")
502 (set_attr "z10prop" "z10_super,z10_super")])
504 (define_insn "*tmdi_reg"
505 [(set (reg CC_REGNUM)
506 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
507 (match_operand:DI 1 "immediate_operand"
508 "N0HD0,N1HD0,N2HD0,N3HD0"))
509 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
511 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
512 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
518 [(set_attr "op_type" "RI")
519 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
521 (define_insn "*tmsi_reg"
522 [(set (reg CC_REGNUM)
523 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
524 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
525 (match_operand:SI 2 "immediate_operand" "n,n")))]
526 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
527 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
531 [(set_attr "op_type" "RI")
532 (set_attr "z10prop" "z10_super,z10_super")])
534 (define_insn "*tm<mode>_full"
535 [(set (reg CC_REGNUM)
536 (compare (match_operand:HQI 0 "register_operand" "d")
537 (match_operand:HQI 1 "immediate_operand" "n")))]
538 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
540 [(set_attr "op_type" "RI")
541 (set_attr "z10prop" "z10_super")])
545 ; Load-and-Test instructions
548 ; tst(di|si) instruction pattern(s).
550 (define_insn "*tstdi_sign"
551 [(set (reg CC_REGNUM)
555 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
556 (const_int 32)) (const_int 32))
557 (match_operand:DI 1 "const0_operand" "")))
558 (set (match_operand:DI 2 "register_operand" "=d,d")
559 (sign_extend:DI (match_dup 0)))]
560 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
563 [(set_attr "op_type" "RRE,RXY")
564 (set_attr "cpu_facility" "*,z10")
565 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
568 (define_insn "*tst<mode>_extimm"
569 [(set (reg CC_REGNUM)
570 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
571 (match_operand:GPR 1 "const0_operand" "")))
572 (set (match_operand:GPR 2 "register_operand" "=d,d")
574 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
578 [(set_attr "op_type" "RR<E>,RXY")
579 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
582 (define_insn "*tst<mode>_cconly_extimm"
583 [(set (reg CC_REGNUM)
584 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
585 (match_operand:GPR 1 "const0_operand" "")))
586 (clobber (match_scratch:GPR 2 "=X,d"))]
587 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
591 [(set_attr "op_type" "RR<E>,RXY")
592 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
594 (define_insn "*tstdi"
595 [(set (reg CC_REGNUM)
596 (compare (match_operand:DI 0 "register_operand" "d")
597 (match_operand:DI 1 "const0_operand" "")))
598 (set (match_operand:DI 2 "register_operand" "=d")
600 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
602 [(set_attr "op_type" "RRE")
603 (set_attr "z10prop" "z10_fr_E1")])
605 (define_insn "*tstsi"
606 [(set (reg CC_REGNUM)
607 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
608 (match_operand:SI 1 "const0_operand" "")))
609 (set (match_operand:SI 2 "register_operand" "=d,d,d")
611 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
616 [(set_attr "op_type" "RR,RS,RSY")
617 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
619 (define_insn "*tstsi_cconly"
620 [(set (reg CC_REGNUM)
621 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
622 (match_operand:SI 1 "const0_operand" "")))
623 (clobber (match_scratch:SI 2 "=X,d,d"))]
624 "s390_match_ccmode(insn, CCSmode)"
629 [(set_attr "op_type" "RR,RS,RSY")
630 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
632 (define_insn "*tstdi_cconly_31"
633 [(set (reg CC_REGNUM)
634 (compare (match_operand:DI 0 "register_operand" "d")
635 (match_operand:DI 1 "const0_operand" "")))]
636 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
638 [(set_attr "op_type" "RS")
639 (set_attr "atype" "reg")])
642 (define_insn "*tst<mode>_cconly2"
643 [(set (reg CC_REGNUM)
644 (compare (match_operand:GPR 0 "register_operand" "d")
645 (match_operand:GPR 1 "const0_operand" "")))]
646 "s390_match_ccmode(insn, CCSmode)"
648 [(set_attr "op_type" "RR<E>")
649 (set_attr "z10prop" "z10_fr_E1")])
651 ; tst(hi|qi) instruction pattern(s).
653 (define_insn "*tst<mode>CCT"
654 [(set (reg CC_REGNUM)
655 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
656 (match_operand:HQI 1 "const0_operand" "")))
657 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
659 "s390_match_ccmode(insn, CCTmode)"
662 icmy\t%2,<icm_lo>,%S0
664 [(set_attr "op_type" "RS,RSY,RI")
665 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
667 (define_insn "*tsthiCCT_cconly"
668 [(set (reg CC_REGNUM)
669 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
670 (match_operand:HI 1 "const0_operand" "")))
671 (clobber (match_scratch:HI 2 "=d,d,X"))]
672 "s390_match_ccmode(insn, CCTmode)"
677 [(set_attr "op_type" "RS,RSY,RI")
678 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
680 (define_insn "*tstqiCCT_cconly"
681 [(set (reg CC_REGNUM)
682 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
683 (match_operand:QI 1 "const0_operand" "")))]
684 "s390_match_ccmode(insn, CCTmode)"
689 [(set_attr "op_type" "SI,SIY,RI")
690 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
692 (define_insn "*tst<mode>"
693 [(set (reg CC_REGNUM)
694 (compare (match_operand:HQI 0 "s_operand" "Q,S")
695 (match_operand:HQI 1 "const0_operand" "")))
696 (set (match_operand:HQI 2 "register_operand" "=d,d")
698 "s390_match_ccmode(insn, CCSmode)"
701 icmy\t%2,<icm_lo>,%S0"
702 [(set_attr "op_type" "RS,RSY")
703 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
705 (define_insn "*tst<mode>_cconly"
706 [(set (reg CC_REGNUM)
707 (compare (match_operand:HQI 0 "s_operand" "Q,S")
708 (match_operand:HQI 1 "const0_operand" "")))
709 (clobber (match_scratch:HQI 2 "=d,d"))]
710 "s390_match_ccmode(insn, CCSmode)"
713 icmy\t%2,<icm_lo>,%S0"
714 [(set_attr "op_type" "RS,RSY")
715 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
718 ; Compare (equality) instructions
720 (define_insn "*cmpdi_cct"
721 [(set (reg CC_REGNUM)
722 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
723 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
724 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
731 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
732 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
734 (define_insn "*cmpsi_cct"
735 [(set (reg CC_REGNUM)
736 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
737 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
738 "s390_match_ccmode (insn, CCTmode)"
746 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
747 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
749 ; Compare (signed) instructions
751 (define_insn "*cmpdi_ccs_sign"
752 [(set (reg CC_REGNUM)
753 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
755 (match_operand:DI 0 "register_operand" "d, d,d")))]
756 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
761 [(set_attr "op_type" "RRE,RXY,RIL")
762 (set_attr "z10prop" "z10_c,*,*")
763 (set_attr "type" "*,*,larl")])
767 (define_insn "*cmpsi_ccs_sign"
768 [(set (reg CC_REGNUM)
769 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
770 (match_operand:SI 0 "register_operand" "d,d,d")))]
771 "s390_match_ccmode(insn, CCSRmode)"
776 [(set_attr "op_type" "RX,RXY,RIL")
777 (set_attr "cpu_facility" "*,*,z10")
778 (set_attr "type" "*,*,larl")])
780 (define_insn "*cmphi_ccs_z10"
781 [(set (reg CC_REGNUM)
782 (compare (match_operand:HI 0 "s_operand" "Q")
783 (match_operand:HI 1 "immediate_operand" "K")))]
784 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
786 [(set_attr "op_type" "SIL")])
788 (define_insn "*cmpdi_ccs_signhi_rl"
789 [(set (reg CC_REGNUM)
790 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
791 (match_operand:GPR 0 "register_operand" "d,d")))]
792 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
796 [(set_attr "op_type" "RXY,RIL")
797 (set_attr "type" "*,larl")])
799 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
800 (define_insn "*cmp<mode>_ccs"
801 [(set (reg CC_REGNUM)
802 (compare (match_operand:GPR 0 "nonimmediate_operand"
804 (match_operand:GPR 1 "general_operand"
806 "s390_match_ccmode(insn, CCSmode)"
815 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
816 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
817 (set_attr "type" "*,*,*,*,*,*,larl")
818 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
821 ; Compare (unsigned) instructions
823 (define_insn "*cmpsi_ccu_zerohi_rlsi"
824 [(set (reg CC_REGNUM)
825 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
826 "larl_operand" "X")))
827 (match_operand:SI 0 "register_operand" "d")))]
828 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
830 [(set_attr "op_type" "RIL")
831 (set_attr "type" "larl")
832 (set_attr "z10prop" "z10_super")])
835 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
836 [(set (reg CC_REGNUM)
837 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
838 "larl_operand" "X")))
839 (match_operand:GPR 0 "register_operand" "d")))]
840 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
842 [(set_attr "op_type" "RIL")
843 (set_attr "type" "larl")
844 (set_attr "z10prop" "z10_super")])
846 (define_insn "*cmpdi_ccu_zero"
847 [(set (reg CC_REGNUM)
848 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
850 (match_operand:DI 0 "register_operand" "d, d,d")))]
851 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
856 [(set_attr "op_type" "RRE,RXY,RIL")
857 (set_attr "cpu_facility" "*,*,z10")
858 (set_attr "type" "*,*,larl")
859 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
861 (define_insn "*cmpdi_ccu"
862 [(set (reg CC_REGNUM)
863 (compare (match_operand:DI 0 "nonimmediate_operand"
865 (match_operand:DI 1 "general_operand"
866 "d,Op,b,D,RT,BQ,Q")))]
867 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
876 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
877 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
878 (set_attr "type" "*,*,larl,*,*,*,*")
879 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
881 (define_insn "*cmpsi_ccu"
882 [(set (reg CC_REGNUM)
883 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
884 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
885 "s390_match_ccmode (insn, CCUmode)"
895 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
896 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
897 (set_attr "type" "*,*,larl,*,*,*,*,*")
898 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
900 (define_insn "*cmphi_ccu"
901 [(set (reg CC_REGNUM)
902 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
903 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
904 "s390_match_ccmode (insn, CCUmode)
905 && !register_operand (operands[1], HImode)"
912 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
913 (set_attr "cpu_facility" "*,*,z10,*,*")
914 (set_attr "z10prop" "*,*,z10_super,*,*")])
916 (define_insn "*cmpqi_ccu"
917 [(set (reg CC_REGNUM)
918 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
919 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
920 "s390_match_ccmode (insn, CCUmode)
921 && !register_operand (operands[1], QImode)"
929 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
930 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
933 ; Block compare (CLC) instruction patterns.
936 [(set (reg CC_REGNUM)
937 (compare (match_operand:BLK 0 "memory_operand" "Q")
938 (match_operand:BLK 1 "memory_operand" "Q")))
939 (use (match_operand 2 "const_int_operand" "n"))]
940 "s390_match_ccmode (insn, CCUmode)
941 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
942 "clc\t%O0(%2,%R0),%S1"
943 [(set_attr "op_type" "SS")])
946 [(set (reg CC_REGNUM)
947 (compare (match_operand 0 "memory_operand" "")
948 (match_operand 1 "memory_operand" "")))]
950 && s390_match_ccmode (insn, CCUmode)
951 && GET_MODE (operands[0]) == GET_MODE (operands[1])
952 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
954 [(set (match_dup 0) (match_dup 1))
955 (use (match_dup 2))])]
957 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
958 operands[0] = adjust_address (operands[0], BLKmode, 0);
959 operands[1] = adjust_address (operands[1], BLKmode, 0);
961 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
962 operands[0], operands[1]);
963 operands[0] = SET_DEST (PATTERN (curr_insn));
967 ; (TF|DF|SF|TD|DD|SD) instructions
969 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
970 (define_insn "*cmp<mode>_ccs_0"
971 [(set (reg CC_REGNUM)
972 (compare (match_operand:FP 0 "register_operand" "f")
973 (match_operand:FP 1 "const0_operand" "")))]
974 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
975 "lt<xde><bt>r\t%0,%0"
976 [(set_attr "op_type" "RRE")
977 (set_attr "type" "fsimp<mode>")])
979 ; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr
980 (define_insn "*cmp<mode>_ccs"
981 [(set (reg CC_REGNUM)
982 (compare (match_operand:FP 0 "register_operand" "f,f")
983 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
984 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
988 [(set_attr "op_type" "RRE,RXE")
989 (set_attr "type" "fsimp<mode>")])
992 ; Compare and Branch instructions
994 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
995 ; The following instructions do a complementary access of their second
996 ; operand (z01 only): crj_c, cgrjc, cr, cgr
997 (define_insn "*cmp_and_br_signed_<mode>"
999 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1000 [(match_operand:GPR 1 "register_operand" "d,d")
1001 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1002 (label_ref (match_operand 3 "" ""))
1004 (clobber (reg:CC CC_REGNUM))]
1007 if (get_attr_length (insn) == 6)
1008 return which_alternative ?
1009 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1011 return which_alternative ?
1012 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1014 [(set_attr "op_type" "RIE")
1015 (set_attr "type" "branch")
1016 (set_attr "z10prop" "z10_super_c,z10_super")
1017 (set (attr "length")
1018 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1019 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1020 ; 10 byte for cgr/jg
1022 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1023 ; The following instructions do a complementary access of their second
1024 ; operand (z10 only): clrj, clgrj, clr, clgr
1025 (define_insn "*cmp_and_br_unsigned_<mode>"
1027 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1028 [(match_operand:GPR 1 "register_operand" "d,d")
1029 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1030 (label_ref (match_operand 3 "" ""))
1032 (clobber (reg:CC CC_REGNUM))]
1035 if (get_attr_length (insn) == 6)
1036 return which_alternative ?
1037 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1039 return which_alternative ?
1040 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1042 [(set_attr "op_type" "RIE")
1043 (set_attr "type" "branch")
1044 (set_attr "z10prop" "z10_super_c,z10_super")
1045 (set (attr "length")
1046 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1047 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1048 ; 10 byte for clgr/jg
1050 ; And now the same two patterns as above but with a negated CC mask.
1052 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1053 ; The following instructions do a complementary access of their second
1054 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1055 (define_insn "*icmp_and_br_signed_<mode>"
1057 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1058 [(match_operand:GPR 1 "register_operand" "d,d")
1059 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1061 (label_ref (match_operand 3 "" ""))))
1062 (clobber (reg:CC CC_REGNUM))]
1065 if (get_attr_length (insn) == 6)
1066 return which_alternative ?
1067 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1069 return which_alternative ?
1070 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1072 [(set_attr "op_type" "RIE")
1073 (set_attr "type" "branch")
1074 (set_attr "z10prop" "z10_super_c,z10_super")
1075 (set (attr "length")
1076 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1077 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1078 ; 10 byte for cgr/jg
1080 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1081 ; The following instructions do a complementary access of their second
1082 ; operand (z10 only): clrj, clgrj, clr, clgr
1083 (define_insn "*icmp_and_br_unsigned_<mode>"
1085 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1086 [(match_operand:GPR 1 "register_operand" "d,d")
1087 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1089 (label_ref (match_operand 3 "" ""))))
1090 (clobber (reg:CC CC_REGNUM))]
1093 if (get_attr_length (insn) == 6)
1094 return which_alternative ?
1095 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1097 return which_alternative ?
1098 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1100 [(set_attr "op_type" "RIE")
1101 (set_attr "type" "branch")
1102 (set_attr "z10prop" "z10_super_c,z10_super")
1103 (set (attr "length")
1104 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1105 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1106 ; 10 byte for clgr/jg
1109 ;;- Move instructions.
1113 ; movti instruction pattern(s).
1116 (define_insn "movti"
1117 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1118 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1125 [(set_attr "op_type" "RSY,RSY,*,*")
1126 (set_attr "type" "lm,stm,*,*")])
1129 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1130 (match_operand:TI 1 "general_operand" ""))]
1131 "TARGET_ZARCH && reload_completed
1132 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1133 [(set (match_dup 2) (match_dup 4))
1134 (set (match_dup 3) (match_dup 5))]
1136 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1137 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1138 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1139 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1143 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1144 (match_operand:TI 1 "general_operand" ""))]
1145 "TARGET_ZARCH && reload_completed
1146 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1147 [(set (match_dup 2) (match_dup 4))
1148 (set (match_dup 3) (match_dup 5))]
1150 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1151 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1152 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1153 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1157 [(set (match_operand:TI 0 "register_operand" "")
1158 (match_operand:TI 1 "memory_operand" ""))]
1159 "TARGET_ZARCH && reload_completed
1160 && !s_operand (operands[1], VOIDmode)"
1161 [(set (match_dup 0) (match_dup 1))]
1163 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1164 addr = gen_lowpart (Pmode, addr);
1165 s390_load_address (addr, XEXP (operands[1], 0));
1166 operands[1] = replace_equiv_address (operands[1], addr);
1171 ; Patterns used for secondary reloads
1174 ; z10 provides move instructions accepting larl memory operands.
1175 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1176 ; These patterns are also used for unaligned SI and DI accesses.
1178 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1179 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1180 (match_operand:INTALL 1 "register_operand" "=d")
1181 (match_operand:P 2 "register_operand" "=&a")])]
1184 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1188 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1189 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1190 (match_operand:INTALL 1 "memory_operand" "")
1191 (match_operand:P 2 "register_operand" "=a")])]
1194 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1198 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1199 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1200 (match_operand:FPALL 1 "register_operand" "=d")
1201 (match_operand:P 2 "register_operand" "=&a")])]
1204 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1208 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1209 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1210 (match_operand:FPALL 1 "memory_operand" "")
1211 (match_operand:P 2 "register_operand" "=a")])]
1214 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1218 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1219 [(parallel [(match_operand:P 0 "register_operand" "=d")
1220 (match_operand:P 1 "larl_operand" "")
1221 (match_operand:P 2 "register_operand" "=a")])]
1224 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1228 ; Handles loading a PLUS (load address) expression
1230 (define_expand "reload<mode>_plus"
1231 [(parallel [(match_operand:P 0 "register_operand" "=a")
1232 (match_operand:P 1 "s390_plus_operand" "")
1233 (match_operand:P 2 "register_operand" "=&a")])]
1236 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1240 ; Handles assessing a non-offsetable memory address
1242 (define_expand "reload<mode>_nonoffmem_in"
1243 [(parallel [(match_operand 0 "register_operand" "")
1244 (match_operand 1 "" "")
1245 (match_operand:P 2 "register_operand" "=&a")])]
1248 gcc_assert (MEM_P (operands[1]));
1249 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1250 operands[1] = replace_equiv_address (operands[1], operands[2]);
1251 emit_move_insn (operands[0], operands[1]);
1255 (define_expand "reload<mode>_nonoffmem_out"
1256 [(parallel [(match_operand 0 "" "")
1257 (match_operand 1 "register_operand" "")
1258 (match_operand:P 2 "register_operand" "=&a")])]
1261 gcc_assert (MEM_P (operands[0]));
1262 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1263 operands[0] = replace_equiv_address (operands[0], operands[2]);
1264 emit_move_insn (operands[0], operands[1]);
1268 (define_expand "reload<mode>_PIC_addr"
1269 [(parallel [(match_operand 0 "register_operand" "=d")
1270 (match_operand 1 "larl_operand" "")
1271 (match_operand:P 2 "register_operand" "=a")])]
1274 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1275 emit_move_insn (operands[0], new_rtx);
1279 ; movdi instruction pattern(s).
1282 (define_expand "movdi"
1283 [(set (match_operand:DI 0 "general_operand" "")
1284 (match_operand:DI 1 "general_operand" ""))]
1287 /* Handle symbolic constants. */
1289 && (SYMBOLIC_CONST (operands[1])
1290 || (GET_CODE (operands[1]) == PLUS
1291 && XEXP (operands[1], 0) == pic_offset_table_rtx
1292 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1293 emit_symbolic_move (operands);
1296 (define_insn "*movdi_larl"
1297 [(set (match_operand:DI 0 "register_operand" "=d")
1298 (match_operand:DI 1 "larl_operand" "X"))]
1300 && !FP_REG_P (operands[0])"
1302 [(set_attr "op_type" "RIL")
1303 (set_attr "type" "larl")
1304 (set_attr "z10prop" "z10_super_A1")])
1306 (define_insn "*movdi_64"
1307 [(set (match_operand:DI 0 "nonimmediate_operand"
1308 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1309 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1310 (match_operand:DI 1 "general_operand"
1311 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1312 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1341 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1342 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1343 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1344 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1346 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1347 z10,*,*,*,*,*,longdisp,*,longdisp,
1349 (set_attr "z10prop" "z10_fwd_A1,
1378 [(set (match_operand:DI 0 "register_operand" "")
1379 (match_operand:DI 1 "register_operand" ""))]
1380 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1381 [(set (match_dup 2) (match_dup 3))
1382 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1383 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1384 "operands[2] = gen_lowpart (SImode, operands[0]);
1385 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1388 [(set (match_operand:DI 0 "register_operand" "")
1389 (match_operand:DI 1 "register_operand" ""))]
1390 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1391 && dead_or_set_p (insn, operands[1])"
1392 [(set (match_dup 3) (match_dup 2))
1393 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1394 (set (match_dup 4) (match_dup 2))]
1395 "operands[2] = gen_lowpart (SImode, operands[1]);
1396 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1399 [(set (match_operand:DI 0 "register_operand" "")
1400 (match_operand:DI 1 "register_operand" ""))]
1401 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1402 && !dead_or_set_p (insn, operands[1])"
1403 [(set (match_dup 3) (match_dup 2))
1404 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1405 (set (match_dup 4) (match_dup 2))
1406 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1407 "operands[2] = gen_lowpart (SImode, operands[1]);
1408 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1410 (define_insn "*movdi_31"
1411 [(set (match_operand:DI 0 "nonimmediate_operand"
1412 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1413 (match_operand:DI 1 "general_operand"
1414 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1429 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1430 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1431 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1433 ; For a load from a symbol ref we can use one of the target registers
1434 ; together with larl to load the address.
1436 [(set (match_operand:DI 0 "register_operand" "")
1437 (match_operand:DI 1 "memory_operand" ""))]
1438 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1439 && larl_operand (XEXP (operands[1], 0), SImode)"
1440 [(set (match_dup 2) (match_dup 3))
1441 (set (match_dup 0) (match_dup 1))]
1443 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1444 operands[3] = XEXP (operands[1], 0);
1445 operands[1] = replace_equiv_address (operands[1], operands[2]);
1449 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1450 (match_operand:DI 1 "general_operand" ""))]
1451 "!TARGET_ZARCH && reload_completed
1452 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1453 [(set (match_dup 2) (match_dup 4))
1454 (set (match_dup 3) (match_dup 5))]
1456 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1457 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1458 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1459 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1463 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1464 (match_operand:DI 1 "general_operand" ""))]
1465 "!TARGET_ZARCH && reload_completed
1466 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1467 [(set (match_dup 2) (match_dup 4))
1468 (set (match_dup 3) (match_dup 5))]
1470 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1471 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1472 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1473 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1477 [(set (match_operand:DI 0 "register_operand" "")
1478 (match_operand:DI 1 "memory_operand" ""))]
1479 "!TARGET_ZARCH && reload_completed
1480 && !FP_REG_P (operands[0])
1481 && !s_operand (operands[1], VOIDmode)"
1482 [(set (match_dup 0) (match_dup 1))]
1484 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1485 s390_load_address (addr, XEXP (operands[1], 0));
1486 operands[1] = replace_equiv_address (operands[1], addr);
1490 [(set (match_operand:DI 0 "register_operand" "")
1491 (mem:DI (match_operand 1 "address_operand" "")))]
1493 && !FP_REG_P (operands[0])
1494 && GET_CODE (operands[1]) == SYMBOL_REF
1495 && CONSTANT_POOL_ADDRESS_P (operands[1])
1496 && get_pool_mode (operands[1]) == DImode
1497 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1498 [(set (match_dup 0) (match_dup 2))]
1499 "operands[2] = get_pool_constant (operands[1]);")
1501 (define_insn "*la_64"
1502 [(set (match_operand:DI 0 "register_operand" "=d,d")
1503 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1508 [(set_attr "op_type" "RX,RXY")
1509 (set_attr "type" "la")
1510 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1514 [(set (match_operand:DI 0 "register_operand" "")
1515 (match_operand:QI 1 "address_operand" ""))
1516 (clobber (reg:CC CC_REGNUM))])]
1518 && preferred_la_operand_p (operands[1], const0_rtx)"
1519 [(set (match_dup 0) (match_dup 1))]
1523 [(set (match_operand:DI 0 "register_operand" "")
1524 (match_operand:DI 1 "register_operand" ""))
1527 (plus:DI (match_dup 0)
1528 (match_operand:DI 2 "nonmemory_operand" "")))
1529 (clobber (reg:CC CC_REGNUM))])]
1531 && !reg_overlap_mentioned_p (operands[0], operands[2])
1532 && preferred_la_operand_p (operands[1], operands[2])"
1533 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1537 ; movsi instruction pattern(s).
1540 (define_expand "movsi"
1541 [(set (match_operand:SI 0 "general_operand" "")
1542 (match_operand:SI 1 "general_operand" ""))]
1545 /* Handle symbolic constants. */
1547 && (SYMBOLIC_CONST (operands[1])
1548 || (GET_CODE (operands[1]) == PLUS
1549 && XEXP (operands[1], 0) == pic_offset_table_rtx
1550 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1551 emit_symbolic_move (operands);
1554 (define_insn "*movsi_larl"
1555 [(set (match_operand:SI 0 "register_operand" "=d")
1556 (match_operand:SI 1 "larl_operand" "X"))]
1557 "!TARGET_64BIT && TARGET_CPU_ZARCH
1558 && !FP_REG_P (operands[0])"
1560 [(set_attr "op_type" "RIL")
1561 (set_attr "type" "larl")
1562 (set_attr "z10prop" "z10_fwd_A1")])
1564 (define_insn "*movsi_zarch"
1565 [(set (match_operand:SI 0 "nonimmediate_operand"
1566 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1567 (match_operand:SI 1 "general_operand"
1568 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1593 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1594 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1595 (set_attr "type" "*,
1617 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1618 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1619 (set_attr "z10prop" "z10_fwd_A1,
1642 (define_insn "*movsi_esa"
1643 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1644 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1658 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1659 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1660 (set_attr "z10prop" "z10_fwd_A1,
1674 [(set (match_operand:SI 0 "register_operand" "")
1675 (mem:SI (match_operand 1 "address_operand" "")))]
1676 "!FP_REG_P (operands[0])
1677 && GET_CODE (operands[1]) == SYMBOL_REF
1678 && CONSTANT_POOL_ADDRESS_P (operands[1])
1679 && get_pool_mode (operands[1]) == SImode
1680 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1681 [(set (match_dup 0) (match_dup 2))]
1682 "operands[2] = get_pool_constant (operands[1]);")
1684 (define_insn "*la_31"
1685 [(set (match_operand:SI 0 "register_operand" "=d,d")
1686 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1687 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1691 [(set_attr "op_type" "RX,RXY")
1692 (set_attr "type" "la")
1693 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1697 [(set (match_operand:SI 0 "register_operand" "")
1698 (match_operand:QI 1 "address_operand" ""))
1699 (clobber (reg:CC CC_REGNUM))])]
1701 && preferred_la_operand_p (operands[1], const0_rtx)"
1702 [(set (match_dup 0) (match_dup 1))]
1706 [(set (match_operand:SI 0 "register_operand" "")
1707 (match_operand:SI 1 "register_operand" ""))
1710 (plus:SI (match_dup 0)
1711 (match_operand:SI 2 "nonmemory_operand" "")))
1712 (clobber (reg:CC CC_REGNUM))])]
1714 && !reg_overlap_mentioned_p (operands[0], operands[2])
1715 && preferred_la_operand_p (operands[1], operands[2])"
1716 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1719 (define_insn "*la_31_and"
1720 [(set (match_operand:SI 0 "register_operand" "=d,d")
1721 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1722 (const_int 2147483647)))]
1727 [(set_attr "op_type" "RX,RXY")
1728 (set_attr "type" "la")
1729 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1731 (define_insn_and_split "*la_31_and_cc"
1732 [(set (match_operand:SI 0 "register_operand" "=d")
1733 (and:SI (match_operand:QI 1 "address_operand" "p")
1734 (const_int 2147483647)))
1735 (clobber (reg:CC CC_REGNUM))]
1738 "&& reload_completed"
1740 (and:SI (match_dup 1) (const_int 2147483647)))]
1742 [(set_attr "op_type" "RX")
1743 (set_attr "type" "la")])
1745 (define_insn "force_la_31"
1746 [(set (match_operand:SI 0 "register_operand" "=d,d")
1747 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1748 (use (const_int 0))]
1753 [(set_attr "op_type" "RX")
1754 (set_attr "type" "la")
1755 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1758 ; movhi instruction pattern(s).
1761 (define_expand "movhi"
1762 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1763 (match_operand:HI 1 "general_operand" ""))]
1766 /* Make it explicit that loading a register from memory
1767 always sign-extends (at least) to SImode. */
1768 if (optimize && can_create_pseudo_p ()
1769 && register_operand (operands[0], VOIDmode)
1770 && GET_CODE (operands[1]) == MEM)
1772 rtx tmp = gen_reg_rtx (SImode);
1773 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1774 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1775 operands[1] = gen_lowpart (HImode, tmp);
1779 (define_insn "*movhi"
1780 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1781 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1793 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1794 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1795 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1796 (set_attr "z10prop" "z10_fr_E1,
1807 [(set (match_operand:HI 0 "register_operand" "")
1808 (mem:HI (match_operand 1 "address_operand" "")))]
1809 "GET_CODE (operands[1]) == SYMBOL_REF
1810 && CONSTANT_POOL_ADDRESS_P (operands[1])
1811 && get_pool_mode (operands[1]) == HImode
1812 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1813 [(set (match_dup 0) (match_dup 2))]
1814 "operands[2] = get_pool_constant (operands[1]);")
1817 ; movqi instruction pattern(s).
1820 (define_expand "movqi"
1821 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1822 (match_operand:QI 1 "general_operand" ""))]
1825 /* On z/Architecture, zero-extending from memory to register
1826 is just as fast as a QImode load. */
1827 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1828 && register_operand (operands[0], VOIDmode)
1829 && GET_CODE (operands[1]) == MEM)
1831 rtx tmp = gen_reg_rtx (DImode);
1832 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1833 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1834 operands[1] = gen_lowpart (QImode, tmp);
1838 (define_insn "*movqi"
1839 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1840 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1852 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1853 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1854 (set_attr "z10prop" "z10_fr_E1,
1865 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1866 (mem:QI (match_operand 1 "address_operand" "")))]
1867 "GET_CODE (operands[1]) == SYMBOL_REF
1868 && CONSTANT_POOL_ADDRESS_P (operands[1])
1869 && get_pool_mode (operands[1]) == QImode
1870 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1871 [(set (match_dup 0) (match_dup 2))]
1872 "operands[2] = get_pool_constant (operands[1]);")
1875 ; movstrictqi instruction pattern(s).
1878 (define_insn "*movstrictqi"
1879 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1880 (match_operand:QI 1 "memory_operand" "R,T"))]
1885 [(set_attr "op_type" "RX,RXY")
1886 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1889 ; movstricthi instruction pattern(s).
1892 (define_insn "*movstricthi"
1893 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1894 (match_operand:HI 1 "memory_operand" "Q,S"))
1895 (clobber (reg:CC CC_REGNUM))]
1900 [(set_attr "op_type" "RS,RSY")
1901 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1904 ; movstrictsi instruction pattern(s).
1907 (define_insn "movstrictsi"
1908 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1909 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1916 [(set_attr "op_type" "RR,RX,RXY,RRE")
1917 (set_attr "type" "lr,load,load,*")
1918 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1921 ; mov(tf|td) instruction pattern(s).
1924 (define_expand "mov<mode>"
1925 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1926 (match_operand:TD_TF 1 "general_operand" ""))]
1930 (define_insn "*mov<mode>_64"
1931 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,o, d,QS, d,o")
1932 (match_operand:TD_TF 1 "general_operand" " f,o,f,QS, d,dRT,d"))]
1942 [(set_attr "op_type" "RRE,*,*,RSY,RSY,*,*")
1943 (set_attr "type" "fsimptf,*,*,lm,stm,*,*")])
1945 (define_insn "*mov<mode>_31"
1946 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,o")
1947 (match_operand:TD_TF 1 "general_operand" " f,o,f"))]
1953 [(set_attr "op_type" "RRE,*,*")
1954 (set_attr "type" "fsimptf,*,*")])
1956 ; TFmode in GPRs splitters
1959 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1960 (match_operand:TD_TF 1 "general_operand" ""))]
1961 "TARGET_ZARCH && reload_completed
1962 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
1963 [(set (match_dup 2) (match_dup 4))
1964 (set (match_dup 3) (match_dup 5))]
1966 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
1967 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
1968 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
1969 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
1973 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1974 (match_operand:TD_TF 1 "general_operand" ""))]
1975 "TARGET_ZARCH && reload_completed
1976 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
1977 [(set (match_dup 2) (match_dup 4))
1978 (set (match_dup 3) (match_dup 5))]
1980 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
1981 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
1982 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
1983 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
1987 [(set (match_operand:TD_TF 0 "register_operand" "")
1988 (match_operand:TD_TF 1 "memory_operand" ""))]
1989 "TARGET_ZARCH && reload_completed
1990 && !FP_REG_P (operands[0])
1991 && !s_operand (operands[1], VOIDmode)"
1992 [(set (match_dup 0) (match_dup 1))]
1994 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
1995 s390_load_address (addr, XEXP (operands[1], 0));
1996 operands[1] = replace_equiv_address (operands[1], addr);
1999 ; TFmode in BFPs splitters
2002 [(set (match_operand:TD_TF 0 "register_operand" "")
2003 (match_operand:TD_TF 1 "memory_operand" ""))]
2004 "reload_completed && offsettable_memref_p (operands[1])
2005 && FP_REG_P (operands[0])"
2006 [(set (match_dup 2) (match_dup 4))
2007 (set (match_dup 3) (match_dup 5))]
2009 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2011 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2013 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2014 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2018 [(set (match_operand:TD_TF 0 "memory_operand" "")
2019 (match_operand:TD_TF 1 "register_operand" ""))]
2020 "reload_completed && offsettable_memref_p (operands[0])
2021 && FP_REG_P (operands[1])"
2022 [(set (match_dup 2) (match_dup 4))
2023 (set (match_dup 3) (match_dup 5))]
2025 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2026 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2027 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2029 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2034 ; mov(df|dd) instruction pattern(s).
2037 (define_expand "mov<mode>"
2038 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2039 (match_operand:DD_DF 1 "general_operand" ""))]
2043 (define_insn "*mov<mode>_64dfp"
2044 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2045 "=f,f,d,f,f,R,T,d, d,RT")
2046 (match_operand:DD_DF 1 "general_operand"
2047 " f,d,f,R,T,f,f,d,RT, d"))]
2060 [(set_attr "op_type" "RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
2061 (set_attr "type" "floaddf,floaddf,floaddf,floaddf,floaddf,
2062 fstoredf,fstoredf,lr,load,store")
2063 (set_attr "z10prop" "*,*,*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_rec")
2066 (define_insn "*mov<mode>_64"
2067 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,R,T,d, d,RT")
2068 (match_operand:DD_DF 1 "general_operand" "f,R,T,f,f,d,RT, d"))]
2079 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
2080 (set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
2081 fstore<mode>,fstore<mode>,lr,load,store")
2082 (set_attr "z10prop" "*,*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_rec")])
2084 (define_insn "*mov<mode>_31"
2085 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2086 "=f,f,f,R,T,d,d,Q,S, d,o")
2087 (match_operand:DD_DF 1 "general_operand"
2088 " f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2102 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2103 (set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
2104 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
2107 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2108 (match_operand:DD_DF 1 "general_operand" ""))]
2109 "!TARGET_ZARCH && reload_completed
2110 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2111 [(set (match_dup 2) (match_dup 4))
2112 (set (match_dup 3) (match_dup 5))]
2114 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2115 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2116 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2117 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2121 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2122 (match_operand:DD_DF 1 "general_operand" ""))]
2123 "!TARGET_ZARCH && reload_completed
2124 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2125 [(set (match_dup 2) (match_dup 4))
2126 (set (match_dup 3) (match_dup 5))]
2128 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2129 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2130 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2131 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2135 [(set (match_operand:DD_DF 0 "register_operand" "")
2136 (match_operand:DD_DF 1 "memory_operand" ""))]
2137 "!TARGET_ZARCH && reload_completed
2138 && !FP_REG_P (operands[0])
2139 && !s_operand (operands[1], VOIDmode)"
2140 [(set (match_dup 0) (match_dup 1))]
2142 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2143 s390_load_address (addr, XEXP (operands[1], 0));
2144 operands[1] = replace_equiv_address (operands[1], addr);
2148 ; mov(sf|sd) instruction pattern(s).
2151 (define_insn "mov<mode>"
2152 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2153 "=f,f,f,R,T,d,d,d,R,T")
2154 (match_operand:SD_SF 1 "general_operand"
2155 " f,R,T,f,f,d,R,T,d,d"))]
2168 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
2169 (set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
2170 fstore<mode>,fstore<mode>,lr,load,load,store,store")
2171 (set_attr "z10prop" "*,*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")])
2174 ; movcc instruction pattern
2177 (define_insn "movcc"
2178 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2179 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2189 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2190 (set_attr "type" "lr,*,*,store,store,load,load")
2191 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")])
2194 ; Block move (MVC) patterns.
2198 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2199 (match_operand:BLK 1 "memory_operand" "Q"))
2200 (use (match_operand 2 "const_int_operand" "n"))]
2201 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2202 "mvc\t%O0(%2,%R0),%S1"
2203 [(set_attr "op_type" "SS")])
2205 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2206 ; order to have it implemented with mvc.
2209 [(set (match_operand:QI 0 "memory_operand" "")
2210 (match_operand:QI 1 "memory_operand" ""))]
2213 [(set (match_dup 0) (match_dup 1))
2214 (use (const_int 1))])]
2216 operands[0] = adjust_address (operands[0], BLKmode, 0);
2217 operands[1] = adjust_address (operands[1], BLKmode, 0);
2223 [(set (match_operand:BLK 0 "memory_operand" "")
2224 (match_operand:BLK 1 "memory_operand" ""))
2225 (use (match_operand 2 "const_int_operand" ""))])
2227 [(set (match_operand:BLK 3 "memory_operand" "")
2228 (match_operand:BLK 4 "memory_operand" ""))
2229 (use (match_operand 5 "const_int_operand" ""))])]
2230 "s390_offset_p (operands[0], operands[3], operands[2])
2231 && s390_offset_p (operands[1], operands[4], operands[2])
2232 && !s390_overlap_p (operands[0], operands[1],
2233 INTVAL (operands[2]) + INTVAL (operands[5]))
2234 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2236 [(set (match_dup 6) (match_dup 7))
2237 (use (match_dup 8))])]
2238 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2239 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2240 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2244 ; load_multiple pattern(s).
2246 ; ??? Due to reload problems with replacing registers inside match_parallel
2247 ; we currently support load_multiple/store_multiple only after reload.
2250 (define_expand "load_multiple"
2251 [(match_par_dup 3 [(set (match_operand 0 "" "")
2252 (match_operand 1 "" ""))
2253 (use (match_operand 2 "" ""))])]
2256 enum machine_mode mode;
2262 /* Support only loading a constant number of fixed-point registers from
2263 memory and only bother with this if more than two */
2264 if (GET_CODE (operands[2]) != CONST_INT
2265 || INTVAL (operands[2]) < 2
2266 || INTVAL (operands[2]) > 16
2267 || GET_CODE (operands[1]) != MEM
2268 || GET_CODE (operands[0]) != REG
2269 || REGNO (operands[0]) >= 16)
2272 count = INTVAL (operands[2]);
2273 regno = REGNO (operands[0]);
2274 mode = GET_MODE (operands[0]);
2275 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2278 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2279 if (!can_create_pseudo_p ())
2281 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2283 from = XEXP (operands[1], 0);
2286 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2287 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2288 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2290 from = XEXP (XEXP (operands[1], 0), 0);
2291 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2298 from = force_reg (Pmode, XEXP (operands[1], 0));
2302 for (i = 0; i < count; i++)
2303 XVECEXP (operands[3], 0, i)
2304 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2305 change_address (operands[1], mode,
2306 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
2309 (define_insn "*load_multiple_di"
2310 [(match_parallel 0 "load_multiple_operation"
2311 [(set (match_operand:DI 1 "register_operand" "=r")
2312 (match_operand:DI 2 "s_operand" "QS"))])]
2313 "reload_completed && TARGET_ZARCH"
2315 int words = XVECLEN (operands[0], 0);
2316 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2317 return "lmg\t%1,%0,%S2";
2319 [(set_attr "op_type" "RSY")
2320 (set_attr "type" "lm")])
2322 (define_insn "*load_multiple_si"
2323 [(match_parallel 0 "load_multiple_operation"
2324 [(set (match_operand:SI 1 "register_operand" "=r,r")
2325 (match_operand:SI 2 "s_operand" "Q,S"))])]
2328 int words = XVECLEN (operands[0], 0);
2329 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2330 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2332 [(set_attr "op_type" "RS,RSY")
2333 (set_attr "type" "lm")])
2336 ; store multiple pattern(s).
2339 (define_expand "store_multiple"
2340 [(match_par_dup 3 [(set (match_operand 0 "" "")
2341 (match_operand 1 "" ""))
2342 (use (match_operand 2 "" ""))])]
2345 enum machine_mode mode;
2351 /* Support only storing a constant number of fixed-point registers to
2352 memory and only bother with this if more than two. */
2353 if (GET_CODE (operands[2]) != CONST_INT
2354 || INTVAL (operands[2]) < 2
2355 || INTVAL (operands[2]) > 16
2356 || GET_CODE (operands[0]) != MEM
2357 || GET_CODE (operands[1]) != REG
2358 || REGNO (operands[1]) >= 16)
2361 count = INTVAL (operands[2]);
2362 regno = REGNO (operands[1]);
2363 mode = GET_MODE (operands[1]);
2364 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2367 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2369 if (!can_create_pseudo_p ())
2371 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2373 to = XEXP (operands[0], 0);
2376 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2377 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2378 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2380 to = XEXP (XEXP (operands[0], 0), 0);
2381 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2388 to = force_reg (Pmode, XEXP (operands[0], 0));
2392 for (i = 0; i < count; i++)
2393 XVECEXP (operands[3], 0, i)
2394 = gen_rtx_SET (VOIDmode,
2395 change_address (operands[0], mode,
2396 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
2397 gen_rtx_REG (mode, regno + i));
2400 (define_insn "*store_multiple_di"
2401 [(match_parallel 0 "store_multiple_operation"
2402 [(set (match_operand:DI 1 "s_operand" "=QS")
2403 (match_operand:DI 2 "register_operand" "r"))])]
2404 "reload_completed && TARGET_ZARCH"
2406 int words = XVECLEN (operands[0], 0);
2407 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2408 return "stmg\t%2,%0,%S1";
2410 [(set_attr "op_type" "RSY")
2411 (set_attr "type" "stm")])
2414 (define_insn "*store_multiple_si"
2415 [(match_parallel 0 "store_multiple_operation"
2416 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2417 (match_operand:SI 2 "register_operand" "r,r"))])]
2420 int words = XVECLEN (operands[0], 0);
2421 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2422 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2424 [(set_attr "op_type" "RS,RSY")
2425 (set_attr "type" "stm")])
2428 ;; String instructions.
2431 (define_insn "*execute_rl"
2432 [(match_parallel 0 ""
2433 [(unspec [(match_operand 1 "register_operand" "a")
2434 (match_operand 2 "" "")
2435 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2436 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2437 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2439 [(set_attr "op_type" "RIL")
2440 (set_attr "type" "cs")])
2442 (define_insn "*execute"
2443 [(match_parallel 0 ""
2444 [(unspec [(match_operand 1 "register_operand" "a")
2445 (match_operand:BLK 2 "memory_operand" "R")
2446 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2447 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2448 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2450 [(set_attr "op_type" "RX")
2451 (set_attr "type" "cs")])
2455 ; strlenM instruction pattern(s).
2458 (define_expand "strlen<mode>"
2459 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2462 (unspec:P [(const_int 0)
2463 (match_operand:BLK 1 "memory_operand" "")
2465 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2466 (clobber (scratch:P))
2467 (clobber (reg:CC CC_REGNUM))])
2469 [(set (match_operand:P 0 "register_operand" "")
2470 (minus:P (match_dup 4) (match_dup 5)))
2471 (clobber (reg:CC CC_REGNUM))])]
2474 operands[4] = gen_reg_rtx (Pmode);
2475 operands[5] = gen_reg_rtx (Pmode);
2476 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2477 operands[1] = replace_equiv_address (operands[1], operands[5]);
2480 (define_insn "*strlen<mode>"
2481 [(set (match_operand:P 0 "register_operand" "=a")
2482 (unspec:P [(match_operand:P 2 "general_operand" "0")
2483 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2485 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2486 (clobber (match_scratch:P 1 "=a"))
2487 (clobber (reg:CC CC_REGNUM))]
2489 "srst\t%0,%1\;jo\t.-4"
2490 [(set_attr "length" "8")
2491 (set_attr "type" "vs")])
2494 ; cmpstrM instruction pattern(s).
2497 (define_expand "cmpstrsi"
2498 [(set (reg:SI 0) (const_int 0))
2500 [(clobber (match_operand 3 "" ""))
2501 (clobber (match_dup 4))
2502 (set (reg:CCU CC_REGNUM)
2503 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2504 (match_operand:BLK 2 "memory_operand" "")))
2507 [(set (match_operand:SI 0 "register_operand" "=d")
2508 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2509 (clobber (reg:CC CC_REGNUM))])]
2512 /* As the result of CMPINT is inverted compared to what we need,
2513 we have to swap the operands. */
2514 rtx op1 = operands[2];
2515 rtx op2 = operands[1];
2516 rtx addr1 = gen_reg_rtx (Pmode);
2517 rtx addr2 = gen_reg_rtx (Pmode);
2519 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2520 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2521 operands[1] = replace_equiv_address_nv (op1, addr1);
2522 operands[2] = replace_equiv_address_nv (op2, addr2);
2523 operands[3] = addr1;
2524 operands[4] = addr2;
2527 (define_insn "*cmpstr<mode>"
2528 [(clobber (match_operand:P 0 "register_operand" "=d"))
2529 (clobber (match_operand:P 1 "register_operand" "=d"))
2530 (set (reg:CCU CC_REGNUM)
2531 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2532 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2535 "clst\t%0,%1\;jo\t.-4"
2536 [(set_attr "length" "8")
2537 (set_attr "type" "vs")])
2540 ; movstr instruction pattern.
2543 (define_expand "movstr"
2544 [(set (reg:SI 0) (const_int 0))
2546 [(clobber (match_dup 3))
2547 (set (match_operand:BLK 1 "memory_operand" "")
2548 (match_operand:BLK 2 "memory_operand" ""))
2549 (set (match_operand 0 "register_operand" "")
2550 (unspec [(match_dup 1)
2552 (reg:SI 0)] UNSPEC_MVST))
2553 (clobber (reg:CC CC_REGNUM))])]
2556 rtx addr1 = gen_reg_rtx (Pmode);
2557 rtx addr2 = gen_reg_rtx (Pmode);
2559 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2560 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2561 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2562 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2563 operands[3] = addr2;
2566 (define_insn "*movstr"
2567 [(clobber (match_operand:P 2 "register_operand" "=d"))
2568 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2569 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2570 (set (match_operand:P 0 "register_operand" "=d")
2571 (unspec [(mem:BLK (match_dup 1))
2572 (mem:BLK (match_dup 3))
2573 (reg:SI 0)] UNSPEC_MVST))
2574 (clobber (reg:CC CC_REGNUM))]
2576 "mvst\t%1,%2\;jo\t.-4"
2577 [(set_attr "length" "8")
2578 (set_attr "type" "vs")])
2582 ; movmemM instruction pattern(s).
2585 (define_expand "movmem<mode>"
2586 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2587 (match_operand:BLK 1 "memory_operand" "")) ; source
2588 (use (match_operand:GPR 2 "general_operand" "")) ; count
2589 (match_operand 3 "" "")]
2591 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2593 ; Move a block that is up to 256 bytes in length.
2594 ; The block length is taken as (operands[2] % 256) + 1.
2596 (define_expand "movmem_short"
2598 [(set (match_operand:BLK 0 "memory_operand" "")
2599 (match_operand:BLK 1 "memory_operand" ""))
2600 (use (match_operand 2 "nonmemory_operand" ""))
2601 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2602 (clobber (match_dup 3))])]
2604 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2606 (define_insn "*movmem_short"
2607 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2608 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2609 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2610 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2611 (clobber (match_scratch 4 "=X,X,X,&a"))]
2612 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2613 && GET_MODE (operands[4]) == Pmode"
2615 [(set_attr "type" "cs")
2616 (set_attr "cpu_facility" "*,*,z10,*")])
2619 [(set (match_operand:BLK 0 "memory_operand" "")
2620 (match_operand:BLK 1 "memory_operand" ""))
2621 (use (match_operand 2 "const_int_operand" ""))
2622 (use (match_operand 3 "immediate_operand" ""))
2623 (clobber (scratch))]
2626 [(set (match_dup 0) (match_dup 1))
2627 (use (match_dup 2))])]
2628 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2631 [(set (match_operand:BLK 0 "memory_operand" "")
2632 (match_operand:BLK 1 "memory_operand" ""))
2633 (use (match_operand 2 "register_operand" ""))
2634 (use (match_operand 3 "memory_operand" ""))
2635 (clobber (scratch))]
2638 [(unspec [(match_dup 2) (match_dup 3)
2639 (const_int 0)] UNSPEC_EXECUTE)
2640 (set (match_dup 0) (match_dup 1))
2641 (use (const_int 1))])]
2645 [(set (match_operand:BLK 0 "memory_operand" "")
2646 (match_operand:BLK 1 "memory_operand" ""))
2647 (use (match_operand 2 "register_operand" ""))
2648 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2649 (clobber (scratch))]
2650 "TARGET_Z10 && reload_completed"
2652 [(unspec [(match_dup 2) (const_int 0)
2653 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2654 (set (match_dup 0) (match_dup 1))
2655 (use (const_int 1))])]
2656 "operands[3] = gen_label_rtx ();")
2659 [(set (match_operand:BLK 0 "memory_operand" "")
2660 (match_operand:BLK 1 "memory_operand" ""))
2661 (use (match_operand 2 "register_operand" ""))
2662 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2663 (clobber (match_operand 3 "register_operand" ""))]
2664 "reload_completed && TARGET_CPU_ZARCH"
2665 [(set (match_dup 3) (label_ref (match_dup 4)))
2667 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2668 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2669 (set (match_dup 0) (match_dup 1))
2670 (use (const_int 1))])]
2671 "operands[4] = gen_label_rtx ();")
2673 ; Move a block of arbitrary length.
2675 (define_expand "movmem_long"
2677 [(clobber (match_dup 2))
2678 (clobber (match_dup 3))
2679 (set (match_operand:BLK 0 "memory_operand" "")
2680 (match_operand:BLK 1 "memory_operand" ""))
2681 (use (match_operand 2 "general_operand" ""))
2683 (clobber (reg:CC CC_REGNUM))])]
2686 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2687 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2688 rtx reg0 = gen_reg_rtx (dreg_mode);
2689 rtx reg1 = gen_reg_rtx (dreg_mode);
2690 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2691 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2692 rtx len0 = gen_lowpart (Pmode, reg0);
2693 rtx len1 = gen_lowpart (Pmode, reg1);
2695 emit_clobber (reg0);
2696 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2697 emit_move_insn (len0, operands[2]);
2699 emit_clobber (reg1);
2700 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2701 emit_move_insn (len1, operands[2]);
2703 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2704 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2709 (define_insn "*movmem_long"
2710 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2711 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2712 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2713 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2716 (clobber (reg:CC CC_REGNUM))]
2717 "TARGET_64BIT || !TARGET_ZARCH"
2718 "mvcle\t%0,%1,0\;jo\t.-4"
2719 [(set_attr "length" "8")
2720 (set_attr "type" "vs")])
2722 (define_insn "*movmem_long_31z"
2723 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2724 (clobber (match_operand:TI 1 "register_operand" "=d"))
2725 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2726 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2729 (clobber (reg:CC CC_REGNUM))]
2730 "!TARGET_64BIT && TARGET_ZARCH"
2731 "mvcle\t%0,%1,0\;jo\t.-4"
2732 [(set_attr "length" "8")
2733 (set_attr "type" "vs")])
2740 (define_expand "signbit<mode>2"
2741 [(set (reg:CCZ CC_REGNUM)
2742 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2745 (set (match_operand:SI 0 "register_operand" "=d")
2746 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2749 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2752 (define_expand "isinf<mode>2"
2753 [(set (reg:CCZ CC_REGNUM)
2754 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2757 (set (match_operand:SI 0 "register_operand" "=d")
2758 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2761 operands[2] = GEN_INT (S390_TDC_INFINITY);
2764 ; This insn is used to generate all variants of the Test Data Class
2765 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2766 ; is the register to be tested and the second one is the bit mask
2767 ; specifying the required test(s).
2769 (define_insn "*TDC_insn_<mode>"
2770 [(set (reg:CCZ CC_REGNUM)
2771 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2772 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2774 "t<_d>c<xde><bt>\t%0,%1"
2775 [(set_attr "op_type" "RXE")
2776 (set_attr "type" "fsimp<mode>")])
2778 (define_insn_and_split "*ccz_to_int"
2779 [(set (match_operand:SI 0 "register_operand" "=d")
2780 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2781 UNSPEC_CCZ_TO_INT))]
2785 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2789 ; setmemM instruction pattern(s).
2792 (define_expand "setmem<mode>"
2793 [(set (match_operand:BLK 0 "memory_operand" "")
2794 (match_operand:QI 2 "general_operand" ""))
2795 (use (match_operand:GPR 1 "general_operand" ""))
2796 (match_operand 3 "" "")]
2798 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2800 ; Clear a block that is up to 256 bytes in length.
2801 ; The block length is taken as (operands[1] % 256) + 1.
2803 (define_expand "clrmem_short"
2805 [(set (match_operand:BLK 0 "memory_operand" "")
2807 (use (match_operand 1 "nonmemory_operand" ""))
2808 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2809 (clobber (match_dup 2))
2810 (clobber (reg:CC CC_REGNUM))])]
2812 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2814 (define_insn "*clrmem_short"
2815 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2817 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2818 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2819 (clobber (match_scratch 3 "=X,X,X,&a"))
2820 (clobber (reg:CC CC_REGNUM))]
2821 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2822 && GET_MODE (operands[3]) == Pmode"
2824 [(set_attr "type" "cs")
2825 (set_attr "cpu_facility" "*,*,z10,*")])
2828 [(set (match_operand:BLK 0 "memory_operand" "")
2830 (use (match_operand 1 "const_int_operand" ""))
2831 (use (match_operand 2 "immediate_operand" ""))
2833 (clobber (reg:CC CC_REGNUM))]
2836 [(set (match_dup 0) (const_int 0))
2838 (clobber (reg:CC CC_REGNUM))])]
2839 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2842 [(set (match_operand:BLK 0 "memory_operand" "")
2844 (use (match_operand 1 "register_operand" ""))
2845 (use (match_operand 2 "memory_operand" ""))
2847 (clobber (reg:CC CC_REGNUM))]
2850 [(unspec [(match_dup 1) (match_dup 2)
2851 (const_int 0)] UNSPEC_EXECUTE)
2852 (set (match_dup 0) (const_int 0))
2854 (clobber (reg:CC CC_REGNUM))])]
2858 [(set (match_operand:BLK 0 "memory_operand" "")
2860 (use (match_operand 1 "register_operand" ""))
2861 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2863 (clobber (reg:CC CC_REGNUM))]
2864 "TARGET_Z10 && reload_completed"
2866 [(unspec [(match_dup 1) (const_int 0)
2867 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2868 (set (match_dup 0) (const_int 0))
2870 (clobber (reg:CC CC_REGNUM))])]
2871 "operands[3] = gen_label_rtx ();")
2874 [(set (match_operand:BLK 0 "memory_operand" "")
2876 (use (match_operand 1 "register_operand" ""))
2877 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2878 (clobber (match_operand 2 "register_operand" ""))
2879 (clobber (reg:CC CC_REGNUM))]
2880 "reload_completed && TARGET_CPU_ZARCH"
2881 [(set (match_dup 2) (label_ref (match_dup 3)))
2883 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2884 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2885 (set (match_dup 0) (const_int 0))
2887 (clobber (reg:CC CC_REGNUM))])]
2888 "operands[3] = gen_label_rtx ();")
2890 ; Initialize a block of arbitrary length with (operands[2] % 256).
2892 (define_expand "setmem_long"
2894 [(clobber (match_dup 1))
2895 (set (match_operand:BLK 0 "memory_operand" "")
2896 (match_operand 2 "shift_count_or_setmem_operand" ""))
2897 (use (match_operand 1 "general_operand" ""))
2899 (clobber (reg:CC CC_REGNUM))])]
2902 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2903 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2904 rtx reg0 = gen_reg_rtx (dreg_mode);
2905 rtx reg1 = gen_reg_rtx (dreg_mode);
2906 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2907 rtx len0 = gen_lowpart (Pmode, reg0);
2909 emit_clobber (reg0);
2910 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2911 emit_move_insn (len0, operands[1]);
2913 emit_move_insn (reg1, const0_rtx);
2915 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2920 (define_insn "*setmem_long"
2921 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2922 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2923 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2925 (use (match_operand:<DBL> 1 "register_operand" "d"))
2926 (clobber (reg:CC CC_REGNUM))]
2927 "TARGET_64BIT || !TARGET_ZARCH"
2928 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2929 [(set_attr "length" "8")
2930 (set_attr "type" "vs")])
2932 (define_insn "*setmem_long_and"
2933 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2934 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2935 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2936 (match_operand 4 "const_int_operand" "n")))
2938 (use (match_operand:<DBL> 1 "register_operand" "d"))
2939 (clobber (reg:CC CC_REGNUM))]
2940 "(TARGET_64BIT || !TARGET_ZARCH) &&
2941 (INTVAL (operands[4]) & 255) == 255"
2942 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2943 [(set_attr "length" "8")
2944 (set_attr "type" "vs")])
2946 (define_insn "*setmem_long_31z"
2947 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2948 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
2949 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2951 (use (match_operand:TI 1 "register_operand" "d"))
2952 (clobber (reg:CC CC_REGNUM))]
2953 "!TARGET_64BIT && TARGET_ZARCH"
2954 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2955 [(set_attr "length" "8")
2956 (set_attr "type" "vs")])
2959 ; cmpmemM instruction pattern(s).
2962 (define_expand "cmpmemsi"
2963 [(set (match_operand:SI 0 "register_operand" "")
2964 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2965 (match_operand:BLK 2 "memory_operand" "") ) )
2966 (use (match_operand:SI 3 "general_operand" ""))
2967 (use (match_operand:SI 4 "" ""))]
2969 "s390_expand_cmpmem (operands[0], operands[1],
2970 operands[2], operands[3]); DONE;")
2972 ; Compare a block that is up to 256 bytes in length.
2973 ; The block length is taken as (operands[2] % 256) + 1.
2975 (define_expand "cmpmem_short"
2977 [(set (reg:CCU CC_REGNUM)
2978 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2979 (match_operand:BLK 1 "memory_operand" "")))
2980 (use (match_operand 2 "nonmemory_operand" ""))
2981 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2982 (clobber (match_dup 3))])]
2984 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2986 (define_insn "*cmpmem_short"
2987 [(set (reg:CCU CC_REGNUM)
2988 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
2989 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
2990 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2991 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2992 (clobber (match_scratch 4 "=X,X,X,&a"))]
2993 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2994 && GET_MODE (operands[4]) == Pmode"
2996 [(set_attr "type" "cs")
2997 (set_attr "cpu_facility" "*,*,z10,*")])
3000 [(set (reg:CCU CC_REGNUM)
3001 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3002 (match_operand:BLK 1 "memory_operand" "")))
3003 (use (match_operand 2 "const_int_operand" ""))
3004 (use (match_operand 3 "immediate_operand" ""))
3005 (clobber (scratch))]
3008 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3009 (use (match_dup 2))])]
3010 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3013 [(set (reg:CCU CC_REGNUM)
3014 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3015 (match_operand:BLK 1 "memory_operand" "")))
3016 (use (match_operand 2 "register_operand" ""))
3017 (use (match_operand 3 "memory_operand" ""))
3018 (clobber (scratch))]
3021 [(unspec [(match_dup 2) (match_dup 3)
3022 (const_int 0)] UNSPEC_EXECUTE)
3023 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3024 (use (const_int 1))])]
3028 [(set (reg:CCU CC_REGNUM)
3029 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3030 (match_operand:BLK 1 "memory_operand" "")))
3031 (use (match_operand 2 "register_operand" ""))
3032 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3033 (clobber (scratch))]
3034 "TARGET_Z10 && reload_completed"
3036 [(unspec [(match_dup 2) (const_int 0)
3037 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3038 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3039 (use (const_int 1))])]
3040 "operands[4] = gen_label_rtx ();")
3043 [(set (reg:CCU CC_REGNUM)
3044 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3045 (match_operand:BLK 1 "memory_operand" "")))
3046 (use (match_operand 2 "register_operand" ""))
3047 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3048 (clobber (match_operand 3 "register_operand" ""))]
3049 "reload_completed && TARGET_CPU_ZARCH"
3050 [(set (match_dup 3) (label_ref (match_dup 4)))
3052 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3053 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3054 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3055 (use (const_int 1))])]
3056 "operands[4] = gen_label_rtx ();")
3058 ; Compare a block of arbitrary length.
3060 (define_expand "cmpmem_long"
3062 [(clobber (match_dup 2))
3063 (clobber (match_dup 3))
3064 (set (reg:CCU CC_REGNUM)
3065 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3066 (match_operand:BLK 1 "memory_operand" "")))
3067 (use (match_operand 2 "general_operand" ""))
3068 (use (match_dup 3))])]
3071 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3072 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3073 rtx reg0 = gen_reg_rtx (dreg_mode);
3074 rtx reg1 = gen_reg_rtx (dreg_mode);
3075 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3076 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3077 rtx len0 = gen_lowpart (Pmode, reg0);
3078 rtx len1 = gen_lowpart (Pmode, reg1);
3080 emit_clobber (reg0);
3081 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3082 emit_move_insn (len0, operands[2]);
3084 emit_clobber (reg1);
3085 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3086 emit_move_insn (len1, operands[2]);
3088 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3089 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3094 (define_insn "*cmpmem_long"
3095 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3096 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3097 (set (reg:CCU CC_REGNUM)
3098 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3099 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3101 (use (match_dup 3))]
3102 "TARGET_64BIT || !TARGET_ZARCH"
3103 "clcle\t%0,%1,0\;jo\t.-4"
3104 [(set_attr "length" "8")
3105 (set_attr "type" "vs")])
3107 (define_insn "*cmpmem_long_31z"
3108 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3109 (clobber (match_operand:TI 1 "register_operand" "=d"))
3110 (set (reg:CCU CC_REGNUM)
3111 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3112 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3114 (use (match_dup 3))]
3115 "!TARGET_64BIT && TARGET_ZARCH"
3116 "clcle\t%0,%1,0\;jo\t.-4"
3117 [(set_attr "op_type" "NN")
3118 (set_attr "type" "vs")
3119 (set_attr "length" "8")])
3121 ; Convert CCUmode condition code to integer.
3122 ; Result is zero if EQ, positive if LTU, negative if GTU.
3124 (define_insn_and_split "cmpint"
3125 [(set (match_operand:SI 0 "register_operand" "=d")
3126 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3128 (clobber (reg:CC CC_REGNUM))]
3132 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3134 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3135 (clobber (reg:CC CC_REGNUM))])])
3137 (define_insn_and_split "*cmpint_cc"
3138 [(set (reg CC_REGNUM)
3139 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3142 (set (match_operand:SI 0 "register_operand" "=d")
3143 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3144 "s390_match_ccmode (insn, CCSmode)"
3146 "&& reload_completed"
3147 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3149 [(set (match_dup 2) (match_dup 3))
3150 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3152 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3153 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3154 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3157 (define_insn_and_split "*cmpint_sign"
3158 [(set (match_operand:DI 0 "register_operand" "=d")
3159 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3160 UNSPEC_CCU_TO_INT)))
3161 (clobber (reg:CC CC_REGNUM))]
3164 "&& reload_completed"
3165 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3167 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3168 (clobber (reg:CC CC_REGNUM))])])
3170 (define_insn_and_split "*cmpint_sign_cc"
3171 [(set (reg CC_REGNUM)
3172 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3173 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3174 UNSPEC_CCU_TO_INT) 0)
3175 (const_int 32)) (const_int 32))
3177 (set (match_operand:DI 0 "register_operand" "=d")
3178 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3179 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3181 "&& reload_completed"
3182 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3184 [(set (match_dup 2) (match_dup 3))
3185 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3187 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3188 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3189 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3194 ;;- Conversion instructions.
3197 (define_insn "*sethighpartsi"
3198 [(set (match_operand:SI 0 "register_operand" "=d,d")
3199 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3200 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3201 (clobber (reg:CC CC_REGNUM))]
3206 [(set_attr "op_type" "RS,RSY")
3207 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3209 (define_insn "*sethighpartdi_64"
3210 [(set (match_operand:DI 0 "register_operand" "=d")
3211 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3212 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3213 (clobber (reg:CC CC_REGNUM))]
3216 [(set_attr "op_type" "RSY")
3217 (set_attr "z10prop" "z10_super")])
3219 (define_insn "*sethighpartdi_31"
3220 [(set (match_operand:DI 0 "register_operand" "=d,d")
3221 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3222 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3223 (clobber (reg:CC CC_REGNUM))]
3228 [(set_attr "op_type" "RS,RSY")
3229 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3232 (define_insn_and_split "*extzv<mode>"
3233 [(set (match_operand:GPR 0 "register_operand" "=d")
3234 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3235 (match_operand 2 "const_int_operand" "n")
3237 (clobber (reg:CC CC_REGNUM))]
3238 "INTVAL (operands[2]) > 0
3239 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3241 "&& reload_completed"
3243 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3244 (clobber (reg:CC CC_REGNUM))])
3245 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3247 int bitsize = INTVAL (operands[2]);
3248 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3249 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3251 operands[1] = adjust_address (operands[1], BLKmode, 0);
3252 set_mem_size (operands[1], GEN_INT (size));
3253 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3254 operands[3] = GEN_INT (mask);
3257 (define_insn_and_split "*extv<mode>"
3258 [(set (match_operand:GPR 0 "register_operand" "=d")
3259 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3260 (match_operand 2 "const_int_operand" "n")
3262 (clobber (reg:CC CC_REGNUM))]
3263 "INTVAL (operands[2]) > 0
3264 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3266 "&& reload_completed"
3268 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3269 (clobber (reg:CC CC_REGNUM))])
3271 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3272 (clobber (reg:CC CC_REGNUM))])]
3274 int bitsize = INTVAL (operands[2]);
3275 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3276 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3278 operands[1] = adjust_address (operands[1], BLKmode, 0);
3279 set_mem_size (operands[1], GEN_INT (size));
3280 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3281 operands[3] = GEN_INT (mask);
3285 ; insv instruction patterns
3288 (define_expand "insv"
3289 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3290 (match_operand 1 "const_int_operand" "")
3291 (match_operand 2 "const_int_operand" ""))
3292 (match_operand 3 "general_operand" ""))]
3295 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3300 (define_insn "*insv<mode>_z10"
3301 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3302 (match_operand 1 "const_int_operand" "I")
3303 (match_operand 2 "const_int_operand" "I"))
3304 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3305 (clobber (reg:CC CC_REGNUM))]
3307 && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
3308 GET_MODE_BITSIZE (<MODE>mode)"
3310 int start = INTVAL (operands[2]);
3311 int size = INTVAL (operands[1]);
3312 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
3314 operands[2] = GEN_INT (offset + start); /* start bit position */
3315 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
3316 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
3317 start - size); /* left shift count */
3319 return "risbg\t%0,%3,%b2,%b1,%b4";
3321 [(set_attr "op_type" "RIE")
3322 (set_attr "z10prop" "z10_super_E1")])
3324 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3325 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3326 (define_insn "*insv<mode>_z10_noshift"
3327 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3328 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3329 (match_operand 2 "const_int_operand" "n"))
3330 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3331 (match_operand 4 "const_int_operand" "n"))))
3332 (clobber (reg:CC CC_REGNUM))]
3334 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3335 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
3336 && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
3342 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3343 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3345 operands[5] = GEN_INT (64 - start - size); /* start bit position */
3346 operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
3347 operands[7] = const0_rtx; /* left shift count */
3349 return "risbg\t%0,%1,%b5,%b6,%b7";
3351 [(set_attr "op_type" "RIE")
3352 (set_attr "z10prop" "z10_super_E1")])
3354 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3355 (define_insn "*insv<mode>_or_z10_noshift"
3356 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3357 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3358 (match_operand 2 "const_int_operand" "n"))
3359 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3360 (clobber (reg:CC CC_REGNUM))]
3362 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3363 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
3368 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3369 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3371 operands[4] = GEN_INT (64 - start - size); /* start bit position */
3372 operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
3373 operands[6] = const0_rtx; /* left shift count */
3375 return "rosbg\t%0,%1,%b4,%b5,%b6";
3377 [(set_attr "op_type" "RIE")])
3379 (define_insn "*insv<mode>_mem_reg"
3380 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3381 (match_operand 1 "const_int_operand" "n,n")
3383 (match_operand:W 2 "register_operand" "d,d"))]
3384 "INTVAL (operands[1]) > 0
3385 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3386 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3388 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3390 operands[1] = GEN_INT ((1ul << size) - 1);
3391 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3392 : "stcmy\t%2,%1,%S0";
3394 [(set_attr "op_type" "RS,RSY")
3395 (set_attr "z10prop" "z10_super,z10_super")])
3397 (define_insn "*insvdi_mem_reghigh"
3398 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3399 (match_operand 1 "const_int_operand" "n")
3401 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3404 && INTVAL (operands[1]) > 0
3405 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3406 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3408 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3410 operands[1] = GEN_INT ((1ul << size) - 1);
3411 return "stcmh\t%2,%1,%S0";
3413 [(set_attr "op_type" "RSY")
3414 (set_attr "z10prop" "z10_super")])
3416 (define_insn "*insvdi_reg_imm"
3417 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3419 (match_operand 1 "const_int_operand" "n"))
3420 (match_operand:DI 2 "const_int_operand" "n"))]
3422 && INTVAL (operands[1]) >= 0
3423 && INTVAL (operands[1]) < BITS_PER_WORD
3424 && INTVAL (operands[1]) % 16 == 0"
3426 switch (BITS_PER_WORD - INTVAL (operands[1]))
3428 case 64: return "iihh\t%0,%x2"; break;
3429 case 48: return "iihl\t%0,%x2"; break;
3430 case 32: return "iilh\t%0,%x2"; break;
3431 case 16: return "iill\t%0,%x2"; break;
3432 default: gcc_unreachable();
3435 [(set_attr "op_type" "RI")
3436 (set_attr "z10prop" "z10_super_E1")])
3438 ; Update the left-most 32 bit of a DI.
3439 (define_insn "*insv_h_di_reg_extimm"
3440 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3443 (match_operand:DI 1 "const_int_operand" "n"))]
3446 [(set_attr "op_type" "RIL")
3447 (set_attr "z10prop" "z10_fwd_E1")])
3449 ; Update the right-most 32 bit of a DI, or the whole of a SI.
3450 (define_insn "*insv_l<mode>_reg_extimm"
3451 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3453 (match_operand 1 "const_int_operand" "n"))
3454 (match_operand:P 2 "const_int_operand" "n"))]
3456 && BITS_PER_WORD - INTVAL (operands[1]) == 32"
3458 [(set_attr "op_type" "RIL")
3459 (set_attr "z10prop" "z10_fwd_A1")])
3462 ; extendsidi2 instruction pattern(s).
3465 (define_expand "extendsidi2"
3466 [(set (match_operand:DI 0 "register_operand" "")
3467 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3472 emit_clobber (operands[0]);
3473 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3474 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3475 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3480 (define_insn "*extendsidi2"
3481 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3482 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3488 [(set_attr "op_type" "RRE,RXY,RIL")
3489 (set_attr "type" "*,*,larl")
3490 (set_attr "cpu_facility" "*,*,z10")
3491 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3494 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3497 (define_expand "extend<HQI:mode><DSI:mode>2"
3498 [(set (match_operand:DSI 0 "register_operand" "")
3499 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3502 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3504 rtx tmp = gen_reg_rtx (SImode);
3505 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3506 emit_insn (gen_extendsidi2 (operands[0], tmp));
3509 else if (!TARGET_EXTIMM)
3511 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
3512 GET_MODE_BITSIZE (<HQI:MODE>mode));
3514 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3515 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3516 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3522 ; extendhidi2 instruction pattern(s).
3525 (define_insn "*extendhidi2_extimm"
3526 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3527 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3528 "TARGET_ZARCH && TARGET_EXTIMM"
3533 [(set_attr "op_type" "RRE,RXY,RIL")
3534 (set_attr "type" "*,*,larl")
3535 (set_attr "cpu_facility" "extimm,extimm,z10")
3536 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3538 (define_insn "*extendhidi2"
3539 [(set (match_operand:DI 0 "register_operand" "=d")
3540 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3543 [(set_attr "op_type" "RXY")
3544 (set_attr "z10prop" "z10_super_E1")])
3547 ; extendhisi2 instruction pattern(s).
3550 (define_insn "*extendhisi2_extimm"
3551 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3552 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3559 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3560 (set_attr "type" "*,*,*,larl")
3561 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3562 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3564 (define_insn "*extendhisi2"
3565 [(set (match_operand:SI 0 "register_operand" "=d,d")
3566 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3571 [(set_attr "op_type" "RX,RXY")
3572 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3575 ; extendqi(si|di)2 instruction pattern(s).
3578 ; lbr, lgbr, lb, lgb
3579 (define_insn "*extendqi<mode>2_extimm"
3580 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3581 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3586 [(set_attr "op_type" "RRE,RXY")
3587 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3590 (define_insn "*extendqi<mode>2"
3591 [(set (match_operand:GPR 0 "register_operand" "=d")
3592 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3593 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3595 [(set_attr "op_type" "RXY")
3596 (set_attr "z10prop" "z10_super_E1")])
3598 (define_insn_and_split "*extendqi<mode>2_short_displ"
3599 [(set (match_operand:GPR 0 "register_operand" "=d")
3600 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3601 (clobber (reg:CC CC_REGNUM))]
3602 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3604 "&& reload_completed"
3606 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3607 (clobber (reg:CC CC_REGNUM))])
3609 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3610 (clobber (reg:CC CC_REGNUM))])]
3612 operands[1] = adjust_address (operands[1], BLKmode, 0);
3613 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
3614 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
3615 - GET_MODE_BITSIZE (QImode));
3619 ; zero_extendsidi2 instruction pattern(s).
3622 (define_expand "zero_extendsidi2"
3623 [(set (match_operand:DI 0 "register_operand" "")
3624 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3629 emit_clobber (operands[0]);
3630 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3631 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3636 (define_insn "*zero_extendsidi2"
3637 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3638 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3644 [(set_attr "op_type" "RRE,RXY,RIL")
3645 (set_attr "type" "*,*,larl")
3646 (set_attr "cpu_facility" "*,*,z10")
3647 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3650 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3653 (define_insn "*llgt_sidi"
3654 [(set (match_operand:DI 0 "register_operand" "=d")
3655 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3656 (const_int 2147483647)))]
3659 [(set_attr "op_type" "RXE")
3660 (set_attr "z10prop" "z10_super_E1")])
3662 (define_insn_and_split "*llgt_sidi_split"
3663 [(set (match_operand:DI 0 "register_operand" "=d")
3664 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3665 (const_int 2147483647)))
3666 (clobber (reg:CC CC_REGNUM))]
3669 "&& reload_completed"
3671 (and:DI (subreg:DI (match_dup 1) 0)
3672 (const_int 2147483647)))]
3675 (define_insn "*llgt_sisi"
3676 [(set (match_operand:SI 0 "register_operand" "=d,d")
3677 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3678 (const_int 2147483647)))]
3683 [(set_attr "op_type" "RRE,RXE")
3684 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3686 (define_insn "*llgt_didi"
3687 [(set (match_operand:DI 0 "register_operand" "=d,d")
3688 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3689 (const_int 2147483647)))]
3694 [(set_attr "op_type" "RRE,RXE")
3695 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3698 [(set (match_operand:DSI 0 "register_operand" "")
3699 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3700 (const_int 2147483647)))
3701 (clobber (reg:CC CC_REGNUM))]
3702 "TARGET_ZARCH && reload_completed"
3704 (and:DSI (match_dup 1)
3705 (const_int 2147483647)))]
3709 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3712 (define_expand "zero_extend<mode>di2"
3713 [(set (match_operand:DI 0 "register_operand" "")
3714 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3719 rtx tmp = gen_reg_rtx (SImode);
3720 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3721 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3724 else if (!TARGET_EXTIMM)
3726 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3727 GET_MODE_BITSIZE(<MODE>mode));
3728 operands[1] = gen_lowpart (DImode, operands[1]);
3729 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3730 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3735 (define_expand "zero_extend<mode>si2"
3736 [(set (match_operand:SI 0 "register_operand" "")
3737 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3742 operands[1] = gen_lowpart (SImode, operands[1]);
3743 emit_insn (gen_andsi3 (operands[0], operands[1],
3744 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3750 (define_insn "*zero_extendhi<mode>2_z10"
3751 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3752 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3758 [(set_attr "op_type" "RXY,RRE,RIL")
3759 (set_attr "type" "*,*,larl")
3760 (set_attr "cpu_facility" "*,*,z10")
3761 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3763 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3764 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3765 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3766 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3771 [(set_attr "op_type" "RRE,RXY")
3772 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3775 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3776 [(set (match_operand:GPR 0 "register_operand" "=d")
3777 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3778 "TARGET_ZARCH && !TARGET_EXTIMM"
3780 [(set_attr "op_type" "RXY")
3781 (set_attr "z10prop" "z10_fwd_A3")])
3783 (define_insn_and_split "*zero_extendhisi2_31"
3784 [(set (match_operand:SI 0 "register_operand" "=&d")
3785 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3786 (clobber (reg:CC CC_REGNUM))]
3789 "&& reload_completed"
3790 [(set (match_dup 0) (const_int 0))
3792 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3793 (clobber (reg:CC CC_REGNUM))])]
3794 "operands[2] = gen_lowpart (HImode, operands[0]);")
3796 (define_insn_and_split "*zero_extendqisi2_31"
3797 [(set (match_operand:SI 0 "register_operand" "=&d")
3798 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
3801 "&& reload_completed"
3802 [(set (match_dup 0) (const_int 0))
3803 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3804 "operands[2] = gen_lowpart (QImode, operands[0]);")
3807 ; zero_extendqihi2 instruction pattern(s).
3810 (define_expand "zero_extendqihi2"
3811 [(set (match_operand:HI 0 "register_operand" "")
3812 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3813 "TARGET_ZARCH && !TARGET_EXTIMM"
3815 operands[1] = gen_lowpart (HImode, operands[1]);
3816 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3820 (define_insn "*zero_extendqihi2_64"
3821 [(set (match_operand:HI 0 "register_operand" "=d")
3822 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3823 "TARGET_ZARCH && !TARGET_EXTIMM"
3825 [(set_attr "op_type" "RXY")
3826 (set_attr "z10prop" "z10_fwd_A3")])
3828 (define_insn_and_split "*zero_extendqihi2_31"
3829 [(set (match_operand:HI 0 "register_operand" "=&d")
3830 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3833 "&& reload_completed"
3834 [(set (match_dup 0) (const_int 0))
3835 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3836 "operands[2] = gen_lowpart (QImode, operands[0]);")
3839 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3842 (define_expand "fixuns_truncdddi2"
3844 [(set (match_operand:DI 0 "register_operand" "")
3845 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3846 (clobber (match_scratch:TD 2 "=f"))])]
3850 rtx label1 = gen_label_rtx ();
3851 rtx label2 = gen_label_rtx ();
3852 rtx temp = gen_reg_rtx (TDmode);
3853 REAL_VALUE_TYPE cmp, sub;
3855 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3856 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3858 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3859 solution is doing the check and the subtraction in TD mode and using a
3860 TD -> DI convert afterwards. */
3861 emit_insn (gen_extendddtd2 (temp, operands[1]));
3862 temp = force_reg (TDmode, temp);
3863 emit_cmp_and_jump_insns (temp,
3864 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3865 LT, NULL_RTX, VOIDmode, 0, label1);
3866 emit_insn (gen_subtd3 (temp, temp,
3867 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3868 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3871 emit_label (label1);
3872 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3873 emit_label (label2);
3877 (define_expand "fixuns_trunctddi2"
3878 [(set (match_operand:DI 0 "register_operand" "")
3879 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
3882 rtx label1 = gen_label_rtx ();
3883 rtx label2 = gen_label_rtx ();
3884 rtx temp = gen_reg_rtx (TDmode);
3885 REAL_VALUE_TYPE cmp, sub;
3887 operands[1] = force_reg (TDmode, operands[1]);
3888 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3889 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3891 emit_cmp_and_jump_insns (operands[1],
3892 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3893 LT, NULL_RTX, VOIDmode, 0, label1);
3894 emit_insn (gen_subtd3 (temp, operands[1],
3895 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3896 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3899 emit_label (label1);
3900 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3901 emit_label (label2);
3906 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2
3907 ; instruction pattern(s).
3910 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
3911 [(set (match_operand:GPR 0 "register_operand" "")
3912 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
3915 rtx label1 = gen_label_rtx ();
3916 rtx label2 = gen_label_rtx ();
3917 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
3918 REAL_VALUE_TYPE cmp, sub;
3920 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
3921 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
3922 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
3924 emit_cmp_and_jump_insns (operands[1],
3925 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
3926 LT, NULL_RTX, VOIDmode, 0, label1);
3927 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
3928 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
3929 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
3933 emit_label (label1);
3934 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
3935 operands[1], GEN_INT (5)));
3936 emit_label (label2);
3940 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
3941 [(set (match_operand:GPR 0 "register_operand" "")
3942 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
3945 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
3950 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
3951 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
3952 [(set (match_operand:GPR 0 "register_operand" "=d")
3953 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
3954 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3955 (clobber (reg:CC CC_REGNUM))]
3957 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
3958 [(set_attr "op_type" "RRE")
3959 (set_attr "type" "ftoi")])
3963 ; fix_trunc(td|dd)di2 instruction pattern(s).
3966 (define_expand "fix_trunc<mode>di2"
3967 [(set (match_operand:DI 0 "register_operand" "")
3968 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
3969 "TARGET_ZARCH && TARGET_HARD_DFP"
3971 operands[1] = force_reg (<MODE>mode, operands[1]);
3972 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
3978 (define_insn "fix_trunc<DFP:mode>di2_dfp"
3979 [(set (match_operand:DI 0 "register_operand" "=d")
3980 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
3981 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3982 (clobber (reg:CC CC_REGNUM))]
3983 "TARGET_ZARCH && TARGET_HARD_DFP"
3984 "cg<DFP:xde>tr\t%0,%h2,%1"
3985 [(set_attr "op_type" "RRF")
3986 (set_attr "type" "ftoidfp")])
3990 ; fix_trunctf(si|di)2 instruction pattern(s).
3993 (define_expand "fix_trunctf<mode>2"
3994 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
3995 (fix:GPR (match_operand:TF 1 "register_operand" "")))
3996 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3997 (clobber (reg:CC CC_REGNUM))])]
4003 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4006 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4007 (define_insn "floatdi<mode>2"
4008 [(set (match_operand:FP 0 "register_operand" "=f")
4009 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4010 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4011 "c<xde>g<bt>r\t%0,%1"
4012 [(set_attr "op_type" "RRE")
4013 (set_attr "type" "itof<mode>" )])
4015 ; cxfbr, cdfbr, cefbr
4016 (define_insn "floatsi<mode>2"
4017 [(set (match_operand:BFP 0 "register_operand" "=f")
4018 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4021 [(set_attr "op_type" "RRE")
4022 (set_attr "type" "itof<mode>" )])
4026 ; truncdfsf2 instruction pattern(s).
4029 (define_insn "truncdfsf2"
4030 [(set (match_operand:SF 0 "register_operand" "=f")
4031 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4034 [(set_attr "op_type" "RRE")
4035 (set_attr "type" "ftruncdf")])
4038 ; trunctf(df|sf)2 instruction pattern(s).
4042 (define_insn "trunctf<mode>2"
4043 [(set (match_operand:DSF 0 "register_operand" "=f")
4044 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4045 (clobber (match_scratch:TF 2 "=f"))]
4047 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4048 [(set_attr "length" "6")
4049 (set_attr "type" "ftrunctf")])
4052 ; trunctddd2 and truncddsd2 instruction pattern(s).
4055 (define_insn "trunctddd2"
4056 [(set (match_operand:DD 0 "register_operand" "=f")
4057 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4058 (clobber (match_scratch:TD 2 "=f"))]
4060 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4061 [(set_attr "length" "6")
4062 (set_attr "type" "ftruncdd")])
4064 (define_insn "truncddsd2"
4065 [(set (match_operand:SD 0 "register_operand" "=f")
4066 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4069 [(set_attr "op_type" "RRF")
4070 (set_attr "type" "ftruncsd")])
4073 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4076 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4077 (define_insn "extend<DSF:mode><BFP:mode>2"
4078 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4079 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4081 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4083 l<BFP:xde><DSF:xde>br\t%0,%1
4084 l<BFP:xde><DSF:xde>b\t%0,%1"
4085 [(set_attr "op_type" "RRE,RXE")
4086 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4089 ; extendddtd2 and extendsddd2 instruction pattern(s).
4092 (define_insn "extendddtd2"
4093 [(set (match_operand:TD 0 "register_operand" "=f")
4094 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4097 [(set_attr "op_type" "RRF")
4098 (set_attr "type" "fsimptf")])
4100 (define_insn "extendsddd2"
4101 [(set (match_operand:DD 0 "register_operand" "=f")
4102 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4105 [(set_attr "op_type" "RRF")
4106 (set_attr "type" "fsimptf")])
4108 ; Binary <-> Decimal floating point trunc patterns
4111 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4112 [(set (reg:DFP_ALL FPR0_REGNUM)
4113 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4114 (use (reg:SI GPR0_REGNUM))
4115 (clobber (reg:CC CC_REGNUM))]
4119 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4120 [(set (reg:BFP FPR0_REGNUM)
4121 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4122 (use (reg:SI GPR0_REGNUM))
4123 (clobber (reg:CC CC_REGNUM))]
4127 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4128 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4129 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4131 [(set (reg:DFP_ALL FPR0_REGNUM)
4132 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4133 (use (reg:SI GPR0_REGNUM))
4134 (clobber (reg:CC CC_REGNUM))])
4135 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4136 (reg:DFP_ALL FPR0_REGNUM))]
4138 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4140 HOST_WIDE_INT flags;
4142 flags = (PFPO_CONVERT |
4143 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4144 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4146 operands[2] = GEN_INT (flags);
4149 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4150 [(set (reg:DFP_ALL FPR2_REGNUM)
4151 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4152 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4154 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4155 (use (reg:SI GPR0_REGNUM))
4156 (clobber (reg:CC CC_REGNUM))])
4157 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4159 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4161 HOST_WIDE_INT flags;
4163 flags = (PFPO_CONVERT |
4164 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4165 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4167 operands[2] = GEN_INT (flags);
4171 ; Binary <-> Decimal floating point extend patterns
4174 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4175 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4176 (use (reg:SI GPR0_REGNUM))
4177 (clobber (reg:CC CC_REGNUM))]
4181 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4182 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4183 (use (reg:SI GPR0_REGNUM))
4184 (clobber (reg:CC CC_REGNUM))]
4188 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4189 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4190 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4192 [(set (reg:DFP_ALL FPR0_REGNUM)
4193 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4194 (use (reg:SI GPR0_REGNUM))
4195 (clobber (reg:CC CC_REGNUM))])
4196 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4197 (reg:DFP_ALL FPR0_REGNUM))]
4199 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4201 HOST_WIDE_INT flags;
4203 flags = (PFPO_CONVERT |
4204 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4205 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4207 operands[2] = GEN_INT (flags);
4210 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4211 [(set (reg:DFP_ALL FPR2_REGNUM)
4212 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4213 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4215 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4216 (use (reg:SI GPR0_REGNUM))
4217 (clobber (reg:CC CC_REGNUM))])
4218 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4220 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4222 HOST_WIDE_INT flags;
4224 flags = (PFPO_CONVERT |
4225 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4226 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4228 operands[2] = GEN_INT (flags);
4233 ;; ARITHMETIC OPERATIONS
4235 ; arithmetic operations set the ConditionCode,
4236 ; because of unpredictable Bits in Register for Halfword and Byte
4237 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4240 ;;- Add instructions.
4244 ; addti3 instruction pattern(s).
4247 (define_insn_and_split "addti3"
4248 [(set (match_operand:TI 0 "register_operand" "=&d")
4249 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4250 (match_operand:TI 2 "general_operand" "do") ) )
4251 (clobber (reg:CC CC_REGNUM))]
4254 "&& reload_completed"
4256 [(set (reg:CCL1 CC_REGNUM)
4257 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4259 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4261 [(set (match_dup 3) (plus:DI
4262 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4263 (match_dup 4)) (match_dup 5)))
4264 (clobber (reg:CC CC_REGNUM))])]
4265 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4266 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4267 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4268 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4269 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4270 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4273 ; adddi3 instruction pattern(s).
4276 (define_expand "adddi3"
4278 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4279 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4280 (match_operand:DI 2 "general_operand" "")))
4281 (clobber (reg:CC CC_REGNUM))])]
4285 (define_insn "*adddi3_sign"
4286 [(set (match_operand:DI 0 "register_operand" "=d,d")
4287 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4288 (match_operand:DI 1 "register_operand" "0,0")))
4289 (clobber (reg:CC CC_REGNUM))]
4294 [(set_attr "op_type" "RRE,RXY")])
4296 (define_insn "*adddi3_zero_cc"
4297 [(set (reg CC_REGNUM)
4298 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4299 (match_operand:DI 1 "register_operand" "0,0"))
4301 (set (match_operand:DI 0 "register_operand" "=d,d")
4302 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4303 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4307 [(set_attr "op_type" "RRE,RXY")
4308 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4310 (define_insn "*adddi3_zero_cconly"
4311 [(set (reg CC_REGNUM)
4312 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4313 (match_operand:DI 1 "register_operand" "0,0"))
4315 (clobber (match_scratch:DI 0 "=d,d"))]
4316 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4320 [(set_attr "op_type" "RRE,RXY")
4321 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4323 (define_insn "*adddi3_zero"
4324 [(set (match_operand:DI 0 "register_operand" "=d,d")
4325 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4326 (match_operand:DI 1 "register_operand" "0,0")))
4327 (clobber (reg:CC CC_REGNUM))]
4332 [(set_attr "op_type" "RRE,RXY")
4333 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4335 (define_insn_and_split "*adddi3_31z"
4336 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4337 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4338 (match_operand:DI 2 "general_operand" "do") ) )
4339 (clobber (reg:CC CC_REGNUM))]
4340 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4342 "&& reload_completed"
4344 [(set (reg:CCL1 CC_REGNUM)
4345 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4347 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4349 [(set (match_dup 3) (plus:SI
4350 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4351 (match_dup 4)) (match_dup 5)))
4352 (clobber (reg:CC CC_REGNUM))])]
4353 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4354 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4355 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4356 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4357 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4358 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4360 (define_insn_and_split "*adddi3_31"
4361 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4362 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4363 (match_operand:DI 2 "general_operand" "do") ) )
4364 (clobber (reg:CC CC_REGNUM))]
4367 "&& reload_completed"
4369 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4370 (clobber (reg:CC CC_REGNUM))])
4372 [(set (reg:CCL1 CC_REGNUM)
4373 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4375 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4377 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4379 (label_ref (match_dup 9))))
4381 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4382 (clobber (reg:CC CC_REGNUM))])
4384 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4385 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4386 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4387 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4388 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4389 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4390 operands[9] = gen_label_rtx ();")
4393 ; addsi3 instruction pattern(s).
4396 (define_expand "addsi3"
4398 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4399 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4400 (match_operand:SI 2 "general_operand" "")))
4401 (clobber (reg:CC CC_REGNUM))])]
4405 (define_insn "*addsi3_sign"
4406 [(set (match_operand:SI 0 "register_operand" "=d,d")
4407 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4408 (match_operand:SI 1 "register_operand" "0,0")))
4409 (clobber (reg:CC CC_REGNUM))]
4414 [(set_attr "op_type" "RX,RXY")])
4417 ; add(di|si)3 instruction pattern(s).
4420 ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4421 (define_insn "*add<mode>3"
4422 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS")
4423 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
4424 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) )
4425 (clobber (reg:CC CC_REGNUM))]
4435 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY")
4436 (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10")
4437 (set_attr "z10prop" "z10_super_E1,
4445 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4446 (define_insn "*add<mode>3_carry1_cc"
4447 [(set (reg CC_REGNUM)
4448 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4449 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4451 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d")
4452 (plus:GPR (match_dup 1) (match_dup 2)))]
4453 "s390_match_ccmode (insn, CCL1mode)"
4461 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4462 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4463 (set_attr "z10prop" "z10_super_E1,
4470 ; alr, al, aly, algr, alg
4471 (define_insn "*add<mode>3_carry1_cconly"
4472 [(set (reg CC_REGNUM)
4473 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4474 (match_operand:GPR 2 "general_operand" "d,R,T"))
4476 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4477 "s390_match_ccmode (insn, CCL1mode)"
4482 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4483 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4485 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4486 (define_insn "*add<mode>3_carry2_cc"
4487 [(set (reg CC_REGNUM)
4488 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4489 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4491 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4492 (plus:GPR (match_dup 1) (match_dup 2)))]
4493 "s390_match_ccmode (insn, CCL1mode)"
4501 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4502 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4503 (set_attr "z10prop" "z10_super_E1,
4510 ; alr, al, aly, algr, alg
4511 (define_insn "*add<mode>3_carry2_cconly"
4512 [(set (reg CC_REGNUM)
4513 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4514 (match_operand:GPR 2 "general_operand" "d,R,T"))
4516 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4517 "s390_match_ccmode (insn, CCL1mode)"
4522 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4523 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4525 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4526 (define_insn "*add<mode>3_cc"
4527 [(set (reg CC_REGNUM)
4528 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4529 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4531 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4532 (plus:GPR (match_dup 1) (match_dup 2)))]
4533 "s390_match_ccmode (insn, CCLmode)"
4541 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4542 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4543 (set_attr "z10prop" "z10_super_E1,
4550 ; alr, al, aly, algr, alg
4551 (define_insn "*add<mode>3_cconly"
4552 [(set (reg CC_REGNUM)
4553 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4554 (match_operand:GPR 2 "general_operand" "d,R,T"))
4556 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4557 "s390_match_ccmode (insn, CCLmode)"
4562 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4563 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4565 ; alr, al, aly, algr, alg
4566 (define_insn "*add<mode>3_cconly2"
4567 [(set (reg CC_REGNUM)
4568 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4569 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
4570 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4571 "s390_match_ccmode(insn, CCLmode)"
4576 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4577 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4579 ; ahi, afi, aghi, agfi, asi, agsi
4580 (define_insn "*add<mode>3_imm_cc"
4581 [(set (reg CC_REGNUM)
4582 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0")
4583 (match_operand:GPR 2 "const_int_operand" "K,Os,C"))
4585 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS")
4586 (plus:GPR (match_dup 1) (match_dup 2)))]
4587 "s390_match_ccmode (insn, CCAmode)
4588 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4589 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4590 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
4591 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
4596 [(set_attr "op_type" "RI,RIL,SIY")
4597 (set_attr "cpu_facility" "*,extimm,z10")
4598 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4601 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4604 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4605 (define_insn "add<mode>3"
4606 [(set (match_operand:FP 0 "register_operand" "=f, f")
4607 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4608 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4609 (clobber (reg:CC CC_REGNUM))]
4612 a<xde><bt>r\t%0,<op1>%2
4614 [(set_attr "op_type" "<RRer>,RXE")
4615 (set_attr "type" "fsimp<mode>")])
4617 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4618 (define_insn "*add<mode>3_cc"
4619 [(set (reg CC_REGNUM)
4620 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4621 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4622 (match_operand:FP 3 "const0_operand" "")))
4623 (set (match_operand:FP 0 "register_operand" "=f,f")
4624 (plus:FP (match_dup 1) (match_dup 2)))]
4625 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4627 a<xde><bt>r\t%0,<op1>%2
4629 [(set_attr "op_type" "<RRer>,RXE")
4630 (set_attr "type" "fsimp<mode>")])
4632 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4633 (define_insn "*add<mode>3_cconly"
4634 [(set (reg CC_REGNUM)
4635 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4636 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4637 (match_operand:FP 3 "const0_operand" "")))
4638 (clobber (match_scratch:FP 0 "=f,f"))]
4639 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4641 a<xde><bt>r\t%0,<op1>%2
4643 [(set_attr "op_type" "<RRer>,RXE")
4644 (set_attr "type" "fsimp<mode>")])
4648 ;;- Subtract instructions.
4652 ; subti3 instruction pattern(s).
4655 (define_insn_and_split "subti3"
4656 [(set (match_operand:TI 0 "register_operand" "=&d")
4657 (minus:TI (match_operand:TI 1 "register_operand" "0")
4658 (match_operand:TI 2 "general_operand" "do") ) )
4659 (clobber (reg:CC CC_REGNUM))]
4662 "&& reload_completed"
4664 [(set (reg:CCL2 CC_REGNUM)
4665 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4667 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4669 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4670 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4671 (clobber (reg:CC CC_REGNUM))])]
4672 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4673 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4674 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4675 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4676 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4677 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4680 ; subdi3 instruction pattern(s).
4683 (define_expand "subdi3"
4685 [(set (match_operand:DI 0 "register_operand" "")
4686 (minus:DI (match_operand:DI 1 "register_operand" "")
4687 (match_operand:DI 2 "general_operand" "")))
4688 (clobber (reg:CC CC_REGNUM))])]
4692 (define_insn "*subdi3_sign"
4693 [(set (match_operand:DI 0 "register_operand" "=d,d")
4694 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4695 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4696 (clobber (reg:CC CC_REGNUM))]
4701 [(set_attr "op_type" "RRE,RXY")
4702 (set_attr "z10prop" "z10_c,*")])
4704 (define_insn "*subdi3_zero_cc"
4705 [(set (reg CC_REGNUM)
4706 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4707 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4709 (set (match_operand:DI 0 "register_operand" "=d,d")
4710 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4711 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4715 [(set_attr "op_type" "RRE,RXY")
4716 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4718 (define_insn "*subdi3_zero_cconly"
4719 [(set (reg CC_REGNUM)
4720 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4721 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4723 (clobber (match_scratch:DI 0 "=d,d"))]
4724 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4728 [(set_attr "op_type" "RRE,RXY")
4729 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4731 (define_insn "*subdi3_zero"
4732 [(set (match_operand:DI 0 "register_operand" "=d,d")
4733 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4734 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4735 (clobber (reg:CC CC_REGNUM))]
4740 [(set_attr "op_type" "RRE,RXY")
4741 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4743 (define_insn_and_split "*subdi3_31z"
4744 [(set (match_operand:DI 0 "register_operand" "=&d")
4745 (minus:DI (match_operand:DI 1 "register_operand" "0")
4746 (match_operand:DI 2 "general_operand" "do") ) )
4747 (clobber (reg:CC CC_REGNUM))]
4748 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4750 "&& reload_completed"
4752 [(set (reg:CCL2 CC_REGNUM)
4753 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4755 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4757 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4758 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4759 (clobber (reg:CC CC_REGNUM))])]
4760 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4761 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4762 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4763 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4764 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4765 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4767 (define_insn_and_split "*subdi3_31"
4768 [(set (match_operand:DI 0 "register_operand" "=&d")
4769 (minus:DI (match_operand:DI 1 "register_operand" "0")
4770 (match_operand:DI 2 "general_operand" "do") ) )
4771 (clobber (reg:CC CC_REGNUM))]
4774 "&& reload_completed"
4776 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4777 (clobber (reg:CC CC_REGNUM))])
4779 [(set (reg:CCL2 CC_REGNUM)
4780 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4782 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4784 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4786 (label_ref (match_dup 9))))
4788 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4789 (clobber (reg:CC CC_REGNUM))])
4791 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4792 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4793 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4794 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4795 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4796 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4797 operands[9] = gen_label_rtx ();")
4800 ; subsi3 instruction pattern(s).
4803 (define_expand "subsi3"
4805 [(set (match_operand:SI 0 "register_operand" "")
4806 (minus:SI (match_operand:SI 1 "register_operand" "")
4807 (match_operand:SI 2 "general_operand" "")))
4808 (clobber (reg:CC CC_REGNUM))])]
4812 (define_insn "*subsi3_sign"
4813 [(set (match_operand:SI 0 "register_operand" "=d,d")
4814 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4815 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4816 (clobber (reg:CC CC_REGNUM))]
4821 [(set_attr "op_type" "RX,RXY")])
4824 ; sub(di|si)3 instruction pattern(s).
4827 ; sr, s, sy, sgr, sg
4828 (define_insn "*sub<mode>3"
4829 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4830 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4831 (match_operand:GPR 2 "general_operand" "d,R,T") ) )
4832 (clobber (reg:CC CC_REGNUM))]
4838 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4839 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4841 ; slr, sl, sly, slgr, slg
4842 (define_insn "*sub<mode>3_borrow_cc"
4843 [(set (reg CC_REGNUM)
4844 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4845 (match_operand:GPR 2 "general_operand" "d,R,T"))
4847 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4848 (minus:GPR (match_dup 1) (match_dup 2)))]
4849 "s390_match_ccmode (insn, CCL2mode)"
4854 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4855 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4857 ; slr, sl, sly, slgr, slg
4858 (define_insn "*sub<mode>3_borrow_cconly"
4859 [(set (reg CC_REGNUM)
4860 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4861 (match_operand:GPR 2 "general_operand" "d,R,T"))
4863 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4864 "s390_match_ccmode (insn, CCL2mode)"
4869 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4870 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4872 ; slr, sl, sly, slgr, slg
4873 (define_insn "*sub<mode>3_cc"
4874 [(set (reg CC_REGNUM)
4875 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4876 (match_operand:GPR 2 "general_operand" "d,R,T"))
4878 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4879 (minus:GPR (match_dup 1) (match_dup 2)))]
4880 "s390_match_ccmode (insn, CCLmode)"
4885 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4886 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4888 ; slr, sl, sly, slgr, slg
4889 (define_insn "*sub<mode>3_cc2"
4890 [(set (reg CC_REGNUM)
4891 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4892 (match_operand:GPR 2 "general_operand" "d,R,T")))
4893 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4894 (minus:GPR (match_dup 1) (match_dup 2)))]
4895 "s390_match_ccmode (insn, CCL3mode)"
4900 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4901 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4903 ; slr, sl, sly, slgr, slg
4904 (define_insn "*sub<mode>3_cconly"
4905 [(set (reg CC_REGNUM)
4906 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4907 (match_operand:GPR 2 "general_operand" "d,R,T"))
4909 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4910 "s390_match_ccmode (insn, CCLmode)"
4915 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4916 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4919 ; slr, sl, sly, slgr, slg
4920 (define_insn "*sub<mode>3_cconly2"
4921 [(set (reg CC_REGNUM)
4922 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4923 (match_operand:GPR 2 "general_operand" "d,R,T")))
4924 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4925 "s390_match_ccmode (insn, CCL3mode)"
4930 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4931 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4935 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
4938 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4939 (define_insn "sub<mode>3"
4940 [(set (match_operand:FP 0 "register_operand" "=f, f")
4941 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
4942 (match_operand:FP 2 "general_operand" "f,<Rf>")))
4943 (clobber (reg:CC CC_REGNUM))]
4946 s<xde><bt>r\t%0,<op1>%2
4948 [(set_attr "op_type" "<RRer>,RXE")
4949 (set_attr "type" "fsimp<mode>")])
4951 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4952 (define_insn "*sub<mode>3_cc"
4953 [(set (reg CC_REGNUM)
4954 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4955 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4956 (match_operand:FP 3 "const0_operand" "")))
4957 (set (match_operand:FP 0 "register_operand" "=f,f")
4958 (minus:FP (match_dup 1) (match_dup 2)))]
4959 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4961 s<xde><bt>r\t%0,<op1>%2
4963 [(set_attr "op_type" "<RRer>,RXE")
4964 (set_attr "type" "fsimp<mode>")])
4966 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4967 (define_insn "*sub<mode>3_cconly"
4968 [(set (reg CC_REGNUM)
4969 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4970 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4971 (match_operand:FP 3 "const0_operand" "")))
4972 (clobber (match_scratch:FP 0 "=f,f"))]
4973 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4975 s<xde><bt>r\t%0,<op1>%2
4977 [(set_attr "op_type" "<RRer>,RXE")
4978 (set_attr "type" "fsimp<mode>")])
4982 ;;- Conditional add/subtract instructions.
4986 ; add(di|si)cc instruction pattern(s).
4989 ; the following 4 patterns are used when the result of an add with
4990 ; carry is checked for an overflow condition
4992 ; op1 + op2 + c < op1
4994 ; alcr, alc, alcgr, alcg
4995 (define_insn "*add<mode>3_alc_carry1_cc"
4996 [(set (reg CC_REGNUM)
4998 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4999 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5000 (match_operand:GPR 2 "general_operand" "d,RT"))
5002 (set (match_operand:GPR 0 "register_operand" "=d,d")
5003 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5004 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5008 [(set_attr "op_type" "RRE,RXY")])
5010 ; alcr, alc, alcgr, alcg
5011 (define_insn "*add<mode>3_alc_carry1_cconly"
5012 [(set (reg CC_REGNUM)
5014 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5015 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5016 (match_operand:GPR 2 "general_operand" "d,RT"))
5018 (clobber (match_scratch:GPR 0 "=d,d"))]
5019 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5023 [(set_attr "op_type" "RRE,RXY")])
5025 ; op1 + op2 + c < op2
5027 ; alcr, alc, alcgr, alcg
5028 (define_insn "*add<mode>3_alc_carry2_cc"
5029 [(set (reg CC_REGNUM)
5031 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5032 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5033 (match_operand:GPR 2 "general_operand" "d,RT"))
5035 (set (match_operand:GPR 0 "register_operand" "=d,d")
5036 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5037 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5041 [(set_attr "op_type" "RRE,RXY")])
5043 ; alcr, alc, alcgr, alcg
5044 (define_insn "*add<mode>3_alc_carry2_cconly"
5045 [(set (reg CC_REGNUM)
5047 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5048 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5049 (match_operand:GPR 2 "general_operand" "d,RT"))
5051 (clobber (match_scratch:GPR 0 "=d,d"))]
5052 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5056 [(set_attr "op_type" "RRE,RXY")])
5058 ; alcr, alc, alcgr, alcg
5059 (define_insn "*add<mode>3_alc_cc"
5060 [(set (reg CC_REGNUM)
5062 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5063 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5064 (match_operand:GPR 2 "general_operand" "d,RT"))
5066 (set (match_operand:GPR 0 "register_operand" "=d,d")
5067 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5068 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5072 [(set_attr "op_type" "RRE,RXY")])
5074 ; alcr, alc, alcgr, alcg
5075 (define_insn "*add<mode>3_alc"
5076 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5077 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5078 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5079 (match_operand:GPR 2 "general_operand" "d,RT")))
5080 (clobber (reg:CC CC_REGNUM))]
5085 [(set_attr "op_type" "RRE,RXY")])
5087 ; slbr, slb, slbgr, slbg
5088 (define_insn "*sub<mode>3_slb_cc"
5089 [(set (reg CC_REGNUM)
5091 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5092 (match_operand:GPR 2 "general_operand" "d,RT"))
5093 (match_operand:GPR 3 "s390_slb_comparison" ""))
5095 (set (match_operand:GPR 0 "register_operand" "=d,d")
5096 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5097 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5101 [(set_attr "op_type" "RRE,RXY")
5102 (set_attr "z10prop" "z10_c,*")])
5104 ; slbr, slb, slbgr, slbg
5105 (define_insn "*sub<mode>3_slb"
5106 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5107 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5108 (match_operand:GPR 2 "general_operand" "d,RT"))
5109 (match_operand:GPR 3 "s390_slb_comparison" "")))
5110 (clobber (reg:CC CC_REGNUM))]
5115 [(set_attr "op_type" "RRE,RXY")
5116 (set_attr "z10prop" "z10_c,*")])
5118 (define_expand "add<mode>cc"
5119 [(match_operand:GPR 0 "register_operand" "")
5120 (match_operand 1 "comparison_operator" "")
5121 (match_operand:GPR 2 "register_operand" "")
5122 (match_operand:GPR 3 "const_int_operand" "")]
5124 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5125 XEXP (operands[1], 0), XEXP (operands[1], 1),
5126 operands[0], operands[2],
5127 operands[3])) FAIL; DONE;")
5130 ; scond instruction pattern(s).
5133 (define_insn_and_split "*scond<mode>"
5134 [(set (match_operand:GPR 0 "register_operand" "=&d")
5135 (match_operand:GPR 1 "s390_alc_comparison" ""))
5136 (clobber (reg:CC CC_REGNUM))]
5139 "&& reload_completed"
5140 [(set (match_dup 0) (const_int 0))
5142 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5144 (clobber (reg:CC CC_REGNUM))])]
5147 (define_insn_and_split "*scond<mode>_neg"
5148 [(set (match_operand:GPR 0 "register_operand" "=&d")
5149 (match_operand:GPR 1 "s390_slb_comparison" ""))
5150 (clobber (reg:CC CC_REGNUM))]
5153 "&& reload_completed"
5154 [(set (match_dup 0) (const_int 0))
5156 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5158 (clobber (reg:CC CC_REGNUM))])
5160 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5161 (clobber (reg:CC CC_REGNUM))])]
5165 (define_expand "cstore<mode>4"
5166 [(set (match_operand:SI 0 "register_operand" "")
5167 (match_operator:SI 1 "s390_scond_operator"
5168 [(match_operand:GPR 2 "register_operand" "")
5169 (match_operand:GPR 3 "general_operand" "")]))]
5171 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5172 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5174 (define_expand "cstorecc4"
5176 [(set (match_operand:SI 0 "register_operand" "")
5177 (match_operator:SI 1 "s390_eqne_operator"
5178 [(match_operand:CCZ1 2 "register_operand")
5179 (match_operand 3 "const0_operand")]))
5180 (clobber (reg:CC CC_REGNUM))])]
5182 "emit_insn (gen_sne (operands[0], operands[2]));
5183 if (GET_CODE (operands[1]) == EQ)
5184 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5187 (define_insn_and_split "sne"
5188 [(set (match_operand:SI 0 "register_operand" "=d")
5189 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5191 (clobber (reg:CC CC_REGNUM))]
5196 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5197 (clobber (reg:CC CC_REGNUM))])])
5201 ;;- Multiply instructions.
5205 ; muldi3 instruction pattern(s).
5208 (define_insn "*muldi3_sign"
5209 [(set (match_operand:DI 0 "register_operand" "=d,d")
5210 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5211 (match_operand:DI 1 "register_operand" "0,0")))]
5216 [(set_attr "op_type" "RRE,RXY")
5217 (set_attr "type" "imuldi")])
5219 (define_insn "muldi3"
5220 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5221 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5222 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5229 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5230 (set_attr "type" "imuldi")
5231 (set_attr "cpu_facility" "*,*,*,z10")])
5234 ; mulsi3 instruction pattern(s).
5237 (define_insn "*mulsi3_sign"
5238 [(set (match_operand:SI 0 "register_operand" "=d,d")
5239 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5240 (match_operand:SI 1 "register_operand" "0,0")))]
5245 [(set_attr "op_type" "RX,RXY")
5246 (set_attr "type" "imulhi")
5247 (set_attr "cpu_facility" "*,z10")])
5249 (define_insn "mulsi3"
5250 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5251 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5252 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5260 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5261 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5262 (set_attr "cpu_facility" "*,*,*,*,z10")])
5265 ; mulsidi3 instruction pattern(s).
5268 (define_insn "mulsidi3"
5269 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5270 (mult:DI (sign_extend:DI
5271 (match_operand:SI 1 "register_operand" "%0,0,0"))
5273 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5279 [(set_attr "op_type" "RR,RX,RXY")
5280 (set_attr "type" "imulsi")
5281 (set_attr "cpu_facility" "*,*,z10")])
5284 ; umulsidi3 instruction pattern(s).
5287 (define_insn "umulsidi3"
5288 [(set (match_operand:DI 0 "register_operand" "=d,d")
5289 (mult:DI (zero_extend:DI
5290 (match_operand:SI 1 "register_operand" "%0,0"))
5292 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
5293 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5297 [(set_attr "op_type" "RRE,RXY")
5298 (set_attr "type" "imulsi")])
5301 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5304 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5305 (define_insn "mul<mode>3"
5306 [(set (match_operand:FP 0 "register_operand" "=f,f")
5307 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5308 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5311 m<xdee><bt>r\t%0,<op1>%2
5313 [(set_attr "op_type" "<RRer>,RXE")
5314 (set_attr "type" "fmul<mode>")])
5316 ; madbr, maebr, maxb, madb, maeb
5317 (define_insn "*fmadd<mode>"
5318 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5319 (plus:DSF (mult:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5320 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5321 (match_operand:DSF 3 "register_operand" "0,0")))]
5322 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5326 [(set_attr "op_type" "RRE,RXE")
5327 (set_attr "type" "fmul<mode>")])
5329 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5330 (define_insn "*fmsub<mode>"
5331 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5332 (minus:DSF (mult:DSF (match_operand:DSF 1 "nonimmediate_operand" "f,f")
5333 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5334 (match_operand:DSF 3 "register_operand" "0,0")))]
5335 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5339 [(set_attr "op_type" "RRE,RXE")
5340 (set_attr "type" "fmul<mode>")])
5343 ;;- Divide and modulo instructions.
5347 ; divmoddi4 instruction pattern(s).
5350 (define_expand "divmoddi4"
5351 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5352 (div:DI (match_operand:DI 1 "register_operand" "")
5353 (match_operand:DI 2 "general_operand" "")))
5354 (set (match_operand:DI 3 "general_operand" "")
5355 (mod:DI (match_dup 1) (match_dup 2)))])
5356 (clobber (match_dup 4))]
5359 rtx insn, div_equal, mod_equal;
5361 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5362 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5364 operands[4] = gen_reg_rtx(TImode);
5365 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5367 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5368 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5370 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5371 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5376 (define_insn "divmodtidi3"
5377 [(set (match_operand:TI 0 "register_operand" "=d,d")
5381 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5382 (match_operand:DI 2 "general_operand" "d,RT")))
5384 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5389 [(set_attr "op_type" "RRE,RXY")
5390 (set_attr "type" "idiv")])
5392 (define_insn "divmodtisi3"
5393 [(set (match_operand:TI 0 "register_operand" "=d,d")
5397 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5399 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5402 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5407 [(set_attr "op_type" "RRE,RXY")
5408 (set_attr "type" "idiv")])
5411 ; udivmoddi4 instruction pattern(s).
5414 (define_expand "udivmoddi4"
5415 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5416 (udiv:DI (match_operand:DI 1 "general_operand" "")
5417 (match_operand:DI 2 "nonimmediate_operand" "")))
5418 (set (match_operand:DI 3 "general_operand" "")
5419 (umod:DI (match_dup 1) (match_dup 2)))])
5420 (clobber (match_dup 4))]
5423 rtx insn, div_equal, mod_equal, equal;
5425 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5426 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5427 equal = gen_rtx_IOR (TImode,
5428 gen_rtx_ASHIFT (TImode,
5429 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5431 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5433 operands[4] = gen_reg_rtx(TImode);
5434 emit_clobber (operands[4]);
5435 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5436 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5438 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5439 set_unique_reg_note (insn, REG_EQUAL, equal);
5441 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5442 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5444 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5445 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5450 (define_insn "udivmodtidi3"
5451 [(set (match_operand:TI 0 "register_operand" "=d,d")
5456 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5458 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5462 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5467 [(set_attr "op_type" "RRE,RXY")
5468 (set_attr "type" "idiv")])
5471 ; divmodsi4 instruction pattern(s).
5474 (define_expand "divmodsi4"
5475 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5476 (div:SI (match_operand:SI 1 "general_operand" "")
5477 (match_operand:SI 2 "nonimmediate_operand" "")))
5478 (set (match_operand:SI 3 "general_operand" "")
5479 (mod:SI (match_dup 1) (match_dup 2)))])
5480 (clobber (match_dup 4))]
5483 rtx insn, div_equal, mod_equal, equal;
5485 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5486 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5487 equal = gen_rtx_IOR (DImode,
5488 gen_rtx_ASHIFT (DImode,
5489 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5491 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5493 operands[4] = gen_reg_rtx(DImode);
5494 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5496 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5497 set_unique_reg_note (insn, REG_EQUAL, equal);
5499 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5500 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5502 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5503 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5508 (define_insn "divmoddisi3"
5509 [(set (match_operand:DI 0 "register_operand" "=d,d")
5514 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5516 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5520 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5525 [(set_attr "op_type" "RR,RX")
5526 (set_attr "type" "idiv")])
5529 ; udivsi3 and umodsi3 instruction pattern(s).
5532 (define_expand "udivmodsi4"
5533 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5534 (udiv:SI (match_operand:SI 1 "general_operand" "")
5535 (match_operand:SI 2 "nonimmediate_operand" "")))
5536 (set (match_operand:SI 3 "general_operand" "")
5537 (umod:SI (match_dup 1) (match_dup 2)))])
5538 (clobber (match_dup 4))]
5539 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5541 rtx insn, div_equal, mod_equal, equal;
5543 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5544 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5545 equal = gen_rtx_IOR (DImode,
5546 gen_rtx_ASHIFT (DImode,
5547 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5549 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5551 operands[4] = gen_reg_rtx(DImode);
5552 emit_clobber (operands[4]);
5553 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5554 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5556 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5557 set_unique_reg_note (insn, REG_EQUAL, equal);
5559 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5560 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5562 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5563 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5568 (define_insn "udivmoddisi3"
5569 [(set (match_operand:DI 0 "register_operand" "=d,d")
5574 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5576 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5580 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5581 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5585 [(set_attr "op_type" "RRE,RXY")
5586 (set_attr "type" "idiv")])
5588 (define_expand "udivsi3"
5589 [(set (match_operand:SI 0 "register_operand" "=d")
5590 (udiv:SI (match_operand:SI 1 "general_operand" "")
5591 (match_operand:SI 2 "general_operand" "")))
5592 (clobber (match_dup 3))]
5593 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5595 rtx insn, udiv_equal, umod_equal, equal;
5597 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5598 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5599 equal = gen_rtx_IOR (DImode,
5600 gen_rtx_ASHIFT (DImode,
5601 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5603 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5605 operands[3] = gen_reg_rtx (DImode);
5607 if (CONSTANT_P (operands[2]))
5609 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5611 rtx label1 = gen_label_rtx ();
5613 operands[1] = make_safe_from (operands[1], operands[0]);
5614 emit_move_insn (operands[0], const0_rtx);
5615 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5617 emit_move_insn (operands[0], const1_rtx);
5618 emit_label (label1);
5622 operands[2] = force_reg (SImode, operands[2]);
5623 operands[2] = make_safe_from (operands[2], operands[0]);
5625 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5626 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5628 set_unique_reg_note (insn, REG_EQUAL, equal);
5630 insn = emit_move_insn (operands[0],
5631 gen_lowpart (SImode, operands[3]));
5632 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5637 rtx label1 = gen_label_rtx ();
5638 rtx label2 = gen_label_rtx ();
5639 rtx label3 = gen_label_rtx ();
5641 operands[1] = force_reg (SImode, operands[1]);
5642 operands[1] = make_safe_from (operands[1], operands[0]);
5643 operands[2] = force_reg (SImode, operands[2]);
5644 operands[2] = make_safe_from (operands[2], operands[0]);
5646 emit_move_insn (operands[0], const0_rtx);
5647 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5649 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5651 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5653 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5654 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5656 set_unique_reg_note (insn, REG_EQUAL, equal);
5658 insn = emit_move_insn (operands[0],
5659 gen_lowpart (SImode, operands[3]));
5660 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5663 emit_label (label1);
5664 emit_move_insn (operands[0], operands[1]);
5666 emit_label (label2);
5667 emit_move_insn (operands[0], const1_rtx);
5668 emit_label (label3);
5670 emit_move_insn (operands[0], operands[0]);
5674 (define_expand "umodsi3"
5675 [(set (match_operand:SI 0 "register_operand" "=d")
5676 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5677 (match_operand:SI 2 "nonimmediate_operand" "")))
5678 (clobber (match_dup 3))]
5679 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5681 rtx insn, udiv_equal, umod_equal, equal;
5683 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5684 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5685 equal = gen_rtx_IOR (DImode,
5686 gen_rtx_ASHIFT (DImode,
5687 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5689 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5691 operands[3] = gen_reg_rtx (DImode);
5693 if (CONSTANT_P (operands[2]))
5695 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5697 rtx label1 = gen_label_rtx ();
5699 operands[1] = make_safe_from (operands[1], operands[0]);
5700 emit_move_insn (operands[0], operands[1]);
5701 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
5703 emit_insn (gen_abssi2 (operands[0], operands[2]));
5704 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5705 emit_label (label1);
5709 operands[2] = force_reg (SImode, operands[2]);
5710 operands[2] = make_safe_from (operands[2], operands[0]);
5712 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5713 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5715 set_unique_reg_note (insn, REG_EQUAL, equal);
5717 insn = emit_move_insn (operands[0],
5718 gen_highpart (SImode, operands[3]));
5719 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5724 rtx label1 = gen_label_rtx ();
5725 rtx label2 = gen_label_rtx ();
5726 rtx label3 = gen_label_rtx ();
5728 operands[1] = force_reg (SImode, operands[1]);
5729 operands[1] = make_safe_from (operands[1], operands[0]);
5730 operands[2] = force_reg (SImode, operands[2]);
5731 operands[2] = make_safe_from (operands[2], operands[0]);
5733 emit_move_insn(operands[0], operands[1]);
5734 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5736 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5738 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5740 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5741 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5743 set_unique_reg_note (insn, REG_EQUAL, equal);
5745 insn = emit_move_insn (operands[0],
5746 gen_highpart (SImode, operands[3]));
5747 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5750 emit_label (label1);
5751 emit_move_insn (operands[0], const0_rtx);
5753 emit_label (label2);
5754 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5755 emit_label (label3);
5761 ; div(df|sf)3 instruction pattern(s).
5764 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
5765 (define_insn "div<mode>3"
5766 [(set (match_operand:FP 0 "register_operand" "=f,f")
5767 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5768 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5771 d<xde><bt>r\t%0,<op1>%2
5773 [(set_attr "op_type" "<RRer>,RXE")
5774 (set_attr "type" "fdiv<mode>")])
5778 ;;- And instructions.
5781 (define_expand "and<mode>3"
5782 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5783 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5784 (match_operand:INT 2 "general_operand" "")))
5785 (clobber (reg:CC CC_REGNUM))]
5787 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5790 ; anddi3 instruction pattern(s).
5793 (define_insn "*anddi3_cc"
5794 [(set (reg CC_REGNUM)
5795 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5796 (match_operand:DI 2 "general_operand" "d,RT"))
5798 (set (match_operand:DI 0 "register_operand" "=d,d")
5799 (and:DI (match_dup 1) (match_dup 2)))]
5800 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
5804 [(set_attr "op_type" "RRE,RXY")
5805 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5807 (define_insn "*anddi3_cconly"
5808 [(set (reg CC_REGNUM)
5809 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5810 (match_operand:DI 2 "general_operand" "d,RT"))
5812 (clobber (match_scratch:DI 0 "=d,d"))]
5813 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
5814 /* Do not steal TM patterns. */
5815 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5819 [(set_attr "op_type" "RRE,RXY")
5820 (set_attr "z10prop" "z10_super_E1, z10_super_E1")])
5822 (define_insn "*anddi3"
5823 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5824 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5825 "%d,o,0,0,0,0,0,0,0,0,0,0")
5826 (match_operand:DI 2 "general_operand"
5827 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
5828 (clobber (reg:CC CC_REGNUM))]
5829 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5843 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
5844 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*")
5845 (set_attr "z10prop" "*,
5859 [(set (match_operand:DI 0 "s_operand" "")
5860 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5861 (clobber (reg:CC CC_REGNUM))]
5864 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5865 (clobber (reg:CC CC_REGNUM))])]
5866 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5870 ; andsi3 instruction pattern(s).
5873 (define_insn "*andsi3_cc"
5874 [(set (reg CC_REGNUM)
5875 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5876 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5878 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5879 (and:SI (match_dup 1) (match_dup 2)))]
5880 "s390_match_ccmode(insn, CCTmode)"
5886 [(set_attr "op_type" "RIL,RR,RX,RXY")
5887 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5889 (define_insn "*andsi3_cconly"
5890 [(set (reg CC_REGNUM)
5891 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5892 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5894 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5895 "s390_match_ccmode(insn, CCTmode)
5896 /* Do not steal TM patterns. */
5897 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5903 [(set_attr "op_type" "RIL,RR,RX,RXY")
5904 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5906 (define_insn "*andsi3_zarch"
5907 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5908 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5909 "%d,o,0,0,0,0,0,0,0,0")
5910 (match_operand:SI 2 "general_operand"
5911 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5912 (clobber (reg:CC CC_REGNUM))]
5913 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5925 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")
5926 (set_attr "z10prop" "*,
5937 (define_insn "*andsi3_esa"
5938 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5939 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5940 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5941 (clobber (reg:CC CC_REGNUM))]
5942 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5948 [(set_attr "op_type" "RR,RX,SI,SS")
5949 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
5953 [(set (match_operand:SI 0 "s_operand" "")
5954 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5955 (clobber (reg:CC CC_REGNUM))]
5958 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5959 (clobber (reg:CC CC_REGNUM))])]
5960 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5963 ; andhi3 instruction pattern(s).
5966 (define_insn "*andhi3_zarch"
5967 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5968 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5969 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5970 (clobber (reg:CC CC_REGNUM))]
5971 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5977 [(set_attr "op_type" "RR,RI,SI,SS")
5978 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")
5981 (define_insn "*andhi3_esa"
5982 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5983 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5984 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5985 (clobber (reg:CC CC_REGNUM))]
5986 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5991 [(set_attr "op_type" "RR,SI,SS")
5992 (set_attr "z10prop" "z10_super_E1,*,*")
5996 [(set (match_operand:HI 0 "s_operand" "")
5997 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5998 (clobber (reg:CC CC_REGNUM))]
6001 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6002 (clobber (reg:CC CC_REGNUM))])]
6003 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6006 ; andqi3 instruction pattern(s).
6009 (define_insn "*andqi3_zarch"
6010 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6011 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6012 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
6013 (clobber (reg:CC CC_REGNUM))]
6014 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6021 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
6022 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6024 (define_insn "*andqi3_esa"
6025 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6026 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6027 (match_operand:QI 2 "general_operand" "d,n,Q")))
6028 (clobber (reg:CC CC_REGNUM))]
6029 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6034 [(set_attr "op_type" "RR,SI,SS")
6035 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6038 ; Block and (NC) patterns.
6042 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6043 (and:BLK (match_dup 0)
6044 (match_operand:BLK 1 "memory_operand" "Q")))
6045 (use (match_operand 2 "const_int_operand" "n"))
6046 (clobber (reg:CC CC_REGNUM))]
6047 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6048 "nc\t%O0(%2,%R0),%S1"
6049 [(set_attr "op_type" "SS")])
6052 [(set (match_operand 0 "memory_operand" "")
6054 (match_operand 1 "memory_operand" "")))
6055 (clobber (reg:CC CC_REGNUM))]
6057 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6058 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6060 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6062 (clobber (reg:CC CC_REGNUM))])]
6064 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6065 operands[0] = adjust_address (operands[0], BLKmode, 0);
6066 operands[1] = adjust_address (operands[1], BLKmode, 0);
6071 [(set (match_operand:BLK 0 "memory_operand" "")
6072 (and:BLK (match_dup 0)
6073 (match_operand:BLK 1 "memory_operand" "")))
6074 (use (match_operand 2 "const_int_operand" ""))
6075 (clobber (reg:CC CC_REGNUM))])
6077 [(set (match_operand:BLK 3 "memory_operand" "")
6078 (and:BLK (match_dup 3)
6079 (match_operand:BLK 4 "memory_operand" "")))
6080 (use (match_operand 5 "const_int_operand" ""))
6081 (clobber (reg:CC CC_REGNUM))])]
6082 "s390_offset_p (operands[0], operands[3], operands[2])
6083 && s390_offset_p (operands[1], operands[4], operands[2])
6084 && !s390_overlap_p (operands[0], operands[1],
6085 INTVAL (operands[2]) + INTVAL (operands[5]))
6086 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6088 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6090 (clobber (reg:CC CC_REGNUM))])]
6091 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6092 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6093 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6097 ;;- Bit set (inclusive or) instructions.
6100 (define_expand "ior<mode>3"
6101 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6102 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6103 (match_operand:INT 2 "general_operand" "")))
6104 (clobber (reg:CC CC_REGNUM))]
6106 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6109 ; iordi3 instruction pattern(s).
6112 (define_insn "*iordi3_cc"
6113 [(set (reg CC_REGNUM)
6114 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6115 (match_operand:DI 2 "general_operand" "d,RT"))
6117 (set (match_operand:DI 0 "register_operand" "=d,d")
6118 (ior:DI (match_dup 1) (match_dup 2)))]
6119 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6123 [(set_attr "op_type" "RRE,RXY")
6124 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6126 (define_insn "*iordi3_cconly"
6127 [(set (reg CC_REGNUM)
6128 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6129 (match_operand:DI 2 "general_operand" "d,RT"))
6131 (clobber (match_scratch:DI 0 "=d,d"))]
6132 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6136 [(set_attr "op_type" "RRE,RXY")
6137 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6139 (define_insn "*iordi3"
6140 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
6141 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
6142 (match_operand:DI 2 "general_operand"
6143 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
6144 (clobber (reg:CC CC_REGNUM))]
6145 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6157 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
6158 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*")
6159 (set_attr "z10prop" "z10_super_E1,
6171 [(set (match_operand:DI 0 "s_operand" "")
6172 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6173 (clobber (reg:CC CC_REGNUM))]
6176 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6177 (clobber (reg:CC CC_REGNUM))])]
6178 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6181 ; iorsi3 instruction pattern(s).
6184 (define_insn "*iorsi3_cc"
6185 [(set (reg CC_REGNUM)
6186 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6187 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6189 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6190 (ior:SI (match_dup 1) (match_dup 2)))]
6191 "s390_match_ccmode(insn, CCTmode)"
6197 [(set_attr "op_type" "RIL,RR,RX,RXY")
6198 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6200 (define_insn "*iorsi3_cconly"
6201 [(set (reg CC_REGNUM)
6202 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6203 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6205 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6206 "s390_match_ccmode(insn, CCTmode)"
6212 [(set_attr "op_type" "RIL,RR,RX,RXY")
6213 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6215 (define_insn "*iorsi3_zarch"
6216 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
6217 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
6218 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
6219 (clobber (reg:CC CC_REGNUM))]
6220 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6230 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")
6231 (set_attr "z10prop" "z10_super_E1,
6240 (define_insn "*iorsi3_esa"
6241 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6242 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6243 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6244 (clobber (reg:CC CC_REGNUM))]
6245 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6251 [(set_attr "op_type" "RR,RX,SI,SS")
6252 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6255 [(set (match_operand:SI 0 "s_operand" "")
6256 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6257 (clobber (reg:CC CC_REGNUM))]
6260 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6261 (clobber (reg:CC CC_REGNUM))])]
6262 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6265 ; iorhi3 instruction pattern(s).
6268 (define_insn "*iorhi3_zarch"
6269 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6270 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6271 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
6272 (clobber (reg:CC CC_REGNUM))]
6273 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6279 [(set_attr "op_type" "RR,RI,SI,SS")
6280 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6282 (define_insn "*iorhi3_esa"
6283 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6284 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6285 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6286 (clobber (reg:CC CC_REGNUM))]
6287 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6292 [(set_attr "op_type" "RR,SI,SS")
6293 (set_attr "z10prop" "z10_super_E1,*,*")])
6296 [(set (match_operand:HI 0 "s_operand" "")
6297 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6298 (clobber (reg:CC CC_REGNUM))]
6301 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6302 (clobber (reg:CC CC_REGNUM))])]
6303 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6306 ; iorqi3 instruction pattern(s).
6309 (define_insn "*iorqi3_zarch"
6310 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6311 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6312 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
6313 (clobber (reg:CC CC_REGNUM))]
6314 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6321 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
6322 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6324 (define_insn "*iorqi3_esa"
6325 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6326 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6327 (match_operand:QI 2 "general_operand" "d,n,Q")))
6328 (clobber (reg:CC CC_REGNUM))]
6329 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6334 [(set_attr "op_type" "RR,SI,SS")
6335 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6338 ; Block inclusive or (OC) patterns.
6342 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6343 (ior:BLK (match_dup 0)
6344 (match_operand:BLK 1 "memory_operand" "Q")))
6345 (use (match_operand 2 "const_int_operand" "n"))
6346 (clobber (reg:CC CC_REGNUM))]
6347 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6348 "oc\t%O0(%2,%R0),%S1"
6349 [(set_attr "op_type" "SS")])
6352 [(set (match_operand 0 "memory_operand" "")
6354 (match_operand 1 "memory_operand" "")))
6355 (clobber (reg:CC CC_REGNUM))]
6357 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6358 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6360 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6362 (clobber (reg:CC CC_REGNUM))])]
6364 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6365 operands[0] = adjust_address (operands[0], BLKmode, 0);
6366 operands[1] = adjust_address (operands[1], BLKmode, 0);
6371 [(set (match_operand:BLK 0 "memory_operand" "")
6372 (ior:BLK (match_dup 0)
6373 (match_operand:BLK 1 "memory_operand" "")))
6374 (use (match_operand 2 "const_int_operand" ""))
6375 (clobber (reg:CC CC_REGNUM))])
6377 [(set (match_operand:BLK 3 "memory_operand" "")
6378 (ior:BLK (match_dup 3)
6379 (match_operand:BLK 4 "memory_operand" "")))
6380 (use (match_operand 5 "const_int_operand" ""))
6381 (clobber (reg:CC CC_REGNUM))])]
6382 "s390_offset_p (operands[0], operands[3], operands[2])
6383 && s390_offset_p (operands[1], operands[4], operands[2])
6384 && !s390_overlap_p (operands[0], operands[1],
6385 INTVAL (operands[2]) + INTVAL (operands[5]))
6386 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6388 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6390 (clobber (reg:CC CC_REGNUM))])]
6391 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6392 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6393 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6397 ;;- Xor instructions.
6400 (define_expand "xor<mode>3"
6401 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6402 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6403 (match_operand:INT 2 "general_operand" "")))
6404 (clobber (reg:CC CC_REGNUM))]
6406 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6409 ; xordi3 instruction pattern(s).
6412 (define_insn "*xordi3_cc"
6413 [(set (reg CC_REGNUM)
6414 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6415 (match_operand:DI 2 "general_operand" "d,RT"))
6417 (set (match_operand:DI 0 "register_operand" "=d,d")
6418 (xor:DI (match_dup 1) (match_dup 2)))]
6419 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6423 [(set_attr "op_type" "RRE,RXY")
6424 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6426 (define_insn "*xordi3_cconly"
6427 [(set (reg CC_REGNUM)
6428 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6429 (match_operand:DI 2 "general_operand" "d,RT"))
6431 (clobber (match_scratch:DI 0 "=d,d"))]
6432 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6436 [(set_attr "op_type" "RRE,RXY")
6437 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6439 (define_insn "*xordi3"
6440 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6441 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6442 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
6443 (clobber (reg:CC CC_REGNUM))]
6444 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6452 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")
6453 (set_attr "cpu_facility" "extimm,extimm,*,*,*,*")
6454 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6457 [(set (match_operand:DI 0 "s_operand" "")
6458 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6459 (clobber (reg:CC CC_REGNUM))]
6462 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6463 (clobber (reg:CC CC_REGNUM))])]
6464 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6467 ; xorsi3 instruction pattern(s).
6470 (define_insn "*xorsi3_cc"
6471 [(set (reg CC_REGNUM)
6472 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6473 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6475 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6476 (xor:SI (match_dup 1) (match_dup 2)))]
6477 "s390_match_ccmode(insn, CCTmode)"
6483 [(set_attr "op_type" "RIL,RR,RX,RXY")
6484 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6486 (define_insn "*xorsi3_cconly"
6487 [(set (reg CC_REGNUM)
6488 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6489 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6491 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6492 "s390_match_ccmode(insn, CCTmode)"
6498 [(set_attr "op_type" "RIL,RR,RX,RXY")
6499 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6501 (define_insn "*xorsi3"
6502 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6503 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6504 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
6505 (clobber (reg:CC CC_REGNUM))]
6506 "s390_logical_operator_ok_p (operands)"
6514 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")
6515 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6518 [(set (match_operand:SI 0 "s_operand" "")
6519 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6520 (clobber (reg:CC CC_REGNUM))]
6523 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6524 (clobber (reg:CC CC_REGNUM))])]
6525 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6528 ; xorhi3 instruction pattern(s).
6531 (define_insn "*xorhi3"
6532 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6533 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6534 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
6535 (clobber (reg:CC CC_REGNUM))]
6536 "s390_logical_operator_ok_p (operands)"
6542 [(set_attr "op_type" "RIL,RR,SI,SS")
6543 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6546 [(set (match_operand:HI 0 "s_operand" "")
6547 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6548 (clobber (reg:CC CC_REGNUM))]
6551 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6552 (clobber (reg:CC CC_REGNUM))])]
6553 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6556 ; xorqi3 instruction pattern(s).
6559 (define_insn "*xorqi3"
6560 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6561 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6562 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
6563 (clobber (reg:CC CC_REGNUM))]
6564 "s390_logical_operator_ok_p (operands)"
6571 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")
6572 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6576 ; Block exclusive or (XC) patterns.
6580 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6581 (xor:BLK (match_dup 0)
6582 (match_operand:BLK 1 "memory_operand" "Q")))
6583 (use (match_operand 2 "const_int_operand" "n"))
6584 (clobber (reg:CC CC_REGNUM))]
6585 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6586 "xc\t%O0(%2,%R0),%S1"
6587 [(set_attr "op_type" "SS")])
6590 [(set (match_operand 0 "memory_operand" "")
6592 (match_operand 1 "memory_operand" "")))
6593 (clobber (reg:CC CC_REGNUM))]
6595 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6596 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6598 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6600 (clobber (reg:CC CC_REGNUM))])]
6602 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6603 operands[0] = adjust_address (operands[0], BLKmode, 0);
6604 operands[1] = adjust_address (operands[1], BLKmode, 0);
6609 [(set (match_operand:BLK 0 "memory_operand" "")
6610 (xor:BLK (match_dup 0)
6611 (match_operand:BLK 1 "memory_operand" "")))
6612 (use (match_operand 2 "const_int_operand" ""))
6613 (clobber (reg:CC CC_REGNUM))])
6615 [(set (match_operand:BLK 3 "memory_operand" "")
6616 (xor:BLK (match_dup 3)
6617 (match_operand:BLK 4 "memory_operand" "")))
6618 (use (match_operand 5 "const_int_operand" ""))
6619 (clobber (reg:CC CC_REGNUM))])]
6620 "s390_offset_p (operands[0], operands[3], operands[2])
6621 && s390_offset_p (operands[1], operands[4], operands[2])
6622 && !s390_overlap_p (operands[0], operands[1],
6623 INTVAL (operands[2]) + INTVAL (operands[5]))
6624 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6626 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6628 (clobber (reg:CC CC_REGNUM))])]
6629 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6630 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6631 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6634 ; Block xor (XC) patterns with src == dest.
6637 (define_insn "*xc_zero"
6638 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6640 (use (match_operand 1 "const_int_operand" "n"))
6641 (clobber (reg:CC CC_REGNUM))]
6642 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6643 "xc\t%O0(%1,%R0),%S0"
6644 [(set_attr "op_type" "SS")])
6648 [(set (match_operand:BLK 0 "memory_operand" "")
6650 (use (match_operand 1 "const_int_operand" ""))
6651 (clobber (reg:CC CC_REGNUM))])
6653 [(set (match_operand:BLK 2 "memory_operand" "")
6655 (use (match_operand 3 "const_int_operand" ""))
6656 (clobber (reg:CC CC_REGNUM))])]
6657 "s390_offset_p (operands[0], operands[2], operands[1])
6658 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6660 [(set (match_dup 4) (const_int 0))
6662 (clobber (reg:CC CC_REGNUM))])]
6663 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6664 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6668 ;;- Negate instructions.
6672 ; neg(di|si)2 instruction pattern(s).
6675 (define_expand "neg<mode>2"
6677 [(set (match_operand:DSI 0 "register_operand" "=d")
6678 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
6679 (clobber (reg:CC CC_REGNUM))])]
6683 (define_insn "*negdi2_sign_cc"
6684 [(set (reg CC_REGNUM)
6685 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6686 (match_operand:SI 1 "register_operand" "d") 0)
6687 (const_int 32)) (const_int 32)))
6689 (set (match_operand:DI 0 "register_operand" "=d")
6690 (neg:DI (sign_extend:DI (match_dup 1))))]
6691 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6693 [(set_attr "op_type" "RRE")
6694 (set_attr "z10prop" "z10_c")])
6696 (define_insn "*negdi2_sign"
6697 [(set (match_operand:DI 0 "register_operand" "=d")
6698 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6699 (clobber (reg:CC CC_REGNUM))]
6702 [(set_attr "op_type" "RRE")
6703 (set_attr "z10prop" "z10_c")])
6706 (define_insn "*neg<mode>2_cc"
6707 [(set (reg CC_REGNUM)
6708 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6710 (set (match_operand:GPR 0 "register_operand" "=d")
6711 (neg:GPR (match_dup 1)))]
6712 "s390_match_ccmode (insn, CCAmode)"
6714 [(set_attr "op_type" "RR<E>")
6715 (set_attr "z10prop" "z10_super_c_E1")])
6718 (define_insn "*neg<mode>2_cconly"
6719 [(set (reg CC_REGNUM)
6720 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6722 (clobber (match_scratch:GPR 0 "=d"))]
6723 "s390_match_ccmode (insn, CCAmode)"
6725 [(set_attr "op_type" "RR<E>")
6726 (set_attr "z10prop" "z10_super_c_E1")])
6729 (define_insn "*neg<mode>2"
6730 [(set (match_operand:GPR 0 "register_operand" "=d")
6731 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
6732 (clobber (reg:CC CC_REGNUM))]
6735 [(set_attr "op_type" "RR<E>")
6736 (set_attr "z10prop" "z10_super_c_E1")])
6738 (define_insn_and_split "*negdi2_31"
6739 [(set (match_operand:DI 0 "register_operand" "=d")
6740 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6741 (clobber (reg:CC CC_REGNUM))]
6744 "&& reload_completed"
6746 [(set (match_dup 2) (neg:SI (match_dup 3)))
6747 (clobber (reg:CC CC_REGNUM))])
6749 [(set (reg:CCAP CC_REGNUM)
6750 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
6751 (set (match_dup 4) (neg:SI (match_dup 5)))])
6753 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
6755 (label_ref (match_dup 6))))
6757 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6758 (clobber (reg:CC CC_REGNUM))])
6760 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6761 operands[3] = operand_subword (operands[1], 0, 0, DImode);
6762 operands[4] = operand_subword (operands[0], 1, 0, DImode);
6763 operands[5] = operand_subword (operands[1], 1, 0, DImode);
6764 operands[6] = gen_label_rtx ();")
6767 ; neg(df|sf)2 instruction pattern(s).
6770 (define_expand "neg<mode>2"
6772 [(set (match_operand:BFP 0 "register_operand" "=f")
6773 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6774 (clobber (reg:CC CC_REGNUM))])]
6778 ; lcxbr, lcdbr, lcebr
6779 (define_insn "*neg<mode>2_cc"
6780 [(set (reg CC_REGNUM)
6781 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6782 (match_operand:BFP 2 "const0_operand" "")))
6783 (set (match_operand:BFP 0 "register_operand" "=f")
6784 (neg:BFP (match_dup 1)))]
6785 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6787 [(set_attr "op_type" "RRE")
6788 (set_attr "type" "fsimp<mode>")])
6790 ; lcxbr, lcdbr, lcebr
6791 (define_insn "*neg<mode>2_cconly"
6792 [(set (reg CC_REGNUM)
6793 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6794 (match_operand:BFP 2 "const0_operand" "")))
6795 (clobber (match_scratch:BFP 0 "=f"))]
6796 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6798 [(set_attr "op_type" "RRE")
6799 (set_attr "type" "fsimp<mode>")])
6802 (define_insn "*neg<mode>2_nocc"
6803 [(set (match_operand:FP 0 "register_operand" "=f")
6804 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6807 [(set_attr "op_type" "RRE")
6808 (set_attr "type" "fsimp<mode>")])
6810 ; lcxbr, lcdbr, lcebr
6811 (define_insn "*neg<mode>2"
6812 [(set (match_operand:BFP 0 "register_operand" "=f")
6813 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6814 (clobber (reg:CC CC_REGNUM))]
6817 [(set_attr "op_type" "RRE")
6818 (set_attr "type" "fsimp<mode>")])
6822 ;;- Absolute value instructions.
6826 ; abs(di|si)2 instruction pattern(s).
6829 (define_insn "*absdi2_sign_cc"
6830 [(set (reg CC_REGNUM)
6831 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6832 (match_operand:SI 1 "register_operand" "d") 0)
6833 (const_int 32)) (const_int 32)))
6835 (set (match_operand:DI 0 "register_operand" "=d")
6836 (abs:DI (sign_extend:DI (match_dup 1))))]
6837 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6839 [(set_attr "op_type" "RRE")
6840 (set_attr "z10prop" "z10_c")])
6842 (define_insn "*absdi2_sign"
6843 [(set (match_operand:DI 0 "register_operand" "=d")
6844 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6845 (clobber (reg:CC CC_REGNUM))]
6848 [(set_attr "op_type" "RRE")
6849 (set_attr "z10prop" "z10_c")])
6852 (define_insn "*abs<mode>2_cc"
6853 [(set (reg CC_REGNUM)
6854 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6856 (set (match_operand:GPR 0 "register_operand" "=d")
6857 (abs:GPR (match_dup 1)))]
6858 "s390_match_ccmode (insn, CCAmode)"
6860 [(set_attr "op_type" "RR<E>")
6861 (set_attr "z10prop" "z10_c")])
6864 (define_insn "*abs<mode>2_cconly"
6865 [(set (reg CC_REGNUM)
6866 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6868 (clobber (match_scratch:GPR 0 "=d"))]
6869 "s390_match_ccmode (insn, CCAmode)"
6871 [(set_attr "op_type" "RR<E>")
6872 (set_attr "z10prop" "z10_c")])
6875 (define_insn "abs<mode>2"
6876 [(set (match_operand:GPR 0 "register_operand" "=d")
6877 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6878 (clobber (reg:CC CC_REGNUM))]
6881 [(set_attr "op_type" "RR<E>")
6882 (set_attr "z10prop" "z10_c")])
6885 ; abs(df|sf)2 instruction pattern(s).
6888 (define_expand "abs<mode>2"
6890 [(set (match_operand:BFP 0 "register_operand" "=f")
6891 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6892 (clobber (reg:CC CC_REGNUM))])]
6896 ; lpxbr, lpdbr, lpebr
6897 (define_insn "*abs<mode>2_cc"
6898 [(set (reg CC_REGNUM)
6899 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6900 (match_operand:BFP 2 "const0_operand" "")))
6901 (set (match_operand:BFP 0 "register_operand" "=f")
6902 (abs:BFP (match_dup 1)))]
6903 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6905 [(set_attr "op_type" "RRE")
6906 (set_attr "type" "fsimp<mode>")])
6908 ; lpxbr, lpdbr, lpebr
6909 (define_insn "*abs<mode>2_cconly"
6910 [(set (reg CC_REGNUM)
6911 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6912 (match_operand:BFP 2 "const0_operand" "")))
6913 (clobber (match_scratch:BFP 0 "=f"))]
6914 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6916 [(set_attr "op_type" "RRE")
6917 (set_attr "type" "fsimp<mode>")])
6920 (define_insn "*abs<mode>2_nocc"
6921 [(set (match_operand:FP 0 "register_operand" "=f")
6922 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6925 [(set_attr "op_type" "RRE")
6926 (set_attr "type" "fsimp<mode>")])
6928 ; lpxbr, lpdbr, lpebr
6929 (define_insn "*abs<mode>2"
6930 [(set (match_operand:BFP 0 "register_operand" "=f")
6931 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6932 (clobber (reg:CC CC_REGNUM))]
6935 [(set_attr "op_type" "RRE")
6936 (set_attr "type" "fsimp<mode>")])
6940 ;;- Negated absolute value instructions
6947 (define_insn "*negabsdi2_sign_cc"
6948 [(set (reg CC_REGNUM)
6949 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6950 (match_operand:SI 1 "register_operand" "d") 0)
6951 (const_int 32)) (const_int 32))))
6953 (set (match_operand:DI 0 "register_operand" "=d")
6954 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6955 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6957 [(set_attr "op_type" "RRE")
6958 (set_attr "z10prop" "z10_c")])
6960 (define_insn "*negabsdi2_sign"
6961 [(set (match_operand:DI 0 "register_operand" "=d")
6962 (neg:DI (abs:DI (sign_extend:DI
6963 (match_operand:SI 1 "register_operand" "d")))))
6964 (clobber (reg:CC CC_REGNUM))]
6967 [(set_attr "op_type" "RRE")
6968 (set_attr "z10prop" "z10_c")])
6971 (define_insn "*negabs<mode>2_cc"
6972 [(set (reg CC_REGNUM)
6973 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6975 (set (match_operand:GPR 0 "register_operand" "=d")
6976 (neg:GPR (abs:GPR (match_dup 1))))]
6977 "s390_match_ccmode (insn, CCAmode)"
6979 [(set_attr "op_type" "RR<E>")
6980 (set_attr "z10prop" "z10_c")])
6983 (define_insn "*negabs<mode>2_cconly"
6984 [(set (reg CC_REGNUM)
6985 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6987 (clobber (match_scratch:GPR 0 "=d"))]
6988 "s390_match_ccmode (insn, CCAmode)"
6990 [(set_attr "op_type" "RR<E>")
6991 (set_attr "z10prop" "z10_c")])
6994 (define_insn "*negabs<mode>2"
6995 [(set (match_operand:GPR 0 "register_operand" "=d")
6996 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6997 (clobber (reg:CC CC_REGNUM))]
7000 [(set_attr "op_type" "RR<E>")
7001 (set_attr "z10prop" "z10_c")])
7007 ; lnxbr, lndbr, lnebr
7008 (define_insn "*negabs<mode>2_cc"
7009 [(set (reg CC_REGNUM)
7010 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7011 (match_operand:BFP 2 "const0_operand" "")))
7012 (set (match_operand:BFP 0 "register_operand" "=f")
7013 (neg:BFP (abs:BFP (match_dup 1))))]
7014 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7016 [(set_attr "op_type" "RRE")
7017 (set_attr "type" "fsimp<mode>")])
7019 ; lnxbr, lndbr, lnebr
7020 (define_insn "*negabs<mode>2_cconly"
7021 [(set (reg CC_REGNUM)
7022 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7023 (match_operand:BFP 2 "const0_operand" "")))
7024 (clobber (match_scratch:BFP 0 "=f"))]
7025 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7027 [(set_attr "op_type" "RRE")
7028 (set_attr "type" "fsimp<mode>")])
7031 (define_insn "*negabs<mode>2_nocc"
7032 [(set (match_operand:FP 0 "register_operand" "=f")
7033 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7036 [(set_attr "op_type" "RRE")
7037 (set_attr "type" "fsimp<mode>")])
7039 ; lnxbr, lndbr, lnebr
7040 (define_insn "*negabs<mode>2"
7041 [(set (match_operand:BFP 0 "register_operand" "=f")
7042 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7043 (clobber (reg:CC CC_REGNUM))]
7046 [(set_attr "op_type" "RRE")
7047 (set_attr "type" "fsimp<mode>")])
7050 ;;- Square root instructions.
7054 ; sqrt(df|sf)2 instruction pattern(s).
7057 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7058 (define_insn "sqrt<mode>2"
7059 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7060 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7065 [(set_attr "op_type" "RRE,RXE")
7066 (set_attr "type" "fsqrt<mode>")])
7070 ;;- One complement instructions.
7074 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7077 (define_expand "one_cmpl<mode>2"
7079 [(set (match_operand:INT 0 "register_operand" "")
7080 (xor:INT (match_operand:INT 1 "register_operand" "")
7082 (clobber (reg:CC CC_REGNUM))])]
7088 ;; Find leftmost bit instructions.
7091 (define_expand "clzdi2"
7092 [(set (match_operand:DI 0 "register_operand" "=d")
7093 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7094 "TARGET_EXTIMM && TARGET_ZARCH"
7096 rtx insn, clz_equal;
7097 rtx wide_reg = gen_reg_rtx (TImode);
7098 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7100 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7102 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7104 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7105 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7110 (define_insn "clztidi2"
7111 [(set (match_operand:TI 0 "register_operand" "=d")
7115 (xor:DI (match_operand:DI 1 "register_operand" "d")
7116 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7117 (subreg:SI (clz:DI (match_dup 1)) 4))))
7120 (zero_extend:TI (clz:DI (match_dup 1)))))
7121 (clobber (reg:CC CC_REGNUM))]
7122 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7123 == (unsigned HOST_WIDE_INT) 1 << 63
7124 && TARGET_EXTIMM && TARGET_ZARCH"
7126 [(set_attr "op_type" "RRE")])
7130 ;;- Rotate instructions.
7134 ; rotl(di|si)3 instruction pattern(s).
7138 (define_insn "rotl<mode>3"
7139 [(set (match_operand:GPR 0 "register_operand" "=d")
7140 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7141 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7144 [(set_attr "op_type" "RSE")
7145 (set_attr "atype" "reg")
7146 (set_attr "z10prop" "z10_super_E1")])
7149 (define_insn "*rotl<mode>3_and"
7150 [(set (match_operand:GPR 0 "register_operand" "=d")
7151 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7152 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7153 (match_operand:SI 3 "const_int_operand" "n"))))]
7154 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7156 [(set_attr "op_type" "RSE")
7157 (set_attr "atype" "reg")
7158 (set_attr "z10prop" "z10_super_E1")])
7162 ;;- Shift instructions.
7166 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7169 (define_expand "<shift><mode>3"
7170 [(set (match_operand:DSI 0 "register_operand" "")
7171 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7172 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7177 (define_insn "*<shift>di3_31"
7178 [(set (match_operand:DI 0 "register_operand" "=d")
7179 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7180 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7183 [(set_attr "op_type" "RS")
7184 (set_attr "atype" "reg")])
7186 ; sll, srl, sllg, srlg
7187 (define_insn "*<shift><mode>3"
7188 [(set (match_operand:GPR 0 "register_operand" "=d")
7189 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7190 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7192 "s<lr>l<g>\t%0,<1>%Y2"
7193 [(set_attr "op_type" "RS<E>")
7194 (set_attr "atype" "reg")
7195 (set_attr "z10prop" "z10_super_E1")])
7198 (define_insn "*<shift>di3_31_and"
7199 [(set (match_operand:DI 0 "register_operand" "=d")
7200 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7201 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7202 (match_operand:SI 3 "const_int_operand" "n"))))]
7203 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7205 [(set_attr "op_type" "RS")
7206 (set_attr "atype" "reg")])
7208 ; sll, srl, sllg, srlg
7209 (define_insn "*<shift><mode>3_and"
7210 [(set (match_operand:GPR 0 "register_operand" "=d")
7211 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7212 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7213 (match_operand:SI 3 "const_int_operand" "n"))))]
7214 "(INTVAL (operands[3]) & 63) == 63"
7215 "s<lr>l<g>\t%0,<1>%Y2"
7216 [(set_attr "op_type" "RS<E>")
7217 (set_attr "atype" "reg")
7218 (set_attr "z10prop" "z10_super_E1")])
7221 ; ashr(di|si)3 instruction pattern(s).
7224 (define_expand "ashr<mode>3"
7226 [(set (match_operand:DSI 0 "register_operand" "")
7227 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7228 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7229 (clobber (reg:CC CC_REGNUM))])]
7233 (define_insn "*ashrdi3_cc_31"
7234 [(set (reg CC_REGNUM)
7235 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7236 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7238 (set (match_operand:DI 0 "register_operand" "=d")
7239 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7240 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7242 [(set_attr "op_type" "RS")
7243 (set_attr "atype" "reg")])
7245 (define_insn "*ashrdi3_cconly_31"
7246 [(set (reg CC_REGNUM)
7247 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7248 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7250 (clobber (match_scratch:DI 0 "=d"))]
7251 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7253 [(set_attr "op_type" "RS")
7254 (set_attr "atype" "reg")])
7256 (define_insn "*ashrdi3_31"
7257 [(set (match_operand:DI 0 "register_operand" "=d")
7258 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7259 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7260 (clobber (reg:CC CC_REGNUM))]
7263 [(set_attr "op_type" "RS")
7264 (set_attr "atype" "reg")])
7267 (define_insn "*ashr<mode>3_cc"
7268 [(set (reg CC_REGNUM)
7269 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7270 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7272 (set (match_operand:GPR 0 "register_operand" "=d")
7273 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7274 "s390_match_ccmode(insn, CCSmode)"
7276 [(set_attr "op_type" "RS<E>")
7277 (set_attr "atype" "reg")
7278 (set_attr "z10prop" "z10_super_E1")])
7281 (define_insn "*ashr<mode>3_cconly"
7282 [(set (reg CC_REGNUM)
7283 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7284 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7286 (clobber (match_scratch:GPR 0 "=d"))]
7287 "s390_match_ccmode(insn, CCSmode)"
7289 [(set_attr "op_type" "RS<E>")
7290 (set_attr "atype" "reg")
7291 (set_attr "z10prop" "z10_super_E1")])
7294 (define_insn "*ashr<mode>3"
7295 [(set (match_operand:GPR 0 "register_operand" "=d")
7296 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7297 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7298 (clobber (reg:CC CC_REGNUM))]
7301 [(set_attr "op_type" "RS<E>")
7302 (set_attr "atype" "reg")
7303 (set_attr "z10prop" "z10_super_E1")])
7306 ; shift pattern with implicit ANDs
7308 (define_insn "*ashrdi3_cc_31_and"
7309 [(set (reg CC_REGNUM)
7310 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7311 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7312 (match_operand:SI 3 "const_int_operand" "n")))
7314 (set (match_operand:DI 0 "register_operand" "=d")
7315 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7316 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7317 && (INTVAL (operands[3]) & 63) == 63"
7319 [(set_attr "op_type" "RS")
7320 (set_attr "atype" "reg")])
7322 (define_insn "*ashrdi3_cconly_31_and"
7323 [(set (reg CC_REGNUM)
7324 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7325 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7326 (match_operand:SI 3 "const_int_operand" "n")))
7328 (clobber (match_scratch:DI 0 "=d"))]
7329 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7330 && (INTVAL (operands[3]) & 63) == 63"
7332 [(set_attr "op_type" "RS")
7333 (set_attr "atype" "reg")])
7335 (define_insn "*ashrdi3_31_and"
7336 [(set (match_operand:DI 0 "register_operand" "=d")
7337 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7338 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7339 (match_operand:SI 3 "const_int_operand" "n"))))
7340 (clobber (reg:CC CC_REGNUM))]
7341 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7343 [(set_attr "op_type" "RS")
7344 (set_attr "atype" "reg")])
7347 (define_insn "*ashr<mode>3_cc_and"
7348 [(set (reg CC_REGNUM)
7349 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7350 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7351 (match_operand:SI 3 "const_int_operand" "n")))
7353 (set (match_operand:GPR 0 "register_operand" "=d")
7354 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7355 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7357 [(set_attr "op_type" "RS<E>")
7358 (set_attr "atype" "reg")
7359 (set_attr "z10prop" "z10_super_E1")])
7362 (define_insn "*ashr<mode>3_cconly_and"
7363 [(set (reg CC_REGNUM)
7364 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7365 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7366 (match_operand:SI 3 "const_int_operand" "n")))
7368 (clobber (match_scratch:GPR 0 "=d"))]
7369 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7371 [(set_attr "op_type" "RS<E>")
7372 (set_attr "atype" "reg")
7373 (set_attr "z10prop" "z10_super_E1")])
7376 (define_insn "*ashr<mode>3_and"
7377 [(set (match_operand:GPR 0 "register_operand" "=d")
7378 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7379 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7380 (match_operand:SI 3 "const_int_operand" "n"))))
7381 (clobber (reg:CC CC_REGNUM))]
7382 "(INTVAL (operands[3]) & 63) == 63"
7384 [(set_attr "op_type" "RS<E>")
7385 (set_attr "atype" "reg")
7386 (set_attr "z10prop" "z10_super_E1")])
7390 ;; Branch instruction patterns.
7393 (define_expand "cbranch<mode>4"
7395 (if_then_else (match_operator 0 "comparison_operator"
7396 [(match_operand:GPR 1 "register_operand" "")
7397 (match_operand:GPR 2 "general_operand" "")])
7398 (label_ref (match_operand 3 "" ""))
7401 "s390_emit_jump (operands[3],
7402 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7405 (define_expand "cbranch<mode>4"
7407 (if_then_else (match_operator 0 "comparison_operator"
7408 [(match_operand:FP 1 "register_operand" "")
7409 (match_operand:FP 2 "general_operand" "")])
7410 (label_ref (match_operand 3 "" ""))
7413 "s390_emit_jump (operands[3],
7414 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7417 (define_expand "cbranchcc4"
7419 (if_then_else (match_operator 0 "s390_eqne_operator"
7420 [(match_operand 1 "cc_reg_operand" "")
7421 (match_operand 2 "const0_operand" "")])
7422 (label_ref (match_operand 3 "" ""))
7425 "s390_emit_jump (operands[3],
7426 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7432 ;;- Conditional jump instructions.
7435 (define_insn "*cjump_64"
7438 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7439 (label_ref (match_operand 0 "" ""))
7443 if (get_attr_length (insn) == 4)
7446 return "jg%C1\t%l0";
7448 [(set_attr "op_type" "RI")
7449 (set_attr "type" "branch")
7450 (set (attr "length")
7451 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7452 (const_int 4) (const_int 6)))])
7454 (define_insn "*cjump_31"
7457 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7458 (label_ref (match_operand 0 "" ""))
7462 gcc_assert (get_attr_length (insn) == 4);
7465 [(set_attr "op_type" "RI")
7466 (set_attr "type" "branch")
7467 (set (attr "length")
7468 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7469 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7470 (const_int 4) (const_int 6))
7471 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7472 (const_int 4) (const_int 8))))])
7474 (define_insn "*cjump_long"
7477 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7478 (match_operand 0 "address_operand" "ZQZR")
7482 if (get_attr_op_type (insn) == OP_TYPE_RR)
7487 [(set (attr "op_type")
7488 (if_then_else (match_operand 0 "register_operand" "")
7489 (const_string "RR") (const_string "RX")))
7490 (set_attr "type" "branch")
7491 (set_attr "atype" "agen")])
7495 ;;- Negated conditional jump instructions.
7498 (define_insn "*icjump_64"
7501 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7503 (label_ref (match_operand 0 "" ""))))]
7506 if (get_attr_length (insn) == 4)
7509 return "jg%D1\t%l0";
7511 [(set_attr "op_type" "RI")
7512 (set_attr "type" "branch")
7513 (set (attr "length")
7514 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7515 (const_int 4) (const_int 6)))])
7517 (define_insn "*icjump_31"
7520 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7522 (label_ref (match_operand 0 "" ""))))]
7525 gcc_assert (get_attr_length (insn) == 4);
7528 [(set_attr "op_type" "RI")
7529 (set_attr "type" "branch")
7530 (set (attr "length")
7531 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7532 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7533 (const_int 4) (const_int 6))
7534 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7535 (const_int 4) (const_int 8))))])
7537 (define_insn "*icjump_long"
7540 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7542 (match_operand 0 "address_operand" "ZQZR")))]
7545 if (get_attr_op_type (insn) == OP_TYPE_RR)
7550 [(set (attr "op_type")
7551 (if_then_else (match_operand 0 "register_operand" "")
7552 (const_string "RR") (const_string "RX")))
7553 (set_attr "type" "branch")
7554 (set_attr "atype" "agen")])
7557 ;;- Trap instructions.
7561 [(trap_if (const_int 1) (const_int 0))]
7564 [(set_attr "op_type" "RI")
7565 (set_attr "type" "branch")])
7567 (define_expand "ctrap<mode>4"
7568 [(trap_if (match_operator 0 "comparison_operator"
7569 [(match_operand:GPR 1 "register_operand" "")
7570 (match_operand:GPR 2 "general_operand" "")])
7571 (match_operand 3 "const0_operand" ""))]
7574 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7575 operands[1], operands[2]);
7576 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7580 (define_expand "ctrap<mode>4"
7581 [(trap_if (match_operator 0 "comparison_operator"
7582 [(match_operand:FP 1 "register_operand" "")
7583 (match_operand:FP 2 "general_operand" "")])
7584 (match_operand 3 "const0_operand" ""))]
7587 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7588 operands[1], operands[2]);
7589 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7593 (define_insn "condtrap"
7594 [(trap_if (match_operator 0 "s390_comparison"
7595 [(match_operand 1 "cc_reg_operand" "c")
7600 [(set_attr "op_type" "RI")
7601 (set_attr "type" "branch")])
7603 ; crt, cgrt, cit, cgit
7604 (define_insn "*cmp_and_trap_signed_int<mode>"
7605 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
7606 [(match_operand:GPR 1 "register_operand" "d,d")
7607 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
7613 [(set_attr "op_type" "RRF,RIE")
7614 (set_attr "type" "branch")
7615 (set_attr "z10prop" "z10_super_c,z10_super")])
7617 ; clrt, clgrt, clfit, clgit
7618 (define_insn "*cmp_and_trap_unsigned_int<mode>"
7619 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
7620 [(match_operand:GPR 1 "register_operand" "d,d")
7621 (match_operand:GPR 2 "nonmemory_operand" "d,D")])
7626 cl<gf>it%C0\t%1,%x2"
7627 [(set_attr "op_type" "RRF,RIE")
7628 (set_attr "type" "branch")
7629 (set_attr "z10prop" "z10_super_c,z10_super")])
7632 ;;- Loop instructions.
7634 ;; This is all complicated by the fact that since this is a jump insn
7635 ;; we must handle our own output reloads.
7639 ; This splitter will be matched by combine and has to add the 2 moves
7640 ; necessary to load the compare and the increment values into a
7641 ; register pair as needed by brxle.
7643 (define_insn_and_split "*brx_stage1_<GPR:mode>"
7646 (match_operator 6 "s390_brx_operator"
7647 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
7648 (match_operand:GPR 2 "general_operand" ""))
7649 (match_operand:GPR 3 "register_operand" "")])
7650 (label_ref (match_operand 0 "" ""))
7652 (set (match_operand:GPR 4 "nonimmediate_operand" "")
7653 (plus:GPR (match_dup 1) (match_dup 2)))
7654 (clobber (match_scratch:GPR 5 ""))]
7657 "!reload_completed && !reload_in_progress"
7658 [(set (match_dup 7) (match_dup 2)) ; the increment
7659 (set (match_dup 8) (match_dup 3)) ; the comparison value
7660 (parallel [(set (pc)
7663 [(plus:GPR (match_dup 1) (match_dup 7))
7665 (label_ref (match_dup 0))
7668 (plus:GPR (match_dup 1) (match_dup 7)))
7669 (clobber (match_dup 5))
7670 (clobber (reg:CC CC_REGNUM))])]
7672 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
7673 operands[7] = gen_lowpart (<GPR:MODE>mode,
7674 gen_highpart (word_mode, dreg));
7675 operands[8] = gen_lowpart (<GPR:MODE>mode,
7676 gen_lowpart (word_mode, dreg));
7681 (define_insn_and_split "*brxg_64bit"
7684 (match_operator 5 "s390_brx_operator"
7685 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
7686 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
7687 (subreg:DI (match_dup 2) 8)])
7688 (label_ref (match_operand 0 "" ""))
7690 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
7691 (plus:DI (match_dup 1)
7692 (subreg:DI (match_dup 2) 0)))
7693 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
7694 (clobber (reg:CC CC_REGNUM))]
7697 if (which_alternative != 0)
7699 else if (get_attr_length (insn) == 6)
7700 return "brx%E5g\t%1,%2,%l0";
7702 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
7704 "&& reload_completed
7705 && (!REG_P (operands[3])
7706 || !rtx_equal_p (operands[1], operands[3]))"
7707 [(set (match_dup 4) (match_dup 1))
7708 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
7709 (clobber (reg:CC CC_REGNUM))])
7710 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
7711 (set (match_dup 3) (match_dup 4))
7712 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
7713 (label_ref (match_dup 0))
7716 [(set_attr "op_type" "RIE")
7717 (set_attr "type" "branch")
7718 (set (attr "length")
7719 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7720 (const_int 6) (const_int 16)))])
7724 (define_insn_and_split "*brx_64bit"
7727 (match_operator 5 "s390_brx_operator"
7728 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
7729 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
7730 (subreg:SI (match_dup 2) 12)])
7731 (label_ref (match_operand 0 "" ""))
7733 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
7734 (plus:SI (match_dup 1)
7735 (subreg:SI (match_dup 2) 4)))
7736 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
7737 (clobber (reg:CC CC_REGNUM))]
7740 if (which_alternative != 0)
7742 else if (get_attr_length (insn) == 6)
7743 return "brx%C5\t%1,%2,%l0";
7745 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
7747 "&& reload_completed
7748 && (!REG_P (operands[3])
7749 || !rtx_equal_p (operands[1], operands[3]))"
7750 [(set (match_dup 4) (match_dup 1))
7751 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
7752 (clobber (reg:CC CC_REGNUM))])
7753 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
7754 (set (match_dup 3) (match_dup 4))
7755 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
7756 (label_ref (match_dup 0))
7759 [(set_attr "op_type" "RSI")
7760 (set_attr "type" "branch")
7761 (set (attr "length")
7762 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7763 (const_int 6) (const_int 14)))])
7767 (define_insn_and_split "*brx_31bit"
7770 (match_operator 5 "s390_brx_operator"
7771 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
7772 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
7773 (subreg:SI (match_dup 2) 4)])
7774 (label_ref (match_operand 0 "" ""))
7776 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
7777 (plus:SI (match_dup 1)
7778 (subreg:SI (match_dup 2) 0)))
7779 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
7780 (clobber (reg:CC CC_REGNUM))]
7781 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
7783 if (which_alternative != 0)
7785 else if (get_attr_length (insn) == 6)
7786 return "brx%C5\t%1,%2,%l0";
7788 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
7790 "&& reload_completed
7791 && (!REG_P (operands[3])
7792 || !rtx_equal_p (operands[1], operands[3]))"
7793 [(set (match_dup 4) (match_dup 1))
7794 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
7795 (clobber (reg:CC CC_REGNUM))])
7796 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
7797 (set (match_dup 3) (match_dup 4))
7798 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
7799 (label_ref (match_dup 0))
7802 [(set_attr "op_type" "RSI")
7803 (set_attr "type" "branch")
7804 (set (attr "length")
7805 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7806 (const_int 6) (const_int 14)))])
7811 (define_expand "doloop_end"
7812 [(use (match_operand 0 "" "")) ; loop pseudo
7813 (use (match_operand 1 "" "")) ; iterations; zero if unknown
7814 (use (match_operand 2 "" "")) ; max iterations
7815 (use (match_operand 3 "" "")) ; loop level
7816 (use (match_operand 4 "" ""))] ; label
7819 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
7820 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
7821 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
7822 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
7823 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
7824 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
7831 (define_insn_and_split "doloop_si64"
7834 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7836 (label_ref (match_operand 0 "" ""))
7838 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7839 (plus:SI (match_dup 1) (const_int -1)))
7840 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7841 (clobber (reg:CC CC_REGNUM))]
7844 if (which_alternative != 0)
7846 else if (get_attr_length (insn) == 4)
7847 return "brct\t%1,%l0";
7849 return "ahi\t%1,-1\;jgne\t%l0";
7851 "&& reload_completed
7852 && (! REG_P (operands[2])
7853 || ! rtx_equal_p (operands[1], operands[2]))"
7854 [(set (match_dup 3) (match_dup 1))
7855 (parallel [(set (reg:CCAN CC_REGNUM)
7856 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7858 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7859 (set (match_dup 2) (match_dup 3))
7860 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7861 (label_ref (match_dup 0))
7864 [(set_attr "op_type" "RI")
7865 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7866 ; hurt us in the (rare) case of ahi.
7867 (set_attr "z10prop" "z10_super_E1")
7868 (set_attr "type" "branch")
7869 (set (attr "length")
7870 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7871 (const_int 4) (const_int 10)))])
7873 (define_insn_and_split "doloop_si31"
7876 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7878 (label_ref (match_operand 0 "" ""))
7880 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7881 (plus:SI (match_dup 1) (const_int -1)))
7882 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7883 (clobber (reg:CC CC_REGNUM))]
7886 if (which_alternative != 0)
7888 else if (get_attr_length (insn) == 4)
7889 return "brct\t%1,%l0";
7893 "&& reload_completed
7894 && (! REG_P (operands[2])
7895 || ! rtx_equal_p (operands[1], operands[2]))"
7896 [(set (match_dup 3) (match_dup 1))
7897 (parallel [(set (reg:CCAN CC_REGNUM)
7898 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7900 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7901 (set (match_dup 2) (match_dup 3))
7902 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7903 (label_ref (match_dup 0))
7906 [(set_attr "op_type" "RI")
7907 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7908 ; hurt us in the (rare) case of ahi.
7909 (set_attr "z10prop" "z10_super_E1")
7910 (set_attr "type" "branch")
7911 (set (attr "length")
7912 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7913 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7914 (const_int 4) (const_int 6))
7915 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7916 (const_int 4) (const_int 8))))])
7918 (define_insn "*doloop_si_long"
7921 (ne (match_operand:SI 1 "register_operand" "d")
7923 (match_operand 0 "address_operand" "ZQZR")
7925 (set (match_operand:SI 2 "register_operand" "=1")
7926 (plus:SI (match_dup 1) (const_int -1)))
7927 (clobber (match_scratch:SI 3 "=X"))
7928 (clobber (reg:CC CC_REGNUM))]
7931 if (get_attr_op_type (insn) == OP_TYPE_RR)
7932 return "bctr\t%1,%0";
7934 return "bct\t%1,%a0";
7936 [(set (attr "op_type")
7937 (if_then_else (match_operand 0 "register_operand" "")
7938 (const_string "RR") (const_string "RX")))
7939 (set_attr "type" "branch")
7940 (set_attr "atype" "agen")
7941 (set_attr "z10prop" "z10_c")])
7943 (define_insn_and_split "doloop_di"
7946 (ne (match_operand:DI 1 "register_operand" "d,d,d")
7948 (label_ref (match_operand 0 "" ""))
7950 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
7951 (plus:DI (match_dup 1) (const_int -1)))
7952 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
7953 (clobber (reg:CC CC_REGNUM))]
7956 if (which_alternative != 0)
7958 else if (get_attr_length (insn) == 4)
7959 return "brctg\t%1,%l0";
7961 return "aghi\t%1,-1\;jgne\t%l0";
7963 "&& reload_completed
7964 && (! REG_P (operands[2])
7965 || ! rtx_equal_p (operands[1], operands[2]))"
7966 [(set (match_dup 3) (match_dup 1))
7967 (parallel [(set (reg:CCAN CC_REGNUM)
7968 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
7970 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
7971 (set (match_dup 2) (match_dup 3))
7972 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7973 (label_ref (match_dup 0))
7976 [(set_attr "op_type" "RI")
7977 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7978 ; hurt us in the (rare) case of ahi.
7979 (set_attr "z10prop" "z10_super_E1")
7980 (set_attr "type" "branch")
7981 (set (attr "length")
7982 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7983 (const_int 4) (const_int 10)))])
7986 ;;- Unconditional jump instructions.
7990 ; jump instruction pattern(s).
7993 (define_expand "jump"
7994 [(match_operand 0 "" "")]
7996 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
7998 (define_insn "*jump64"
7999 [(set (pc) (label_ref (match_operand 0 "" "")))]
8002 if (get_attr_length (insn) == 4)
8007 [(set_attr "op_type" "RI")
8008 (set_attr "type" "branch")
8009 (set (attr "length")
8010 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8011 (const_int 4) (const_int 6)))])
8013 (define_insn "*jump31"
8014 [(set (pc) (label_ref (match_operand 0 "" "")))]
8017 gcc_assert (get_attr_length (insn) == 4);
8020 [(set_attr "op_type" "RI")
8021 (set_attr "type" "branch")
8022 (set (attr "length")
8023 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
8024 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8025 (const_int 4) (const_int 6))
8026 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8027 (const_int 4) (const_int 8))))])
8030 ; indirect-jump instruction pattern(s).
8033 (define_insn "indirect_jump"
8034 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8037 if (get_attr_op_type (insn) == OP_TYPE_RR)
8042 [(set (attr "op_type")
8043 (if_then_else (match_operand 0 "register_operand" "")
8044 (const_string "RR") (const_string "RX")))
8045 (set_attr "type" "branch")
8046 (set_attr "atype" "agen")])
8049 ; casesi instruction pattern(s).
8052 (define_insn "casesi_jump"
8053 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8054 (use (label_ref (match_operand 1 "" "")))]
8057 if (get_attr_op_type (insn) == OP_TYPE_RR)
8062 [(set (attr "op_type")
8063 (if_then_else (match_operand 0 "register_operand" "")
8064 (const_string "RR") (const_string "RX")))
8065 (set_attr "type" "branch")
8066 (set_attr "atype" "agen")])
8068 (define_expand "casesi"
8069 [(match_operand:SI 0 "general_operand" "")
8070 (match_operand:SI 1 "general_operand" "")
8071 (match_operand:SI 2 "general_operand" "")
8072 (label_ref (match_operand 3 "" ""))
8073 (label_ref (match_operand 4 "" ""))]
8076 rtx index = gen_reg_rtx (SImode);
8077 rtx base = gen_reg_rtx (Pmode);
8078 rtx target = gen_reg_rtx (Pmode);
8080 emit_move_insn (index, operands[0]);
8081 emit_insn (gen_subsi3 (index, index, operands[1]));
8082 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8085 if (Pmode != SImode)
8086 index = convert_to_mode (Pmode, index, 1);
8087 if (GET_CODE (index) != REG)
8088 index = copy_to_mode_reg (Pmode, index);
8091 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8093 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8095 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8097 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8098 emit_move_insn (target, index);
8101 target = gen_rtx_PLUS (Pmode, base, target);
8102 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8109 ;;- Jump to subroutine.
8114 ; untyped call instruction pattern(s).
8117 ;; Call subroutine returning any type.
8118 (define_expand "untyped_call"
8119 [(parallel [(call (match_operand 0 "" "")
8121 (match_operand 1 "" "")
8122 (match_operand 2 "" "")])]
8127 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8129 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8131 rtx set = XVECEXP (operands[2], 0, i);
8132 emit_move_insn (SET_DEST (set), SET_SRC (set));
8135 /* The optimizer does not know that the call sets the function value
8136 registers we stored in the result block. We avoid problems by
8137 claiming that all hard registers are used and clobbered at this
8139 emit_insn (gen_blockage ());
8144 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8145 ;; all of memory. This blocks insns from being moved across this point.
8147 (define_insn "blockage"
8148 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8151 [(set_attr "type" "none")
8152 (set_attr "length" "0")])
8158 (define_expand "sibcall"
8159 [(call (match_operand 0 "" "")
8160 (match_operand 1 "" ""))]
8163 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8167 (define_insn "*sibcall_br"
8168 [(call (mem:QI (reg SIBCALL_REGNUM))
8169 (match_operand 0 "const_int_operand" "n"))]
8170 "SIBLING_CALL_P (insn)
8171 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8173 [(set_attr "op_type" "RR")
8174 (set_attr "type" "branch")
8175 (set_attr "atype" "agen")])
8177 (define_insn "*sibcall_brc"
8178 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8179 (match_operand 1 "const_int_operand" "n"))]
8180 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8182 [(set_attr "op_type" "RI")
8183 (set_attr "type" "branch")])
8185 (define_insn "*sibcall_brcl"
8186 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8187 (match_operand 1 "const_int_operand" "n"))]
8188 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8190 [(set_attr "op_type" "RIL")
8191 (set_attr "type" "branch")])
8194 ; sibcall_value patterns
8197 (define_expand "sibcall_value"
8198 [(set (match_operand 0 "" "")
8199 (call (match_operand 1 "" "")
8200 (match_operand 2 "" "")))]
8203 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8207 (define_insn "*sibcall_value_br"
8208 [(set (match_operand 0 "" "")
8209 (call (mem:QI (reg SIBCALL_REGNUM))
8210 (match_operand 1 "const_int_operand" "n")))]
8211 "SIBLING_CALL_P (insn)
8212 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8214 [(set_attr "op_type" "RR")
8215 (set_attr "type" "branch")
8216 (set_attr "atype" "agen")])
8218 (define_insn "*sibcall_value_brc"
8219 [(set (match_operand 0 "" "")
8220 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8221 (match_operand 2 "const_int_operand" "n")))]
8222 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8224 [(set_attr "op_type" "RI")
8225 (set_attr "type" "branch")])
8227 (define_insn "*sibcall_value_brcl"
8228 [(set (match_operand 0 "" "")
8229 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8230 (match_operand 2 "const_int_operand" "n")))]
8231 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8233 [(set_attr "op_type" "RIL")
8234 (set_attr "type" "branch")])
8238 ; call instruction pattern(s).
8241 (define_expand "call"
8242 [(call (match_operand 0 "" "")
8243 (match_operand 1 "" ""))
8244 (use (match_operand 2 "" ""))]
8247 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8248 gen_rtx_REG (Pmode, RETURN_REGNUM));
8252 (define_insn "*bras"
8253 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8254 (match_operand 1 "const_int_operand" "n"))
8255 (clobber (match_operand 2 "register_operand" "=r"))]
8256 "!SIBLING_CALL_P (insn)
8257 && TARGET_SMALL_EXEC
8258 && GET_MODE (operands[2]) == Pmode"
8260 [(set_attr "op_type" "RI")
8261 (set_attr "type" "jsr")])
8263 (define_insn "*brasl"
8264 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8265 (match_operand 1 "const_int_operand" "n"))
8266 (clobber (match_operand 2 "register_operand" "=r"))]
8267 "!SIBLING_CALL_P (insn)
8269 && GET_MODE (operands[2]) == Pmode"
8271 [(set_attr "op_type" "RIL")
8272 (set_attr "type" "jsr")])
8274 (define_insn "*basr"
8275 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8276 (match_operand 1 "const_int_operand" "n"))
8277 (clobber (match_operand 2 "register_operand" "=r"))]
8278 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8280 if (get_attr_op_type (insn) == OP_TYPE_RR)
8281 return "basr\t%2,%0";
8283 return "bas\t%2,%a0";
8285 [(set (attr "op_type")
8286 (if_then_else (match_operand 0 "register_operand" "")
8287 (const_string "RR") (const_string "RX")))
8288 (set_attr "type" "jsr")
8289 (set_attr "atype" "agen")])
8292 ; call_value instruction pattern(s).
8295 (define_expand "call_value"
8296 [(set (match_operand 0 "" "")
8297 (call (match_operand 1 "" "")
8298 (match_operand 2 "" "")))
8299 (use (match_operand 3 "" ""))]
8302 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8303 gen_rtx_REG (Pmode, RETURN_REGNUM));
8307 (define_insn "*bras_r"
8308 [(set (match_operand 0 "" "")
8309 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8310 (match_operand:SI 2 "const_int_operand" "n")))
8311 (clobber (match_operand 3 "register_operand" "=r"))]
8312 "!SIBLING_CALL_P (insn)
8313 && TARGET_SMALL_EXEC
8314 && GET_MODE (operands[3]) == Pmode"
8316 [(set_attr "op_type" "RI")
8317 (set_attr "type" "jsr")])
8319 (define_insn "*brasl_r"
8320 [(set (match_operand 0 "" "")
8321 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8322 (match_operand 2 "const_int_operand" "n")))
8323 (clobber (match_operand 3 "register_operand" "=r"))]
8324 "!SIBLING_CALL_P (insn)
8326 && GET_MODE (operands[3]) == Pmode"
8328 [(set_attr "op_type" "RIL")
8329 (set_attr "type" "jsr")])
8331 (define_insn "*basr_r"
8332 [(set (match_operand 0 "" "")
8333 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8334 (match_operand 2 "const_int_operand" "n")))
8335 (clobber (match_operand 3 "register_operand" "=r"))]
8336 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8338 if (get_attr_op_type (insn) == OP_TYPE_RR)
8339 return "basr\t%3,%1";
8341 return "bas\t%3,%a1";
8343 [(set (attr "op_type")
8344 (if_then_else (match_operand 1 "register_operand" "")
8345 (const_string "RR") (const_string "RX")))
8346 (set_attr "type" "jsr")
8347 (set_attr "atype" "agen")])
8350 ;;- Thread-local storage support.
8353 (define_expand "get_tp_64"
8354 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
8358 (define_expand "get_tp_31"
8359 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
8363 (define_expand "set_tp_64"
8364 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
8365 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
8369 (define_expand "set_tp_31"
8370 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
8371 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
8375 (define_insn "*set_tp"
8376 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8379 [(set_attr "type" "none")
8380 (set_attr "length" "0")])
8382 (define_insn "*tls_load_64"
8383 [(set (match_operand:DI 0 "register_operand" "=d")
8384 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8385 (match_operand:DI 2 "" "")]
8389 [(set_attr "op_type" "RXE")
8390 (set_attr "z10prop" "z10_fwd_A3")])
8392 (define_insn "*tls_load_31"
8393 [(set (match_operand:SI 0 "register_operand" "=d,d")
8394 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8395 (match_operand:SI 2 "" "")]
8401 [(set_attr "op_type" "RX,RXY")
8402 (set_attr "type" "load")
8403 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8405 (define_insn "*bras_tls"
8406 [(set (match_operand 0 "" "")
8407 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8408 (match_operand 2 "const_int_operand" "n")))
8409 (clobber (match_operand 3 "register_operand" "=r"))
8410 (use (match_operand 4 "" ""))]
8411 "!SIBLING_CALL_P (insn)
8412 && TARGET_SMALL_EXEC
8413 && GET_MODE (operands[3]) == Pmode"
8415 [(set_attr "op_type" "RI")
8416 (set_attr "type" "jsr")])
8418 (define_insn "*brasl_tls"
8419 [(set (match_operand 0 "" "")
8420 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8421 (match_operand 2 "const_int_operand" "n")))
8422 (clobber (match_operand 3 "register_operand" "=r"))
8423 (use (match_operand 4 "" ""))]
8424 "!SIBLING_CALL_P (insn)
8426 && GET_MODE (operands[3]) == Pmode"
8428 [(set_attr "op_type" "RIL")
8429 (set_attr "type" "jsr")])
8431 (define_insn "*basr_tls"
8432 [(set (match_operand 0 "" "")
8433 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8434 (match_operand 2 "const_int_operand" "n")))
8435 (clobber (match_operand 3 "register_operand" "=r"))
8436 (use (match_operand 4 "" ""))]
8437 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8439 if (get_attr_op_type (insn) == OP_TYPE_RR)
8440 return "basr\t%3,%1%J4";
8442 return "bas\t%3,%a1%J4";
8444 [(set (attr "op_type")
8445 (if_then_else (match_operand 1 "register_operand" "")
8446 (const_string "RR") (const_string "RX")))
8447 (set_attr "type" "jsr")
8448 (set_attr "atype" "agen")])
8451 ;;- Atomic operations
8455 ; memory barrier pattern.
8458 (define_expand "memory_barrier"
8460 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8463 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8464 MEM_VOLATILE_P (operands[0]) = 1;
8467 (define_insn "*memory_barrier"
8468 [(set (match_operand:BLK 0 "" "")
8469 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8472 [(set_attr "op_type" "RR")])
8474 ; Although bcr is superscalar on Z10, this variant will never become part of
8475 ; an execution group.
8478 ; compare and swap patterns.
8481 (define_expand "sync_compare_and_swap<mode>"
8483 [(set (match_operand:TDSI 0 "register_operand" "")
8484 (match_operand:TDSI 1 "memory_operand" ""))
8486 (unspec_volatile:TDSI
8488 (match_operand:TDSI 2 "register_operand" "")
8489 (match_operand:TDSI 3 "register_operand" "")]
8491 (set (reg:CCZ1 CC_REGNUM)
8492 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8495 (define_expand "sync_compare_and_swap<mode>"
8497 [(set (match_operand:HQI 0 "register_operand" "")
8498 (match_operand:HQI 1 "memory_operand" ""))
8500 (unspec_volatile:HQI
8502 (match_operand:HQI 2 "general_operand" "")
8503 (match_operand:HQI 3 "general_operand" "")]
8505 (clobber (reg:CC CC_REGNUM))])]
8507 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
8508 operands[2], operands[3]); DONE;")
8511 (define_insn "*sync_compare_and_swap<mode>"
8512 [(set (match_operand:DW 0 "register_operand" "=r")
8513 (match_operand:DW 1 "memory_operand" "+Q"))
8517 (match_operand:DW 2 "register_operand" "0")
8518 (match_operand:DW 3 "register_operand" "r")]
8520 (set (reg:CCZ1 CC_REGNUM)
8521 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8523 "cds<tg>\t%0,%3,%S1"
8524 [(set_attr "op_type" "RS<TE>")
8525 (set_attr "type" "sem")])
8528 (define_insn "*sync_compare_and_swap<mode>"
8529 [(set (match_operand:GPR 0 "register_operand" "=r")
8530 (match_operand:GPR 1 "memory_operand" "+Q"))
8532 (unspec_volatile:GPR
8534 (match_operand:GPR 2 "register_operand" "0")
8535 (match_operand:GPR 3 "register_operand" "r")]
8537 (set (reg:CCZ1 CC_REGNUM)
8538 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8541 [(set_attr "op_type" "RS<E>")
8542 (set_attr "type" "sem")])
8546 ; Other atomic instruction patterns.
8549 (define_expand "sync_lock_test_and_set<mode>"
8550 [(match_operand:HQI 0 "register_operand")
8551 (match_operand:HQI 1 "memory_operand")
8552 (match_operand:HQI 2 "general_operand")]
8554 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
8555 operands[2], false); DONE;")
8557 (define_expand "sync_<atomic><mode>"
8558 [(set (match_operand:HQI 0 "memory_operand")
8559 (ATOMIC:HQI (match_dup 0)
8560 (match_operand:HQI 1 "general_operand")))]
8562 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
8563 operands[1], false); DONE;")
8565 (define_expand "sync_old_<atomic><mode>"
8566 [(set (match_operand:HQI 0 "register_operand")
8567 (match_operand:HQI 1 "memory_operand"))
8569 (ATOMIC:HQI (match_dup 1)
8570 (match_operand:HQI 2 "general_operand")))]
8572 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8573 operands[2], false); DONE;")
8575 (define_expand "sync_new_<atomic><mode>"
8576 [(set (match_operand:HQI 0 "register_operand")
8577 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
8578 (match_operand:HQI 2 "general_operand")))
8579 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
8581 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8582 operands[2], true); DONE;")
8585 ;;- Miscellaneous instructions.
8589 ; allocate stack instruction pattern(s).
8592 (define_expand "allocate_stack"
8593 [(match_operand 0 "general_operand" "")
8594 (match_operand 1 "general_operand" "")]
8597 rtx temp = gen_reg_rtx (Pmode);
8599 emit_move_insn (temp, s390_back_chain_rtx ());
8600 anti_adjust_stack (operands[1]);
8601 emit_move_insn (s390_back_chain_rtx (), temp);
8603 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
8609 ; setjmp instruction pattern.
8612 (define_expand "builtin_setjmp_receiver"
8613 [(match_operand 0 "" "")]
8616 emit_insn (s390_load_got ());
8617 emit_use (pic_offset_table_rtx);
8621 ;; These patterns say how to save and restore the stack pointer. We need not
8622 ;; save the stack pointer at function level since we are careful to
8623 ;; preserve the backchain. At block level, we have to restore the backchain
8624 ;; when we restore the stack pointer.
8626 ;; For nonlocal gotos, we must save both the stack pointer and its
8627 ;; backchain and restore both. Note that in the nonlocal case, the
8628 ;; save area is a memory location.
8630 (define_expand "save_stack_function"
8631 [(match_operand 0 "general_operand" "")
8632 (match_operand 1 "general_operand" "")]
8636 (define_expand "restore_stack_function"
8637 [(match_operand 0 "general_operand" "")
8638 (match_operand 1 "general_operand" "")]
8642 (define_expand "restore_stack_block"
8643 [(match_operand 0 "register_operand" "")
8644 (match_operand 1 "register_operand" "")]
8647 rtx temp = gen_reg_rtx (Pmode);
8649 emit_move_insn (temp, s390_back_chain_rtx ());
8650 emit_move_insn (operands[0], operands[1]);
8651 emit_move_insn (s390_back_chain_rtx (), temp);
8656 (define_expand "save_stack_nonlocal"
8657 [(match_operand 0 "memory_operand" "")
8658 (match_operand 1 "register_operand" "")]
8661 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8663 /* Copy the backchain to the first word, sp to the second and the
8664 literal pool base to the third. */
8666 rtx save_bc = adjust_address (operands[0], Pmode, 0);
8667 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
8668 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
8670 if (TARGET_BACKCHAIN)
8671 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
8673 emit_move_insn (save_sp, operands[1]);
8674 emit_move_insn (save_bp, base);
8679 (define_expand "restore_stack_nonlocal"
8680 [(match_operand 0 "register_operand" "")
8681 (match_operand 1 "memory_operand" "")]
8684 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8685 rtx temp = NULL_RTX;
8687 /* Restore the backchain from the first word, sp from the second and the
8688 literal pool base from the third. */
8690 rtx save_bc = adjust_address (operands[1], Pmode, 0);
8691 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
8692 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
8694 if (TARGET_BACKCHAIN)
8695 temp = force_reg (Pmode, save_bc);
8697 emit_move_insn (base, save_bp);
8698 emit_move_insn (operands[0], save_sp);
8701 emit_move_insn (s390_back_chain_rtx (), temp);
8707 (define_expand "exception_receiver"
8711 s390_set_has_landing_pad_p (true);
8716 ; nop instruction pattern(s).
8723 [(set_attr "op_type" "RR")
8724 (set_attr "z10prop" "z10_fr_E1")])
8730 [(set_attr "op_type" "RR")])
8734 ; Special literal pool access instruction pattern(s).
8737 (define_insn "*pool_entry"
8738 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
8739 UNSPECV_POOL_ENTRY)]
8742 enum machine_mode mode = GET_MODE (PATTERN (insn));
8743 unsigned int align = GET_MODE_BITSIZE (mode);
8744 s390_output_pool_entry (operands[0], mode, align);
8747 [(set (attr "length")
8748 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
8750 (define_insn "pool_align"
8751 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
8752 UNSPECV_POOL_ALIGN)]
8755 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8757 (define_insn "pool_section_start"
8758 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
8761 [(set_attr "length" "0")])
8763 (define_insn "pool_section_end"
8764 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
8767 [(set_attr "length" "0")])
8769 (define_insn "main_base_31_small"
8770 [(set (match_operand 0 "register_operand" "=a")
8771 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8772 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8774 [(set_attr "op_type" "RR")
8775 (set_attr "type" "la")])
8777 (define_insn "main_base_31_large"
8778 [(set (match_operand 0 "register_operand" "=a")
8779 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
8780 (set (pc) (label_ref (match_operand 2 "" "")))]
8781 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8783 [(set_attr "op_type" "RI")])
8785 (define_insn "main_base_64"
8786 [(set (match_operand 0 "register_operand" "=a")
8787 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8788 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8790 [(set_attr "op_type" "RIL")
8791 (set_attr "type" "larl")
8792 (set_attr "z10prop" "z10_fwd_A1")])
8794 (define_insn "main_pool"
8795 [(set (match_operand 0 "register_operand" "=a")
8796 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
8797 "GET_MODE (operands[0]) == Pmode"
8802 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
8803 (const_string "larl") (const_string "la")))])
8805 (define_insn "reload_base_31"
8806 [(set (match_operand 0 "register_operand" "=a")
8807 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8808 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8809 "basr\t%0,0\;la\t%0,%1-.(%0)"
8810 [(set_attr "length" "6")
8811 (set_attr "type" "la")])
8813 (define_insn "reload_base_64"
8814 [(set (match_operand 0 "register_operand" "=a")
8815 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8816 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8818 [(set_attr "op_type" "RIL")
8819 (set_attr "type" "larl")
8820 (set_attr "z10prop" "z10_fwd_A1")])
8823 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
8828 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8831 ;; Insns related to generating the function prologue and epilogue.
8835 (define_expand "prologue"
8836 [(use (const_int 0))]
8838 "s390_emit_prologue (); DONE;")
8840 (define_expand "epilogue"
8841 [(use (const_int 1))]
8843 "s390_emit_epilogue (false); DONE;")
8845 (define_expand "sibcall_epilogue"
8846 [(use (const_int 0))]
8848 "s390_emit_epilogue (true); DONE;")
8850 (define_insn "*return"
8852 (use (match_operand 0 "register_operand" "a"))]
8853 "GET_MODE (operands[0]) == Pmode"
8855 [(set_attr "op_type" "RR")
8856 (set_attr "type" "jsr")
8857 (set_attr "atype" "agen")])
8860 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
8861 ;; pointer. This is used for compatibility.
8863 (define_expand "ptr_extend"
8864 [(set (match_operand:DI 0 "register_operand" "=r")
8865 (match_operand:SI 1 "register_operand" "r"))]
8868 emit_insn (gen_anddi3 (operands[0],
8869 gen_lowpart (DImode, operands[1]),
8870 GEN_INT (0x7fffffff)));
8874 ;; Instruction definition to expand eh_return macro to support
8875 ;; swapping in special linkage return addresses.
8877 (define_expand "eh_return"
8878 [(use (match_operand 0 "register_operand" ""))]
8881 s390_emit_tpf_eh_return (operands[0]);
8886 ; Stack Protector Patterns
8889 (define_expand "stack_protect_set"
8890 [(set (match_operand 0 "memory_operand" "")
8891 (match_operand 1 "memory_operand" ""))]
8894 #ifdef TARGET_THREAD_SSP_OFFSET
8896 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8897 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8900 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
8902 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
8907 (define_insn "stack_protect_set<mode>"
8908 [(set (match_operand:DSI 0 "memory_operand" "=Q")
8909 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
8911 "mvc\t%O0(%G0,%R0),%S1"
8912 [(set_attr "op_type" "SS")])
8914 (define_expand "stack_protect_test"
8915 [(set (reg:CC CC_REGNUM)
8916 (compare (match_operand 0 "memory_operand" "")
8917 (match_operand 1 "memory_operand" "")))
8918 (match_operand 2 "" "")]
8922 #ifdef TARGET_THREAD_SSP_OFFSET
8924 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8925 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8928 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
8930 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
8932 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
8933 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
8934 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
8938 (define_insn "stack_protect_test<mode>"
8939 [(set (reg:CCZ CC_REGNUM)
8940 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
8941 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
8943 "clc\t%O0(%G0,%R0),%S1"
8944 [(set_attr "op_type" "SS")])
8946 ; This is used in s390_emit_prologue in order to prevent insns
8947 ; adjusting the stack pointer to be moved over insns writing stack
8948 ; slots using a copy of the stack pointer in a different register.
8949 (define_insn "stack_tie"
8950 [(set (match_operand:BLK 0 "memory_operand" "+m")
8951 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
8954 [(set_attr "length" "0")])
8958 ; Data prefetch patterns
8961 (define_insn "prefetch"
8962 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
8963 (match_operand:SI 1 "const_int_operand" " n,n")
8964 (match_operand:SI 2 "const_int_operand" " n,n"))]
8967 switch (which_alternative)
8970 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
8972 if (larl_operand (operands[0], Pmode))
8973 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
8976 /* This might be reached for symbolic operands with an odd
8977 addend. We simply omit the prefetch for such rare cases. */
8982 [(set_attr "type" "load,larl")
8983 (set_attr "op_type" "RXY,RIL")
8984 (set_attr "z10prop" "z10_super")])
8988 ; Byte swap instructions
8991 (define_insn "bswap<mode>2"
8992 [(set (match_operand:GPR 0 "register_operand" "=d, d")
8993 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
8998 [(set_attr "type" "*,load")
8999 (set_attr "op_type" "RRE,RXY")
9000 (set_attr "z10prop" "z10_super")])