1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 ;; 2009, 2010 Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
68 ; GOT/PLT and lt-relative accesses
69 (UNSPEC_LTREL_OFFSET 100)
70 (UNSPEC_LTREL_BASE 101)
71 (UNSPEC_POOL_OFFSET 102)
79 (UNSPEC_RELOAD_BASE 210)
80 (UNSPEC_MAIN_BASE 211)
88 ; TLS relocation specifiers
93 (UNSPEC_GOTNTPOFF 504)
94 (UNSPEC_INDNTPOFF 505)
97 (UNSPEC_TLSLDM_NTPOFF 511)
104 ; Stack Smashing Protector
108 ; Test Data Class (TDC)
109 (UNSPEC_TDC_INSN 800)
113 ;; UNSPEC_VOLATILE usage
121 (UNSPECV_TPF_PROLOGUE 20)
122 (UNSPECV_TPF_EPILOGUE 21)
126 (UNSPECV_POOL_SECTION 201)
127 (UNSPECV_POOL_ALIGN 202)
128 (UNSPECV_POOL_ENTRY 203)
129 (UNSPECV_MAIN_POOL 300)
142 ; Registers with special meaning
146 ; Sibling call register.
148 ; Literal pool base register.
150 ; Return address register.
152 ; Condition code register.
154 ; Thread local storage pointer register.
158 ; Hardware register names
162 ; General purpose registers
164 ; Floating point registers.
170 ;; PFPO GPR0 argument format
175 ; PFPO operation type
176 (PFPO_CONVERT 0x1000000)
178 (PFPO_OP_TYPE_SF 0x5)
179 (PFPO_OP_TYPE_DF 0x6)
180 (PFPO_OP_TYPE_TF 0x7)
181 (PFPO_OP_TYPE_SD 0x8)
182 (PFPO_OP_TYPE_DD 0x9)
183 (PFPO_OP_TYPE_TD 0xa)
184 ; Bitposition of operand types
185 (PFPO_OP0_TYPE_SHIFT 16)
186 (PFPO_OP1_TYPE_SHIFT 8)
190 ;; Instruction operand type as used in the Principles of Operation.
191 ;; Used to determine defaults for length and other attribute values.
193 (define_attr "op_type"
194 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
197 ;; Instruction type attribute used for scheduling.
199 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
200 cs,vs,store,sem,idiv,
201 imulhi,imulsi,imuldi,
202 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
203 floadtf,floaddf,floadsf,fstoredf,fstoresf,
204 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
205 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
206 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
207 itoftf, itofdf, itofsf, itofdd, itoftd,
208 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
209 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
211 (cond [(eq_attr "op_type" "NN") (const_string "other")
212 (eq_attr "op_type" "SS") (const_string "cs")]
213 (const_string "integer")))
215 ;; Another attribute used for scheduling purposes:
216 ;; agen: Instruction uses the address generation unit
217 ;; reg: Instruction does not use the agen unit
219 (define_attr "atype" "agen,reg"
220 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
222 (const_string "agen")))
224 ;; Properties concerning Z10 execution grouping and value forwarding.
225 ;; z10_super: instruction is superscalar.
226 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
227 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
228 ;; target register. It can forward this value to a second instruction that reads
229 ;; the same register if that second instruction is issued in the same group.
230 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
231 ;; instruction in the S pipe writes to the register, then the T instruction
232 ;; can immediately read the new value.
233 ;; z10_fr: union of Z10_fwd and z10_rec.
234 ;; z10_c: second operand of instruction is a register and read with complemented bits.
236 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
239 (define_attr "z10prop" "none,
240 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
241 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
243 z10_fr, z10_fr_A3, z10_fr_E1,
245 (const_string "none"))
250 (define_attr "length" ""
251 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
252 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
256 ;; Processor type. This attribute must exactly match the processor_type
257 ;; enumeration in s390.h. The current machine description does not
258 ;; distinguish between g5 and g6, but there are differences between the two
259 ;; CPUs could in theory be modeled.
261 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
262 (const (symbol_ref "s390_tune_attr")))
264 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
265 (const_string "standard"))
267 (define_attr "enabled" ""
268 (cond [(eq_attr "cpu_facility" "standard")
271 (and (eq_attr "cpu_facility" "ieee")
272 (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0)))
275 (and (eq_attr "cpu_facility" "zarch")
276 (ne (symbol_ref "TARGET_ZARCH") (const_int 0)))
279 (and (eq_attr "cpu_facility" "longdisp")
280 (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0)))
283 (and (eq_attr "cpu_facility" "extimm")
284 (ne (symbol_ref "TARGET_EXTIMM") (const_int 0)))
287 (and (eq_attr "cpu_facility" "dfp")
288 (ne (symbol_ref "TARGET_DFP") (const_int 0)))
291 (and (eq_attr "cpu_facility" "z10")
292 (ne (symbol_ref "TARGET_Z10") (const_int 0)))
296 ;; Pipeline description for z900. For lack of anything better,
297 ;; this description is also used for the g5 and g6.
300 ;; Pipeline description for z990, z9-109 and z9-ec.
303 ;; Pipeline description for z10
307 (include "predicates.md")
309 ;; Constraint definitions
310 (include "constraints.md")
317 ;; These mode iterators allow floating point patterns to be generated from the
319 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
320 (SD "TARGET_HARD_DFP")])
321 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
322 (define_mode_iterator FPALL [TF DF SF TD DD SD])
323 (define_mode_iterator BFP [TF DF SF])
324 (define_mode_iterator DFP [TD DD])
325 (define_mode_iterator DFP_ALL [TD DD SD])
326 (define_mode_iterator DSF [DF SF])
327 (define_mode_iterator SD_SF [SF SD])
328 (define_mode_iterator DD_DF [DF DD])
329 (define_mode_iterator TD_TF [TF TD])
331 ;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated
332 ;; from the same template.
333 (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI])
335 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
336 ;; from the same template.
337 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
338 (define_mode_iterator DSI [DI SI])
340 ;; These mode iterators allow :P to be used for patterns that operate on
341 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
342 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
344 ;; These macros refer to the actual word_mode of the configuration. This is equal
345 ;; to Pmode except on 31-bit machines in zarch mode.
346 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
347 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
349 ;; This mode iterator allows the QI and HI patterns to be defined from
350 ;; the same template.
351 (define_mode_iterator HQI [HI QI])
353 ;; This mode iterator allows the integer patterns to be defined from the
355 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
356 (define_mode_iterator INTALL [TI DI SI HI QI])
358 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
359 ;; the same template.
360 (define_code_iterator SHIFT [ashift lshiftrt])
362 ;; This iterator and attribute allow to combine most atomic operations.
363 (define_code_iterator ATOMIC [and ior xor plus minus mult])
364 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
365 (plus "add") (minus "sub") (mult "nand")])
367 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
368 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
369 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
371 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
372 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
374 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
376 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
377 ;; Likewise for "<RXe>".
378 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
379 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
381 ;; The decimal floating point variants of add, sub, div and mul support 3
382 ;; fp register operands. The following attributes allow to merge the bfp and
383 ;; dfp variants in a single insn definition.
385 ;; This attribute is used to set op_type accordingly.
386 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
387 (DD "RRR") (SD "RRR")])
389 ;; This attribute is used in the operand constraint list in order to have the
390 ;; first and the second operand match for bfp modes.
391 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
393 ;; This attribute is used in the operand list of the instruction to have an
394 ;; additional operand for the dfp instructions.
395 (define_mode_attr op1 [(TF "") (DF "") (SF "")
396 (TD "%1,") (DD "%1,") (SD "%1,")])
399 ;; This attribute is used in the operand constraint list
400 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
401 ;; TFmode values are represented by a fp register pair. Since the
402 ;; sign bit instructions only handle single source and target fp registers
403 ;; these instructions can only be used for TFmode values if the source and
404 ;; target operand uses the same fp register.
405 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
407 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
408 ;; This is used to disable the memory alternative in TFmode patterns.
409 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
411 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
412 ;; within instruction mnemonics.
413 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
415 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
416 ;; modes and to an empty string for bfp modes.
417 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
419 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
420 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
421 ;; version only operates on one register.
422 (define_mode_attr d0 [(DI "d") (SI "0")])
424 ;; In combination with d0 this allows to combine instructions of which the 31bit
425 ;; version only operates on one register. The DImode version needs an additional
426 ;; register for the assembler output.
427 (define_mode_attr 1 [(DI "%1,") (SI "")])
429 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
430 ;; 'ashift' and "srdl" in 'lshiftrt'.
431 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
433 ;; In SHIFT templates, this attribute holds the correct standard name for the
434 ;; pattern itself and the corresponding function calls.
435 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
437 ;; This attribute handles differences in the instruction 'type' and will result
438 ;; in "RRE" for DImode and "RR" for SImode.
439 (define_mode_attr E [(DI "E") (SI "")])
441 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
442 ;; to result in "RXY" for DImode and "RX" for SImode.
443 (define_mode_attr Y [(DI "Y") (SI "")])
445 ;; This attribute handles differences in the instruction 'type' and will result
446 ;; in "RSE" for TImode and "RS" for DImode.
447 (define_mode_attr TE [(TI "E") (DI "")])
449 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
450 ;; and "lcr" in SImode.
451 (define_mode_attr g [(DI "g") (SI "")])
453 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
454 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
455 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
456 ;; variant for long displacements.
457 (define_mode_attr y [(DI "g") (SI "y")])
459 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
460 ;; and "cds" in DImode.
461 (define_mode_attr tg [(TI "g") (DI "")])
463 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
464 ;; and "cfdbr" in SImode.
465 (define_mode_attr gf [(DI "g") (SI "f")])
467 ;; ICM mask required to load MODE value into the lowest subreg
468 ;; of a SImode register.
469 (define_mode_attr icm_lo [(HI "3") (QI "1")])
471 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
472 ;; HImode and "llgc" in QImode.
473 (define_mode_attr hc [(HI "h") (QI "c")])
475 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
477 (define_mode_attr DBL [(DI "TI") (SI "DI")])
479 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
480 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
481 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
483 ;; Maximum unsigned integer that fits in MODE.
484 (define_mode_attr max_uint [(HI "65535") (QI "255")])
487 ;;- Compare instructions.
490 ; Test-under-Mask instructions
492 (define_insn "*tmqi_mem"
493 [(set (reg CC_REGNUM)
494 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
495 (match_operand:QI 1 "immediate_operand" "n,n"))
496 (match_operand:QI 2 "immediate_operand" "n,n")))]
497 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
501 [(set_attr "op_type" "SI,SIY")
502 (set_attr "z10prop" "z10_super,z10_super")])
504 (define_insn "*tmdi_reg"
505 [(set (reg CC_REGNUM)
506 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
507 (match_operand:DI 1 "immediate_operand"
508 "N0HD0,N1HD0,N2HD0,N3HD0"))
509 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
511 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
512 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
518 [(set_attr "op_type" "RI")
519 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
521 (define_insn "*tmsi_reg"
522 [(set (reg CC_REGNUM)
523 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
524 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
525 (match_operand:SI 2 "immediate_operand" "n,n")))]
526 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
527 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
531 [(set_attr "op_type" "RI")
532 (set_attr "z10prop" "z10_super,z10_super")])
534 (define_insn "*tm<mode>_full"
535 [(set (reg CC_REGNUM)
536 (compare (match_operand:HQI 0 "register_operand" "d")
537 (match_operand:HQI 1 "immediate_operand" "n")))]
538 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
540 [(set_attr "op_type" "RI")
541 (set_attr "z10prop" "z10_super")])
545 ; Load-and-Test instructions
548 ; tst(di|si) instruction pattern(s).
550 (define_insn "*tstdi_sign"
551 [(set (reg CC_REGNUM)
555 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
556 (const_int 32)) (const_int 32))
557 (match_operand:DI 1 "const0_operand" "")))
558 (set (match_operand:DI 2 "register_operand" "=d,d")
559 (sign_extend:DI (match_dup 0)))]
560 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
563 [(set_attr "op_type" "RRE,RXY")
564 (set_attr "cpu_facility" "*,z10")
565 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
568 (define_insn "*tst<mode>_extimm"
569 [(set (reg CC_REGNUM)
570 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
571 (match_operand:GPR 1 "const0_operand" "")))
572 (set (match_operand:GPR 2 "register_operand" "=d,d")
574 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
578 [(set_attr "op_type" "RR<E>,RXY")
579 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
582 (define_insn "*tst<mode>_cconly_extimm"
583 [(set (reg CC_REGNUM)
584 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
585 (match_operand:GPR 1 "const0_operand" "")))
586 (clobber (match_scratch:GPR 2 "=X,d"))]
587 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
591 [(set_attr "op_type" "RR<E>,RXY")
592 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
594 (define_insn "*tstdi"
595 [(set (reg CC_REGNUM)
596 (compare (match_operand:DI 0 "register_operand" "d")
597 (match_operand:DI 1 "const0_operand" "")))
598 (set (match_operand:DI 2 "register_operand" "=d")
600 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
602 [(set_attr "op_type" "RRE")
603 (set_attr "z10prop" "z10_fr_E1")])
605 (define_insn "*tstsi"
606 [(set (reg CC_REGNUM)
607 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
608 (match_operand:SI 1 "const0_operand" "")))
609 (set (match_operand:SI 2 "register_operand" "=d,d,d")
611 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
616 [(set_attr "op_type" "RR,RS,RSY")
617 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
619 (define_insn "*tstsi_cconly"
620 [(set (reg CC_REGNUM)
621 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
622 (match_operand:SI 1 "const0_operand" "")))
623 (clobber (match_scratch:SI 2 "=X,d,d"))]
624 "s390_match_ccmode(insn, CCSmode)"
629 [(set_attr "op_type" "RR,RS,RSY")
630 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
632 (define_insn "*tstdi_cconly_31"
633 [(set (reg CC_REGNUM)
634 (compare (match_operand:DI 0 "register_operand" "d")
635 (match_operand:DI 1 "const0_operand" "")))]
636 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
638 [(set_attr "op_type" "RS")
639 (set_attr "atype" "reg")])
642 (define_insn "*tst<mode>_cconly2"
643 [(set (reg CC_REGNUM)
644 (compare (match_operand:GPR 0 "register_operand" "d")
645 (match_operand:GPR 1 "const0_operand" "")))]
646 "s390_match_ccmode(insn, CCSmode)"
648 [(set_attr "op_type" "RR<E>")
649 (set_attr "z10prop" "z10_fr_E1")])
651 ; tst(hi|qi) instruction pattern(s).
653 (define_insn "*tst<mode>CCT"
654 [(set (reg CC_REGNUM)
655 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
656 (match_operand:HQI 1 "const0_operand" "")))
657 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
659 "s390_match_ccmode(insn, CCTmode)"
662 icmy\t%2,<icm_lo>,%S0
664 [(set_attr "op_type" "RS,RSY,RI")
665 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
667 (define_insn "*tsthiCCT_cconly"
668 [(set (reg CC_REGNUM)
669 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
670 (match_operand:HI 1 "const0_operand" "")))
671 (clobber (match_scratch:HI 2 "=d,d,X"))]
672 "s390_match_ccmode(insn, CCTmode)"
677 [(set_attr "op_type" "RS,RSY,RI")
678 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
680 (define_insn "*tstqiCCT_cconly"
681 [(set (reg CC_REGNUM)
682 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
683 (match_operand:QI 1 "const0_operand" "")))]
684 "s390_match_ccmode(insn, CCTmode)"
689 [(set_attr "op_type" "SI,SIY,RI")
690 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
692 (define_insn "*tst<mode>"
693 [(set (reg CC_REGNUM)
694 (compare (match_operand:HQI 0 "s_operand" "Q,S")
695 (match_operand:HQI 1 "const0_operand" "")))
696 (set (match_operand:HQI 2 "register_operand" "=d,d")
698 "s390_match_ccmode(insn, CCSmode)"
701 icmy\t%2,<icm_lo>,%S0"
702 [(set_attr "op_type" "RS,RSY")
703 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
705 (define_insn "*tst<mode>_cconly"
706 [(set (reg CC_REGNUM)
707 (compare (match_operand:HQI 0 "s_operand" "Q,S")
708 (match_operand:HQI 1 "const0_operand" "")))
709 (clobber (match_scratch:HQI 2 "=d,d"))]
710 "s390_match_ccmode(insn, CCSmode)"
713 icmy\t%2,<icm_lo>,%S0"
714 [(set_attr "op_type" "RS,RSY")
715 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
718 ; Compare (equality) instructions
720 (define_insn "*cmpdi_cct"
721 [(set (reg CC_REGNUM)
722 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
723 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
724 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
731 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
732 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
734 (define_insn "*cmpsi_cct"
735 [(set (reg CC_REGNUM)
736 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
737 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
738 "s390_match_ccmode (insn, CCTmode)"
746 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
747 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
749 ; Compare (signed) instructions
751 (define_insn "*cmpdi_ccs_sign"
752 [(set (reg CC_REGNUM)
753 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
755 (match_operand:DI 0 "register_operand" "d, d,d")))]
756 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
761 [(set_attr "op_type" "RRE,RXY,RIL")
762 (set_attr "z10prop" "z10_c,*,*")
763 (set_attr "type" "*,*,larl")])
767 (define_insn "*cmpsi_ccs_sign"
768 [(set (reg CC_REGNUM)
769 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
770 (match_operand:SI 0 "register_operand" "d,d,d")))]
771 "s390_match_ccmode(insn, CCSRmode)"
776 [(set_attr "op_type" "RX,RXY,RIL")
777 (set_attr "cpu_facility" "*,*,z10")
778 (set_attr "type" "*,*,larl")])
780 (define_insn "*cmphi_ccs_z10"
781 [(set (reg CC_REGNUM)
782 (compare (match_operand:HI 0 "s_operand" "Q")
783 (match_operand:HI 1 "immediate_operand" "K")))]
784 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
786 [(set_attr "op_type" "SIL")])
788 (define_insn "*cmpdi_ccs_signhi_rl"
789 [(set (reg CC_REGNUM)
790 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
791 (match_operand:GPR 0 "register_operand" "d,d")))]
792 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
796 [(set_attr "op_type" "RXY,RIL")
797 (set_attr "type" "*,larl")])
799 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
800 (define_insn "*cmp<mode>_ccs"
801 [(set (reg CC_REGNUM)
802 (compare (match_operand:GPR 0 "nonimmediate_operand"
804 (match_operand:GPR 1 "general_operand"
806 "s390_match_ccmode(insn, CCSmode)"
815 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
816 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
817 (set_attr "type" "*,*,*,*,*,*,larl")
818 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
821 ; Compare (unsigned) instructions
823 (define_insn "*cmpsi_ccu_zerohi_rlsi"
824 [(set (reg CC_REGNUM)
825 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
826 "larl_operand" "X")))
827 (match_operand:SI 0 "register_operand" "d")))]
828 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
830 [(set_attr "op_type" "RIL")
831 (set_attr "type" "larl")
832 (set_attr "z10prop" "z10_super")])
835 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
836 [(set (reg CC_REGNUM)
837 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
838 "larl_operand" "X")))
839 (match_operand:GPR 0 "register_operand" "d")))]
840 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
842 [(set_attr "op_type" "RIL")
843 (set_attr "type" "larl")
844 (set_attr "z10prop" "z10_super")])
846 (define_insn "*cmpdi_ccu_zero"
847 [(set (reg CC_REGNUM)
848 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
850 (match_operand:DI 0 "register_operand" "d, d,d")))]
851 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
856 [(set_attr "op_type" "RRE,RXY,RIL")
857 (set_attr "cpu_facility" "*,*,z10")
858 (set_attr "type" "*,*,larl")
859 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
861 (define_insn "*cmpdi_ccu"
862 [(set (reg CC_REGNUM)
863 (compare (match_operand:DI 0 "nonimmediate_operand"
865 (match_operand:DI 1 "general_operand"
866 "d,Op,b,D,RT,BQ,Q")))]
867 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
876 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
877 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
878 (set_attr "type" "*,*,larl,*,*,*,*")
879 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
881 (define_insn "*cmpsi_ccu"
882 [(set (reg CC_REGNUM)
883 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
884 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
885 "s390_match_ccmode (insn, CCUmode)"
895 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
896 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
897 (set_attr "type" "*,*,larl,*,*,*,*,*")
898 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
900 (define_insn "*cmphi_ccu"
901 [(set (reg CC_REGNUM)
902 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
903 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
904 "s390_match_ccmode (insn, CCUmode)
905 && !register_operand (operands[1], HImode)"
912 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
913 (set_attr "cpu_facility" "*,*,z10,*,*")
914 (set_attr "z10prop" "*,*,z10_super,*,*")])
916 (define_insn "*cmpqi_ccu"
917 [(set (reg CC_REGNUM)
918 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
919 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
920 "s390_match_ccmode (insn, CCUmode)
921 && !register_operand (operands[1], QImode)"
929 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
930 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
933 ; Block compare (CLC) instruction patterns.
936 [(set (reg CC_REGNUM)
937 (compare (match_operand:BLK 0 "memory_operand" "Q")
938 (match_operand:BLK 1 "memory_operand" "Q")))
939 (use (match_operand 2 "const_int_operand" "n"))]
940 "s390_match_ccmode (insn, CCUmode)
941 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
942 "clc\t%O0(%2,%R0),%S1"
943 [(set_attr "op_type" "SS")])
946 [(set (reg CC_REGNUM)
947 (compare (match_operand 0 "memory_operand" "")
948 (match_operand 1 "memory_operand" "")))]
950 && s390_match_ccmode (insn, CCUmode)
951 && GET_MODE (operands[0]) == GET_MODE (operands[1])
952 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
954 [(set (match_dup 0) (match_dup 1))
955 (use (match_dup 2))])]
957 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
958 operands[0] = adjust_address (operands[0], BLKmode, 0);
959 operands[1] = adjust_address (operands[1], BLKmode, 0);
961 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
962 operands[0], operands[1]);
963 operands[0] = SET_DEST (PATTERN (curr_insn));
967 ; (TF|DF|SF|TD|DD|SD) instructions
969 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
970 (define_insn "*cmp<mode>_ccs_0"
971 [(set (reg CC_REGNUM)
972 (compare (match_operand:FP 0 "register_operand" "f")
973 (match_operand:FP 1 "const0_operand" "")))]
974 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
975 "lt<xde><bt>r\t%0,%0"
976 [(set_attr "op_type" "RRE")
977 (set_attr "type" "fsimp<mode>")])
979 ; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr
980 (define_insn "*cmp<mode>_ccs"
981 [(set (reg CC_REGNUM)
982 (compare (match_operand:FP 0 "register_operand" "f,f")
983 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
984 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
988 [(set_attr "op_type" "RRE,RXE")
989 (set_attr "type" "fsimp<mode>")])
992 ; Compare and Branch instructions
994 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
995 ; The following instructions do a complementary access of their second
996 ; operand (z01 only): crj_c, cgrjc, cr, cgr
997 (define_insn "*cmp_and_br_signed_<mode>"
999 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1000 [(match_operand:GPR 1 "register_operand" "d,d")
1001 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1002 (label_ref (match_operand 3 "" ""))
1004 (clobber (reg:CC CC_REGNUM))]
1007 if (get_attr_length (insn) == 6)
1008 return which_alternative ?
1009 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1011 return which_alternative ?
1012 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1014 [(set_attr "op_type" "RIE")
1015 (set_attr "type" "branch")
1016 (set_attr "z10prop" "z10_super_c,z10_super")
1017 (set (attr "length")
1018 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1019 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1020 ; 10 byte for cgr/jg
1022 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1023 ; The following instructions do a complementary access of their second
1024 ; operand (z10 only): clrj, clgrj, clr, clgr
1025 (define_insn "*cmp_and_br_unsigned_<mode>"
1027 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1028 [(match_operand:GPR 1 "register_operand" "d,d")
1029 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1030 (label_ref (match_operand 3 "" ""))
1032 (clobber (reg:CC CC_REGNUM))]
1035 if (get_attr_length (insn) == 6)
1036 return which_alternative ?
1037 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1039 return which_alternative ?
1040 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1042 [(set_attr "op_type" "RIE")
1043 (set_attr "type" "branch")
1044 (set_attr "z10prop" "z10_super_c,z10_super")
1045 (set (attr "length")
1046 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1047 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1048 ; 10 byte for clgr/jg
1050 ; And now the same two patterns as above but with a negated CC mask.
1052 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1053 ; The following instructions do a complementary access of their second
1054 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1055 (define_insn "*icmp_and_br_signed_<mode>"
1057 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1058 [(match_operand:GPR 1 "register_operand" "d,d")
1059 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1061 (label_ref (match_operand 3 "" ""))))
1062 (clobber (reg:CC CC_REGNUM))]
1065 if (get_attr_length (insn) == 6)
1066 return which_alternative ?
1067 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1069 return which_alternative ?
1070 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1072 [(set_attr "op_type" "RIE")
1073 (set_attr "type" "branch")
1074 (set_attr "z10prop" "z10_super_c,z10_super")
1075 (set (attr "length")
1076 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1077 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1078 ; 10 byte for cgr/jg
1080 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1081 ; The following instructions do a complementary access of their second
1082 ; operand (z10 only): clrj, clgrj, clr, clgr
1083 (define_insn "*icmp_and_br_unsigned_<mode>"
1085 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1086 [(match_operand:GPR 1 "register_operand" "d,d")
1087 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1089 (label_ref (match_operand 3 "" ""))))
1090 (clobber (reg:CC CC_REGNUM))]
1093 if (get_attr_length (insn) == 6)
1094 return which_alternative ?
1095 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1097 return which_alternative ?
1098 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1100 [(set_attr "op_type" "RIE")
1101 (set_attr "type" "branch")
1102 (set_attr "z10prop" "z10_super_c,z10_super")
1103 (set (attr "length")
1104 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1105 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1106 ; 10 byte for clgr/jg
1109 ;;- Move instructions.
1113 ; movti instruction pattern(s).
1116 (define_insn "movti"
1117 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1118 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1125 [(set_attr "op_type" "RSY,RSY,*,*")
1126 (set_attr "type" "lm,stm,*,*")])
1129 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1130 (match_operand:TI 1 "general_operand" ""))]
1131 "TARGET_ZARCH && reload_completed
1132 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1133 [(set (match_dup 2) (match_dup 4))
1134 (set (match_dup 3) (match_dup 5))]
1136 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1137 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1138 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1139 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1143 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1144 (match_operand:TI 1 "general_operand" ""))]
1145 "TARGET_ZARCH && reload_completed
1146 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1147 [(set (match_dup 2) (match_dup 4))
1148 (set (match_dup 3) (match_dup 5))]
1150 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1151 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1152 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1153 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1157 [(set (match_operand:TI 0 "register_operand" "")
1158 (match_operand:TI 1 "memory_operand" ""))]
1159 "TARGET_ZARCH && reload_completed
1160 && !s_operand (operands[1], VOIDmode)"
1161 [(set (match_dup 0) (match_dup 1))]
1163 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1164 addr = gen_lowpart (Pmode, addr);
1165 s390_load_address (addr, XEXP (operands[1], 0));
1166 operands[1] = replace_equiv_address (operands[1], addr);
1171 ; Patterns used for secondary reloads
1174 ; z10 provides move instructions accepting larl memory operands.
1175 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1176 ; These patterns are also used for unaligned SI and DI accesses.
1178 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1179 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1180 (match_operand:INTALL 1 "register_operand" "=d")
1181 (match_operand:P 2 "register_operand" "=&a")])]
1184 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1188 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1189 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1190 (match_operand:INTALL 1 "memory_operand" "")
1191 (match_operand:P 2 "register_operand" "=a")])]
1194 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1198 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1199 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1200 (match_operand:FPALL 1 "register_operand" "=d")
1201 (match_operand:P 2 "register_operand" "=&a")])]
1204 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1208 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1209 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1210 (match_operand:FPALL 1 "memory_operand" "")
1211 (match_operand:P 2 "register_operand" "=a")])]
1214 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1218 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1219 [(parallel [(match_operand:P 0 "register_operand" "=d")
1220 (match_operand:P 1 "larl_operand" "")
1221 (match_operand:P 2 "register_operand" "=a")])]
1224 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1228 ; Handles loading a PLUS (load address) expression
1230 (define_expand "reload<mode>_plus"
1231 [(parallel [(match_operand:P 0 "register_operand" "=a")
1232 (match_operand:P 1 "s390_plus_operand" "")
1233 (match_operand:P 2 "register_operand" "=&a")])]
1236 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1240 ; Handles assessing a non-offsetable memory address
1242 (define_expand "reload<mode>_nonoffmem_in"
1243 [(parallel [(match_operand 0 "register_operand" "")
1244 (match_operand 1 "" "")
1245 (match_operand:P 2 "register_operand" "=&a")])]
1248 gcc_assert (MEM_P (operands[1]));
1249 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1250 operands[1] = replace_equiv_address (operands[1], operands[2]);
1251 emit_move_insn (operands[0], operands[1]);
1255 (define_expand "reload<mode>_nonoffmem_out"
1256 [(parallel [(match_operand 0 "" "")
1257 (match_operand 1 "register_operand" "")
1258 (match_operand:P 2 "register_operand" "=&a")])]
1261 gcc_assert (MEM_P (operands[0]));
1262 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1263 operands[0] = replace_equiv_address (operands[0], operands[2]);
1264 emit_move_insn (operands[0], operands[1]);
1268 (define_expand "reload<mode>_PIC_addr"
1269 [(parallel [(match_operand 0 "register_operand" "=d")
1270 (match_operand 1 "larl_operand" "")
1271 (match_operand:P 2 "register_operand" "=a")])]
1274 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1275 emit_move_insn (operands[0], new_rtx);
1279 ; movdi instruction pattern(s).
1282 (define_expand "movdi"
1283 [(set (match_operand:DI 0 "general_operand" "")
1284 (match_operand:DI 1 "general_operand" ""))]
1287 /* Handle symbolic constants. */
1289 && (SYMBOLIC_CONST (operands[1])
1290 || (GET_CODE (operands[1]) == PLUS
1291 && XEXP (operands[1], 0) == pic_offset_table_rtx
1292 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1293 emit_symbolic_move (operands);
1296 (define_insn "*movdi_larl"
1297 [(set (match_operand:DI 0 "register_operand" "=d")
1298 (match_operand:DI 1 "larl_operand" "X"))]
1300 && !FP_REG_P (operands[0])"
1302 [(set_attr "op_type" "RIL")
1303 (set_attr "type" "larl")
1304 (set_attr "z10prop" "z10_super_A1")])
1306 (define_insn "*movdi_64"
1307 [(set (match_operand:DI 0 "nonimmediate_operand"
1308 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1309 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1310 (match_operand:DI 1 "general_operand"
1311 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1312 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1341 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1342 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1343 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1344 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1346 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1347 z10,*,*,*,*,*,longdisp,*,longdisp,
1349 (set_attr "z10prop" "z10_fwd_A1,
1378 [(set (match_operand:DI 0 "register_operand" "")
1379 (match_operand:DI 1 "register_operand" ""))]
1380 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1381 [(set (match_dup 2) (match_dup 3))
1382 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1383 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1384 "operands[2] = gen_lowpart (SImode, operands[0]);
1385 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1388 [(set (match_operand:DI 0 "register_operand" "")
1389 (match_operand:DI 1 "register_operand" ""))]
1390 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1391 && dead_or_set_p (insn, operands[1])"
1392 [(set (match_dup 3) (match_dup 2))
1393 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1394 (set (match_dup 4) (match_dup 2))]
1395 "operands[2] = gen_lowpart (SImode, operands[1]);
1396 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1399 [(set (match_operand:DI 0 "register_operand" "")
1400 (match_operand:DI 1 "register_operand" ""))]
1401 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1402 && !dead_or_set_p (insn, operands[1])"
1403 [(set (match_dup 3) (match_dup 2))
1404 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1405 (set (match_dup 4) (match_dup 2))
1406 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1407 "operands[2] = gen_lowpart (SImode, operands[1]);
1408 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1410 (define_insn "*movdi_31"
1411 [(set (match_operand:DI 0 "nonimmediate_operand"
1412 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1413 (match_operand:DI 1 "general_operand"
1414 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1429 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1430 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1431 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1433 ; For a load from a symbol ref we can use one of the target registers
1434 ; together with larl to load the address.
1436 [(set (match_operand:DI 0 "register_operand" "")
1437 (match_operand:DI 1 "memory_operand" ""))]
1438 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1439 && larl_operand (XEXP (operands[1], 0), SImode)"
1440 [(set (match_dup 2) (match_dup 3))
1441 (set (match_dup 0) (match_dup 1))]
1443 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1444 operands[3] = XEXP (operands[1], 0);
1445 operands[1] = replace_equiv_address (operands[1], operands[2]);
1449 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1450 (match_operand:DI 1 "general_operand" ""))]
1451 "!TARGET_ZARCH && reload_completed
1452 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1453 [(set (match_dup 2) (match_dup 4))
1454 (set (match_dup 3) (match_dup 5))]
1456 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1457 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1458 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1459 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1463 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1464 (match_operand:DI 1 "general_operand" ""))]
1465 "!TARGET_ZARCH && reload_completed
1466 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1467 [(set (match_dup 2) (match_dup 4))
1468 (set (match_dup 3) (match_dup 5))]
1470 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1471 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1472 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1473 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1477 [(set (match_operand:DI 0 "register_operand" "")
1478 (match_operand:DI 1 "memory_operand" ""))]
1479 "!TARGET_ZARCH && reload_completed
1480 && !FP_REG_P (operands[0])
1481 && !s_operand (operands[1], VOIDmode)"
1482 [(set (match_dup 0) (match_dup 1))]
1484 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1485 s390_load_address (addr, XEXP (operands[1], 0));
1486 operands[1] = replace_equiv_address (operands[1], addr);
1490 [(set (match_operand:DI 0 "register_operand" "")
1491 (mem:DI (match_operand 1 "address_operand" "")))]
1493 && !FP_REG_P (operands[0])
1494 && GET_CODE (operands[1]) == SYMBOL_REF
1495 && CONSTANT_POOL_ADDRESS_P (operands[1])
1496 && get_pool_mode (operands[1]) == DImode
1497 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1498 [(set (match_dup 0) (match_dup 2))]
1499 "operands[2] = get_pool_constant (operands[1]);")
1501 (define_insn "*la_64"
1502 [(set (match_operand:DI 0 "register_operand" "=d,d")
1503 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1508 [(set_attr "op_type" "RX,RXY")
1509 (set_attr "type" "la")
1510 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1514 [(set (match_operand:DI 0 "register_operand" "")
1515 (match_operand:QI 1 "address_operand" ""))
1516 (clobber (reg:CC CC_REGNUM))])]
1518 && preferred_la_operand_p (operands[1], const0_rtx)"
1519 [(set (match_dup 0) (match_dup 1))]
1523 [(set (match_operand:DI 0 "register_operand" "")
1524 (match_operand:DI 1 "register_operand" ""))
1527 (plus:DI (match_dup 0)
1528 (match_operand:DI 2 "nonmemory_operand" "")))
1529 (clobber (reg:CC CC_REGNUM))])]
1531 && !reg_overlap_mentioned_p (operands[0], operands[2])
1532 && preferred_la_operand_p (operands[1], operands[2])"
1533 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1537 ; movsi instruction pattern(s).
1540 (define_expand "movsi"
1541 [(set (match_operand:SI 0 "general_operand" "")
1542 (match_operand:SI 1 "general_operand" ""))]
1545 /* Handle symbolic constants. */
1547 && (SYMBOLIC_CONST (operands[1])
1548 || (GET_CODE (operands[1]) == PLUS
1549 && XEXP (operands[1], 0) == pic_offset_table_rtx
1550 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1551 emit_symbolic_move (operands);
1554 (define_insn "*movsi_larl"
1555 [(set (match_operand:SI 0 "register_operand" "=d")
1556 (match_operand:SI 1 "larl_operand" "X"))]
1557 "!TARGET_64BIT && TARGET_CPU_ZARCH
1558 && !FP_REG_P (operands[0])"
1560 [(set_attr "op_type" "RIL")
1561 (set_attr "type" "larl")
1562 (set_attr "z10prop" "z10_fwd_A1")])
1564 (define_insn "*movsi_zarch"
1565 [(set (match_operand:SI 0 "nonimmediate_operand"
1566 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1567 (match_operand:SI 1 "general_operand"
1568 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1593 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1594 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1595 (set_attr "type" "*,
1617 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1618 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1619 (set_attr "z10prop" "z10_fwd_A1,
1642 (define_insn "*movsi_esa"
1643 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1644 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1658 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1659 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1660 (set_attr "z10prop" "z10_fwd_A1,
1674 [(set (match_operand:SI 0 "register_operand" "")
1675 (mem:SI (match_operand 1 "address_operand" "")))]
1676 "!FP_REG_P (operands[0])
1677 && GET_CODE (operands[1]) == SYMBOL_REF
1678 && CONSTANT_POOL_ADDRESS_P (operands[1])
1679 && get_pool_mode (operands[1]) == SImode
1680 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1681 [(set (match_dup 0) (match_dup 2))]
1682 "operands[2] = get_pool_constant (operands[1]);")
1684 (define_insn "*la_31"
1685 [(set (match_operand:SI 0 "register_operand" "=d,d")
1686 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1687 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1691 [(set_attr "op_type" "RX,RXY")
1692 (set_attr "type" "la")
1693 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1697 [(set (match_operand:SI 0 "register_operand" "")
1698 (match_operand:QI 1 "address_operand" ""))
1699 (clobber (reg:CC CC_REGNUM))])]
1701 && preferred_la_operand_p (operands[1], const0_rtx)"
1702 [(set (match_dup 0) (match_dup 1))]
1706 [(set (match_operand:SI 0 "register_operand" "")
1707 (match_operand:SI 1 "register_operand" ""))
1710 (plus:SI (match_dup 0)
1711 (match_operand:SI 2 "nonmemory_operand" "")))
1712 (clobber (reg:CC CC_REGNUM))])]
1714 && !reg_overlap_mentioned_p (operands[0], operands[2])
1715 && preferred_la_operand_p (operands[1], operands[2])"
1716 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1719 (define_insn "*la_31_and"
1720 [(set (match_operand:SI 0 "register_operand" "=d,d")
1721 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1722 (const_int 2147483647)))]
1727 [(set_attr "op_type" "RX,RXY")
1728 (set_attr "type" "la")
1729 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1731 (define_insn_and_split "*la_31_and_cc"
1732 [(set (match_operand:SI 0 "register_operand" "=d")
1733 (and:SI (match_operand:QI 1 "address_operand" "p")
1734 (const_int 2147483647)))
1735 (clobber (reg:CC CC_REGNUM))]
1738 "&& reload_completed"
1740 (and:SI (match_dup 1) (const_int 2147483647)))]
1742 [(set_attr "op_type" "RX")
1743 (set_attr "type" "la")])
1745 (define_insn "force_la_31"
1746 [(set (match_operand:SI 0 "register_operand" "=d,d")
1747 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1748 (use (const_int 0))]
1753 [(set_attr "op_type" "RX")
1754 (set_attr "type" "la")
1755 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1758 ; movhi instruction pattern(s).
1761 (define_expand "movhi"
1762 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1763 (match_operand:HI 1 "general_operand" ""))]
1766 /* Make it explicit that loading a register from memory
1767 always sign-extends (at least) to SImode. */
1768 if (optimize && can_create_pseudo_p ()
1769 && register_operand (operands[0], VOIDmode)
1770 && GET_CODE (operands[1]) == MEM)
1772 rtx tmp = gen_reg_rtx (SImode);
1773 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1774 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1775 operands[1] = gen_lowpart (HImode, tmp);
1779 (define_insn "*movhi"
1780 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1781 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1793 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1794 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1795 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1796 (set_attr "z10prop" "z10_fr_E1,
1807 [(set (match_operand:HI 0 "register_operand" "")
1808 (mem:HI (match_operand 1 "address_operand" "")))]
1809 "GET_CODE (operands[1]) == SYMBOL_REF
1810 && CONSTANT_POOL_ADDRESS_P (operands[1])
1811 && get_pool_mode (operands[1]) == HImode
1812 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1813 [(set (match_dup 0) (match_dup 2))]
1814 "operands[2] = get_pool_constant (operands[1]);")
1817 ; movqi instruction pattern(s).
1820 (define_expand "movqi"
1821 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1822 (match_operand:QI 1 "general_operand" ""))]
1825 /* On z/Architecture, zero-extending from memory to register
1826 is just as fast as a QImode load. */
1827 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1828 && register_operand (operands[0], VOIDmode)
1829 && GET_CODE (operands[1]) == MEM)
1831 rtx tmp = gen_reg_rtx (DImode);
1832 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1833 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1834 operands[1] = gen_lowpart (QImode, tmp);
1838 (define_insn "*movqi"
1839 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1840 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1852 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1853 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1854 (set_attr "z10prop" "z10_fr_E1,
1865 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1866 (mem:QI (match_operand 1 "address_operand" "")))]
1867 "GET_CODE (operands[1]) == SYMBOL_REF
1868 && CONSTANT_POOL_ADDRESS_P (operands[1])
1869 && get_pool_mode (operands[1]) == QImode
1870 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1871 [(set (match_dup 0) (match_dup 2))]
1872 "operands[2] = get_pool_constant (operands[1]);")
1875 ; movstrictqi instruction pattern(s).
1878 (define_insn "*movstrictqi"
1879 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1880 (match_operand:QI 1 "memory_operand" "R,T"))]
1885 [(set_attr "op_type" "RX,RXY")
1886 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1889 ; movstricthi instruction pattern(s).
1892 (define_insn "*movstricthi"
1893 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1894 (match_operand:HI 1 "memory_operand" "Q,S"))
1895 (clobber (reg:CC CC_REGNUM))]
1900 [(set_attr "op_type" "RS,RSY")
1901 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1904 ; movstrictsi instruction pattern(s).
1907 (define_insn "movstrictsi"
1908 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1909 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1916 [(set_attr "op_type" "RR,RX,RXY,RRE")
1917 (set_attr "type" "lr,load,load,*")
1918 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1921 ; mov(tf|td) instruction pattern(s).
1924 (define_expand "mov<mode>"
1925 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1926 (match_operand:TD_TF 1 "general_operand" ""))]
1930 (define_insn "*mov<mode>_64"
1931 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,o, d,QS, d,o")
1932 (match_operand:TD_TF 1 "general_operand" " f,o,f,QS, d,dRT,d"))]
1942 [(set_attr "op_type" "RRE,*,*,RSY,RSY,*,*")
1943 (set_attr "type" "fsimptf,*,*,lm,stm,*,*")])
1945 (define_insn "*mov<mode>_31"
1946 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,o")
1947 (match_operand:TD_TF 1 "general_operand" " f,o,f"))]
1953 [(set_attr "op_type" "RRE,*,*")
1954 (set_attr "type" "fsimptf,*,*")])
1956 ; TFmode in GPRs splitters
1959 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1960 (match_operand:TD_TF 1 "general_operand" ""))]
1961 "TARGET_ZARCH && reload_completed
1962 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
1963 [(set (match_dup 2) (match_dup 4))
1964 (set (match_dup 3) (match_dup 5))]
1966 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
1967 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
1968 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
1969 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
1973 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1974 (match_operand:TD_TF 1 "general_operand" ""))]
1975 "TARGET_ZARCH && reload_completed
1976 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
1977 [(set (match_dup 2) (match_dup 4))
1978 (set (match_dup 3) (match_dup 5))]
1980 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
1981 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
1982 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
1983 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
1987 [(set (match_operand:TD_TF 0 "register_operand" "")
1988 (match_operand:TD_TF 1 "memory_operand" ""))]
1989 "TARGET_ZARCH && reload_completed
1990 && !FP_REG_P (operands[0])
1991 && !s_operand (operands[1], VOIDmode)"
1992 [(set (match_dup 0) (match_dup 1))]
1994 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
1995 s390_load_address (addr, XEXP (operands[1], 0));
1996 operands[1] = replace_equiv_address (operands[1], addr);
1999 ; TFmode in BFPs splitters
2002 [(set (match_operand:TD_TF 0 "register_operand" "")
2003 (match_operand:TD_TF 1 "memory_operand" ""))]
2004 "reload_completed && offsettable_memref_p (operands[1])
2005 && FP_REG_P (operands[0])"
2006 [(set (match_dup 2) (match_dup 4))
2007 (set (match_dup 3) (match_dup 5))]
2009 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2011 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2013 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2014 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2018 [(set (match_operand:TD_TF 0 "memory_operand" "")
2019 (match_operand:TD_TF 1 "register_operand" ""))]
2020 "reload_completed && offsettable_memref_p (operands[0])
2021 && FP_REG_P (operands[1])"
2022 [(set (match_dup 2) (match_dup 4))
2023 (set (match_dup 3) (match_dup 5))]
2025 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2026 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2027 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2029 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2034 ; mov(df|dd) instruction pattern(s).
2037 (define_expand "mov<mode>"
2038 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2039 (match_operand:DD_DF 1 "general_operand" ""))]
2043 (define_insn "*mov<mode>_64dfp"
2044 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2045 "=f,f,d,f,f,R,T,d,d, d,RT")
2046 (match_operand:DD_DF 1 "general_operand"
2047 " f,d,f,R,T,f,f,G,d,RT, d"))]
2061 [(set_attr "op_type" "RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2062 (set_attr "type" "floaddf,floaddf,floaddf,floaddf,floaddf,
2063 fstoredf,fstoredf,*,lr,load,store")
2064 (set_attr "z10prop" "*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2067 (define_insn "*mov<mode>_64"
2068 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d, d,RT")
2069 (match_operand:DD_DF 1 "general_operand" "f,R,T,f,f,G,d,RT, d"))]
2081 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2082 (set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
2083 fstore<mode>,fstore<mode>,*,lr,load,store")
2084 (set_attr "z10prop" "*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")])
2086 (define_insn "*mov<mode>_31"
2087 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2088 "=f,f,f,R,T,d,d,Q,S, d,o")
2089 (match_operand:DD_DF 1 "general_operand"
2090 " f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2104 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2105 (set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
2106 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
2109 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2110 (match_operand:DD_DF 1 "general_operand" ""))]
2111 "!TARGET_ZARCH && reload_completed
2112 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2113 [(set (match_dup 2) (match_dup 4))
2114 (set (match_dup 3) (match_dup 5))]
2116 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2117 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2118 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2119 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2123 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2124 (match_operand:DD_DF 1 "general_operand" ""))]
2125 "!TARGET_ZARCH && reload_completed
2126 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2127 [(set (match_dup 2) (match_dup 4))
2128 (set (match_dup 3) (match_dup 5))]
2130 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2131 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2132 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2133 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2137 [(set (match_operand:DD_DF 0 "register_operand" "")
2138 (match_operand:DD_DF 1 "memory_operand" ""))]
2139 "!TARGET_ZARCH && reload_completed
2140 && !FP_REG_P (operands[0])
2141 && !s_operand (operands[1], VOIDmode)"
2142 [(set (match_dup 0) (match_dup 1))]
2144 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2145 s390_load_address (addr, XEXP (operands[1], 0));
2146 operands[1] = replace_equiv_address (operands[1], addr);
2150 ; mov(sf|sd) instruction pattern(s).
2153 (define_insn "mov<mode>"
2154 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2155 "=f,f,f,R,T,d,d,d,d,R,T")
2156 (match_operand:SD_SF 1 "general_operand"
2157 " f,R,T,f,f,G,d,R,T,d,d"))]
2171 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2172 (set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
2173 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2174 (set_attr "z10prop" "*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")])
2177 ; movcc instruction pattern
2180 (define_insn "movcc"
2181 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2182 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2192 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2193 (set_attr "type" "lr,*,*,store,store,load,load")
2194 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")])
2197 ; Block move (MVC) patterns.
2201 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2202 (match_operand:BLK 1 "memory_operand" "Q"))
2203 (use (match_operand 2 "const_int_operand" "n"))]
2204 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2205 "mvc\t%O0(%2,%R0),%S1"
2206 [(set_attr "op_type" "SS")])
2208 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2209 ; order to have it implemented with mvc.
2212 [(set (match_operand:QI 0 "memory_operand" "")
2213 (match_operand:QI 1 "memory_operand" ""))]
2216 [(set (match_dup 0) (match_dup 1))
2217 (use (const_int 1))])]
2219 operands[0] = adjust_address (operands[0], BLKmode, 0);
2220 operands[1] = adjust_address (operands[1], BLKmode, 0);
2226 [(set (match_operand:BLK 0 "memory_operand" "")
2227 (match_operand:BLK 1 "memory_operand" ""))
2228 (use (match_operand 2 "const_int_operand" ""))])
2230 [(set (match_operand:BLK 3 "memory_operand" "")
2231 (match_operand:BLK 4 "memory_operand" ""))
2232 (use (match_operand 5 "const_int_operand" ""))])]
2233 "s390_offset_p (operands[0], operands[3], operands[2])
2234 && s390_offset_p (operands[1], operands[4], operands[2])
2235 && !s390_overlap_p (operands[0], operands[1],
2236 INTVAL (operands[2]) + INTVAL (operands[5]))
2237 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2239 [(set (match_dup 6) (match_dup 7))
2240 (use (match_dup 8))])]
2241 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2242 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2243 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2247 ; load_multiple pattern(s).
2249 ; ??? Due to reload problems with replacing registers inside match_parallel
2250 ; we currently support load_multiple/store_multiple only after reload.
2253 (define_expand "load_multiple"
2254 [(match_par_dup 3 [(set (match_operand 0 "" "")
2255 (match_operand 1 "" ""))
2256 (use (match_operand 2 "" ""))])]
2259 enum machine_mode mode;
2265 /* Support only loading a constant number of fixed-point registers from
2266 memory and only bother with this if more than two */
2267 if (GET_CODE (operands[2]) != CONST_INT
2268 || INTVAL (operands[2]) < 2
2269 || INTVAL (operands[2]) > 16
2270 || GET_CODE (operands[1]) != MEM
2271 || GET_CODE (operands[0]) != REG
2272 || REGNO (operands[0]) >= 16)
2275 count = INTVAL (operands[2]);
2276 regno = REGNO (operands[0]);
2277 mode = GET_MODE (operands[0]);
2278 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2281 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2282 if (!can_create_pseudo_p ())
2284 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2286 from = XEXP (operands[1], 0);
2289 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2290 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2291 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2293 from = XEXP (XEXP (operands[1], 0), 0);
2294 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2301 from = force_reg (Pmode, XEXP (operands[1], 0));
2305 for (i = 0; i < count; i++)
2306 XVECEXP (operands[3], 0, i)
2307 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2308 change_address (operands[1], mode,
2309 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
2312 (define_insn "*load_multiple_di"
2313 [(match_parallel 0 "load_multiple_operation"
2314 [(set (match_operand:DI 1 "register_operand" "=r")
2315 (match_operand:DI 2 "s_operand" "QS"))])]
2316 "reload_completed && TARGET_ZARCH"
2318 int words = XVECLEN (operands[0], 0);
2319 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2320 return "lmg\t%1,%0,%S2";
2322 [(set_attr "op_type" "RSY")
2323 (set_attr "type" "lm")])
2325 (define_insn "*load_multiple_si"
2326 [(match_parallel 0 "load_multiple_operation"
2327 [(set (match_operand:SI 1 "register_operand" "=r,r")
2328 (match_operand:SI 2 "s_operand" "Q,S"))])]
2331 int words = XVECLEN (operands[0], 0);
2332 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2333 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2335 [(set_attr "op_type" "RS,RSY")
2336 (set_attr "type" "lm")])
2339 ; store multiple pattern(s).
2342 (define_expand "store_multiple"
2343 [(match_par_dup 3 [(set (match_operand 0 "" "")
2344 (match_operand 1 "" ""))
2345 (use (match_operand 2 "" ""))])]
2348 enum machine_mode mode;
2354 /* Support only storing a constant number of fixed-point registers to
2355 memory and only bother with this if more than two. */
2356 if (GET_CODE (operands[2]) != CONST_INT
2357 || INTVAL (operands[2]) < 2
2358 || INTVAL (operands[2]) > 16
2359 || GET_CODE (operands[0]) != MEM
2360 || GET_CODE (operands[1]) != REG
2361 || REGNO (operands[1]) >= 16)
2364 count = INTVAL (operands[2]);
2365 regno = REGNO (operands[1]);
2366 mode = GET_MODE (operands[1]);
2367 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2370 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2372 if (!can_create_pseudo_p ())
2374 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2376 to = XEXP (operands[0], 0);
2379 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2380 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2381 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2383 to = XEXP (XEXP (operands[0], 0), 0);
2384 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2391 to = force_reg (Pmode, XEXP (operands[0], 0));
2395 for (i = 0; i < count; i++)
2396 XVECEXP (operands[3], 0, i)
2397 = gen_rtx_SET (VOIDmode,
2398 change_address (operands[0], mode,
2399 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
2400 gen_rtx_REG (mode, regno + i));
2403 (define_insn "*store_multiple_di"
2404 [(match_parallel 0 "store_multiple_operation"
2405 [(set (match_operand:DI 1 "s_operand" "=QS")
2406 (match_operand:DI 2 "register_operand" "r"))])]
2407 "reload_completed && TARGET_ZARCH"
2409 int words = XVECLEN (operands[0], 0);
2410 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2411 return "stmg\t%2,%0,%S1";
2413 [(set_attr "op_type" "RSY")
2414 (set_attr "type" "stm")])
2417 (define_insn "*store_multiple_si"
2418 [(match_parallel 0 "store_multiple_operation"
2419 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2420 (match_operand:SI 2 "register_operand" "r,r"))])]
2423 int words = XVECLEN (operands[0], 0);
2424 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2425 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2427 [(set_attr "op_type" "RS,RSY")
2428 (set_attr "type" "stm")])
2431 ;; String instructions.
2434 (define_insn "*execute_rl"
2435 [(match_parallel 0 ""
2436 [(unspec [(match_operand 1 "register_operand" "a")
2437 (match_operand 2 "" "")
2438 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2439 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2440 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2442 [(set_attr "op_type" "RIL")
2443 (set_attr "type" "cs")])
2445 (define_insn "*execute"
2446 [(match_parallel 0 ""
2447 [(unspec [(match_operand 1 "register_operand" "a")
2448 (match_operand:BLK 2 "memory_operand" "R")
2449 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2450 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2451 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2453 [(set_attr "op_type" "RX")
2454 (set_attr "type" "cs")])
2458 ; strlenM instruction pattern(s).
2461 (define_expand "strlen<mode>"
2462 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2465 (unspec:P [(const_int 0)
2466 (match_operand:BLK 1 "memory_operand" "")
2468 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2469 (clobber (scratch:P))
2470 (clobber (reg:CC CC_REGNUM))])
2472 [(set (match_operand:P 0 "register_operand" "")
2473 (minus:P (match_dup 4) (match_dup 5)))
2474 (clobber (reg:CC CC_REGNUM))])]
2477 operands[4] = gen_reg_rtx (Pmode);
2478 operands[5] = gen_reg_rtx (Pmode);
2479 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2480 operands[1] = replace_equiv_address (operands[1], operands[5]);
2483 (define_insn "*strlen<mode>"
2484 [(set (match_operand:P 0 "register_operand" "=a")
2485 (unspec:P [(match_operand:P 2 "general_operand" "0")
2486 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2488 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2489 (clobber (match_scratch:P 1 "=a"))
2490 (clobber (reg:CC CC_REGNUM))]
2492 "srst\t%0,%1\;jo\t.-4"
2493 [(set_attr "length" "8")
2494 (set_attr "type" "vs")])
2497 ; cmpstrM instruction pattern(s).
2500 (define_expand "cmpstrsi"
2501 [(set (reg:SI 0) (const_int 0))
2503 [(clobber (match_operand 3 "" ""))
2504 (clobber (match_dup 4))
2505 (set (reg:CCU CC_REGNUM)
2506 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2507 (match_operand:BLK 2 "memory_operand" "")))
2510 [(set (match_operand:SI 0 "register_operand" "=d")
2511 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2512 (clobber (reg:CC CC_REGNUM))])]
2515 /* As the result of CMPINT is inverted compared to what we need,
2516 we have to swap the operands. */
2517 rtx op1 = operands[2];
2518 rtx op2 = operands[1];
2519 rtx addr1 = gen_reg_rtx (Pmode);
2520 rtx addr2 = gen_reg_rtx (Pmode);
2522 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2523 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2524 operands[1] = replace_equiv_address_nv (op1, addr1);
2525 operands[2] = replace_equiv_address_nv (op2, addr2);
2526 operands[3] = addr1;
2527 operands[4] = addr2;
2530 (define_insn "*cmpstr<mode>"
2531 [(clobber (match_operand:P 0 "register_operand" "=d"))
2532 (clobber (match_operand:P 1 "register_operand" "=d"))
2533 (set (reg:CCU CC_REGNUM)
2534 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2535 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2538 "clst\t%0,%1\;jo\t.-4"
2539 [(set_attr "length" "8")
2540 (set_attr "type" "vs")])
2543 ; movstr instruction pattern.
2546 (define_expand "movstr"
2547 [(set (reg:SI 0) (const_int 0))
2549 [(clobber (match_dup 3))
2550 (set (match_operand:BLK 1 "memory_operand" "")
2551 (match_operand:BLK 2 "memory_operand" ""))
2552 (set (match_operand 0 "register_operand" "")
2553 (unspec [(match_dup 1)
2555 (reg:SI 0)] UNSPEC_MVST))
2556 (clobber (reg:CC CC_REGNUM))])]
2559 rtx addr1 = gen_reg_rtx (Pmode);
2560 rtx addr2 = gen_reg_rtx (Pmode);
2562 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2563 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2564 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2565 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2566 operands[3] = addr2;
2569 (define_insn "*movstr"
2570 [(clobber (match_operand:P 2 "register_operand" "=d"))
2571 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2572 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2573 (set (match_operand:P 0 "register_operand" "=d")
2574 (unspec [(mem:BLK (match_dup 1))
2575 (mem:BLK (match_dup 3))
2576 (reg:SI 0)] UNSPEC_MVST))
2577 (clobber (reg:CC CC_REGNUM))]
2579 "mvst\t%1,%2\;jo\t.-4"
2580 [(set_attr "length" "8")
2581 (set_attr "type" "vs")])
2585 ; movmemM instruction pattern(s).
2588 (define_expand "movmem<mode>"
2589 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2590 (match_operand:BLK 1 "memory_operand" "")) ; source
2591 (use (match_operand:GPR 2 "general_operand" "")) ; count
2592 (match_operand 3 "" "")]
2594 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2596 ; Move a block that is up to 256 bytes in length.
2597 ; The block length is taken as (operands[2] % 256) + 1.
2599 (define_expand "movmem_short"
2601 [(set (match_operand:BLK 0 "memory_operand" "")
2602 (match_operand:BLK 1 "memory_operand" ""))
2603 (use (match_operand 2 "nonmemory_operand" ""))
2604 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2605 (clobber (match_dup 3))])]
2607 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2609 (define_insn "*movmem_short"
2610 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2611 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2612 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2613 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2614 (clobber (match_scratch 4 "=X,X,X,&a"))]
2615 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2616 && GET_MODE (operands[4]) == Pmode"
2618 [(set_attr "type" "cs")
2619 (set_attr "cpu_facility" "*,*,z10,*")])
2622 [(set (match_operand:BLK 0 "memory_operand" "")
2623 (match_operand:BLK 1 "memory_operand" ""))
2624 (use (match_operand 2 "const_int_operand" ""))
2625 (use (match_operand 3 "immediate_operand" ""))
2626 (clobber (scratch))]
2629 [(set (match_dup 0) (match_dup 1))
2630 (use (match_dup 2))])]
2631 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2634 [(set (match_operand:BLK 0 "memory_operand" "")
2635 (match_operand:BLK 1 "memory_operand" ""))
2636 (use (match_operand 2 "register_operand" ""))
2637 (use (match_operand 3 "memory_operand" ""))
2638 (clobber (scratch))]
2641 [(unspec [(match_dup 2) (match_dup 3)
2642 (const_int 0)] UNSPEC_EXECUTE)
2643 (set (match_dup 0) (match_dup 1))
2644 (use (const_int 1))])]
2648 [(set (match_operand:BLK 0 "memory_operand" "")
2649 (match_operand:BLK 1 "memory_operand" ""))
2650 (use (match_operand 2 "register_operand" ""))
2651 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2652 (clobber (scratch))]
2653 "TARGET_Z10 && reload_completed"
2655 [(unspec [(match_dup 2) (const_int 0)
2656 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2657 (set (match_dup 0) (match_dup 1))
2658 (use (const_int 1))])]
2659 "operands[3] = gen_label_rtx ();")
2662 [(set (match_operand:BLK 0 "memory_operand" "")
2663 (match_operand:BLK 1 "memory_operand" ""))
2664 (use (match_operand 2 "register_operand" ""))
2665 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2666 (clobber (match_operand 3 "register_operand" ""))]
2667 "reload_completed && TARGET_CPU_ZARCH"
2668 [(set (match_dup 3) (label_ref (match_dup 4)))
2670 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2671 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2672 (set (match_dup 0) (match_dup 1))
2673 (use (const_int 1))])]
2674 "operands[4] = gen_label_rtx ();")
2676 ; Move a block of arbitrary length.
2678 (define_expand "movmem_long"
2680 [(clobber (match_dup 2))
2681 (clobber (match_dup 3))
2682 (set (match_operand:BLK 0 "memory_operand" "")
2683 (match_operand:BLK 1 "memory_operand" ""))
2684 (use (match_operand 2 "general_operand" ""))
2686 (clobber (reg:CC CC_REGNUM))])]
2689 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2690 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2691 rtx reg0 = gen_reg_rtx (dreg_mode);
2692 rtx reg1 = gen_reg_rtx (dreg_mode);
2693 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2694 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2695 rtx len0 = gen_lowpart (Pmode, reg0);
2696 rtx len1 = gen_lowpart (Pmode, reg1);
2698 emit_clobber (reg0);
2699 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2700 emit_move_insn (len0, operands[2]);
2702 emit_clobber (reg1);
2703 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2704 emit_move_insn (len1, operands[2]);
2706 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2707 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2712 (define_insn "*movmem_long"
2713 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2714 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2715 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2716 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2719 (clobber (reg:CC CC_REGNUM))]
2720 "TARGET_64BIT || !TARGET_ZARCH"
2721 "mvcle\t%0,%1,0\;jo\t.-4"
2722 [(set_attr "length" "8")
2723 (set_attr "type" "vs")])
2725 (define_insn "*movmem_long_31z"
2726 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2727 (clobber (match_operand:TI 1 "register_operand" "=d"))
2728 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2729 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2732 (clobber (reg:CC CC_REGNUM))]
2733 "!TARGET_64BIT && TARGET_ZARCH"
2734 "mvcle\t%0,%1,0\;jo\t.-4"
2735 [(set_attr "length" "8")
2736 (set_attr "type" "vs")])
2743 (define_expand "signbit<mode>2"
2744 [(set (reg:CCZ CC_REGNUM)
2745 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2748 (set (match_operand:SI 0 "register_operand" "=d")
2749 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2752 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2755 (define_expand "isinf<mode>2"
2756 [(set (reg:CCZ CC_REGNUM)
2757 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2760 (set (match_operand:SI 0 "register_operand" "=d")
2761 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2764 operands[2] = GEN_INT (S390_TDC_INFINITY);
2767 ; This insn is used to generate all variants of the Test Data Class
2768 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2769 ; is the register to be tested and the second one is the bit mask
2770 ; specifying the required test(s).
2772 (define_insn "*TDC_insn_<mode>"
2773 [(set (reg:CCZ CC_REGNUM)
2774 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2775 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2777 "t<_d>c<xde><bt>\t%0,%1"
2778 [(set_attr "op_type" "RXE")
2779 (set_attr "type" "fsimp<mode>")])
2781 (define_insn_and_split "*ccz_to_int"
2782 [(set (match_operand:SI 0 "register_operand" "=d")
2783 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2784 UNSPEC_CCZ_TO_INT))]
2788 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2792 ; setmemM instruction pattern(s).
2795 (define_expand "setmem<mode>"
2796 [(set (match_operand:BLK 0 "memory_operand" "")
2797 (match_operand:QI 2 "general_operand" ""))
2798 (use (match_operand:GPR 1 "general_operand" ""))
2799 (match_operand 3 "" "")]
2801 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2803 ; Clear a block that is up to 256 bytes in length.
2804 ; The block length is taken as (operands[1] % 256) + 1.
2806 (define_expand "clrmem_short"
2808 [(set (match_operand:BLK 0 "memory_operand" "")
2810 (use (match_operand 1 "nonmemory_operand" ""))
2811 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2812 (clobber (match_dup 2))
2813 (clobber (reg:CC CC_REGNUM))])]
2815 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2817 (define_insn "*clrmem_short"
2818 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2820 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2821 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2822 (clobber (match_scratch 3 "=X,X,X,&a"))
2823 (clobber (reg:CC CC_REGNUM))]
2824 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2825 && GET_MODE (operands[3]) == Pmode"
2827 [(set_attr "type" "cs")
2828 (set_attr "cpu_facility" "*,*,z10,*")])
2831 [(set (match_operand:BLK 0 "memory_operand" "")
2833 (use (match_operand 1 "const_int_operand" ""))
2834 (use (match_operand 2 "immediate_operand" ""))
2836 (clobber (reg:CC CC_REGNUM))]
2839 [(set (match_dup 0) (const_int 0))
2841 (clobber (reg:CC CC_REGNUM))])]
2842 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2845 [(set (match_operand:BLK 0 "memory_operand" "")
2847 (use (match_operand 1 "register_operand" ""))
2848 (use (match_operand 2 "memory_operand" ""))
2850 (clobber (reg:CC CC_REGNUM))]
2853 [(unspec [(match_dup 1) (match_dup 2)
2854 (const_int 0)] UNSPEC_EXECUTE)
2855 (set (match_dup 0) (const_int 0))
2857 (clobber (reg:CC CC_REGNUM))])]
2861 [(set (match_operand:BLK 0 "memory_operand" "")
2863 (use (match_operand 1 "register_operand" ""))
2864 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2866 (clobber (reg:CC CC_REGNUM))]
2867 "TARGET_Z10 && reload_completed"
2869 [(unspec [(match_dup 1) (const_int 0)
2870 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2871 (set (match_dup 0) (const_int 0))
2873 (clobber (reg:CC CC_REGNUM))])]
2874 "operands[3] = gen_label_rtx ();")
2877 [(set (match_operand:BLK 0 "memory_operand" "")
2879 (use (match_operand 1 "register_operand" ""))
2880 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2881 (clobber (match_operand 2 "register_operand" ""))
2882 (clobber (reg:CC CC_REGNUM))]
2883 "reload_completed && TARGET_CPU_ZARCH"
2884 [(set (match_dup 2) (label_ref (match_dup 3)))
2886 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2887 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2888 (set (match_dup 0) (const_int 0))
2890 (clobber (reg:CC CC_REGNUM))])]
2891 "operands[3] = gen_label_rtx ();")
2893 ; Initialize a block of arbitrary length with (operands[2] % 256).
2895 (define_expand "setmem_long"
2897 [(clobber (match_dup 1))
2898 (set (match_operand:BLK 0 "memory_operand" "")
2899 (match_operand 2 "shift_count_or_setmem_operand" ""))
2900 (use (match_operand 1 "general_operand" ""))
2902 (clobber (reg:CC CC_REGNUM))])]
2905 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2906 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2907 rtx reg0 = gen_reg_rtx (dreg_mode);
2908 rtx reg1 = gen_reg_rtx (dreg_mode);
2909 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2910 rtx len0 = gen_lowpart (Pmode, reg0);
2912 emit_clobber (reg0);
2913 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2914 emit_move_insn (len0, operands[1]);
2916 emit_move_insn (reg1, const0_rtx);
2918 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2923 (define_insn "*setmem_long"
2924 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2925 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2926 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2928 (use (match_operand:<DBL> 1 "register_operand" "d"))
2929 (clobber (reg:CC CC_REGNUM))]
2930 "TARGET_64BIT || !TARGET_ZARCH"
2931 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2932 [(set_attr "length" "8")
2933 (set_attr "type" "vs")])
2935 (define_insn "*setmem_long_and"
2936 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2937 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2938 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2939 (match_operand 4 "const_int_operand" "n")))
2941 (use (match_operand:<DBL> 1 "register_operand" "d"))
2942 (clobber (reg:CC CC_REGNUM))]
2943 "(TARGET_64BIT || !TARGET_ZARCH) &&
2944 (INTVAL (operands[4]) & 255) == 255"
2945 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2946 [(set_attr "length" "8")
2947 (set_attr "type" "vs")])
2949 (define_insn "*setmem_long_31z"
2950 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2951 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
2952 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2954 (use (match_operand:TI 1 "register_operand" "d"))
2955 (clobber (reg:CC CC_REGNUM))]
2956 "!TARGET_64BIT && TARGET_ZARCH"
2957 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2958 [(set_attr "length" "8")
2959 (set_attr "type" "vs")])
2962 ; cmpmemM instruction pattern(s).
2965 (define_expand "cmpmemsi"
2966 [(set (match_operand:SI 0 "register_operand" "")
2967 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2968 (match_operand:BLK 2 "memory_operand" "") ) )
2969 (use (match_operand:SI 3 "general_operand" ""))
2970 (use (match_operand:SI 4 "" ""))]
2972 "s390_expand_cmpmem (operands[0], operands[1],
2973 operands[2], operands[3]); DONE;")
2975 ; Compare a block that is up to 256 bytes in length.
2976 ; The block length is taken as (operands[2] % 256) + 1.
2978 (define_expand "cmpmem_short"
2980 [(set (reg:CCU CC_REGNUM)
2981 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2982 (match_operand:BLK 1 "memory_operand" "")))
2983 (use (match_operand 2 "nonmemory_operand" ""))
2984 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2985 (clobber (match_dup 3))])]
2987 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2989 (define_insn "*cmpmem_short"
2990 [(set (reg:CCU CC_REGNUM)
2991 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
2992 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
2993 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2994 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2995 (clobber (match_scratch 4 "=X,X,X,&a"))]
2996 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2997 && GET_MODE (operands[4]) == Pmode"
2999 [(set_attr "type" "cs")
3000 (set_attr "cpu_facility" "*,*,z10,*")])
3003 [(set (reg:CCU CC_REGNUM)
3004 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3005 (match_operand:BLK 1 "memory_operand" "")))
3006 (use (match_operand 2 "const_int_operand" ""))
3007 (use (match_operand 3 "immediate_operand" ""))
3008 (clobber (scratch))]
3011 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3012 (use (match_dup 2))])]
3013 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3016 [(set (reg:CCU CC_REGNUM)
3017 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3018 (match_operand:BLK 1 "memory_operand" "")))
3019 (use (match_operand 2 "register_operand" ""))
3020 (use (match_operand 3 "memory_operand" ""))
3021 (clobber (scratch))]
3024 [(unspec [(match_dup 2) (match_dup 3)
3025 (const_int 0)] UNSPEC_EXECUTE)
3026 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3027 (use (const_int 1))])]
3031 [(set (reg:CCU CC_REGNUM)
3032 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3033 (match_operand:BLK 1 "memory_operand" "")))
3034 (use (match_operand 2 "register_operand" ""))
3035 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3036 (clobber (scratch))]
3037 "TARGET_Z10 && reload_completed"
3039 [(unspec [(match_dup 2) (const_int 0)
3040 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3041 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3042 (use (const_int 1))])]
3043 "operands[4] = gen_label_rtx ();")
3046 [(set (reg:CCU CC_REGNUM)
3047 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3048 (match_operand:BLK 1 "memory_operand" "")))
3049 (use (match_operand 2 "register_operand" ""))
3050 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3051 (clobber (match_operand 3 "register_operand" ""))]
3052 "reload_completed && TARGET_CPU_ZARCH"
3053 [(set (match_dup 3) (label_ref (match_dup 4)))
3055 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3056 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3057 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3058 (use (const_int 1))])]
3059 "operands[4] = gen_label_rtx ();")
3061 ; Compare a block of arbitrary length.
3063 (define_expand "cmpmem_long"
3065 [(clobber (match_dup 2))
3066 (clobber (match_dup 3))
3067 (set (reg:CCU CC_REGNUM)
3068 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3069 (match_operand:BLK 1 "memory_operand" "")))
3070 (use (match_operand 2 "general_operand" ""))
3071 (use (match_dup 3))])]
3074 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3075 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3076 rtx reg0 = gen_reg_rtx (dreg_mode);
3077 rtx reg1 = gen_reg_rtx (dreg_mode);
3078 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3079 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3080 rtx len0 = gen_lowpart (Pmode, reg0);
3081 rtx len1 = gen_lowpart (Pmode, reg1);
3083 emit_clobber (reg0);
3084 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3085 emit_move_insn (len0, operands[2]);
3087 emit_clobber (reg1);
3088 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3089 emit_move_insn (len1, operands[2]);
3091 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3092 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3097 (define_insn "*cmpmem_long"
3098 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3099 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3100 (set (reg:CCU CC_REGNUM)
3101 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3102 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3104 (use (match_dup 3))]
3105 "TARGET_64BIT || !TARGET_ZARCH"
3106 "clcle\t%0,%1,0\;jo\t.-4"
3107 [(set_attr "length" "8")
3108 (set_attr "type" "vs")])
3110 (define_insn "*cmpmem_long_31z"
3111 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3112 (clobber (match_operand:TI 1 "register_operand" "=d"))
3113 (set (reg:CCU CC_REGNUM)
3114 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3115 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3117 (use (match_dup 3))]
3118 "!TARGET_64BIT && TARGET_ZARCH"
3119 "clcle\t%0,%1,0\;jo\t.-4"
3120 [(set_attr "op_type" "NN")
3121 (set_attr "type" "vs")
3122 (set_attr "length" "8")])
3124 ; Convert CCUmode condition code to integer.
3125 ; Result is zero if EQ, positive if LTU, negative if GTU.
3127 (define_insn_and_split "cmpint"
3128 [(set (match_operand:SI 0 "register_operand" "=d")
3129 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3131 (clobber (reg:CC CC_REGNUM))]
3135 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3137 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3138 (clobber (reg:CC CC_REGNUM))])])
3140 (define_insn_and_split "*cmpint_cc"
3141 [(set (reg CC_REGNUM)
3142 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3145 (set (match_operand:SI 0 "register_operand" "=d")
3146 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3147 "s390_match_ccmode (insn, CCSmode)"
3149 "&& reload_completed"
3150 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3152 [(set (match_dup 2) (match_dup 3))
3153 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3155 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3156 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3157 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3160 (define_insn_and_split "*cmpint_sign"
3161 [(set (match_operand:DI 0 "register_operand" "=d")
3162 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3163 UNSPEC_CCU_TO_INT)))
3164 (clobber (reg:CC CC_REGNUM))]
3167 "&& reload_completed"
3168 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3170 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3171 (clobber (reg:CC CC_REGNUM))])])
3173 (define_insn_and_split "*cmpint_sign_cc"
3174 [(set (reg CC_REGNUM)
3175 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3176 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3177 UNSPEC_CCU_TO_INT) 0)
3178 (const_int 32)) (const_int 32))
3180 (set (match_operand:DI 0 "register_operand" "=d")
3181 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3182 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3184 "&& reload_completed"
3185 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3187 [(set (match_dup 2) (match_dup 3))
3188 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3190 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3191 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3192 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3197 ;;- Conversion instructions.
3200 (define_insn "*sethighpartsi"
3201 [(set (match_operand:SI 0 "register_operand" "=d,d")
3202 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3203 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3204 (clobber (reg:CC CC_REGNUM))]
3209 [(set_attr "op_type" "RS,RSY")
3210 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3212 (define_insn "*sethighpartdi_64"
3213 [(set (match_operand:DI 0 "register_operand" "=d")
3214 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3215 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3216 (clobber (reg:CC CC_REGNUM))]
3219 [(set_attr "op_type" "RSY")
3220 (set_attr "z10prop" "z10_super")])
3222 (define_insn "*sethighpartdi_31"
3223 [(set (match_operand:DI 0 "register_operand" "=d,d")
3224 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3225 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3226 (clobber (reg:CC CC_REGNUM))]
3231 [(set_attr "op_type" "RS,RSY")
3232 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3235 (define_insn_and_split "*extzv<mode>"
3236 [(set (match_operand:GPR 0 "register_operand" "=d")
3237 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3238 (match_operand 2 "const_int_operand" "n")
3240 (clobber (reg:CC CC_REGNUM))]
3241 "INTVAL (operands[2]) > 0
3242 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3244 "&& reload_completed"
3246 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3247 (clobber (reg:CC CC_REGNUM))])
3248 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3250 int bitsize = INTVAL (operands[2]);
3251 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3252 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3254 operands[1] = adjust_address (operands[1], BLKmode, 0);
3255 set_mem_size (operands[1], GEN_INT (size));
3256 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3257 operands[3] = GEN_INT (mask);
3260 (define_insn_and_split "*extv<mode>"
3261 [(set (match_operand:GPR 0 "register_operand" "=d")
3262 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3263 (match_operand 2 "const_int_operand" "n")
3265 (clobber (reg:CC CC_REGNUM))]
3266 "INTVAL (operands[2]) > 0
3267 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3269 "&& reload_completed"
3271 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3272 (clobber (reg:CC CC_REGNUM))])
3274 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3275 (clobber (reg:CC CC_REGNUM))])]
3277 int bitsize = INTVAL (operands[2]);
3278 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3279 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3281 operands[1] = adjust_address (operands[1], BLKmode, 0);
3282 set_mem_size (operands[1], GEN_INT (size));
3283 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3284 operands[3] = GEN_INT (mask);
3288 ; insv instruction patterns
3291 (define_expand "insv"
3292 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3293 (match_operand 1 "const_int_operand" "")
3294 (match_operand 2 "const_int_operand" ""))
3295 (match_operand 3 "general_operand" ""))]
3298 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3303 (define_insn "*insv<mode>_z10"
3304 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3305 (match_operand 1 "const_int_operand" "I")
3306 (match_operand 2 "const_int_operand" "I"))
3307 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3308 (clobber (reg:CC CC_REGNUM))]
3310 && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
3311 GET_MODE_BITSIZE (<MODE>mode)"
3313 int start = INTVAL (operands[2]);
3314 int size = INTVAL (operands[1]);
3315 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
3317 operands[2] = GEN_INT (offset + start); /* start bit position */
3318 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
3319 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
3320 start - size); /* left shift count */
3322 return "risbg\t%0,%3,%b2,%b1,%b4";
3324 [(set_attr "op_type" "RIE")
3325 (set_attr "z10prop" "z10_super_E1")])
3327 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3328 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3329 (define_insn "*insv<mode>_z10_noshift"
3330 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3331 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3332 (match_operand 2 "const_int_operand" "n"))
3333 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3334 (match_operand 4 "const_int_operand" "n"))))
3335 (clobber (reg:CC CC_REGNUM))]
3337 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3338 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
3339 && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
3345 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3346 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3348 operands[5] = GEN_INT (64 - start - size); /* start bit position */
3349 operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
3350 operands[7] = const0_rtx; /* left shift count */
3352 return "risbg\t%0,%1,%b5,%b6,%b7";
3354 [(set_attr "op_type" "RIE")
3355 (set_attr "z10prop" "z10_super_E1")])
3357 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3358 (define_insn "*insv<mode>_or_z10_noshift"
3359 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3360 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3361 (match_operand 2 "const_int_operand" "n"))
3362 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3363 (clobber (reg:CC CC_REGNUM))]
3365 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3366 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
3371 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3372 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3374 operands[4] = GEN_INT (64 - start - size); /* start bit position */
3375 operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
3376 operands[6] = const0_rtx; /* left shift count */
3378 return "rosbg\t%0,%1,%b4,%b5,%b6";
3380 [(set_attr "op_type" "RIE")])
3382 (define_insn "*insv<mode>_mem_reg"
3383 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3384 (match_operand 1 "const_int_operand" "n,n")
3386 (match_operand:W 2 "register_operand" "d,d"))]
3387 "INTVAL (operands[1]) > 0
3388 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3389 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3391 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3393 operands[1] = GEN_INT ((1ul << size) - 1);
3394 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3395 : "stcmy\t%2,%1,%S0";
3397 [(set_attr "op_type" "RS,RSY")
3398 (set_attr "z10prop" "z10_super,z10_super")])
3400 (define_insn "*insvdi_mem_reghigh"
3401 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3402 (match_operand 1 "const_int_operand" "n")
3404 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3407 && INTVAL (operands[1]) > 0
3408 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3409 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3411 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3413 operands[1] = GEN_INT ((1ul << size) - 1);
3414 return "stcmh\t%2,%1,%S0";
3416 [(set_attr "op_type" "RSY")
3417 (set_attr "z10prop" "z10_super")])
3419 (define_insn "*insvdi_reg_imm"
3420 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3422 (match_operand 1 "const_int_operand" "n"))
3423 (match_operand:DI 2 "const_int_operand" "n"))]
3425 && INTVAL (operands[1]) >= 0
3426 && INTVAL (operands[1]) < BITS_PER_WORD
3427 && INTVAL (operands[1]) % 16 == 0"
3429 switch (BITS_PER_WORD - INTVAL (operands[1]))
3431 case 64: return "iihh\t%0,%x2"; break;
3432 case 48: return "iihl\t%0,%x2"; break;
3433 case 32: return "iilh\t%0,%x2"; break;
3434 case 16: return "iill\t%0,%x2"; break;
3435 default: gcc_unreachable();
3438 [(set_attr "op_type" "RI")
3439 (set_attr "z10prop" "z10_super_E1")])
3441 ; Update the left-most 32 bit of a DI.
3442 (define_insn "*insv_h_di_reg_extimm"
3443 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3446 (match_operand:DI 1 "const_int_operand" "n"))]
3449 [(set_attr "op_type" "RIL")
3450 (set_attr "z10prop" "z10_fwd_E1")])
3452 ; Update the right-most 32 bit of a DI, or the whole of a SI.
3453 (define_insn "*insv_l<mode>_reg_extimm"
3454 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3456 (match_operand 1 "const_int_operand" "n"))
3457 (match_operand:P 2 "const_int_operand" "n"))]
3459 && BITS_PER_WORD - INTVAL (operands[1]) == 32"
3461 [(set_attr "op_type" "RIL")
3462 (set_attr "z10prop" "z10_fwd_A1")])
3465 ; extendsidi2 instruction pattern(s).
3468 (define_expand "extendsidi2"
3469 [(set (match_operand:DI 0 "register_operand" "")
3470 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3475 emit_clobber (operands[0]);
3476 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3477 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3478 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3483 (define_insn "*extendsidi2"
3484 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3485 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3491 [(set_attr "op_type" "RRE,RXY,RIL")
3492 (set_attr "type" "*,*,larl")
3493 (set_attr "cpu_facility" "*,*,z10")
3494 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3497 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3500 (define_expand "extend<HQI:mode><DSI:mode>2"
3501 [(set (match_operand:DSI 0 "register_operand" "")
3502 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3505 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3507 rtx tmp = gen_reg_rtx (SImode);
3508 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3509 emit_insn (gen_extendsidi2 (operands[0], tmp));
3512 else if (!TARGET_EXTIMM)
3514 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
3515 GET_MODE_BITSIZE (<HQI:MODE>mode));
3517 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3518 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3519 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3525 ; extendhidi2 instruction pattern(s).
3528 (define_insn "*extendhidi2_extimm"
3529 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3530 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3531 "TARGET_ZARCH && TARGET_EXTIMM"
3536 [(set_attr "op_type" "RRE,RXY,RIL")
3537 (set_attr "type" "*,*,larl")
3538 (set_attr "cpu_facility" "extimm,extimm,z10")
3539 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3541 (define_insn "*extendhidi2"
3542 [(set (match_operand:DI 0 "register_operand" "=d")
3543 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3546 [(set_attr "op_type" "RXY")
3547 (set_attr "z10prop" "z10_super_E1")])
3550 ; extendhisi2 instruction pattern(s).
3553 (define_insn "*extendhisi2_extimm"
3554 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3555 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3562 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3563 (set_attr "type" "*,*,*,larl")
3564 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3565 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3567 (define_insn "*extendhisi2"
3568 [(set (match_operand:SI 0 "register_operand" "=d,d")
3569 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3574 [(set_attr "op_type" "RX,RXY")
3575 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3578 ; extendqi(si|di)2 instruction pattern(s).
3581 ; lbr, lgbr, lb, lgb
3582 (define_insn "*extendqi<mode>2_extimm"
3583 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3584 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3589 [(set_attr "op_type" "RRE,RXY")
3590 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3593 (define_insn "*extendqi<mode>2"
3594 [(set (match_operand:GPR 0 "register_operand" "=d")
3595 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3596 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3598 [(set_attr "op_type" "RXY")
3599 (set_attr "z10prop" "z10_super_E1")])
3601 (define_insn_and_split "*extendqi<mode>2_short_displ"
3602 [(set (match_operand:GPR 0 "register_operand" "=d")
3603 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3604 (clobber (reg:CC CC_REGNUM))]
3605 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3607 "&& reload_completed"
3609 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3610 (clobber (reg:CC CC_REGNUM))])
3612 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3613 (clobber (reg:CC CC_REGNUM))])]
3615 operands[1] = adjust_address (operands[1], BLKmode, 0);
3616 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
3617 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
3618 - GET_MODE_BITSIZE (QImode));
3622 ; zero_extendsidi2 instruction pattern(s).
3625 (define_expand "zero_extendsidi2"
3626 [(set (match_operand:DI 0 "register_operand" "")
3627 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3632 emit_clobber (operands[0]);
3633 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3634 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3639 (define_insn "*zero_extendsidi2"
3640 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3641 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3647 [(set_attr "op_type" "RRE,RXY,RIL")
3648 (set_attr "type" "*,*,larl")
3649 (set_attr "cpu_facility" "*,*,z10")
3650 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3653 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3656 (define_insn "*llgt_sidi"
3657 [(set (match_operand:DI 0 "register_operand" "=d")
3658 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3659 (const_int 2147483647)))]
3662 [(set_attr "op_type" "RXE")
3663 (set_attr "z10prop" "z10_super_E1")])
3665 (define_insn_and_split "*llgt_sidi_split"
3666 [(set (match_operand:DI 0 "register_operand" "=d")
3667 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3668 (const_int 2147483647)))
3669 (clobber (reg:CC CC_REGNUM))]
3672 "&& reload_completed"
3674 (and:DI (subreg:DI (match_dup 1) 0)
3675 (const_int 2147483647)))]
3678 (define_insn "*llgt_sisi"
3679 [(set (match_operand:SI 0 "register_operand" "=d,d")
3680 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3681 (const_int 2147483647)))]
3686 [(set_attr "op_type" "RRE,RXE")
3687 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3689 (define_insn "*llgt_didi"
3690 [(set (match_operand:DI 0 "register_operand" "=d,d")
3691 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3692 (const_int 2147483647)))]
3697 [(set_attr "op_type" "RRE,RXE")
3698 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3701 [(set (match_operand:DSI 0 "register_operand" "")
3702 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3703 (const_int 2147483647)))
3704 (clobber (reg:CC CC_REGNUM))]
3705 "TARGET_ZARCH && reload_completed"
3707 (and:DSI (match_dup 1)
3708 (const_int 2147483647)))]
3712 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3715 (define_expand "zero_extend<mode>di2"
3716 [(set (match_operand:DI 0 "register_operand" "")
3717 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3722 rtx tmp = gen_reg_rtx (SImode);
3723 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3724 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3727 else if (!TARGET_EXTIMM)
3729 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3730 GET_MODE_BITSIZE(<MODE>mode));
3731 operands[1] = gen_lowpart (DImode, operands[1]);
3732 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3733 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3738 (define_expand "zero_extend<mode>si2"
3739 [(set (match_operand:SI 0 "register_operand" "")
3740 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3745 operands[1] = gen_lowpart (SImode, operands[1]);
3746 emit_insn (gen_andsi3 (operands[0], operands[1],
3747 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3753 (define_insn "*zero_extendhi<mode>2_z10"
3754 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3755 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3761 [(set_attr "op_type" "RXY,RRE,RIL")
3762 (set_attr "type" "*,*,larl")
3763 (set_attr "cpu_facility" "*,*,z10")
3764 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3766 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3767 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3768 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3769 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3774 [(set_attr "op_type" "RRE,RXY")
3775 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3778 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3779 [(set (match_operand:GPR 0 "register_operand" "=d")
3780 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3781 "TARGET_ZARCH && !TARGET_EXTIMM"
3783 [(set_attr "op_type" "RXY")
3784 (set_attr "z10prop" "z10_fwd_A3")])
3786 (define_insn_and_split "*zero_extendhisi2_31"
3787 [(set (match_operand:SI 0 "register_operand" "=&d")
3788 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3789 (clobber (reg:CC CC_REGNUM))]
3792 "&& reload_completed"
3793 [(set (match_dup 0) (const_int 0))
3795 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3796 (clobber (reg:CC CC_REGNUM))])]
3797 "operands[2] = gen_lowpart (HImode, operands[0]);")
3799 (define_insn_and_split "*zero_extendqisi2_31"
3800 [(set (match_operand:SI 0 "register_operand" "=&d")
3801 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
3804 "&& reload_completed"
3805 [(set (match_dup 0) (const_int 0))
3806 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3807 "operands[2] = gen_lowpart (QImode, operands[0]);")
3810 ; zero_extendqihi2 instruction pattern(s).
3813 (define_expand "zero_extendqihi2"
3814 [(set (match_operand:HI 0 "register_operand" "")
3815 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3816 "TARGET_ZARCH && !TARGET_EXTIMM"
3818 operands[1] = gen_lowpart (HImode, operands[1]);
3819 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3823 (define_insn "*zero_extendqihi2_64"
3824 [(set (match_operand:HI 0 "register_operand" "=d")
3825 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3826 "TARGET_ZARCH && !TARGET_EXTIMM"
3828 [(set_attr "op_type" "RXY")
3829 (set_attr "z10prop" "z10_fwd_A3")])
3831 (define_insn_and_split "*zero_extendqihi2_31"
3832 [(set (match_operand:HI 0 "register_operand" "=&d")
3833 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3836 "&& reload_completed"
3837 [(set (match_dup 0) (const_int 0))
3838 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3839 "operands[2] = gen_lowpart (QImode, operands[0]);")
3842 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3845 (define_expand "fixuns_truncdddi2"
3847 [(set (match_operand:DI 0 "register_operand" "")
3848 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3849 (clobber (match_scratch:TD 2 "=f"))])]
3853 rtx label1 = gen_label_rtx ();
3854 rtx label2 = gen_label_rtx ();
3855 rtx temp = gen_reg_rtx (TDmode);
3856 REAL_VALUE_TYPE cmp, sub;
3858 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3859 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3861 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3862 solution is doing the check and the subtraction in TD mode and using a
3863 TD -> DI convert afterwards. */
3864 emit_insn (gen_extendddtd2 (temp, operands[1]));
3865 temp = force_reg (TDmode, temp);
3866 emit_cmp_and_jump_insns (temp,
3867 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3868 LT, NULL_RTX, VOIDmode, 0, label1);
3869 emit_insn (gen_subtd3 (temp, temp,
3870 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3871 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3874 emit_label (label1);
3875 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3876 emit_label (label2);
3880 (define_expand "fixuns_trunctddi2"
3881 [(set (match_operand:DI 0 "register_operand" "")
3882 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
3885 rtx label1 = gen_label_rtx ();
3886 rtx label2 = gen_label_rtx ();
3887 rtx temp = gen_reg_rtx (TDmode);
3888 REAL_VALUE_TYPE cmp, sub;
3890 operands[1] = force_reg (TDmode, operands[1]);
3891 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3892 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3894 emit_cmp_and_jump_insns (operands[1],
3895 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3896 LT, NULL_RTX, VOIDmode, 0, label1);
3897 emit_insn (gen_subtd3 (temp, operands[1],
3898 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3899 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3902 emit_label (label1);
3903 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3904 emit_label (label2);
3909 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2
3910 ; instruction pattern(s).
3913 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
3914 [(set (match_operand:GPR 0 "register_operand" "")
3915 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
3918 rtx label1 = gen_label_rtx ();
3919 rtx label2 = gen_label_rtx ();
3920 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
3921 REAL_VALUE_TYPE cmp, sub;
3923 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
3924 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
3925 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
3927 emit_cmp_and_jump_insns (operands[1],
3928 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
3929 LT, NULL_RTX, VOIDmode, 0, label1);
3930 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
3931 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
3932 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
3936 emit_label (label1);
3937 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
3938 operands[1], GEN_INT (5)));
3939 emit_label (label2);
3943 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
3944 [(set (match_operand:GPR 0 "register_operand" "")
3945 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
3948 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
3953 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
3954 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
3955 [(set (match_operand:GPR 0 "register_operand" "=d")
3956 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
3957 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3958 (clobber (reg:CC CC_REGNUM))]
3960 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
3961 [(set_attr "op_type" "RRE")
3962 (set_attr "type" "ftoi")])
3966 ; fix_trunc(td|dd)di2 instruction pattern(s).
3969 (define_expand "fix_trunc<mode>di2"
3970 [(set (match_operand:DI 0 "register_operand" "")
3971 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
3972 "TARGET_ZARCH && TARGET_HARD_DFP"
3974 operands[1] = force_reg (<MODE>mode, operands[1]);
3975 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
3981 (define_insn "fix_trunc<DFP:mode>di2_dfp"
3982 [(set (match_operand:DI 0 "register_operand" "=d")
3983 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
3984 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3985 (clobber (reg:CC CC_REGNUM))]
3986 "TARGET_ZARCH && TARGET_HARD_DFP"
3987 "cg<DFP:xde>tr\t%0,%h2,%1"
3988 [(set_attr "op_type" "RRF")
3989 (set_attr "type" "ftoidfp")])
3993 ; fix_trunctf(si|di)2 instruction pattern(s).
3996 (define_expand "fix_trunctf<mode>2"
3997 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
3998 (fix:GPR (match_operand:TF 1 "register_operand" "")))
3999 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4000 (clobber (reg:CC CC_REGNUM))])]
4006 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4009 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4010 (define_insn "floatdi<mode>2"
4011 [(set (match_operand:FP 0 "register_operand" "=f")
4012 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4013 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4014 "c<xde>g<bt>r\t%0,%1"
4015 [(set_attr "op_type" "RRE")
4016 (set_attr "type" "itof<mode>" )])
4018 ; cxfbr, cdfbr, cefbr
4019 (define_insn "floatsi<mode>2"
4020 [(set (match_operand:BFP 0 "register_operand" "=f")
4021 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4024 [(set_attr "op_type" "RRE")
4025 (set_attr "type" "itof<mode>" )])
4029 ; truncdfsf2 instruction pattern(s).
4032 (define_insn "truncdfsf2"
4033 [(set (match_operand:SF 0 "register_operand" "=f")
4034 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4037 [(set_attr "op_type" "RRE")
4038 (set_attr "type" "ftruncdf")])
4041 ; trunctf(df|sf)2 instruction pattern(s).
4045 (define_insn "trunctf<mode>2"
4046 [(set (match_operand:DSF 0 "register_operand" "=f")
4047 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4048 (clobber (match_scratch:TF 2 "=f"))]
4050 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4051 [(set_attr "length" "6")
4052 (set_attr "type" "ftrunctf")])
4055 ; trunctddd2 and truncddsd2 instruction pattern(s).
4058 (define_insn "trunctddd2"
4059 [(set (match_operand:DD 0 "register_operand" "=f")
4060 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4061 (clobber (match_scratch:TD 2 "=f"))]
4063 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4064 [(set_attr "length" "6")
4065 (set_attr "type" "ftruncdd")])
4067 (define_insn "truncddsd2"
4068 [(set (match_operand:SD 0 "register_operand" "=f")
4069 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4072 [(set_attr "op_type" "RRF")
4073 (set_attr "type" "ftruncsd")])
4076 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4079 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4080 (define_insn "extend<DSF:mode><BFP:mode>2"
4081 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4082 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4084 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4086 l<BFP:xde><DSF:xde>br\t%0,%1
4087 l<BFP:xde><DSF:xde>b\t%0,%1"
4088 [(set_attr "op_type" "RRE,RXE")
4089 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4092 ; extendddtd2 and extendsddd2 instruction pattern(s).
4095 (define_insn "extendddtd2"
4096 [(set (match_operand:TD 0 "register_operand" "=f")
4097 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4100 [(set_attr "op_type" "RRF")
4101 (set_attr "type" "fsimptf")])
4103 (define_insn "extendsddd2"
4104 [(set (match_operand:DD 0 "register_operand" "=f")
4105 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4108 [(set_attr "op_type" "RRF")
4109 (set_attr "type" "fsimptf")])
4111 ; Binary <-> Decimal floating point trunc patterns
4114 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4115 [(set (reg:DFP_ALL FPR0_REGNUM)
4116 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4117 (use (reg:SI GPR0_REGNUM))
4118 (clobber (reg:CC CC_REGNUM))]
4122 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4123 [(set (reg:BFP FPR0_REGNUM)
4124 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4125 (use (reg:SI GPR0_REGNUM))
4126 (clobber (reg:CC CC_REGNUM))]
4130 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4131 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4132 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4134 [(set (reg:DFP_ALL FPR0_REGNUM)
4135 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4136 (use (reg:SI GPR0_REGNUM))
4137 (clobber (reg:CC CC_REGNUM))])
4138 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4139 (reg:DFP_ALL FPR0_REGNUM))]
4141 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4143 HOST_WIDE_INT flags;
4145 flags = (PFPO_CONVERT |
4146 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4147 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4149 operands[2] = GEN_INT (flags);
4152 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4153 [(set (reg:DFP_ALL FPR2_REGNUM)
4154 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4155 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4157 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4158 (use (reg:SI GPR0_REGNUM))
4159 (clobber (reg:CC CC_REGNUM))])
4160 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4162 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4164 HOST_WIDE_INT flags;
4166 flags = (PFPO_CONVERT |
4167 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4168 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4170 operands[2] = GEN_INT (flags);
4174 ; Binary <-> Decimal floating point extend patterns
4177 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4178 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4179 (use (reg:SI GPR0_REGNUM))
4180 (clobber (reg:CC CC_REGNUM))]
4184 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4185 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4186 (use (reg:SI GPR0_REGNUM))
4187 (clobber (reg:CC CC_REGNUM))]
4191 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4192 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4193 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4195 [(set (reg:DFP_ALL FPR0_REGNUM)
4196 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4197 (use (reg:SI GPR0_REGNUM))
4198 (clobber (reg:CC CC_REGNUM))])
4199 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4200 (reg:DFP_ALL FPR0_REGNUM))]
4202 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4204 HOST_WIDE_INT flags;
4206 flags = (PFPO_CONVERT |
4207 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4208 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4210 operands[2] = GEN_INT (flags);
4213 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4214 [(set (reg:DFP_ALL FPR2_REGNUM)
4215 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4216 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4218 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4219 (use (reg:SI GPR0_REGNUM))
4220 (clobber (reg:CC CC_REGNUM))])
4221 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4223 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4225 HOST_WIDE_INT flags;
4227 flags = (PFPO_CONVERT |
4228 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4229 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4231 operands[2] = GEN_INT (flags);
4236 ;; ARITHMETIC OPERATIONS
4238 ; arithmetic operations set the ConditionCode,
4239 ; because of unpredictable Bits in Register for Halfword and Byte
4240 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4243 ;;- Add instructions.
4247 ; addti3 instruction pattern(s).
4250 (define_insn_and_split "addti3"
4251 [(set (match_operand:TI 0 "register_operand" "=&d")
4252 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4253 (match_operand:TI 2 "general_operand" "do") ) )
4254 (clobber (reg:CC CC_REGNUM))]
4257 "&& reload_completed"
4259 [(set (reg:CCL1 CC_REGNUM)
4260 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4262 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4264 [(set (match_dup 3) (plus:DI
4265 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4266 (match_dup 4)) (match_dup 5)))
4267 (clobber (reg:CC CC_REGNUM))])]
4268 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4269 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4270 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4271 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4272 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4273 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4276 ; adddi3 instruction pattern(s).
4279 (define_expand "adddi3"
4281 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4282 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4283 (match_operand:DI 2 "general_operand" "")))
4284 (clobber (reg:CC CC_REGNUM))])]
4288 (define_insn "*adddi3_sign"
4289 [(set (match_operand:DI 0 "register_operand" "=d,d")
4290 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4291 (match_operand:DI 1 "register_operand" "0,0")))
4292 (clobber (reg:CC CC_REGNUM))]
4297 [(set_attr "op_type" "RRE,RXY")])
4299 (define_insn "*adddi3_zero_cc"
4300 [(set (reg CC_REGNUM)
4301 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4302 (match_operand:DI 1 "register_operand" "0,0"))
4304 (set (match_operand:DI 0 "register_operand" "=d,d")
4305 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4306 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4310 [(set_attr "op_type" "RRE,RXY")
4311 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4313 (define_insn "*adddi3_zero_cconly"
4314 [(set (reg CC_REGNUM)
4315 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4316 (match_operand:DI 1 "register_operand" "0,0"))
4318 (clobber (match_scratch:DI 0 "=d,d"))]
4319 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4323 [(set_attr "op_type" "RRE,RXY")
4324 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4326 (define_insn "*adddi3_zero"
4327 [(set (match_operand:DI 0 "register_operand" "=d,d")
4328 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4329 (match_operand:DI 1 "register_operand" "0,0")))
4330 (clobber (reg:CC CC_REGNUM))]
4335 [(set_attr "op_type" "RRE,RXY")
4336 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4338 (define_insn_and_split "*adddi3_31z"
4339 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4340 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4341 (match_operand:DI 2 "general_operand" "do") ) )
4342 (clobber (reg:CC CC_REGNUM))]
4343 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4345 "&& reload_completed"
4347 [(set (reg:CCL1 CC_REGNUM)
4348 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4350 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4352 [(set (match_dup 3) (plus:SI
4353 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4354 (match_dup 4)) (match_dup 5)))
4355 (clobber (reg:CC CC_REGNUM))])]
4356 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4357 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4358 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4359 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4360 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4361 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4363 (define_insn_and_split "*adddi3_31"
4364 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4365 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4366 (match_operand:DI 2 "general_operand" "do") ) )
4367 (clobber (reg:CC CC_REGNUM))]
4370 "&& reload_completed"
4372 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4373 (clobber (reg:CC CC_REGNUM))])
4375 [(set (reg:CCL1 CC_REGNUM)
4376 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4378 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4380 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4382 (label_ref (match_dup 9))))
4384 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4385 (clobber (reg:CC CC_REGNUM))])
4387 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4388 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4389 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4390 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4391 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4392 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4393 operands[9] = gen_label_rtx ();")
4396 ; addsi3 instruction pattern(s).
4399 (define_expand "addsi3"
4401 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4402 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4403 (match_operand:SI 2 "general_operand" "")))
4404 (clobber (reg:CC CC_REGNUM))])]
4408 (define_insn "*addsi3_sign"
4409 [(set (match_operand:SI 0 "register_operand" "=d,d")
4410 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4411 (match_operand:SI 1 "register_operand" "0,0")))
4412 (clobber (reg:CC CC_REGNUM))]
4417 [(set_attr "op_type" "RX,RXY")])
4420 ; add(di|si)3 instruction pattern(s).
4423 ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4424 (define_insn "*add<mode>3"
4425 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS")
4426 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
4427 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) )
4428 (clobber (reg:CC CC_REGNUM))]
4438 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY")
4439 (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10")
4440 (set_attr "z10prop" "z10_super_E1,
4448 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4449 (define_insn "*add<mode>3_carry1_cc"
4450 [(set (reg CC_REGNUM)
4451 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4452 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4454 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d")
4455 (plus:GPR (match_dup 1) (match_dup 2)))]
4456 "s390_match_ccmode (insn, CCL1mode)"
4464 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4465 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4466 (set_attr "z10prop" "z10_super_E1,
4473 ; alr, al, aly, algr, alg
4474 (define_insn "*add<mode>3_carry1_cconly"
4475 [(set (reg CC_REGNUM)
4476 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4477 (match_operand:GPR 2 "general_operand" "d,R,T"))
4479 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4480 "s390_match_ccmode (insn, CCL1mode)"
4485 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4486 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4488 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4489 (define_insn "*add<mode>3_carry2_cc"
4490 [(set (reg CC_REGNUM)
4491 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4492 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4494 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4495 (plus:GPR (match_dup 1) (match_dup 2)))]
4496 "s390_match_ccmode (insn, CCL1mode)"
4504 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4505 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4506 (set_attr "z10prop" "z10_super_E1,
4513 ; alr, al, aly, algr, alg
4514 (define_insn "*add<mode>3_carry2_cconly"
4515 [(set (reg CC_REGNUM)
4516 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4517 (match_operand:GPR 2 "general_operand" "d,R,T"))
4519 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4520 "s390_match_ccmode (insn, CCL1mode)"
4525 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4526 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4528 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4529 (define_insn "*add<mode>3_cc"
4530 [(set (reg CC_REGNUM)
4531 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4532 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4534 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4535 (plus:GPR (match_dup 1) (match_dup 2)))]
4536 "s390_match_ccmode (insn, CCLmode)"
4544 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4545 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4546 (set_attr "z10prop" "z10_super_E1,
4553 ; alr, al, aly, algr, alg
4554 (define_insn "*add<mode>3_cconly"
4555 [(set (reg CC_REGNUM)
4556 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4557 (match_operand:GPR 2 "general_operand" "d,R,T"))
4559 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4560 "s390_match_ccmode (insn, CCLmode)"
4565 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4566 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4568 ; alr, al, aly, algr, alg
4569 (define_insn "*add<mode>3_cconly2"
4570 [(set (reg CC_REGNUM)
4571 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4572 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
4573 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4574 "s390_match_ccmode(insn, CCLmode)"
4579 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4580 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4582 ; ahi, afi, aghi, agfi, asi, agsi
4583 (define_insn "*add<mode>3_imm_cc"
4584 [(set (reg CC_REGNUM)
4585 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0")
4586 (match_operand:GPR 2 "const_int_operand" "K,Os,C"))
4588 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS")
4589 (plus:GPR (match_dup 1) (match_dup 2)))]
4590 "s390_match_ccmode (insn, CCAmode)
4591 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4592 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4593 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
4594 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
4599 [(set_attr "op_type" "RI,RIL,SIY")
4600 (set_attr "cpu_facility" "*,extimm,z10")
4601 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4604 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4607 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4608 (define_insn "add<mode>3"
4609 [(set (match_operand:FP 0 "register_operand" "=f, f")
4610 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4611 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4612 (clobber (reg:CC CC_REGNUM))]
4615 a<xde><bt>r\t%0,<op1>%2
4617 [(set_attr "op_type" "<RRer>,RXE")
4618 (set_attr "type" "fsimp<mode>")])
4620 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4621 (define_insn "*add<mode>3_cc"
4622 [(set (reg CC_REGNUM)
4623 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4624 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4625 (match_operand:FP 3 "const0_operand" "")))
4626 (set (match_operand:FP 0 "register_operand" "=f,f")
4627 (plus:FP (match_dup 1) (match_dup 2)))]
4628 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4630 a<xde><bt>r\t%0,<op1>%2
4632 [(set_attr "op_type" "<RRer>,RXE")
4633 (set_attr "type" "fsimp<mode>")])
4635 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4636 (define_insn "*add<mode>3_cconly"
4637 [(set (reg CC_REGNUM)
4638 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4639 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4640 (match_operand:FP 3 "const0_operand" "")))
4641 (clobber (match_scratch:FP 0 "=f,f"))]
4642 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4644 a<xde><bt>r\t%0,<op1>%2
4646 [(set_attr "op_type" "<RRer>,RXE")
4647 (set_attr "type" "fsimp<mode>")])
4651 ;;- Subtract instructions.
4655 ; subti3 instruction pattern(s).
4658 (define_insn_and_split "subti3"
4659 [(set (match_operand:TI 0 "register_operand" "=&d")
4660 (minus:TI (match_operand:TI 1 "register_operand" "0")
4661 (match_operand:TI 2 "general_operand" "do") ) )
4662 (clobber (reg:CC CC_REGNUM))]
4665 "&& reload_completed"
4667 [(set (reg:CCL2 CC_REGNUM)
4668 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4670 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4672 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4673 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4674 (clobber (reg:CC CC_REGNUM))])]
4675 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4676 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4677 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4678 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4679 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4680 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4683 ; subdi3 instruction pattern(s).
4686 (define_expand "subdi3"
4688 [(set (match_operand:DI 0 "register_operand" "")
4689 (minus:DI (match_operand:DI 1 "register_operand" "")
4690 (match_operand:DI 2 "general_operand" "")))
4691 (clobber (reg:CC CC_REGNUM))])]
4695 (define_insn "*subdi3_sign"
4696 [(set (match_operand:DI 0 "register_operand" "=d,d")
4697 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4698 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4699 (clobber (reg:CC CC_REGNUM))]
4704 [(set_attr "op_type" "RRE,RXY")
4705 (set_attr "z10prop" "z10_c,*")])
4707 (define_insn "*subdi3_zero_cc"
4708 [(set (reg CC_REGNUM)
4709 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4710 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4712 (set (match_operand:DI 0 "register_operand" "=d,d")
4713 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4714 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4718 [(set_attr "op_type" "RRE,RXY")
4719 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4721 (define_insn "*subdi3_zero_cconly"
4722 [(set (reg CC_REGNUM)
4723 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4724 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4726 (clobber (match_scratch:DI 0 "=d,d"))]
4727 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4731 [(set_attr "op_type" "RRE,RXY")
4732 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4734 (define_insn "*subdi3_zero"
4735 [(set (match_operand:DI 0 "register_operand" "=d,d")
4736 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4737 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4738 (clobber (reg:CC CC_REGNUM))]
4743 [(set_attr "op_type" "RRE,RXY")
4744 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4746 (define_insn_and_split "*subdi3_31z"
4747 [(set (match_operand:DI 0 "register_operand" "=&d")
4748 (minus:DI (match_operand:DI 1 "register_operand" "0")
4749 (match_operand:DI 2 "general_operand" "do") ) )
4750 (clobber (reg:CC CC_REGNUM))]
4751 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4753 "&& reload_completed"
4755 [(set (reg:CCL2 CC_REGNUM)
4756 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4758 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4760 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4761 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4762 (clobber (reg:CC CC_REGNUM))])]
4763 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4764 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4765 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4766 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4767 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4768 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4770 (define_insn_and_split "*subdi3_31"
4771 [(set (match_operand:DI 0 "register_operand" "=&d")
4772 (minus:DI (match_operand:DI 1 "register_operand" "0")
4773 (match_operand:DI 2 "general_operand" "do") ) )
4774 (clobber (reg:CC CC_REGNUM))]
4777 "&& reload_completed"
4779 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4780 (clobber (reg:CC CC_REGNUM))])
4782 [(set (reg:CCL2 CC_REGNUM)
4783 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4785 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4787 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4789 (label_ref (match_dup 9))))
4791 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4792 (clobber (reg:CC CC_REGNUM))])
4794 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4795 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4796 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4797 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4798 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4799 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4800 operands[9] = gen_label_rtx ();")
4803 ; subsi3 instruction pattern(s).
4806 (define_expand "subsi3"
4808 [(set (match_operand:SI 0 "register_operand" "")
4809 (minus:SI (match_operand:SI 1 "register_operand" "")
4810 (match_operand:SI 2 "general_operand" "")))
4811 (clobber (reg:CC CC_REGNUM))])]
4815 (define_insn "*subsi3_sign"
4816 [(set (match_operand:SI 0 "register_operand" "=d,d")
4817 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4818 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4819 (clobber (reg:CC CC_REGNUM))]
4824 [(set_attr "op_type" "RX,RXY")])
4827 ; sub(di|si)3 instruction pattern(s).
4830 ; sr, s, sy, sgr, sg
4831 (define_insn "*sub<mode>3"
4832 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4833 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4834 (match_operand:GPR 2 "general_operand" "d,R,T") ) )
4835 (clobber (reg:CC CC_REGNUM))]
4841 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4842 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4844 ; slr, sl, sly, slgr, slg
4845 (define_insn "*sub<mode>3_borrow_cc"
4846 [(set (reg CC_REGNUM)
4847 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4848 (match_operand:GPR 2 "general_operand" "d,R,T"))
4850 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4851 (minus:GPR (match_dup 1) (match_dup 2)))]
4852 "s390_match_ccmode (insn, CCL2mode)"
4857 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4858 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4860 ; slr, sl, sly, slgr, slg
4861 (define_insn "*sub<mode>3_borrow_cconly"
4862 [(set (reg CC_REGNUM)
4863 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4864 (match_operand:GPR 2 "general_operand" "d,R,T"))
4866 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4867 "s390_match_ccmode (insn, CCL2mode)"
4872 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4873 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4875 ; slr, sl, sly, slgr, slg
4876 (define_insn "*sub<mode>3_cc"
4877 [(set (reg CC_REGNUM)
4878 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4879 (match_operand:GPR 2 "general_operand" "d,R,T"))
4881 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4882 (minus:GPR (match_dup 1) (match_dup 2)))]
4883 "s390_match_ccmode (insn, CCLmode)"
4888 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4889 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4891 ; slr, sl, sly, slgr, slg
4892 (define_insn "*sub<mode>3_cc2"
4893 [(set (reg CC_REGNUM)
4894 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4895 (match_operand:GPR 2 "general_operand" "d,R,T")))
4896 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4897 (minus:GPR (match_dup 1) (match_dup 2)))]
4898 "s390_match_ccmode (insn, CCL3mode)"
4903 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4904 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4906 ; slr, sl, sly, slgr, slg
4907 (define_insn "*sub<mode>3_cconly"
4908 [(set (reg CC_REGNUM)
4909 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4910 (match_operand:GPR 2 "general_operand" "d,R,T"))
4912 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4913 "s390_match_ccmode (insn, CCLmode)"
4918 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4919 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4922 ; slr, sl, sly, slgr, slg
4923 (define_insn "*sub<mode>3_cconly2"
4924 [(set (reg CC_REGNUM)
4925 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4926 (match_operand:GPR 2 "general_operand" "d,R,T")))
4927 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4928 "s390_match_ccmode (insn, CCL3mode)"
4933 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4934 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4938 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
4941 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4942 (define_insn "sub<mode>3"
4943 [(set (match_operand:FP 0 "register_operand" "=f, f")
4944 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
4945 (match_operand:FP 2 "general_operand" "f,<Rf>")))
4946 (clobber (reg:CC CC_REGNUM))]
4949 s<xde><bt>r\t%0,<op1>%2
4951 [(set_attr "op_type" "<RRer>,RXE")
4952 (set_attr "type" "fsimp<mode>")])
4954 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4955 (define_insn "*sub<mode>3_cc"
4956 [(set (reg CC_REGNUM)
4957 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4958 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4959 (match_operand:FP 3 "const0_operand" "")))
4960 (set (match_operand:FP 0 "register_operand" "=f,f")
4961 (minus:FP (match_dup 1) (match_dup 2)))]
4962 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4964 s<xde><bt>r\t%0,<op1>%2
4966 [(set_attr "op_type" "<RRer>,RXE")
4967 (set_attr "type" "fsimp<mode>")])
4969 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
4970 (define_insn "*sub<mode>3_cconly"
4971 [(set (reg CC_REGNUM)
4972 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4973 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4974 (match_operand:FP 3 "const0_operand" "")))
4975 (clobber (match_scratch:FP 0 "=f,f"))]
4976 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4978 s<xde><bt>r\t%0,<op1>%2
4980 [(set_attr "op_type" "<RRer>,RXE")
4981 (set_attr "type" "fsimp<mode>")])
4985 ;;- Conditional add/subtract instructions.
4989 ; add(di|si)cc instruction pattern(s).
4992 ; the following 4 patterns are used when the result of an add with
4993 ; carry is checked for an overflow condition
4995 ; op1 + op2 + c < op1
4997 ; alcr, alc, alcgr, alcg
4998 (define_insn "*add<mode>3_alc_carry1_cc"
4999 [(set (reg CC_REGNUM)
5001 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5002 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5003 (match_operand:GPR 2 "general_operand" "d,RT"))
5005 (set (match_operand:GPR 0 "register_operand" "=d,d")
5006 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5007 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5011 [(set_attr "op_type" "RRE,RXY")])
5013 ; alcr, alc, alcgr, alcg
5014 (define_insn "*add<mode>3_alc_carry1_cconly"
5015 [(set (reg CC_REGNUM)
5017 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5018 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5019 (match_operand:GPR 2 "general_operand" "d,RT"))
5021 (clobber (match_scratch:GPR 0 "=d,d"))]
5022 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5026 [(set_attr "op_type" "RRE,RXY")])
5028 ; op1 + op2 + c < op2
5030 ; alcr, alc, alcgr, alcg
5031 (define_insn "*add<mode>3_alc_carry2_cc"
5032 [(set (reg CC_REGNUM)
5034 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5035 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5036 (match_operand:GPR 2 "general_operand" "d,RT"))
5038 (set (match_operand:GPR 0 "register_operand" "=d,d")
5039 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5040 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5044 [(set_attr "op_type" "RRE,RXY")])
5046 ; alcr, alc, alcgr, alcg
5047 (define_insn "*add<mode>3_alc_carry2_cconly"
5048 [(set (reg CC_REGNUM)
5050 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5051 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5052 (match_operand:GPR 2 "general_operand" "d,RT"))
5054 (clobber (match_scratch:GPR 0 "=d,d"))]
5055 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5059 [(set_attr "op_type" "RRE,RXY")])
5061 ; alcr, alc, alcgr, alcg
5062 (define_insn "*add<mode>3_alc_cc"
5063 [(set (reg CC_REGNUM)
5065 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5066 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5067 (match_operand:GPR 2 "general_operand" "d,RT"))
5069 (set (match_operand:GPR 0 "register_operand" "=d,d")
5070 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5071 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5075 [(set_attr "op_type" "RRE,RXY")])
5077 ; alcr, alc, alcgr, alcg
5078 (define_insn "*add<mode>3_alc"
5079 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5080 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5081 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5082 (match_operand:GPR 2 "general_operand" "d,RT")))
5083 (clobber (reg:CC CC_REGNUM))]
5088 [(set_attr "op_type" "RRE,RXY")])
5090 ; slbr, slb, slbgr, slbg
5091 (define_insn "*sub<mode>3_slb_cc"
5092 [(set (reg CC_REGNUM)
5094 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5095 (match_operand:GPR 2 "general_operand" "d,RT"))
5096 (match_operand:GPR 3 "s390_slb_comparison" ""))
5098 (set (match_operand:GPR 0 "register_operand" "=d,d")
5099 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5100 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5104 [(set_attr "op_type" "RRE,RXY")
5105 (set_attr "z10prop" "z10_c,*")])
5107 ; slbr, slb, slbgr, slbg
5108 (define_insn "*sub<mode>3_slb"
5109 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5110 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5111 (match_operand:GPR 2 "general_operand" "d,RT"))
5112 (match_operand:GPR 3 "s390_slb_comparison" "")))
5113 (clobber (reg:CC CC_REGNUM))]
5118 [(set_attr "op_type" "RRE,RXY")
5119 (set_attr "z10prop" "z10_c,*")])
5121 (define_expand "add<mode>cc"
5122 [(match_operand:GPR 0 "register_operand" "")
5123 (match_operand 1 "comparison_operator" "")
5124 (match_operand:GPR 2 "register_operand" "")
5125 (match_operand:GPR 3 "const_int_operand" "")]
5127 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5128 XEXP (operands[1], 0), XEXP (operands[1], 1),
5129 operands[0], operands[2],
5130 operands[3])) FAIL; DONE;")
5133 ; scond instruction pattern(s).
5136 (define_insn_and_split "*scond<mode>"
5137 [(set (match_operand:GPR 0 "register_operand" "=&d")
5138 (match_operand:GPR 1 "s390_alc_comparison" ""))
5139 (clobber (reg:CC CC_REGNUM))]
5142 "&& reload_completed"
5143 [(set (match_dup 0) (const_int 0))
5145 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5147 (clobber (reg:CC CC_REGNUM))])]
5150 (define_insn_and_split "*scond<mode>_neg"
5151 [(set (match_operand:GPR 0 "register_operand" "=&d")
5152 (match_operand:GPR 1 "s390_slb_comparison" ""))
5153 (clobber (reg:CC CC_REGNUM))]
5156 "&& reload_completed"
5157 [(set (match_dup 0) (const_int 0))
5159 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5161 (clobber (reg:CC CC_REGNUM))])
5163 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5164 (clobber (reg:CC CC_REGNUM))])]
5168 (define_expand "cstore<mode>4"
5169 [(set (match_operand:SI 0 "register_operand" "")
5170 (match_operator:SI 1 "s390_scond_operator"
5171 [(match_operand:GPR 2 "register_operand" "")
5172 (match_operand:GPR 3 "general_operand" "")]))]
5174 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5175 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5177 (define_expand "cstorecc4"
5179 [(set (match_operand:SI 0 "register_operand" "")
5180 (match_operator:SI 1 "s390_eqne_operator"
5181 [(match_operand:CCZ1 2 "register_operand")
5182 (match_operand 3 "const0_operand")]))
5183 (clobber (reg:CC CC_REGNUM))])]
5185 "emit_insn (gen_sne (operands[0], operands[2]));
5186 if (GET_CODE (operands[1]) == EQ)
5187 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5190 (define_insn_and_split "sne"
5191 [(set (match_operand:SI 0 "register_operand" "=d")
5192 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5194 (clobber (reg:CC CC_REGNUM))]
5199 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5200 (clobber (reg:CC CC_REGNUM))])])
5204 ;;- Multiply instructions.
5208 ; muldi3 instruction pattern(s).
5211 (define_insn "*muldi3_sign"
5212 [(set (match_operand:DI 0 "register_operand" "=d,d")
5213 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5214 (match_operand:DI 1 "register_operand" "0,0")))]
5219 [(set_attr "op_type" "RRE,RXY")
5220 (set_attr "type" "imuldi")])
5222 (define_insn "muldi3"
5223 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5224 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5225 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5232 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5233 (set_attr "type" "imuldi")
5234 (set_attr "cpu_facility" "*,*,*,z10")])
5237 ; mulsi3 instruction pattern(s).
5240 (define_insn "*mulsi3_sign"
5241 [(set (match_operand:SI 0 "register_operand" "=d,d")
5242 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5243 (match_operand:SI 1 "register_operand" "0,0")))]
5248 [(set_attr "op_type" "RX,RXY")
5249 (set_attr "type" "imulhi")
5250 (set_attr "cpu_facility" "*,z10")])
5252 (define_insn "mulsi3"
5253 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5254 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5255 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5263 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5264 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5265 (set_attr "cpu_facility" "*,*,*,*,z10")])
5268 ; mulsidi3 instruction pattern(s).
5271 (define_insn "mulsidi3"
5272 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5273 (mult:DI (sign_extend:DI
5274 (match_operand:SI 1 "register_operand" "%0,0,0"))
5276 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5282 [(set_attr "op_type" "RR,RX,RXY")
5283 (set_attr "type" "imulsi")
5284 (set_attr "cpu_facility" "*,*,z10")])
5287 ; umulsidi3 instruction pattern(s).
5290 (define_insn "umulsidi3"
5291 [(set (match_operand:DI 0 "register_operand" "=d,d")
5292 (mult:DI (zero_extend:DI
5293 (match_operand:SI 1 "register_operand" "%0,0"))
5295 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
5296 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5300 [(set_attr "op_type" "RRE,RXY")
5301 (set_attr "type" "imulsi")])
5304 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5307 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5308 (define_insn "mul<mode>3"
5309 [(set (match_operand:FP 0 "register_operand" "=f,f")
5310 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5311 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5314 m<xdee><bt>r\t%0,<op1>%2
5316 [(set_attr "op_type" "<RRer>,RXE")
5317 (set_attr "type" "fmul<mode>")])
5319 ; madbr, maebr, maxb, madb, maeb
5320 (define_insn "*fmadd<mode>"
5321 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5322 (plus:DSF (mult:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5323 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5324 (match_operand:DSF 3 "register_operand" "0,0")))]
5325 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5329 [(set_attr "op_type" "RRE,RXE")
5330 (set_attr "type" "fmul<mode>")])
5332 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5333 (define_insn "*fmsub<mode>"
5334 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5335 (minus:DSF (mult:DSF (match_operand:DSF 1 "nonimmediate_operand" "f,f")
5336 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5337 (match_operand:DSF 3 "register_operand" "0,0")))]
5338 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5342 [(set_attr "op_type" "RRE,RXE")
5343 (set_attr "type" "fmul<mode>")])
5346 ;;- Divide and modulo instructions.
5350 ; divmoddi4 instruction pattern(s).
5353 (define_expand "divmoddi4"
5354 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5355 (div:DI (match_operand:DI 1 "register_operand" "")
5356 (match_operand:DI 2 "general_operand" "")))
5357 (set (match_operand:DI 3 "general_operand" "")
5358 (mod:DI (match_dup 1) (match_dup 2)))])
5359 (clobber (match_dup 4))]
5362 rtx insn, div_equal, mod_equal;
5364 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5365 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5367 operands[4] = gen_reg_rtx(TImode);
5368 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5370 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5371 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5373 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5374 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5379 (define_insn "divmodtidi3"
5380 [(set (match_operand:TI 0 "register_operand" "=d,d")
5384 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5385 (match_operand:DI 2 "general_operand" "d,RT")))
5387 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5392 [(set_attr "op_type" "RRE,RXY")
5393 (set_attr "type" "idiv")])
5395 (define_insn "divmodtisi3"
5396 [(set (match_operand:TI 0 "register_operand" "=d,d")
5400 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5402 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5405 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5410 [(set_attr "op_type" "RRE,RXY")
5411 (set_attr "type" "idiv")])
5414 ; udivmoddi4 instruction pattern(s).
5417 (define_expand "udivmoddi4"
5418 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5419 (udiv:DI (match_operand:DI 1 "general_operand" "")
5420 (match_operand:DI 2 "nonimmediate_operand" "")))
5421 (set (match_operand:DI 3 "general_operand" "")
5422 (umod:DI (match_dup 1) (match_dup 2)))])
5423 (clobber (match_dup 4))]
5426 rtx insn, div_equal, mod_equal, equal;
5428 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5429 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5430 equal = gen_rtx_IOR (TImode,
5431 gen_rtx_ASHIFT (TImode,
5432 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5434 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5436 operands[4] = gen_reg_rtx(TImode);
5437 emit_clobber (operands[4]);
5438 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5439 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5441 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5442 set_unique_reg_note (insn, REG_EQUAL, equal);
5444 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5445 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5447 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5448 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5453 (define_insn "udivmodtidi3"
5454 [(set (match_operand:TI 0 "register_operand" "=d,d")
5459 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5461 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5465 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5470 [(set_attr "op_type" "RRE,RXY")
5471 (set_attr "type" "idiv")])
5474 ; divmodsi4 instruction pattern(s).
5477 (define_expand "divmodsi4"
5478 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5479 (div:SI (match_operand:SI 1 "general_operand" "")
5480 (match_operand:SI 2 "nonimmediate_operand" "")))
5481 (set (match_operand:SI 3 "general_operand" "")
5482 (mod:SI (match_dup 1) (match_dup 2)))])
5483 (clobber (match_dup 4))]
5486 rtx insn, div_equal, mod_equal, equal;
5488 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5489 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5490 equal = gen_rtx_IOR (DImode,
5491 gen_rtx_ASHIFT (DImode,
5492 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5494 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5496 operands[4] = gen_reg_rtx(DImode);
5497 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5499 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5500 set_unique_reg_note (insn, REG_EQUAL, equal);
5502 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5503 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5505 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5506 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5511 (define_insn "divmoddisi3"
5512 [(set (match_operand:DI 0 "register_operand" "=d,d")
5517 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5519 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5523 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5528 [(set_attr "op_type" "RR,RX")
5529 (set_attr "type" "idiv")])
5532 ; udivsi3 and umodsi3 instruction pattern(s).
5535 (define_expand "udivmodsi4"
5536 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5537 (udiv:SI (match_operand:SI 1 "general_operand" "")
5538 (match_operand:SI 2 "nonimmediate_operand" "")))
5539 (set (match_operand:SI 3 "general_operand" "")
5540 (umod:SI (match_dup 1) (match_dup 2)))])
5541 (clobber (match_dup 4))]
5542 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5544 rtx insn, div_equal, mod_equal, equal;
5546 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5547 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5548 equal = gen_rtx_IOR (DImode,
5549 gen_rtx_ASHIFT (DImode,
5550 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5552 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5554 operands[4] = gen_reg_rtx(DImode);
5555 emit_clobber (operands[4]);
5556 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5557 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5559 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5560 set_unique_reg_note (insn, REG_EQUAL, equal);
5562 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5563 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5565 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5566 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5571 (define_insn "udivmoddisi3"
5572 [(set (match_operand:DI 0 "register_operand" "=d,d")
5577 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5579 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5583 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5584 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5588 [(set_attr "op_type" "RRE,RXY")
5589 (set_attr "type" "idiv")])
5591 (define_expand "udivsi3"
5592 [(set (match_operand:SI 0 "register_operand" "=d")
5593 (udiv:SI (match_operand:SI 1 "general_operand" "")
5594 (match_operand:SI 2 "general_operand" "")))
5595 (clobber (match_dup 3))]
5596 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5598 rtx insn, udiv_equal, umod_equal, equal;
5600 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5601 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5602 equal = gen_rtx_IOR (DImode,
5603 gen_rtx_ASHIFT (DImode,
5604 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5606 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5608 operands[3] = gen_reg_rtx (DImode);
5610 if (CONSTANT_P (operands[2]))
5612 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5614 rtx label1 = gen_label_rtx ();
5616 operands[1] = make_safe_from (operands[1], operands[0]);
5617 emit_move_insn (operands[0], const0_rtx);
5618 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5620 emit_move_insn (operands[0], const1_rtx);
5621 emit_label (label1);
5625 operands[2] = force_reg (SImode, operands[2]);
5626 operands[2] = make_safe_from (operands[2], operands[0]);
5628 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5629 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5631 set_unique_reg_note (insn, REG_EQUAL, equal);
5633 insn = emit_move_insn (operands[0],
5634 gen_lowpart (SImode, operands[3]));
5635 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5640 rtx label1 = gen_label_rtx ();
5641 rtx label2 = gen_label_rtx ();
5642 rtx label3 = gen_label_rtx ();
5644 operands[1] = force_reg (SImode, operands[1]);
5645 operands[1] = make_safe_from (operands[1], operands[0]);
5646 operands[2] = force_reg (SImode, operands[2]);
5647 operands[2] = make_safe_from (operands[2], operands[0]);
5649 emit_move_insn (operands[0], const0_rtx);
5650 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5652 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5654 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5656 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5657 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5659 set_unique_reg_note (insn, REG_EQUAL, equal);
5661 insn = emit_move_insn (operands[0],
5662 gen_lowpart (SImode, operands[3]));
5663 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5666 emit_label (label1);
5667 emit_move_insn (operands[0], operands[1]);
5669 emit_label (label2);
5670 emit_move_insn (operands[0], const1_rtx);
5671 emit_label (label3);
5673 emit_move_insn (operands[0], operands[0]);
5677 (define_expand "umodsi3"
5678 [(set (match_operand:SI 0 "register_operand" "=d")
5679 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5680 (match_operand:SI 2 "nonimmediate_operand" "")))
5681 (clobber (match_dup 3))]
5682 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5684 rtx insn, udiv_equal, umod_equal, equal;
5686 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5687 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5688 equal = gen_rtx_IOR (DImode,
5689 gen_rtx_ASHIFT (DImode,
5690 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5692 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5694 operands[3] = gen_reg_rtx (DImode);
5696 if (CONSTANT_P (operands[2]))
5698 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5700 rtx label1 = gen_label_rtx ();
5702 operands[1] = make_safe_from (operands[1], operands[0]);
5703 emit_move_insn (operands[0], operands[1]);
5704 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
5706 emit_insn (gen_abssi2 (operands[0], operands[2]));
5707 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5708 emit_label (label1);
5712 operands[2] = force_reg (SImode, operands[2]);
5713 operands[2] = make_safe_from (operands[2], operands[0]);
5715 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5716 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5718 set_unique_reg_note (insn, REG_EQUAL, equal);
5720 insn = emit_move_insn (operands[0],
5721 gen_highpart (SImode, operands[3]));
5722 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5727 rtx label1 = gen_label_rtx ();
5728 rtx label2 = gen_label_rtx ();
5729 rtx label3 = gen_label_rtx ();
5731 operands[1] = force_reg (SImode, operands[1]);
5732 operands[1] = make_safe_from (operands[1], operands[0]);
5733 operands[2] = force_reg (SImode, operands[2]);
5734 operands[2] = make_safe_from (operands[2], operands[0]);
5736 emit_move_insn(operands[0], operands[1]);
5737 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5739 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5741 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5743 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5744 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5746 set_unique_reg_note (insn, REG_EQUAL, equal);
5748 insn = emit_move_insn (operands[0],
5749 gen_highpart (SImode, operands[3]));
5750 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5753 emit_label (label1);
5754 emit_move_insn (operands[0], const0_rtx);
5756 emit_label (label2);
5757 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5758 emit_label (label3);
5764 ; div(df|sf)3 instruction pattern(s).
5767 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
5768 (define_insn "div<mode>3"
5769 [(set (match_operand:FP 0 "register_operand" "=f,f")
5770 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5771 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5774 d<xde><bt>r\t%0,<op1>%2
5776 [(set_attr "op_type" "<RRer>,RXE")
5777 (set_attr "type" "fdiv<mode>")])
5781 ;;- And instructions.
5784 (define_expand "and<mode>3"
5785 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5786 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5787 (match_operand:INT 2 "general_operand" "")))
5788 (clobber (reg:CC CC_REGNUM))]
5790 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5793 ; anddi3 instruction pattern(s).
5796 (define_insn "*anddi3_cc"
5797 [(set (reg CC_REGNUM)
5798 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5799 (match_operand:DI 2 "general_operand" "d,RT"))
5801 (set (match_operand:DI 0 "register_operand" "=d,d")
5802 (and:DI (match_dup 1) (match_dup 2)))]
5803 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
5807 [(set_attr "op_type" "RRE,RXY")
5808 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5810 (define_insn "*anddi3_cconly"
5811 [(set (reg CC_REGNUM)
5812 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5813 (match_operand:DI 2 "general_operand" "d,RT"))
5815 (clobber (match_scratch:DI 0 "=d,d"))]
5816 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
5817 /* Do not steal TM patterns. */
5818 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5822 [(set_attr "op_type" "RRE,RXY")
5823 (set_attr "z10prop" "z10_super_E1, z10_super_E1")])
5825 (define_insn "*anddi3"
5826 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5827 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5828 "%d,o,0,0,0,0,0,0,0,0,0,0")
5829 (match_operand:DI 2 "general_operand"
5830 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
5831 (clobber (reg:CC CC_REGNUM))]
5832 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5846 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
5847 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*")
5848 (set_attr "z10prop" "*,
5862 [(set (match_operand:DI 0 "s_operand" "")
5863 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5864 (clobber (reg:CC CC_REGNUM))]
5867 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5868 (clobber (reg:CC CC_REGNUM))])]
5869 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5873 ; andsi3 instruction pattern(s).
5876 (define_insn "*andsi3_cc"
5877 [(set (reg CC_REGNUM)
5878 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5879 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5881 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5882 (and:SI (match_dup 1) (match_dup 2)))]
5883 "s390_match_ccmode(insn, CCTmode)"
5889 [(set_attr "op_type" "RIL,RR,RX,RXY")
5890 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5892 (define_insn "*andsi3_cconly"
5893 [(set (reg CC_REGNUM)
5894 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5895 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5897 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5898 "s390_match_ccmode(insn, CCTmode)
5899 /* Do not steal TM patterns. */
5900 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5906 [(set_attr "op_type" "RIL,RR,RX,RXY")
5907 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5909 (define_insn "*andsi3_zarch"
5910 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5911 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5912 "%d,o,0,0,0,0,0,0,0,0")
5913 (match_operand:SI 2 "general_operand"
5914 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5915 (clobber (reg:CC CC_REGNUM))]
5916 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5928 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")
5929 (set_attr "z10prop" "*,
5940 (define_insn "*andsi3_esa"
5941 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5942 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5943 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5944 (clobber (reg:CC CC_REGNUM))]
5945 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5951 [(set_attr "op_type" "RR,RX,SI,SS")
5952 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
5956 [(set (match_operand:SI 0 "s_operand" "")
5957 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5958 (clobber (reg:CC CC_REGNUM))]
5961 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5962 (clobber (reg:CC CC_REGNUM))])]
5963 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5966 ; andhi3 instruction pattern(s).
5969 (define_insn "*andhi3_zarch"
5970 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5971 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5972 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5973 (clobber (reg:CC CC_REGNUM))]
5974 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5980 [(set_attr "op_type" "RR,RI,SI,SS")
5981 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")
5984 (define_insn "*andhi3_esa"
5985 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5986 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5987 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5988 (clobber (reg:CC CC_REGNUM))]
5989 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5994 [(set_attr "op_type" "RR,SI,SS")
5995 (set_attr "z10prop" "z10_super_E1,*,*")
5999 [(set (match_operand:HI 0 "s_operand" "")
6000 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6001 (clobber (reg:CC CC_REGNUM))]
6004 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6005 (clobber (reg:CC CC_REGNUM))])]
6006 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6009 ; andqi3 instruction pattern(s).
6012 (define_insn "*andqi3_zarch"
6013 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6014 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6015 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
6016 (clobber (reg:CC CC_REGNUM))]
6017 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6024 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
6025 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6027 (define_insn "*andqi3_esa"
6028 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6029 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6030 (match_operand:QI 2 "general_operand" "d,n,Q")))
6031 (clobber (reg:CC CC_REGNUM))]
6032 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6037 [(set_attr "op_type" "RR,SI,SS")
6038 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6041 ; Block and (NC) patterns.
6045 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6046 (and:BLK (match_dup 0)
6047 (match_operand:BLK 1 "memory_operand" "Q")))
6048 (use (match_operand 2 "const_int_operand" "n"))
6049 (clobber (reg:CC CC_REGNUM))]
6050 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6051 "nc\t%O0(%2,%R0),%S1"
6052 [(set_attr "op_type" "SS")])
6055 [(set (match_operand 0 "memory_operand" "")
6057 (match_operand 1 "memory_operand" "")))
6058 (clobber (reg:CC CC_REGNUM))]
6060 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6061 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6063 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6065 (clobber (reg:CC CC_REGNUM))])]
6067 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6068 operands[0] = adjust_address (operands[0], BLKmode, 0);
6069 operands[1] = adjust_address (operands[1], BLKmode, 0);
6074 [(set (match_operand:BLK 0 "memory_operand" "")
6075 (and:BLK (match_dup 0)
6076 (match_operand:BLK 1 "memory_operand" "")))
6077 (use (match_operand 2 "const_int_operand" ""))
6078 (clobber (reg:CC CC_REGNUM))])
6080 [(set (match_operand:BLK 3 "memory_operand" "")
6081 (and:BLK (match_dup 3)
6082 (match_operand:BLK 4 "memory_operand" "")))
6083 (use (match_operand 5 "const_int_operand" ""))
6084 (clobber (reg:CC CC_REGNUM))])]
6085 "s390_offset_p (operands[0], operands[3], operands[2])
6086 && s390_offset_p (operands[1], operands[4], operands[2])
6087 && !s390_overlap_p (operands[0], operands[1],
6088 INTVAL (operands[2]) + INTVAL (operands[5]))
6089 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6091 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6093 (clobber (reg:CC CC_REGNUM))])]
6094 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6095 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6096 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6100 ;;- Bit set (inclusive or) instructions.
6103 (define_expand "ior<mode>3"
6104 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6105 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6106 (match_operand:INT 2 "general_operand" "")))
6107 (clobber (reg:CC CC_REGNUM))]
6109 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6112 ; iordi3 instruction pattern(s).
6115 (define_insn "*iordi3_cc"
6116 [(set (reg CC_REGNUM)
6117 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6118 (match_operand:DI 2 "general_operand" "d,RT"))
6120 (set (match_operand:DI 0 "register_operand" "=d,d")
6121 (ior:DI (match_dup 1) (match_dup 2)))]
6122 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6126 [(set_attr "op_type" "RRE,RXY")
6127 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6129 (define_insn "*iordi3_cconly"
6130 [(set (reg CC_REGNUM)
6131 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6132 (match_operand:DI 2 "general_operand" "d,RT"))
6134 (clobber (match_scratch:DI 0 "=d,d"))]
6135 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6139 [(set_attr "op_type" "RRE,RXY")
6140 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6142 (define_insn "*iordi3"
6143 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
6144 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
6145 (match_operand:DI 2 "general_operand"
6146 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
6147 (clobber (reg:CC CC_REGNUM))]
6148 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6160 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
6161 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*")
6162 (set_attr "z10prop" "z10_super_E1,
6174 [(set (match_operand:DI 0 "s_operand" "")
6175 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6176 (clobber (reg:CC CC_REGNUM))]
6179 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6180 (clobber (reg:CC CC_REGNUM))])]
6181 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6184 ; iorsi3 instruction pattern(s).
6187 (define_insn "*iorsi3_cc"
6188 [(set (reg CC_REGNUM)
6189 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6190 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6192 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6193 (ior:SI (match_dup 1) (match_dup 2)))]
6194 "s390_match_ccmode(insn, CCTmode)"
6200 [(set_attr "op_type" "RIL,RR,RX,RXY")
6201 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6203 (define_insn "*iorsi3_cconly"
6204 [(set (reg CC_REGNUM)
6205 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6206 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6208 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6209 "s390_match_ccmode(insn, CCTmode)"
6215 [(set_attr "op_type" "RIL,RR,RX,RXY")
6216 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6218 (define_insn "*iorsi3_zarch"
6219 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
6220 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
6221 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
6222 (clobber (reg:CC CC_REGNUM))]
6223 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6233 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")
6234 (set_attr "z10prop" "z10_super_E1,
6243 (define_insn "*iorsi3_esa"
6244 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6245 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6246 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6247 (clobber (reg:CC CC_REGNUM))]
6248 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6254 [(set_attr "op_type" "RR,RX,SI,SS")
6255 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6258 [(set (match_operand:SI 0 "s_operand" "")
6259 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6260 (clobber (reg:CC CC_REGNUM))]
6263 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6264 (clobber (reg:CC CC_REGNUM))])]
6265 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6268 ; iorhi3 instruction pattern(s).
6271 (define_insn "*iorhi3_zarch"
6272 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6273 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6274 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
6275 (clobber (reg:CC CC_REGNUM))]
6276 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6282 [(set_attr "op_type" "RR,RI,SI,SS")
6283 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6285 (define_insn "*iorhi3_esa"
6286 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6287 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6288 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6289 (clobber (reg:CC CC_REGNUM))]
6290 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6295 [(set_attr "op_type" "RR,SI,SS")
6296 (set_attr "z10prop" "z10_super_E1,*,*")])
6299 [(set (match_operand:HI 0 "s_operand" "")
6300 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6301 (clobber (reg:CC CC_REGNUM))]
6304 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6305 (clobber (reg:CC CC_REGNUM))])]
6306 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6309 ; iorqi3 instruction pattern(s).
6312 (define_insn "*iorqi3_zarch"
6313 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6314 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6315 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
6316 (clobber (reg:CC CC_REGNUM))]
6317 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6324 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
6325 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6327 (define_insn "*iorqi3_esa"
6328 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6329 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6330 (match_operand:QI 2 "general_operand" "d,n,Q")))
6331 (clobber (reg:CC CC_REGNUM))]
6332 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6337 [(set_attr "op_type" "RR,SI,SS")
6338 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6341 ; Block inclusive or (OC) patterns.
6345 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6346 (ior:BLK (match_dup 0)
6347 (match_operand:BLK 1 "memory_operand" "Q")))
6348 (use (match_operand 2 "const_int_operand" "n"))
6349 (clobber (reg:CC CC_REGNUM))]
6350 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6351 "oc\t%O0(%2,%R0),%S1"
6352 [(set_attr "op_type" "SS")])
6355 [(set (match_operand 0 "memory_operand" "")
6357 (match_operand 1 "memory_operand" "")))
6358 (clobber (reg:CC CC_REGNUM))]
6360 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6361 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6363 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6365 (clobber (reg:CC CC_REGNUM))])]
6367 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6368 operands[0] = adjust_address (operands[0], BLKmode, 0);
6369 operands[1] = adjust_address (operands[1], BLKmode, 0);
6374 [(set (match_operand:BLK 0 "memory_operand" "")
6375 (ior:BLK (match_dup 0)
6376 (match_operand:BLK 1 "memory_operand" "")))
6377 (use (match_operand 2 "const_int_operand" ""))
6378 (clobber (reg:CC CC_REGNUM))])
6380 [(set (match_operand:BLK 3 "memory_operand" "")
6381 (ior:BLK (match_dup 3)
6382 (match_operand:BLK 4 "memory_operand" "")))
6383 (use (match_operand 5 "const_int_operand" ""))
6384 (clobber (reg:CC CC_REGNUM))])]
6385 "s390_offset_p (operands[0], operands[3], operands[2])
6386 && s390_offset_p (operands[1], operands[4], operands[2])
6387 && !s390_overlap_p (operands[0], operands[1],
6388 INTVAL (operands[2]) + INTVAL (operands[5]))
6389 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6391 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6393 (clobber (reg:CC CC_REGNUM))])]
6394 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6395 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6396 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6400 ;;- Xor instructions.
6403 (define_expand "xor<mode>3"
6404 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6405 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6406 (match_operand:INT 2 "general_operand" "")))
6407 (clobber (reg:CC CC_REGNUM))]
6409 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6412 ; xordi3 instruction pattern(s).
6415 (define_insn "*xordi3_cc"
6416 [(set (reg CC_REGNUM)
6417 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6418 (match_operand:DI 2 "general_operand" "d,RT"))
6420 (set (match_operand:DI 0 "register_operand" "=d,d")
6421 (xor:DI (match_dup 1) (match_dup 2)))]
6422 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6426 [(set_attr "op_type" "RRE,RXY")
6427 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6429 (define_insn "*xordi3_cconly"
6430 [(set (reg CC_REGNUM)
6431 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6432 (match_operand:DI 2 "general_operand" "d,RT"))
6434 (clobber (match_scratch:DI 0 "=d,d"))]
6435 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6439 [(set_attr "op_type" "RRE,RXY")
6440 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6442 (define_insn "*xordi3"
6443 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6444 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6445 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
6446 (clobber (reg:CC CC_REGNUM))]
6447 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6455 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")
6456 (set_attr "cpu_facility" "extimm,extimm,*,*,*,*")
6457 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6460 [(set (match_operand:DI 0 "s_operand" "")
6461 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6462 (clobber (reg:CC CC_REGNUM))]
6465 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6466 (clobber (reg:CC CC_REGNUM))])]
6467 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6470 ; xorsi3 instruction pattern(s).
6473 (define_insn "*xorsi3_cc"
6474 [(set (reg CC_REGNUM)
6475 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6476 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6478 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6479 (xor:SI (match_dup 1) (match_dup 2)))]
6480 "s390_match_ccmode(insn, CCTmode)"
6486 [(set_attr "op_type" "RIL,RR,RX,RXY")
6487 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6489 (define_insn "*xorsi3_cconly"
6490 [(set (reg CC_REGNUM)
6491 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6492 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6494 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6495 "s390_match_ccmode(insn, CCTmode)"
6501 [(set_attr "op_type" "RIL,RR,RX,RXY")
6502 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6504 (define_insn "*xorsi3"
6505 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6506 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6507 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
6508 (clobber (reg:CC CC_REGNUM))]
6509 "s390_logical_operator_ok_p (operands)"
6517 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")
6518 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6521 [(set (match_operand:SI 0 "s_operand" "")
6522 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6523 (clobber (reg:CC CC_REGNUM))]
6526 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6527 (clobber (reg:CC CC_REGNUM))])]
6528 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6531 ; xorhi3 instruction pattern(s).
6534 (define_insn "*xorhi3"
6535 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6536 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6537 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
6538 (clobber (reg:CC CC_REGNUM))]
6539 "s390_logical_operator_ok_p (operands)"
6545 [(set_attr "op_type" "RIL,RR,SI,SS")
6546 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6549 [(set (match_operand:HI 0 "s_operand" "")
6550 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6551 (clobber (reg:CC CC_REGNUM))]
6554 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6555 (clobber (reg:CC CC_REGNUM))])]
6556 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6559 ; xorqi3 instruction pattern(s).
6562 (define_insn "*xorqi3"
6563 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6564 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6565 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
6566 (clobber (reg:CC CC_REGNUM))]
6567 "s390_logical_operator_ok_p (operands)"
6574 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")
6575 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6579 ; Block exclusive or (XC) patterns.
6583 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6584 (xor:BLK (match_dup 0)
6585 (match_operand:BLK 1 "memory_operand" "Q")))
6586 (use (match_operand 2 "const_int_operand" "n"))
6587 (clobber (reg:CC CC_REGNUM))]
6588 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6589 "xc\t%O0(%2,%R0),%S1"
6590 [(set_attr "op_type" "SS")])
6593 [(set (match_operand 0 "memory_operand" "")
6595 (match_operand 1 "memory_operand" "")))
6596 (clobber (reg:CC CC_REGNUM))]
6598 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6599 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6601 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6603 (clobber (reg:CC CC_REGNUM))])]
6605 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6606 operands[0] = adjust_address (operands[0], BLKmode, 0);
6607 operands[1] = adjust_address (operands[1], BLKmode, 0);
6612 [(set (match_operand:BLK 0 "memory_operand" "")
6613 (xor:BLK (match_dup 0)
6614 (match_operand:BLK 1 "memory_operand" "")))
6615 (use (match_operand 2 "const_int_operand" ""))
6616 (clobber (reg:CC CC_REGNUM))])
6618 [(set (match_operand:BLK 3 "memory_operand" "")
6619 (xor:BLK (match_dup 3)
6620 (match_operand:BLK 4 "memory_operand" "")))
6621 (use (match_operand 5 "const_int_operand" ""))
6622 (clobber (reg:CC CC_REGNUM))])]
6623 "s390_offset_p (operands[0], operands[3], operands[2])
6624 && s390_offset_p (operands[1], operands[4], operands[2])
6625 && !s390_overlap_p (operands[0], operands[1],
6626 INTVAL (operands[2]) + INTVAL (operands[5]))
6627 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6629 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6631 (clobber (reg:CC CC_REGNUM))])]
6632 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6633 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6634 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6637 ; Block xor (XC) patterns with src == dest.
6640 (define_insn "*xc_zero"
6641 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6643 (use (match_operand 1 "const_int_operand" "n"))
6644 (clobber (reg:CC CC_REGNUM))]
6645 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6646 "xc\t%O0(%1,%R0),%S0"
6647 [(set_attr "op_type" "SS")])
6651 [(set (match_operand:BLK 0 "memory_operand" "")
6653 (use (match_operand 1 "const_int_operand" ""))
6654 (clobber (reg:CC CC_REGNUM))])
6656 [(set (match_operand:BLK 2 "memory_operand" "")
6658 (use (match_operand 3 "const_int_operand" ""))
6659 (clobber (reg:CC CC_REGNUM))])]
6660 "s390_offset_p (operands[0], operands[2], operands[1])
6661 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6663 [(set (match_dup 4) (const_int 0))
6665 (clobber (reg:CC CC_REGNUM))])]
6666 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6667 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6671 ;;- Negate instructions.
6675 ; neg(di|si)2 instruction pattern(s).
6678 (define_expand "neg<mode>2"
6680 [(set (match_operand:DSI 0 "register_operand" "=d")
6681 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
6682 (clobber (reg:CC CC_REGNUM))])]
6686 (define_insn "*negdi2_sign_cc"
6687 [(set (reg CC_REGNUM)
6688 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6689 (match_operand:SI 1 "register_operand" "d") 0)
6690 (const_int 32)) (const_int 32)))
6692 (set (match_operand:DI 0 "register_operand" "=d")
6693 (neg:DI (sign_extend:DI (match_dup 1))))]
6694 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6696 [(set_attr "op_type" "RRE")
6697 (set_attr "z10prop" "z10_c")])
6699 (define_insn "*negdi2_sign"
6700 [(set (match_operand:DI 0 "register_operand" "=d")
6701 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6702 (clobber (reg:CC CC_REGNUM))]
6705 [(set_attr "op_type" "RRE")
6706 (set_attr "z10prop" "z10_c")])
6709 (define_insn "*neg<mode>2_cc"
6710 [(set (reg CC_REGNUM)
6711 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6713 (set (match_operand:GPR 0 "register_operand" "=d")
6714 (neg:GPR (match_dup 1)))]
6715 "s390_match_ccmode (insn, CCAmode)"
6717 [(set_attr "op_type" "RR<E>")
6718 (set_attr "z10prop" "z10_super_c_E1")])
6721 (define_insn "*neg<mode>2_cconly"
6722 [(set (reg CC_REGNUM)
6723 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6725 (clobber (match_scratch:GPR 0 "=d"))]
6726 "s390_match_ccmode (insn, CCAmode)"
6728 [(set_attr "op_type" "RR<E>")
6729 (set_attr "z10prop" "z10_super_c_E1")])
6732 (define_insn "*neg<mode>2"
6733 [(set (match_operand:GPR 0 "register_operand" "=d")
6734 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
6735 (clobber (reg:CC CC_REGNUM))]
6738 [(set_attr "op_type" "RR<E>")
6739 (set_attr "z10prop" "z10_super_c_E1")])
6741 (define_insn_and_split "*negdi2_31"
6742 [(set (match_operand:DI 0 "register_operand" "=d")
6743 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6744 (clobber (reg:CC CC_REGNUM))]
6747 "&& reload_completed"
6749 [(set (match_dup 2) (neg:SI (match_dup 3)))
6750 (clobber (reg:CC CC_REGNUM))])
6752 [(set (reg:CCAP CC_REGNUM)
6753 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
6754 (set (match_dup 4) (neg:SI (match_dup 5)))])
6756 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
6758 (label_ref (match_dup 6))))
6760 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6761 (clobber (reg:CC CC_REGNUM))])
6763 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6764 operands[3] = operand_subword (operands[1], 0, 0, DImode);
6765 operands[4] = operand_subword (operands[0], 1, 0, DImode);
6766 operands[5] = operand_subword (operands[1], 1, 0, DImode);
6767 operands[6] = gen_label_rtx ();")
6770 ; neg(df|sf)2 instruction pattern(s).
6773 (define_expand "neg<mode>2"
6775 [(set (match_operand:BFP 0 "register_operand" "=f")
6776 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6777 (clobber (reg:CC CC_REGNUM))])]
6781 ; lcxbr, lcdbr, lcebr
6782 (define_insn "*neg<mode>2_cc"
6783 [(set (reg CC_REGNUM)
6784 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6785 (match_operand:BFP 2 "const0_operand" "")))
6786 (set (match_operand:BFP 0 "register_operand" "=f")
6787 (neg:BFP (match_dup 1)))]
6788 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6790 [(set_attr "op_type" "RRE")
6791 (set_attr "type" "fsimp<mode>")])
6793 ; lcxbr, lcdbr, lcebr
6794 (define_insn "*neg<mode>2_cconly"
6795 [(set (reg CC_REGNUM)
6796 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6797 (match_operand:BFP 2 "const0_operand" "")))
6798 (clobber (match_scratch:BFP 0 "=f"))]
6799 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6801 [(set_attr "op_type" "RRE")
6802 (set_attr "type" "fsimp<mode>")])
6805 (define_insn "*neg<mode>2_nocc"
6806 [(set (match_operand:FP 0 "register_operand" "=f")
6807 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6810 [(set_attr "op_type" "RRE")
6811 (set_attr "type" "fsimp<mode>")])
6813 ; lcxbr, lcdbr, lcebr
6814 (define_insn "*neg<mode>2"
6815 [(set (match_operand:BFP 0 "register_operand" "=f")
6816 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6817 (clobber (reg:CC CC_REGNUM))]
6820 [(set_attr "op_type" "RRE")
6821 (set_attr "type" "fsimp<mode>")])
6825 ;;- Absolute value instructions.
6829 ; abs(di|si)2 instruction pattern(s).
6832 (define_insn "*absdi2_sign_cc"
6833 [(set (reg CC_REGNUM)
6834 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6835 (match_operand:SI 1 "register_operand" "d") 0)
6836 (const_int 32)) (const_int 32)))
6838 (set (match_operand:DI 0 "register_operand" "=d")
6839 (abs:DI (sign_extend:DI (match_dup 1))))]
6840 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6842 [(set_attr "op_type" "RRE")
6843 (set_attr "z10prop" "z10_c")])
6845 (define_insn "*absdi2_sign"
6846 [(set (match_operand:DI 0 "register_operand" "=d")
6847 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6848 (clobber (reg:CC CC_REGNUM))]
6851 [(set_attr "op_type" "RRE")
6852 (set_attr "z10prop" "z10_c")])
6855 (define_insn "*abs<mode>2_cc"
6856 [(set (reg CC_REGNUM)
6857 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6859 (set (match_operand:GPR 0 "register_operand" "=d")
6860 (abs:GPR (match_dup 1)))]
6861 "s390_match_ccmode (insn, CCAmode)"
6863 [(set_attr "op_type" "RR<E>")
6864 (set_attr "z10prop" "z10_c")])
6867 (define_insn "*abs<mode>2_cconly"
6868 [(set (reg CC_REGNUM)
6869 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6871 (clobber (match_scratch:GPR 0 "=d"))]
6872 "s390_match_ccmode (insn, CCAmode)"
6874 [(set_attr "op_type" "RR<E>")
6875 (set_attr "z10prop" "z10_c")])
6878 (define_insn "abs<mode>2"
6879 [(set (match_operand:GPR 0 "register_operand" "=d")
6880 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6881 (clobber (reg:CC CC_REGNUM))]
6884 [(set_attr "op_type" "RR<E>")
6885 (set_attr "z10prop" "z10_c")])
6888 ; abs(df|sf)2 instruction pattern(s).
6891 (define_expand "abs<mode>2"
6893 [(set (match_operand:BFP 0 "register_operand" "=f")
6894 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6895 (clobber (reg:CC CC_REGNUM))])]
6899 ; lpxbr, lpdbr, lpebr
6900 (define_insn "*abs<mode>2_cc"
6901 [(set (reg CC_REGNUM)
6902 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6903 (match_operand:BFP 2 "const0_operand" "")))
6904 (set (match_operand:BFP 0 "register_operand" "=f")
6905 (abs:BFP (match_dup 1)))]
6906 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6908 [(set_attr "op_type" "RRE")
6909 (set_attr "type" "fsimp<mode>")])
6911 ; lpxbr, lpdbr, lpebr
6912 (define_insn "*abs<mode>2_cconly"
6913 [(set (reg CC_REGNUM)
6914 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6915 (match_operand:BFP 2 "const0_operand" "")))
6916 (clobber (match_scratch:BFP 0 "=f"))]
6917 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6919 [(set_attr "op_type" "RRE")
6920 (set_attr "type" "fsimp<mode>")])
6923 (define_insn "*abs<mode>2_nocc"
6924 [(set (match_operand:FP 0 "register_operand" "=f")
6925 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6928 [(set_attr "op_type" "RRE")
6929 (set_attr "type" "fsimp<mode>")])
6931 ; lpxbr, lpdbr, lpebr
6932 (define_insn "*abs<mode>2"
6933 [(set (match_operand:BFP 0 "register_operand" "=f")
6934 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6935 (clobber (reg:CC CC_REGNUM))]
6938 [(set_attr "op_type" "RRE")
6939 (set_attr "type" "fsimp<mode>")])
6943 ;;- Negated absolute value instructions
6950 (define_insn "*negabsdi2_sign_cc"
6951 [(set (reg CC_REGNUM)
6952 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6953 (match_operand:SI 1 "register_operand" "d") 0)
6954 (const_int 32)) (const_int 32))))
6956 (set (match_operand:DI 0 "register_operand" "=d")
6957 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6958 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
6960 [(set_attr "op_type" "RRE")
6961 (set_attr "z10prop" "z10_c")])
6963 (define_insn "*negabsdi2_sign"
6964 [(set (match_operand:DI 0 "register_operand" "=d")
6965 (neg:DI (abs:DI (sign_extend:DI
6966 (match_operand:SI 1 "register_operand" "d")))))
6967 (clobber (reg:CC CC_REGNUM))]
6970 [(set_attr "op_type" "RRE")
6971 (set_attr "z10prop" "z10_c")])
6974 (define_insn "*negabs<mode>2_cc"
6975 [(set (reg CC_REGNUM)
6976 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6978 (set (match_operand:GPR 0 "register_operand" "=d")
6979 (neg:GPR (abs:GPR (match_dup 1))))]
6980 "s390_match_ccmode (insn, CCAmode)"
6982 [(set_attr "op_type" "RR<E>")
6983 (set_attr "z10prop" "z10_c")])
6986 (define_insn "*negabs<mode>2_cconly"
6987 [(set (reg CC_REGNUM)
6988 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6990 (clobber (match_scratch:GPR 0 "=d"))]
6991 "s390_match_ccmode (insn, CCAmode)"
6993 [(set_attr "op_type" "RR<E>")
6994 (set_attr "z10prop" "z10_c")])
6997 (define_insn "*negabs<mode>2"
6998 [(set (match_operand:GPR 0 "register_operand" "=d")
6999 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7000 (clobber (reg:CC CC_REGNUM))]
7003 [(set_attr "op_type" "RR<E>")
7004 (set_attr "z10prop" "z10_c")])
7010 ; lnxbr, lndbr, lnebr
7011 (define_insn "*negabs<mode>2_cc"
7012 [(set (reg CC_REGNUM)
7013 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7014 (match_operand:BFP 2 "const0_operand" "")))
7015 (set (match_operand:BFP 0 "register_operand" "=f")
7016 (neg:BFP (abs:BFP (match_dup 1))))]
7017 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7019 [(set_attr "op_type" "RRE")
7020 (set_attr "type" "fsimp<mode>")])
7022 ; lnxbr, lndbr, lnebr
7023 (define_insn "*negabs<mode>2_cconly"
7024 [(set (reg CC_REGNUM)
7025 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7026 (match_operand:BFP 2 "const0_operand" "")))
7027 (clobber (match_scratch:BFP 0 "=f"))]
7028 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7030 [(set_attr "op_type" "RRE")
7031 (set_attr "type" "fsimp<mode>")])
7034 (define_insn "*negabs<mode>2_nocc"
7035 [(set (match_operand:FP 0 "register_operand" "=f")
7036 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7039 [(set_attr "op_type" "RRE")
7040 (set_attr "type" "fsimp<mode>")])
7042 ; lnxbr, lndbr, lnebr
7043 (define_insn "*negabs<mode>2"
7044 [(set (match_operand:BFP 0 "register_operand" "=f")
7045 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7046 (clobber (reg:CC CC_REGNUM))]
7049 [(set_attr "op_type" "RRE")
7050 (set_attr "type" "fsimp<mode>")])
7053 ;;- Square root instructions.
7057 ; sqrt(df|sf)2 instruction pattern(s).
7060 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7061 (define_insn "sqrt<mode>2"
7062 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7063 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7068 [(set_attr "op_type" "RRE,RXE")
7069 (set_attr "type" "fsqrt<mode>")])
7073 ;;- One complement instructions.
7077 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7080 (define_expand "one_cmpl<mode>2"
7082 [(set (match_operand:INT 0 "register_operand" "")
7083 (xor:INT (match_operand:INT 1 "register_operand" "")
7085 (clobber (reg:CC CC_REGNUM))])]
7091 ;; Find leftmost bit instructions.
7094 (define_expand "clzdi2"
7095 [(set (match_operand:DI 0 "register_operand" "=d")
7096 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7097 "TARGET_EXTIMM && TARGET_ZARCH"
7099 rtx insn, clz_equal;
7100 rtx wide_reg = gen_reg_rtx (TImode);
7101 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7103 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7105 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7107 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7108 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7113 (define_insn "clztidi2"
7114 [(set (match_operand:TI 0 "register_operand" "=d")
7118 (xor:DI (match_operand:DI 1 "register_operand" "d")
7119 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7120 (subreg:SI (clz:DI (match_dup 1)) 4))))
7123 (zero_extend:TI (clz:DI (match_dup 1)))))
7124 (clobber (reg:CC CC_REGNUM))]
7125 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7126 == (unsigned HOST_WIDE_INT) 1 << 63
7127 && TARGET_EXTIMM && TARGET_ZARCH"
7129 [(set_attr "op_type" "RRE")])
7133 ;;- Rotate instructions.
7137 ; rotl(di|si)3 instruction pattern(s).
7141 (define_insn "rotl<mode>3"
7142 [(set (match_operand:GPR 0 "register_operand" "=d")
7143 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7144 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7147 [(set_attr "op_type" "RSE")
7148 (set_attr "atype" "reg")
7149 (set_attr "z10prop" "z10_super_E1")])
7152 (define_insn "*rotl<mode>3_and"
7153 [(set (match_operand:GPR 0 "register_operand" "=d")
7154 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7155 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7156 (match_operand:SI 3 "const_int_operand" "n"))))]
7157 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7159 [(set_attr "op_type" "RSE")
7160 (set_attr "atype" "reg")
7161 (set_attr "z10prop" "z10_super_E1")])
7165 ;;- Shift instructions.
7169 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7172 (define_expand "<shift><mode>3"
7173 [(set (match_operand:DSI 0 "register_operand" "")
7174 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7175 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7180 (define_insn "*<shift>di3_31"
7181 [(set (match_operand:DI 0 "register_operand" "=d")
7182 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7183 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7186 [(set_attr "op_type" "RS")
7187 (set_attr "atype" "reg")])
7189 ; sll, srl, sllg, srlg
7190 (define_insn "*<shift><mode>3"
7191 [(set (match_operand:GPR 0 "register_operand" "=d")
7192 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7193 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7195 "s<lr>l<g>\t%0,<1>%Y2"
7196 [(set_attr "op_type" "RS<E>")
7197 (set_attr "atype" "reg")
7198 (set_attr "z10prop" "z10_super_E1")])
7201 (define_insn "*<shift>di3_31_and"
7202 [(set (match_operand:DI 0 "register_operand" "=d")
7203 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7204 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7205 (match_operand:SI 3 "const_int_operand" "n"))))]
7206 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7208 [(set_attr "op_type" "RS")
7209 (set_attr "atype" "reg")])
7211 ; sll, srl, sllg, srlg
7212 (define_insn "*<shift><mode>3_and"
7213 [(set (match_operand:GPR 0 "register_operand" "=d")
7214 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7215 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7216 (match_operand:SI 3 "const_int_operand" "n"))))]
7217 "(INTVAL (operands[3]) & 63) == 63"
7218 "s<lr>l<g>\t%0,<1>%Y2"
7219 [(set_attr "op_type" "RS<E>")
7220 (set_attr "atype" "reg")
7221 (set_attr "z10prop" "z10_super_E1")])
7224 ; ashr(di|si)3 instruction pattern(s).
7227 (define_expand "ashr<mode>3"
7229 [(set (match_operand:DSI 0 "register_operand" "")
7230 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7231 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7232 (clobber (reg:CC CC_REGNUM))])]
7236 (define_insn "*ashrdi3_cc_31"
7237 [(set (reg CC_REGNUM)
7238 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7239 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7241 (set (match_operand:DI 0 "register_operand" "=d")
7242 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7243 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7245 [(set_attr "op_type" "RS")
7246 (set_attr "atype" "reg")])
7248 (define_insn "*ashrdi3_cconly_31"
7249 [(set (reg CC_REGNUM)
7250 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7251 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7253 (clobber (match_scratch:DI 0 "=d"))]
7254 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7256 [(set_attr "op_type" "RS")
7257 (set_attr "atype" "reg")])
7259 (define_insn "*ashrdi3_31"
7260 [(set (match_operand:DI 0 "register_operand" "=d")
7261 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7262 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7263 (clobber (reg:CC CC_REGNUM))]
7266 [(set_attr "op_type" "RS")
7267 (set_attr "atype" "reg")])
7270 (define_insn "*ashr<mode>3_cc"
7271 [(set (reg CC_REGNUM)
7272 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7273 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7275 (set (match_operand:GPR 0 "register_operand" "=d")
7276 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7277 "s390_match_ccmode(insn, CCSmode)"
7279 [(set_attr "op_type" "RS<E>")
7280 (set_attr "atype" "reg")
7281 (set_attr "z10prop" "z10_super_E1")])
7284 (define_insn "*ashr<mode>3_cconly"
7285 [(set (reg CC_REGNUM)
7286 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7287 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7289 (clobber (match_scratch:GPR 0 "=d"))]
7290 "s390_match_ccmode(insn, CCSmode)"
7292 [(set_attr "op_type" "RS<E>")
7293 (set_attr "atype" "reg")
7294 (set_attr "z10prop" "z10_super_E1")])
7297 (define_insn "*ashr<mode>3"
7298 [(set (match_operand:GPR 0 "register_operand" "=d")
7299 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7300 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7301 (clobber (reg:CC CC_REGNUM))]
7304 [(set_attr "op_type" "RS<E>")
7305 (set_attr "atype" "reg")
7306 (set_attr "z10prop" "z10_super_E1")])
7309 ; shift pattern with implicit ANDs
7311 (define_insn "*ashrdi3_cc_31_and"
7312 [(set (reg CC_REGNUM)
7313 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7314 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7315 (match_operand:SI 3 "const_int_operand" "n")))
7317 (set (match_operand:DI 0 "register_operand" "=d")
7318 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7319 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7320 && (INTVAL (operands[3]) & 63) == 63"
7322 [(set_attr "op_type" "RS")
7323 (set_attr "atype" "reg")])
7325 (define_insn "*ashrdi3_cconly_31_and"
7326 [(set (reg CC_REGNUM)
7327 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7328 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7329 (match_operand:SI 3 "const_int_operand" "n")))
7331 (clobber (match_scratch:DI 0 "=d"))]
7332 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7333 && (INTVAL (operands[3]) & 63) == 63"
7335 [(set_attr "op_type" "RS")
7336 (set_attr "atype" "reg")])
7338 (define_insn "*ashrdi3_31_and"
7339 [(set (match_operand:DI 0 "register_operand" "=d")
7340 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7341 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7342 (match_operand:SI 3 "const_int_operand" "n"))))
7343 (clobber (reg:CC CC_REGNUM))]
7344 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7346 [(set_attr "op_type" "RS")
7347 (set_attr "atype" "reg")])
7350 (define_insn "*ashr<mode>3_cc_and"
7351 [(set (reg CC_REGNUM)
7352 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7353 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7354 (match_operand:SI 3 "const_int_operand" "n")))
7356 (set (match_operand:GPR 0 "register_operand" "=d")
7357 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7358 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7360 [(set_attr "op_type" "RS<E>")
7361 (set_attr "atype" "reg")
7362 (set_attr "z10prop" "z10_super_E1")])
7365 (define_insn "*ashr<mode>3_cconly_and"
7366 [(set (reg CC_REGNUM)
7367 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7368 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7369 (match_operand:SI 3 "const_int_operand" "n")))
7371 (clobber (match_scratch:GPR 0 "=d"))]
7372 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7374 [(set_attr "op_type" "RS<E>")
7375 (set_attr "atype" "reg")
7376 (set_attr "z10prop" "z10_super_E1")])
7379 (define_insn "*ashr<mode>3_and"
7380 [(set (match_operand:GPR 0 "register_operand" "=d")
7381 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7382 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7383 (match_operand:SI 3 "const_int_operand" "n"))))
7384 (clobber (reg:CC CC_REGNUM))]
7385 "(INTVAL (operands[3]) & 63) == 63"
7387 [(set_attr "op_type" "RS<E>")
7388 (set_attr "atype" "reg")
7389 (set_attr "z10prop" "z10_super_E1")])
7393 ;; Branch instruction patterns.
7396 (define_expand "cbranch<mode>4"
7398 (if_then_else (match_operator 0 "comparison_operator"
7399 [(match_operand:GPR 1 "register_operand" "")
7400 (match_operand:GPR 2 "general_operand" "")])
7401 (label_ref (match_operand 3 "" ""))
7404 "s390_emit_jump (operands[3],
7405 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7408 (define_expand "cbranch<mode>4"
7410 (if_then_else (match_operator 0 "comparison_operator"
7411 [(match_operand:FP 1 "register_operand" "")
7412 (match_operand:FP 2 "general_operand" "")])
7413 (label_ref (match_operand 3 "" ""))
7416 "s390_emit_jump (operands[3],
7417 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7420 (define_expand "cbranchcc4"
7422 (if_then_else (match_operator 0 "s390_eqne_operator"
7423 [(match_operand 1 "cc_reg_operand" "")
7424 (match_operand 2 "const0_operand" "")])
7425 (label_ref (match_operand 3 "" ""))
7428 "s390_emit_jump (operands[3],
7429 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7435 ;;- Conditional jump instructions.
7438 (define_insn "*cjump_64"
7441 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7442 (label_ref (match_operand 0 "" ""))
7446 if (get_attr_length (insn) == 4)
7449 return "jg%C1\t%l0";
7451 [(set_attr "op_type" "RI")
7452 (set_attr "type" "branch")
7453 (set (attr "length")
7454 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7455 (const_int 4) (const_int 6)))])
7457 (define_insn "*cjump_31"
7460 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7461 (label_ref (match_operand 0 "" ""))
7465 gcc_assert (get_attr_length (insn) == 4);
7468 [(set_attr "op_type" "RI")
7469 (set_attr "type" "branch")
7470 (set (attr "length")
7471 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7472 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7473 (const_int 4) (const_int 6))
7474 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7475 (const_int 4) (const_int 8))))])
7477 (define_insn "*cjump_long"
7480 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7481 (match_operand 0 "address_operand" "ZQZR")
7485 if (get_attr_op_type (insn) == OP_TYPE_RR)
7490 [(set (attr "op_type")
7491 (if_then_else (match_operand 0 "register_operand" "")
7492 (const_string "RR") (const_string "RX")))
7493 (set_attr "type" "branch")
7494 (set_attr "atype" "agen")])
7498 ;;- Negated conditional jump instructions.
7501 (define_insn "*icjump_64"
7504 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7506 (label_ref (match_operand 0 "" ""))))]
7509 if (get_attr_length (insn) == 4)
7512 return "jg%D1\t%l0";
7514 [(set_attr "op_type" "RI")
7515 (set_attr "type" "branch")
7516 (set (attr "length")
7517 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7518 (const_int 4) (const_int 6)))])
7520 (define_insn "*icjump_31"
7523 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7525 (label_ref (match_operand 0 "" ""))))]
7528 gcc_assert (get_attr_length (insn) == 4);
7531 [(set_attr "op_type" "RI")
7532 (set_attr "type" "branch")
7533 (set (attr "length")
7534 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7535 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7536 (const_int 4) (const_int 6))
7537 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7538 (const_int 4) (const_int 8))))])
7540 (define_insn "*icjump_long"
7543 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7545 (match_operand 0 "address_operand" "ZQZR")))]
7548 if (get_attr_op_type (insn) == OP_TYPE_RR)
7553 [(set (attr "op_type")
7554 (if_then_else (match_operand 0 "register_operand" "")
7555 (const_string "RR") (const_string "RX")))
7556 (set_attr "type" "branch")
7557 (set_attr "atype" "agen")])
7560 ;;- Trap instructions.
7564 [(trap_if (const_int 1) (const_int 0))]
7567 [(set_attr "op_type" "RI")
7568 (set_attr "type" "branch")])
7570 (define_expand "ctrap<mode>4"
7571 [(trap_if (match_operator 0 "comparison_operator"
7572 [(match_operand:GPR 1 "register_operand" "")
7573 (match_operand:GPR 2 "general_operand" "")])
7574 (match_operand 3 "const0_operand" ""))]
7577 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7578 operands[1], operands[2]);
7579 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7583 (define_expand "ctrap<mode>4"
7584 [(trap_if (match_operator 0 "comparison_operator"
7585 [(match_operand:FP 1 "register_operand" "")
7586 (match_operand:FP 2 "general_operand" "")])
7587 (match_operand 3 "const0_operand" ""))]
7590 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7591 operands[1], operands[2]);
7592 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7596 (define_insn "condtrap"
7597 [(trap_if (match_operator 0 "s390_comparison"
7598 [(match_operand 1 "cc_reg_operand" "c")
7603 [(set_attr "op_type" "RI")
7604 (set_attr "type" "branch")])
7606 ; crt, cgrt, cit, cgit
7607 (define_insn "*cmp_and_trap_signed_int<mode>"
7608 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
7609 [(match_operand:GPR 1 "register_operand" "d,d")
7610 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
7616 [(set_attr "op_type" "RRF,RIE")
7617 (set_attr "type" "branch")
7618 (set_attr "z10prop" "z10_super_c,z10_super")])
7620 ; clrt, clgrt, clfit, clgit
7621 (define_insn "*cmp_and_trap_unsigned_int<mode>"
7622 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
7623 [(match_operand:GPR 1 "register_operand" "d,d")
7624 (match_operand:GPR 2 "nonmemory_operand" "d,D")])
7629 cl<gf>it%C0\t%1,%x2"
7630 [(set_attr "op_type" "RRF,RIE")
7631 (set_attr "type" "branch")
7632 (set_attr "z10prop" "z10_super_c,z10_super")])
7635 ;;- Loop instructions.
7637 ;; This is all complicated by the fact that since this is a jump insn
7638 ;; we must handle our own output reloads.
7642 ; This splitter will be matched by combine and has to add the 2 moves
7643 ; necessary to load the compare and the increment values into a
7644 ; register pair as needed by brxle.
7646 (define_insn_and_split "*brx_stage1_<GPR:mode>"
7649 (match_operator 6 "s390_brx_operator"
7650 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
7651 (match_operand:GPR 2 "general_operand" ""))
7652 (match_operand:GPR 3 "register_operand" "")])
7653 (label_ref (match_operand 0 "" ""))
7655 (set (match_operand:GPR 4 "nonimmediate_operand" "")
7656 (plus:GPR (match_dup 1) (match_dup 2)))
7657 (clobber (match_scratch:GPR 5 ""))]
7660 "!reload_completed && !reload_in_progress"
7661 [(set (match_dup 7) (match_dup 2)) ; the increment
7662 (set (match_dup 8) (match_dup 3)) ; the comparison value
7663 (parallel [(set (pc)
7666 [(plus:GPR (match_dup 1) (match_dup 7))
7668 (label_ref (match_dup 0))
7671 (plus:GPR (match_dup 1) (match_dup 7)))
7672 (clobber (match_dup 5))
7673 (clobber (reg:CC CC_REGNUM))])]
7675 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
7676 operands[7] = gen_lowpart (<GPR:MODE>mode,
7677 gen_highpart (word_mode, dreg));
7678 operands[8] = gen_lowpart (<GPR:MODE>mode,
7679 gen_lowpart (word_mode, dreg));
7684 (define_insn_and_split "*brxg_64bit"
7687 (match_operator 5 "s390_brx_operator"
7688 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
7689 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
7690 (subreg:DI (match_dup 2) 8)])
7691 (label_ref (match_operand 0 "" ""))
7693 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
7694 (plus:DI (match_dup 1)
7695 (subreg:DI (match_dup 2) 0)))
7696 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
7697 (clobber (reg:CC CC_REGNUM))]
7700 if (which_alternative != 0)
7702 else if (get_attr_length (insn) == 6)
7703 return "brx%E5g\t%1,%2,%l0";
7705 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
7707 "&& reload_completed
7708 && (!REG_P (operands[3])
7709 || !rtx_equal_p (operands[1], operands[3]))"
7710 [(set (match_dup 4) (match_dup 1))
7711 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
7712 (clobber (reg:CC CC_REGNUM))])
7713 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
7714 (set (match_dup 3) (match_dup 4))
7715 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
7716 (label_ref (match_dup 0))
7719 [(set_attr "op_type" "RIE")
7720 (set_attr "type" "branch")
7721 (set (attr "length")
7722 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7723 (const_int 6) (const_int 16)))])
7727 (define_insn_and_split "*brx_64bit"
7730 (match_operator 5 "s390_brx_operator"
7731 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
7732 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
7733 (subreg:SI (match_dup 2) 12)])
7734 (label_ref (match_operand 0 "" ""))
7736 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
7737 (plus:SI (match_dup 1)
7738 (subreg:SI (match_dup 2) 4)))
7739 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
7740 (clobber (reg:CC CC_REGNUM))]
7743 if (which_alternative != 0)
7745 else if (get_attr_length (insn) == 6)
7746 return "brx%C5\t%1,%2,%l0";
7748 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
7750 "&& reload_completed
7751 && (!REG_P (operands[3])
7752 || !rtx_equal_p (operands[1], operands[3]))"
7753 [(set (match_dup 4) (match_dup 1))
7754 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
7755 (clobber (reg:CC CC_REGNUM))])
7756 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
7757 (set (match_dup 3) (match_dup 4))
7758 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
7759 (label_ref (match_dup 0))
7762 [(set_attr "op_type" "RSI")
7763 (set_attr "type" "branch")
7764 (set (attr "length")
7765 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7766 (const_int 6) (const_int 14)))])
7770 (define_insn_and_split "*brx_31bit"
7773 (match_operator 5 "s390_brx_operator"
7774 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
7775 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
7776 (subreg:SI (match_dup 2) 4)])
7777 (label_ref (match_operand 0 "" ""))
7779 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
7780 (plus:SI (match_dup 1)
7781 (subreg:SI (match_dup 2) 0)))
7782 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
7783 (clobber (reg:CC CC_REGNUM))]
7784 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
7786 if (which_alternative != 0)
7788 else if (get_attr_length (insn) == 6)
7789 return "brx%C5\t%1,%2,%l0";
7791 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
7793 "&& reload_completed
7794 && (!REG_P (operands[3])
7795 || !rtx_equal_p (operands[1], operands[3]))"
7796 [(set (match_dup 4) (match_dup 1))
7797 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
7798 (clobber (reg:CC CC_REGNUM))])
7799 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
7800 (set (match_dup 3) (match_dup 4))
7801 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
7802 (label_ref (match_dup 0))
7805 [(set_attr "op_type" "RSI")
7806 (set_attr "type" "branch")
7807 (set (attr "length")
7808 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7809 (const_int 6) (const_int 14)))])
7814 (define_expand "doloop_end"
7815 [(use (match_operand 0 "" "")) ; loop pseudo
7816 (use (match_operand 1 "" "")) ; iterations; zero if unknown
7817 (use (match_operand 2 "" "")) ; max iterations
7818 (use (match_operand 3 "" "")) ; loop level
7819 (use (match_operand 4 "" ""))] ; label
7822 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
7823 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
7824 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
7825 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
7826 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
7827 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
7834 (define_insn_and_split "doloop_si64"
7837 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7839 (label_ref (match_operand 0 "" ""))
7841 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7842 (plus:SI (match_dup 1) (const_int -1)))
7843 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7844 (clobber (reg:CC CC_REGNUM))]
7847 if (which_alternative != 0)
7849 else if (get_attr_length (insn) == 4)
7850 return "brct\t%1,%l0";
7852 return "ahi\t%1,-1\;jgne\t%l0";
7854 "&& reload_completed
7855 && (! REG_P (operands[2])
7856 || ! rtx_equal_p (operands[1], operands[2]))"
7857 [(set (match_dup 3) (match_dup 1))
7858 (parallel [(set (reg:CCAN CC_REGNUM)
7859 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7861 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7862 (set (match_dup 2) (match_dup 3))
7863 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7864 (label_ref (match_dup 0))
7867 [(set_attr "op_type" "RI")
7868 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7869 ; hurt us in the (rare) case of ahi.
7870 (set_attr "z10prop" "z10_super_E1")
7871 (set_attr "type" "branch")
7872 (set (attr "length")
7873 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7874 (const_int 4) (const_int 10)))])
7876 (define_insn_and_split "doloop_si31"
7879 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7881 (label_ref (match_operand 0 "" ""))
7883 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7884 (plus:SI (match_dup 1) (const_int -1)))
7885 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7886 (clobber (reg:CC CC_REGNUM))]
7889 if (which_alternative != 0)
7891 else if (get_attr_length (insn) == 4)
7892 return "brct\t%1,%l0";
7896 "&& reload_completed
7897 && (! REG_P (operands[2])
7898 || ! rtx_equal_p (operands[1], operands[2]))"
7899 [(set (match_dup 3) (match_dup 1))
7900 (parallel [(set (reg:CCAN CC_REGNUM)
7901 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7903 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7904 (set (match_dup 2) (match_dup 3))
7905 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7906 (label_ref (match_dup 0))
7909 [(set_attr "op_type" "RI")
7910 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7911 ; hurt us in the (rare) case of ahi.
7912 (set_attr "z10prop" "z10_super_E1")
7913 (set_attr "type" "branch")
7914 (set (attr "length")
7915 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7916 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7917 (const_int 4) (const_int 6))
7918 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7919 (const_int 4) (const_int 8))))])
7921 (define_insn "*doloop_si_long"
7924 (ne (match_operand:SI 1 "register_operand" "d")
7926 (match_operand 0 "address_operand" "ZQZR")
7928 (set (match_operand:SI 2 "register_operand" "=1")
7929 (plus:SI (match_dup 1) (const_int -1)))
7930 (clobber (match_scratch:SI 3 "=X"))
7931 (clobber (reg:CC CC_REGNUM))]
7934 if (get_attr_op_type (insn) == OP_TYPE_RR)
7935 return "bctr\t%1,%0";
7937 return "bct\t%1,%a0";
7939 [(set (attr "op_type")
7940 (if_then_else (match_operand 0 "register_operand" "")
7941 (const_string "RR") (const_string "RX")))
7942 (set_attr "type" "branch")
7943 (set_attr "atype" "agen")
7944 (set_attr "z10prop" "z10_c")])
7946 (define_insn_and_split "doloop_di"
7949 (ne (match_operand:DI 1 "register_operand" "d,d,d")
7951 (label_ref (match_operand 0 "" ""))
7953 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
7954 (plus:DI (match_dup 1) (const_int -1)))
7955 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
7956 (clobber (reg:CC CC_REGNUM))]
7959 if (which_alternative != 0)
7961 else if (get_attr_length (insn) == 4)
7962 return "brctg\t%1,%l0";
7964 return "aghi\t%1,-1\;jgne\t%l0";
7966 "&& reload_completed
7967 && (! REG_P (operands[2])
7968 || ! rtx_equal_p (operands[1], operands[2]))"
7969 [(set (match_dup 3) (match_dup 1))
7970 (parallel [(set (reg:CCAN CC_REGNUM)
7971 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
7973 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
7974 (set (match_dup 2) (match_dup 3))
7975 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7976 (label_ref (match_dup 0))
7979 [(set_attr "op_type" "RI")
7980 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7981 ; hurt us in the (rare) case of ahi.
7982 (set_attr "z10prop" "z10_super_E1")
7983 (set_attr "type" "branch")
7984 (set (attr "length")
7985 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7986 (const_int 4) (const_int 10)))])
7989 ;;- Unconditional jump instructions.
7993 ; jump instruction pattern(s).
7996 (define_expand "jump"
7997 [(match_operand 0 "" "")]
7999 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8001 (define_insn "*jump64"
8002 [(set (pc) (label_ref (match_operand 0 "" "")))]
8005 if (get_attr_length (insn) == 4)
8010 [(set_attr "op_type" "RI")
8011 (set_attr "type" "branch")
8012 (set (attr "length")
8013 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8014 (const_int 4) (const_int 6)))])
8016 (define_insn "*jump31"
8017 [(set (pc) (label_ref (match_operand 0 "" "")))]
8020 gcc_assert (get_attr_length (insn) == 4);
8023 [(set_attr "op_type" "RI")
8024 (set_attr "type" "branch")
8025 (set (attr "length")
8026 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
8027 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8028 (const_int 4) (const_int 6))
8029 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8030 (const_int 4) (const_int 8))))])
8033 ; indirect-jump instruction pattern(s).
8036 (define_insn "indirect_jump"
8037 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8040 if (get_attr_op_type (insn) == OP_TYPE_RR)
8045 [(set (attr "op_type")
8046 (if_then_else (match_operand 0 "register_operand" "")
8047 (const_string "RR") (const_string "RX")))
8048 (set_attr "type" "branch")
8049 (set_attr "atype" "agen")])
8052 ; casesi instruction pattern(s).
8055 (define_insn "casesi_jump"
8056 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8057 (use (label_ref (match_operand 1 "" "")))]
8060 if (get_attr_op_type (insn) == OP_TYPE_RR)
8065 [(set (attr "op_type")
8066 (if_then_else (match_operand 0 "register_operand" "")
8067 (const_string "RR") (const_string "RX")))
8068 (set_attr "type" "branch")
8069 (set_attr "atype" "agen")])
8071 (define_expand "casesi"
8072 [(match_operand:SI 0 "general_operand" "")
8073 (match_operand:SI 1 "general_operand" "")
8074 (match_operand:SI 2 "general_operand" "")
8075 (label_ref (match_operand 3 "" ""))
8076 (label_ref (match_operand 4 "" ""))]
8079 rtx index = gen_reg_rtx (SImode);
8080 rtx base = gen_reg_rtx (Pmode);
8081 rtx target = gen_reg_rtx (Pmode);
8083 emit_move_insn (index, operands[0]);
8084 emit_insn (gen_subsi3 (index, index, operands[1]));
8085 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8088 if (Pmode != SImode)
8089 index = convert_to_mode (Pmode, index, 1);
8090 if (GET_CODE (index) != REG)
8091 index = copy_to_mode_reg (Pmode, index);
8094 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8096 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8098 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8100 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8101 emit_move_insn (target, index);
8104 target = gen_rtx_PLUS (Pmode, base, target);
8105 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8112 ;;- Jump to subroutine.
8117 ; untyped call instruction pattern(s).
8120 ;; Call subroutine returning any type.
8121 (define_expand "untyped_call"
8122 [(parallel [(call (match_operand 0 "" "")
8124 (match_operand 1 "" "")
8125 (match_operand 2 "" "")])]
8130 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8132 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8134 rtx set = XVECEXP (operands[2], 0, i);
8135 emit_move_insn (SET_DEST (set), SET_SRC (set));
8138 /* The optimizer does not know that the call sets the function value
8139 registers we stored in the result block. We avoid problems by
8140 claiming that all hard registers are used and clobbered at this
8142 emit_insn (gen_blockage ());
8147 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8148 ;; all of memory. This blocks insns from being moved across this point.
8150 (define_insn "blockage"
8151 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8154 [(set_attr "type" "none")
8155 (set_attr "length" "0")])
8161 (define_expand "sibcall"
8162 [(call (match_operand 0 "" "")
8163 (match_operand 1 "" ""))]
8166 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8170 (define_insn "*sibcall_br"
8171 [(call (mem:QI (reg SIBCALL_REGNUM))
8172 (match_operand 0 "const_int_operand" "n"))]
8173 "SIBLING_CALL_P (insn)
8174 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8176 [(set_attr "op_type" "RR")
8177 (set_attr "type" "branch")
8178 (set_attr "atype" "agen")])
8180 (define_insn "*sibcall_brc"
8181 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8182 (match_operand 1 "const_int_operand" "n"))]
8183 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8185 [(set_attr "op_type" "RI")
8186 (set_attr "type" "branch")])
8188 (define_insn "*sibcall_brcl"
8189 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8190 (match_operand 1 "const_int_operand" "n"))]
8191 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8193 [(set_attr "op_type" "RIL")
8194 (set_attr "type" "branch")])
8197 ; sibcall_value patterns
8200 (define_expand "sibcall_value"
8201 [(set (match_operand 0 "" "")
8202 (call (match_operand 1 "" "")
8203 (match_operand 2 "" "")))]
8206 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8210 (define_insn "*sibcall_value_br"
8211 [(set (match_operand 0 "" "")
8212 (call (mem:QI (reg SIBCALL_REGNUM))
8213 (match_operand 1 "const_int_operand" "n")))]
8214 "SIBLING_CALL_P (insn)
8215 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8217 [(set_attr "op_type" "RR")
8218 (set_attr "type" "branch")
8219 (set_attr "atype" "agen")])
8221 (define_insn "*sibcall_value_brc"
8222 [(set (match_operand 0 "" "")
8223 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8224 (match_operand 2 "const_int_operand" "n")))]
8225 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8227 [(set_attr "op_type" "RI")
8228 (set_attr "type" "branch")])
8230 (define_insn "*sibcall_value_brcl"
8231 [(set (match_operand 0 "" "")
8232 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8233 (match_operand 2 "const_int_operand" "n")))]
8234 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8236 [(set_attr "op_type" "RIL")
8237 (set_attr "type" "branch")])
8241 ; call instruction pattern(s).
8244 (define_expand "call"
8245 [(call (match_operand 0 "" "")
8246 (match_operand 1 "" ""))
8247 (use (match_operand 2 "" ""))]
8250 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8251 gen_rtx_REG (Pmode, RETURN_REGNUM));
8255 (define_insn "*bras"
8256 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8257 (match_operand 1 "const_int_operand" "n"))
8258 (clobber (match_operand 2 "register_operand" "=r"))]
8259 "!SIBLING_CALL_P (insn)
8260 && TARGET_SMALL_EXEC
8261 && GET_MODE (operands[2]) == Pmode"
8263 [(set_attr "op_type" "RI")
8264 (set_attr "type" "jsr")])
8266 (define_insn "*brasl"
8267 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8268 (match_operand 1 "const_int_operand" "n"))
8269 (clobber (match_operand 2 "register_operand" "=r"))]
8270 "!SIBLING_CALL_P (insn)
8272 && GET_MODE (operands[2]) == Pmode"
8274 [(set_attr "op_type" "RIL")
8275 (set_attr "type" "jsr")])
8277 (define_insn "*basr"
8278 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8279 (match_operand 1 "const_int_operand" "n"))
8280 (clobber (match_operand 2 "register_operand" "=r"))]
8281 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8283 if (get_attr_op_type (insn) == OP_TYPE_RR)
8284 return "basr\t%2,%0";
8286 return "bas\t%2,%a0";
8288 [(set (attr "op_type")
8289 (if_then_else (match_operand 0 "register_operand" "")
8290 (const_string "RR") (const_string "RX")))
8291 (set_attr "type" "jsr")
8292 (set_attr "atype" "agen")])
8295 ; call_value instruction pattern(s).
8298 (define_expand "call_value"
8299 [(set (match_operand 0 "" "")
8300 (call (match_operand 1 "" "")
8301 (match_operand 2 "" "")))
8302 (use (match_operand 3 "" ""))]
8305 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8306 gen_rtx_REG (Pmode, RETURN_REGNUM));
8310 (define_insn "*bras_r"
8311 [(set (match_operand 0 "" "")
8312 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8313 (match_operand:SI 2 "const_int_operand" "n")))
8314 (clobber (match_operand 3 "register_operand" "=r"))]
8315 "!SIBLING_CALL_P (insn)
8316 && TARGET_SMALL_EXEC
8317 && GET_MODE (operands[3]) == Pmode"
8319 [(set_attr "op_type" "RI")
8320 (set_attr "type" "jsr")])
8322 (define_insn "*brasl_r"
8323 [(set (match_operand 0 "" "")
8324 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8325 (match_operand 2 "const_int_operand" "n")))
8326 (clobber (match_operand 3 "register_operand" "=r"))]
8327 "!SIBLING_CALL_P (insn)
8329 && GET_MODE (operands[3]) == Pmode"
8331 [(set_attr "op_type" "RIL")
8332 (set_attr "type" "jsr")])
8334 (define_insn "*basr_r"
8335 [(set (match_operand 0 "" "")
8336 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8337 (match_operand 2 "const_int_operand" "n")))
8338 (clobber (match_operand 3 "register_operand" "=r"))]
8339 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8341 if (get_attr_op_type (insn) == OP_TYPE_RR)
8342 return "basr\t%3,%1";
8344 return "bas\t%3,%a1";
8346 [(set (attr "op_type")
8347 (if_then_else (match_operand 1 "register_operand" "")
8348 (const_string "RR") (const_string "RX")))
8349 (set_attr "type" "jsr")
8350 (set_attr "atype" "agen")])
8353 ;;- Thread-local storage support.
8356 (define_expand "get_tp_64"
8357 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
8361 (define_expand "get_tp_31"
8362 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
8366 (define_expand "set_tp_64"
8367 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
8368 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
8372 (define_expand "set_tp_31"
8373 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
8374 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
8378 (define_insn "*set_tp"
8379 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8382 [(set_attr "type" "none")
8383 (set_attr "length" "0")])
8385 (define_insn "*tls_load_64"
8386 [(set (match_operand:DI 0 "register_operand" "=d")
8387 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8388 (match_operand:DI 2 "" "")]
8392 [(set_attr "op_type" "RXE")
8393 (set_attr "z10prop" "z10_fwd_A3")])
8395 (define_insn "*tls_load_31"
8396 [(set (match_operand:SI 0 "register_operand" "=d,d")
8397 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8398 (match_operand:SI 2 "" "")]
8404 [(set_attr "op_type" "RX,RXY")
8405 (set_attr "type" "load")
8406 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8408 (define_insn "*bras_tls"
8409 [(set (match_operand 0 "" "")
8410 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8411 (match_operand 2 "const_int_operand" "n")))
8412 (clobber (match_operand 3 "register_operand" "=r"))
8413 (use (match_operand 4 "" ""))]
8414 "!SIBLING_CALL_P (insn)
8415 && TARGET_SMALL_EXEC
8416 && GET_MODE (operands[3]) == Pmode"
8418 [(set_attr "op_type" "RI")
8419 (set_attr "type" "jsr")])
8421 (define_insn "*brasl_tls"
8422 [(set (match_operand 0 "" "")
8423 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8424 (match_operand 2 "const_int_operand" "n")))
8425 (clobber (match_operand 3 "register_operand" "=r"))
8426 (use (match_operand 4 "" ""))]
8427 "!SIBLING_CALL_P (insn)
8429 && GET_MODE (operands[3]) == Pmode"
8431 [(set_attr "op_type" "RIL")
8432 (set_attr "type" "jsr")])
8434 (define_insn "*basr_tls"
8435 [(set (match_operand 0 "" "")
8436 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8437 (match_operand 2 "const_int_operand" "n")))
8438 (clobber (match_operand 3 "register_operand" "=r"))
8439 (use (match_operand 4 "" ""))]
8440 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8442 if (get_attr_op_type (insn) == OP_TYPE_RR)
8443 return "basr\t%3,%1%J4";
8445 return "bas\t%3,%a1%J4";
8447 [(set (attr "op_type")
8448 (if_then_else (match_operand 1 "register_operand" "")
8449 (const_string "RR") (const_string "RX")))
8450 (set_attr "type" "jsr")
8451 (set_attr "atype" "agen")])
8454 ;;- Atomic operations
8458 ; memory barrier pattern.
8461 (define_expand "memory_barrier"
8463 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8466 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8467 MEM_VOLATILE_P (operands[0]) = 1;
8470 (define_insn "*memory_barrier"
8471 [(set (match_operand:BLK 0 "" "")
8472 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8475 [(set_attr "op_type" "RR")])
8477 ; Although bcr is superscalar on Z10, this variant will never become part of
8478 ; an execution group.
8481 ; compare and swap patterns.
8484 (define_expand "sync_compare_and_swap<mode>"
8486 [(set (match_operand:TDSI 0 "register_operand" "")
8487 (match_operand:TDSI 1 "memory_operand" ""))
8489 (unspec_volatile:TDSI
8491 (match_operand:TDSI 2 "register_operand" "")
8492 (match_operand:TDSI 3 "register_operand" "")]
8494 (set (reg:CCZ1 CC_REGNUM)
8495 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8498 (define_expand "sync_compare_and_swap<mode>"
8500 [(set (match_operand:HQI 0 "register_operand" "")
8501 (match_operand:HQI 1 "memory_operand" ""))
8503 (unspec_volatile:HQI
8505 (match_operand:HQI 2 "general_operand" "")
8506 (match_operand:HQI 3 "general_operand" "")]
8508 (clobber (reg:CC CC_REGNUM))])]
8510 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
8511 operands[2], operands[3]); DONE;")
8514 (define_insn "*sync_compare_and_swap<mode>"
8515 [(set (match_operand:DW 0 "register_operand" "=r")
8516 (match_operand:DW 1 "memory_operand" "+Q"))
8520 (match_operand:DW 2 "register_operand" "0")
8521 (match_operand:DW 3 "register_operand" "r")]
8523 (set (reg:CCZ1 CC_REGNUM)
8524 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8526 "cds<tg>\t%0,%3,%S1"
8527 [(set_attr "op_type" "RS<TE>")
8528 (set_attr "type" "sem")])
8531 (define_insn "*sync_compare_and_swap<mode>"
8532 [(set (match_operand:GPR 0 "register_operand" "=r")
8533 (match_operand:GPR 1 "memory_operand" "+Q"))
8535 (unspec_volatile:GPR
8537 (match_operand:GPR 2 "register_operand" "0")
8538 (match_operand:GPR 3 "register_operand" "r")]
8540 (set (reg:CCZ1 CC_REGNUM)
8541 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8544 [(set_attr "op_type" "RS<E>")
8545 (set_attr "type" "sem")])
8549 ; Other atomic instruction patterns.
8552 (define_expand "sync_lock_test_and_set<mode>"
8553 [(match_operand:HQI 0 "register_operand")
8554 (match_operand:HQI 1 "memory_operand")
8555 (match_operand:HQI 2 "general_operand")]
8557 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
8558 operands[2], false); DONE;")
8560 (define_expand "sync_<atomic><mode>"
8561 [(set (match_operand:HQI 0 "memory_operand")
8562 (ATOMIC:HQI (match_dup 0)
8563 (match_operand:HQI 1 "general_operand")))]
8565 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
8566 operands[1], false); DONE;")
8568 (define_expand "sync_old_<atomic><mode>"
8569 [(set (match_operand:HQI 0 "register_operand")
8570 (match_operand:HQI 1 "memory_operand"))
8572 (ATOMIC:HQI (match_dup 1)
8573 (match_operand:HQI 2 "general_operand")))]
8575 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8576 operands[2], false); DONE;")
8578 (define_expand "sync_new_<atomic><mode>"
8579 [(set (match_operand:HQI 0 "register_operand")
8580 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
8581 (match_operand:HQI 2 "general_operand")))
8582 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
8584 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8585 operands[2], true); DONE;")
8588 ;;- Miscellaneous instructions.
8592 ; allocate stack instruction pattern(s).
8595 (define_expand "allocate_stack"
8596 [(match_operand 0 "general_operand" "")
8597 (match_operand 1 "general_operand" "")]
8600 rtx temp = gen_reg_rtx (Pmode);
8602 emit_move_insn (temp, s390_back_chain_rtx ());
8603 anti_adjust_stack (operands[1]);
8604 emit_move_insn (s390_back_chain_rtx (), temp);
8606 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
8612 ; setjmp instruction pattern.
8615 (define_expand "builtin_setjmp_receiver"
8616 [(match_operand 0 "" "")]
8619 emit_insn (s390_load_got ());
8620 emit_use (pic_offset_table_rtx);
8624 ;; These patterns say how to save and restore the stack pointer. We need not
8625 ;; save the stack pointer at function level since we are careful to
8626 ;; preserve the backchain. At block level, we have to restore the backchain
8627 ;; when we restore the stack pointer.
8629 ;; For nonlocal gotos, we must save both the stack pointer and its
8630 ;; backchain and restore both. Note that in the nonlocal case, the
8631 ;; save area is a memory location.
8633 (define_expand "save_stack_function"
8634 [(match_operand 0 "general_operand" "")
8635 (match_operand 1 "general_operand" "")]
8639 (define_expand "restore_stack_function"
8640 [(match_operand 0 "general_operand" "")
8641 (match_operand 1 "general_operand" "")]
8645 (define_expand "restore_stack_block"
8646 [(match_operand 0 "register_operand" "")
8647 (match_operand 1 "register_operand" "")]
8650 rtx temp = gen_reg_rtx (Pmode);
8652 emit_move_insn (temp, s390_back_chain_rtx ());
8653 emit_move_insn (operands[0], operands[1]);
8654 emit_move_insn (s390_back_chain_rtx (), temp);
8659 (define_expand "save_stack_nonlocal"
8660 [(match_operand 0 "memory_operand" "")
8661 (match_operand 1 "register_operand" "")]
8664 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8666 /* Copy the backchain to the first word, sp to the second and the
8667 literal pool base to the third. */
8669 rtx save_bc = adjust_address (operands[0], Pmode, 0);
8670 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
8671 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
8673 if (TARGET_BACKCHAIN)
8674 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
8676 emit_move_insn (save_sp, operands[1]);
8677 emit_move_insn (save_bp, base);
8682 (define_expand "restore_stack_nonlocal"
8683 [(match_operand 0 "register_operand" "")
8684 (match_operand 1 "memory_operand" "")]
8687 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8688 rtx temp = NULL_RTX;
8690 /* Restore the backchain from the first word, sp from the second and the
8691 literal pool base from the third. */
8693 rtx save_bc = adjust_address (operands[1], Pmode, 0);
8694 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
8695 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
8697 if (TARGET_BACKCHAIN)
8698 temp = force_reg (Pmode, save_bc);
8700 emit_move_insn (base, save_bp);
8701 emit_move_insn (operands[0], save_sp);
8704 emit_move_insn (s390_back_chain_rtx (), temp);
8710 (define_expand "exception_receiver"
8714 s390_set_has_landing_pad_p (true);
8719 ; nop instruction pattern(s).
8726 [(set_attr "op_type" "RR")
8727 (set_attr "z10prop" "z10_fr_E1")])
8733 [(set_attr "op_type" "RR")])
8737 ; Special literal pool access instruction pattern(s).
8740 (define_insn "*pool_entry"
8741 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
8742 UNSPECV_POOL_ENTRY)]
8745 enum machine_mode mode = GET_MODE (PATTERN (insn));
8746 unsigned int align = GET_MODE_BITSIZE (mode);
8747 s390_output_pool_entry (operands[0], mode, align);
8750 [(set (attr "length")
8751 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
8753 (define_insn "pool_align"
8754 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
8755 UNSPECV_POOL_ALIGN)]
8758 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8760 (define_insn "pool_section_start"
8761 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
8764 [(set_attr "length" "0")])
8766 (define_insn "pool_section_end"
8767 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
8770 [(set_attr "length" "0")])
8772 (define_insn "main_base_31_small"
8773 [(set (match_operand 0 "register_operand" "=a")
8774 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8775 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8777 [(set_attr "op_type" "RR")
8778 (set_attr "type" "la")])
8780 (define_insn "main_base_31_large"
8781 [(set (match_operand 0 "register_operand" "=a")
8782 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
8783 (set (pc) (label_ref (match_operand 2 "" "")))]
8784 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8786 [(set_attr "op_type" "RI")])
8788 (define_insn "main_base_64"
8789 [(set (match_operand 0 "register_operand" "=a")
8790 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8791 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8793 [(set_attr "op_type" "RIL")
8794 (set_attr "type" "larl")
8795 (set_attr "z10prop" "z10_fwd_A1")])
8797 (define_insn "main_pool"
8798 [(set (match_operand 0 "register_operand" "=a")
8799 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
8800 "GET_MODE (operands[0]) == Pmode"
8805 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
8806 (const_string "larl") (const_string "la")))])
8808 (define_insn "reload_base_31"
8809 [(set (match_operand 0 "register_operand" "=a")
8810 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8811 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8812 "basr\t%0,0\;la\t%0,%1-.(%0)"
8813 [(set_attr "length" "6")
8814 (set_attr "type" "la")])
8816 (define_insn "reload_base_64"
8817 [(set (match_operand 0 "register_operand" "=a")
8818 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8819 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8821 [(set_attr "op_type" "RIL")
8822 (set_attr "type" "larl")
8823 (set_attr "z10prop" "z10_fwd_A1")])
8826 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
8831 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8834 ;; Insns related to generating the function prologue and epilogue.
8838 (define_expand "prologue"
8839 [(use (const_int 0))]
8841 "s390_emit_prologue (); DONE;")
8843 (define_expand "epilogue"
8844 [(use (const_int 1))]
8846 "s390_emit_epilogue (false); DONE;")
8848 (define_expand "sibcall_epilogue"
8849 [(use (const_int 0))]
8851 "s390_emit_epilogue (true); DONE;")
8853 (define_insn "*return"
8855 (use (match_operand 0 "register_operand" "a"))]
8856 "GET_MODE (operands[0]) == Pmode"
8858 [(set_attr "op_type" "RR")
8859 (set_attr "type" "jsr")
8860 (set_attr "atype" "agen")])
8863 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
8864 ;; pointer. This is used for compatibility.
8866 (define_expand "ptr_extend"
8867 [(set (match_operand:DI 0 "register_operand" "=r")
8868 (match_operand:SI 1 "register_operand" "r"))]
8871 emit_insn (gen_anddi3 (operands[0],
8872 gen_lowpart (DImode, operands[1]),
8873 GEN_INT (0x7fffffff)));
8877 ;; Instruction definition to expand eh_return macro to support
8878 ;; swapping in special linkage return addresses.
8880 (define_expand "eh_return"
8881 [(use (match_operand 0 "register_operand" ""))]
8884 s390_emit_tpf_eh_return (operands[0]);
8889 ; Stack Protector Patterns
8892 (define_expand "stack_protect_set"
8893 [(set (match_operand 0 "memory_operand" "")
8894 (match_operand 1 "memory_operand" ""))]
8897 #ifdef TARGET_THREAD_SSP_OFFSET
8899 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8900 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8903 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
8905 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
8910 (define_insn "stack_protect_set<mode>"
8911 [(set (match_operand:DSI 0 "memory_operand" "=Q")
8912 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
8914 "mvc\t%O0(%G0,%R0),%S1"
8915 [(set_attr "op_type" "SS")])
8917 (define_expand "stack_protect_test"
8918 [(set (reg:CC CC_REGNUM)
8919 (compare (match_operand 0 "memory_operand" "")
8920 (match_operand 1 "memory_operand" "")))
8921 (match_operand 2 "" "")]
8925 #ifdef TARGET_THREAD_SSP_OFFSET
8927 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8928 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8931 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
8933 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
8935 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
8936 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
8937 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
8941 (define_insn "stack_protect_test<mode>"
8942 [(set (reg:CCZ CC_REGNUM)
8943 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
8944 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
8946 "clc\t%O0(%G0,%R0),%S1"
8947 [(set_attr "op_type" "SS")])
8949 ; This is used in s390_emit_prologue in order to prevent insns
8950 ; adjusting the stack pointer to be moved over insns writing stack
8951 ; slots using a copy of the stack pointer in a different register.
8952 (define_insn "stack_tie"
8953 [(set (match_operand:BLK 0 "memory_operand" "+m")
8954 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
8957 [(set_attr "length" "0")])
8961 ; Data prefetch patterns
8964 (define_insn "prefetch"
8965 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
8966 (match_operand:SI 1 "const_int_operand" " n,n")
8967 (match_operand:SI 2 "const_int_operand" " n,n"))]
8970 switch (which_alternative)
8973 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
8975 if (larl_operand (operands[0], Pmode))
8976 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
8979 /* This might be reached for symbolic operands with an odd
8980 addend. We simply omit the prefetch for such rare cases. */
8985 [(set_attr "type" "load,larl")
8986 (set_attr "op_type" "RXY,RIL")
8987 (set_attr "z10prop" "z10_super")])
8991 ; Byte swap instructions
8994 (define_insn "bswap<mode>2"
8995 [(set (match_operand:GPR 0 "register_operand" "=d, d")
8996 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9001 [(set_attr "type" "*,load")
9002 (set_attr "op_type" "RRE,RXY")
9003 (set_attr "z10prop" "z10_super")])