| blob | 23fde85bb53411491a8aa030e5cb93f7a2add5fb |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; REGNOS
27 ;;
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (CA_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
52 ;;
53 ;; UNSPEC usage
54 ;;
56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_PROBE_STACK 4) ; probe stack memory reference
59 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
60 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
61 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
62 (UNSPEC_MOVSI_GOT 8)
63 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
64 (UNSPEC_FCTIWZ 10)
65 (UNSPEC_FRIM 11)
66 (UNSPEC_FRIN 12)
67 (UNSPEC_FRIP 13)
68 (UNSPEC_FRIZ 14)
69 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
70 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
71 (UNSPEC_TLSGD 17)
72 (UNSPEC_TLSLD 18)
73 (UNSPEC_MOVESI_FROM_CR 19)
74 (UNSPEC_MOVESI_TO_CR 20)
75 (UNSPEC_TLSDTPREL 21)
76 (UNSPEC_TLSDTPRELHA 22)
77 (UNSPEC_TLSDTPRELLO 23)
78 (UNSPEC_TLSGOTDTPREL 24)
79 (UNSPEC_TLSTPREL 25)
80 (UNSPEC_TLSTPRELHA 26)
81 (UNSPEC_TLSTPRELLO 27)
82 (UNSPEC_TLSGOTTPREL 28)
83 (UNSPEC_TLSTLS 29)
84 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
85 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
86 (UNSPEC_STFIWX 32)
87 (UNSPEC_POPCNTB 33)
88 (UNSPEC_FRES 34)
89 (UNSPEC_SP_SET 35)
90 (UNSPEC_SP_TEST 36)
91 (UNSPEC_SYNC 37)
92 (UNSPEC_LWSYNC 38)
93 (UNSPEC_ISYNC 39)
94 (UNSPEC_SYNC_OP 40)
95 (UNSPEC_ATOMIC 41)
96 (UNSPEC_CMPXCHG 42)
97 (UNSPEC_XCHG 43)
98 (UNSPEC_AND 44)
99 (UNSPEC_DLMZB 45)
100 (UNSPEC_DLMZB_CR 46)
101 (UNSPEC_DLMZB_STRLEN 47)
102 (UNSPEC_RSQRT 48)
103 (UNSPEC_TOCREL 49)
104 (UNSPEC_MACHOPIC_OFFSET 50)
105 (UNSPEC_BPERM 51)
106 (UNSPEC_COPYSIGN 52)
107 (UNSPEC_PARITY 53)
108 (UNSPEC_FCTIW 54)
109 (UNSPEC_FCTID 55)
110 (UNSPEC_LFIWAX 56)
111 (UNSPEC_LFIWZX 57)
112 (UNSPEC_FCTIWUZ 58)
113 ])
115 ;;
116 ;; UNSPEC_VOLATILE usage
117 ;;
119 (define_constants
120 [(UNSPECV_BLOCK 0)
121 (UNSPECV_LL 1) ; load-locked
122 (UNSPECV_SC 2) ; store-conditional
123 (UNSPECV_PROBE_STACK_RANGE 3) ; probe range of stack addresses
124 (UNSPECV_EH_RR 9) ; eh_reg_restore
125 ])
126 \f
127 ;; Define an insn type attribute. This is used in function unit delay
128 ;; computations.
129 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
130 (const_string "integer"))
132 ;; Define floating point instruction sub-types for use with Xfpu.md
133 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
135 ;; Length (in bytes).
136 ; '(pc)' in the following doesn't include the instruction itself; it is
137 ; calculated as if the instruction had zero size.
138 (define_attr "length" ""
139 (if_then_else (eq_attr "type" "branch")
140 (if_then_else (and (ge (minus (match_dup 0) (pc))
141 (const_int -32768))
142 (lt (minus (match_dup 0) (pc))
143 (const_int 32764)))
144 (const_int 4)
145 (const_int 8))
146 (const_int 4)))
148 ;; Processor type -- this attribute must exactly match the processor_type
149 ;; enumeration in rs6000.h.
151 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
152 (const (symbol_ref "rs6000_cpu_attr")))
155 ;; If this instruction is microcoded on the CELL processor
156 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
157 (define_attr "cell_micro" "not,conditional,always"
158 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
159 (const_string "always")
160 (const_string "not")))
162 (automata_option "ndfa")
164 (include "rios1.md")
165 (include "rios2.md")
166 (include "rs64.md")
167 (include "mpc.md")
168 (include "40x.md")
169 (include "440.md")
170 (include "476.md")
171 (include "603.md")
172 (include "6xx.md")
173 (include "7xx.md")
174 (include "7450.md")
175 (include "8540.md")
176 (include "e300c2c3.md")
177 (include "e500mc.md")
178 (include "e500mc64.md")
179 (include "power4.md")
180 (include "power5.md")
181 (include "power6.md")
182 (include "power7.md")
183 (include "cell.md")
184 (include "xfpu.md")
185 (include "a2.md")
186 (include "titan.md")
188 (include "predicates.md")
189 (include "constraints.md")
191 (include "darwin.md")
193 \f
194 ;; Mode iterators
196 ; This mode iterator allows :GPR to be used to indicate the allowable size
197 ; of whole values in GPRs.
198 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
200 ; Any supported integer mode.
201 (define_mode_iterator INT [QI HI SI DI TI])
203 ; Any supported integer mode that fits in one register.
204 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
206 ; extend modes for DImode
207 (define_mode_iterator QHSI [QI HI SI])
209 ; SImode or DImode, even if DImode doesn't fit in GPRs.
210 (define_mode_iterator SDI [SI DI])
212 ; The size of a pointer. Also, the size of the value that a record-condition
213 ; (one with a '.') will compare; and the size used for arithmetic carries.
214 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
216 ; Any hardware-supported floating-point mode
217 (define_mode_iterator FP [
218 (SF "TARGET_HARD_FLOAT
219 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
220 (DF "TARGET_HARD_FLOAT
221 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
222 (TF "!TARGET_IEEEQUAD
223 && TARGET_HARD_FLOAT
224 && (TARGET_FPRS || TARGET_E500_DOUBLE)
225 && TARGET_LONG_DOUBLE_128")
226 (DD "TARGET_DFP")
227 (TD "TARGET_DFP")])
229 ; These modes do not fit in integer registers in 32-bit mode.
230 ; but on e500v2, the gpr are 64 bit registers
231 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
233 ; Iterator for reciprocal estimate instructions
234 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
236 ; Iterator for just SF/DF
237 (define_mode_iterator SFDF [SF DF])
239 ; Various instructions that come in SI and DI forms.
240 ; A generic w/d attribute, for things like cmpw/cmpd.
241 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
243 ; DImode bits
244 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
246 ;; ISEL/ISEL64 target selection
247 (define_mode_attr sel [(SI "") (DI "64")])
249 ;; Suffix for reload patterns
250 (define_mode_attr ptrsize [(SI "32bit")
251 (DI "64bit")])
253 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
254 (DI "TARGET_64BIT")])
256 (define_mode_attr mptrsize [(SI "si")
257 (DI "di")])
259 (define_mode_attr rreg [(SF "f")
260 (DF "ws")
261 (V4SF "wf")
262 (V2DF "wd")])
264 (define_mode_attr rreg2 [(SF "f")
265 (DF "d")])
267 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
268 (DF "TARGET_FCFID")])
270 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
271 (DF "TARGET_E500_DOUBLE")])
273 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
274 (DF "TARGET_DOUBLE_FLOAT")])
275 \f
276 ;; Start with fixed-point load and store insns. Here we put only the more
277 ;; complex forms. Basic data transfer is done later.
279 (define_expand "zero_extend<mode>di2"
280 [(set (match_operand:DI 0 "gpc_reg_operand" "")
281 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
282 "TARGET_POWERPC64"
283 "")
285 (define_insn "*zero_extend<mode>di2_internal1"
286 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
287 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
288 "TARGET_POWERPC64"
289 "@
290 l<wd>z%U1%X1 %0,%1
291 rldicl %0,%1,0,<dbits>"
292 [(set_attr "type" "load,*")])
294 (define_insn "*zero_extend<mode>di2_internal2"
295 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
296 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
297 (const_int 0)))
298 (clobber (match_scratch:DI 2 "=r,r"))]
299 "TARGET_64BIT"
300 "@
301 rldicl. %2,%1,0,<dbits>
302 #"
303 [(set_attr "type" "compare")
304 (set_attr "length" "4,8")])
306 (define_split
307 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
308 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
309 (const_int 0)))
310 (clobber (match_scratch:DI 2 ""))]
311 "TARGET_POWERPC64 && reload_completed"
312 [(set (match_dup 2)
313 (zero_extend:DI (match_dup 1)))
314 (set (match_dup 0)
315 (compare:CC (match_dup 2)
316 (const_int 0)))]
317 "")
319 (define_insn "*zero_extend<mode>di2_internal3"
320 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
321 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
322 (const_int 0)))
323 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
324 (zero_extend:DI (match_dup 1)))]
325 "TARGET_64BIT"
326 "@
327 rldicl. %0,%1,0,<dbits>
328 #"
329 [(set_attr "type" "compare")
330 (set_attr "length" "4,8")])
332 (define_split
333 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
334 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
335 (const_int 0)))
336 (set (match_operand:DI 0 "gpc_reg_operand" "")
337 (zero_extend:DI (match_dup 1)))]
338 "TARGET_POWERPC64 && reload_completed"
339 [(set (match_dup 0)
340 (zero_extend:DI (match_dup 1)))
341 (set (match_dup 2)
342 (compare:CC (match_dup 0)
343 (const_int 0)))]
344 "")
346 (define_insn "extendqidi2"
347 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
348 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
349 "TARGET_POWERPC64"
350 "extsb %0,%1"
351 [(set_attr "type" "exts")])
353 (define_insn ""
354 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
355 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
356 (const_int 0)))
357 (clobber (match_scratch:DI 2 "=r,r"))]
358 "TARGET_64BIT"
359 "@
360 extsb. %2,%1
361 #"
362 [(set_attr "type" "compare")
363 (set_attr "length" "4,8")])
365 (define_split
366 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
367 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
368 (const_int 0)))
369 (clobber (match_scratch:DI 2 ""))]
370 "TARGET_POWERPC64 && reload_completed"
371 [(set (match_dup 2)
372 (sign_extend:DI (match_dup 1)))
373 (set (match_dup 0)
374 (compare:CC (match_dup 2)
375 (const_int 0)))]
376 "")
378 (define_insn ""
379 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
380 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
381 (const_int 0)))
382 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
383 (sign_extend:DI (match_dup 1)))]
384 "TARGET_64BIT"
385 "@
386 extsb. %0,%1
387 #"
388 [(set_attr "type" "compare")
389 (set_attr "length" "4,8")])
391 (define_split
392 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
393 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
394 (const_int 0)))
395 (set (match_operand:DI 0 "gpc_reg_operand" "")
396 (sign_extend:DI (match_dup 1)))]
397 "TARGET_POWERPC64 && reload_completed"
398 [(set (match_dup 0)
399 (sign_extend:DI (match_dup 1)))
400 (set (match_dup 2)
401 (compare:CC (match_dup 0)
402 (const_int 0)))]
403 "")
405 (define_expand "extendhidi2"
406 [(set (match_operand:DI 0 "gpc_reg_operand" "")
407 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
408 "TARGET_POWERPC64"
409 "")
411 (define_insn ""
412 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
413 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
414 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
415 "@
416 lha%U1%X1 %0,%1
417 extsh %0,%1"
418 [(set_attr "type" "load_ext,exts")])
420 (define_insn ""
421 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
422 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
423 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
424 "extsh %0,%1"
425 [(set_attr "type" "exts")])
427 (define_insn ""
428 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
429 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
430 (const_int 0)))
431 (clobber (match_scratch:DI 2 "=r,r"))]
432 "TARGET_64BIT"
433 "@
434 extsh. %2,%1
435 #"
436 [(set_attr "type" "compare")
437 (set_attr "length" "4,8")])
439 (define_split
440 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
441 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
442 (const_int 0)))
443 (clobber (match_scratch:DI 2 ""))]
444 "TARGET_POWERPC64 && reload_completed"
445 [(set (match_dup 2)
446 (sign_extend:DI (match_dup 1)))
447 (set (match_dup 0)
448 (compare:CC (match_dup 2)
449 (const_int 0)))]
450 "")
452 (define_insn ""
453 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
454 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
455 (const_int 0)))
456 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
457 (sign_extend:DI (match_dup 1)))]
458 "TARGET_64BIT"
459 "@
460 extsh. %0,%1
461 #"
462 [(set_attr "type" "compare")
463 (set_attr "length" "4,8")])
465 (define_split
466 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
467 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
468 (const_int 0)))
469 (set (match_operand:DI 0 "gpc_reg_operand" "")
470 (sign_extend:DI (match_dup 1)))]
471 "TARGET_POWERPC64 && reload_completed"
472 [(set (match_dup 0)
473 (sign_extend:DI (match_dup 1)))
474 (set (match_dup 2)
475 (compare:CC (match_dup 0)
476 (const_int 0)))]
477 "")
479 (define_expand "extendsidi2"
480 [(set (match_operand:DI 0 "gpc_reg_operand" "")
481 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
482 "TARGET_POWERPC64"
483 "")
485 (define_insn ""
486 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
487 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
488 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
489 "@
490 lwa%U1%X1 %0,%1
491 extsw %0,%1"
492 [(set_attr "type" "load_ext,exts")])
494 (define_insn ""
495 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
496 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
497 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
498 "extsw %0,%1"
499 [(set_attr "type" "exts")])
501 (define_insn ""
502 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
503 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
504 (const_int 0)))
505 (clobber (match_scratch:DI 2 "=r,r"))]
506 "TARGET_64BIT"
507 "@
508 extsw. %2,%1
509 #"
510 [(set_attr "type" "compare")
511 (set_attr "length" "4,8")])
513 (define_split
514 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
515 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
516 (const_int 0)))
517 (clobber (match_scratch:DI 2 ""))]
518 "TARGET_POWERPC64 && reload_completed"
519 [(set (match_dup 2)
520 (sign_extend:DI (match_dup 1)))
521 (set (match_dup 0)
522 (compare:CC (match_dup 2)
523 (const_int 0)))]
524 "")
526 (define_insn ""
527 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
528 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
529 (const_int 0)))
530 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
531 (sign_extend:DI (match_dup 1)))]
532 "TARGET_64BIT"
533 "@
534 extsw. %0,%1
535 #"
536 [(set_attr "type" "compare")
537 (set_attr "length" "4,8")])
539 (define_split
540 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
541 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
542 (const_int 0)))
543 (set (match_operand:DI 0 "gpc_reg_operand" "")
544 (sign_extend:DI (match_dup 1)))]
545 "TARGET_POWERPC64 && reload_completed"
546 [(set (match_dup 0)
547 (sign_extend:DI (match_dup 1)))
548 (set (match_dup 2)
549 (compare:CC (match_dup 0)
550 (const_int 0)))]
551 "")
553 (define_expand "zero_extendqisi2"
554 [(set (match_operand:SI 0 "gpc_reg_operand" "")
555 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
556 ""
557 "")
559 (define_insn ""
560 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
561 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
562 ""
563 "@
564 lbz%U1%X1 %0,%1
565 {rlinm|rlwinm} %0,%1,0,0xff"
566 [(set_attr "type" "load,*")])
568 (define_insn ""
569 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
570 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
571 (const_int 0)))
572 (clobber (match_scratch:SI 2 "=r,r"))]
573 ""
574 "@
575 {andil.|andi.} %2,%1,0xff
576 #"
577 [(set_attr "type" "fast_compare,compare")
578 (set_attr "length" "4,8")])
580 (define_split
581 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
582 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
583 (const_int 0)))
584 (clobber (match_scratch:SI 2 ""))]
585 "reload_completed"
586 [(set (match_dup 2)
587 (zero_extend:SI (match_dup 1)))
588 (set (match_dup 0)
589 (compare:CC (match_dup 2)
590 (const_int 0)))]
591 "")
593 (define_insn ""
594 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
595 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
596 (const_int 0)))
597 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
598 (zero_extend:SI (match_dup 1)))]
599 ""
600 "@
601 {andil.|andi.} %0,%1,0xff
602 #"
603 [(set_attr "type" "fast_compare,compare")
604 (set_attr "length" "4,8")])
606 (define_split
607 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
608 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
609 (const_int 0)))
610 (set (match_operand:SI 0 "gpc_reg_operand" "")
611 (zero_extend:SI (match_dup 1)))]
612 "reload_completed"
613 [(set (match_dup 0)
614 (zero_extend:SI (match_dup 1)))
615 (set (match_dup 2)
616 (compare:CC (match_dup 0)
617 (const_int 0)))]
618 "")
620 (define_expand "extendqisi2"
621 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
622 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
623 ""
624 "
625 {
626 if (TARGET_POWERPC)
627 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
628 else if (TARGET_POWER)
629 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
630 else
631 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
632 DONE;
633 }")
635 (define_insn "extendqisi2_ppc"
636 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
637 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
638 "TARGET_POWERPC"
639 "extsb %0,%1"
640 [(set_attr "type" "exts")])
642 (define_insn ""
643 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
644 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
645 (const_int 0)))
646 (clobber (match_scratch:SI 2 "=r,r"))]
647 "TARGET_POWERPC"
648 "@
649 extsb. %2,%1
650 #"
651 [(set_attr "type" "compare")
652 (set_attr "length" "4,8")])
654 (define_split
655 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
656 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
657 (const_int 0)))
658 (clobber (match_scratch:SI 2 ""))]
659 "TARGET_POWERPC && reload_completed"
660 [(set (match_dup 2)
661 (sign_extend:SI (match_dup 1)))
662 (set (match_dup 0)
663 (compare:CC (match_dup 2)
664 (const_int 0)))]
665 "")
667 (define_insn ""
668 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
669 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
670 (const_int 0)))
671 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
672 (sign_extend:SI (match_dup 1)))]
673 "TARGET_POWERPC"
674 "@
675 extsb. %0,%1
676 #"
677 [(set_attr "type" "compare")
678 (set_attr "length" "4,8")])
680 (define_split
681 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
682 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
683 (const_int 0)))
684 (set (match_operand:SI 0 "gpc_reg_operand" "")
685 (sign_extend:SI (match_dup 1)))]
686 "TARGET_POWERPC && reload_completed"
687 [(set (match_dup 0)
688 (sign_extend:SI (match_dup 1)))
689 (set (match_dup 2)
690 (compare:CC (match_dup 0)
691 (const_int 0)))]
692 "")
694 (define_expand "extendqisi2_power"
695 [(parallel [(set (match_dup 2)
696 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
697 (const_int 24)))
698 (clobber (scratch:SI))])
699 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
700 (ashiftrt:SI (match_dup 2)
701 (const_int 24)))
702 (clobber (scratch:SI))])]
703 "TARGET_POWER"
704 "
705 { operands[1] = gen_lowpart (SImode, operands[1]);
706 operands[2] = gen_reg_rtx (SImode); }")
708 (define_expand "extendqisi2_no_power"
709 [(set (match_dup 2)
710 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
711 (const_int 24)))
712 (set (match_operand:SI 0 "gpc_reg_operand" "")
713 (ashiftrt:SI (match_dup 2)
714 (const_int 24)))]
715 "! TARGET_POWER && ! TARGET_POWERPC"
716 "
717 { operands[1] = gen_lowpart (SImode, operands[1]);
718 operands[2] = gen_reg_rtx (SImode); }")
720 (define_expand "zero_extendqihi2"
721 [(set (match_operand:HI 0 "gpc_reg_operand" "")
722 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
723 ""
724 "")
726 (define_insn ""
727 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
728 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
729 ""
730 "@
731 lbz%U1%X1 %0,%1
732 {rlinm|rlwinm} %0,%1,0,0xff"
733 [(set_attr "type" "load,*")])
735 (define_insn ""
736 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
737 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
738 (const_int 0)))
739 (clobber (match_scratch:HI 2 "=r,r"))]
740 ""
741 "@
742 {andil.|andi.} %2,%1,0xff
743 #"
744 [(set_attr "type" "fast_compare,compare")
745 (set_attr "length" "4,8")])
747 (define_split
748 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
749 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
750 (const_int 0)))
751 (clobber (match_scratch:HI 2 ""))]
752 "reload_completed"
753 [(set (match_dup 2)
754 (zero_extend:HI (match_dup 1)))
755 (set (match_dup 0)
756 (compare:CC (match_dup 2)
757 (const_int 0)))]
758 "")
760 (define_insn ""
761 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
762 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
763 (const_int 0)))
764 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
765 (zero_extend:HI (match_dup 1)))]
766 ""
767 "@
768 {andil.|andi.} %0,%1,0xff
769 #"
770 [(set_attr "type" "fast_compare,compare")
771 (set_attr "length" "4,8")])
773 (define_split
774 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
775 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
776 (const_int 0)))
777 (set (match_operand:HI 0 "gpc_reg_operand" "")
778 (zero_extend:HI (match_dup 1)))]
779 "reload_completed"
780 [(set (match_dup 0)
781 (zero_extend:HI (match_dup 1)))
782 (set (match_dup 2)
783 (compare:CC (match_dup 0)
784 (const_int 0)))]
785 "")
787 (define_expand "extendqihi2"
788 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
789 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
790 ""
791 "
792 {
793 if (TARGET_POWERPC)
794 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
795 else if (TARGET_POWER)
796 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
797 else
798 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
799 DONE;
800 }")
802 (define_insn "extendqihi2_ppc"
803 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
804 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
805 "TARGET_POWERPC"
806 "extsb %0,%1"
807 [(set_attr "type" "exts")])
809 (define_insn ""
810 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
811 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
812 (const_int 0)))
813 (clobber (match_scratch:HI 2 "=r,r"))]
814 "TARGET_POWERPC"
815 "@
816 extsb. %2,%1
817 #"
818 [(set_attr "type" "compare")
819 (set_attr "length" "4,8")])
821 (define_split
822 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
823 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
824 (const_int 0)))
825 (clobber (match_scratch:HI 2 ""))]
826 "TARGET_POWERPC && reload_completed"
827 [(set (match_dup 2)
828 (sign_extend:HI (match_dup 1)))
829 (set (match_dup 0)
830 (compare:CC (match_dup 2)
831 (const_int 0)))]
832 "")
834 (define_insn ""
835 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
836 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
837 (const_int 0)))
838 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
839 (sign_extend:HI (match_dup 1)))]
840 "TARGET_POWERPC"
841 "@
842 extsb. %0,%1
843 #"
844 [(set_attr "type" "compare")
845 (set_attr "length" "4,8")])
847 (define_split
848 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
849 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
850 (const_int 0)))
851 (set (match_operand:HI 0 "gpc_reg_operand" "")
852 (sign_extend:HI (match_dup 1)))]
853 "TARGET_POWERPC && reload_completed"
854 [(set (match_dup 0)
855 (sign_extend:HI (match_dup 1)))
856 (set (match_dup 2)
857 (compare:CC (match_dup 0)
858 (const_int 0)))]
859 "")
861 (define_expand "extendqihi2_power"
862 [(parallel [(set (match_dup 2)
863 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
864 (const_int 24)))
865 (clobber (scratch:SI))])
866 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
867 (ashiftrt:SI (match_dup 2)
868 (const_int 24)))
869 (clobber (scratch:SI))])]
870 "TARGET_POWER"
871 "
872 { operands[0] = gen_lowpart (SImode, operands[0]);
873 operands[1] = gen_lowpart (SImode, operands[1]);
874 operands[2] = gen_reg_rtx (SImode); }")
876 (define_expand "extendqihi2_no_power"
877 [(set (match_dup 2)
878 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
879 (const_int 24)))
880 (set (match_operand:HI 0 "gpc_reg_operand" "")
881 (ashiftrt:SI (match_dup 2)
882 (const_int 24)))]
883 "! TARGET_POWER && ! TARGET_POWERPC"
884 "
885 { operands[0] = gen_lowpart (SImode, operands[0]);
886 operands[1] = gen_lowpart (SImode, operands[1]);
887 operands[2] = gen_reg_rtx (SImode); }")
889 (define_expand "zero_extendhisi2"
890 [(set (match_operand:SI 0 "gpc_reg_operand" "")
891 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
892 ""
893 "")
895 (define_insn ""
896 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
897 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
898 ""
899 "@
900 lhz%U1%X1 %0,%1
901 {rlinm|rlwinm} %0,%1,0,0xffff"
902 [(set_attr "type" "load,*")])
904 (define_insn ""
905 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
906 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
907 (const_int 0)))
908 (clobber (match_scratch:SI 2 "=r,r"))]
909 ""
910 "@
911 {andil.|andi.} %2,%1,0xffff
912 #"
913 [(set_attr "type" "fast_compare,compare")
914 (set_attr "length" "4,8")])
916 (define_split
917 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
918 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
919 (const_int 0)))
920 (clobber (match_scratch:SI 2 ""))]
921 "reload_completed"
922 [(set (match_dup 2)
923 (zero_extend:SI (match_dup 1)))
924 (set (match_dup 0)
925 (compare:CC (match_dup 2)
926 (const_int 0)))]
927 "")
929 (define_insn ""
930 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
931 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
932 (const_int 0)))
933 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
934 (zero_extend:SI (match_dup 1)))]
935 ""
936 "@
937 {andil.|andi.} %0,%1,0xffff
938 #"
939 [(set_attr "type" "fast_compare,compare")
940 (set_attr "length" "4,8")])
942 (define_split
943 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
944 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
945 (const_int 0)))
946 (set (match_operand:SI 0 "gpc_reg_operand" "")
947 (zero_extend:SI (match_dup 1)))]
948 "reload_completed"
949 [(set (match_dup 0)
950 (zero_extend:SI (match_dup 1)))
951 (set (match_dup 2)
952 (compare:CC (match_dup 0)
953 (const_int 0)))]
954 "")
956 (define_expand "extendhisi2"
957 [(set (match_operand:SI 0 "gpc_reg_operand" "")
958 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
959 ""
960 "")
962 (define_insn ""
963 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
964 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
965 "rs6000_gen_cell_microcode"
966 "@
967 lha%U1%X1 %0,%1
968 {exts|extsh} %0,%1"
969 [(set_attr "type" "load_ext,exts")])
971 (define_insn ""
972 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
973 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
974 "!rs6000_gen_cell_microcode"
975 "{exts|extsh} %0,%1"
976 [(set_attr "type" "exts")])
978 (define_insn ""
979 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
980 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
981 (const_int 0)))
982 (clobber (match_scratch:SI 2 "=r,r"))]
983 ""
984 "@
985 {exts.|extsh.} %2,%1
986 #"
987 [(set_attr "type" "compare")
988 (set_attr "length" "4,8")])
990 (define_split
991 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
992 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
993 (const_int 0)))
994 (clobber (match_scratch:SI 2 ""))]
995 "reload_completed"
996 [(set (match_dup 2)
997 (sign_extend:SI (match_dup 1)))
998 (set (match_dup 0)
999 (compare:CC (match_dup 2)
1000 (const_int 0)))]
1001 "")
1003 (define_insn ""
1004 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1005 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1006 (const_int 0)))
1007 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1008 (sign_extend:SI (match_dup 1)))]
1009 ""
1010 "@
1011 {exts.|extsh.} %0,%1
1012 #"
1013 [(set_attr "type" "compare")
1014 (set_attr "length" "4,8")])
1015 \f
1016 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1018 (define_insn "*macchwc"
1019 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1020 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1021 (match_operand:SI 2 "gpc_reg_operand" "r")
1022 (const_int 16))
1023 (sign_extend:SI
1024 (match_operand:HI 1 "gpc_reg_operand" "r")))
1025 (match_operand:SI 4 "gpc_reg_operand" "0"))
1026 (const_int 0)))
1027 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1028 (plus:SI (mult:SI (ashiftrt:SI
1029 (match_dup 2)
1030 (const_int 16))
1031 (sign_extend:SI
1032 (match_dup 1)))
1033 (match_dup 4)))]
1034 "TARGET_MULHW"
1035 "macchw. %0, %1, %2"
1036 [(set_attr "type" "imul3")])
1038 (define_insn "*macchw"
1039 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1040 (plus:SI (mult:SI (ashiftrt:SI
1041 (match_operand:SI 2 "gpc_reg_operand" "r")
1042 (const_int 16))
1043 (sign_extend:SI
1044 (match_operand:HI 1 "gpc_reg_operand" "r")))
1045 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1046 "TARGET_MULHW"
1047 "macchw %0, %1, %2"
1048 [(set_attr "type" "imul3")])
1050 (define_insn "*macchwuc"
1051 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1052 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1053 (match_operand:SI 2 "gpc_reg_operand" "r")
1054 (const_int 16))
1055 (zero_extend:SI
1056 (match_operand:HI 1 "gpc_reg_operand" "r")))
1057 (match_operand:SI 4 "gpc_reg_operand" "0"))
1058 (const_int 0)))
1059 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1060 (plus:SI (mult:SI (lshiftrt:SI
1061 (match_dup 2)
1062 (const_int 16))
1063 (zero_extend:SI
1064 (match_dup 1)))
1065 (match_dup 4)))]
1066 "TARGET_MULHW"
1067 "macchwu. %0, %1, %2"
1068 [(set_attr "type" "imul3")])
1070 (define_insn "*macchwu"
1071 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1072 (plus:SI (mult:SI (lshiftrt:SI
1073 (match_operand:SI 2 "gpc_reg_operand" "r")
1074 (const_int 16))
1075 (zero_extend:SI
1076 (match_operand:HI 1 "gpc_reg_operand" "r")))
1077 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1078 "TARGET_MULHW"
1079 "macchwu %0, %1, %2"
1080 [(set_attr "type" "imul3")])
1082 (define_insn "*machhwc"
1083 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1084 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1085 (match_operand:SI 1 "gpc_reg_operand" "%r")
1086 (const_int 16))
1087 (ashiftrt:SI
1088 (match_operand:SI 2 "gpc_reg_operand" "r")
1089 (const_int 16)))
1090 (match_operand:SI 4 "gpc_reg_operand" "0"))
1091 (const_int 0)))
1092 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1093 (plus:SI (mult:SI (ashiftrt:SI
1094 (match_dup 1)
1095 (const_int 16))
1096 (ashiftrt:SI
1097 (match_dup 2)
1098 (const_int 16)))
1099 (match_dup 4)))]
1100 "TARGET_MULHW"
1101 "machhw. %0, %1, %2"
1102 [(set_attr "type" "imul3")])
1104 (define_insn "*machhw"
1105 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1106 (plus:SI (mult:SI (ashiftrt:SI
1107 (match_operand:SI 1 "gpc_reg_operand" "%r")
1108 (const_int 16))
1109 (ashiftrt:SI
1110 (match_operand:SI 2 "gpc_reg_operand" "r")
1111 (const_int 16)))
1112 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1113 "TARGET_MULHW"
1114 "machhw %0, %1, %2"
1115 [(set_attr "type" "imul3")])
1117 (define_insn "*machhwuc"
1118 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1119 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1120 (match_operand:SI 1 "gpc_reg_operand" "%r")
1121 (const_int 16))
1122 (lshiftrt:SI
1123 (match_operand:SI 2 "gpc_reg_operand" "r")
1124 (const_int 16)))
1125 (match_operand:SI 4 "gpc_reg_operand" "0"))
1126 (const_int 0)))
1127 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1128 (plus:SI (mult:SI (lshiftrt:SI
1129 (match_dup 1)
1130 (const_int 16))
1131 (lshiftrt:SI
1132 (match_dup 2)
1133 (const_int 16)))
1134 (match_dup 4)))]
1135 "TARGET_MULHW"
1136 "machhwu. %0, %1, %2"
1137 [(set_attr "type" "imul3")])
1139 (define_insn "*machhwu"
1140 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1141 (plus:SI (mult:SI (lshiftrt:SI
1142 (match_operand:SI 1 "gpc_reg_operand" "%r")
1143 (const_int 16))
1144 (lshiftrt:SI
1145 (match_operand:SI 2 "gpc_reg_operand" "r")
1146 (const_int 16)))
1147 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1148 "TARGET_MULHW"
1149 "machhwu %0, %1, %2"
1150 [(set_attr "type" "imul3")])
1152 (define_insn "*maclhwc"
1153 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1154 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1155 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1156 (sign_extend:SI
1157 (match_operand:HI 2 "gpc_reg_operand" "r")))
1158 (match_operand:SI 4 "gpc_reg_operand" "0"))
1159 (const_int 0)))
1160 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1161 (plus:SI (mult:SI (sign_extend:SI
1162 (match_dup 1))
1163 (sign_extend:SI
1164 (match_dup 2)))
1165 (match_dup 4)))]
1166 "TARGET_MULHW"
1167 "maclhw. %0, %1, %2"
1168 [(set_attr "type" "imul3")])
1170 (define_insn "*maclhw"
1171 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1172 (plus:SI (mult:SI (sign_extend:SI
1173 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1174 (sign_extend:SI
1175 (match_operand:HI 2 "gpc_reg_operand" "r")))
1176 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1177 "TARGET_MULHW"
1178 "maclhw %0, %1, %2"
1179 [(set_attr "type" "imul3")])
1181 (define_insn "*maclhwuc"
1182 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1183 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1184 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1185 (zero_extend:SI
1186 (match_operand:HI 2 "gpc_reg_operand" "r")))
1187 (match_operand:SI 4 "gpc_reg_operand" "0"))
1188 (const_int 0)))
1189 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1190 (plus:SI (mult:SI (zero_extend:SI
1191 (match_dup 1))
1192 (zero_extend:SI
1193 (match_dup 2)))
1194 (match_dup 4)))]
1195 "TARGET_MULHW"
1196 "maclhwu. %0, %1, %2"
1197 [(set_attr "type" "imul3")])
1199 (define_insn "*maclhwu"
1200 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1201 (plus:SI (mult:SI (zero_extend:SI
1202 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1203 (zero_extend:SI
1204 (match_operand:HI 2 "gpc_reg_operand" "r")))
1205 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1206 "TARGET_MULHW"
1207 "maclhwu %0, %1, %2"
1208 [(set_attr "type" "imul3")])
1210 (define_insn "*nmacchwc"
1211 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1212 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1213 (mult:SI (ashiftrt:SI
1214 (match_operand:SI 2 "gpc_reg_operand" "r")
1215 (const_int 16))
1216 (sign_extend:SI
1217 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1218 (const_int 0)))
1219 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1220 (minus:SI (match_dup 4)
1221 (mult:SI (ashiftrt:SI
1222 (match_dup 2)
1223 (const_int 16))
1224 (sign_extend:SI
1225 (match_dup 1)))))]
1226 "TARGET_MULHW"
1227 "nmacchw. %0, %1, %2"
1228 [(set_attr "type" "imul3")])
1230 (define_insn "*nmacchw"
1231 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1232 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1233 (mult:SI (ashiftrt:SI
1234 (match_operand:SI 2 "gpc_reg_operand" "r")
1235 (const_int 16))
1236 (sign_extend:SI
1237 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1238 "TARGET_MULHW"
1239 "nmacchw %0, %1, %2"
1240 [(set_attr "type" "imul3")])
1242 (define_insn "*nmachhwc"
1243 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1244 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1245 (mult:SI (ashiftrt:SI
1246 (match_operand:SI 1 "gpc_reg_operand" "%r")
1247 (const_int 16))
1248 (ashiftrt:SI
1249 (match_operand:SI 2 "gpc_reg_operand" "r")
1250 (const_int 16))))
1251 (const_int 0)))
1252 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1253 (minus:SI (match_dup 4)
1254 (mult:SI (ashiftrt:SI
1255 (match_dup 1)
1256 (const_int 16))
1257 (ashiftrt:SI
1258 (match_dup 2)
1259 (const_int 16)))))]
1260 "TARGET_MULHW"
1261 "nmachhw. %0, %1, %2"
1262 [(set_attr "type" "imul3")])
1264 (define_insn "*nmachhw"
1265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1266 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1267 (mult:SI (ashiftrt:SI
1268 (match_operand:SI 1 "gpc_reg_operand" "%r")
1269 (const_int 16))
1270 (ashiftrt:SI
1271 (match_operand:SI 2 "gpc_reg_operand" "r")
1272 (const_int 16)))))]
1273 "TARGET_MULHW"
1274 "nmachhw %0, %1, %2"
1275 [(set_attr "type" "imul3")])
1277 (define_insn "*nmaclhwc"
1278 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1279 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1280 (mult:SI (sign_extend:SI
1281 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1282 (sign_extend:SI
1283 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1284 (const_int 0)))
1285 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1286 (minus:SI (match_dup 4)
1287 (mult:SI (sign_extend:SI
1288 (match_dup 1))
1289 (sign_extend:SI
1290 (match_dup 2)))))]
1291 "TARGET_MULHW"
1292 "nmaclhw. %0, %1, %2"
1293 [(set_attr "type" "imul3")])
1295 (define_insn "*nmaclhw"
1296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1297 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1298 (mult:SI (sign_extend:SI
1299 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1300 (sign_extend:SI
1301 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1302 "TARGET_MULHW"
1303 "nmaclhw %0, %1, %2"
1304 [(set_attr "type" "imul3")])
1306 (define_insn "*mulchwc"
1307 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1308 (compare:CC (mult:SI (ashiftrt:SI
1309 (match_operand:SI 2 "gpc_reg_operand" "r")
1310 (const_int 16))
1311 (sign_extend:SI
1312 (match_operand:HI 1 "gpc_reg_operand" "r")))
1313 (const_int 0)))
1314 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1315 (mult:SI (ashiftrt:SI
1316 (match_dup 2)
1317 (const_int 16))
1318 (sign_extend:SI
1319 (match_dup 1))))]
1320 "TARGET_MULHW"
1321 "mulchw. %0, %1, %2"
1322 [(set_attr "type" "imul3")])
1324 (define_insn "*mulchw"
1325 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1326 (mult:SI (ashiftrt:SI
1327 (match_operand:SI 2 "gpc_reg_operand" "r")
1328 (const_int 16))
1329 (sign_extend:SI
1330 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1331 "TARGET_MULHW"
1332 "mulchw %0, %1, %2"
1333 [(set_attr "type" "imul3")])
1335 (define_insn "*mulchwuc"
1336 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1337 (compare:CC (mult:SI (lshiftrt:SI
1338 (match_operand:SI 2 "gpc_reg_operand" "r")
1339 (const_int 16))
1340 (zero_extend:SI
1341 (match_operand:HI 1 "gpc_reg_operand" "r")))
1342 (const_int 0)))
1343 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1344 (mult:SI (lshiftrt:SI
1345 (match_dup 2)
1346 (const_int 16))
1347 (zero_extend:SI
1348 (match_dup 1))))]
1349 "TARGET_MULHW"
1350 "mulchwu. %0, %1, %2"
1351 [(set_attr "type" "imul3")])
1353 (define_insn "*mulchwu"
1354 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1355 (mult:SI (lshiftrt:SI
1356 (match_operand:SI 2 "gpc_reg_operand" "r")
1357 (const_int 16))
1358 (zero_extend:SI
1359 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1360 "TARGET_MULHW"
1361 "mulchwu %0, %1, %2"
1362 [(set_attr "type" "imul3")])
1364 (define_insn "*mulhhwc"
1365 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1366 (compare:CC (mult:SI (ashiftrt:SI
1367 (match_operand:SI 1 "gpc_reg_operand" "%r")
1368 (const_int 16))
1369 (ashiftrt:SI
1370 (match_operand:SI 2 "gpc_reg_operand" "r")
1371 (const_int 16)))
1372 (const_int 0)))
1373 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1374 (mult:SI (ashiftrt:SI
1375 (match_dup 1)
1376 (const_int 16))
1377 (ashiftrt:SI
1378 (match_dup 2)
1379 (const_int 16))))]
1380 "TARGET_MULHW"
1381 "mulhhw. %0, %1, %2"
1382 [(set_attr "type" "imul3")])
1384 (define_insn "*mulhhw"
1385 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1386 (mult:SI (ashiftrt:SI
1387 (match_operand:SI 1 "gpc_reg_operand" "%r")
1388 (const_int 16))
1389 (ashiftrt:SI
1390 (match_operand:SI 2 "gpc_reg_operand" "r")
1391 (const_int 16))))]
1392 "TARGET_MULHW"
1393 "mulhhw %0, %1, %2"
1394 [(set_attr "type" "imul3")])
1396 (define_insn "*mulhhwuc"
1397 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1398 (compare:CC (mult:SI (lshiftrt:SI
1399 (match_operand:SI 1 "gpc_reg_operand" "%r")
1400 (const_int 16))
1401 (lshiftrt:SI
1402 (match_operand:SI 2 "gpc_reg_operand" "r")
1403 (const_int 16)))
1404 (const_int 0)))
1405 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1406 (mult:SI (lshiftrt:SI
1407 (match_dup 1)
1408 (const_int 16))
1409 (lshiftrt:SI
1410 (match_dup 2)
1411 (const_int 16))))]
1412 "TARGET_MULHW"
1413 "mulhhwu. %0, %1, %2"
1414 [(set_attr "type" "imul3")])
1416 (define_insn "*mulhhwu"
1417 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1418 (mult:SI (lshiftrt:SI
1419 (match_operand:SI 1 "gpc_reg_operand" "%r")
1420 (const_int 16))
1421 (lshiftrt:SI
1422 (match_operand:SI 2 "gpc_reg_operand" "r")
1423 (const_int 16))))]
1424 "TARGET_MULHW"
1425 "mulhhwu %0, %1, %2"
1426 [(set_attr "type" "imul3")])
1428 (define_insn "*mullhwc"
1429 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1430 (compare:CC (mult:SI (sign_extend:SI
1431 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1432 (sign_extend:SI
1433 (match_operand:HI 2 "gpc_reg_operand" "r")))
1434 (const_int 0)))
1435 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1436 (mult:SI (sign_extend:SI
1437 (match_dup 1))
1438 (sign_extend:SI
1439 (match_dup 2))))]
1440 "TARGET_MULHW"
1441 "mullhw. %0, %1, %2"
1442 [(set_attr "type" "imul3")])
1444 (define_insn "*mullhw"
1445 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1446 (mult:SI (sign_extend:SI
1447 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1448 (sign_extend:SI
1449 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1450 "TARGET_MULHW"
1451 "mullhw %0, %1, %2"
1452 [(set_attr "type" "imul3")])
1454 (define_insn "*mullhwuc"
1455 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1456 (compare:CC (mult:SI (zero_extend:SI
1457 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1458 (zero_extend:SI
1459 (match_operand:HI 2 "gpc_reg_operand" "r")))
1460 (const_int 0)))
1461 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1462 (mult:SI (zero_extend:SI
1463 (match_dup 1))
1464 (zero_extend:SI
1465 (match_dup 2))))]
1466 "TARGET_MULHW"
1467 "mullhwu. %0, %1, %2"
1468 [(set_attr "type" "imul3")])
1470 (define_insn "*mullhwu"
1471 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1472 (mult:SI (zero_extend:SI
1473 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1474 (zero_extend:SI
1475 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1476 "TARGET_MULHW"
1477 "mullhwu %0, %1, %2"
1478 [(set_attr "type" "imul3")])
1479 \f
1480 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1481 (define_insn "dlmzb"
1482 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1483 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1484 (match_operand:SI 2 "gpc_reg_operand" "r")]
1485 UNSPEC_DLMZB_CR))
1486 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1487 (unspec:SI [(match_dup 1)
1488 (match_dup 2)]
1489 UNSPEC_DLMZB))]
1490 "TARGET_DLMZB"
1491 "dlmzb. %0, %1, %2")
1493 (define_expand "strlensi"
1494 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1495 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1496 (match_operand:QI 2 "const_int_operand" "")
1497 (match_operand 3 "const_int_operand" "")]
1498 UNSPEC_DLMZB_STRLEN))
1499 (clobber (match_scratch:CC 4 "=x"))]
1500 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1501 {
1502 rtx result = operands[0];
1503 rtx src = operands[1];
1504 rtx search_char = operands[2];
1505 rtx align = operands[3];
1506 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1507 rtx loop_label, end_label, mem, cr0, cond;
1508 if (search_char != const0_rtx
1509 || GET_CODE (align) != CONST_INT
1510 || INTVAL (align) < 8)
1511 FAIL;
1512 word1 = gen_reg_rtx (SImode);
1513 word2 = gen_reg_rtx (SImode);
1514 scratch_dlmzb = gen_reg_rtx (SImode);
1515 scratch_string = gen_reg_rtx (Pmode);
1516 loop_label = gen_label_rtx ();
1517 end_label = gen_label_rtx ();
1518 addr = force_reg (Pmode, XEXP (src, 0));
1519 emit_move_insn (scratch_string, addr);
1520 emit_label (loop_label);
1521 mem = change_address (src, SImode, scratch_string);
1522 emit_move_insn (word1, mem);
1523 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1524 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1525 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1526 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1527 emit_jump_insn (gen_rtx_SET (VOIDmode,
1528 pc_rtx,
1529 gen_rtx_IF_THEN_ELSE (VOIDmode,
1530 cond,
1531 gen_rtx_LABEL_REF
1532 (VOIDmode,
1533 end_label),
1534 pc_rtx)));
1535 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1536 emit_jump_insn (gen_rtx_SET (VOIDmode,
1537 pc_rtx,
1538 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1539 emit_barrier ();
1540 emit_label (end_label);
1541 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1542 emit_insn (gen_subsi3 (result, scratch_string, addr));
1543 emit_insn (gen_subsi3 (result, result, const1_rtx));
1544 DONE;
1545 })
1546 \f
1547 (define_split
1548 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1549 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1550 (const_int 0)))
1551 (set (match_operand:SI 0 "gpc_reg_operand" "")
1552 (sign_extend:SI (match_dup 1)))]
1553 "reload_completed"
1554 [(set (match_dup 0)
1555 (sign_extend:SI (match_dup 1)))
1556 (set (match_dup 2)
1557 (compare:CC (match_dup 0)
1558 (const_int 0)))]
1559 "")
1561 ;; Fixed-point arithmetic insns.
1563 (define_expand "add<mode>3"
1564 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1565 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1566 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1567 ""
1568 {
1569 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1570 {
1571 if (non_short_cint_operand (operands[2], DImode))
1572 FAIL;
1573 }
1574 else if (GET_CODE (operands[2]) == CONST_INT
1575 && ! add_operand (operands[2], <MODE>mode))
1576 {
1577 rtx tmp = ((!can_create_pseudo_p ()
1578 || rtx_equal_p (operands[0], operands[1]))
1579 ? operands[0] : gen_reg_rtx (<MODE>mode));
1581 HOST_WIDE_INT val = INTVAL (operands[2]);
1582 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1583 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1585 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1586 FAIL;
1588 /* The ordering here is important for the prolog expander.
1589 When space is allocated from the stack, adding 'low' first may
1590 produce a temporary deallocation (which would be bad). */
1591 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1592 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1593 DONE;
1594 }
1595 })
1597 ;; Discourage ai/addic because of carry but provide it in an alternative
1598 ;; allowing register zero as source.
1599 (define_insn "*add<mode>3_internal1"
1600 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1601 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1602 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1603 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1604 "@
1605 {cax|add} %0,%1,%2
1606 {cal %0,%2(%1)|addi %0,%1,%2}
1607 {ai|addic} %0,%1,%2
1608 {cau|addis} %0,%1,%v2"
1609 [(set_attr "length" "4,4,4,4")])
1611 (define_insn "addsi3_high"
1612 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1613 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1614 (high:SI (match_operand 2 "" ""))))]
1615 "TARGET_MACHO && !TARGET_64BIT"
1616 "{cau|addis} %0,%1,ha16(%2)"
1617 [(set_attr "length" "4")])
1619 (define_insn "*add<mode>3_internal2"
1620 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1621 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1622 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1623 (const_int 0)))
1624 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1625 ""
1626 "@
1627 {cax.|add.} %3,%1,%2
1628 {ai.|addic.} %3,%1,%2
1629 #
1630 #"
1631 [(set_attr "type" "fast_compare,compare,compare,compare")
1632 (set_attr "length" "4,4,8,8")])
1634 (define_split
1635 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1636 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1637 (match_operand:GPR 2 "reg_or_short_operand" ""))
1638 (const_int 0)))
1639 (clobber (match_scratch:GPR 3 ""))]
1640 "reload_completed"
1641 [(set (match_dup 3)
1642 (plus:GPR (match_dup 1)
1643 (match_dup 2)))
1644 (set (match_dup 0)
1645 (compare:CC (match_dup 3)
1646 (const_int 0)))]
1647 "")
1649 (define_insn "*add<mode>3_internal3"
1650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1651 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1652 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1653 (const_int 0)))
1654 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1655 (plus:P (match_dup 1)
1656 (match_dup 2)))]
1657 ""
1658 "@
1659 {cax.|add.} %0,%1,%2
1660 {ai.|addic.} %0,%1,%2
1661 #
1662 #"
1663 [(set_attr "type" "fast_compare,compare,compare,compare")
1664 (set_attr "length" "4,4,8,8")])
1666 (define_split
1667 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1668 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1669 (match_operand:P 2 "reg_or_short_operand" ""))
1670 (const_int 0)))
1671 (set (match_operand:P 0 "gpc_reg_operand" "")
1672 (plus:P (match_dup 1) (match_dup 2)))]
1673 "reload_completed"
1674 [(set (match_dup 0)
1675 (plus:P (match_dup 1)
1676 (match_dup 2)))
1677 (set (match_dup 3)
1678 (compare:CC (match_dup 0)
1679 (const_int 0)))]
1680 "")
1682 ;; Split an add that we can't do in one insn into two insns, each of which
1683 ;; does one 16-bit part. This is used by combine. Note that the low-order
1684 ;; add should be last in case the result gets used in an address.
1686 (define_split
1687 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1688 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1689 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1690 ""
1691 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1692 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1693 {
1694 HOST_WIDE_INT val = INTVAL (operands[2]);
1695 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1696 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1698 operands[4] = GEN_INT (low);
1699 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1700 operands[3] = GEN_INT (rest);
1701 else if (can_create_pseudo_p ())
1702 {
1703 operands[3] = gen_reg_rtx (DImode);
1704 emit_move_insn (operands[3], operands[2]);
1705 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1706 DONE;
1707 }
1708 else
1709 FAIL;
1710 })
1712 (define_insn "one_cmpl<mode>2"
1713 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1714 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1715 ""
1716 "nor %0,%1,%1")
1718 (define_insn ""
1719 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1720 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1721 (const_int 0)))
1722 (clobber (match_scratch:P 2 "=r,r"))]
1723 ""
1724 "@
1725 nor. %2,%1,%1
1726 #"
1727 [(set_attr "type" "fast_compare,compare")
1728 (set_attr "length" "4,8")])
1730 (define_split
1731 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1732 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1733 (const_int 0)))
1734 (clobber (match_scratch:P 2 ""))]
1735 "reload_completed"
1736 [(set (match_dup 2)
1737 (not:P (match_dup 1)))
1738 (set (match_dup 0)
1739 (compare:CC (match_dup 2)
1740 (const_int 0)))]
1741 "")
1743 (define_insn ""
1744 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1745 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1746 (const_int 0)))
1747 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1748 (not:P (match_dup 1)))]
1749 ""
1750 "@
1751 nor. %0,%1,%1
1752 #"
1753 [(set_attr "type" "fast_compare,compare")
1754 (set_attr "length" "4,8")])
1756 (define_split
1757 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1758 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1759 (const_int 0)))
1760 (set (match_operand:P 0 "gpc_reg_operand" "")
1761 (not:P (match_dup 1)))]
1762 "reload_completed"
1763 [(set (match_dup 0)
1764 (not:P (match_dup 1)))
1765 (set (match_dup 2)
1766 (compare:CC (match_dup 0)
1767 (const_int 0)))]
1768 "")
1770 (define_insn ""
1771 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1772 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1773 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1774 "! TARGET_POWERPC"
1775 "{sf%I1|subf%I1c} %0,%2,%1")
1777 (define_insn ""
1778 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1779 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1780 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1781 "TARGET_POWERPC"
1782 "@
1783 subf %0,%2,%1
1784 subfic %0,%2,%1")
1786 (define_insn ""
1787 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1788 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1789 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1790 (const_int 0)))
1791 (clobber (match_scratch:SI 3 "=r,r"))]
1792 "! TARGET_POWERPC"
1793 "@
1794 {sf.|subfc.} %3,%2,%1
1795 #"
1796 [(set_attr "type" "compare")
1797 (set_attr "length" "4,8")])
1799 (define_insn ""
1800 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1801 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1802 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1803 (const_int 0)))
1804 (clobber (match_scratch:P 3 "=r,r"))]
1805 "TARGET_POWERPC"
1806 "@
1807 subf. %3,%2,%1
1808 #"
1809 [(set_attr "type" "fast_compare")
1810 (set_attr "length" "4,8")])
1812 (define_split
1813 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1814 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1815 (match_operand:P 2 "gpc_reg_operand" ""))
1816 (const_int 0)))
1817 (clobber (match_scratch:P 3 ""))]
1818 "reload_completed"
1819 [(set (match_dup 3)
1820 (minus:P (match_dup 1)
1821 (match_dup 2)))
1822 (set (match_dup 0)
1823 (compare:CC (match_dup 3)
1824 (const_int 0)))]
1825 "")
1827 (define_insn ""
1828 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1829 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1830 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1831 (const_int 0)))
1832 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1833 (minus:SI (match_dup 1) (match_dup 2)))]
1834 "! TARGET_POWERPC"
1835 "@
1836 {sf.|subfc.} %0,%2,%1
1837 #"
1838 [(set_attr "type" "compare")
1839 (set_attr "length" "4,8")])
1841 (define_insn ""
1842 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1843 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1844 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1845 (const_int 0)))
1846 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1847 (minus:P (match_dup 1)
1848 (match_dup 2)))]
1849 "TARGET_POWERPC"
1850 "@
1851 subf. %0,%2,%1
1852 #"
1853 [(set_attr "type" "fast_compare")
1854 (set_attr "length" "4,8")])
1856 (define_split
1857 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1858 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1859 (match_operand:P 2 "gpc_reg_operand" ""))
1860 (const_int 0)))
1861 (set (match_operand:P 0 "gpc_reg_operand" "")
1862 (minus:P (match_dup 1)
1863 (match_dup 2)))]
1864 "reload_completed"
1865 [(set (match_dup 0)
1866 (minus:P (match_dup 1)
1867 (match_dup 2)))
1868 (set (match_dup 3)
1869 (compare:CC (match_dup 0)
1870 (const_int 0)))]
1871 "")
1873 (define_expand "sub<mode>3"
1874 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1875 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1876 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1877 ""
1878 "
1879 {
1880 if (GET_CODE (operands[2]) == CONST_INT)
1881 {
1882 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1883 negate_rtx (<MODE>mode, operands[2])));
1884 DONE;
1885 }
1886 }")
1888 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1889 ;; instruction and some auxiliary computations. Then we just have a single
1890 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1891 ;; combine.
1893 (define_expand "sminsi3"
1894 [(set (match_dup 3)
1895 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1896 (match_operand:SI 2 "reg_or_short_operand" ""))
1897 (const_int 0)
1898 (minus:SI (match_dup 2) (match_dup 1))))
1899 (set (match_operand:SI 0 "gpc_reg_operand" "")
1900 (minus:SI (match_dup 2) (match_dup 3)))]
1901 "TARGET_POWER || TARGET_ISEL"
1902 "
1903 {
1904 if (TARGET_ISEL)
1905 {
1906 operands[2] = force_reg (SImode, operands[2]);
1907 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1908 DONE;
1909 }
1911 operands[3] = gen_reg_rtx (SImode);
1912 }")
1914 (define_split
1915 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1916 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1917 (match_operand:SI 2 "reg_or_short_operand" "")))
1918 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1919 "TARGET_POWER"
1920 [(set (match_dup 3)
1921 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1922 (const_int 0)
1923 (minus:SI (match_dup 2) (match_dup 1))))
1924 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1925 "")
1927 (define_expand "smaxsi3"
1928 [(set (match_dup 3)
1929 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1930 (match_operand:SI 2 "reg_or_short_operand" ""))
1931 (const_int 0)
1932 (minus:SI (match_dup 2) (match_dup 1))))
1933 (set (match_operand:SI 0 "gpc_reg_operand" "")
1934 (plus:SI (match_dup 3) (match_dup 1)))]
1935 "TARGET_POWER || TARGET_ISEL"
1936 "
1937 {
1938 if (TARGET_ISEL)
1939 {
1940 operands[2] = force_reg (SImode, operands[2]);
1941 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1942 DONE;
1943 }
1944 operands[3] = gen_reg_rtx (SImode);
1945 }")
1947 (define_split
1948 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1949 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1950 (match_operand:SI 2 "reg_or_short_operand" "")))
1951 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1952 "TARGET_POWER"
1953 [(set (match_dup 3)
1954 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1955 (const_int 0)
1956 (minus:SI (match_dup 2) (match_dup 1))))
1957 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1958 "")
1960 (define_expand "uminsi3"
1961 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1962 (match_dup 5)))
1963 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1964 (match_dup 5)))
1965 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1966 (const_int 0)
1967 (minus:SI (match_dup 4) (match_dup 3))))
1968 (set (match_operand:SI 0 "gpc_reg_operand" "")
1969 (minus:SI (match_dup 2) (match_dup 3)))]
1970 "TARGET_POWER || TARGET_ISEL"
1971 "
1972 {
1973 if (TARGET_ISEL)
1974 {
1975 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1976 DONE;
1977 }
1978 operands[3] = gen_reg_rtx (SImode);
1979 operands[4] = gen_reg_rtx (SImode);
1980 operands[5] = GEN_INT (-2147483647 - 1);
1981 }")
1983 (define_expand "umaxsi3"
1984 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1985 (match_dup 5)))
1986 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1987 (match_dup 5)))
1988 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1989 (const_int 0)
1990 (minus:SI (match_dup 4) (match_dup 3))))
1991 (set (match_operand:SI 0 "gpc_reg_operand" "")
1992 (plus:SI (match_dup 3) (match_dup 1)))]
1993 "TARGET_POWER || TARGET_ISEL"
1994 "
1995 {
1996 if (TARGET_ISEL)
1997 {
1998 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1999 DONE;
2000 }
2001 operands[3] = gen_reg_rtx (SImode);
2002 operands[4] = gen_reg_rtx (SImode);
2003 operands[5] = GEN_INT (-2147483647 - 1);
2004 }")
2006 (define_insn ""
2007 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2008 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
2009 (match_operand:SI 2 "reg_or_short_operand" "rI"))
2010 (const_int 0)
2011 (minus:SI (match_dup 2) (match_dup 1))))]
2012 "TARGET_POWER"
2013 "doz%I2 %0,%1,%2")
2015 (define_insn ""
2016 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2017 (compare:CC
2018 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2019 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2020 (const_int 0)
2021 (minus:SI (match_dup 2) (match_dup 1)))
2022 (const_int 0)))
2023 (clobber (match_scratch:SI 3 "=r,r"))]
2024 "TARGET_POWER"
2025 "@
2026 doz%I2. %3,%1,%2
2027 #"
2028 [(set_attr "type" "delayed_compare")
2029 (set_attr "length" "4,8")])
2031 (define_split
2032 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2033 (compare:CC
2034 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2035 (match_operand:SI 2 "reg_or_short_operand" ""))
2036 (const_int 0)
2037 (minus:SI (match_dup 2) (match_dup 1)))
2038 (const_int 0)))
2039 (clobber (match_scratch:SI 3 ""))]
2040 "TARGET_POWER && reload_completed"
2041 [(set (match_dup 3)
2042 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2043 (const_int 0)
2044 (minus:SI (match_dup 2) (match_dup 1))))
2045 (set (match_dup 0)
2046 (compare:CC (match_dup 3)
2047 (const_int 0)))]
2048 "")
2050 (define_insn ""
2051 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2052 (compare:CC
2053 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2054 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2055 (const_int 0)
2056 (minus:SI (match_dup 2) (match_dup 1)))
2057 (const_int 0)))
2058 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2059 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2060 (const_int 0)
2061 (minus:SI (match_dup 2) (match_dup 1))))]
2062 "TARGET_POWER"
2063 "@
2064 doz%I2. %0,%1,%2
2065 #"
2066 [(set_attr "type" "delayed_compare")
2067 (set_attr "length" "4,8")])
2069 (define_split
2070 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2071 (compare:CC
2072 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2073 (match_operand:SI 2 "reg_or_short_operand" ""))
2074 (const_int 0)
2075 (minus:SI (match_dup 2) (match_dup 1)))
2076 (const_int 0)))
2077 (set (match_operand:SI 0 "gpc_reg_operand" "")
2078 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2079 (const_int 0)
2080 (minus:SI (match_dup 2) (match_dup 1))))]
2081 "TARGET_POWER && reload_completed"
2082 [(set (match_dup 0)
2083 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2084 (const_int 0)
2085 (minus:SI (match_dup 2) (match_dup 1))))
2086 (set (match_dup 3)
2087 (compare:CC (match_dup 0)
2088 (const_int 0)))]
2089 "")
2091 ;; We don't need abs with condition code because such comparisons should
2092 ;; never be done.
2093 (define_expand "abssi2"
2094 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2095 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2096 ""
2097 "
2098 {
2099 if (TARGET_ISEL)
2100 {
2101 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2102 DONE;
2103 }
2104 else if (! TARGET_POWER)
2105 {
2106 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2107 DONE;
2108 }
2109 }")
2111 (define_insn "*abssi2_power"
2112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2113 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2114 "TARGET_POWER"
2115 "abs %0,%1")
2117 (define_insn_and_split "abs<mode>2_isel"
2118 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2119 (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
2120 (clobber (match_scratch:GPR 2 "=&b"))
2121 (clobber (match_scratch:CC 3 "=y"))]
2122 "TARGET_ISEL"
2123 "#"
2124 "&& reload_completed"
2125 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2126 (set (match_dup 3)
2127 (compare:CC (match_dup 1)
2128 (const_int 0)))
2129 (set (match_dup 0)
2130 (if_then_else:GPR (lt (match_dup 3)
2131 (const_int 0))
2132 (match_dup 2)
2133 (match_dup 1)))]
2134 "")
2136 (define_insn_and_split "nabs<mode>2_isel"
2137 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2138 (neg:GPR (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b"))))
2139 (clobber (match_scratch:GPR 2 "=&b"))
2140 (clobber (match_scratch:CC 3 "=y"))]
2141 "TARGET_ISEL"
2142 "#"
2143 "&& reload_completed"
2144 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2145 (set (match_dup 3)
2146 (compare:CC (match_dup 1)
2147 (const_int 0)))
2148 (set (match_dup 0)
2149 (if_then_else:GPR (lt (match_dup 3)
2150 (const_int 0))
2151 (match_dup 1)
2152 (match_dup 2)))]
2153 "")
2155 (define_insn_and_split "abssi2_nopower"
2156 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2157 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2158 (clobber (match_scratch:SI 2 "=&r,&r"))]
2159 "! TARGET_POWER && ! TARGET_ISEL"
2160 "#"
2161 "&& reload_completed"
2162 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2163 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2164 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2165 "")
2167 (define_insn "*nabs_power"
2168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2169 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2170 "TARGET_POWER"
2171 "nabs %0,%1")
2173 (define_insn_and_split "*nabs_nopower"
2174 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2175 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2176 (clobber (match_scratch:SI 2 "=&r,&r"))]
2177 "! TARGET_POWER"
2178 "#"
2179 "&& reload_completed"
2180 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2181 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2182 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2183 "")
2185 (define_expand "neg<mode>2"
2186 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2187 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2188 ""
2189 "")
2191 (define_insn "*neg<mode>2_internal"
2192 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2193 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2194 ""
2195 "neg %0,%1")
2197 (define_insn ""
2198 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2199 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2200 (const_int 0)))
2201 (clobber (match_scratch:P 2 "=r,r"))]
2202 ""
2203 "@
2204 neg. %2,%1
2205 #"
2206 [(set_attr "type" "fast_compare")
2207 (set_attr "length" "4,8")])
2209 (define_split
2210 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2211 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2212 (const_int 0)))
2213 (clobber (match_scratch:P 2 ""))]
2214 "reload_completed"
2215 [(set (match_dup 2)
2216 (neg:P (match_dup 1)))
2217 (set (match_dup 0)
2218 (compare:CC (match_dup 2)
2219 (const_int 0)))]
2220 "")
2222 (define_insn ""
2223 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2224 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2225 (const_int 0)))
2226 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2227 (neg:P (match_dup 1)))]
2228 ""
2229 "@
2230 neg. %0,%1
2231 #"
2232 [(set_attr "type" "fast_compare")
2233 (set_attr "length" "4,8")])
2235 (define_split
2236 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2237 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2238 (const_int 0)))
2239 (set (match_operand:P 0 "gpc_reg_operand" "")
2240 (neg:P (match_dup 1)))]
2241 "reload_completed"
2242 [(set (match_dup 0)
2243 (neg:P (match_dup 1)))
2244 (set (match_dup 2)
2245 (compare:CC (match_dup 0)
2246 (const_int 0)))]
2247 "")
2249 (define_insn "clz<mode>2"
2250 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2251 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2252 ""
2253 "{cntlz|cntlz<wd>} %0,%1"
2254 [(set_attr "type" "cntlz")])
2256 (define_expand "ctz<mode>2"
2257 [(set (match_dup 2)
2258 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2259 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2260 (match_dup 2)))
2261 (clobber (scratch:CC))])
2262 (set (match_dup 4) (clz:GPR (match_dup 3)))
2263 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2264 (minus:GPR (match_dup 5) (match_dup 4)))]
2265 ""
2266 {
2267 operands[2] = gen_reg_rtx (<MODE>mode);
2268 operands[3] = gen_reg_rtx (<MODE>mode);
2269 operands[4] = gen_reg_rtx (<MODE>mode);
2270 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2271 })
2273 (define_expand "ffs<mode>2"
2274 [(set (match_dup 2)
2275 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2276 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2277 (match_dup 2)))
2278 (clobber (scratch:CC))])
2279 (set (match_dup 4) (clz:GPR (match_dup 3)))
2280 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2281 (minus:GPR (match_dup 5) (match_dup 4)))]
2282 ""
2283 {
2284 operands[2] = gen_reg_rtx (<MODE>mode);
2285 operands[3] = gen_reg_rtx (<MODE>mode);
2286 operands[4] = gen_reg_rtx (<MODE>mode);
2287 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2288 })
2290 (define_insn "popcntb<mode>2"
2291 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2292 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2293 UNSPEC_POPCNTB))]
2294 "TARGET_POPCNTB"
2295 "popcntb %0,%1")
2297 (define_insn "popcntd<mode>2"
2298 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2299 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2300 "TARGET_POPCNTD"
2301 "popcnt<wd> %0,%1")
2303 (define_expand "popcount<mode>2"
2304 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2305 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2306 "TARGET_POPCNTB || TARGET_POPCNTD"
2307 {
2308 rs6000_emit_popcount (operands[0], operands[1]);
2309 DONE;
2310 })
2312 (define_insn "parity<mode>2_cmpb"
2313 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2314 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2315 "TARGET_CMPB && TARGET_POPCNTB"
2316 "prty<wd> %0,%1")
2318 (define_expand "parity<mode>2"
2319 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2320 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2321 "TARGET_POPCNTB"
2322 {
2323 rs6000_emit_parity (operands[0], operands[1]);
2324 DONE;
2325 })
2327 ;; Since the hardware zeros the upper part of the register, save generating the
2328 ;; AND immediate if we are converting to unsigned
2329 (define_insn "*bswaphi2_extenddi"
2330 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2331 (zero_extend:DI
2332 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2333 "TARGET_POWERPC64"
2334 "lhbrx %0,%y1"
2335 [(set_attr "length" "4")
2336 (set_attr "type" "load")])
2338 (define_insn "*bswaphi2_extendsi"
2339 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2340 (zero_extend:SI
2341 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2342 "TARGET_POWERPC"
2343 "lhbrx %0,%y1"
2344 [(set_attr "length" "4")
2345 (set_attr "type" "load")])
2347 (define_expand "bswaphi2"
2348 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2349 (bswap:HI
2350 (match_operand:HI 1 "reg_or_mem_operand" "")))
2351 (clobber (match_scratch:SI 2 ""))])]
2352 ""
2353 {
2354 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2355 operands[1] = force_reg (HImode, operands[1]);
2356 })
2358 (define_insn "bswaphi2_internal"
2359 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2360 (bswap:HI
2361 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2362 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2363 "TARGET_POWERPC"
2364 "@
2365 lhbrx %0,%y1
2366 sthbrx %1,%y0
2367 #"
2368 [(set_attr "length" "4,4,12")
2369 (set_attr "type" "load,store,*")])
2371 (define_split
2372 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2373 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2374 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2375 "TARGET_POWERPC && reload_completed"
2376 [(set (match_dup 3)
2377 (zero_extract:SI (match_dup 4)
2378 (const_int 8)
2379 (const_int 16)))
2380 (set (match_dup 2)
2381 (and:SI (ashift:SI (match_dup 4)
2382 (const_int 8))
2383 (const_int 65280))) ;; 0xff00
2384 (set (match_dup 3)
2385 (ior:SI (match_dup 3)
2386 (match_dup 2)))]
2387 "
2388 {
2389 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2390 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2391 }")
2393 (define_insn "*bswapsi2_extenddi"
2394 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2395 (zero_extend:DI
2396 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2397 "TARGET_POWERPC64"
2398 "lwbrx %0,%y1"
2399 [(set_attr "length" "4")
2400 (set_attr "type" "load")])
2402 (define_expand "bswapsi2"
2403 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2404 (bswap:SI
2405 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2406 ""
2407 {
2408 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2409 operands[1] = force_reg (SImode, operands[1]);
2410 })
2412 (define_insn "*bswapsi2_internal"
2413 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2414 (bswap:SI
2415 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2416 ""
2417 "@
2418 {lbrx|lwbrx} %0,%y1
2419 {stbrx|stwbrx} %1,%y0
2420 #"
2421 [(set_attr "length" "4,4,12")
2422 (set_attr "type" "load,store,*")])
2424 (define_split
2425 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2426 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2427 "reload_completed"
2428 [(set (match_dup 0)
2429 (rotate:SI (match_dup 1) (const_int 8)))
2430 (set (zero_extract:SI (match_dup 0)
2431 (const_int 8)
2432 (const_int 0))
2433 (match_dup 1))
2434 (set (zero_extract:SI (match_dup 0)
2435 (const_int 8)
2436 (const_int 16))
2437 (rotate:SI (match_dup 1)
2438 (const_int 16)))]
2439 "")
2441 (define_expand "bswapdi2"
2442 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2443 (bswap:DI
2444 (match_operand:DI 1 "reg_or_mem_operand" "")))
2445 (clobber (match_scratch:DI 2 ""))
2446 (clobber (match_scratch:DI 3 ""))
2447 (clobber (match_scratch:DI 4 ""))])]
2448 ""
2449 {
2450 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2451 operands[1] = force_reg (DImode, operands[1]);
2453 if (!TARGET_POWERPC64)
2454 {
2455 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2456 that uses 64-bit registers needs the same scratch registers as 64-bit
2457 mode. */
2458 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2459 DONE;
2460 }
2461 })
2463 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2464 (define_insn "*bswapdi2_ldbrx"
2465 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2466 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2467 (clobber (match_scratch:DI 2 "=X,X,&r"))
2468 (clobber (match_scratch:DI 3 "=X,X,&r"))
2469 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2470 "TARGET_POWERPC64 && TARGET_LDBRX
2471 && (REG_P (operands[0]) || REG_P (operands[1]))"
2472 "@
2473 ldbrx %0,%y1
2474 stdbrx %1,%y0
2475 #"
2476 [(set_attr "length" "4,4,36")
2477 (set_attr "type" "load,store,*")])
2479 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2480 (define_insn "*bswapdi2_64bit"
2481 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2482 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2483 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2484 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2485 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2486 "TARGET_POWERPC64 && !TARGET_LDBRX
2487 && (REG_P (operands[0]) || REG_P (operands[1]))"
2488 "#"
2489 [(set_attr "length" "16,12,36")])
2491 (define_split
2492 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2493 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2494 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2495 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2496 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2497 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2498 [(const_int 0)]
2499 "
2500 {
2501 rtx dest = operands[0];
2502 rtx src = operands[1];
2503 rtx op2 = operands[2];
2504 rtx op3 = operands[3];
2505 rtx op4 = operands[4];
2506 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2507 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2508 rtx addr1;
2509 rtx addr2;
2510 rtx word_high;
2511 rtx word_low;
2513 addr1 = XEXP (src, 0);
2514 if (GET_CODE (addr1) == PLUS)
2515 {
2516 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2517 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2518 }
2519 else
2520 {
2521 emit_move_insn (op2, GEN_INT (4));
2522 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2523 }
2525 if (BYTES_BIG_ENDIAN)
2526 {
2527 word_high = change_address (src, SImode, addr1);
2528 word_low = change_address (src, SImode, addr2);
2529 }
2530 else
2531 {
2532 word_high = change_address (src, SImode, addr2);
2533 word_low = change_address (src, SImode, addr1);
2534 }
2536 emit_insn (gen_bswapsi2 (op3_32, word_low));
2537 emit_insn (gen_bswapsi2 (op4_32, word_high));
2538 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2539 emit_insn (gen_iordi3 (dest, dest, op4));
2540 }")
2542 (define_split
2543 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2544 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2545 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2546 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2547 (clobber (match_operand:DI 4 "" ""))]
2548 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2549 [(const_int 0)]
2550 "
2551 {
2552 rtx dest = operands[0];
2553 rtx src = operands[1];
2554 rtx op2 = operands[2];
2555 rtx op3 = operands[3];
2556 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2557 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2558 rtx addr1;
2559 rtx addr2;
2560 rtx word_high;
2561 rtx word_low;
2563 addr1 = XEXP (dest, 0);
2564 if (GET_CODE (addr1) == PLUS)
2565 {
2566 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2567 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2568 }
2569 else
2570 {
2571 emit_move_insn (op2, GEN_INT (4));
2572 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2573 }
2575 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2576 if (BYTES_BIG_ENDIAN)
2577 {
2578 word_high = change_address (dest, SImode, addr1);
2579 word_low = change_address (dest, SImode, addr2);
2580 emit_insn (gen_bswapsi2 (word_high, src_si));
2581 emit_insn (gen_bswapsi2 (word_low, op3_si));
2582 }
2583 else
2584 {
2585 word_high = change_address (dest, SImode, addr2);
2586 word_low = change_address (dest, SImode, addr1);
2587 emit_insn (gen_bswapsi2 (word_low, src_si));
2588 emit_insn (gen_bswapsi2 (word_high, op3_si));
2589 }
2590 }")
2592 (define_split
2593 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2594 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2595 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2596 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2597 (clobber (match_operand:DI 4 "" ""))]
2598 "TARGET_POWERPC64 && reload_completed"
2599 [(const_int 0)]
2600 "
2601 {
2602 rtx dest = operands[0];
2603 rtx src = operands[1];
2604 rtx op2 = operands[2];
2605 rtx op3 = operands[3];
2606 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2607 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2608 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2609 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2611 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2612 emit_insn (gen_bswapsi2 (dest_si, src_si));
2613 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2614 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2615 emit_insn (gen_iordi3 (dest, dest, op3));
2616 }")
2618 (define_insn "bswapdi2_32bit"
2619 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2620 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2621 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2622 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2623 "#"
2624 [(set_attr "length" "16,12,36")])
2626 (define_split
2627 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2628 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2629 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2630 "!TARGET_POWERPC64 && reload_completed"
2631 [(const_int 0)]
2632 "
2633 {
2634 rtx dest = operands[0];
2635 rtx src = operands[1];
2636 rtx op2 = operands[2];
2637 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2638 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2639 rtx addr1;
2640 rtx addr2;
2641 rtx word_high;
2642 rtx word_low;
2644 addr1 = XEXP (src, 0);
2645 if (GET_CODE (addr1) == PLUS)
2646 {
2647 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2648 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2649 }
2650 else
2651 {
2652 emit_move_insn (op2, GEN_INT (4));
2653 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2654 }
2656 if (BYTES_BIG_ENDIAN)
2657 {
2658 word_high = change_address (src, SImode, addr1);
2659 word_low = change_address (src, SImode, addr2);
2660 }
2661 else
2662 {
2663 word_high = change_address (src, SImode, addr2);
2664 word_low = change_address (src, SImode, addr1);
2665 }
2667 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2668 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2669 }")
2671 (define_split
2672 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2673 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2674 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2675 "!TARGET_POWERPC64 && reload_completed"
2676 [(const_int 0)]
2677 "
2678 {
2679 rtx dest = operands[0];
2680 rtx src = operands[1];
2681 rtx op2 = operands[2];
2682 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2683 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2684 rtx addr1;
2685 rtx addr2;
2686 rtx word_high;
2687 rtx word_low;
2689 addr1 = XEXP (dest, 0);
2690 if (GET_CODE (addr1) == PLUS)
2691 {
2692 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2693 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2694 }
2695 else
2696 {
2697 emit_move_insn (op2, GEN_INT (4));
2698 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2699 }
2701 if (BYTES_BIG_ENDIAN)
2702 {
2703 word_high = change_address (dest, SImode, addr1);
2704 word_low = change_address (dest, SImode, addr2);
2705 }
2706 else
2707 {
2708 word_high = change_address (dest, SImode, addr2);
2709 word_low = change_address (dest, SImode, addr1);
2710 }
2712 emit_insn (gen_bswapsi2 (word_high, src_low));
2713 emit_insn (gen_bswapsi2 (word_low, src_high));
2714 }")
2716 (define_split
2717 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2718 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2719 (clobber (match_operand:SI 2 "" ""))]
2720 "!TARGET_POWERPC64 && reload_completed"
2721 [(const_int 0)]
2722 "
2723 {
2724 rtx dest = operands[0];
2725 rtx src = operands[1];
2726 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2727 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2728 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2729 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2731 emit_insn (gen_bswapsi2 (dest_high, src_low));
2732 emit_insn (gen_bswapsi2 (dest_low, src_high));
2733 }")
2735 (define_expand "mulsi3"
2736 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2737 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2738 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2739 ""
2740 "
2741 {
2742 if (TARGET_POWER)
2743 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2744 else
2745 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2746 DONE;
2747 }")
2749 (define_insn "mulsi3_mq"
2750 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2751 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2752 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2753 (clobber (match_scratch:SI 3 "=q,q"))]
2754 "TARGET_POWER"
2755 "@
2756 {muls|mullw} %0,%1,%2
2757 {muli|mulli} %0,%1,%2"
2758 [(set (attr "type")
2759 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2760 (const_string "imul3")
2761 (match_operand:SI 2 "short_cint_operand" "")
2762 (const_string "imul2")]
2763 (const_string "imul")))])
2765 (define_insn "mulsi3_no_mq"
2766 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2767 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2768 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2769 "! TARGET_POWER"
2770 "@
2771 {muls|mullw} %0,%1,%2
2772 {muli|mulli} %0,%1,%2"
2773 [(set (attr "type")
2774 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2775 (const_string "imul3")
2776 (match_operand:SI 2 "short_cint_operand" "")
2777 (const_string "imul2")]
2778 (const_string "imul")))])
2780 (define_insn "*mulsi3_mq_internal1"
2781 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2782 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2783 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2784 (const_int 0)))
2785 (clobber (match_scratch:SI 3 "=r,r"))
2786 (clobber (match_scratch:SI 4 "=q,q"))]
2787 "TARGET_POWER"
2788 "@
2789 {muls.|mullw.} %3,%1,%2
2790 #"
2791 [(set_attr "type" "imul_compare")
2792 (set_attr "length" "4,8")])
2794 (define_split
2795 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2796 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2797 (match_operand:SI 2 "gpc_reg_operand" ""))
2798 (const_int 0)))
2799 (clobber (match_scratch:SI 3 ""))
2800 (clobber (match_scratch:SI 4 ""))]
2801 "TARGET_POWER && reload_completed"
2802 [(parallel [(set (match_dup 3)
2803 (mult:SI (match_dup 1) (match_dup 2)))
2804 (clobber (match_dup 4))])
2805 (set (match_dup 0)
2806 (compare:CC (match_dup 3)
2807 (const_int 0)))]
2808 "")
2810 (define_insn "*mulsi3_no_mq_internal1"
2811 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2812 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2813 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2814 (const_int 0)))
2815 (clobber (match_scratch:SI 3 "=r,r"))]
2816 "! TARGET_POWER"
2817 "@
2818 {muls.|mullw.} %3,%1,%2
2819 #"
2820 [(set_attr "type" "imul_compare")
2821 (set_attr "length" "4,8")])
2823 (define_split
2824 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2825 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2826 (match_operand:SI 2 "gpc_reg_operand" ""))
2827 (const_int 0)))
2828 (clobber (match_scratch:SI 3 ""))]
2829 "! TARGET_POWER && reload_completed"
2830 [(set (match_dup 3)
2831 (mult:SI (match_dup 1) (match_dup 2)))
2832 (set (match_dup 0)
2833 (compare:CC (match_dup 3)
2834 (const_int 0)))]
2835 "")
2837 (define_insn "*mulsi3_mq_internal2"
2838 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2839 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2840 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2841 (const_int 0)))
2842 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2843 (mult:SI (match_dup 1) (match_dup 2)))
2844 (clobber (match_scratch:SI 4 "=q,q"))]
2845 "TARGET_POWER"
2846 "@
2847 {muls.|mullw.} %0,%1,%2
2848 #"
2849 [(set_attr "type" "imul_compare")
2850 (set_attr "length" "4,8")])
2852 (define_split
2853 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2854 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2855 (match_operand:SI 2 "gpc_reg_operand" ""))
2856 (const_int 0)))
2857 (set (match_operand:SI 0 "gpc_reg_operand" "")
2858 (mult:SI (match_dup 1) (match_dup 2)))
2859 (clobber (match_scratch:SI 4 ""))]
2860 "TARGET_POWER && reload_completed"
2861 [(parallel [(set (match_dup 0)
2862 (mult:SI (match_dup 1) (match_dup 2)))
2863 (clobber (match_dup 4))])
2864 (set (match_dup 3)
2865 (compare:CC (match_dup 0)
2866 (const_int 0)))]
2867 "")
2869 (define_insn "*mulsi3_no_mq_internal2"
2870 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2871 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2872 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2873 (const_int 0)))
2874 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2875 (mult:SI (match_dup 1) (match_dup 2)))]
2876 "! TARGET_POWER"
2877 "@
2878 {muls.|mullw.} %0,%1,%2
2879 #"
2880 [(set_attr "type" "imul_compare")
2881 (set_attr "length" "4,8")])
2883 (define_split
2884 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2885 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2886 (match_operand:SI 2 "gpc_reg_operand" ""))
2887 (const_int 0)))
2888 (set (match_operand:SI 0 "gpc_reg_operand" "")
2889 (mult:SI (match_dup 1) (match_dup 2)))]
2890 "! TARGET_POWER && reload_completed"
2891 [(set (match_dup 0)
2892 (mult:SI (match_dup 1) (match_dup 2)))
2893 (set (match_dup 3)
2894 (compare:CC (match_dup 0)
2895 (const_int 0)))]
2896 "")
2898 ;; Operand 1 is divided by operand 2; quotient goes to operand
2899 ;; 0 and remainder to operand 3.
2900 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2902 (define_expand "divmodsi4"
2903 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2904 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2905 (match_operand:SI 2 "gpc_reg_operand" "")))
2906 (set (match_operand:SI 3 "register_operand" "")
2907 (mod:SI (match_dup 1) (match_dup 2)))])]
2908 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2909 "
2910 {
2911 if (! TARGET_POWER && ! TARGET_POWERPC)
2912 {
2913 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2914 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2915 emit_insn (gen_divss_call ());
2916 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2917 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2918 DONE;
2919 }
2920 }")
2922 (define_insn "*divmodsi4_internal"
2923 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2924 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2925 (match_operand:SI 2 "gpc_reg_operand" "r")))
2926 (set (match_operand:SI 3 "register_operand" "=q")
2927 (mod:SI (match_dup 1) (match_dup 2)))]
2928 "TARGET_POWER"
2929 "divs %0,%1,%2"
2930 [(set_attr "type" "idiv")])
2932 (define_expand "udiv<mode>3"
2933 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2934 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2935 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2936 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2937 "
2938 {
2939 if (! TARGET_POWER && ! TARGET_POWERPC)
2940 {
2941 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2942 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2943 emit_insn (gen_quous_call ());
2944 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2945 DONE;
2946 }
2947 else if (TARGET_POWER)
2948 {
2949 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2950 DONE;
2951 }
2952 }")
2954 (define_insn "udivsi3_mq"
2955 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2956 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2957 (match_operand:SI 2 "gpc_reg_operand" "r")))
2958 (clobber (match_scratch:SI 3 "=q"))]
2959 "TARGET_POWERPC && TARGET_POWER"
2960 "divwu %0,%1,%2"
2961 [(set_attr "type" "idiv")])
2963 (define_insn "*udivsi3_no_mq"
2964 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2965 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2966 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2967 "TARGET_POWERPC && ! TARGET_POWER"
2968 "div<wd>u %0,%1,%2"
2969 [(set (attr "type")
2970 (cond [(match_operand:SI 0 "" "")
2971 (const_string "idiv")]
2972 (const_string "ldiv")))])
2975 ;; For powers of two we can do srai/aze for divide and then adjust for
2976 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2977 ;; used; for PowerPC, force operands into register and do a normal divide;
2978 ;; for AIX common-mode, use quoss call on register operands.
2979 (define_expand "div<mode>3"
2980 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2981 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2982 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2983 ""
2984 "
2985 {
2986 if (GET_CODE (operands[2]) == CONST_INT
2987 && INTVAL (operands[2]) > 0
2988 && exact_log2 (INTVAL (operands[2])) >= 0)
2989 ;
2990 else if (TARGET_POWERPC)
2991 {
2992 operands[2] = force_reg (<MODE>mode, operands[2]);
2993 if (TARGET_POWER)
2994 {
2995 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2996 DONE;
2997 }
2998 }
2999 else if (TARGET_POWER)
3000 FAIL;
3001 else
3002 {
3003 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3004 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3005 emit_insn (gen_quoss_call ());
3006 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3007 DONE;
3008 }
3009 }")
3011 (define_insn "divsi3_mq"
3012 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3013 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3014 (match_operand:SI 2 "gpc_reg_operand" "r")))
3015 (clobber (match_scratch:SI 3 "=q"))]
3016 "TARGET_POWERPC && TARGET_POWER"
3017 "divw %0,%1,%2"
3018 [(set_attr "type" "idiv")])
3020 (define_insn "*div<mode>3_no_mq"
3021 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3022 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3023 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
3024 "TARGET_POWERPC && ! TARGET_POWER"
3025 "div<wd> %0,%1,%2"
3026 [(set (attr "type")
3027 (cond [(match_operand:SI 0 "" "")
3028 (const_string "idiv")]
3029 (const_string "ldiv")))])
3031 (define_expand "mod<mode>3"
3032 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
3033 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
3034 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
3035 ""
3036 "
3037 {
3038 int i;
3039 rtx temp1;
3040 rtx temp2;
3042 if (GET_CODE (operands[2]) != CONST_INT
3043 || INTVAL (operands[2]) <= 0
3044 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
3045 FAIL;
3047 temp1 = gen_reg_rtx (<MODE>mode);
3048 temp2 = gen_reg_rtx (<MODE>mode);
3050 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
3051 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
3052 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
3053 DONE;
3054 }")
3056 (define_insn ""
3057 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3058 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3059 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
3060 ""
3061 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
3062 [(set_attr "type" "two")
3063 (set_attr "length" "8")])
3065 (define_insn ""
3066 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3067 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3068 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3069 (const_int 0)))
3070 (clobber (match_scratch:P 3 "=r,r"))]
3071 ""
3072 "@
3073 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
3074 #"
3075 [(set_attr "type" "compare")
3076 (set_attr "length" "8,12")
3077 (set_attr "cell_micro" "not")])
3079 (define_split
3080 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3081 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3082 (match_operand:GPR 2 "exact_log2_cint_operand"
3083 ""))
3084 (const_int 0)))
3085 (clobber (match_scratch:GPR 3 ""))]
3086 "reload_completed"
3087 [(set (match_dup 3)
3088 (div:<MODE> (match_dup 1) (match_dup 2)))
3089 (set (match_dup 0)
3090 (compare:CC (match_dup 3)
3091 (const_int 0)))]
3092 "")
3094 (define_insn ""
3095 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3096 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3097 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3098 (const_int 0)))
3099 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
3100 (div:P (match_dup 1) (match_dup 2)))]
3101 ""
3102 "@
3103 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
3104 #"
3105 [(set_attr "type" "compare")
3106 (set_attr "length" "8,12")
3107 (set_attr "cell_micro" "not")])
3109 (define_split
3110 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3111 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3112 (match_operand:GPR 2 "exact_log2_cint_operand"
3113 ""))
3114 (const_int 0)))
3115 (set (match_operand:GPR 0 "gpc_reg_operand" "")
3116 (div:GPR (match_dup 1) (match_dup 2)))]
3117 "reload_completed"
3118 [(set (match_dup 0)
3119 (div:<MODE> (match_dup 1) (match_dup 2)))
3120 (set (match_dup 3)
3121 (compare:CC (match_dup 0)
3122 (const_int 0)))]
3123 "")
3125 (define_insn ""
3126 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3127 (udiv:SI
3128 (plus:DI (ashift:DI
3129 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3130 (const_int 32))
3131 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
3132 (match_operand:SI 3 "gpc_reg_operand" "r")))
3133 (set (match_operand:SI 2 "register_operand" "=*q")
3134 (umod:SI
3135 (plus:DI (ashift:DI
3136 (zero_extend:DI (match_dup 1)) (const_int 32))
3137 (zero_extend:DI (match_dup 4)))
3138 (match_dup 3)))]
3139 "TARGET_POWER"
3140 "div %0,%1,%3"
3141 [(set_attr "type" "idiv")])
3143 ;; To do unsigned divide we handle the cases of the divisor looking like a
3144 ;; negative number. If it is a constant that is less than 2**31, we don't
3145 ;; have to worry about the branches. So make a few subroutines here.
3146 ;;
3147 ;; First comes the normal case.
3148 (define_expand "udivmodsi4_normal"
3149 [(set (match_dup 4) (const_int 0))
3150 (parallel [(set (match_operand:SI 0 "" "")
3151 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3152 (const_int 32))
3153 (zero_extend:DI (match_operand:SI 1 "" "")))
3154 (match_operand:SI 2 "" "")))
3155 (set (match_operand:SI 3 "" "")
3156 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3157 (const_int 32))
3158 (zero_extend:DI (match_dup 1)))
3159 (match_dup 2)))])]
3160 "TARGET_POWER"
3161 "
3162 { operands[4] = gen_reg_rtx (SImode); }")
3164 ;; This handles the branches.
3165 (define_expand "udivmodsi4_tests"
3166 [(set (match_operand:SI 0 "" "") (const_int 0))
3167 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
3168 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
3169 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
3170 (label_ref (match_operand:SI 4 "" "")) (pc)))
3171 (set (match_dup 0) (const_int 1))
3172 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
3173 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
3174 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
3175 (label_ref (match_dup 4)) (pc)))]
3176 "TARGET_POWER"
3177 "
3178 { operands[5] = gen_reg_rtx (CCUNSmode);
3179 operands[6] = gen_reg_rtx (CCmode);
3180 }")
3182 (define_expand "udivmodsi4"
3183 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3184 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
3185 (match_operand:SI 2 "reg_or_cint_operand" "")))
3186 (set (match_operand:SI 3 "gpc_reg_operand" "")
3187 (umod:SI (match_dup 1) (match_dup 2)))])]
3188 ""
3189 "
3190 {
3191 rtx label = 0;
3193 if (! TARGET_POWER)
3194 {
3195 if (! TARGET_POWERPC)
3196 {
3197 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3198 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3199 emit_insn (gen_divus_call ());
3200 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3201 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3202 DONE;
3203 }
3204 else
3205 FAIL;
3206 }
3208 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
3209 {
3210 operands[2] = force_reg (SImode, operands[2]);
3211 label = gen_label_rtx ();
3212 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
3213 operands[3], label));
3214 }
3215 else
3216 operands[2] = force_reg (SImode, operands[2]);
3218 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
3219 operands[3]));
3220 if (label)
3221 emit_label (label);
3223 DONE;
3224 }")
3226 ;; AIX architecture-independent common-mode multiply (DImode),
3227 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
3228 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
3229 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
3230 ;; assumed unused if generating common-mode, so ignore.
3231 (define_insn "mulh_call"
3232 [(set (reg:SI 3)
3233 (truncate:SI
3234 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
3235 (sign_extend:DI (reg:SI 4)))
3236 (const_int 32))))
3237 (clobber (reg:SI LR_REGNO))]
3238 "! TARGET_POWER && ! TARGET_POWERPC"
3239 "bla __mulh"
3240 [(set_attr "type" "imul")])
3242 (define_insn "mull_call"
3243 [(set (reg:DI 3)
3244 (mult:DI (sign_extend:DI (reg:SI 3))
3245 (sign_extend:DI (reg:SI 4))))
3246 (clobber (reg:SI LR_REGNO))
3247 (clobber (reg:SI 0))]
3248 "! TARGET_POWER && ! TARGET_POWERPC"
3249 "bla __mull"
3250 [(set_attr "type" "imul")])
3252 (define_insn "divss_call"
3253 [(set (reg:SI 3)
3254 (div:SI (reg:SI 3) (reg:SI 4)))
3255 (set (reg:SI 4)
3256 (mod:SI (reg:SI 3) (reg:SI 4)))
3257 (clobber (reg:SI LR_REGNO))
3258 (clobber (reg:SI 0))]
3259 "! TARGET_POWER && ! TARGET_POWERPC"
3260 "bla __divss"
3261 [(set_attr "type" "idiv")])
3263 (define_insn "divus_call"
3264 [(set (reg:SI 3)
3265 (udiv:SI (reg:SI 3) (reg:SI 4)))
3266 (set (reg:SI 4)
3267 (umod:SI (reg:SI 3) (reg:SI 4)))
3268 (clobber (reg:SI LR_REGNO))
3269 (clobber (reg:SI 0))
3270 (clobber (match_scratch:CC 0 "=x"))
3271 (clobber (reg:CC CR1_REGNO))]
3272 "! TARGET_POWER && ! TARGET_POWERPC"
3273 "bla __divus"
3274 [(set_attr "type" "idiv")])
3276 (define_insn "quoss_call"
3277 [(set (reg:SI 3)
3278 (div:SI (reg:SI 3) (reg:SI 4)))
3279 (clobber (reg:SI LR_REGNO))]
3280 "! TARGET_POWER && ! TARGET_POWERPC"
3281 "bla __quoss"
3282 [(set_attr "type" "idiv")])
3284 (define_insn "quous_call"
3285 [(set (reg:SI 3)
3286 (udiv:SI (reg:SI 3) (reg:SI 4)))
3287 (clobber (reg:SI LR_REGNO))
3288 (clobber (reg:SI 0))
3289 (clobber (match_scratch:CC 0 "=x"))
3290 (clobber (reg:CC CR1_REGNO))]
3291 "! TARGET_POWER && ! TARGET_POWERPC"
3292 "bla __quous"
3293 [(set_attr "type" "idiv")])
3294 \f
3295 ;; Logical instructions
3296 ;; The logical instructions are mostly combined by using match_operator,
3297 ;; but the plain AND insns are somewhat different because there is no
3298 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3299 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3301 (define_expand "andsi3"
3302 [(parallel
3303 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3304 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3305 (match_operand:SI 2 "and_operand" "")))
3306 (clobber (match_scratch:CC 3 ""))])]
3307 ""
3308 "")
3310 (define_insn "andsi3_mc"
3311 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3312 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3313 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3314 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3315 "rs6000_gen_cell_microcode"
3316 "@
3317 and %0,%1,%2
3318 {rlinm|rlwinm} %0,%1,0,%m2,%M2
3319 {andil.|andi.} %0,%1,%b2
3320 {andiu.|andis.} %0,%1,%u2"
3321 [(set_attr "type" "*,*,fast_compare,fast_compare")])
3323 (define_insn "andsi3_nomc"
3324 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3325 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3326 (match_operand:SI 2 "and_operand" "?r,T")))
3327 (clobber (match_scratch:CC 3 "=X,X"))]
3328 "!rs6000_gen_cell_microcode"
3329 "@
3330 and %0,%1,%2
3331 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3333 (define_insn "andsi3_internal0_nomc"
3334 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3335 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3336 (match_operand:SI 2 "and_operand" "?r,T")))]
3337 "!rs6000_gen_cell_microcode"
3338 "@
3339 and %0,%1,%2
3340 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3343 ;; Note to set cr's other than cr0 we do the and immediate and then
3344 ;; the test again -- this avoids a mfcr which on the higher end
3345 ;; machines causes an execution serialization
3347 (define_insn "*andsi3_internal2_mc"
3348 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3349 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3350 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3351 (const_int 0)))
3352 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3353 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3354 "TARGET_32BIT && rs6000_gen_cell_microcode"
3355 "@
3356 and. %3,%1,%2
3357 {andil.|andi.} %3,%1,%b2
3358 {andiu.|andis.} %3,%1,%u2
3359 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3360 #
3361 #
3362 #
3363 #"
3364 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3365 compare,compare,compare,compare")
3366 (set_attr "length" "4,4,4,4,8,8,8,8")])
3368 (define_insn "*andsi3_internal3_mc"
3369 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3370 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3371 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3372 (const_int 0)))
3373 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3374 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3375 "TARGET_64BIT && rs6000_gen_cell_microcode"
3376 "@
3377 #
3378 {andil.|andi.} %3,%1,%b2
3379 {andiu.|andis.} %3,%1,%u2
3380 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3381 #
3382 #
3383 #
3384 #"
3385 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3386 compare,compare,compare")
3387 (set_attr "length" "8,4,4,4,8,8,8,8")])
3389 (define_split
3390 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3391 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3392 (match_operand:GPR 2 "and_operand" ""))
3393 (const_int 0)))
3394 (clobber (match_scratch:GPR 3 ""))
3395 (clobber (match_scratch:CC 4 ""))]
3396 "reload_completed"
3397 [(parallel [(set (match_dup 3)
3398 (and:<MODE> (match_dup 1)
3399 (match_dup 2)))
3400 (clobber (match_dup 4))])
3401 (set (match_dup 0)
3402 (compare:CC (match_dup 3)
3403 (const_int 0)))]
3404 "")
3406 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3407 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3409 (define_split
3410 [(set (match_operand:CC 0 "cc_reg_operand" "")
3411 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3412 (match_operand:SI 2 "gpc_reg_operand" ""))
3413 (const_int 0)))
3414 (clobber (match_scratch:SI 3 ""))
3415 (clobber (match_scratch:CC 4 ""))]
3416 "TARGET_POWERPC64 && reload_completed"
3417 [(parallel [(set (match_dup 3)
3418 (and:SI (match_dup 1)
3419 (match_dup 2)))
3420 (clobber (match_dup 4))])
3421 (set (match_dup 0)
3422 (compare:CC (match_dup 3)
3423 (const_int 0)))]
3424 "")
3426 (define_insn "*andsi3_internal4"
3427 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3428 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3429 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3430 (const_int 0)))
3431 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3432 (and:SI (match_dup 1)
3433 (match_dup 2)))
3434 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3435 "TARGET_32BIT && rs6000_gen_cell_microcode"
3436 "@
3437 and. %0,%1,%2
3438 {andil.|andi.} %0,%1,%b2
3439 {andiu.|andis.} %0,%1,%u2
3440 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3441 #
3442 #
3443 #
3444 #"
3445 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3446 compare,compare,compare,compare")
3447 (set_attr "length" "4,4,4,4,8,8,8,8")])
3449 (define_insn "*andsi3_internal5_mc"
3450 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3451 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3452 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3453 (const_int 0)))
3454 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3455 (and:SI (match_dup 1)
3456 (match_dup 2)))
3457 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3458 "TARGET_64BIT && rs6000_gen_cell_microcode"
3459 "@
3460 #
3461 {andil.|andi.} %0,%1,%b2
3462 {andiu.|andis.} %0,%1,%u2
3463 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3464 #
3465 #
3466 #
3467 #"
3468 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3469 compare,compare,compare")
3470 (set_attr "length" "8,4,4,4,8,8,8,8")])
3472 (define_split
3473 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3474 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3475 (match_operand:SI 2 "and_operand" ""))
3476 (const_int 0)))
3477 (set (match_operand:SI 0 "gpc_reg_operand" "")
3478 (and:SI (match_dup 1)
3479 (match_dup 2)))
3480 (clobber (match_scratch:CC 4 ""))]
3481 "reload_completed"
3482 [(parallel [(set (match_dup 0)
3483 (and:SI (match_dup 1)
3484 (match_dup 2)))
3485 (clobber (match_dup 4))])
3486 (set (match_dup 3)
3487 (compare:CC (match_dup 0)
3488 (const_int 0)))]
3489 "")
3491 (define_split
3492 [(set (match_operand:CC 3 "cc_reg_operand" "")
3493 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3494 (match_operand:SI 2 "gpc_reg_operand" ""))
3495 (const_int 0)))
3496 (set (match_operand:SI 0 "gpc_reg_operand" "")
3497 (and:SI (match_dup 1)
3498 (match_dup 2)))
3499 (clobber (match_scratch:CC 4 ""))]
3500 "TARGET_POWERPC64 && reload_completed"
3501 [(parallel [(set (match_dup 0)
3502 (and:SI (match_dup 1)
3503 (match_dup 2)))
3504 (clobber (match_dup 4))])
3505 (set (match_dup 3)
3506 (compare:CC (match_dup 0)
3507 (const_int 0)))]
3508 "")
3510 ;; Handle the PowerPC64 rlwinm corner case
3512 (define_insn_and_split "*andsi3_internal6"
3513 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3514 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3515 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3516 "TARGET_POWERPC64"
3517 "#"
3518 "TARGET_POWERPC64"
3519 [(set (match_dup 0)
3520 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3521 (match_dup 4)))
3522 (set (match_dup 0)
3523 (rotate:SI (match_dup 0) (match_dup 5)))]
3524 "
3525 {
3526 int mb = extract_MB (operands[2]);
3527 int me = extract_ME (operands[2]);
3528 operands[3] = GEN_INT (me + 1);
3529 operands[5] = GEN_INT (32 - (me + 1));
3530 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3531 }"
3532 [(set_attr "length" "8")])
3534 (define_expand "iorsi3"
3535 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3536 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3537 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3538 ""
3539 "
3540 {
3541 if (GET_CODE (operands[2]) == CONST_INT
3542 && ! logical_operand (operands[2], SImode))
3543 {
3544 HOST_WIDE_INT value = INTVAL (operands[2]);
3545 rtx tmp = ((!can_create_pseudo_p ()
3546 || rtx_equal_p (operands[0], operands[1]))
3547 ? operands[0] : gen_reg_rtx (SImode));
3549 emit_insn (gen_iorsi3 (tmp, operands[1],
3550 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3551 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3552 DONE;
3553 }
3554 }")
3556 (define_expand "xorsi3"
3557 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3558 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3559 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3560 ""
3561 "
3562 {
3563 if (GET_CODE (operands[2]) == CONST_INT
3564 && ! logical_operand (operands[2], SImode))
3565 {
3566 HOST_WIDE_INT value = INTVAL (operands[2]);
3567 rtx tmp = ((!can_create_pseudo_p ()
3568 || rtx_equal_p (operands[0], operands[1]))
3569 ? operands[0] : gen_reg_rtx (SImode));
3571 emit_insn (gen_xorsi3 (tmp, operands[1],
3572 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3573 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3574 DONE;
3575 }
3576 }")
3578 (define_insn "*boolsi3_internal1"
3579 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3580 (match_operator:SI 3 "boolean_or_operator"
3581 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3582 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3583 ""
3584 "@
3585 %q3 %0,%1,%2
3586 {%q3il|%q3i} %0,%1,%b2
3587 {%q3iu|%q3is} %0,%1,%u2")
3589 (define_insn "*boolsi3_internal2"
3590 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3591 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3592 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3593 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3594 (const_int 0)))
3595 (clobber (match_scratch:SI 3 "=r,r"))]
3596 "TARGET_32BIT"
3597 "@
3598 %q4. %3,%1,%2
3599 #"
3600 [(set_attr "type" "fast_compare,compare")
3601 (set_attr "length" "4,8")])
3603 (define_split
3604 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3605 (compare:CC (match_operator:SI 4 "boolean_operator"
3606 [(match_operand:SI 1 "gpc_reg_operand" "")
3607 (match_operand:SI 2 "gpc_reg_operand" "")])
3608 (const_int 0)))
3609 (clobber (match_scratch:SI 3 ""))]
3610 "TARGET_32BIT && reload_completed"
3611 [(set (match_dup 3) (match_dup 4))
3612 (set (match_dup 0)
3613 (compare:CC (match_dup 3)
3614 (const_int 0)))]
3615 "")
3617 (define_insn "*boolsi3_internal3"
3618 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3619 (compare:CC (match_operator:SI 4 "boolean_operator"
3620 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3621 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3622 (const_int 0)))
3623 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3624 (match_dup 4))]
3625 "TARGET_32BIT"
3626 "@
3627 %q4. %0,%1,%2
3628 #"
3629 [(set_attr "type" "fast_compare,compare")
3630 (set_attr "length" "4,8")])
3632 (define_split
3633 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3634 (compare:CC (match_operator:SI 4 "boolean_operator"
3635 [(match_operand:SI 1 "gpc_reg_operand" "")
3636 (match_operand:SI 2 "gpc_reg_operand" "")])
3637 (const_int 0)))
3638 (set (match_operand:SI 0 "gpc_reg_operand" "")
3639 (match_dup 4))]
3640 "TARGET_32BIT && reload_completed"
3641 [(set (match_dup 0) (match_dup 4))
3642 (set (match_dup 3)
3643 (compare:CC (match_dup 0)
3644 (const_int 0)))]
3645 "")
3647 ;; Split a logical operation that we can't do in one insn into two insns,
3648 ;; each of which does one 16-bit part. This is used by combine.
3650 (define_split
3651 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3652 (match_operator:SI 3 "boolean_or_operator"
3653 [(match_operand:SI 1 "gpc_reg_operand" "")
3654 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3655 ""
3656 [(set (match_dup 0) (match_dup 4))
3657 (set (match_dup 0) (match_dup 5))]
3658 "
3659 {
3660 rtx i;
3661 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3662 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3663 operands[1], i);
3664 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3665 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3666 operands[0], i);
3667 }")
3669 (define_insn "*boolcsi3_internal1"
3670 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3671 (match_operator:SI 3 "boolean_operator"
3672 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3673 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3674 ""
3675 "%q3 %0,%2,%1")
3677 (define_insn "*boolcsi3_internal2"
3678 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3679 (compare:CC (match_operator:SI 4 "boolean_operator"
3680 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3681 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3682 (const_int 0)))
3683 (clobber (match_scratch:SI 3 "=r,r"))]
3684 "TARGET_32BIT"
3685 "@
3686 %q4. %3,%2,%1
3687 #"
3688 [(set_attr "type" "compare")
3689 (set_attr "length" "4,8")])
3691 (define_split
3692 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3693 (compare:CC (match_operator:SI 4 "boolean_operator"
3694 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3695 (match_operand:SI 2 "gpc_reg_operand" "")])
3696 (const_int 0)))
3697 (clobber (match_scratch:SI 3 ""))]
3698 "TARGET_32BIT && reload_completed"
3699 [(set (match_dup 3) (match_dup 4))
3700 (set (match_dup 0)
3701 (compare:CC (match_dup 3)
3702 (const_int 0)))]
3703 "")
3705 (define_insn "*boolcsi3_internal3"
3706 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3707 (compare:CC (match_operator:SI 4 "boolean_operator"
3708 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3709 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3710 (const_int 0)))
3711 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3712 (match_dup 4))]
3713 "TARGET_32BIT"
3714 "@
3715 %q4. %0,%2,%1
3716 #"
3717 [(set_attr "type" "compare")
3718 (set_attr "length" "4,8")])
3720 (define_split
3721 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3722 (compare:CC (match_operator:SI 4 "boolean_operator"
3723 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3724 (match_operand:SI 2 "gpc_reg_operand" "")])
3725 (const_int 0)))
3726 (set (match_operand:SI 0 "gpc_reg_operand" "")
3727 (match_dup 4))]
3728 "TARGET_32BIT && reload_completed"
3729 [(set (match_dup 0) (match_dup 4))
3730 (set (match_dup 3)
3731 (compare:CC (match_dup 0)
3732 (const_int 0)))]
3733 "")
3735 (define_insn "*boolccsi3_internal1"
3736 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3737 (match_operator:SI 3 "boolean_operator"
3738 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3739 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3740 ""
3741 "%q3 %0,%1,%2")
3743 (define_insn "*boolccsi3_internal2"
3744 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3745 (compare:CC (match_operator:SI 4 "boolean_operator"
3746 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3747 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3748 (const_int 0)))
3749 (clobber (match_scratch:SI 3 "=r,r"))]
3750 "TARGET_32BIT"
3751 "@
3752 %q4. %3,%1,%2
3753 #"
3754 [(set_attr "type" "fast_compare,compare")
3755 (set_attr "length" "4,8")])
3757 (define_split
3758 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3759 (compare:CC (match_operator:SI 4 "boolean_operator"
3760 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3761 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3762 (const_int 0)))
3763 (clobber (match_scratch:SI 3 ""))]
3764 "TARGET_32BIT && reload_completed"
3765 [(set (match_dup 3) (match_dup 4))
3766 (set (match_dup 0)
3767 (compare:CC (match_dup 3)
3768 (const_int 0)))]
3769 "")
3771 (define_insn "*boolccsi3_internal3"
3772 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3773 (compare:CC (match_operator:SI 4 "boolean_operator"
3774 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3775 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3776 (const_int 0)))
3777 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3778 (match_dup 4))]
3779 "TARGET_32BIT"
3780 "@
3781 %q4. %0,%1,%2
3782 #"
3783 [(set_attr "type" "fast_compare,compare")
3784 (set_attr "length" "4,8")])
3786 (define_split
3787 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3788 (compare:CC (match_operator:SI 4 "boolean_operator"
3789 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3790 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3791 (const_int 0)))
3792 (set (match_operand:SI 0 "gpc_reg_operand" "")
3793 (match_dup 4))]
3794 "TARGET_32BIT && reload_completed"
3795 [(set (match_dup 0) (match_dup 4))
3796 (set (match_dup 3)
3797 (compare:CC (match_dup 0)
3798 (const_int 0)))]
3799 "")
3801 ;; maskir insn. We need four forms because things might be in arbitrary
3802 ;; orders. Don't define forms that only set CR fields because these
3803 ;; would modify an input register.
3805 (define_insn "*maskir_internal1"
3806 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3807 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3808 (match_operand:SI 1 "gpc_reg_operand" "0"))
3809 (and:SI (match_dup 2)
3810 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3811 "TARGET_POWER"
3812 "maskir %0,%3,%2")
3814 (define_insn "*maskir_internal2"
3815 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3816 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3817 (match_operand:SI 1 "gpc_reg_operand" "0"))
3818 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3819 (match_dup 2))))]
3820 "TARGET_POWER"
3821 "maskir %0,%3,%2")
3823 (define_insn "*maskir_internal3"
3824 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3825 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3826 (match_operand:SI 3 "gpc_reg_operand" "r"))
3827 (and:SI (not:SI (match_dup 2))
3828 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3829 "TARGET_POWER"
3830 "maskir %0,%3,%2")
3832 (define_insn "*maskir_internal4"
3833 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3834 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3835 (match_operand:SI 2 "gpc_reg_operand" "r"))
3836 (and:SI (not:SI (match_dup 2))
3837 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3838 "TARGET_POWER"
3839 "maskir %0,%3,%2")
3841 (define_insn "*maskir_internal5"
3842 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3843 (compare:CC
3844 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3845 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3846 (and:SI (match_dup 2)
3847 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3848 (const_int 0)))
3849 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3850 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3851 (and:SI (match_dup 2) (match_dup 3))))]
3852 "TARGET_POWER"
3853 "@
3854 maskir. %0,%3,%2
3855 #"
3856 [(set_attr "type" "compare")
3857 (set_attr "length" "4,8")])
3859 (define_split
3860 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3861 (compare:CC
3862 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3863 (match_operand:SI 1 "gpc_reg_operand" ""))
3864 (and:SI (match_dup 2)
3865 (match_operand:SI 3 "gpc_reg_operand" "")))
3866 (const_int 0)))
3867 (set (match_operand:SI 0 "gpc_reg_operand" "")
3868 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3869 (and:SI (match_dup 2) (match_dup 3))))]
3870 "TARGET_POWER && reload_completed"
3871 [(set (match_dup 0)
3872 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3873 (and:SI (match_dup 2) (match_dup 3))))
3874 (set (match_dup 4)
3875 (compare:CC (match_dup 0)
3876 (const_int 0)))]
3877 "")
3879 (define_insn "*maskir_internal6"
3880 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3881 (compare:CC
3882 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3883 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3884 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3885 (match_dup 2)))
3886 (const_int 0)))
3887 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3888 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3889 (and:SI (match_dup 3) (match_dup 2))))]
3890 "TARGET_POWER"
3891 "@
3892 maskir. %0,%3,%2
3893 #"
3894 [(set_attr "type" "compare")
3895 (set_attr "length" "4,8")])
3897 (define_split
3898 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3899 (compare:CC
3900 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3901 (match_operand:SI 1 "gpc_reg_operand" ""))
3902 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3903 (match_dup 2)))
3904 (const_int 0)))
3905 (set (match_operand:SI 0 "gpc_reg_operand" "")
3906 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3907 (and:SI (match_dup 3) (match_dup 2))))]
3908 "TARGET_POWER && reload_completed"
3909 [(set (match_dup 0)
3910 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3911 (and:SI (match_dup 3) (match_dup 2))))
3912 (set (match_dup 4)
3913 (compare:CC (match_dup 0)
3914 (const_int 0)))]
3915 "")
3917 (define_insn "*maskir_internal7"
3918 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3919 (compare:CC
3920 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3921 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3922 (and:SI (not:SI (match_dup 2))
3923 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3924 (const_int 0)))
3925 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3926 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3927 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3928 "TARGET_POWER"
3929 "@
3930 maskir. %0,%3,%2
3931 #"
3932 [(set_attr "type" "compare")
3933 (set_attr "length" "4,8")])
3935 (define_split
3936 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3937 (compare:CC
3938 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3939 (match_operand:SI 3 "gpc_reg_operand" ""))
3940 (and:SI (not:SI (match_dup 2))
3941 (match_operand:SI 1 "gpc_reg_operand" "")))
3942 (const_int 0)))
3943 (set (match_operand:SI 0 "gpc_reg_operand" "")
3944 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3945 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3946 "TARGET_POWER && reload_completed"
3947 [(set (match_dup 0)
3948 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3949 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3950 (set (match_dup 4)
3951 (compare:CC (match_dup 0)
3952 (const_int 0)))]
3953 "")
3955 (define_insn "*maskir_internal8"
3956 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3957 (compare:CC
3958 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3959 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3960 (and:SI (not:SI (match_dup 2))
3961 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3962 (const_int 0)))
3963 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3964 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3965 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3966 "TARGET_POWER"
3967 "@
3968 maskir. %0,%3,%2
3969 #"
3970 [(set_attr "type" "compare")
3971 (set_attr "length" "4,8")])
3973 (define_split
3974 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3975 (compare:CC
3976 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3977 (match_operand:SI 2 "gpc_reg_operand" ""))
3978 (and:SI (not:SI (match_dup 2))
3979 (match_operand:SI 1 "gpc_reg_operand" "")))
3980 (const_int 0)))
3981 (set (match_operand:SI 0 "gpc_reg_operand" "")
3982 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3983 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3984 "TARGET_POWER && reload_completed"
3985 [(set (match_dup 0)
3986 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3987 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3988 (set (match_dup 4)
3989 (compare:CC (match_dup 0)
3990 (const_int 0)))]
3991 "")
3992 \f
3993 ;; Rotate and shift insns, in all their variants. These support shifts,
3994 ;; field inserts and extracts, and various combinations thereof.
3995 (define_expand "insv"
3996 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3997 (match_operand:SI 1 "const_int_operand" "")
3998 (match_operand:SI 2 "const_int_operand" ""))
3999 (match_operand 3 "gpc_reg_operand" ""))]
4000 ""
4001 "
4002 {
4003 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4004 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4005 compiler if the address of the structure is taken later. Likewise, do
4006 not handle invalid E500 subregs. */
4007 if (GET_CODE (operands[0]) == SUBREG
4008 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
4009 || ((TARGET_E500_DOUBLE || TARGET_SPE)
4010 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
4011 FAIL;
4013 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
4014 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
4015 else
4016 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
4017 DONE;
4018 }")
4020 (define_insn "insvsi"
4021 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4022 (match_operand:SI 1 "const_int_operand" "i")
4023 (match_operand:SI 2 "const_int_operand" "i"))
4024 (match_operand:SI 3 "gpc_reg_operand" "r"))]
4025 ""
4026 "*
4027 {
4028 int start = INTVAL (operands[2]) & 31;
4029 int size = INTVAL (operands[1]) & 31;
4031 operands[4] = GEN_INT (32 - start - size);
4032 operands[1] = GEN_INT (start + size - 1);
4033 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4034 }"
4035 [(set_attr "type" "insert_word")])
4037 (define_insn "*insvsi_internal1"
4038 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4039 (match_operand:SI 1 "const_int_operand" "i")
4040 (match_operand:SI 2 "const_int_operand" "i"))
4041 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4042 (match_operand:SI 4 "const_int_operand" "i")))]
4043 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4044 "*
4045 {
4046 int shift = INTVAL (operands[4]) & 31;
4047 int start = INTVAL (operands[2]) & 31;
4048 int size = INTVAL (operands[1]) & 31;
4050 operands[4] = GEN_INT (shift - start - size);
4051 operands[1] = GEN_INT (start + size - 1);
4052 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4053 }"
4054 [(set_attr "type" "insert_word")])
4056 (define_insn "*insvsi_internal2"
4057 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4058 (match_operand:SI 1 "const_int_operand" "i")
4059 (match_operand:SI 2 "const_int_operand" "i"))
4060 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4061 (match_operand:SI 4 "const_int_operand" "i")))]
4062 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4063 "*
4064 {
4065 int shift = INTVAL (operands[4]) & 31;
4066 int start = INTVAL (operands[2]) & 31;
4067 int size = INTVAL (operands[1]) & 31;
4069 operands[4] = GEN_INT (32 - shift - start - size);
4070 operands[1] = GEN_INT (start + size - 1);
4071 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4072 }"
4073 [(set_attr "type" "insert_word")])
4075 (define_insn "*insvsi_internal3"
4076 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4077 (match_operand:SI 1 "const_int_operand" "i")
4078 (match_operand:SI 2 "const_int_operand" "i"))
4079 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4080 (match_operand:SI 4 "const_int_operand" "i")))]
4081 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4082 "*
4083 {
4084 int shift = INTVAL (operands[4]) & 31;
4085 int start = INTVAL (operands[2]) & 31;
4086 int size = INTVAL (operands[1]) & 31;
4088 operands[4] = GEN_INT (32 - shift - start - size);
4089 operands[1] = GEN_INT (start + size - 1);
4090 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4091 }"
4092 [(set_attr "type" "insert_word")])
4094 (define_insn "*insvsi_internal4"
4095 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4096 (match_operand:SI 1 "const_int_operand" "i")
4097 (match_operand:SI 2 "const_int_operand" "i"))
4098 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4099 (match_operand:SI 4 "const_int_operand" "i")
4100 (match_operand:SI 5 "const_int_operand" "i")))]
4101 "INTVAL (operands[4]) >= INTVAL (operands[1])"
4102 "*
4103 {
4104 int extract_start = INTVAL (operands[5]) & 31;
4105 int extract_size = INTVAL (operands[4]) & 31;
4106 int insert_start = INTVAL (operands[2]) & 31;
4107 int insert_size = INTVAL (operands[1]) & 31;
4109 /* Align extract field with insert field */
4110 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
4111 operands[1] = GEN_INT (insert_start + insert_size - 1);
4112 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
4113 }"
4114 [(set_attr "type" "insert_word")])
4116 ;; combine patterns for rlwimi
4117 (define_insn "*insvsi_internal5"
4118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4119 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4120 (match_operand:SI 1 "mask_operand" "i"))
4121 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4122 (match_operand:SI 2 "const_int_operand" "i"))
4123 (match_operand:SI 5 "mask_operand" "i"))))]
4124 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4125 "*
4126 {
4127 int me = extract_ME(operands[5]);
4128 int mb = extract_MB(operands[5]);
4129 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4130 operands[2] = GEN_INT(mb);
4131 operands[1] = GEN_INT(me);
4132 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4133 }"
4134 [(set_attr "type" "insert_word")])
4136 (define_insn "*insvsi_internal6"
4137 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4138 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4139 (match_operand:SI 2 "const_int_operand" "i"))
4140 (match_operand:SI 5 "mask_operand" "i"))
4141 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4142 (match_operand:SI 1 "mask_operand" "i"))))]
4143 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4144 "*
4145 {
4146 int me = extract_ME(operands[5]);
4147 int mb = extract_MB(operands[5]);
4148 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4149 operands[2] = GEN_INT(mb);
4150 operands[1] = GEN_INT(me);
4151 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4152 }"
4153 [(set_attr "type" "insert_word")])
4155 (define_insn "insvdi"
4156 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4157 (match_operand:SI 1 "const_int_operand" "i")
4158 (match_operand:SI 2 "const_int_operand" "i"))
4159 (match_operand:DI 3 "gpc_reg_operand" "r"))]
4160 "TARGET_POWERPC64"
4161 "*
4162 {
4163 int start = INTVAL (operands[2]) & 63;
4164 int size = INTVAL (operands[1]) & 63;
4166 operands[1] = GEN_INT (64 - start - size);
4167 return \"rldimi %0,%3,%H1,%H2\";
4168 }"
4169 [(set_attr "type" "insert_dword")])
4171 (define_insn "*insvdi_internal2"
4172 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4173 (match_operand:SI 1 "const_int_operand" "i")
4174 (match_operand:SI 2 "const_int_operand" "i"))
4175 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4176 (match_operand:SI 4 "const_int_operand" "i")))]
4177 "TARGET_POWERPC64
4178 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4179 "*
4180 {
4181 int shift = INTVAL (operands[4]) & 63;
4182 int start = (INTVAL (operands[2]) & 63) - 32;
4183 int size = INTVAL (operands[1]) & 63;
4185 operands[4] = GEN_INT (64 - shift - start - size);
4186 operands[2] = GEN_INT (start);
4187 operands[1] = GEN_INT (start + size - 1);
4188 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4189 }")
4191 (define_insn "*insvdi_internal3"
4192 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4193 (match_operand:SI 1 "const_int_operand" "i")
4194 (match_operand:SI 2 "const_int_operand" "i"))
4195 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4196 (match_operand:SI 4 "const_int_operand" "i")))]
4197 "TARGET_POWERPC64
4198 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4199 "*
4200 {
4201 int shift = INTVAL (operands[4]) & 63;
4202 int start = (INTVAL (operands[2]) & 63) - 32;
4203 int size = INTVAL (operands[1]) & 63;
4205 operands[4] = GEN_INT (64 - shift - start - size);
4206 operands[2] = GEN_INT (start);
4207 operands[1] = GEN_INT (start + size - 1);
4208 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4209 }")
4211 (define_expand "extzv"
4212 [(set (match_operand 0 "gpc_reg_operand" "")
4213 (zero_extract (match_operand 1 "gpc_reg_operand" "")
4214 (match_operand:SI 2 "const_int_operand" "")
4215 (match_operand:SI 3 "const_int_operand" "")))]
4216 ""
4217 "
4218 {
4219 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4220 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4221 compiler if the address of the structure is taken later. */
4222 if (GET_CODE (operands[0]) == SUBREG
4223 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
4224 FAIL;
4226 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
4227 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
4228 else
4229 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
4230 DONE;
4231 }")
4233 (define_insn "extzvsi"
4234 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4235 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4236 (match_operand:SI 2 "const_int_operand" "i")
4237 (match_operand:SI 3 "const_int_operand" "i")))]
4238 ""
4239 "*
4240 {
4241 int start = INTVAL (operands[3]) & 31;
4242 int size = INTVAL (operands[2]) & 31;
4244 if (start + size >= 32)
4245 operands[3] = const0_rtx;
4246 else
4247 operands[3] = GEN_INT (start + size);
4248 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
4249 }")
4251 (define_insn "*extzvsi_internal1"
4252 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4253 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4254 (match_operand:SI 2 "const_int_operand" "i,i")
4255 (match_operand:SI 3 "const_int_operand" "i,i"))
4256 (const_int 0)))
4257 (clobber (match_scratch:SI 4 "=r,r"))]
4258 ""
4259 "*
4260 {
4261 int start = INTVAL (operands[3]) & 31;
4262 int size = INTVAL (operands[2]) & 31;
4264 /* Force split for non-cc0 compare. */
4265 if (which_alternative == 1)
4266 return \"#\";
4268 /* If the bit-field being tested fits in the upper or lower half of a
4269 word, it is possible to use andiu. or andil. to test it. This is
4270 useful because the condition register set-use delay is smaller for
4271 andi[ul]. than for rlinm. This doesn't work when the starting bit
4272 position is 0 because the LT and GT bits may be set wrong. */
4274 if ((start > 0 && start + size <= 16) || start >= 16)
4275 {
4276 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
4277 - (1 << (16 - (start & 15) - size))));
4278 if (start < 16)
4279 return \"{andiu.|andis.} %4,%1,%3\";
4280 else
4281 return \"{andil.|andi.} %4,%1,%3\";
4282 }
4284 if (start + size >= 32)
4285 operands[3] = const0_rtx;
4286 else
4287 operands[3] = GEN_INT (start + size);
4288 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
4289 }"
4290 [(set_attr "type" "delayed_compare")
4291 (set_attr "length" "4,8")])
4293 (define_split
4294 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4295 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4296 (match_operand:SI 2 "const_int_operand" "")
4297 (match_operand:SI 3 "const_int_operand" ""))
4298 (const_int 0)))
4299 (clobber (match_scratch:SI 4 ""))]
4300 "reload_completed"
4301 [(set (match_dup 4)
4302 (zero_extract:SI (match_dup 1) (match_dup 2)
4303 (match_dup 3)))
4304 (set (match_dup 0)
4305 (compare:CC (match_dup 4)
4306 (const_int 0)))]
4307 "")
4309 (define_insn "*extzvsi_internal2"
4310 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4311 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4312 (match_operand:SI 2 "const_int_operand" "i,i")
4313 (match_operand:SI 3 "const_int_operand" "i,i"))
4314 (const_int 0)))
4315 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4316 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4317 ""
4318 "*
4319 {
4320 int start = INTVAL (operands[3]) & 31;
4321 int size = INTVAL (operands[2]) & 31;
4323 /* Force split for non-cc0 compare. */
4324 if (which_alternative == 1)
4325 return \"#\";
4327 /* Since we are using the output value, we can't ignore any need for
4328 a shift. The bit-field must end at the LSB. */
4329 if (start >= 16 && start + size == 32)
4330 {
4331 operands[3] = GEN_INT ((1 << size) - 1);
4332 return \"{andil.|andi.} %0,%1,%3\";
4333 }
4335 if (start + size >= 32)
4336 operands[3] = const0_rtx;
4337 else
4338 operands[3] = GEN_INT (start + size);
4339 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
4340 }"
4341 [(set_attr "type" "delayed_compare")
4342 (set_attr "length" "4,8")])
4344 (define_split
4345 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4346 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4347 (match_operand:SI 2 "const_int_operand" "")
4348 (match_operand:SI 3 "const_int_operand" ""))
4349 (const_int 0)))
4350 (set (match_operand:SI 0 "gpc_reg_operand" "")
4351 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4352 "reload_completed"
4353 [(set (match_dup 0)
4354 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
4355 (set (match_dup 4)
4356 (compare:CC (match_dup 0)
4357 (const_int 0)))]
4358 "")
4360 (define_insn "extzvdi"
4361 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4362 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4363 (match_operand:SI 2 "const_int_operand" "i")
4364 (match_operand:SI 3 "const_int_operand" "i")))]
4365 "TARGET_POWERPC64"
4366 "*
4367 {
4368 int start = INTVAL (operands[3]) & 63;
4369 int size = INTVAL (operands[2]) & 63;
4371 if (start + size >= 64)
4372 operands[3] = const0_rtx;
4373 else
4374 operands[3] = GEN_INT (start + size);
4375 operands[2] = GEN_INT (64 - size);
4376 return \"rldicl %0,%1,%3,%2\";
4377 }")
4379 (define_insn "*extzvdi_internal1"
4380 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
4381 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4382 (match_operand:SI 2 "const_int_operand" "i")
4383 (match_operand:SI 3 "const_int_operand" "i"))
4384 (const_int 0)))
4385 (clobber (match_scratch:DI 4 "=r"))]
4386 "TARGET_64BIT && rs6000_gen_cell_microcode"
4387 "*
4388 {
4389 int start = INTVAL (operands[3]) & 63;
4390 int size = INTVAL (operands[2]) & 63;
4392 if (start + size >= 64)
4393 operands[3] = const0_rtx;
4394 else
4395 operands[3] = GEN_INT (start + size);
4396 operands[2] = GEN_INT (64 - size);
4397 return \"rldicl. %4,%1,%3,%2\";
4398 }"
4399 [(set_attr "type" "compare")])
4401 (define_insn "*extzvdi_internal2"
4402 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
4403 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4404 (match_operand:SI 2 "const_int_operand" "i")
4405 (match_operand:SI 3 "const_int_operand" "i"))
4406 (const_int 0)))
4407 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4408 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
4409 "TARGET_64BIT && rs6000_gen_cell_microcode"
4410 "*
4411 {
4412 int start = INTVAL (operands[3]) & 63;
4413 int size = INTVAL (operands[2]) & 63;
4415 if (start + size >= 64)
4416 operands[3] = const0_rtx;
4417 else
4418 operands[3] = GEN_INT (start + size);
4419 operands[2] = GEN_INT (64 - size);
4420 return \"rldicl. %0,%1,%3,%2\";
4421 }"
4422 [(set_attr "type" "compare")])
4424 (define_insn "rotlsi3"
4425 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4426 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4427 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4428 ""
4429 "@
4430 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4431 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4432 [(set_attr "type" "var_shift_rotate,integer")])
4434 (define_insn "*rotlsi3_64"
4435 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4436 (zero_extend:DI
4437 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4438 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4439 "TARGET_64BIT"
4440 "@
4441 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4442 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4443 [(set_attr "type" "var_shift_rotate,integer")])
4445 (define_insn "*rotlsi3_internal2"
4446 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4447 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4448 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4449 (const_int 0)))
4450 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4451 ""
4452 "@
4453 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4454 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4455 #
4456 #"
4457 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4458 (set_attr "length" "4,4,8,8")])
4460 (define_split
4461 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4462 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4463 (match_operand:SI 2 "reg_or_cint_operand" ""))
4464 (const_int 0)))
4465 (clobber (match_scratch:SI 3 ""))]
4466 "reload_completed"
4467 [(set (match_dup 3)
4468 (rotate:SI (match_dup 1) (match_dup 2)))
4469 (set (match_dup 0)
4470 (compare:CC (match_dup 3)
4471 (const_int 0)))]
4472 "")
4474 (define_insn "*rotlsi3_internal3"
4475 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4476 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4477 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4478 (const_int 0)))
4479 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4480 (rotate:SI (match_dup 1) (match_dup 2)))]
4481 ""
4482 "@
4483 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4484 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4485 #
4486 #"
4487 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4488 (set_attr "length" "4,4,8,8")])
4490 (define_split
4491 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4492 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4493 (match_operand:SI 2 "reg_or_cint_operand" ""))
4494 (const_int 0)))
4495 (set (match_operand:SI 0 "gpc_reg_operand" "")
4496 (rotate:SI (match_dup 1) (match_dup 2)))]
4497 "reload_completed"
4498 [(set (match_dup 0)
4499 (rotate:SI (match_dup 1) (match_dup 2)))
4500 (set (match_dup 3)
4501 (compare:CC (match_dup 0)
4502 (const_int 0)))]
4503 "")
4505 (define_insn "*rotlsi3_internal4"
4506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4507 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4508 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4509 (match_operand:SI 3 "mask_operand" "n,n")))]
4510 ""
4511 "@
4512 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4513 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4514 [(set_attr "type" "var_shift_rotate,integer")])
4516 (define_insn "*rotlsi3_internal5"
4517 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4518 (compare:CC (and:SI
4519 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4520 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4521 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4522 (const_int 0)))
4523 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4524 ""
4525 "@
4526 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4527 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4528 #
4529 #"
4530 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4531 (set_attr "length" "4,4,8,8")])
4533 (define_split
4534 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4535 (compare:CC (and:SI
4536 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4537 (match_operand:SI 2 "reg_or_cint_operand" ""))
4538 (match_operand:SI 3 "mask_operand" ""))
4539 (const_int 0)))
4540 (clobber (match_scratch:SI 4 ""))]
4541 "reload_completed"
4542 [(set (match_dup 4)
4543 (and:SI (rotate:SI (match_dup 1)
4544 (match_dup 2))
4545 (match_dup 3)))
4546 (set (match_dup 0)
4547 (compare:CC (match_dup 4)
4548 (const_int 0)))]
4549 "")
4551 (define_insn "*rotlsi3_internal6"
4552 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4553 (compare:CC (and:SI
4554 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4555 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4556 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4557 (const_int 0)))
4558 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4559 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4560 ""
4561 "@
4562 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4563 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4564 #
4565 #"
4566 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4567 (set_attr "length" "4,4,8,8")])
4569 (define_split
4570 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4571 (compare:CC (and:SI
4572 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4573 (match_operand:SI 2 "reg_or_cint_operand" ""))
4574 (match_operand:SI 3 "mask_operand" ""))
4575 (const_int 0)))
4576 (set (match_operand:SI 0 "gpc_reg_operand" "")
4577 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4578 "reload_completed"
4579 [(set (match_dup 0)
4580 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4581 (set (match_dup 4)
4582 (compare:CC (match_dup 0)
4583 (const_int 0)))]
4584 "")
4586 (define_insn "*rotlsi3_internal7"
4587 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4588 (zero_extend:SI
4589 (subreg:QI
4590 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4591 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4592 ""
4593 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4594 [(set (attr "cell_micro")
4595 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4596 (const_string "not")
4597 (const_string "always")))])
4599 (define_insn "*rotlsi3_internal8"
4600 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4601 (compare:CC (zero_extend:SI
4602 (subreg:QI
4603 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4604 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4605 (const_int 0)))
4606 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4607 ""
4608 "@
4609 {rlnm.|rlwnm.} %3,%1,%2,0xff
4610 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4611 #
4612 #"
4613 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4614 (set_attr "length" "4,4,8,8")])
4616 (define_split
4617 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4618 (compare:CC (zero_extend:SI
4619 (subreg:QI
4620 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4621 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4622 (const_int 0)))
4623 (clobber (match_scratch:SI 3 ""))]
4624 "reload_completed"
4625 [(set (match_dup 3)
4626 (zero_extend:SI (subreg:QI
4627 (rotate:SI (match_dup 1)
4628 (match_dup 2)) 0)))
4629 (set (match_dup 0)
4630 (compare:CC (match_dup 3)
4631 (const_int 0)))]
4632 "")
4634 (define_insn "*rotlsi3_internal9"
4635 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4636 (compare:CC (zero_extend:SI
4637 (subreg:QI
4638 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4639 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4640 (const_int 0)))
4641 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4642 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4643 ""
4644 "@
4645 {rlnm.|rlwnm.} %0,%1,%2,0xff
4646 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4647 #
4648 #"
4649 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4650 (set_attr "length" "4,4,8,8")])
4652 (define_split
4653 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4654 (compare:CC (zero_extend:SI
4655 (subreg:QI
4656 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4657 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4658 (const_int 0)))
4659 (set (match_operand:SI 0 "gpc_reg_operand" "")
4660 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4661 "reload_completed"
4662 [(set (match_dup 0)
4663 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4664 (set (match_dup 3)
4665 (compare:CC (match_dup 0)
4666 (const_int 0)))]
4667 "")
4669 (define_insn "*rotlsi3_internal10"
4670 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4671 (zero_extend:SI
4672 (subreg:HI
4673 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4674 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4675 ""
4676 "@
4677 {rlnm|rlwnm} %0,%1,%2,0xffff
4678 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4679 [(set_attr "type" "var_shift_rotate,integer")])
4682 (define_insn "*rotlsi3_internal11"
4683 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4684 (compare:CC (zero_extend:SI
4685 (subreg:HI
4686 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4687 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4688 (const_int 0)))
4689 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4690 ""
4691 "@
4692 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4693 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4694 #
4695 #"
4696 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4697 (set_attr "length" "4,4,8,8")])
4699 (define_split
4700 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4701 (compare:CC (zero_extend:SI
4702 (subreg:HI
4703 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4704 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4705 (const_int 0)))
4706 (clobber (match_scratch:SI 3 ""))]
4707 "reload_completed"
4708 [(set (match_dup 3)
4709 (zero_extend:SI (subreg:HI
4710 (rotate:SI (match_dup 1)
4711 (match_dup 2)) 0)))
4712 (set (match_dup 0)
4713 (compare:CC (match_dup 3)
4714 (const_int 0)))]
4715 "")
4717 (define_insn "*rotlsi3_internal12"
4718 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4719 (compare:CC (zero_extend:SI
4720 (subreg:HI
4721 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4722 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4723 (const_int 0)))
4724 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4725 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4726 ""
4727 "@
4728 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4729 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4730 #
4731 #"
4732 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4733 (set_attr "length" "4,4,8,8")])
4735 (define_split
4736 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4737 (compare:CC (zero_extend:SI
4738 (subreg:HI
4739 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4740 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4741 (const_int 0)))
4742 (set (match_operand:SI 0 "gpc_reg_operand" "")
4743 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4744 "reload_completed"
4745 [(set (match_dup 0)
4746 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4747 (set (match_dup 3)
4748 (compare:CC (match_dup 0)
4749 (const_int 0)))]
4750 "")
4752 ;; Note that we use "sle." instead of "sl." so that we can set
4753 ;; SHIFT_COUNT_TRUNCATED.
4755 (define_expand "ashlsi3"
4756 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4757 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4758 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4759 ""
4760 "
4761 {
4762 if (TARGET_POWER)
4763 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4764 else
4765 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4766 DONE;
4767 }")
4769 (define_insn "ashlsi3_power"
4770 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4771 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4772 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4773 (clobber (match_scratch:SI 3 "=q,X"))]
4774 "TARGET_POWER"
4775 "@
4776 sle %0,%1,%2
4777 {sli|slwi} %0,%1,%h2")
4779 (define_insn "ashlsi3_no_power"
4780 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4781 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4782 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4783 "! TARGET_POWER"
4784 "@
4785 {sl|slw} %0,%1,%2
4786 {sli|slwi} %0,%1,%h2"
4787 [(set_attr "type" "var_shift_rotate,shift")])
4789 (define_insn "*ashlsi3_64"
4790 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4791 (zero_extend:DI
4792 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4793 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4794 "TARGET_POWERPC64"
4795 "@
4796 {sl|slw} %0,%1,%2
4797 {sli|slwi} %0,%1,%h2"
4798 [(set_attr "type" "var_shift_rotate,shift")])
4800 (define_insn ""
4801 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4802 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4803 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4804 (const_int 0)))
4805 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4806 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4807 "TARGET_POWER"
4808 "@
4809 sle. %3,%1,%2
4810 {sli.|slwi.} %3,%1,%h2
4811 #
4812 #"
4813 [(set_attr "type" "delayed_compare")
4814 (set_attr "length" "4,4,8,8")])
4816 (define_split
4817 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4818 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4819 (match_operand:SI 2 "reg_or_cint_operand" ""))
4820 (const_int 0)))
4821 (clobber (match_scratch:SI 3 ""))
4822 (clobber (match_scratch:SI 4 ""))]
4823 "TARGET_POWER && reload_completed"
4824 [(parallel [(set (match_dup 3)
4825 (ashift:SI (match_dup 1) (match_dup 2)))
4826 (clobber (match_dup 4))])
4827 (set (match_dup 0)
4828 (compare:CC (match_dup 3)
4829 (const_int 0)))]
4830 "")
4832 (define_insn ""
4833 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4834 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4835 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4836 (const_int 0)))
4837 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4838 "! TARGET_POWER && TARGET_32BIT"
4839 "@
4840 {sl.|slw.} %3,%1,%2
4841 {sli.|slwi.} %3,%1,%h2
4842 #
4843 #"
4844 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4845 (set_attr "length" "4,4,8,8")])
4847 (define_split
4848 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4849 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4850 (match_operand:SI 2 "reg_or_cint_operand" ""))
4851 (const_int 0)))
4852 (clobber (match_scratch:SI 3 ""))]
4853 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4854 [(set (match_dup 3)
4855 (ashift:SI (match_dup 1) (match_dup 2)))
4856 (set (match_dup 0)
4857 (compare:CC (match_dup 3)
4858 (const_int 0)))]
4859 "")
4861 (define_insn ""
4862 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4863 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4864 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4865 (const_int 0)))
4866 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4867 (ashift:SI (match_dup 1) (match_dup 2)))
4868 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4869 "TARGET_POWER"
4870 "@
4871 sle. %0,%1,%2
4872 {sli.|slwi.} %0,%1,%h2
4873 #
4874 #"
4875 [(set_attr "type" "delayed_compare")
4876 (set_attr "length" "4,4,8,8")])
4878 (define_split
4879 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4880 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4881 (match_operand:SI 2 "reg_or_cint_operand" ""))
4882 (const_int 0)))
4883 (set (match_operand:SI 0 "gpc_reg_operand" "")
4884 (ashift:SI (match_dup 1) (match_dup 2)))
4885 (clobber (match_scratch:SI 4 ""))]
4886 "TARGET_POWER && reload_completed"
4887 [(parallel [(set (match_dup 0)
4888 (ashift:SI (match_dup 1) (match_dup 2)))
4889 (clobber (match_dup 4))])
4890 (set (match_dup 3)
4891 (compare:CC (match_dup 0)
4892 (const_int 0)))]
4893 "")
4895 (define_insn ""
4896 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4897 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4898 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4899 (const_int 0)))
4900 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4901 (ashift:SI (match_dup 1) (match_dup 2)))]
4902 "! TARGET_POWER && TARGET_32BIT"
4903 "@
4904 {sl.|slw.} %0,%1,%2
4905 {sli.|slwi.} %0,%1,%h2
4906 #
4907 #"
4908 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4909 (set_attr "length" "4,4,8,8")])
4911 (define_split
4912 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4913 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4914 (match_operand:SI 2 "reg_or_cint_operand" ""))
4915 (const_int 0)))
4916 (set (match_operand:SI 0 "gpc_reg_operand" "")
4917 (ashift:SI (match_dup 1) (match_dup 2)))]
4918 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4919 [(set (match_dup 0)
4920 (ashift:SI (match_dup 1) (match_dup 2)))
4921 (set (match_dup 3)
4922 (compare:CC (match_dup 0)
4923 (const_int 0)))]
4924 "")
4926 (define_insn "rlwinm"
4927 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4928 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4929 (match_operand:SI 2 "const_int_operand" "i"))
4930 (match_operand:SI 3 "mask_operand" "n")))]
4931 "includes_lshift_p (operands[2], operands[3])"
4932 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4934 (define_insn ""
4935 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4936 (compare:CC
4937 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4938 (match_operand:SI 2 "const_int_operand" "i,i"))
4939 (match_operand:SI 3 "mask_operand" "n,n"))
4940 (const_int 0)))
4941 (clobber (match_scratch:SI 4 "=r,r"))]
4942 "includes_lshift_p (operands[2], operands[3])"
4943 "@
4944 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4945 #"
4946 [(set_attr "type" "delayed_compare")
4947 (set_attr "length" "4,8")])
4949 (define_split
4950 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4951 (compare:CC
4952 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4953 (match_operand:SI 2 "const_int_operand" ""))
4954 (match_operand:SI 3 "mask_operand" ""))
4955 (const_int 0)))
4956 (clobber (match_scratch:SI 4 ""))]
4957 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4958 [(set (match_dup 4)
4959 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4960 (match_dup 3)))
4961 (set (match_dup 0)
4962 (compare:CC (match_dup 4)
4963 (const_int 0)))]
4964 "")
4966 (define_insn ""
4967 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4968 (compare:CC
4969 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4970 (match_operand:SI 2 "const_int_operand" "i,i"))
4971 (match_operand:SI 3 "mask_operand" "n,n"))
4972 (const_int 0)))
4973 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4974 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4975 "includes_lshift_p (operands[2], operands[3])"
4976 "@
4977 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4978 #"
4979 [(set_attr "type" "delayed_compare")
4980 (set_attr "length" "4,8")])
4982 (define_split
4983 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4984 (compare:CC
4985 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4986 (match_operand:SI 2 "const_int_operand" ""))
4987 (match_operand:SI 3 "mask_operand" ""))
4988 (const_int 0)))
4989 (set (match_operand:SI 0 "gpc_reg_operand" "")
4990 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4991 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4992 [(set (match_dup 0)
4993 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4994 (set (match_dup 4)
4995 (compare:CC (match_dup 0)
4996 (const_int 0)))]
4997 "")
4999 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5000 ;; "sli x,x,0".
5001 (define_expand "lshrsi3"
5002 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
5003 (use (match_operand:SI 1 "gpc_reg_operand" ""))
5004 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
5005 ""
5006 "
5007 {
5008 if (TARGET_POWER)
5009 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
5010 else
5011 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
5012 DONE;
5013 }")
5015 (define_insn "lshrsi3_power"
5016 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5017 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5018 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
5019 (clobber (match_scratch:SI 3 "=q,X,X"))]
5020 "TARGET_POWER"
5021 "@
5022 sre %0,%1,%2
5023 mr %0,%1
5024 {s%A2i|s%A2wi} %0,%1,%h2")
5026 (define_insn "lshrsi3_no_power"
5027 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5028 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5029 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
5030 "! TARGET_POWER"
5031 "@
5032 mr %0,%1
5033 {sr|srw} %0,%1,%2
5034 {sri|srwi} %0,%1,%h2"
5035 [(set_attr "type" "integer,var_shift_rotate,shift")])
5037 (define_insn "*lshrsi3_64"
5038 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5039 (zero_extend:DI
5040 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5041 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5042 "TARGET_POWERPC64"
5043 "@
5044 {sr|srw} %0,%1,%2
5045 {sri|srwi} %0,%1,%h2"
5046 [(set_attr "type" "var_shift_rotate,shift")])
5048 (define_insn ""
5049 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5050 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5051 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5052 (const_int 0)))
5053 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
5054 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5055 "TARGET_POWER"
5056 "@
5057 sre. %3,%1,%2
5058 mr. %1,%1
5059 {s%A2i.|s%A2wi.} %3,%1,%h2
5060 #
5061 #
5062 #"
5063 [(set_attr "type" "delayed_compare")
5064 (set_attr "length" "4,4,4,8,8,8")])
5066 (define_split
5067 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5068 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5069 (match_operand:SI 2 "reg_or_cint_operand" ""))
5070 (const_int 0)))
5071 (clobber (match_scratch:SI 3 ""))
5072 (clobber (match_scratch:SI 4 ""))]
5073 "TARGET_POWER && reload_completed"
5074 [(parallel [(set (match_dup 3)
5075 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5076 (clobber (match_dup 4))])
5077 (set (match_dup 0)
5078 (compare:CC (match_dup 3)
5079 (const_int 0)))]
5080 "")
5082 (define_insn ""
5083 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5084 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5085 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5086 (const_int 0)))
5087 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
5088 "! TARGET_POWER && TARGET_32BIT"
5089 "@
5090 mr. %1,%1
5091 {sr.|srw.} %3,%1,%2
5092 {sri.|srwi.} %3,%1,%h2
5093 #
5094 #
5095 #"
5096 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5097 (set_attr "length" "4,4,4,8,8,8")])
5099 (define_split
5100 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5101 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5102 (match_operand:SI 2 "reg_or_cint_operand" ""))
5103 (const_int 0)))
5104 (clobber (match_scratch:SI 3 ""))]
5105 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5106 [(set (match_dup 3)
5107 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5108 (set (match_dup 0)
5109 (compare:CC (match_dup 3)
5110 (const_int 0)))]
5111 "")
5113 (define_insn ""
5114 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5115 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5116 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5117 (const_int 0)))
5118 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5119 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5120 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5121 "TARGET_POWER"
5122 "@
5123 sre. %0,%1,%2
5124 mr. %0,%1
5125 {s%A2i.|s%A2wi.} %0,%1,%h2
5126 #
5127 #
5128 #"
5129 [(set_attr "type" "delayed_compare")
5130 (set_attr "length" "4,4,4,8,8,8")])
5132 (define_split
5133 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5134 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5135 (match_operand:SI 2 "reg_or_cint_operand" ""))
5136 (const_int 0)))
5137 (set (match_operand:SI 0 "gpc_reg_operand" "")
5138 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5139 (clobber (match_scratch:SI 4 ""))]
5140 "TARGET_POWER && reload_completed"
5141 [(parallel [(set (match_dup 0)
5142 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5143 (clobber (match_dup 4))])
5144 (set (match_dup 3)
5145 (compare:CC (match_dup 0)
5146 (const_int 0)))]
5147 "")
5149 (define_insn ""
5150 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5151 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5152 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5153 (const_int 0)))
5154 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5155 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5156 "! TARGET_POWER && TARGET_32BIT"
5157 "@
5158 mr. %0,%1
5159 {sr.|srw.} %0,%1,%2
5160 {sri.|srwi.} %0,%1,%h2
5161 #
5162 #
5163 #"
5164 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5165 (set_attr "length" "4,4,4,8,8,8")])
5167 (define_split
5168 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5169 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5170 (match_operand:SI 2 "reg_or_cint_operand" ""))
5171 (const_int 0)))
5172 (set (match_operand:SI 0 "gpc_reg_operand" "")
5173 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5174 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5175 [(set (match_dup 0)
5176 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5177 (set (match_dup 3)
5178 (compare:CC (match_dup 0)
5179 (const_int 0)))]
5180 "")
5182 (define_insn ""
5183 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5184 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5185 (match_operand:SI 2 "const_int_operand" "i"))
5186 (match_operand:SI 3 "mask_operand" "n")))]
5187 "includes_rshift_p (operands[2], operands[3])"
5188 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
5190 (define_insn ""
5191 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5192 (compare:CC
5193 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5194 (match_operand:SI 2 "const_int_operand" "i,i"))
5195 (match_operand:SI 3 "mask_operand" "n,n"))
5196 (const_int 0)))
5197 (clobber (match_scratch:SI 4 "=r,r"))]
5198 "includes_rshift_p (operands[2], operands[3])"
5199 "@
5200 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
5201 #"
5202 [(set_attr "type" "delayed_compare")
5203 (set_attr "length" "4,8")])
5205 (define_split
5206 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5207 (compare:CC
5208 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5209 (match_operand:SI 2 "const_int_operand" ""))
5210 (match_operand:SI 3 "mask_operand" ""))
5211 (const_int 0)))
5212 (clobber (match_scratch:SI 4 ""))]
5213 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5214 [(set (match_dup 4)
5215 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
5216 (match_dup 3)))
5217 (set (match_dup 0)
5218 (compare:CC (match_dup 4)
5219 (const_int 0)))]
5220 "")
5222 (define_insn ""
5223 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5224 (compare:CC
5225 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5226 (match_operand:SI 2 "const_int_operand" "i,i"))
5227 (match_operand:SI 3 "mask_operand" "n,n"))
5228 (const_int 0)))
5229 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5230 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5231 "includes_rshift_p (operands[2], operands[3])"
5232 "@
5233 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
5234 #"
5235 [(set_attr "type" "delayed_compare")
5236 (set_attr "length" "4,8")])
5238 (define_split
5239 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5240 (compare:CC
5241 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5242 (match_operand:SI 2 "const_int_operand" ""))
5243 (match_operand:SI 3 "mask_operand" ""))
5244 (const_int 0)))
5245 (set (match_operand:SI 0 "gpc_reg_operand" "")
5246 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5247 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5248 [(set (match_dup 0)
5249 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5250 (set (match_dup 4)
5251 (compare:CC (match_dup 0)
5252 (const_int 0)))]
5253 "")
5255 (define_insn ""
5256 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5257 (zero_extend:SI
5258 (subreg:QI
5259 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5260 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5261 "includes_rshift_p (operands[2], GEN_INT (255))"
5262 "{rlinm|rlwinm} %0,%1,%s2,0xff")
5264 (define_insn ""
5265 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5266 (compare:CC
5267 (zero_extend:SI
5268 (subreg:QI
5269 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5270 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5271 (const_int 0)))
5272 (clobber (match_scratch:SI 3 "=r,r"))]
5273 "includes_rshift_p (operands[2], GEN_INT (255))"
5274 "@
5275 {rlinm.|rlwinm.} %3,%1,%s2,0xff
5276 #"
5277 [(set_attr "type" "delayed_compare")
5278 (set_attr "length" "4,8")])
5280 (define_split
5281 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5282 (compare:CC
5283 (zero_extend:SI
5284 (subreg:QI
5285 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5286 (match_operand:SI 2 "const_int_operand" "")) 0))
5287 (const_int 0)))
5288 (clobber (match_scratch:SI 3 ""))]
5289 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5290 [(set (match_dup 3)
5291 (zero_extend:SI (subreg:QI
5292 (lshiftrt:SI (match_dup 1)
5293 (match_dup 2)) 0)))
5294 (set (match_dup 0)
5295 (compare:CC (match_dup 3)
5296 (const_int 0)))]
5297 "")
5299 (define_insn ""
5300 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5301 (compare:CC
5302 (zero_extend:SI
5303 (subreg:QI
5304 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5305 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5306 (const_int 0)))
5307 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5308 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5309 "includes_rshift_p (operands[2], GEN_INT (255))"
5310 "@
5311 {rlinm.|rlwinm.} %0,%1,%s2,0xff
5312 #"
5313 [(set_attr "type" "delayed_compare")
5314 (set_attr "length" "4,8")])
5316 (define_split
5317 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5318 (compare:CC
5319 (zero_extend:SI
5320 (subreg:QI
5321 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5322 (match_operand:SI 2 "const_int_operand" "")) 0))
5323 (const_int 0)))
5324 (set (match_operand:SI 0 "gpc_reg_operand" "")
5325 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5326 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5327 [(set (match_dup 0)
5328 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5329 (set (match_dup 3)
5330 (compare:CC (match_dup 0)
5331 (const_int 0)))]
5332 "")
5334 (define_insn ""
5335 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5336 (zero_extend:SI
5337 (subreg:HI
5338 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5339 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5340 "includes_rshift_p (operands[2], GEN_INT (65535))"
5341 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
5343 (define_insn ""
5344 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5345 (compare:CC
5346 (zero_extend:SI
5347 (subreg:HI
5348 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5349 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5350 (const_int 0)))
5351 (clobber (match_scratch:SI 3 "=r,r"))]
5352 "includes_rshift_p (operands[2], GEN_INT (65535))"
5353 "@
5354 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
5355 #"
5356 [(set_attr "type" "delayed_compare")
5357 (set_attr "length" "4,8")])
5359 (define_split
5360 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5361 (compare:CC
5362 (zero_extend:SI
5363 (subreg:HI
5364 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5365 (match_operand:SI 2 "const_int_operand" "")) 0))
5366 (const_int 0)))
5367 (clobber (match_scratch:SI 3 ""))]
5368 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5369 [(set (match_dup 3)
5370 (zero_extend:SI (subreg:HI
5371 (lshiftrt:SI (match_dup 1)
5372 (match_dup 2)) 0)))
5373 (set (match_dup 0)
5374 (compare:CC (match_dup 3)
5375 (const_int 0)))]
5376 "")
5378 (define_insn ""
5379 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5380 (compare:CC
5381 (zero_extend:SI
5382 (subreg:HI
5383 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5384 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5385 (const_int 0)))
5386 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5387 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5388 "includes_rshift_p (operands[2], GEN_INT (65535))"
5389 "@
5390 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
5391 #"
5392 [(set_attr "type" "delayed_compare")
5393 (set_attr "length" "4,8")])
5395 (define_split
5396 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5397 (compare:CC
5398 (zero_extend:SI
5399 (subreg:HI
5400 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5401 (match_operand:SI 2 "const_int_operand" "")) 0))
5402 (const_int 0)))
5403 (set (match_operand:SI 0 "gpc_reg_operand" "")
5404 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5405 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5406 [(set (match_dup 0)
5407 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5408 (set (match_dup 3)
5409 (compare:CC (match_dup 0)
5410 (const_int 0)))]
5411 "")
5413 (define_insn ""
5414 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5415 (const_int 1)
5416 (match_operand:SI 1 "gpc_reg_operand" "r"))
5417 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5418 (const_int 31)))]
5419 "TARGET_POWER"
5420 "rrib %0,%1,%2")
5422 (define_insn ""
5423 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5424 (const_int 1)
5425 (match_operand:SI 1 "gpc_reg_operand" "r"))
5426 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5427 (const_int 31)))]
5428 "TARGET_POWER"
5429 "rrib %0,%1,%2")
5431 (define_insn ""
5432 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5433 (const_int 1)
5434 (match_operand:SI 1 "gpc_reg_operand" "r"))
5435 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5436 (const_int 1)
5437 (const_int 0)))]
5438 "TARGET_POWER"
5439 "rrib %0,%1,%2")
5441 (define_expand "ashrsi3"
5442 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5443 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5444 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5445 ""
5446 "
5447 {
5448 if (TARGET_POWER)
5449 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
5450 else
5451 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
5452 DONE;
5453 }")
5455 (define_insn "ashrsi3_power"
5456 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5457 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5458 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
5459 (clobber (match_scratch:SI 3 "=q,X"))]
5460 "TARGET_POWER"
5461 "@
5462 srea %0,%1,%2
5463 {srai|srawi} %0,%1,%h2"
5464 [(set_attr "type" "shift")])
5466 (define_insn "ashrsi3_no_power"
5467 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5468 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5469 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
5470 "! TARGET_POWER"
5471 "@
5472 {sra|sraw} %0,%1,%2
5473 {srai|srawi} %0,%1,%h2"
5474 [(set_attr "type" "var_shift_rotate,shift")])
5476 (define_insn "*ashrsi3_64"
5477 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5478 (sign_extend:DI
5479 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5480 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5481 "TARGET_POWERPC64"
5482 "@
5483 {sra|sraw} %0,%1,%2
5484 {srai|srawi} %0,%1,%h2"
5485 [(set_attr "type" "var_shift_rotate,shift")])
5487 (define_insn ""
5488 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5489 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5490 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5491 (const_int 0)))
5492 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5493 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5494 "TARGET_POWER"
5495 "@
5496 srea. %3,%1,%2
5497 {srai.|srawi.} %3,%1,%h2
5498 #
5499 #"
5500 [(set_attr "type" "delayed_compare")
5501 (set_attr "length" "4,4,8,8")])
5503 (define_split
5504 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5505 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5506 (match_operand:SI 2 "reg_or_cint_operand" ""))
5507 (const_int 0)))
5508 (clobber (match_scratch:SI 3 ""))
5509 (clobber (match_scratch:SI 4 ""))]
5510 "TARGET_POWER && reload_completed"
5511 [(parallel [(set (match_dup 3)
5512 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5513 (clobber (match_dup 4))])
5514 (set (match_dup 0)
5515 (compare:CC (match_dup 3)
5516 (const_int 0)))]
5517 "")
5519 (define_insn ""
5520 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5521 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5522 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5523 (const_int 0)))
5524 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5525 "! TARGET_POWER"
5526 "@
5527 {sra.|sraw.} %3,%1,%2
5528 {srai.|srawi.} %3,%1,%h2
5529 #
5530 #"
5531 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5532 (set_attr "length" "4,4,8,8")])
5534 (define_split
5535 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5536 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5537 (match_operand:SI 2 "reg_or_cint_operand" ""))
5538 (const_int 0)))
5539 (clobber (match_scratch:SI 3 ""))]
5540 "! TARGET_POWER && reload_completed"
5541 [(set (match_dup 3)
5542 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5543 (set (match_dup 0)
5544 (compare:CC (match_dup 3)
5545 (const_int 0)))]
5546 "")
5548 (define_insn ""
5549 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5550 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5551 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5552 (const_int 0)))
5553 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5554 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5555 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5556 "TARGET_POWER"
5557 "@
5558 srea. %0,%1,%2
5559 {srai.|srawi.} %0,%1,%h2
5560 #
5561 #"
5562 [(set_attr "type" "delayed_compare")
5563 (set_attr "length" "4,4,8,8")])
5565 (define_split
5566 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5567 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5568 (match_operand:SI 2 "reg_or_cint_operand" ""))
5569 (const_int 0)))
5570 (set (match_operand:SI 0 "gpc_reg_operand" "")
5571 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5572 (clobber (match_scratch:SI 4 ""))]
5573 "TARGET_POWER && reload_completed"
5574 [(parallel [(set (match_dup 0)
5575 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5576 (clobber (match_dup 4))])
5577 (set (match_dup 3)
5578 (compare:CC (match_dup 0)
5579 (const_int 0)))]
5580 "")
5582 (define_insn ""
5583 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5584 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5585 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5586 (const_int 0)))
5587 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5588 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5589 "! TARGET_POWER"
5590 "@
5591 {sra.|sraw.} %0,%1,%2
5592 {srai.|srawi.} %0,%1,%h2
5593 #
5594 #"
5595 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5596 (set_attr "length" "4,4,8,8")])
5597 \f
5598 ;; Builtins to replace a division to generate FRE reciprocal estimate
5599 ;; instructions and the necessary fixup instructions
5600 (define_expand "recip<mode>3"
5601 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5602 (match_operand:RECIPF 1 "gpc_reg_operand" "")
5603 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
5604 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
5605 {
5606 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
5607 DONE;
5608 })
5610 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
5611 ;; hardware division. This is only done before register allocation and with
5612 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
5613 (define_split
5614 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
5615 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
5616 (match_operand 2 "gpc_reg_operand" "")))]
5617 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5618 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
5619 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
5620 [(const_int 0)]
5621 {
5622 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
5623 DONE;
5624 })
5626 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5627 ;; appropriate fixup.
5628 (define_expand "rsqrt<mode>2"
5629 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5630 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5631 "RS6000_RECIP_HAVE_RSQRT_P (<MODE>mode)"
5632 {
5633 rs6000_emit_swrsqrt (operands[0], operands[1]);
5634 DONE;
5635 })
5636 \f
5637 (define_split
5638 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5639 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5640 (match_operand:SI 2 "reg_or_cint_operand" ""))
5641 (const_int 0)))
5642 (set (match_operand:SI 0 "gpc_reg_operand" "")
5643 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5644 "! TARGET_POWER && reload_completed"
5645 [(set (match_dup 0)
5646 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5647 (set (match_dup 3)
5648 (compare:CC (match_dup 0)
5649 (const_int 0)))]
5650 "")
5652 ;; Floating-point insns, excluding normal data motion.
5653 ;;
5654 ;; PowerPC has a full set of single-precision floating point instructions.
5655 ;;
5656 ;; For the POWER architecture, we pretend that we have both SFmode and
5657 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5658 ;; The only conversions we will do will be when storing to memory. In that
5659 ;; case, we will use the "frsp" instruction before storing.
5660 ;;
5661 ;; Note that when we store into a single-precision memory location, we need to
5662 ;; use the frsp insn first. If the register being stored isn't dead, we
5663 ;; need a scratch register for the frsp. But this is difficult when the store
5664 ;; is done by reload. It is not incorrect to do the frsp on the register in
5665 ;; this case, we just lose precision that we would have otherwise gotten but
5666 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5668 (define_expand "extendsfdf2"
5669 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5670 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5671 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5672 "")
5674 (define_insn_and_split "*extendsfdf2_fpr"
5675 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5676 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5677 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5678 "@
5679 #
5680 fmr %0,%1
5681 lfs%U1%X1 %0,%1"
5682 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5683 [(const_int 0)]
5684 {
5685 emit_note (NOTE_INSN_DELETED);
5686 DONE;
5687 }
5688 [(set_attr "type" "fp,fp,fpload")])
5690 (define_expand "truncdfsf2"
5691 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5692 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5693 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5694 "")
5696 (define_insn "*truncdfsf2_fpr"
5697 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5698 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5699 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5700 "frsp %0,%1"
5701 [(set_attr "type" "fp")])
5703 (define_insn "aux_truncdfsf2"
5704 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5705 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5706 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5707 "frsp %0,%1"
5708 [(set_attr "type" "fp")])
5710 (define_expand "negsf2"
5711 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5712 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5713 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5714 "")
5716 (define_insn "*negsf2"
5717 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5718 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5719 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5720 "fneg %0,%1"
5721 [(set_attr "type" "fp")])
5723 (define_expand "abssf2"
5724 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5725 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5726 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5727 "")
5729 (define_insn "*abssf2"
5730 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5731 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5732 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5733 "fabs %0,%1"
5734 [(set_attr "type" "fp")])
5736 (define_insn ""
5737 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5738 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5739 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5740 "fnabs %0,%1"
5741 [(set_attr "type" "fp")])
5743 (define_expand "addsf3"
5744 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5745 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5746 (match_operand:SF 2 "gpc_reg_operand" "")))]
5747 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5748 "")
5750 (define_insn ""
5751 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5752 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5753 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5754 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5755 "fadds %0,%1,%2"
5756 [(set_attr "type" "fp")
5757 (set_attr "fp_type" "fp_addsub_s")])
5759 (define_insn ""
5760 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5761 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5762 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5763 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5764 "{fa|fadd} %0,%1,%2"
5765 [(set_attr "type" "fp")])
5767 (define_expand "subsf3"
5768 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5769 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5770 (match_operand:SF 2 "gpc_reg_operand" "")))]
5771 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5772 "")
5774 (define_insn ""
5775 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5776 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5777 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5778 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5779 "fsubs %0,%1,%2"
5780 [(set_attr "type" "fp")
5781 (set_attr "fp_type" "fp_addsub_s")])
5783 (define_insn ""
5784 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5785 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5786 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5787 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5788 "{fs|fsub} %0,%1,%2"
5789 [(set_attr "type" "fp")])
5791 (define_expand "mulsf3"
5792 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5793 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5794 (match_operand:SF 2 "gpc_reg_operand" "")))]
5795 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5796 "")
5798 (define_insn ""
5799 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5800 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5801 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5802 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5803 "fmuls %0,%1,%2"
5804 [(set_attr "type" "fp")
5805 (set_attr "fp_type" "fp_mul_s")])
5807 (define_insn ""
5808 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5809 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5810 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5811 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5812 "{fm|fmul} %0,%1,%2"
5813 [(set_attr "type" "dmul")])
5815 (define_expand "divsf3"
5816 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5817 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5818 (match_operand:SF 2 "gpc_reg_operand" "")))]
5819 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5820 "")
5822 (define_insn ""
5823 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5824 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5825 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5826 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5827 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5828 "fdivs %0,%1,%2"
5829 [(set_attr "type" "sdiv")])
5831 (define_insn ""
5832 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5833 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5834 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5835 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5836 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5837 "{fd|fdiv} %0,%1,%2"
5838 [(set_attr "type" "ddiv")])
5840 (define_insn "fres"
5841 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5842 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5843 "TARGET_FRES"
5844 "fres %0,%1"
5845 [(set_attr "type" "fp")])
5847 (define_insn "*fmaddsf4_powerpc"
5848 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5849 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5850 (match_operand:SF 2 "gpc_reg_operand" "f"))
5851 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5852 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5853 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5854 "fmadds %0,%1,%2,%3"
5855 [(set_attr "type" "fp")
5856 (set_attr "fp_type" "fp_maddsub_s")])
5858 (define_insn "*fmaddsf4_power"
5859 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5860 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5861 (match_operand:SF 2 "gpc_reg_operand" "f"))
5862 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5863 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5864 "{fma|fmadd} %0,%1,%2,%3"
5865 [(set_attr "type" "dmul")])
5867 (define_insn "*fmsubsf4_powerpc"
5868 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5869 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5870 (match_operand:SF 2 "gpc_reg_operand" "f"))
5871 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5872 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5873 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5874 "fmsubs %0,%1,%2,%3"
5875 [(set_attr "type" "fp")
5876 (set_attr "fp_type" "fp_maddsub_s")])
5878 (define_insn "*fmsubsf4_power"
5879 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5880 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5881 (match_operand:SF 2 "gpc_reg_operand" "f"))
5882 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5883 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5884 "{fms|fmsub} %0,%1,%2,%3"
5885 [(set_attr "type" "dmul")])
5887 (define_insn "*fnmaddsf4_powerpc_1"
5888 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5889 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5890 (match_operand:SF 2 "gpc_reg_operand" "f"))
5891 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5892 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5893 && TARGET_SINGLE_FLOAT"
5894 "fnmadds %0,%1,%2,%3"
5895 [(set_attr "type" "fp")
5896 (set_attr "fp_type" "fp_maddsub_s")])
5898 (define_insn "*fnmaddsf4_powerpc_2"
5899 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5900 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5901 (match_operand:SF 2 "gpc_reg_operand" "f"))
5902 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5903 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5904 && ! HONOR_SIGNED_ZEROS (SFmode)"
5905 "fnmadds %0,%1,%2,%3"
5906 [(set_attr "type" "fp")
5907 (set_attr "fp_type" "fp_maddsub_s")])
5909 (define_insn "*fnmaddsf4_power_1"
5910 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5911 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5912 (match_operand:SF 2 "gpc_reg_operand" "f"))
5913 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5914 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5915 "{fnma|fnmadd} %0,%1,%2,%3"
5916 [(set_attr "type" "dmul")])
5918 (define_insn "*fnmaddsf4_power_2"
5919 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5920 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5921 (match_operand:SF 2 "gpc_reg_operand" "f"))
5922 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5923 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5924 && ! HONOR_SIGNED_ZEROS (SFmode)"
5925 "{fnma|fnmadd} %0,%1,%2,%3"
5926 [(set_attr "type" "dmul")])
5928 (define_insn "*fnmsubsf4_powerpc_1"
5929 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5930 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5931 (match_operand:SF 2 "gpc_reg_operand" "f"))
5932 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5933 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5934 && TARGET_SINGLE_FLOAT"
5935 "fnmsubs %0,%1,%2,%3"
5936 [(set_attr "type" "fp")
5937 (set_attr "fp_type" "fp_maddsub_s")])
5939 (define_insn "*fnmsubsf4_powerpc_2"
5940 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5941 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5942 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5943 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5944 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5945 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5946 "fnmsubs %0,%1,%2,%3"
5947 [(set_attr "type" "fp")
5948 (set_attr "fp_type" "fp_maddsub_s")])
5950 (define_insn "*fnmsubsf4_power_1"
5951 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5952 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5953 (match_operand:SF 2 "gpc_reg_operand" "f"))
5954 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5955 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5956 "{fnms|fnmsub} %0,%1,%2,%3"
5957 [(set_attr "type" "dmul")])
5959 (define_insn "*fnmsubsf4_power_2"
5960 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5961 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5962 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5963 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5964 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5965 && ! HONOR_SIGNED_ZEROS (SFmode)"
5966 "{fnms|fnmsub} %0,%1,%2,%3"
5967 [(set_attr "type" "dmul")])
5969 (define_expand "sqrtsf2"
5970 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5971 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5972 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5973 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5974 && !TARGET_SIMPLE_FPU"
5975 "")
5977 (define_insn ""
5978 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5979 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5980 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5981 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5982 "fsqrts %0,%1"
5983 [(set_attr "type" "ssqrt")])
5985 (define_insn ""
5986 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5987 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5988 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5989 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5990 "fsqrt %0,%1"
5991 [(set_attr "type" "dsqrt")])
5993 (define_insn "*rsqrtsf_internal1"
5994 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5995 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5996 UNSPEC_RSQRT))]
5997 "TARGET_FRSQRTES"
5998 "frsqrtes %0,%1"
5999 [(set_attr "type" "fp")])
6001 (define_expand "copysign<mode>3"
6002 [(set (match_dup 3)
6003 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
6004 (set (match_dup 4)
6005 (neg:SFDF (abs:SFDF (match_dup 1))))
6006 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
6007 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
6008 (match_dup 5))
6009 (match_dup 3)
6010 (match_dup 4)))]
6011 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6012 && ((TARGET_PPC_GFXOPT
6013 && !HONOR_NANS (<MODE>mode)
6014 && !HONOR_SIGNED_ZEROS (<MODE>mode))
6015 || TARGET_CMPB
6016 || VECTOR_UNIT_VSX_P (<MODE>mode))"
6017 {
6018 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
6019 {
6020 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
6021 operands[2]));
6022 DONE;
6023 }
6025 operands[3] = gen_reg_rtx (<MODE>mode);
6026 operands[4] = gen_reg_rtx (<MODE>mode);
6027 operands[5] = CONST0_RTX (<MODE>mode);
6028 })
6030 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
6031 ;; compiler from optimizing -0.0
6032 (define_insn "copysign<mode>3_fcpsgn"
6033 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6034 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
6035 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
6036 UNSPEC_COPYSIGN))]
6037 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6038 "fcpsgn %0,%2,%1"
6039 [(set_attr "type" "fp")])
6041 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
6042 ;; fsel instruction and some auxiliary computations. Then we just have a
6043 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
6044 ;; combine.
6045 (define_expand "smaxsf3"
6046 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6047 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6048 (match_operand:SF 2 "gpc_reg_operand" ""))
6049 (match_dup 1)
6050 (match_dup 2)))]
6051 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6052 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6053 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6055 (define_expand "sminsf3"
6056 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6057 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6058 (match_operand:SF 2 "gpc_reg_operand" ""))
6059 (match_dup 2)
6060 (match_dup 1)))]
6061 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6062 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6063 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6065 (define_split
6066 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6067 (match_operator:SF 3 "min_max_operator"
6068 [(match_operand:SF 1 "gpc_reg_operand" "")
6069 (match_operand:SF 2 "gpc_reg_operand" "")]))]
6070 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6071 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6072 [(const_int 0)]
6073 "
6074 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6075 operands[1], operands[2]);
6076 DONE;
6077 }")
6079 (define_expand "mov<mode>cc"
6080 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
6081 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6082 (match_operand:GPR 2 "gpc_reg_operand" "")
6083 (match_operand:GPR 3 "gpc_reg_operand" "")))]
6084 "TARGET_ISEL<sel>"
6085 "
6086 {
6087 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6088 DONE;
6089 else
6090 FAIL;
6091 }")
6093 ;; We use the BASE_REGS for the isel input operands because, if rA is
6094 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
6095 ;; because we may switch the operands and rB may end up being rA.
6096 ;;
6097 ;; We need 2 patterns: an unsigned and a signed pattern. We could
6098 ;; leave out the mode in operand 4 and use one pattern, but reload can
6099 ;; change the mode underneath our feet and then gets confused trying
6100 ;; to reload the value.
6101 (define_insn "isel_signed_<mode>"
6102 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
6103 (if_then_else:GPR
6104 (match_operator 1 "scc_comparison_operator"
6105 [(match_operand:CC 4 "cc_reg_operand" "y,y")
6106 (const_int 0)])
6107 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
6108 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
6109 "TARGET_ISEL<sel>"
6110 "*
6111 { return output_isel (operands); }"
6112 [(set_attr "type" "isel")
6113 (set_attr "length" "4")])
6115 (define_insn "isel_unsigned_<mode>"
6116 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
6117 (if_then_else:GPR
6118 (match_operator 1 "scc_comparison_operator"
6119 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
6120 (const_int 0)])
6121 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
6122 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
6123 "TARGET_ISEL<sel>"
6124 "*
6125 { return output_isel (operands); }"
6126 [(set_attr "type" "isel")
6127 (set_attr "length" "4")])
6129 (define_expand "movsfcc"
6130 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6131 (if_then_else:SF (match_operand 1 "comparison_operator" "")
6132 (match_operand:SF 2 "gpc_reg_operand" "")
6133 (match_operand:SF 3 "gpc_reg_operand" "")))]
6134 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6135 "
6136 {
6137 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6138 DONE;
6139 else
6140 FAIL;
6141 }")
6143 (define_insn "*fselsfsf4"
6144 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6145 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6146 (match_operand:SF 4 "zero_fp_constant" "F"))
6147 (match_operand:SF 2 "gpc_reg_operand" "f")
6148 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6149 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6150 "fsel %0,%1,%2,%3"
6151 [(set_attr "type" "fp")])
6153 (define_insn "*fseldfsf4"
6154 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6155 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6156 (match_operand:DF 4 "zero_fp_constant" "F"))
6157 (match_operand:SF 2 "gpc_reg_operand" "f")
6158 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6159 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6160 "fsel %0,%1,%2,%3"
6161 [(set_attr "type" "fp")])
6163 (define_expand "negdf2"
6164 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6165 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6166 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6167 "")
6169 (define_insn "*negdf2_fpr"
6170 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6171 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6172 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6173 && !VECTOR_UNIT_VSX_P (DFmode)"
6174 "fneg %0,%1"
6175 [(set_attr "type" "fp")])
6177 (define_expand "absdf2"
6178 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6179 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6180 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6181 "")
6183 (define_insn "*absdf2_fpr"
6184 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6185 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6186 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6187 && !VECTOR_UNIT_VSX_P (DFmode)"
6188 "fabs %0,%1"
6189 [(set_attr "type" "fp")])
6191 (define_insn "*nabsdf2_fpr"
6192 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6193 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6194 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6195 && !VECTOR_UNIT_VSX_P (DFmode)"
6196 "fnabs %0,%1"
6197 [(set_attr "type" "fp")])
6199 (define_expand "adddf3"
6200 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6201 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6202 (match_operand:DF 2 "gpc_reg_operand" "")))]
6203 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6204 "")
6206 (define_insn "*adddf3_fpr"
6207 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6208 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6209 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6210 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6211 && !VECTOR_UNIT_VSX_P (DFmode)"
6212 "{fa|fadd} %0,%1,%2"
6213 [(set_attr "type" "fp")
6214 (set_attr "fp_type" "fp_addsub_d")])
6216 (define_expand "subdf3"
6217 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6218 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6219 (match_operand:DF 2 "gpc_reg_operand" "")))]
6220 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6221 "")
6223 (define_insn "*subdf3_fpr"
6224 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6225 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6226 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6227 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6228 && !VECTOR_UNIT_VSX_P (DFmode)"
6229 "{fs|fsub} %0,%1,%2"
6230 [(set_attr "type" "fp")
6231 (set_attr "fp_type" "fp_addsub_d")])
6233 (define_expand "muldf3"
6234 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6235 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
6236 (match_operand:DF 2 "gpc_reg_operand" "")))]
6237 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6238 "")
6240 (define_insn "*muldf3_fpr"
6241 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6242 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6243 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6244 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6245 && !VECTOR_UNIT_VSX_P (DFmode)"
6246 "{fm|fmul} %0,%1,%2"
6247 [(set_attr "type" "dmul")
6248 (set_attr "fp_type" "fp_mul_d")])
6250 (define_expand "divdf3"
6251 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6252 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
6253 (match_operand:DF 2 "gpc_reg_operand" "")))]
6254 "TARGET_HARD_FLOAT
6255 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
6256 && !TARGET_SIMPLE_FPU"
6257 "")
6259 (define_insn "*divdf3_fpr"
6260 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6261 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6262 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6263 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
6264 && !VECTOR_UNIT_VSX_P (DFmode)"
6265 "{fd|fdiv} %0,%1,%2"
6266 [(set_attr "type" "ddiv")])
6268 (define_insn "*fred_fpr"
6269 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6270 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
6271 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
6272 "fre %0,%1"
6273 [(set_attr "type" "fp")])
6275 (define_insn "*rsqrtdf_internal1"
6276 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6277 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
6278 UNSPEC_RSQRT))]
6279 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
6280 "frsqrte %0,%1"
6281 [(set_attr "type" "fp")])
6283 (define_insn "*fmadddf4_fpr"
6284 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6285 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6286 (match_operand:DF 2 "gpc_reg_operand" "d"))
6287 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6288 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6289 && VECTOR_UNIT_NONE_P (DFmode)"
6290 "{fma|fmadd} %0,%1,%2,%3"
6291 [(set_attr "type" "dmul")
6292 (set_attr "fp_type" "fp_maddsub_d")])
6294 (define_insn "*fmsubdf4_fpr"
6295 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6296 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6297 (match_operand:DF 2 "gpc_reg_operand" "d"))
6298 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6299 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6300 && VECTOR_UNIT_NONE_P (DFmode)"
6301 "{fms|fmsub} %0,%1,%2,%3"
6302 [(set_attr "type" "dmul")
6303 (set_attr "fp_type" "fp_maddsub_d")])
6305 (define_insn "*fnmadddf4_fpr_1"
6306 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6307 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6308 (match_operand:DF 2 "gpc_reg_operand" "d"))
6309 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6310 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6311 && VECTOR_UNIT_NONE_P (DFmode)"
6312 "{fnma|fnmadd} %0,%1,%2,%3"
6313 [(set_attr "type" "dmul")
6314 (set_attr "fp_type" "fp_maddsub_d")])
6316 (define_insn "*fnmadddf4_fpr_2"
6317 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6318 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d"))
6319 (match_operand:DF 2 "gpc_reg_operand" "d"))
6320 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6321 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6322 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6323 "{fnma|fnmadd} %0,%1,%2,%3"
6324 [(set_attr "type" "dmul")
6325 (set_attr "fp_type" "fp_maddsub_d")])
6327 (define_insn "*fnmsubdf4_fpr_1"
6328 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6329 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6330 (match_operand:DF 2 "gpc_reg_operand" "d"))
6331 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6332 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6333 && VECTOR_UNIT_NONE_P (DFmode)"
6334 "{fnms|fnmsub} %0,%1,%2,%3"
6335 [(set_attr "type" "dmul")
6336 (set_attr "fp_type" "fp_maddsub_d")])
6338 (define_insn "*fnmsubdf4_fpr_2"
6339 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6340 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d")
6341 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6342 (match_operand:DF 2 "gpc_reg_operand" "d"))))]
6343 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6344 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6345 "{fnms|fnmsub} %0,%1,%2,%3"
6346 [(set_attr "type" "dmul")
6347 (set_attr "fp_type" "fp_maddsub_d")])
6349 (define_expand "sqrtdf2"
6350 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6351 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6352 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6353 && TARGET_DOUBLE_FLOAT"
6354 "")
6356 (define_insn "*sqrtdf2_fpr"
6357 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6358 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6359 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6360 && TARGET_DOUBLE_FLOAT
6361 && !VECTOR_UNIT_VSX_P (DFmode)"
6362 "fsqrt %0,%1"
6363 [(set_attr "type" "dsqrt")])
6365 ;; The conditional move instructions allow us to perform max and min
6366 ;; operations even when
6368 (define_expand "smaxdf3"
6369 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6370 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6371 (match_operand:DF 2 "gpc_reg_operand" ""))
6372 (match_dup 1)
6373 (match_dup 2)))]
6374 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6375 && !flag_trapping_math"
6376 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6378 (define_expand "smindf3"
6379 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6380 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6381 (match_operand:DF 2 "gpc_reg_operand" ""))
6382 (match_dup 2)
6383 (match_dup 1)))]
6384 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6385 && !flag_trapping_math"
6386 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6388 (define_split
6389 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6390 (match_operator:DF 3 "min_max_operator"
6391 [(match_operand:DF 1 "gpc_reg_operand" "")
6392 (match_operand:DF 2 "gpc_reg_operand" "")]))]
6393 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6394 && !flag_trapping_math"
6395 [(const_int 0)]
6396 "
6397 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6398 operands[1], operands[2]);
6399 DONE;
6400 }")
6402 (define_expand "movdfcc"
6403 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6404 (if_then_else:DF (match_operand 1 "comparison_operator" "")
6405 (match_operand:DF 2 "gpc_reg_operand" "")
6406 (match_operand:DF 3 "gpc_reg_operand" "")))]
6407 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6408 "
6409 {
6410 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6411 DONE;
6412 else
6413 FAIL;
6414 }")
6416 (define_insn "*fseldfdf4"
6417 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6418 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6419 (match_operand:DF 4 "zero_fp_constant" "F"))
6420 (match_operand:DF 2 "gpc_reg_operand" "d")
6421 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6422 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6423 "fsel %0,%1,%2,%3"
6424 [(set_attr "type" "fp")])
6426 (define_insn "*fselsfdf4"
6427 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6428 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6429 (match_operand:SF 4 "zero_fp_constant" "F"))
6430 (match_operand:DF 2 "gpc_reg_operand" "d")
6431 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6432 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6433 "fsel %0,%1,%2,%3"
6434 [(set_attr "type" "fp")])
6435 \f
6436 ;; Conversions to and from floating-point.
6438 ; We don't define lfiwax/lfiwzx with the normal definition, because we
6439 ; don't want to support putting SImode in FPR registers.
6440 (define_insn "lfiwax"
6441 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6442 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
6443 UNSPEC_LFIWAX))]
6444 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
6445 "lfiwax %0,%y1"
6446 [(set_attr "type" "fpload")])
6448 (define_insn_and_split "floatsi<mode>2_lfiwax"
6449 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>,<rreg2>")
6450 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "Z,r")))
6451 (clobber (match_operand:SI 2 "indexed_or_indirect_operand" "=Z,Z"))
6452 (clobber (match_operand:DI 3 "gpc_reg_operand" "=d,d"))]
6453 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
6454 && <SI_CONVERT_FP>"
6455 "#"
6456 "MEM_P (operands[1]) || reload_completed"
6457 [(pc)]
6458 "
6459 {
6460 if (MEM_P (operands[1]))
6461 {
6462 operands[1] = rs6000_address_for_fpconvert (operands[1]);
6463 emit_insn (gen_lfiwax (operands[3], operands[1]));
6464 }
6465 else
6466 {
6467 emit_move_insn (operands[2], operands[1]);
6468 emit_insn (gen_lfiwax (operands[3], operands[2]));
6469 }
6470 emit_insn (gen_floatdi<mode>2 (operands[0], operands[3]));
6471 DONE;
6472 }"
6473 [(set_attr "length" "8,12")])
6475 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
6476 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6477 (float:SFDF (match_operand:SI 1 "memory_operand" "Z")))
6478 (clobber (match_scratch:DI 2 "=d"))]
6479 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
6480 && <SI_CONVERT_FP>"
6481 "#"
6482 "&& reload_completed"
6483 [(pc)]
6484 "
6485 {
6486 emit_insn (gen_lfiwax (operands[2], operands[1]));
6487 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
6488 DONE;
6489 }"
6490 [(set_attr "length" "8")])
6492 (define_insn_and_split "floatsi<mode>2_lfiwax_mem2"
6493 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6494 (float:SFDF
6495 (sign_extend:DI
6496 (match_operand:SI 1 "memory_operand" "Z"))))
6497 (clobber (match_scratch:DI 2 "=d"))]
6498 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
6499 && <SI_CONVERT_FP>"
6500 "#"
6501 "&& reload_completed"
6502 [(pc)]
6503 "
6504 {
6505 emit_insn (gen_lfiwax (operands[2], operands[1]));
6506 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
6507 DONE;
6508 }"
6509 [(set_attr "length" "8")])
6511 (define_insn "lfiwzx"
6512 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6513 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
6514 UNSPEC_LFIWZX))]
6515 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
6516 "lfiwzx %0,%y1"
6517 [(set_attr "type" "fpload")])
6519 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
6520 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>,<rreg2>")
6521 (unsigned_float:SFDF (match_operand:SI 1 "gpc_reg_operand" "Z,r")))
6522 (clobber (match_operand:SI 2 "indexed_or_indirect_operand" "=Z,Z"))
6523 (clobber (match_operand:DI 3 "gpc_reg_operand" "=d,d"))]
6524 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
6525 && <SI_CONVERT_FP>"
6526 "#"
6527 "MEM_P (operands[1]) || reload_completed"
6528 [(pc)]
6529 "
6530 {
6531 if (MEM_P (operands[1]))
6532 {
6533 operands[1] = rs6000_address_for_fpconvert (operands[1]);
6534 emit_insn (gen_lfiwzx (operands[3], operands[1]));
6535 }
6536 else
6537 {
6538 emit_move_insn (operands[2], operands[1]);
6539 emit_insn (gen_lfiwzx (operands[3], operands[2]));
6540 }
6541 emit_insn (gen_floatdi<mode>2 (operands[0], operands[3]));
6542 DONE;
6543 }"
6544 [(set_attr "length" "8,12")])
6546 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
6547 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6548 (unsigned_float:SFDF (match_operand:SI 1 "memory_operand" "Z")))
6549 (clobber (match_scratch:DI 2 "=d"))]
6550 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
6551 && <SI_CONVERT_FP>"
6552 "#"
6553 "&& reload_completed"
6554 [(pc)]
6555 "
6556 {
6557 emit_insn (gen_lfiwzx (operands[2], operands[1]));
6558 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
6559 DONE;
6560 }"
6561 [(set_attr "length" "8")])
6563 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem2"
6564 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6565 (unsigned_float:SFDF
6566 (zero_extend:DI
6567 (match_operand:SI 1 "memory_operand" "Z"))))
6568 (clobber (match_scratch:DI 2 "=d"))]
6569 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
6570 && <SI_CONVERT_FP>"
6571 "#"
6572 "&& reload_completed"
6573 [(pc)]
6574 "
6575 {
6576 emit_insn (gen_lfiwzx (operands[2], operands[1]));
6577 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
6578 DONE;
6579 }"
6580 [(set_attr "length" "8")])
6582 ; For each of these conversions, there is a define_expand, a define_insn
6583 ; with a '#' template, and a define_split (with C code). The idea is
6584 ; to allow constant folding with the template of the define_insn,
6585 ; then to have the insns split later (between sched1 and final).
6587 (define_expand "floatsidf2"
6588 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6589 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
6590 (use (match_dup 2))
6591 (use (match_dup 3))
6592 (clobber (match_dup 4))
6593 (clobber (match_dup 5))
6594 (clobber (match_dup 6))])]
6595 "TARGET_HARD_FLOAT
6596 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6597 "
6598 {
6599 if (TARGET_E500_DOUBLE)
6600 {
6601 if (!REG_P (operands[1]))
6602 operands[1] = force_reg (SImode, operands[1]);
6603 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
6604 DONE;
6605 }
6606 else if (TARGET_LFIWAX && TARGET_FCFID)
6607 {
6608 rs6000_expand_convert_si_to_sfdf (operands[0], operands[1], false);
6609 DONE;
6610 }
6611 else if (TARGET_FCFID)
6612 {
6613 rtx dreg = operands[1];
6614 if (!REG_P (dreg))
6615 dreg = force_reg (SImode, dreg);
6616 dreg = convert_to_mode (DImode, dreg, false);
6617 emit_insn (gen_floatdidf2 (operands[0], dreg));
6618 DONE;
6619 }
6621 if (!REG_P (operands[1]))
6622 operands[1] = force_reg (SImode, operands[1]);
6623 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6624 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
6625 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
6626 operands[5] = gen_reg_rtx (DFmode);
6627 operands[6] = gen_reg_rtx (SImode);
6628 }")
6630 (define_insn_and_split "*floatsidf2_internal"
6631 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6632 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6633 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6634 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6635 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6636 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6637 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
6638 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6639 "#"
6640 ""
6641 [(pc)]
6642 "
6643 {
6644 rtx lowword, highword;
6645 gcc_assert (MEM_P (operands[4]));
6646 highword = adjust_address (operands[4], SImode, 0);
6647 lowword = adjust_address (operands[4], SImode, 4);
6648 if (! WORDS_BIG_ENDIAN)
6649 {
6650 rtx tmp;
6651 tmp = highword; highword = lowword; lowword = tmp;
6652 }
6654 emit_insn (gen_xorsi3 (operands[6], operands[1],
6655 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
6656 emit_move_insn (lowword, operands[6]);
6657 emit_move_insn (highword, operands[2]);
6658 emit_move_insn (operands[5], operands[4]);
6659 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6660 DONE;
6661 }"
6662 [(set_attr "length" "24")])
6664 ;; If we don't have a direct conversion to single precision, don't enable this
6665 ;; conversion for 32-bit without fast math, because we don't have the insn to
6666 ;; generate the fixup swizzle to avoid double rounding problems.
6667 (define_expand "floatunssisf2"
6668 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6669 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6670 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6671 && (!TARGET_FPRS
6672 || (TARGET_FPRS
6673 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
6674 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6675 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6676 "
6677 {
6678 if (!TARGET_FPRS)
6679 {
6680 if (!REG_P (operands[1]))
6681 operands[1] = force_reg (SImode, operands[1]);
6682 }
6683 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
6684 {
6685 rs6000_expand_convert_si_to_sfdf (operands[0], operands[1], true);
6686 DONE;
6687 }
6688 else
6689 {
6690 rtx dreg = operands[1];
6691 if (!REG_P (dreg))
6692 dreg = force_reg (SImode, dreg);
6693 dreg = convert_to_mode (DImode, dreg, true);
6694 emit_insn (gen_floatdisf2 (operands[0], dreg));
6695 DONE;
6696 }
6697 }")
6699 (define_expand "floatunssidf2"
6700 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6701 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
6702 (use (match_dup 2))
6703 (use (match_dup 3))
6704 (clobber (match_dup 4))
6705 (clobber (match_dup 5))])]
6706 "TARGET_HARD_FLOAT
6707 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6708 "
6709 {
6710 if (TARGET_E500_DOUBLE)
6711 {
6712 if (!REG_P (operands[1]))
6713 operands[1] = force_reg (SImode, operands[1]);
6714 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6715 DONE;
6716 }
6717 else if (TARGET_LFIWZX && TARGET_FCFID)
6718 {
6719 rs6000_expand_convert_si_to_sfdf (operands[0], operands[1], true);
6720 DONE;
6721 }
6722 else if (TARGET_FCFID)
6723 {
6724 rtx dreg = operands[1];
6725 if (!REG_P (dreg))
6726 dreg = force_reg (SImode, dreg);
6727 dreg = convert_to_mode (DImode, dreg, true);
6728 emit_insn (gen_floatdidf2 (operands[0], dreg));
6729 DONE;
6730 }
6732 if (!REG_P (operands[1]))
6733 operands[1] = force_reg (SImode, operands[1]);
6734 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6735 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6736 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
6737 operands[5] = gen_reg_rtx (DFmode);
6738 }")
6740 (define_insn_and_split "*floatunssidf2_internal"
6741 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6742 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6743 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6744 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6745 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6746 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6747 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6748 && !(TARGET_FCFID && TARGET_POWERPC64)"
6749 "#"
6750 ""
6751 [(pc)]
6752 "
6753 {
6754 rtx lowword, highword;
6755 gcc_assert (MEM_P (operands[4]));
6756 highword = adjust_address (operands[4], SImode, 0);
6757 lowword = adjust_address (operands[4], SImode, 4);
6758 if (! WORDS_BIG_ENDIAN)
6759 {
6760 rtx tmp;
6761 tmp = highword; highword = lowword; lowword = tmp;
6762 }
6764 emit_move_insn (lowword, operands[1]);
6765 emit_move_insn (highword, operands[2]);
6766 emit_move_insn (operands[5], operands[4]);
6767 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6768 DONE;
6769 }"
6770 [(set_attr "length" "20")])
6772 (define_expand "fix_trunc<mode>si2"
6773 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6774 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6775 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT
6776 && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
6777 "
6778 {
6779 if (!<E500_CONVERT>)
6780 {
6781 rtx tmp, stack;
6783 if (TARGET_STFIWX)
6784 {
6785 tmp = gen_reg_rtx (DImode);
6786 stack = rs6000_allocate_stack_temp (SImode, false, true);
6787 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1],
6788 tmp, stack));
6789 }
6790 else
6791 {
6792 tmp = gen_reg_rtx (DImode);
6793 stack = rs6000_allocate_stack_temp (DImode, true, false);
6794 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
6795 tmp, stack));
6796 }
6797 DONE;
6798 }
6799 }")
6801 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
6802 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6803 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")))
6804 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6805 (clobber (match_operand:SI 3 "indexed_or_indirect_operand" "=Z"))]
6806 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6807 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
6808 && TARGET_STFIWX"
6809 "#"
6810 "&& reload_completed"
6811 [(pc)]
6812 "
6813 {
6814 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6815 if (TARGET_MFPGPR && TARGET_POWERPC64 && REG_P (operands[0])
6816 && INT_REGNO_P (REGNO (operands[0])))
6817 {
6818 rtx reg = gen_lowpart (DImode, operands[0]);
6819 emit_move_insn (reg, operands[2]);
6820 }
6821 else
6822 {
6823 emit_insn (gen_stfiwx (operands[3], operands[2]));
6824 emit_move_insn (operands[0], operands[3]);
6825 }
6826 DONE;
6827 }"
6828 [(set_attr "length" "12")])
6830 (define_insn_and_split "*fix_trunc<mode>si2_mem"
6831 [(set (match_operand:SI 0 "memory_operand" "=Z")
6832 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")))
6833 (clobber (match_scratch:DI 2 "=d"))]
6834 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6835 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
6836 && TARGET_STFIWX"
6837 "#"
6838 "&& reload_completed"
6839 [(pc)]
6840 "
6841 {
6842 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6843 emit_insn (gen_stfiwx (operands[0], operands[2]));
6844 DONE;
6845 }"
6846 [(set_attr "length" "8")])
6848 (define_insn_and_split "fix_trunc<mode>si2_internal"
6849 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6850 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<rreg>")))
6851 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6852 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6853 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6854 && TARGET_DOUBLE_FLOAT"
6855 "#"
6856 ""
6857 [(pc)]
6858 "
6859 {
6860 rtx lowword;
6861 gcc_assert (MEM_P (operands[3]));
6862 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6864 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6865 emit_move_insn (operands[3], operands[2]);
6866 emit_move_insn (operands[0], lowword);
6867 DONE;
6868 }"
6869 [(set_attr "length" "16")])
6871 (define_expand "fix_trunc<mode>di2"
6872 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6873 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6874 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6875 && TARGET_FCFID"
6876 "")
6878 (define_insn "*fix_trunc<mode>di2_fctidz"
6879 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6880 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6881 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6882 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6883 "fctidz %0,%1"
6884 [(set_attr "type" "fp")])
6886 (define_expand "fixuns_trunc<mode>si2"
6887 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6888 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6889 "TARGET_HARD_FLOAT
6890 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6891 || <E500_CONVERT>)"
6892 "
6893 {
6894 if (!<E500_CONVERT>)
6895 {
6896 rtx tmp = gen_reg_rtx (DImode);
6897 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6898 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1],
6899 tmp, stack));
6900 DONE;
6901 }
6902 }")
6904 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6905 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6906 (unsigned_fix:SI
6907 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")))
6908 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6909 (clobber (match_operand:SI 3 "indexed_or_indirect_operand" "=Z"))]
6910 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6911 && TARGET_STFIWX"
6912 "#"
6913 "&& reload_completed"
6914 [(pc)]
6915 "
6916 {
6917 emit_insn (gen_fctiwuz_<mode> (operands[2], operands[1]));
6918 if (TARGET_MFPGPR && TARGET_POWERPC64 && REG_P (operands[0])
6919 && INT_REGNO_P (REGNO (operands[0])))
6920 {
6921 rtx reg = gen_lowpart (DImode, operands[0]);
6922 emit_move_insn (reg, operands[2]);
6923 }
6924 else
6925 {
6926 emit_insn (gen_stfiwx (operands[3], operands[2]));
6927 emit_move_insn (operands[0], operands[3]);
6928 }
6929 DONE;
6930 }"
6931 [(set_attr "length" "12")])
6933 (define_insn_and_split "*fixuns_trunc<mode>si2_mem"
6934 [(set (match_operand:SI 0 "memory_operand" "=Z")
6935 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")))
6936 (clobber (match_scratch:DI 2 "=d"))]
6937 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6938 && TARGET_STFIWX"
6939 "#"
6940 "&& reload_completed"
6941 [(pc)]
6942 "
6943 {
6944 emit_insn (gen_fctiwuz_<mode> (operands[2], operands[1]));
6945 emit_insn (gen_stfiwx (operands[0], operands[2]));
6946 DONE;
6947 }"
6948 [(set_attr "length" "8")])
6950 (define_expand "fixuns_trunc<mode>di2"
6951 [(set (match_operand:DI 0 "register_operand" "")
6952 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6953 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6954 "")
6956 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6957 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6958 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6959 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6960 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6961 "fctiduz %0,%1"
6962 [(set_attr "type" "fp")])
6964 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6965 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6966 ; because the first makes it clear that operand 0 is not live
6967 ; before the instruction.
6968 (define_insn "fctiwz_<mode>"
6969 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6970 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6971 UNSPEC_FCTIWZ))]
6972 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6973 && TARGET_DOUBLE_FLOAT"
6974 "{fcirz|fctiwz} %0,%1"
6975 [(set_attr "type" "fp")])
6977 (define_insn "fctiwuz_<mode>"
6978 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6979 (unspec:DI [(unsigned_fix:SI
6980 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6981 UNSPEC_FCTIWUZ))]
6982 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6983 "fctiwuz %0,%1"
6984 [(set_attr "type" "fp")])
6986 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6987 ;; since the friz instruction does not truncate the value if the floating
6988 ;; point value is < LONG_MIN or > LONG_MAX.
6989 (define_insn "*friz"
6990 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6991 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6992 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_POPCNTB
6993 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6994 && !flag_trapping_math && TARGET_FRIZ"
6995 "friz %0,%1"
6996 [(set_attr "type" "fp")])
6998 ;; No VSX equivalent to fctid
6999 (define_insn "lrint<mode>di2"
7000 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
7001 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7002 UNSPEC_FCTID))]
7003 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7004 "fctid %0,%1"
7005 [(set_attr "type" "fp")])
7007 (define_expand "btrunc<mode>2"
7008 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7009 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7010 UNSPEC_FRIZ))]
7011 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7012 "")
7014 (define_insn "*btrunc<mode>2_fpr"
7015 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7016 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7017 UNSPEC_FRIZ))]
7018 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7019 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7020 "friz %0,%1"
7021 [(set_attr "type" "fp")])
7023 (define_expand "ceil<mode>2"
7024 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7025 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7026 UNSPEC_FRIP))]
7027 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7028 "")
7030 (define_insn "*ceil<mode>2_fpr"
7031 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7032 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7033 UNSPEC_FRIP))]
7034 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7035 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7036 "frip %0,%1"
7037 [(set_attr "type" "fp")])
7039 (define_expand "floor<mode>2"
7040 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7041 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7042 UNSPEC_FRIM))]
7043 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7044 "")
7046 (define_insn "*floor<mode>2_fpr"
7047 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7048 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7049 UNSPEC_FRIM))]
7050 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7051 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7052 "frim %0,%1"
7053 [(set_attr "type" "fp")])
7055 ;; No VSX equivalent to frin
7056 (define_insn "round<mode>2"
7057 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7058 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7059 UNSPEC_FRIN))]
7060 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7061 "frin %0,%1"
7062 [(set_attr "type" "fp")])
7064 ; An UNSPEC is used so we don't have to support SImode in FP registers.
7065 (define_insn "stfiwx"
7066 [(set (match_operand:SI 0 "memory_operand" "=Z")
7067 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
7068 UNSPEC_STFIWX))]
7069 "TARGET_PPC_GFXOPT"
7070 "stfiwx %1,%y0"
7071 [(set_attr "type" "fpstore")])
7073 ;; If we don't have a direct conversion to single precision, don't enable this
7074 ;; conversion for 32-bit without fast math, because we don't have the insn to
7075 ;; generate the fixup swizzle to avoid double rounding problems.
7076 (define_expand "floatsisf2"
7077 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7078 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
7079 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
7080 && (!TARGET_FPRS
7081 || (TARGET_FPRS
7082 && ((TARGET_FCFIDS && TARGET_LFIWAX)
7083 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
7084 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
7085 "
7086 {
7087 if (!TARGET_FPRS)
7088 {
7089 if (!REG_P (operands[1]))
7090 operands[1] = force_reg (SImode, operands[1]);
7091 }
7092 else if (TARGET_FCFIDS && TARGET_LFIWAX)
7093 {
7094 rs6000_expand_convert_si_to_sfdf (operands[0], operands[1], false);
7095 DONE;
7096 }
7097 else
7098 {
7099 rtx dreg = operands[1];
7100 if (!REG_P (dreg))
7101 dreg = force_reg (SImode, dreg);
7102 dreg = convert_to_mode (DImode, dreg, false);
7103 emit_insn (gen_floatdisf2 (operands[0], dreg));
7104 DONE;
7105 }
7106 }")
7108 (define_expand "floatdidf2"
7109 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7110 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
7111 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
7112 "")
7114 (define_insn "*floatdidf2_fpr"
7115 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7116 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7117 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
7118 && !VECTOR_UNIT_VSX_P (DFmode)"
7119 "fcfid %0,%1"
7120 [(set_attr "type" "fp")])
7122 ; Allow the combiner to merge source memory operands to the conversion so that
7123 ; the optimizer/register allocator doesn't try to load the value too early in a
7124 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
7125 ; hit. We will split after reload to avoid the trip through the GPRs
7127 (define_insn_and_split "*floatdidf2_mem"
7128 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7129 (float:DF (match_operand:DI 1 "memory_operand" "m")))
7130 (clobber (match_scratch:DI 2 "=d"))]
7131 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
7132 "#"
7133 "&& reload_completed"
7134 [(set (match_dup 2) (match_dup 1))
7135 (set (match_dup 0) (float:DF (match_dup 2)))]
7136 ""
7137 [(set_attr "length" "8")])
7139 (define_expand "floatunsdidf2"
7140 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7141 (unsigned_float:DF
7142 (match_operand:DI 1 "gpc_reg_operand" "")))]
7143 "TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode)"
7144 "")
7146 (define_insn "*floatunsdidf2_fcfidu"
7147 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7148 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7149 "TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
7150 "fcfidu %0,%1"
7151 [(set_attr "type" "fp")
7152 (set_attr "length" "4")])
7154 (define_insn_and_split "*floatunsdidf2_mem"
7155 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7156 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
7157 (clobber (match_scratch:DI 2 "=d"))]
7158 "TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode)"
7159 "#"
7160 "&& reload_completed"
7161 [(set (match_dup 2) (match_dup 1))
7162 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
7163 ""
7164 [(set_attr "length" "8")])
7166 (define_expand "floatdisf2"
7167 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7168 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
7169 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7170 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
7171 "
7172 {
7173 if (!TARGET_FCFIDS)
7174 {
7175 rtx val = operands[1];
7176 if (!flag_unsafe_math_optimizations)
7177 {
7178 rtx label = gen_label_rtx ();
7179 val = gen_reg_rtx (DImode);
7180 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
7181 emit_label (label);
7182 }
7183 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
7184 DONE;
7185 }
7186 }")
7188 (define_insn "floatdisf2_fcfids"
7189 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7190 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7191 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7192 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
7193 "fcfids %0,%1"
7194 [(set_attr "type" "fp")])
7196 (define_insn_and_split "*floatdisf2_mem"
7197 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7198 (float:SF (match_operand:DI 1 "memory_operand" "m")))
7199 (clobber (match_scratch:DI 2 "=f"))]
7200 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7201 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
7202 "#"
7203 "&& reload_completed"
7204 [(pc)]
7205 "
7206 {
7207 emit_move_insn (operands[2], operands[1]);
7208 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
7209 DONE;
7210 }"
7211 [(set_attr "length" "8")])
7213 ;; This is not IEEE compliant if rounding mode is "round to nearest".
7214 ;; If the DI->DF conversion is inexact, then it's possible to suffer
7215 ;; from double rounding.
7216 (define_insn_and_split "floatdisf2_internal1"
7217 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7218 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
7219 (clobber (match_scratch:DF 2 "=d"))]
7220 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
7221 "#"
7222 "&& reload_completed"
7223 [(set (match_dup 2)
7224 (float:DF (match_dup 1)))
7225 (set (match_dup 0)
7226 (float_truncate:SF (match_dup 2)))]
7227 "")
7229 ;; Twiddles bits to avoid double rounding.
7230 ;; Bits that might be truncated when converting to DFmode are replaced
7231 ;; by a bit that won't be lost at that stage, but is below the SFmode
7232 ;; rounding position.
7233 (define_expand "floatdisf2_internal2"
7234 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
7235 (const_int 53)))
7236 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
7237 (const_int 2047)))
7238 (clobber (scratch:CC))])
7239 (set (match_dup 3) (plus:DI (match_dup 3)
7240 (const_int 1)))
7241 (set (match_dup 0) (plus:DI (match_dup 0)
7242 (const_int 2047)))
7243 (set (match_dup 4) (compare:CCUNS (match_dup 3)
7244 (const_int 2)))
7245 (set (match_dup 0) (ior:DI (match_dup 0)
7246 (match_dup 1)))
7247 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
7248 (const_int -2048)))
7249 (clobber (scratch:CC))])
7250 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
7251 (label_ref (match_operand:DI 2 "" ""))
7252 (pc)))
7253 (set (match_dup 0) (match_dup 1))]
7254 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
7255 "
7256 {
7257 operands[3] = gen_reg_rtx (DImode);
7258 operands[4] = gen_reg_rtx (CCUNSmode);
7259 }")
7261 (define_expand "floatunsdisf2"
7262 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7263 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
7264 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7265 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7266 "")
7268 (define_insn "floatunsdisf2_fcfidus"
7269 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7270 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7271 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7272 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7273 "fcfidus %0,%1"
7274 [(set_attr "type" "fp")])
7276 (define_insn_and_split "*floatunsdisf2_mem"
7277 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7278 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
7279 (clobber (match_scratch:DI 2 "=f"))]
7280 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7281 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7282 "#"
7283 "&& reload_completed"
7284 [(pc)]
7285 "
7286 {
7287 emit_move_insn (operands[2], operands[1]);
7288 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
7289 DONE;
7290 }"
7291 [(set_attr "length" "8")])
7292 \f
7293 ;; Define the DImode operations that can be done in a small number
7294 ;; of instructions. The & constraints are to prevent the register
7295 ;; allocator from allocating registers that overlap with the inputs
7296 ;; (for example, having an input in 7,8 and an output in 6,7). We
7297 ;; also allow for the output being the same as one of the inputs.
7299 (define_insn "*adddi3_noppc64"
7300 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
7301 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
7302 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
7303 "! TARGET_POWERPC64"
7304 "*
7305 {
7306 if (WORDS_BIG_ENDIAN)
7307 return (GET_CODE (operands[2])) != CONST_INT
7308 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
7309 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
7310 else
7311 return (GET_CODE (operands[2])) != CONST_INT
7312 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
7313 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
7314 }"
7315 [(set_attr "type" "two")
7316 (set_attr "length" "8")])
7318 (define_insn "*subdi3_noppc64"
7319 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
7320 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
7321 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
7322 "! TARGET_POWERPC64"
7323 "*
7324 {
7325 if (WORDS_BIG_ENDIAN)
7326 return (GET_CODE (operands[1]) != CONST_INT)
7327 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
7328 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
7329 else
7330 return (GET_CODE (operands[1]) != CONST_INT)
7331 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
7332 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
7333 }"
7334 [(set_attr "type" "two")
7335 (set_attr "length" "8")])
7337 (define_insn "*negdi2_noppc64"
7338 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7339 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
7340 "! TARGET_POWERPC64"
7341 "*
7342 {
7343 return (WORDS_BIG_ENDIAN)
7344 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
7345 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
7346 }"
7347 [(set_attr "type" "two")
7348 (set_attr "length" "8")])
7350 (define_expand "mulsidi3"
7351 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7352 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7353 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7354 "! TARGET_POWERPC64"
7355 "
7356 {
7357 if (! TARGET_POWER && ! TARGET_POWERPC)
7358 {
7359 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7360 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7361 emit_insn (gen_mull_call ());
7362 if (WORDS_BIG_ENDIAN)
7363 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
7364 else
7365 {
7366 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
7367 gen_rtx_REG (SImode, 3));
7368 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
7369 gen_rtx_REG (SImode, 4));
7370 }
7371 DONE;
7372 }
7373 else if (TARGET_POWER)
7374 {
7375 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
7376 DONE;
7377 }
7378 }")
7380 (define_insn "mulsidi3_mq"
7381 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7382 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7383 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7384 (clobber (match_scratch:SI 3 "=q"))]
7385 "TARGET_POWER"
7386 "mul %0,%1,%2\;mfmq %L0"
7387 [(set_attr "type" "imul")
7388 (set_attr "length" "8")])
7390 (define_insn "*mulsidi3_no_mq"
7391 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7392 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7393 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7394 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7395 "*
7396 {
7397 return (WORDS_BIG_ENDIAN)
7398 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
7399 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
7400 }"
7401 [(set_attr "type" "imul")
7402 (set_attr "length" "8")])
7404 (define_split
7405 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7406 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7407 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7408 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7409 [(set (match_dup 3)
7410 (truncate:SI
7411 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
7412 (sign_extend:DI (match_dup 2)))
7413 (const_int 32))))
7414 (set (match_dup 4)
7415 (mult:SI (match_dup 1)
7416 (match_dup 2)))]
7417 "
7418 {
7419 int endian = (WORDS_BIG_ENDIAN == 0);
7420 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7421 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7422 }")
7424 (define_expand "umulsidi3"
7425 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7426 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7427 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7428 "TARGET_POWERPC && ! TARGET_POWERPC64"
7429 "
7430 {
7431 if (TARGET_POWER)
7432 {
7433 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
7434 DONE;
7435 }
7436 }")
7438 (define_insn "umulsidi3_mq"
7439 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7440 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7441 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7442 (clobber (match_scratch:SI 3 "=q"))]
7443 "TARGET_POWERPC && TARGET_POWER"
7444 "*
7445 {
7446 return (WORDS_BIG_ENDIAN)
7447 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7448 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7449 }"
7450 [(set_attr "type" "imul")
7451 (set_attr "length" "8")])
7453 (define_insn "*umulsidi3_no_mq"
7454 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7455 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7456 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7457 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7458 "*
7459 {
7460 return (WORDS_BIG_ENDIAN)
7461 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7462 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7463 }"
7464 [(set_attr "type" "imul")
7465 (set_attr "length" "8")])
7467 (define_split
7468 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7469 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7470 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7471 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7472 [(set (match_dup 3)
7473 (truncate:SI
7474 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
7475 (zero_extend:DI (match_dup 2)))
7476 (const_int 32))))
7477 (set (match_dup 4)
7478 (mult:SI (match_dup 1)
7479 (match_dup 2)))]
7480 "
7481 {
7482 int endian = (WORDS_BIG_ENDIAN == 0);
7483 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7484 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7485 }")
7487 (define_expand "smulsi3_highpart"
7488 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7489 (truncate:SI
7490 (lshiftrt:DI (mult:DI (sign_extend:DI
7491 (match_operand:SI 1 "gpc_reg_operand" ""))
7492 (sign_extend:DI
7493 (match_operand:SI 2 "gpc_reg_operand" "")))
7494 (const_int 32))))]
7495 ""
7496 "
7497 {
7498 if (! TARGET_POWER && ! TARGET_POWERPC)
7499 {
7500 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7501 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7502 emit_insn (gen_mulh_call ());
7503 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
7504 DONE;
7505 }
7506 else if (TARGET_POWER)
7507 {
7508 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7509 DONE;
7510 }
7511 }")
7513 (define_insn "smulsi3_highpart_mq"
7514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7515 (truncate:SI
7516 (lshiftrt:DI (mult:DI (sign_extend:DI
7517 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7518 (sign_extend:DI
7519 (match_operand:SI 2 "gpc_reg_operand" "r")))
7520 (const_int 32))))
7521 (clobber (match_scratch:SI 3 "=q"))]
7522 "TARGET_POWER"
7523 "mul %0,%1,%2"
7524 [(set_attr "type" "imul")])
7526 (define_insn "*smulsi3_highpart_no_mq"
7527 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7528 (truncate:SI
7529 (lshiftrt:DI (mult:DI (sign_extend:DI
7530 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7531 (sign_extend:DI
7532 (match_operand:SI 2 "gpc_reg_operand" "r")))
7533 (const_int 32))))]
7534 "TARGET_POWERPC && ! TARGET_POWER"
7535 "mulhw %0,%1,%2"
7536 [(set_attr "type" "imul")])
7538 (define_expand "umulsi3_highpart"
7539 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7540 (truncate:SI
7541 (lshiftrt:DI (mult:DI (zero_extend:DI
7542 (match_operand:SI 1 "gpc_reg_operand" ""))
7543 (zero_extend:DI
7544 (match_operand:SI 2 "gpc_reg_operand" "")))
7545 (const_int 32))))]
7546 "TARGET_POWERPC"
7547 "
7548 {
7549 if (TARGET_POWER)
7550 {
7551 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7552 DONE;
7553 }
7554 }")
7556 (define_insn "umulsi3_highpart_mq"
7557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7558 (truncate:SI
7559 (lshiftrt:DI (mult:DI (zero_extend:DI
7560 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7561 (zero_extend:DI
7562 (match_operand:SI 2 "gpc_reg_operand" "r")))
7563 (const_int 32))))
7564 (clobber (match_scratch:SI 3 "=q"))]
7565 "TARGET_POWERPC && TARGET_POWER"
7566 "mulhwu %0,%1,%2"
7567 [(set_attr "type" "imul")])
7569 (define_insn "*umulsi3_highpart_no_mq"
7570 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7571 (truncate:SI
7572 (lshiftrt:DI (mult:DI (zero_extend:DI
7573 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7574 (zero_extend:DI
7575 (match_operand:SI 2 "gpc_reg_operand" "r")))
7576 (const_int 32))))]
7577 "TARGET_POWERPC && ! TARGET_POWER"
7578 "mulhwu %0,%1,%2"
7579 [(set_attr "type" "imul")])
7581 ;; If operands 0 and 2 are in the same register, we have a problem. But
7582 ;; operands 0 and 1 (the usual case) can be in the same register. That's
7583 ;; why we have the strange constraints below.
7584 (define_insn "ashldi3_power"
7585 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7586 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7587 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7588 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7589 "TARGET_POWER"
7590 "@
7591 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
7592 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7593 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7594 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
7595 [(set_attr "length" "8")])
7597 (define_insn "lshrdi3_power"
7598 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7599 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7600 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7601 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7602 "TARGET_POWER"
7603 "@
7604 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
7605 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7606 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7607 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
7608 [(set_attr "length" "8")])
7610 ;; Shift by a variable amount is too complex to be worth open-coding. We
7611 ;; just handle shifts by constants.
7612 (define_insn "ashrdi3_power"
7613 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7614 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7615 (match_operand:SI 2 "const_int_operand" "M,i")))
7616 (clobber (match_scratch:SI 3 "=X,q"))]
7617 "TARGET_POWER"
7618 "@
7619 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7620 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
7621 [(set_attr "type" "shift")
7622 (set_attr "length" "8")])
7624 (define_insn "ashrdi3_no_power"
7625 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
7626 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7627 (match_operand:SI 2 "const_int_operand" "M,i")))]
7628 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
7629 "@
7630 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7631 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
7632 [(set_attr "type" "two,three")
7633 (set_attr "length" "8,12")])
7635 (define_insn "*ashrdisi3_noppc64"
7636 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7637 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7638 (const_int 32)) 4))]
7639 "TARGET_32BIT && !TARGET_POWERPC64"
7640 "*
7641 {
7642 if (REGNO (operands[0]) == REGNO (operands[1]))
7643 return \"\";
7644 else
7645 return \"mr %0,%1\";
7646 }"
7647 [(set_attr "length" "4")])
7649 \f
7650 ;; PowerPC64 DImode operations.
7652 (define_expand "absdi2"
7653 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7654 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
7655 "TARGET_POWERPC64"
7656 "
7657 {
7658 if (TARGET_ISEL)
7659 emit_insn (gen_absdi2_isel (operands[0], operands[1]));
7660 else
7661 emit_insn (gen_absdi2_internal (operands[0], operands[1]));
7662 DONE;
7663 }")
7665 (define_insn_and_split "absdi2_internal"
7666 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7667 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
7668 (clobber (match_scratch:DI 2 "=&r,&r"))]
7669 "TARGET_POWERPC64 && !TARGET_ISEL"
7670 "#"
7671 "&& reload_completed"
7672 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7673 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7674 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
7675 "")
7677 (define_insn_and_split "*nabsdi2"
7678 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7679 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
7680 (clobber (match_scratch:DI 2 "=&r,&r"))]
7681 "TARGET_POWERPC64 && !TARGET_ISEL"
7682 "#"
7683 "&& reload_completed"
7684 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7685 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7686 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7687 "")
7689 (define_insn "muldi3"
7690 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7691 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7692 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
7693 "TARGET_POWERPC64"
7694 "@
7695 mulld %0,%1,%2
7696 mulli %0,%1,%2"
7697 [(set (attr "type")
7698 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
7699 (const_string "imul3")
7700 (match_operand:SI 2 "short_cint_operand" "")
7701 (const_string "imul2")]
7702 (const_string "lmul")))])
7704 (define_insn "*muldi3_internal1"
7705 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7706 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7707 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7708 (const_int 0)))
7709 (clobber (match_scratch:DI 3 "=r,r"))]
7710 "TARGET_POWERPC64"
7711 "@
7712 mulld. %3,%1,%2
7713 #"
7714 [(set_attr "type" "lmul_compare")
7715 (set_attr "length" "4,8")])
7717 (define_split
7718 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7719 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7720 (match_operand:DI 2 "gpc_reg_operand" ""))
7721 (const_int 0)))
7722 (clobber (match_scratch:DI 3 ""))]
7723 "TARGET_POWERPC64 && reload_completed"
7724 [(set (match_dup 3)
7725 (mult:DI (match_dup 1) (match_dup 2)))
7726 (set (match_dup 0)
7727 (compare:CC (match_dup 3)
7728 (const_int 0)))]
7729 "")
7731 (define_insn "*muldi3_internal2"
7732 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7733 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7734 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7735 (const_int 0)))
7736 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7737 (mult:DI (match_dup 1) (match_dup 2)))]
7738 "TARGET_POWERPC64"
7739 "@
7740 mulld. %0,%1,%2
7741 #"
7742 [(set_attr "type" "lmul_compare")
7743 (set_attr "length" "4,8")])
7745 (define_split
7746 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7747 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7748 (match_operand:DI 2 "gpc_reg_operand" ""))
7749 (const_int 0)))
7750 (set (match_operand:DI 0 "gpc_reg_operand" "")
7751 (mult:DI (match_dup 1) (match_dup 2)))]
7752 "TARGET_POWERPC64 && reload_completed"
7753 [(set (match_dup 0)
7754 (mult:DI (match_dup 1) (match_dup 2)))
7755 (set (match_dup 3)
7756 (compare:CC (match_dup 0)
7757 (const_int 0)))]
7758 "")
7760 (define_insn "smuldi3_highpart"
7761 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7762 (truncate:DI
7763 (lshiftrt:TI (mult:TI (sign_extend:TI
7764 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7765 (sign_extend:TI
7766 (match_operand:DI 2 "gpc_reg_operand" "r")))
7767 (const_int 64))))]
7768 "TARGET_POWERPC64"
7769 "mulhd %0,%1,%2"
7770 [(set_attr "type" "lmul")])
7772 (define_insn "umuldi3_highpart"
7773 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7774 (truncate:DI
7775 (lshiftrt:TI (mult:TI (zero_extend:TI
7776 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7777 (zero_extend:TI
7778 (match_operand:DI 2 "gpc_reg_operand" "r")))
7779 (const_int 64))))]
7780 "TARGET_POWERPC64"
7781 "mulhdu %0,%1,%2"
7782 [(set_attr "type" "lmul")])
7784 (define_insn "rotldi3"
7785 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7786 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7787 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7788 "TARGET_POWERPC64"
7789 "@
7790 rldcl %0,%1,%2,0
7791 rldicl %0,%1,%H2,0"
7792 [(set_attr "type" "var_shift_rotate,integer")])
7794 (define_insn "*rotldi3_internal2"
7795 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7796 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7797 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7798 (const_int 0)))
7799 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7800 "TARGET_64BIT"
7801 "@
7802 rldcl. %3,%1,%2,0
7803 rldicl. %3,%1,%H2,0
7804 #
7805 #"
7806 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7807 (set_attr "length" "4,4,8,8")])
7809 (define_split
7810 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7811 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7812 (match_operand:DI 2 "reg_or_cint_operand" ""))
7813 (const_int 0)))
7814 (clobber (match_scratch:DI 3 ""))]
7815 "TARGET_POWERPC64 && reload_completed"
7816 [(set (match_dup 3)
7817 (rotate:DI (match_dup 1) (match_dup 2)))
7818 (set (match_dup 0)
7819 (compare:CC (match_dup 3)
7820 (const_int 0)))]
7821 "")
7823 (define_insn "*rotldi3_internal3"
7824 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7825 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7826 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7827 (const_int 0)))
7828 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7829 (rotate:DI (match_dup 1) (match_dup 2)))]
7830 "TARGET_64BIT"
7831 "@
7832 rldcl. %0,%1,%2,0
7833 rldicl. %0,%1,%H2,0
7834 #
7835 #"
7836 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7837 (set_attr "length" "4,4,8,8")])
7839 (define_split
7840 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7841 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7842 (match_operand:DI 2 "reg_or_cint_operand" ""))
7843 (const_int 0)))
7844 (set (match_operand:DI 0 "gpc_reg_operand" "")
7845 (rotate:DI (match_dup 1) (match_dup 2)))]
7846 "TARGET_POWERPC64 && reload_completed"
7847 [(set (match_dup 0)
7848 (rotate:DI (match_dup 1) (match_dup 2)))
7849 (set (match_dup 3)
7850 (compare:CC (match_dup 0)
7851 (const_int 0)))]
7852 "")
7854 (define_insn "*rotldi3_internal4"
7855 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7856 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7857 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7858 (match_operand:DI 3 "mask64_operand" "n,n")))]
7859 "TARGET_POWERPC64"
7860 "@
7861 rldc%B3 %0,%1,%2,%S3
7862 rldic%B3 %0,%1,%H2,%S3"
7863 [(set_attr "type" "var_shift_rotate,integer")])
7865 (define_insn "*rotldi3_internal5"
7866 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7867 (compare:CC (and:DI
7868 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7869 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7870 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7871 (const_int 0)))
7872 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7873 "TARGET_64BIT"
7874 "@
7875 rldc%B3. %4,%1,%2,%S3
7876 rldic%B3. %4,%1,%H2,%S3
7877 #
7878 #"
7879 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7880 (set_attr "length" "4,4,8,8")])
7882 (define_split
7883 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7884 (compare:CC (and:DI
7885 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7886 (match_operand:DI 2 "reg_or_cint_operand" ""))
7887 (match_operand:DI 3 "mask64_operand" ""))
7888 (const_int 0)))
7889 (clobber (match_scratch:DI 4 ""))]
7890 "TARGET_POWERPC64 && reload_completed"
7891 [(set (match_dup 4)
7892 (and:DI (rotate:DI (match_dup 1)
7893 (match_dup 2))
7894 (match_dup 3)))
7895 (set (match_dup 0)
7896 (compare:CC (match_dup 4)
7897 (const_int 0)))]
7898 "")
7900 (define_insn "*rotldi3_internal6"
7901 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
7902 (compare:CC (and:DI
7903 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7904 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7905 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7906 (const_int 0)))
7907 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7908 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7909 "TARGET_64BIT"
7910 "@
7911 rldc%B3. %0,%1,%2,%S3
7912 rldic%B3. %0,%1,%H2,%S3
7913 #
7914 #"
7915 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7916 (set_attr "length" "4,4,8,8")])
7918 (define_split
7919 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7920 (compare:CC (and:DI
7921 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7922 (match_operand:DI 2 "reg_or_cint_operand" ""))
7923 (match_operand:DI 3 "mask64_operand" ""))
7924 (const_int 0)))
7925 (set (match_operand:DI 0 "gpc_reg_operand" "")
7926 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7927 "TARGET_POWERPC64 && reload_completed"
7928 [(set (match_dup 0)
7929 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7930 (set (match_dup 4)
7931 (compare:CC (match_dup 0)
7932 (const_int 0)))]
7933 "")
7935 (define_insn "*rotldi3_internal7"
7936 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7937 (zero_extend:DI
7938 (subreg:QI
7939 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7940 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7941 "TARGET_POWERPC64"
7942 "@
7943 rldcl %0,%1,%2,56
7944 rldicl %0,%1,%H2,56"
7945 [(set_attr "type" "var_shift_rotate,integer")])
7947 (define_insn "*rotldi3_internal8"
7948 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7949 (compare:CC (zero_extend:DI
7950 (subreg:QI
7951 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7952 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7953 (const_int 0)))
7954 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7955 "TARGET_64BIT"
7956 "@
7957 rldcl. %3,%1,%2,56
7958 rldicl. %3,%1,%H2,56
7959 #
7960 #"
7961 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7962 (set_attr "length" "4,4,8,8")])
7964 (define_split
7965 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7966 (compare:CC (zero_extend:DI
7967 (subreg:QI
7968 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7969 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7970 (const_int 0)))
7971 (clobber (match_scratch:DI 3 ""))]
7972 "TARGET_POWERPC64 && reload_completed"
7973 [(set (match_dup 3)
7974 (zero_extend:DI (subreg:QI
7975 (rotate:DI (match_dup 1)
7976 (match_dup 2)) 0)))
7977 (set (match_dup 0)
7978 (compare:CC (match_dup 3)
7979 (const_int 0)))]
7980 "")
7982 (define_insn "*rotldi3_internal9"
7983 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7984 (compare:CC (zero_extend:DI
7985 (subreg:QI
7986 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7987 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7988 (const_int 0)))
7989 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7990 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7991 "TARGET_64BIT"
7992 "@
7993 rldcl. %0,%1,%2,56
7994 rldicl. %0,%1,%H2,56
7995 #
7996 #"
7997 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7998 (set_attr "length" "4,4,8,8")])
8000 (define_split
8001 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8002 (compare:CC (zero_extend:DI
8003 (subreg:QI
8004 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8005 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8006 (const_int 0)))
8007 (set (match_operand:DI 0 "gpc_reg_operand" "")
8008 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8009 "TARGET_POWERPC64 && reload_completed"
8010 [(set (match_dup 0)
8011 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8012 (set (match_dup 3)
8013 (compare:CC (match_dup 0)
8014 (const_int 0)))]
8015 "")
8017 (define_insn "*rotldi3_internal10"
8018 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8019 (zero_extend:DI
8020 (subreg:HI
8021 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8022 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
8023 "TARGET_POWERPC64"
8024 "@
8025 rldcl %0,%1,%2,48
8026 rldicl %0,%1,%H2,48"
8027 [(set_attr "type" "var_shift_rotate,integer")])
8029 (define_insn "*rotldi3_internal11"
8030 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8031 (compare:CC (zero_extend:DI
8032 (subreg:HI
8033 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8034 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8035 (const_int 0)))
8036 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8037 "TARGET_64BIT"
8038 "@
8039 rldcl. %3,%1,%2,48
8040 rldicl. %3,%1,%H2,48
8041 #
8042 #"
8043 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8044 (set_attr "length" "4,4,8,8")])
8046 (define_split
8047 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8048 (compare:CC (zero_extend:DI
8049 (subreg:HI
8050 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8051 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8052 (const_int 0)))
8053 (clobber (match_scratch:DI 3 ""))]
8054 "TARGET_POWERPC64 && reload_completed"
8055 [(set (match_dup 3)
8056 (zero_extend:DI (subreg:HI
8057 (rotate:DI (match_dup 1)
8058 (match_dup 2)) 0)))
8059 (set (match_dup 0)
8060 (compare:CC (match_dup 3)
8061 (const_int 0)))]
8062 "")
8064 (define_insn "*rotldi3_internal12"
8065 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8066 (compare:CC (zero_extend:DI
8067 (subreg:HI
8068 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8069 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8070 (const_int 0)))
8071 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8072 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8073 "TARGET_64BIT"
8074 "@
8075 rldcl. %0,%1,%2,48
8076 rldicl. %0,%1,%H2,48
8077 #
8078 #"
8079 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8080 (set_attr "length" "4,4,8,8")])
8082 (define_split
8083 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8084 (compare:CC (zero_extend:DI
8085 (subreg:HI
8086 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8087 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8088 (const_int 0)))
8089 (set (match_operand:DI 0 "gpc_reg_operand" "")
8090 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8091 "TARGET_POWERPC64 && reload_completed"
8092 [(set (match_dup 0)
8093 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8094 (set (match_dup 3)
8095 (compare:CC (match_dup 0)
8096 (const_int 0)))]
8097 "")
8099 (define_insn "*rotldi3_internal13"
8100 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8101 (zero_extend:DI
8102 (subreg:SI
8103 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8104 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
8105 "TARGET_POWERPC64"
8106 "@
8107 rldcl %0,%1,%2,32
8108 rldicl %0,%1,%H2,32"
8109 [(set_attr "type" "var_shift_rotate,integer")])
8111 (define_insn "*rotldi3_internal14"
8112 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8113 (compare:CC (zero_extend:DI
8114 (subreg:SI
8115 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8116 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8117 (const_int 0)))
8118 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8119 "TARGET_64BIT"
8120 "@
8121 rldcl. %3,%1,%2,32
8122 rldicl. %3,%1,%H2,32
8123 #
8124 #"
8125 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8126 (set_attr "length" "4,4,8,8")])
8128 (define_split
8129 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8130 (compare:CC (zero_extend:DI
8131 (subreg:SI
8132 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8133 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8134 (const_int 0)))
8135 (clobber (match_scratch:DI 3 ""))]
8136 "TARGET_POWERPC64 && reload_completed"
8137 [(set (match_dup 3)
8138 (zero_extend:DI (subreg:SI
8139 (rotate:DI (match_dup 1)
8140 (match_dup 2)) 0)))
8141 (set (match_dup 0)
8142 (compare:CC (match_dup 3)
8143 (const_int 0)))]
8144 "")
8146 (define_insn "*rotldi3_internal15"
8147 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8148 (compare:CC (zero_extend:DI
8149 (subreg:SI
8150 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8151 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8152 (const_int 0)))
8153 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8154 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8155 "TARGET_64BIT"
8156 "@
8157 rldcl. %0,%1,%2,32
8158 rldicl. %0,%1,%H2,32
8159 #
8160 #"
8161 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8162 (set_attr "length" "4,4,8,8")])
8164 (define_split
8165 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8166 (compare:CC (zero_extend:DI
8167 (subreg:SI
8168 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8169 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8170 (const_int 0)))
8171 (set (match_operand:DI 0 "gpc_reg_operand" "")
8172 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8173 "TARGET_POWERPC64 && reload_completed"
8174 [(set (match_dup 0)
8175 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8176 (set (match_dup 3)
8177 (compare:CC (match_dup 0)
8178 (const_int 0)))]
8179 "")
8181 (define_expand "ashldi3"
8182 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8183 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8184 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8185 "TARGET_POWERPC64 || TARGET_POWER"
8186 "
8187 {
8188 if (TARGET_POWERPC64)
8189 ;
8190 else if (TARGET_POWER)
8191 {
8192 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
8193 DONE;
8194 }
8195 else
8196 FAIL;
8197 }")
8199 (define_insn "*ashldi3_internal1"
8200 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8201 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8202 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8203 "TARGET_POWERPC64"
8204 "@
8205 sld %0,%1,%2
8206 sldi %0,%1,%H2"
8207 [(set_attr "type" "var_shift_rotate,shift")])
8209 (define_insn "*ashldi3_internal2"
8210 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8211 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8212 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8213 (const_int 0)))
8214 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8215 "TARGET_64BIT"
8216 "@
8217 sld. %3,%1,%2
8218 sldi. %3,%1,%H2
8219 #
8220 #"
8221 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8222 (set_attr "length" "4,4,8,8")])
8224 (define_split
8225 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8226 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8227 (match_operand:SI 2 "reg_or_cint_operand" ""))
8228 (const_int 0)))
8229 (clobber (match_scratch:DI 3 ""))]
8230 "TARGET_POWERPC64 && reload_completed"
8231 [(set (match_dup 3)
8232 (ashift:DI (match_dup 1) (match_dup 2)))
8233 (set (match_dup 0)
8234 (compare:CC (match_dup 3)
8235 (const_int 0)))]
8236 "")
8238 (define_insn "*ashldi3_internal3"
8239 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8240 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8241 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8242 (const_int 0)))
8243 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8244 (ashift:DI (match_dup 1) (match_dup 2)))]
8245 "TARGET_64BIT"
8246 "@
8247 sld. %0,%1,%2
8248 sldi. %0,%1,%H2
8249 #
8250 #"
8251 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8252 (set_attr "length" "4,4,8,8")])
8254 (define_split
8255 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8256 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8257 (match_operand:SI 2 "reg_or_cint_operand" ""))
8258 (const_int 0)))
8259 (set (match_operand:DI 0 "gpc_reg_operand" "")
8260 (ashift:DI (match_dup 1) (match_dup 2)))]
8261 "TARGET_POWERPC64 && reload_completed"
8262 [(set (match_dup 0)
8263 (ashift:DI (match_dup 1) (match_dup 2)))
8264 (set (match_dup 3)
8265 (compare:CC (match_dup 0)
8266 (const_int 0)))]
8267 "")
8269 (define_insn "*ashldi3_internal4"
8270 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8271 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
8272 (match_operand:SI 2 "const_int_operand" "i"))
8273 (match_operand:DI 3 "const_int_operand" "n")))]
8274 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
8275 "rldic %0,%1,%H2,%W3")
8277 (define_insn "ashldi3_internal5"
8278 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8279 (compare:CC
8280 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8281 (match_operand:SI 2 "const_int_operand" "i,i"))
8282 (match_operand:DI 3 "const_int_operand" "n,n"))
8283 (const_int 0)))
8284 (clobber (match_scratch:DI 4 "=r,r"))]
8285 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
8286 "@
8287 rldic. %4,%1,%H2,%W3
8288 #"
8289 [(set_attr "type" "compare")
8290 (set_attr "length" "4,8")])
8292 (define_split
8293 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8294 (compare:CC
8295 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8296 (match_operand:SI 2 "const_int_operand" ""))
8297 (match_operand:DI 3 "const_int_operand" ""))
8298 (const_int 0)))
8299 (clobber (match_scratch:DI 4 ""))]
8300 "TARGET_POWERPC64 && reload_completed
8301 && includes_rldic_lshift_p (operands[2], operands[3])"
8302 [(set (match_dup 4)
8303 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8304 (match_dup 3)))
8305 (set (match_dup 0)
8306 (compare:CC (match_dup 4)
8307 (const_int 0)))]
8308 "")
8310 (define_insn "*ashldi3_internal6"
8311 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
8312 (compare:CC
8313 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8314 (match_operand:SI 2 "const_int_operand" "i,i"))
8315 (match_operand:DI 3 "const_int_operand" "n,n"))
8316 (const_int 0)))
8317 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8318 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8319 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
8320 "@
8321 rldic. %0,%1,%H2,%W3
8322 #"
8323 [(set_attr "type" "compare")
8324 (set_attr "length" "4,8")])
8326 (define_split
8327 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8328 (compare:CC
8329 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8330 (match_operand:SI 2 "const_int_operand" ""))
8331 (match_operand:DI 3 "const_int_operand" ""))
8332 (const_int 0)))
8333 (set (match_operand:DI 0 "gpc_reg_operand" "")
8334 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8335 "TARGET_POWERPC64 && reload_completed
8336 && includes_rldic_lshift_p (operands[2], operands[3])"
8337 [(set (match_dup 0)
8338 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8339 (match_dup 3)))
8340 (set (match_dup 4)
8341 (compare:CC (match_dup 0)
8342 (const_int 0)))]
8343 "")
8345 (define_insn "*ashldi3_internal7"
8346 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8347 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
8348 (match_operand:SI 2 "const_int_operand" "i"))
8349 (match_operand:DI 3 "mask64_operand" "n")))]
8350 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
8351 "rldicr %0,%1,%H2,%S3")
8353 (define_insn "ashldi3_internal8"
8354 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8355 (compare:CC
8356 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8357 (match_operand:SI 2 "const_int_operand" "i,i"))
8358 (match_operand:DI 3 "mask64_operand" "n,n"))
8359 (const_int 0)))
8360 (clobber (match_scratch:DI 4 "=r,r"))]
8361 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
8362 "@
8363 rldicr. %4,%1,%H2,%S3
8364 #"
8365 [(set_attr "type" "compare")
8366 (set_attr "length" "4,8")])
8368 (define_split
8369 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8370 (compare:CC
8371 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8372 (match_operand:SI 2 "const_int_operand" ""))
8373 (match_operand:DI 3 "mask64_operand" ""))
8374 (const_int 0)))
8375 (clobber (match_scratch:DI 4 ""))]
8376 "TARGET_POWERPC64 && reload_completed
8377 && includes_rldicr_lshift_p (operands[2], operands[3])"
8378 [(set (match_dup 4)
8379 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8380 (match_dup 3)))
8381 (set (match_dup 0)
8382 (compare:CC (match_dup 4)
8383 (const_int 0)))]
8384 "")
8386 (define_insn "*ashldi3_internal9"
8387 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
8388 (compare:CC
8389 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8390 (match_operand:SI 2 "const_int_operand" "i,i"))
8391 (match_operand:DI 3 "mask64_operand" "n,n"))
8392 (const_int 0)))
8393 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8394 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8395 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
8396 "@
8397 rldicr. %0,%1,%H2,%S3
8398 #"
8399 [(set_attr "type" "compare")
8400 (set_attr "length" "4,8")])
8402 (define_split
8403 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8404 (compare:CC
8405 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8406 (match_operand:SI 2 "const_int_operand" ""))
8407 (match_operand:DI 3 "mask64_operand" ""))
8408 (const_int 0)))
8409 (set (match_operand:DI 0 "gpc_reg_operand" "")
8410 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8411 "TARGET_POWERPC64 && reload_completed
8412 && includes_rldicr_lshift_p (operands[2], operands[3])"
8413 [(set (match_dup 0)
8414 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8415 (match_dup 3)))
8416 (set (match_dup 4)
8417 (compare:CC (match_dup 0)
8418 (const_int 0)))]
8419 "")
8421 (define_expand "lshrdi3"
8422 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8423 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8424 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8425 "TARGET_POWERPC64 || TARGET_POWER"
8426 "
8427 {
8428 if (TARGET_POWERPC64)
8429 ;
8430 else if (TARGET_POWER)
8431 {
8432 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
8433 DONE;
8434 }
8435 else
8436 FAIL;
8437 }")
8439 (define_insn "*lshrdi3_internal1"
8440 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8441 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8442 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8443 "TARGET_POWERPC64"
8444 "@
8445 srd %0,%1,%2
8446 srdi %0,%1,%H2"
8447 [(set_attr "type" "var_shift_rotate,shift")])
8449 (define_insn "*lshrdi3_internal2"
8450 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8451 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8452 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8453 (const_int 0)))
8454 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8455 "TARGET_64BIT "
8456 "@
8457 srd. %3,%1,%2
8458 srdi. %3,%1,%H2
8459 #
8460 #"
8461 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8462 (set_attr "length" "4,4,8,8")])
8464 (define_split
8465 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8466 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8467 (match_operand:SI 2 "reg_or_cint_operand" ""))
8468 (const_int 0)))
8469 (clobber (match_scratch:DI 3 ""))]
8470 "TARGET_POWERPC64 && reload_completed"
8471 [(set (match_dup 3)
8472 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8473 (set (match_dup 0)
8474 (compare:CC (match_dup 3)
8475 (const_int 0)))]
8476 "")
8478 (define_insn "*lshrdi3_internal3"
8479 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8480 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8481 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8482 (const_int 0)))
8483 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8484 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8485 "TARGET_64BIT"
8486 "@
8487 srd. %0,%1,%2
8488 srdi. %0,%1,%H2
8489 #
8490 #"
8491 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8492 (set_attr "length" "4,4,8,8")])
8494 (define_split
8495 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8496 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8497 (match_operand:SI 2 "reg_or_cint_operand" ""))
8498 (const_int 0)))
8499 (set (match_operand:DI 0 "gpc_reg_operand" "")
8500 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8501 "TARGET_POWERPC64 && reload_completed"
8502 [(set (match_dup 0)
8503 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8504 (set (match_dup 3)
8505 (compare:CC (match_dup 0)
8506 (const_int 0)))]
8507 "")
8509 (define_expand "ashrdi3"
8510 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8511 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8512 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8513 "WORDS_BIG_ENDIAN"
8514 "
8515 {
8516 if (TARGET_POWERPC64)
8517 ;
8518 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
8519 {
8520 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
8521 DONE;
8522 }
8523 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
8524 && WORDS_BIG_ENDIAN)
8525 {
8526 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
8527 DONE;
8528 }
8529 else
8530 FAIL;
8531 }")
8533 (define_insn "*ashrdi3_internal1"
8534 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8535 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8536 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8537 "TARGET_POWERPC64"
8538 "@
8539 srad %0,%1,%2
8540 sradi %0,%1,%H2"
8541 [(set_attr "type" "var_shift_rotate,shift")])
8543 (define_insn "*ashrdi3_internal2"
8544 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8545 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8546 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8547 (const_int 0)))
8548 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8549 "TARGET_64BIT"
8550 "@
8551 srad. %3,%1,%2
8552 sradi. %3,%1,%H2
8553 #
8554 #"
8555 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8556 (set_attr "length" "4,4,8,8")])
8558 (define_split
8559 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8560 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8561 (match_operand:SI 2 "reg_or_cint_operand" ""))
8562 (const_int 0)))
8563 (clobber (match_scratch:DI 3 ""))]
8564 "TARGET_POWERPC64 && reload_completed"
8565 [(set (match_dup 3)
8566 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8567 (set (match_dup 0)
8568 (compare:CC (match_dup 3)
8569 (const_int 0)))]
8570 "")
8572 (define_insn "*ashrdi3_internal3"
8573 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8574 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8575 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8576 (const_int 0)))
8577 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8578 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8579 "TARGET_64BIT"
8580 "@
8581 srad. %0,%1,%2
8582 sradi. %0,%1,%H2
8583 #
8584 #"
8585 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8586 (set_attr "length" "4,4,8,8")])
8588 (define_split
8589 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8590 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8591 (match_operand:SI 2 "reg_or_cint_operand" ""))
8592 (const_int 0)))
8593 (set (match_operand:DI 0 "gpc_reg_operand" "")
8594 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8595 "TARGET_POWERPC64 && reload_completed"
8596 [(set (match_dup 0)
8597 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8598 (set (match_dup 3)
8599 (compare:CC (match_dup 0)
8600 (const_int 0)))]
8601 "")
8603 (define_expand "anddi3"
8604 [(parallel
8605 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8606 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8607 (match_operand:DI 2 "and64_2_operand" "")))
8608 (clobber (match_scratch:CC 3 ""))])]
8609 "TARGET_POWERPC64"
8610 "")
8612 (define_insn "anddi3_mc"
8613 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8614 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8615 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8616 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8617 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8618 "@
8619 and %0,%1,%2
8620 rldic%B2 %0,%1,0,%S2
8621 rlwinm %0,%1,0,%m2,%M2
8622 andi. %0,%1,%b2
8623 andis. %0,%1,%u2
8624 #"
8625 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8626 (set_attr "length" "4,4,4,4,4,8")])
8628 (define_insn "anddi3_nomc"
8629 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8630 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8631 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8632 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8633 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8634 "@
8635 and %0,%1,%2
8636 rldic%B2 %0,%1,0,%S2
8637 rlwinm %0,%1,0,%m2,%M2
8638 #"
8639 [(set_attr "length" "4,4,4,8")])
8641 (define_split
8642 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8643 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8644 (match_operand:DI 2 "mask64_2_operand" "")))
8645 (clobber (match_scratch:CC 3 ""))]
8646 "TARGET_POWERPC64
8647 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8648 && !mask_operand (operands[2], DImode)
8649 && !mask64_operand (operands[2], DImode)"
8650 [(set (match_dup 0)
8651 (and:DI (rotate:DI (match_dup 1)
8652 (match_dup 4))
8653 (match_dup 5)))
8654 (set (match_dup 0)
8655 (and:DI (rotate:DI (match_dup 0)
8656 (match_dup 6))
8657 (match_dup 7)))]
8658 {
8659 build_mask64_2_operands (operands[2], &operands[4]);
8660 })
8662 (define_insn "*anddi3_internal2_mc"
8663 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8664 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8665 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8666 (const_int 0)))
8667 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8668 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8669 "TARGET_64BIT && rs6000_gen_cell_microcode"
8670 "@
8671 and. %3,%1,%2
8672 rldic%B2. %3,%1,0,%S2
8673 rlwinm. %3,%1,0,%m2,%M2
8674 andi. %3,%1,%b2
8675 andis. %3,%1,%u2
8676 #
8677 #
8678 #
8679 #
8680 #
8681 #
8682 #"
8683 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8684 fast_compare,compare,compare,compare,compare,compare,\
8685 compare,compare")
8686 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8688 (define_split
8689 [(set (match_operand:CC 0 "cc_reg_operand" "")
8690 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8691 (match_operand:DI 2 "mask64_2_operand" ""))
8692 (const_int 0)))
8693 (clobber (match_scratch:DI 3 ""))
8694 (clobber (match_scratch:CC 4 ""))]
8695 "TARGET_64BIT && reload_completed
8696 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8697 && !mask_operand (operands[2], DImode)
8698 && !mask64_operand (operands[2], DImode)"
8699 [(set (match_dup 3)
8700 (and:DI (rotate:DI (match_dup 1)
8701 (match_dup 5))
8702 (match_dup 6)))
8703 (parallel [(set (match_dup 0)
8704 (compare:CC (and:DI (rotate:DI (match_dup 3)
8705 (match_dup 7))
8706 (match_dup 8))
8707 (const_int 0)))
8708 (clobber (match_dup 3))])]
8709 "
8710 {
8711 build_mask64_2_operands (operands[2], &operands[5]);
8712 }")
8714 (define_insn "*anddi3_internal3_mc"
8715 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8716 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8717 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8718 (const_int 0)))
8719 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8720 (and:DI (match_dup 1) (match_dup 2)))
8721 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8722 "TARGET_64BIT && rs6000_gen_cell_microcode"
8723 "@
8724 and. %0,%1,%2
8725 rldic%B2. %0,%1,0,%S2
8726 rlwinm. %0,%1,0,%m2,%M2
8727 andi. %0,%1,%b2
8728 andis. %0,%1,%u2
8729 #
8730 #
8731 #
8732 #
8733 #
8734 #
8735 #"
8736 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8737 fast_compare,compare,compare,compare,compare,compare,\
8738 compare,compare")
8739 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8741 (define_split
8742 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8743 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8744 (match_operand:DI 2 "and64_2_operand" ""))
8745 (const_int 0)))
8746 (set (match_operand:DI 0 "gpc_reg_operand" "")
8747 (and:DI (match_dup 1) (match_dup 2)))
8748 (clobber (match_scratch:CC 4 ""))]
8749 "TARGET_64BIT && reload_completed"
8750 [(parallel [(set (match_dup 0)
8751 (and:DI (match_dup 1) (match_dup 2)))
8752 (clobber (match_dup 4))])
8753 (set (match_dup 3)
8754 (compare:CC (match_dup 0)
8755 (const_int 0)))]
8756 "")
8758 (define_split
8759 [(set (match_operand:CC 3 "cc_reg_operand" "")
8760 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8761 (match_operand:DI 2 "mask64_2_operand" ""))
8762 (const_int 0)))
8763 (set (match_operand:DI 0 "gpc_reg_operand" "")
8764 (and:DI (match_dup 1) (match_dup 2)))
8765 (clobber (match_scratch:CC 4 ""))]
8766 "TARGET_64BIT && reload_completed
8767 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8768 && !mask_operand (operands[2], DImode)
8769 && !mask64_operand (operands[2], DImode)"
8770 [(set (match_dup 0)
8771 (and:DI (rotate:DI (match_dup 1)
8772 (match_dup 5))
8773 (match_dup 6)))
8774 (parallel [(set (match_dup 3)
8775 (compare:CC (and:DI (rotate:DI (match_dup 0)
8776 (match_dup 7))
8777 (match_dup 8))
8778 (const_int 0)))
8779 (set (match_dup 0)
8780 (and:DI (rotate:DI (match_dup 0)
8781 (match_dup 7))
8782 (match_dup 8)))])]
8783 "
8784 {
8785 build_mask64_2_operands (operands[2], &operands[5]);
8786 }")
8788 (define_expand "iordi3"
8789 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8790 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8791 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8792 "TARGET_POWERPC64"
8793 "
8794 {
8795 if (non_logical_cint_operand (operands[2], DImode))
8796 {
8797 HOST_WIDE_INT value;
8798 rtx tmp = ((!can_create_pseudo_p ()
8799 || rtx_equal_p (operands[0], operands[1]))
8800 ? operands[0] : gen_reg_rtx (DImode));
8802 if (GET_CODE (operands[2]) == CONST_INT)
8803 {
8804 value = INTVAL (operands[2]);
8805 emit_insn (gen_iordi3 (tmp, operands[1],
8806 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8807 }
8808 else
8809 {
8810 value = CONST_DOUBLE_LOW (operands[2]);
8811 emit_insn (gen_iordi3 (tmp, operands[1],
8812 immed_double_const (value
8813 & (~ (HOST_WIDE_INT) 0xffff),
8814 0, DImode)));
8815 }
8817 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8818 DONE;
8819 }
8820 }")
8822 (define_expand "xordi3"
8823 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8824 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8825 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8826 "TARGET_POWERPC64"
8827 "
8828 {
8829 if (non_logical_cint_operand (operands[2], DImode))
8830 {
8831 HOST_WIDE_INT value;
8832 rtx tmp = ((!can_create_pseudo_p ()
8833 || rtx_equal_p (operands[0], operands[1]))
8834 ? operands[0] : gen_reg_rtx (DImode));
8836 if (GET_CODE (operands[2]) == CONST_INT)
8837 {
8838 value = INTVAL (operands[2]);
8839 emit_insn (gen_xordi3 (tmp, operands[1],
8840 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8841 }
8842 else
8843 {
8844 value = CONST_DOUBLE_LOW (operands[2]);
8845 emit_insn (gen_xordi3 (tmp, operands[1],
8846 immed_double_const (value
8847 & (~ (HOST_WIDE_INT) 0xffff),
8848 0, DImode)));
8849 }
8851 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8852 DONE;
8853 }
8854 }")
8856 (define_insn "*booldi3_internal1"
8857 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8858 (match_operator:DI 3 "boolean_or_operator"
8859 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8860 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8861 "TARGET_POWERPC64"
8862 "@
8863 %q3 %0,%1,%2
8864 %q3i %0,%1,%b2
8865 %q3is %0,%1,%u2")
8867 (define_insn "*booldi3_internal2"
8868 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8869 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8870 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8871 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8872 (const_int 0)))
8873 (clobber (match_scratch:DI 3 "=r,r"))]
8874 "TARGET_64BIT"
8875 "@
8876 %q4. %3,%1,%2
8877 #"
8878 [(set_attr "type" "fast_compare,compare")
8879 (set_attr "length" "4,8")])
8881 (define_split
8882 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8883 (compare:CC (match_operator:DI 4 "boolean_operator"
8884 [(match_operand:DI 1 "gpc_reg_operand" "")
8885 (match_operand:DI 2 "gpc_reg_operand" "")])
8886 (const_int 0)))
8887 (clobber (match_scratch:DI 3 ""))]
8888 "TARGET_POWERPC64 && reload_completed"
8889 [(set (match_dup 3) (match_dup 4))
8890 (set (match_dup 0)
8891 (compare:CC (match_dup 3)
8892 (const_int 0)))]
8893 "")
8895 (define_insn "*booldi3_internal3"
8896 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8897 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8898 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8899 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8900 (const_int 0)))
8901 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8902 (match_dup 4))]
8903 "TARGET_64BIT"
8904 "@
8905 %q4. %0,%1,%2
8906 #"
8907 [(set_attr "type" "fast_compare,compare")
8908 (set_attr "length" "4,8")])
8910 (define_split
8911 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8912 (compare:CC (match_operator:DI 4 "boolean_operator"
8913 [(match_operand:DI 1 "gpc_reg_operand" "")
8914 (match_operand:DI 2 "gpc_reg_operand" "")])
8915 (const_int 0)))
8916 (set (match_operand:DI 0 "gpc_reg_operand" "")
8917 (match_dup 4))]
8918 "TARGET_POWERPC64 && reload_completed"
8919 [(set (match_dup 0) (match_dup 4))
8920 (set (match_dup 3)
8921 (compare:CC (match_dup 0)
8922 (const_int 0)))]
8923 "")
8925 ;; Split a logical operation that we can't do in one insn into two insns,
8926 ;; each of which does one 16-bit part. This is used by combine.
8928 (define_split
8929 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8930 (match_operator:DI 3 "boolean_or_operator"
8931 [(match_operand:DI 1 "gpc_reg_operand" "")
8932 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8933 "TARGET_POWERPC64"
8934 [(set (match_dup 0) (match_dup 4))
8935 (set (match_dup 0) (match_dup 5))]
8936 "
8937 {
8938 rtx i3,i4;
8940 if (GET_CODE (operands[2]) == CONST_DOUBLE)
8941 {
8942 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
8943 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
8944 0, DImode);
8945 i4 = GEN_INT (value & 0xffff);
8946 }
8947 else
8948 {
8949 i3 = GEN_INT (INTVAL (operands[2])
8950 & (~ (HOST_WIDE_INT) 0xffff));
8951 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8952 }
8953 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8954 operands[1], i3);
8955 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8956 operands[0], i4);
8957 }")
8959 (define_insn "*boolcdi3_internal1"
8960 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8961 (match_operator:DI 3 "boolean_operator"
8962 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8963 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8964 "TARGET_POWERPC64"
8965 "%q3 %0,%2,%1")
8967 (define_insn "*boolcdi3_internal2"
8968 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8969 (compare:CC (match_operator:DI 4 "boolean_operator"
8970 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8971 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8972 (const_int 0)))
8973 (clobber (match_scratch:DI 3 "=r,r"))]
8974 "TARGET_64BIT"
8975 "@
8976 %q4. %3,%2,%1
8977 #"
8978 [(set_attr "type" "fast_compare,compare")
8979 (set_attr "length" "4,8")])
8981 (define_split
8982 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8983 (compare:CC (match_operator:DI 4 "boolean_operator"
8984 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8985 (match_operand:DI 2 "gpc_reg_operand" "")])
8986 (const_int 0)))
8987 (clobber (match_scratch:DI 3 ""))]
8988 "TARGET_POWERPC64 && reload_completed"
8989 [(set (match_dup 3) (match_dup 4))
8990 (set (match_dup 0)
8991 (compare:CC (match_dup 3)
8992 (const_int 0)))]
8993 "")
8995 (define_insn "*boolcdi3_internal3"
8996 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8997 (compare:CC (match_operator:DI 4 "boolean_operator"
8998 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8999 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
9000 (const_int 0)))
9001 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
9002 (match_dup 4))]
9003 "TARGET_64BIT"
9004 "@
9005 %q4. %0,%2,%1
9006 #"
9007 [(set_attr "type" "fast_compare,compare")
9008 (set_attr "length" "4,8")])
9010 (define_split
9011 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9012 (compare:CC (match_operator:DI 4 "boolean_operator"
9013 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9014 (match_operand:DI 2 "gpc_reg_operand" "")])
9015 (const_int 0)))
9016 (set (match_operand:DI 0 "gpc_reg_operand" "")
9017 (match_dup 4))]
9018 "TARGET_POWERPC64 && reload_completed"
9019 [(set (match_dup 0) (match_dup 4))
9020 (set (match_dup 3)
9021 (compare:CC (match_dup 0)
9022 (const_int 0)))]
9023 "")
9025 (define_insn "*boolccdi3_internal1"
9026 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9027 (match_operator:DI 3 "boolean_operator"
9028 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
9029 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
9030 "TARGET_POWERPC64"
9031 "%q3 %0,%1,%2")
9033 (define_insn "*boolccdi3_internal2"
9034 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
9035 (compare:CC (match_operator:DI 4 "boolean_operator"
9036 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
9037 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
9038 (const_int 0)))
9039 (clobber (match_scratch:DI 3 "=r,r"))]
9040 "TARGET_64BIT"
9041 "@
9042 %q4. %3,%1,%2
9043 #"
9044 [(set_attr "type" "fast_compare,compare")
9045 (set_attr "length" "4,8")])
9047 (define_split
9048 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9049 (compare:CC (match_operator:DI 4 "boolean_operator"
9050 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9051 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
9052 (const_int 0)))
9053 (clobber (match_scratch:DI 3 ""))]
9054 "TARGET_POWERPC64 && reload_completed"
9055 [(set (match_dup 3) (match_dup 4))
9056 (set (match_dup 0)
9057 (compare:CC (match_dup 3)
9058 (const_int 0)))]
9059 "")
9061 (define_insn "*boolccdi3_internal3"
9062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9063 (compare:CC (match_operator:DI 4 "boolean_operator"
9064 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
9065 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
9066 (const_int 0)))
9067 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
9068 (match_dup 4))]
9069 "TARGET_64BIT"
9070 "@
9071 %q4. %0,%1,%2
9072 #"
9073 [(set_attr "type" "fast_compare,compare")
9074 (set_attr "length" "4,8")])
9076 (define_split
9077 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9078 (compare:CC (match_operator:DI 4 "boolean_operator"
9079 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9080 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
9081 (const_int 0)))
9082 (set (match_operand:DI 0 "gpc_reg_operand" "")
9083 (match_dup 4))]
9084 "TARGET_POWERPC64 && reload_completed"
9085 [(set (match_dup 0) (match_dup 4))
9086 (set (match_dup 3)
9087 (compare:CC (match_dup 0)
9088 (const_int 0)))]
9089 "")
9091 (define_expand "smindi3"
9092 [(match_operand:DI 0 "gpc_reg_operand" "")
9093 (match_operand:DI 1 "gpc_reg_operand" "")
9094 (match_operand:DI 2 "gpc_reg_operand" "")]
9095 "TARGET_ISEL64"
9096 "
9097 {
9098 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
9099 DONE;
9100 }")
9102 (define_expand "smaxdi3"
9103 [(match_operand:DI 0 "gpc_reg_operand" "")
9104 (match_operand:DI 1 "gpc_reg_operand" "")
9105 (match_operand:DI 2 "gpc_reg_operand" "")]
9106 "TARGET_ISEL64"
9107 "
9108 {
9109 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
9110 DONE;
9111 }")
9113 (define_expand "umindi3"
9114 [(match_operand:DI 0 "gpc_reg_operand" "")
9115 (match_operand:DI 1 "gpc_reg_operand" "")
9116 (match_operand:DI 2 "gpc_reg_operand" "")]
9117 "TARGET_ISEL64"
9118 "
9119 {
9120 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
9121 DONE;
9122 }")
9124 (define_expand "umaxdi3"
9125 [(match_operand:DI 0 "gpc_reg_operand" "")
9126 (match_operand:DI 1 "gpc_reg_operand" "")
9127 (match_operand:DI 2 "gpc_reg_operand" "")]
9128 "TARGET_ISEL64"
9129 "
9130 {
9131 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
9132 DONE;
9133 }")
9135 \f
9136 ;; Now define ways of moving data around.
9138 ;; Set up a register with a value from the GOT table
9140 (define_expand "movsi_got"
9141 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9142 (unspec:SI [(match_operand:SI 1 "got_operand" "")
9143 (match_dup 2)] UNSPEC_MOVSI_GOT))]
9144 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
9145 "
9146 {
9147 if (GET_CODE (operands[1]) == CONST)
9148 {
9149 rtx offset = const0_rtx;
9150 HOST_WIDE_INT value;
9152 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
9153 value = INTVAL (offset);
9154 if (value != 0)
9155 {
9156 rtx tmp = (!can_create_pseudo_p ()
9157 ? operands[0]
9158 : gen_reg_rtx (Pmode));
9159 emit_insn (gen_movsi_got (tmp, operands[1]));
9160 emit_insn (gen_addsi3 (operands[0], tmp, offset));
9161 DONE;
9162 }
9163 }
9165 operands[2] = rs6000_got_register (operands[1]);
9166 }")
9168 (define_insn "*movsi_got_internal"
9169 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9170 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
9171 (match_operand:SI 2 "gpc_reg_operand" "b")]
9172 UNSPEC_MOVSI_GOT))]
9173 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
9174 "{l|lwz} %0,%a1@got(%2)"
9175 [(set_attr "type" "load")])
9177 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
9178 ;; didn't get allocated to a hard register.
9179 (define_split
9180 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9181 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
9182 (match_operand:SI 2 "memory_operand" "")]
9183 UNSPEC_MOVSI_GOT))]
9184 "DEFAULT_ABI == ABI_V4
9185 && flag_pic == 1
9186 && (reload_in_progress || reload_completed)"
9187 [(set (match_dup 0) (match_dup 2))
9188 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
9189 UNSPEC_MOVSI_GOT))]
9190 "")
9192 ;; For SI, we special-case integers that can't be loaded in one insn. We
9193 ;; do the load 16-bits at a time. We could do this by loading from memory,
9194 ;; and this is even supposed to be faster, but it is simpler not to get
9195 ;; integers in the TOC.
9196 (define_insn "movsi_low"
9197 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9198 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9199 (match_operand 2 "" ""))))]
9200 "TARGET_MACHO && ! TARGET_64BIT"
9201 "{l|lwz} %0,lo16(%2)(%1)"
9202 [(set_attr "type" "load")
9203 (set_attr "length" "4")])
9205 (define_insn "*movsi_internal1"
9206 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
9207 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
9208 "!TARGET_SINGLE_FPU &&
9209 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
9210 "@
9211 mr %0,%1
9212 {cal|la} %0,%a1
9213 {l%U1%X1|lwz%U1%X1} %0,%1
9214 {st%U0%X0|stw%U0%X0} %1,%0
9215 {lil|li} %0,%1
9216 {liu|lis} %0,%v1
9217 #
9218 {cal|la} %0,%a1
9219 mf%1 %0
9220 mt%0 %1
9221 mt%0 %1
9222 mt%0 %1
9223 {cror 0,0,0|nop}"
9224 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
9225 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
9227 (define_insn "*movsi_internal1_single"
9228 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
9229 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
9230 "TARGET_SINGLE_FPU &&
9231 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
9232 "@
9233 mr %0,%1
9234 {cal|la} %0,%a1
9235 {l%U1%X1|lwz%U1%X1} %0,%1
9236 {st%U0%X0|stw%U0%X0} %1,%0
9237 {lil|li} %0,%1
9238 {liu|lis} %0,%v1
9239 #
9240 {cal|la} %0,%a1
9241 mf%1 %0
9242 mt%0 %1
9243 mt%0 %1
9244 mt%0 %1
9245 {cror 0,0,0|nop}
9246 stfs%U0%X0 %1, %0
9247 lfs%U1%X1 %0, %1"
9248 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
9249 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
9251 ;; Split a load of a large constant into the appropriate two-insn
9252 ;; sequence.
9254 (define_split
9255 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9256 (match_operand:SI 1 "const_int_operand" ""))]
9257 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
9258 && (INTVAL (operands[1]) & 0xffff) != 0"
9259 [(set (match_dup 0)
9260 (match_dup 2))
9261 (set (match_dup 0)
9262 (ior:SI (match_dup 0)
9263 (match_dup 3)))]
9264 "
9265 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
9267 if (tem == operands[0])
9268 DONE;
9269 else
9270 FAIL;
9271 }")
9273 (define_insn "*mov<mode>_internal2"
9274 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
9275 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
9276 (const_int 0)))
9277 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
9278 ""
9279 "@
9280 {cmpi|cmp<wd>i} %2,%0,0
9281 mr. %0,%1
9282 #"
9283 [(set_attr "type" "cmp,compare,cmp")
9284 (set_attr "length" "4,4,8")])
9286 (define_split
9287 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9288 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9289 (const_int 0)))
9290 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
9291 "reload_completed"
9292 [(set (match_dup 0) (match_dup 1))
9293 (set (match_dup 2)
9294 (compare:CC (match_dup 0)
9295 (const_int 0)))]
9296 "")
9297 \f
9298 (define_insn "*movhi_internal"
9299 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
9300 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
9301 "gpc_reg_operand (operands[0], HImode)
9302 || gpc_reg_operand (operands[1], HImode)"
9303 "@
9304 mr %0,%1
9305 lhz%U1%X1 %0,%1
9306 sth%U0%X0 %1,%0
9307 {lil|li} %0,%w1
9308 mf%1 %0
9309 mt%0 %1
9310 mt%0 %1
9311 {cror 0,0,0|nop}"
9312 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
9314 (define_expand "mov<mode>"
9315 [(set (match_operand:INT 0 "general_operand" "")
9316 (match_operand:INT 1 "any_operand" ""))]
9317 ""
9318 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9320 (define_insn "*movqi_internal"
9321 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
9322 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
9323 "gpc_reg_operand (operands[0], QImode)
9324 || gpc_reg_operand (operands[1], QImode)"
9325 "@
9326 mr %0,%1
9327 lbz%U1%X1 %0,%1
9328 stb%U0%X0 %1,%0
9329 {lil|li} %0,%1
9330 mf%1 %0
9331 mt%0 %1
9332 mt%0 %1
9333 {cror 0,0,0|nop}"
9334 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
9335 \f
9336 ;; Here is how to move condition codes around. When we store CC data in
9337 ;; an integer register or memory, we store just the high-order 4 bits.
9338 ;; This lets us not shift in the most common case of CR0.
9339 (define_expand "movcc"
9340 [(set (match_operand:CC 0 "nonimmediate_operand" "")
9341 (match_operand:CC 1 "nonimmediate_operand" ""))]
9342 ""
9343 "")
9345 (define_insn "*movcc_internal1"
9346 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
9347 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
9348 "register_operand (operands[0], CCmode)
9349 || register_operand (operands[1], CCmode)"
9350 "@
9351 mcrf %0,%1
9352 mtcrf 128,%1
9353 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
9354 crxor %0,%0,%0
9355 mfcr %0%Q1
9356 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
9357 mr %0,%1
9358 {lil|li} %0,%1
9359 mf%1 %0
9360 mt%0 %1
9361 mt%0 %1
9362 {l%U1%X1|lwz%U1%X1} %0,%1
9363 {st%U0%U1|stw%U0%U1} %1,%0"
9364 [(set (attr "type")
9365 (cond [(eq_attr "alternative" "0,3")
9366 (const_string "cr_logical")
9367 (eq_attr "alternative" "1,2")
9368 (const_string "mtcr")
9369 (eq_attr "alternative" "6,7,9")
9370 (const_string "integer")
9371 (eq_attr "alternative" "8")
9372 (const_string "mfjmpr")
9373 (eq_attr "alternative" "10")
9374 (const_string "mtjmpr")
9375 (eq_attr "alternative" "11")
9376 (const_string "load")
9377 (eq_attr "alternative" "12")
9378 (const_string "store")
9379 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
9380 (const_string "mfcrf")
9381 ]
9382 (const_string "mfcr")))
9383 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
9384 \f
9385 ;; For floating-point, we normally deal with the floating-point registers
9386 ;; unless -msoft-float is used. The sole exception is that parameter passing
9387 ;; can produce floating-point values in fixed-point registers. Unless the
9388 ;; value is a simple constant or already in memory, we deal with this by
9389 ;; allocating memory and copying the value explicitly via that memory location.
9390 (define_expand "movsf"
9391 [(set (match_operand:SF 0 "nonimmediate_operand" "")
9392 (match_operand:SF 1 "any_operand" ""))]
9393 ""
9394 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
9396 (define_split
9397 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9398 (match_operand:SF 1 "const_double_operand" ""))]
9399 "reload_completed
9400 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9401 || (GET_CODE (operands[0]) == SUBREG
9402 && GET_CODE (SUBREG_REG (operands[0])) == REG
9403 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9404 [(set (match_dup 2) (match_dup 3))]
9405 "
9406 {
9407 long l;
9408 REAL_VALUE_TYPE rv;
9410 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9411 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
9413 if (! TARGET_POWERPC64)
9414 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
9415 else
9416 operands[2] = gen_lowpart (SImode, operands[0]);
9418 operands[3] = gen_int_mode (l, SImode);
9419 }")
9421 (define_insn "*movsf_hardfloat"
9422 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
9423 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
9424 "(gpc_reg_operand (operands[0], SFmode)
9425 || gpc_reg_operand (operands[1], SFmode))
9426 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9427 "@
9428 mr %0,%1
9429 {l%U1%X1|lwz%U1%X1} %0,%1
9430 {st%U0%X0|stw%U0%X0} %1,%0
9431 fmr %0,%1
9432 lfs%U1%X1 %0,%1
9433 stfs%U0%X0 %1,%0
9434 mt%0 %1
9435 mt%0 %1
9436 mf%1 %0
9437 {cror 0,0,0|nop}
9438 #
9439 #"
9440 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
9441 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
9443 (define_insn "*movsf_softfloat"
9444 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
9445 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
9446 "(gpc_reg_operand (operands[0], SFmode)
9447 || gpc_reg_operand (operands[1], SFmode))
9448 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9449 "@
9450 mr %0,%1
9451 mt%0 %1
9452 mt%0 %1
9453 mf%1 %0
9454 {l%U1%X1|lwz%U1%X1} %0,%1
9455 {st%U0%X0|stw%U0%X0} %1,%0
9456 {lil|li} %0,%1
9457 {liu|lis} %0,%v1
9458 {cal|la} %0,%a1
9459 #
9460 #
9461 {cror 0,0,0|nop}"
9462 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
9463 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
9465 \f
9466 (define_expand "movdf"
9467 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9468 (match_operand:DF 1 "any_operand" ""))]
9469 ""
9470 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
9472 (define_split
9473 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9474 (match_operand:DF 1 "const_int_operand" ""))]
9475 "! TARGET_POWERPC64 && reload_completed
9476 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9477 || (GET_CODE (operands[0]) == SUBREG
9478 && GET_CODE (SUBREG_REG (operands[0])) == REG
9479 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9480 [(set (match_dup 2) (match_dup 4))
9481 (set (match_dup 3) (match_dup 1))]
9482 "
9483 {
9484 int endian = (WORDS_BIG_ENDIAN == 0);
9485 HOST_WIDE_INT value = INTVAL (operands[1]);
9487 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9488 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9489 #if HOST_BITS_PER_WIDE_INT == 32
9490 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9491 #else
9492 operands[4] = GEN_INT (value >> 32);
9493 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9494 #endif
9495 }")
9497 (define_split
9498 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9499 (match_operand:DF 1 "const_double_operand" ""))]
9500 "! TARGET_POWERPC64 && reload_completed
9501 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9502 || (GET_CODE (operands[0]) == SUBREG
9503 && GET_CODE (SUBREG_REG (operands[0])) == REG
9504 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9505 [(set (match_dup 2) (match_dup 4))
9506 (set (match_dup 3) (match_dup 5))]
9507 "
9508 {
9509 int endian = (WORDS_BIG_ENDIAN == 0);
9510 long l[2];
9511 REAL_VALUE_TYPE rv;
9513 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9514 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9516 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9517 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9518 operands[4] = gen_int_mode (l[endian], SImode);
9519 operands[5] = gen_int_mode (l[1 - endian], SImode);
9520 }")
9522 (define_split
9523 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9524 (match_operand:DF 1 "const_double_operand" ""))]
9525 "TARGET_POWERPC64 && reload_completed
9526 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9527 || (GET_CODE (operands[0]) == SUBREG
9528 && GET_CODE (SUBREG_REG (operands[0])) == REG
9529 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9530 [(set (match_dup 2) (match_dup 3))]
9531 "
9532 {
9533 int endian = (WORDS_BIG_ENDIAN == 0);
9534 long l[2];
9535 REAL_VALUE_TYPE rv;
9536 #if HOST_BITS_PER_WIDE_INT >= 64
9537 HOST_WIDE_INT val;
9538 #endif
9540 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9541 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9543 operands[2] = gen_lowpart (DImode, operands[0]);
9544 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9545 #if HOST_BITS_PER_WIDE_INT >= 64
9546 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9547 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9549 operands[3] = gen_int_mode (val, DImode);
9550 #else
9551 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
9552 #endif
9553 }")
9555 ;; Don't have reload use general registers to load a constant. First,
9556 ;; it might not work if the output operand is the equivalent of
9557 ;; a non-offsettable memref, but also it is less efficient than loading
9558 ;; the constant into an FP register, since it will probably be used there.
9559 ;; The "??" is a kludge until we can figure out a more reasonable way
9560 ;; of handling these non-offsettable values.
9561 (define_insn "*movdf_hardfloat32"
9562 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
9563 (match_operand:DF 1 "input_operand" "r,m,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
9564 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9565 && (gpc_reg_operand (operands[0], DFmode)
9566 || gpc_reg_operand (operands[1], DFmode))"
9567 "*
9568 {
9569 switch (which_alternative)
9570 {
9571 default:
9572 gcc_unreachable ();
9573 case 0:
9574 case 1:
9575 case 2:
9576 return \"#\";
9577 case 3:
9578 case 4:
9579 return \"xxlor %x0,%x1,%x1\";
9580 case 5:
9581 case 6:
9582 return \"lxsd%U1x %x0,%y1\";
9583 case 7:
9584 case 8:
9585 return \"stxsd%U0x %x1,%y0\";
9586 case 9:
9587 return \"fmr %0,%1\";
9588 case 10:
9589 return \"lfd%U1%X1 %0,%1\";
9590 case 11:
9591 return \"stfd%U0%X0 %1,%0\";
9592 case 12:
9593 return \"xxlxor %x0,%x0,%x0\";
9594 case 13:
9595 case 14:
9596 case 15:
9597 return \"#\";
9598 }
9599 }"
9600 [(set_attr "type" "two,load,store,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
9601 (set_attr "length" "8,16,16,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9603 (define_insn "*movdf_softfloat32"
9604 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
9605 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
9606 "! TARGET_POWERPC64
9607 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9608 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9609 && (gpc_reg_operand (operands[0], DFmode)
9610 || gpc_reg_operand (operands[1], DFmode))"
9611 "#"
9612 [(set_attr "type" "two,load,store,*,*,*")
9613 (set_attr "length" "8,8,8,8,12,16")])
9615 ; ld/std require word-aligned displacements -> 'Y' constraint.
9616 ; List Y->r and r->Y before r->r for reload.
9617 (define_insn "*movdf_hardfloat64_mfpgpr"
9618 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r,r,d")
9619 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
9620 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9621 && TARGET_DOUBLE_FLOAT
9622 && (gpc_reg_operand (operands[0], DFmode)
9623 || gpc_reg_operand (operands[1], DFmode))"
9624 "@
9625 std%U0%X0 %1,%0
9626 ld%U1%X1 %0,%1
9627 mr %0,%1
9628 xxlor %x0,%x1,%x1
9629 xxlor %x0,%x1,%x1
9630 lxsd%U1x %x0,%y1
9631 lxsd%U1x %x0,%y1
9632 stxsd%U0x %x1,%y0
9633 stxsd%U0x %x1,%y0
9634 fmr %0,%1
9635 lfd%U1%X1 %0,%1
9636 stfd%U0%X0 %1,%0
9637 xxlxor %x0,%x0,%x0
9638 mt%0 %1
9639 mf%1 %0
9640 {cror 0,0,0|nop}
9641 #
9642 #
9643 #
9644 mftgpr %0,%1
9645 mffgpr %0,%1"
9646 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
9647 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9649 ; ld/std require word-aligned displacements -> 'Y' constraint.
9650 ; List Y->r and r->Y before r->r for reload.
9651 (define_insn "*movdf_hardfloat64"
9652 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r")
9653 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
9654 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9655 && TARGET_DOUBLE_FLOAT
9656 && (gpc_reg_operand (operands[0], DFmode)
9657 || gpc_reg_operand (operands[1], DFmode))"
9658 "@
9659 std%U0%X0 %1,%0
9660 ld%U1%X1 %0,%1
9661 mr %0,%1
9662 xxlor %x0,%x1,%x1
9663 xxlor %x0,%x1,%x1
9664 lxsd%U1x %x0,%y1
9665 lxsd%U1x %x0,%y1
9666 stxsd%U0x %x1,%y0
9667 stxsd%U0x %x1,%y0
9668 fmr %0,%1
9669 lfd%U1%X1 %0,%1
9670 stfd%U0%X0 %1,%0
9671 xxlxor %x0,%x0,%x0
9672 mt%0 %1
9673 mf%1 %0
9674 {cror 0,0,0|nop}
9675 #
9676 #
9677 #"
9678 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
9679 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9681 (define_insn "*movdf_softfloat64"
9682 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
9683 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
9684 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9685 && (gpc_reg_operand (operands[0], DFmode)
9686 || gpc_reg_operand (operands[1], DFmode))"
9687 "@
9688 ld%U1%X1 %0,%1
9689 std%U0%X0 %1,%0
9690 mr %0,%1
9691 mt%0 %1
9692 mf%1 %0
9693 #
9694 #
9695 #
9696 {cror 0,0,0|nop}"
9697 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
9698 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9699 \f
9700 (define_expand "movtf"
9701 [(set (match_operand:TF 0 "general_operand" "")
9702 (match_operand:TF 1 "any_operand" ""))]
9703 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
9704 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
9706 ; It's important to list the o->f and f->o moves before f->f because
9707 ; otherwise reload, given m->f, will try to pick f->f and reload it,
9708 ; which doesn't make progress. Likewise r->Y must be before r->r.
9709 (define_insn_and_split "*movtf_internal"
9710 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
9711 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
9712 "!TARGET_IEEEQUAD
9713 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
9714 && (gpc_reg_operand (operands[0], TFmode)
9715 || gpc_reg_operand (operands[1], TFmode))"
9716 "#"
9717 "&& reload_completed"
9718 [(pc)]
9719 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9720 [(set_attr "length" "8,8,8,20,20,16")])
9722 (define_insn_and_split "*movtf_softfloat"
9723 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
9724 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
9725 "!TARGET_IEEEQUAD
9726 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
9727 && (gpc_reg_operand (operands[0], TFmode)
9728 || gpc_reg_operand (operands[1], TFmode))"
9729 "#"
9730 "&& reload_completed"
9731 [(pc)]
9732 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9733 [(set_attr "length" "20,20,16")])
9735 (define_expand "extenddftf2"
9736 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9737 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9738 "!TARGET_IEEEQUAD
9739 && TARGET_HARD_FLOAT
9740 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9741 && TARGET_LONG_DOUBLE_128"
9742 {
9743 if (TARGET_E500_DOUBLE)
9744 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9745 else
9746 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9747 DONE;
9748 })
9750 (define_expand "extenddftf2_fprs"
9751 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9752 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9753 (use (match_dup 2))])]
9754 "!TARGET_IEEEQUAD
9755 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9756 && TARGET_LONG_DOUBLE_128"
9757 {
9758 operands[2] = CONST0_RTX (DFmode);
9759 /* Generate GOT reference early for SVR4 PIC. */
9760 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9761 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9762 })
9764 (define_insn_and_split "*extenddftf2_internal"
9765 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
9766 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
9767 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
9768 "!TARGET_IEEEQUAD
9769 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9770 && TARGET_LONG_DOUBLE_128"
9771 "#"
9772 "&& reload_completed"
9773 [(pc)]
9774 {
9775 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9776 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9777 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9778 operands[1]);
9779 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9780 operands[2]);
9781 DONE;
9782 })
9784 (define_expand "extendsftf2"
9785 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9786 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9787 "!TARGET_IEEEQUAD
9788 && TARGET_HARD_FLOAT
9789 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9790 && TARGET_LONG_DOUBLE_128"
9791 {
9792 rtx tmp = gen_reg_rtx (DFmode);
9793 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9794 emit_insn (gen_extenddftf2 (operands[0], tmp));
9795 DONE;
9796 })
9798 (define_expand "trunctfdf2"
9799 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9800 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9801 "!TARGET_IEEEQUAD
9802 && TARGET_HARD_FLOAT
9803 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9804 && TARGET_LONG_DOUBLE_128"
9805 "")
9807 (define_insn_and_split "trunctfdf2_internal1"
9808 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9809 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9810 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9811 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9812 "@
9813 #
9814 fmr %0,%1"
9815 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9816 [(const_int 0)]
9817 {
9818 emit_note (NOTE_INSN_DELETED);
9819 DONE;
9820 }
9821 [(set_attr "type" "fp")])
9823 (define_insn "trunctfdf2_internal2"
9824 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9825 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9826 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9827 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9828 && TARGET_LONG_DOUBLE_128"
9829 "fadd %0,%1,%L1"
9830 [(set_attr "type" "fp")
9831 (set_attr "fp_type" "fp_addsub_d")])
9833 (define_expand "trunctfsf2"
9834 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9835 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9836 "!TARGET_IEEEQUAD
9837 && TARGET_HARD_FLOAT
9838 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9839 && TARGET_LONG_DOUBLE_128"
9840 {
9841 if (TARGET_E500_DOUBLE)
9842 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9843 else
9844 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9845 DONE;
9846 })
9848 (define_insn_and_split "trunctfsf2_fprs"
9849 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9850 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9851 (clobber (match_scratch:DF 2 "=d"))]
9852 "!TARGET_IEEEQUAD
9853 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9854 && TARGET_LONG_DOUBLE_128"
9855 "#"
9856 "&& reload_completed"
9857 [(set (match_dup 2)
9858 (float_truncate:DF (match_dup 1)))
9859 (set (match_dup 0)
9860 (float_truncate:SF (match_dup 2)))]
9861 "")
9863 (define_expand "floatsitf2"
9864 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9865 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9866 "!TARGET_IEEEQUAD
9867 && TARGET_HARD_FLOAT
9868 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9869 && TARGET_LONG_DOUBLE_128"
9870 {
9871 rtx tmp = gen_reg_rtx (DFmode);
9872 expand_float (tmp, operands[1], false);
9873 emit_insn (gen_extenddftf2 (operands[0], tmp));
9874 DONE;
9875 })
9877 ; fadd, but rounding towards zero.
9878 ; This is probably not the optimal code sequence.
9879 (define_insn "fix_trunc_helper"
9880 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9881 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9882 UNSPEC_FIX_TRUNC_TF))
9883 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9884 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9885 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9886 [(set_attr "type" "fp")
9887 (set_attr "length" "20")])
9889 (define_expand "fix_trunctfsi2"
9890 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9891 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9892 "!TARGET_IEEEQUAD
9893 && (TARGET_POWER2 || TARGET_POWERPC)
9894 && TARGET_HARD_FLOAT
9895 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9896 && TARGET_LONG_DOUBLE_128"
9897 {
9898 if (TARGET_E500_DOUBLE)
9899 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9900 else
9901 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9902 DONE;
9903 })
9905 (define_expand "fix_trunctfsi2_fprs"
9906 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9907 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9908 (clobber (match_dup 2))
9909 (clobber (match_dup 3))
9910 (clobber (match_dup 4))
9911 (clobber (match_dup 5))])]
9912 "!TARGET_IEEEQUAD
9913 && (TARGET_POWER2 || TARGET_POWERPC)
9914 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9915 {
9916 operands[2] = gen_reg_rtx (DFmode);
9917 operands[3] = gen_reg_rtx (DFmode);
9918 operands[4] = gen_reg_rtx (DImode);
9919 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
9920 })
9922 (define_insn_and_split "*fix_trunctfsi2_internal"
9923 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9924 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9925 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9926 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9927 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9928 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9929 "!TARGET_IEEEQUAD
9930 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9931 "#"
9932 ""
9933 [(pc)]
9934 {
9935 rtx lowword;
9936 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9938 gcc_assert (MEM_P (operands[5]));
9939 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9941 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
9942 emit_move_insn (operands[5], operands[4]);
9943 emit_move_insn (operands[0], lowword);
9944 DONE;
9945 })
9947 (define_expand "negtf2"
9948 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9949 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9950 "!TARGET_IEEEQUAD
9951 && TARGET_HARD_FLOAT
9952 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9953 && TARGET_LONG_DOUBLE_128"
9954 "")
9956 (define_insn "negtf2_internal"
9957 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9958 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9959 "!TARGET_IEEEQUAD
9960 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9961 "*
9962 {
9963 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9964 return \"fneg %L0,%L1\;fneg %0,%1\";
9965 else
9966 return \"fneg %0,%1\;fneg %L0,%L1\";
9967 }"
9968 [(set_attr "type" "fp")
9969 (set_attr "length" "8")])
9971 (define_expand "abstf2"
9972 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9973 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9974 "!TARGET_IEEEQUAD
9975 && TARGET_HARD_FLOAT
9976 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9977 && TARGET_LONG_DOUBLE_128"
9978 "
9979 {
9980 rtx label = gen_label_rtx ();
9981 if (TARGET_E500_DOUBLE)
9982 {
9983 if (flag_finite_math_only && !flag_trapping_math)
9984 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9985 else
9986 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9987 }
9988 else
9989 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9990 emit_label (label);
9991 DONE;
9992 }")
9994 (define_expand "abstf2_internal"
9995 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9996 (match_operand:TF 1 "gpc_reg_operand" ""))
9997 (set (match_dup 3) (match_dup 5))
9998 (set (match_dup 5) (abs:DF (match_dup 5)))
9999 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
10000 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
10001 (label_ref (match_operand 2 "" ""))
10002 (pc)))
10003 (set (match_dup 6) (neg:DF (match_dup 6)))]
10004 "!TARGET_IEEEQUAD
10005 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10006 && TARGET_LONG_DOUBLE_128"
10007 "
10008 {
10009 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
10010 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
10011 operands[3] = gen_reg_rtx (DFmode);
10012 operands[4] = gen_reg_rtx (CCFPmode);
10013 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
10014 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
10015 }")
10016 \f
10017 ;; Next come the multi-word integer load and store and the load and store
10018 ;; multiple insns.
10020 ; List r->r after r->"o<>", otherwise reload will try to reload a
10021 ; non-offsettable address by using r->r which won't make progress.
10022 (define_insn "*movdi_internal32"
10023 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r")
10024 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
10025 "! TARGET_POWERPC64
10026 && (gpc_reg_operand (operands[0], DImode)
10027 || gpc_reg_operand (operands[1], DImode))"
10028 "@
10029 #
10030 #
10031 #
10032 fmr %0,%1
10033 lfd%U1%X1 %0,%1
10034 stfd%U0%X0 %1,%0
10035 #"
10036 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
10038 (define_split
10039 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10040 (match_operand:DI 1 "const_int_operand" ""))]
10041 "! TARGET_POWERPC64 && reload_completed"
10042 [(set (match_dup 2) (match_dup 4))
10043 (set (match_dup 3) (match_dup 1))]
10044 "
10045 {
10046 HOST_WIDE_INT value = INTVAL (operands[1]);
10047 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10048 DImode);
10049 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10050 DImode);
10051 #if HOST_BITS_PER_WIDE_INT == 32
10052 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
10053 #else
10054 operands[4] = GEN_INT (value >> 32);
10055 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
10056 #endif
10057 }")
10059 (define_split
10060 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
10061 (match_operand:DIFD 1 "input_operand" ""))]
10062 "reload_completed && !TARGET_POWERPC64
10063 && gpr_or_gpr_p (operands[0], operands[1])"
10064 [(pc)]
10065 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10067 (define_insn "*movdi_mfpgpr"
10068 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
10069 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
10070 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
10071 && (gpc_reg_operand (operands[0], DImode)
10072 || gpc_reg_operand (operands[1], DImode))"
10073 "@
10074 mr %0,%1
10075 ld%U1%X1 %0,%1
10076 std%U0%X0 %1,%0
10077 li %0,%1
10078 lis %0,%v1
10079 #
10080 {cal|la} %0,%a1
10081 fmr %0,%1
10082 lfd%U1%X1 %0,%1
10083 stfd%U0%X0 %1,%0
10084 mf%1 %0
10085 mt%0 %1
10086 {cror 0,0,0|nop}
10087 mftgpr %0,%1
10088 mffgpr %0,%1"
10089 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
10090 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
10092 (define_insn "*movdi_internal64"
10093 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
10094 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
10095 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
10096 && (gpc_reg_operand (operands[0], DImode)
10097 || gpc_reg_operand (operands[1], DImode))"
10098 "@
10099 mr %0,%1
10100 ld%U1%X1 %0,%1
10101 std%U0%X0 %1,%0
10102 li %0,%1
10103 lis %0,%v1
10104 #
10105 {cal|la} %0,%a1
10106 fmr %0,%1
10107 lfd%U1%X1 %0,%1
10108 stfd%U0%X0 %1,%0
10109 mf%1 %0
10110 mt%0 %1
10111 {cror 0,0,0|nop}"
10112 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
10113 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
10115 ;; immediate value valid for a single instruction hiding in a const_double
10116 (define_insn ""
10117 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10118 (match_operand:DI 1 "const_double_operand" "F"))]
10119 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
10120 && GET_CODE (operands[1]) == CONST_DOUBLE
10121 && num_insns_constant (operands[1], DImode) == 1"
10122 "*
10123 {
10124 return ((unsigned HOST_WIDE_INT)
10125 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
10126 ? \"li %0,%1\" : \"lis %0,%v1\";
10127 }")
10129 ;; Generate all one-bits and clear left or right.
10130 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
10131 (define_split
10132 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10133 (match_operand:DI 1 "mask64_operand" ""))]
10134 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10135 [(set (match_dup 0) (const_int -1))
10136 (set (match_dup 0)
10137 (and:DI (rotate:DI (match_dup 0)
10138 (const_int 0))
10139 (match_dup 1)))]
10140 "")
10142 ;; Split a load of a large constant into the appropriate five-instruction
10143 ;; sequence. Handle anything in a constant number of insns.
10144 ;; When non-easy constants can go in the TOC, this should use
10145 ;; easy_fp_constant predicate.
10146 (define_split
10147 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10148 (match_operand:DI 1 "const_int_operand" ""))]
10149 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10150 [(set (match_dup 0) (match_dup 2))
10151 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10152 "
10153 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10155 if (tem == operands[0])
10156 DONE;
10157 else
10158 FAIL;
10159 }")
10161 (define_split
10162 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10163 (match_operand:DI 1 "const_double_operand" ""))]
10164 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10165 [(set (match_dup 0) (match_dup 2))
10166 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10167 "
10168 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10170 if (tem == operands[0])
10171 DONE;
10172 else
10173 FAIL;
10174 }")
10175 \f
10176 ;; TImode is similar, except that we usually want to compute the address into
10177 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
10178 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
10180 ;; We say that MQ is clobbered in the last alternative because the first
10181 ;; alternative would never get used otherwise since it would need a reload
10182 ;; while the 2nd alternative would not. We put memory cases first so they
10183 ;; are preferred. Otherwise, we'd try to reload the output instead of
10184 ;; giving the SCRATCH mq.
10186 (define_insn "*movti_power"
10187 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
10188 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
10189 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
10190 "TARGET_POWER && ! TARGET_POWERPC64
10191 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
10192 "*
10193 {
10194 switch (which_alternative)
10195 {
10196 default:
10197 gcc_unreachable ();
10199 case 0:
10200 if (TARGET_STRING)
10201 return \"{stsi|stswi} %1,%P0,16\";
10202 case 1:
10203 case 2:
10204 return \"#\";
10205 case 3:
10206 /* If the address is not used in the output, we can use lsi. Otherwise,
10207 fall through to generating four loads. */
10208 if (TARGET_STRING
10209 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10210 return \"{lsi|lswi} %0,%P1,16\";
10211 /* ... fall through ... */
10212 case 4:
10213 case 5:
10214 return \"#\";
10215 }
10216 }"
10217 [(set_attr "type" "store,store,*,load,load,*")])
10219 (define_insn "*movti_string"
10220 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
10221 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
10222 "! TARGET_POWER && ! TARGET_POWERPC64
10223 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
10224 "*
10225 {
10226 switch (which_alternative)
10227 {
10228 default:
10229 gcc_unreachable ();
10230 case 0:
10231 if (TARGET_STRING)
10232 return \"{stsi|stswi} %1,%P0,16\";
10233 case 1:
10234 case 2:
10235 return \"#\";
10236 case 3:
10237 /* If the address is not used in the output, we can use lsi. Otherwise,
10238 fall through to generating four loads. */
10239 if (TARGET_STRING
10240 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10241 return \"{lsi|lswi} %0,%P1,16\";
10242 /* ... fall through ... */
10243 case 4:
10244 case 5:
10245 return \"#\";
10246 }
10247 }"
10248 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
10249 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
10250 (const_string "always")
10251 (const_string "conditional")))])
10253 (define_insn "*movti_ppc64"
10254 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
10255 (match_operand:TI 1 "input_operand" "r,r,m"))]
10256 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
10257 || gpc_reg_operand (operands[1], TImode)))
10258 && VECTOR_MEM_NONE_P (TImode)"
10259 "#"
10260 [(set_attr "type" "*,store,load")])
10262 (define_split
10263 [(set (match_operand:TI 0 "gpc_reg_operand" "")
10264 (match_operand:TI 1 "const_double_operand" ""))]
10265 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
10266 [(set (match_dup 2) (match_dup 4))
10267 (set (match_dup 3) (match_dup 5))]
10268 "
10269 {
10270 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10271 TImode);
10272 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10273 TImode);
10274 if (GET_CODE (operands[1]) == CONST_DOUBLE)
10275 {
10276 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
10277 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
10278 }
10279 else if (GET_CODE (operands[1]) == CONST_INT)
10280 {
10281 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
10282 operands[5] = operands[1];
10283 }
10284 else
10285 FAIL;
10286 }")
10288 (define_split
10289 [(set (match_operand:TI 0 "nonimmediate_operand" "")
10290 (match_operand:TI 1 "input_operand" ""))]
10291 "reload_completed && VECTOR_MEM_NONE_P (TImode)
10292 && gpr_or_gpr_p (operands[0], operands[1])"
10293 [(pc)]
10294 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10295 \f
10296 (define_expand "load_multiple"
10297 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10298 (match_operand:SI 1 "" ""))
10299 (use (match_operand:SI 2 "" ""))])]
10300 "TARGET_STRING && !TARGET_POWERPC64"
10301 "
10302 {
10303 int regno;
10304 int count;
10305 rtx op1;
10306 int i;
10308 /* Support only loading a constant number of fixed-point registers from
10309 memory and only bother with this if more than two; the machine
10310 doesn't support more than eight. */
10311 if (GET_CODE (operands[2]) != CONST_INT
10312 || INTVAL (operands[2]) <= 2
10313 || INTVAL (operands[2]) > 8
10314 || GET_CODE (operands[1]) != MEM
10315 || GET_CODE (operands[0]) != REG
10316 || REGNO (operands[0]) >= 32)
10317 FAIL;
10319 count = INTVAL (operands[2]);
10320 regno = REGNO (operands[0]);
10322 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10323 op1 = replace_equiv_address (operands[1],
10324 force_reg (SImode, XEXP (operands[1], 0)));
10326 for (i = 0; i < count; i++)
10327 XVECEXP (operands[3], 0, i)
10328 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
10329 adjust_address_nv (op1, SImode, i * 4));
10330 }")
10332 (define_insn "*ldmsi8"
10333 [(match_parallel 0 "load_multiple_operation"
10334 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10335 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10336 (set (match_operand:SI 3 "gpc_reg_operand" "")
10337 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10338 (set (match_operand:SI 4 "gpc_reg_operand" "")
10339 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10340 (set (match_operand:SI 5 "gpc_reg_operand" "")
10341 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10342 (set (match_operand:SI 6 "gpc_reg_operand" "")
10343 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10344 (set (match_operand:SI 7 "gpc_reg_operand" "")
10345 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10346 (set (match_operand:SI 8 "gpc_reg_operand" "")
10347 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
10348 (set (match_operand:SI 9 "gpc_reg_operand" "")
10349 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
10350 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10351 "*
10352 { return rs6000_output_load_multiple (operands); }"
10353 [(set_attr "type" "load_ux")
10354 (set_attr "length" "32")])
10356 (define_insn "*ldmsi7"
10357 [(match_parallel 0 "load_multiple_operation"
10358 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10359 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10360 (set (match_operand:SI 3 "gpc_reg_operand" "")
10361 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10362 (set (match_operand:SI 4 "gpc_reg_operand" "")
10363 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10364 (set (match_operand:SI 5 "gpc_reg_operand" "")
10365 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10366 (set (match_operand:SI 6 "gpc_reg_operand" "")
10367 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10368 (set (match_operand:SI 7 "gpc_reg_operand" "")
10369 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10370 (set (match_operand:SI 8 "gpc_reg_operand" "")
10371 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
10372 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10373 "*
10374 { return rs6000_output_load_multiple (operands); }"
10375 [(set_attr "type" "load_ux")
10376 (set_attr "length" "32")])
10378 (define_insn "*ldmsi6"
10379 [(match_parallel 0 "load_multiple_operation"
10380 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10381 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10382 (set (match_operand:SI 3 "gpc_reg_operand" "")
10383 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10384 (set (match_operand:SI 4 "gpc_reg_operand" "")
10385 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10386 (set (match_operand:SI 5 "gpc_reg_operand" "")
10387 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10388 (set (match_operand:SI 6 "gpc_reg_operand" "")
10389 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10390 (set (match_operand:SI 7 "gpc_reg_operand" "")
10391 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
10392 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10393 "*
10394 { return rs6000_output_load_multiple (operands); }"
10395 [(set_attr "type" "load_ux")
10396 (set_attr "length" "32")])
10398 (define_insn "*ldmsi5"
10399 [(match_parallel 0 "load_multiple_operation"
10400 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10401 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10402 (set (match_operand:SI 3 "gpc_reg_operand" "")
10403 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10404 (set (match_operand:SI 4 "gpc_reg_operand" "")
10405 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10406 (set (match_operand:SI 5 "gpc_reg_operand" "")
10407 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10408 (set (match_operand:SI 6 "gpc_reg_operand" "")
10409 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10410 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10411 "*
10412 { return rs6000_output_load_multiple (operands); }"
10413 [(set_attr "type" "load_ux")
10414 (set_attr "length" "32")])
10416 (define_insn "*ldmsi4"
10417 [(match_parallel 0 "load_multiple_operation"
10418 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10419 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10420 (set (match_operand:SI 3 "gpc_reg_operand" "")
10421 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10422 (set (match_operand:SI 4 "gpc_reg_operand" "")
10423 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10424 (set (match_operand:SI 5 "gpc_reg_operand" "")
10425 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10426 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10427 "*
10428 { return rs6000_output_load_multiple (operands); }"
10429 [(set_attr "type" "load_ux")
10430 (set_attr "length" "32")])
10432 (define_insn "*ldmsi3"
10433 [(match_parallel 0 "load_multiple_operation"
10434 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10435 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10436 (set (match_operand:SI 3 "gpc_reg_operand" "")
10437 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10438 (set (match_operand:SI 4 "gpc_reg_operand" "")
10439 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10440 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10441 "*
10442 { return rs6000_output_load_multiple (operands); }"
10443 [(set_attr "type" "load_ux")
10444 (set_attr "length" "32")])
10446 (define_expand "store_multiple"
10447 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10448 (match_operand:SI 1 "" ""))
10449 (clobber (scratch:SI))
10450 (use (match_operand:SI 2 "" ""))])]
10451 "TARGET_STRING && !TARGET_POWERPC64"
10452 "
10453 {
10454 int regno;
10455 int count;
10456 rtx to;
10457 rtx op0;
10458 int i;
10460 /* Support only storing a constant number of fixed-point registers to
10461 memory and only bother with this if more than two; the machine
10462 doesn't support more than eight. */
10463 if (GET_CODE (operands[2]) != CONST_INT
10464 || INTVAL (operands[2]) <= 2
10465 || INTVAL (operands[2]) > 8
10466 || GET_CODE (operands[0]) != MEM
10467 || GET_CODE (operands[1]) != REG
10468 || REGNO (operands[1]) >= 32)
10469 FAIL;
10471 count = INTVAL (operands[2]);
10472 regno = REGNO (operands[1]);
10474 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10475 to = force_reg (SImode, XEXP (operands[0], 0));
10476 op0 = replace_equiv_address (operands[0], to);
10478 XVECEXP (operands[3], 0, 0)
10479 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10480 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10481 gen_rtx_SCRATCH (SImode));
10483 for (i = 1; i < count; i++)
10484 XVECEXP (operands[3], 0, i + 1)
10485 = gen_rtx_SET (VOIDmode,
10486 adjust_address_nv (op0, SImode, i * 4),
10487 gen_rtx_REG (SImode, regno + i));
10488 }")
10490 (define_insn "*stmsi8"
10491 [(match_parallel 0 "store_multiple_operation"
10492 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10493 (match_operand:SI 2 "gpc_reg_operand" "r"))
10494 (clobber (match_scratch:SI 3 "=X"))
10495 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10496 (match_operand:SI 4 "gpc_reg_operand" "r"))
10497 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10498 (match_operand:SI 5 "gpc_reg_operand" "r"))
10499 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10500 (match_operand:SI 6 "gpc_reg_operand" "r"))
10501 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10502 (match_operand:SI 7 "gpc_reg_operand" "r"))
10503 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10504 (match_operand:SI 8 "gpc_reg_operand" "r"))
10505 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10506 (match_operand:SI 9 "gpc_reg_operand" "r"))
10507 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10508 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10509 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10510 "{stsi|stswi} %2,%1,%O0"
10511 [(set_attr "type" "store_ux")
10512 (set_attr "cell_micro" "always")])
10514 (define_insn "*stmsi7"
10515 [(match_parallel 0 "store_multiple_operation"
10516 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10517 (match_operand:SI 2 "gpc_reg_operand" "r"))
10518 (clobber (match_scratch:SI 3 "=X"))
10519 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10520 (match_operand:SI 4 "gpc_reg_operand" "r"))
10521 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10522 (match_operand:SI 5 "gpc_reg_operand" "r"))
10523 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10524 (match_operand:SI 6 "gpc_reg_operand" "r"))
10525 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10526 (match_operand:SI 7 "gpc_reg_operand" "r"))
10527 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10528 (match_operand:SI 8 "gpc_reg_operand" "r"))
10529 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10530 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10531 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10532 "{stsi|stswi} %2,%1,%O0"
10533 [(set_attr "type" "store_ux")
10534 (set_attr "cell_micro" "always")])
10536 (define_insn "*stmsi6"
10537 [(match_parallel 0 "store_multiple_operation"
10538 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10539 (match_operand:SI 2 "gpc_reg_operand" "r"))
10540 (clobber (match_scratch:SI 3 "=X"))
10541 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10542 (match_operand:SI 4 "gpc_reg_operand" "r"))
10543 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10544 (match_operand:SI 5 "gpc_reg_operand" "r"))
10545 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10546 (match_operand:SI 6 "gpc_reg_operand" "r"))
10547 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10548 (match_operand:SI 7 "gpc_reg_operand" "r"))
10549 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10550 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10551 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10552 "{stsi|stswi} %2,%1,%O0"
10553 [(set_attr "type" "store_ux")
10554 (set_attr "cell_micro" "always")])
10556 (define_insn "*stmsi5"
10557 [(match_parallel 0 "store_multiple_operation"
10558 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10559 (match_operand:SI 2 "gpc_reg_operand" "r"))
10560 (clobber (match_scratch:SI 3 "=X"))
10561 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10562 (match_operand:SI 4 "gpc_reg_operand" "r"))
10563 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10564 (match_operand:SI 5 "gpc_reg_operand" "r"))
10565 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10566 (match_operand:SI 6 "gpc_reg_operand" "r"))
10567 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10568 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10569 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10570 "{stsi|stswi} %2,%1,%O0"
10571 [(set_attr "type" "store_ux")
10572 (set_attr "cell_micro" "always")])
10574 (define_insn "*stmsi4"
10575 [(match_parallel 0 "store_multiple_operation"
10576 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10577 (match_operand:SI 2 "gpc_reg_operand" "r"))
10578 (clobber (match_scratch:SI 3 "=X"))
10579 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10580 (match_operand:SI 4 "gpc_reg_operand" "r"))
10581 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10582 (match_operand:SI 5 "gpc_reg_operand" "r"))
10583 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10584 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10585 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10586 "{stsi|stswi} %2,%1,%O0"
10587 [(set_attr "type" "store_ux")
10588 (set_attr "cell_micro" "always")])
10590 (define_insn "*stmsi3"
10591 [(match_parallel 0 "store_multiple_operation"
10592 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10593 (match_operand:SI 2 "gpc_reg_operand" "r"))
10594 (clobber (match_scratch:SI 3 "=X"))
10595 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10596 (match_operand:SI 4 "gpc_reg_operand" "r"))
10597 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10598 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10599 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10600 "{stsi|stswi} %2,%1,%O0"
10601 [(set_attr "type" "store_ux")
10602 (set_attr "cell_micro" "always")])
10604 (define_insn "*stmsi8_power"
10605 [(match_parallel 0 "store_multiple_operation"
10606 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10607 (match_operand:SI 2 "gpc_reg_operand" "r"))
10608 (clobber (match_scratch:SI 3 "=q"))
10609 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10610 (match_operand:SI 4 "gpc_reg_operand" "r"))
10611 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10612 (match_operand:SI 5 "gpc_reg_operand" "r"))
10613 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10614 (match_operand:SI 6 "gpc_reg_operand" "r"))
10615 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10616 (match_operand:SI 7 "gpc_reg_operand" "r"))
10617 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10618 (match_operand:SI 8 "gpc_reg_operand" "r"))
10619 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10620 (match_operand:SI 9 "gpc_reg_operand" "r"))
10621 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10622 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10623 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10624 "{stsi|stswi} %2,%1,%O0"
10625 [(set_attr "type" "store_ux")
10626 (set_attr "cell_micro" "always")])
10628 (define_insn "*stmsi7_power"
10629 [(match_parallel 0 "store_multiple_operation"
10630 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10631 (match_operand:SI 2 "gpc_reg_operand" "r"))
10632 (clobber (match_scratch:SI 3 "=q"))
10633 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10634 (match_operand:SI 4 "gpc_reg_operand" "r"))
10635 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10636 (match_operand:SI 5 "gpc_reg_operand" "r"))
10637 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10638 (match_operand:SI 6 "gpc_reg_operand" "r"))
10639 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10640 (match_operand:SI 7 "gpc_reg_operand" "r"))
10641 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10642 (match_operand:SI 8 "gpc_reg_operand" "r"))
10643 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10644 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10645 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10646 "{stsi|stswi} %2,%1,%O0"
10647 [(set_attr "type" "store_ux")
10648 (set_attr "cell_micro" "always")])
10650 (define_insn "*stmsi6_power"
10651 [(match_parallel 0 "store_multiple_operation"
10652 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10653 (match_operand:SI 2 "gpc_reg_operand" "r"))
10654 (clobber (match_scratch:SI 3 "=q"))
10655 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10656 (match_operand:SI 4 "gpc_reg_operand" "r"))
10657 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10658 (match_operand:SI 5 "gpc_reg_operand" "r"))
10659 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10660 (match_operand:SI 6 "gpc_reg_operand" "r"))
10661 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10662 (match_operand:SI 7 "gpc_reg_operand" "r"))
10663 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10664 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10665 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10666 "{stsi|stswi} %2,%1,%O0"
10667 [(set_attr "type" "store_ux")
10668 (set_attr "cell_micro" "always")])
10670 (define_insn "*stmsi5_power"
10671 [(match_parallel 0 "store_multiple_operation"
10672 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10673 (match_operand:SI 2 "gpc_reg_operand" "r"))
10674 (clobber (match_scratch:SI 3 "=q"))
10675 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10676 (match_operand:SI 4 "gpc_reg_operand" "r"))
10677 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10678 (match_operand:SI 5 "gpc_reg_operand" "r"))
10679 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10680 (match_operand:SI 6 "gpc_reg_operand" "r"))
10681 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10682 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10683 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10684 "{stsi|stswi} %2,%1,%O0"
10685 [(set_attr "type" "store_ux")
10686 (set_attr "cell_micro" "always")])
10688 (define_insn "*stmsi4_power"
10689 [(match_parallel 0 "store_multiple_operation"
10690 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10691 (match_operand:SI 2 "gpc_reg_operand" "r"))
10692 (clobber (match_scratch:SI 3 "=q"))
10693 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10694 (match_operand:SI 4 "gpc_reg_operand" "r"))
10695 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10696 (match_operand:SI 5 "gpc_reg_operand" "r"))
10697 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10698 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10699 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10700 "{stsi|stswi} %2,%1,%O0"
10701 [(set_attr "type" "store_ux")
10702 (set_attr "cell_micro" "always")])
10704 (define_insn "*stmsi3_power"
10705 [(match_parallel 0 "store_multiple_operation"
10706 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10707 (match_operand:SI 2 "gpc_reg_operand" "r"))
10708 (clobber (match_scratch:SI 3 "=q"))
10709 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10710 (match_operand:SI 4 "gpc_reg_operand" "r"))
10711 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10712 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10713 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10714 "{stsi|stswi} %2,%1,%O0"
10715 [(set_attr "type" "store_ux")
10716 (set_attr "cell_micro" "always")])
10717 \f
10718 (define_expand "setmemsi"
10719 [(parallel [(set (match_operand:BLK 0 "" "")
10720 (match_operand 2 "const_int_operand" ""))
10721 (use (match_operand:SI 1 "" ""))
10722 (use (match_operand:SI 3 "" ""))])]
10723 ""
10724 "
10725 {
10726 /* If value to set is not zero, use the library routine. */
10727 if (operands[2] != const0_rtx)
10728 FAIL;
10730 if (expand_block_clear (operands))
10731 DONE;
10732 else
10733 FAIL;
10734 }")
10736 ;; String/block move insn.
10737 ;; Argument 0 is the destination
10738 ;; Argument 1 is the source
10739 ;; Argument 2 is the length
10740 ;; Argument 3 is the alignment
10742 (define_expand "movmemsi"
10743 [(parallel [(set (match_operand:BLK 0 "" "")
10744 (match_operand:BLK 1 "" ""))
10745 (use (match_operand:SI 2 "" ""))
10746 (use (match_operand:SI 3 "" ""))])]
10747 ""
10748 "
10749 {
10750 if (expand_block_move (operands))
10751 DONE;
10752 else
10753 FAIL;
10754 }")
10756 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10757 ;; register allocator doesn't have a clue about allocating 8 word registers.
10758 ;; rD/rS = r5 is preferred, efficient form.
10759 (define_expand "movmemsi_8reg"
10760 [(parallel [(set (match_operand 0 "" "")
10761 (match_operand 1 "" ""))
10762 (use (match_operand 2 "" ""))
10763 (use (match_operand 3 "" ""))
10764 (clobber (reg:SI 5))
10765 (clobber (reg:SI 6))
10766 (clobber (reg:SI 7))
10767 (clobber (reg:SI 8))
10768 (clobber (reg:SI 9))
10769 (clobber (reg:SI 10))
10770 (clobber (reg:SI 11))
10771 (clobber (reg:SI 12))
10772 (clobber (match_scratch:SI 4 ""))])]
10773 "TARGET_STRING"
10774 "")
10776 (define_insn ""
10777 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10778 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10779 (use (match_operand:SI 2 "immediate_operand" "i"))
10780 (use (match_operand:SI 3 "immediate_operand" "i"))
10781 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10782 (clobber (reg:SI 6))
10783 (clobber (reg:SI 7))
10784 (clobber (reg:SI 8))
10785 (clobber (reg:SI 9))
10786 (clobber (reg:SI 10))
10787 (clobber (reg:SI 11))
10788 (clobber (reg:SI 12))
10789 (clobber (match_scratch:SI 5 "=q"))]
10790 "TARGET_STRING && TARGET_POWER
10791 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10792 || INTVAL (operands[2]) == 0)
10793 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10794 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10795 && REGNO (operands[4]) == 5"
10796 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10797 [(set_attr "type" "store_ux")
10798 (set_attr "cell_micro" "always")
10799 (set_attr "length" "8")])
10801 (define_insn ""
10802 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10803 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10804 (use (match_operand:SI 2 "immediate_operand" "i"))
10805 (use (match_operand:SI 3 "immediate_operand" "i"))
10806 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10807 (clobber (reg:SI 6))
10808 (clobber (reg:SI 7))
10809 (clobber (reg:SI 8))
10810 (clobber (reg:SI 9))
10811 (clobber (reg:SI 10))
10812 (clobber (reg:SI 11))
10813 (clobber (reg:SI 12))
10814 (clobber (match_scratch:SI 5 "=X"))]
10815 "TARGET_STRING && ! TARGET_POWER
10816 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10817 || INTVAL (operands[2]) == 0)
10818 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10819 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10820 && REGNO (operands[4]) == 5"
10821 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10822 [(set_attr "type" "store_ux")
10823 (set_attr "cell_micro" "always")
10824 (set_attr "length" "8")])
10826 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10827 ;; register allocator doesn't have a clue about allocating 6 word registers.
10828 ;; rD/rS = r5 is preferred, efficient form.
10829 (define_expand "movmemsi_6reg"
10830 [(parallel [(set (match_operand 0 "" "")
10831 (match_operand 1 "" ""))
10832 (use (match_operand 2 "" ""))
10833 (use (match_operand 3 "" ""))
10834 (clobber (reg:SI 5))
10835 (clobber (reg:SI 6))
10836 (clobber (reg:SI 7))
10837 (clobber (reg:SI 8))
10838 (clobber (reg:SI 9))
10839 (clobber (reg:SI 10))
10840 (clobber (match_scratch:SI 4 ""))])]
10841 "TARGET_STRING"
10842 "")
10844 (define_insn ""
10845 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10846 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10847 (use (match_operand:SI 2 "immediate_operand" "i"))
10848 (use (match_operand:SI 3 "immediate_operand" "i"))
10849 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10850 (clobber (reg:SI 6))
10851 (clobber (reg:SI 7))
10852 (clobber (reg:SI 8))
10853 (clobber (reg:SI 9))
10854 (clobber (reg:SI 10))
10855 (clobber (match_scratch:SI 5 "=q"))]
10856 "TARGET_STRING && TARGET_POWER
10857 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
10858 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10859 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10860 && REGNO (operands[4]) == 5"
10861 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10862 [(set_attr "type" "store_ux")
10863 (set_attr "cell_micro" "always")
10864 (set_attr "length" "8")])
10866 (define_insn ""
10867 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10868 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10869 (use (match_operand:SI 2 "immediate_operand" "i"))
10870 (use (match_operand:SI 3 "immediate_operand" "i"))
10871 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10872 (clobber (reg:SI 6))
10873 (clobber (reg:SI 7))
10874 (clobber (reg:SI 8))
10875 (clobber (reg:SI 9))
10876 (clobber (reg:SI 10))
10877 (clobber (match_scratch:SI 5 "=X"))]
10878 "TARGET_STRING && ! TARGET_POWER
10879 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10880 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10881 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10882 && REGNO (operands[4]) == 5"
10883 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10884 [(set_attr "type" "store_ux")
10885 (set_attr "cell_micro" "always")
10886 (set_attr "length" "8")])
10888 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10889 ;; problems with TImode.
10890 ;; rD/rS = r5 is preferred, efficient form.
10891 (define_expand "movmemsi_4reg"
10892 [(parallel [(set (match_operand 0 "" "")
10893 (match_operand 1 "" ""))
10894 (use (match_operand 2 "" ""))
10895 (use (match_operand 3 "" ""))
10896 (clobber (reg:SI 5))
10897 (clobber (reg:SI 6))
10898 (clobber (reg:SI 7))
10899 (clobber (reg:SI 8))
10900 (clobber (match_scratch:SI 4 ""))])]
10901 "TARGET_STRING"
10902 "")
10904 (define_insn ""
10905 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10906 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10907 (use (match_operand:SI 2 "immediate_operand" "i"))
10908 (use (match_operand:SI 3 "immediate_operand" "i"))
10909 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10910 (clobber (reg:SI 6))
10911 (clobber (reg:SI 7))
10912 (clobber (reg:SI 8))
10913 (clobber (match_scratch:SI 5 "=q"))]
10914 "TARGET_STRING && TARGET_POWER
10915 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10916 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10917 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10918 && REGNO (operands[4]) == 5"
10919 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10920 [(set_attr "type" "store_ux")
10921 (set_attr "cell_micro" "always")
10922 (set_attr "length" "8")])
10924 (define_insn ""
10925 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10926 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10927 (use (match_operand:SI 2 "immediate_operand" "i"))
10928 (use (match_operand:SI 3 "immediate_operand" "i"))
10929 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10930 (clobber (reg:SI 6))
10931 (clobber (reg:SI 7))
10932 (clobber (reg:SI 8))
10933 (clobber (match_scratch:SI 5 "=X"))]
10934 "TARGET_STRING && ! TARGET_POWER
10935 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10936 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10937 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10938 && REGNO (operands[4]) == 5"
10939 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10940 [(set_attr "type" "store_ux")
10941 (set_attr "cell_micro" "always")
10942 (set_attr "length" "8")])
10944 ;; Move up to 8 bytes at a time.
10945 (define_expand "movmemsi_2reg"
10946 [(parallel [(set (match_operand 0 "" "")
10947 (match_operand 1 "" ""))
10948 (use (match_operand 2 "" ""))
10949 (use (match_operand 3 "" ""))
10950 (clobber (match_scratch:DI 4 ""))
10951 (clobber (match_scratch:SI 5 ""))])]
10952 "TARGET_STRING && ! TARGET_POWERPC64"
10953 "")
10955 (define_insn ""
10956 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10957 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10958 (use (match_operand:SI 2 "immediate_operand" "i"))
10959 (use (match_operand:SI 3 "immediate_operand" "i"))
10960 (clobber (match_scratch:DI 4 "=&r"))
10961 (clobber (match_scratch:SI 5 "=q"))]
10962 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
10963 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10964 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10965 [(set_attr "type" "store_ux")
10966 (set_attr "cell_micro" "always")
10967 (set_attr "length" "8")])
10969 (define_insn ""
10970 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10971 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10972 (use (match_operand:SI 2 "immediate_operand" "i"))
10973 (use (match_operand:SI 3 "immediate_operand" "i"))
10974 (clobber (match_scratch:DI 4 "=&r"))
10975 (clobber (match_scratch:SI 5 "=X"))]
10976 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
10977 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10978 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10979 [(set_attr "type" "store_ux")
10980 (set_attr "cell_micro" "always")
10981 (set_attr "length" "8")])
10983 ;; Move up to 4 bytes at a time.
10984 (define_expand "movmemsi_1reg"
10985 [(parallel [(set (match_operand 0 "" "")
10986 (match_operand 1 "" ""))
10987 (use (match_operand 2 "" ""))
10988 (use (match_operand 3 "" ""))
10989 (clobber (match_scratch:SI 4 ""))
10990 (clobber (match_scratch:SI 5 ""))])]
10991 "TARGET_STRING"
10992 "")
10994 (define_insn ""
10995 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10996 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10997 (use (match_operand:SI 2 "immediate_operand" "i"))
10998 (use (match_operand:SI 3 "immediate_operand" "i"))
10999 (clobber (match_scratch:SI 4 "=&r"))
11000 (clobber (match_scratch:SI 5 "=q"))]
11001 "TARGET_STRING && TARGET_POWER
11002 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
11003 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11004 [(set_attr "type" "store_ux")
11005 (set_attr "cell_micro" "always")
11006 (set_attr "length" "8")])
11008 (define_insn ""
11009 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
11010 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
11011 (use (match_operand:SI 2 "immediate_operand" "i"))
11012 (use (match_operand:SI 3 "immediate_operand" "i"))
11013 (clobber (match_scratch:SI 4 "=&r"))
11014 (clobber (match_scratch:SI 5 "=X"))]
11015 "TARGET_STRING && ! TARGET_POWER
11016 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
11017 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11018 [(set_attr "type" "store_ux")
11019 (set_attr "cell_micro" "always")
11020 (set_attr "length" "8")])
11021 \f
11022 ;; Define insns that do load or store with update. Some of these we can
11023 ;; get by using pre-decrement or pre-increment, but the hardware can also
11024 ;; do cases where the increment is not the size of the object.
11025 ;;
11026 ;; In all these cases, we use operands 0 and 1 for the register being
11027 ;; incremented because those are the operands that local-alloc will
11028 ;; tie and these are the pair most likely to be tieable (and the ones
11029 ;; that will benefit the most).
11031 (define_insn "*movdi_update1"
11032 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
11033 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
11034 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
11035 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
11036 (plus:DI (match_dup 1) (match_dup 2)))]
11037 "TARGET_POWERPC64 && TARGET_UPDATE
11038 && (!avoiding_indexed_address_p (DImode)
11039 || !gpc_reg_operand (operands[2], DImode))"
11040 "@
11041 ldux %3,%0,%2
11042 ldu %3,%2(%0)"
11043 [(set_attr "type" "load_ux,load_u")])
11045 (define_insn "movdi_<mode>_update"
11046 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
11047 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
11048 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
11049 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
11050 (plus:P (match_dup 1) (match_dup 2)))]
11051 "TARGET_POWERPC64 && TARGET_UPDATE
11052 && (!avoiding_indexed_address_p (Pmode)
11053 || !gpc_reg_operand (operands[2], Pmode)
11054 || (REG_P (operands[0])
11055 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
11056 "@
11057 stdux %3,%0,%2
11058 stdu %3,%2(%0)"
11059 [(set_attr "type" "store_ux,store_u")])
11061 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
11062 ;; needed for stack allocation, even if the user passes -mno-update.
11063 (define_insn "movdi_<mode>_update_stack"
11064 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
11065 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
11066 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
11067 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
11068 (plus:P (match_dup 1) (match_dup 2)))]
11069 "TARGET_POWERPC64"
11070 "@
11071 stdux %3,%0,%2
11072 stdu %3,%2(%0)"
11073 [(set_attr "type" "store_ux,store_u")])
11075 (define_insn "*movsi_update1"
11076 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11077 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11078 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11079 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11080 (plus:SI (match_dup 1) (match_dup 2)))]
11081 "TARGET_UPDATE
11082 && (!avoiding_indexed_address_p (SImode)
11083 || !gpc_reg_operand (operands[2], SImode))"
11084 "@
11085 {lux|lwzux} %3,%0,%2
11086 {lu|lwzu} %3,%2(%0)"
11087 [(set_attr "type" "load_ux,load_u")])
11089 (define_insn "*movsi_update2"
11090 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
11091 (sign_extend:DI
11092 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
11093 (match_operand:DI 2 "gpc_reg_operand" "r")))))
11094 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
11095 (plus:DI (match_dup 1) (match_dup 2)))]
11096 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
11097 && !avoiding_indexed_address_p (DImode)"
11098 "lwaux %3,%0,%2"
11099 [(set_attr "type" "load_ext_ux")])
11101 (define_insn "movsi_update"
11102 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11103 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11104 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11105 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11106 (plus:SI (match_dup 1) (match_dup 2)))]
11107 "TARGET_UPDATE
11108 && (!avoiding_indexed_address_p (SImode)
11109 || !gpc_reg_operand (operands[2], SImode)
11110 || (REG_P (operands[0])
11111 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
11112 "@
11113 {stux|stwux} %3,%0,%2
11114 {stu|stwu} %3,%2(%0)"
11115 [(set_attr "type" "store_ux,store_u")])
11117 ;; This is an unconditional pattern; needed for stack allocation, even
11118 ;; if the user passes -mno-update.
11119 (define_insn "movsi_update_stack"
11120 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11121 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11122 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11123 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11124 (plus:SI (match_dup 1) (match_dup 2)))]
11125 ""
11126 "@
11127 {stux|stwux} %3,%0,%2
11128 {stu|stwu} %3,%2(%0)"
11129 [(set_attr "type" "store_ux,store_u")])
11131 (define_insn "*movhi_update1"
11132 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
11133 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11134 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11135 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11136 (plus:SI (match_dup 1) (match_dup 2)))]
11137 "TARGET_UPDATE
11138 && (!avoiding_indexed_address_p (SImode)
11139 || !gpc_reg_operand (operands[2], SImode))"
11140 "@
11141 lhzux %3,%0,%2
11142 lhzu %3,%2(%0)"
11143 [(set_attr "type" "load_ux,load_u")])
11145 (define_insn "*movhi_update2"
11146 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11147 (zero_extend:SI
11148 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11149 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11150 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11151 (plus:SI (match_dup 1) (match_dup 2)))]
11152 "TARGET_UPDATE
11153 && (!avoiding_indexed_address_p (SImode)
11154 || !gpc_reg_operand (operands[2], SImode))"
11155 "@
11156 lhzux %3,%0,%2
11157 lhzu %3,%2(%0)"
11158 [(set_attr "type" "load_ux,load_u")])
11160 (define_insn "*movhi_update3"
11161 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11162 (sign_extend:SI
11163 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11164 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11165 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11166 (plus:SI (match_dup 1) (match_dup 2)))]
11167 "TARGET_UPDATE && rs6000_gen_cell_microcode
11168 && (!avoiding_indexed_address_p (SImode)
11169 || !gpc_reg_operand (operands[2], SImode))"
11170 "@
11171 lhaux %3,%0,%2
11172 lhau %3,%2(%0)"
11173 [(set_attr "type" "load_ext_ux,load_ext_u")])
11175 (define_insn "*movhi_update4"
11176 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11177 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11178 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
11179 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11180 (plus:SI (match_dup 1) (match_dup 2)))]
11181 "TARGET_UPDATE
11182 && (!avoiding_indexed_address_p (SImode)
11183 || !gpc_reg_operand (operands[2], SImode))"
11184 "@
11185 sthux %3,%0,%2
11186 sthu %3,%2(%0)"
11187 [(set_attr "type" "store_ux,store_u")])
11189 (define_insn "*movqi_update1"
11190 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
11191 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11192 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11193 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11194 (plus:SI (match_dup 1) (match_dup 2)))]
11195 "TARGET_UPDATE
11196 && (!avoiding_indexed_address_p (SImode)
11197 || !gpc_reg_operand (operands[2], SImode))"
11198 "@
11199 lbzux %3,%0,%2
11200 lbzu %3,%2(%0)"
11201 [(set_attr "type" "load_ux,load_u")])
11203 (define_insn "*movqi_update2"
11204 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11205 (zero_extend:SI
11206 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11207 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11208 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11209 (plus:SI (match_dup 1) (match_dup 2)))]
11210 "TARGET_UPDATE
11211 && (!avoiding_indexed_address_p (SImode)
11212 || !gpc_reg_operand (operands[2], SImode))"
11213 "@
11214 lbzux %3,%0,%2
11215 lbzu %3,%2(%0)"
11216 [(set_attr "type" "load_ux,load_u")])
11218 (define_insn "*movqi_update3"
11219 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11220 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11221 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
11222 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11223 (plus:SI (match_dup 1) (match_dup 2)))]
11224 "TARGET_UPDATE
11225 && (!avoiding_indexed_address_p (SImode)
11226 || !gpc_reg_operand (operands[2], SImode))"
11227 "@
11228 stbux %3,%0,%2
11229 stbu %3,%2(%0)"
11230 [(set_attr "type" "store_ux,store_u")])
11232 (define_insn "*movsf_update1"
11233 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
11234 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11235 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11236 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11237 (plus:SI (match_dup 1) (match_dup 2)))]
11238 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11239 && (!avoiding_indexed_address_p (SImode)
11240 || !gpc_reg_operand (operands[2], SImode))"
11241 "@
11242 lfsux %3,%0,%2
11243 lfsu %3,%2(%0)"
11244 [(set_attr "type" "fpload_ux,fpload_u")])
11246 (define_insn "*movsf_update2"
11247 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11248 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11249 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
11250 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11251 (plus:SI (match_dup 1) (match_dup 2)))]
11252 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11253 && (!avoiding_indexed_address_p (SImode)
11254 || !gpc_reg_operand (operands[2], SImode))"
11255 "@
11256 stfsux %3,%0,%2
11257 stfsu %3,%2(%0)"
11258 [(set_attr "type" "fpstore_ux,fpstore_u")])
11260 (define_insn "*movsf_update3"
11261 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
11262 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11263 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11264 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11265 (plus:SI (match_dup 1) (match_dup 2)))]
11266 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11267 && (!avoiding_indexed_address_p (SImode)
11268 || !gpc_reg_operand (operands[2], SImode))"
11269 "@
11270 {lux|lwzux} %3,%0,%2
11271 {lu|lwzu} %3,%2(%0)"
11272 [(set_attr "type" "load_ux,load_u")])
11274 (define_insn "*movsf_update4"
11275 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11276 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11277 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
11278 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11279 (plus:SI (match_dup 1) (match_dup 2)))]
11280 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11281 && (!avoiding_indexed_address_p (SImode)
11282 || !gpc_reg_operand (operands[2], SImode))"
11283 "@
11284 {stux|stwux} %3,%0,%2
11285 {stu|stwu} %3,%2(%0)"
11286 [(set_attr "type" "store_ux,store_u")])
11288 (define_insn "*movdf_update1"
11289 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
11290 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11291 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11292 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11293 (plus:SI (match_dup 1) (match_dup 2)))]
11294 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11295 && (!avoiding_indexed_address_p (SImode)
11296 || !gpc_reg_operand (operands[2], SImode))"
11297 "@
11298 lfdux %3,%0,%2
11299 lfdu %3,%2(%0)"
11300 [(set_attr "type" "fpload_ux,fpload_u")])
11302 (define_insn "*movdf_update2"
11303 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11304 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11305 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
11306 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11307 (plus:SI (match_dup 1) (match_dup 2)))]
11308 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11309 && (!avoiding_indexed_address_p (SImode)
11310 || !gpc_reg_operand (operands[2], SImode))"
11311 "@
11312 stfdux %3,%0,%2
11313 stfdu %3,%2(%0)"
11314 [(set_attr "type" "fpstore_ux,fpstore_u")])
11316 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
11318 (define_insn "*lfq_power2"
11319 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
11320 (match_operand:V2DF 1 "memory_operand" ""))]
11321 "TARGET_POWER2
11322 && TARGET_HARD_FLOAT && TARGET_FPRS"
11323 "lfq%U1%X1 %0,%1")
11325 (define_peephole2
11326 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11327 (match_operand:DF 1 "memory_operand" ""))
11328 (set (match_operand:DF 2 "gpc_reg_operand" "")
11329 (match_operand:DF 3 "memory_operand" ""))]
11330 "TARGET_POWER2
11331 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11332 && registers_ok_for_quad_peep (operands[0], operands[2])
11333 && mems_ok_for_quad_peep (operands[1], operands[3])"
11334 [(set (match_dup 0)
11335 (match_dup 1))]
11336 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
11337 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
11339 (define_insn "*stfq_power2"
11340 [(set (match_operand:V2DF 0 "memory_operand" "")
11341 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
11342 "TARGET_POWER2
11343 && TARGET_HARD_FLOAT && TARGET_FPRS"
11344 "stfq%U0%X0 %1,%0")
11347 (define_peephole2
11348 [(set (match_operand:DF 0 "memory_operand" "")
11349 (match_operand:DF 1 "gpc_reg_operand" ""))
11350 (set (match_operand:DF 2 "memory_operand" "")
11351 (match_operand:DF 3 "gpc_reg_operand" ""))]
11352 "TARGET_POWER2
11353 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11354 && registers_ok_for_quad_peep (operands[1], operands[3])
11355 && mems_ok_for_quad_peep (operands[0], operands[2])"
11356 [(set (match_dup 0)
11357 (match_dup 1))]
11358 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
11359 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
11361 ;; After inserting conditional returns we can sometimes have
11362 ;; unnecessary register moves. Unfortunately we cannot have a
11363 ;; modeless peephole here, because some single SImode sets have early
11364 ;; clobber outputs. Although those sets expand to multi-ppc-insn
11365 ;; sequences, using get_attr_length here will smash the operands
11366 ;; array. Neither is there an early_cobbler_p predicate.
11367 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
11368 (define_peephole2
11369 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11370 (match_operand:DF 1 "any_operand" ""))
11371 (set (match_operand:DF 2 "gpc_reg_operand" "")
11372 (match_dup 0))]
11373 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
11374 && peep2_reg_dead_p (2, operands[0])"
11375 [(set (match_dup 2) (match_dup 1))])
11377 (define_peephole2
11378 [(set (match_operand:SF 0 "gpc_reg_operand" "")
11379 (match_operand:SF 1 "any_operand" ""))
11380 (set (match_operand:SF 2 "gpc_reg_operand" "")
11381 (match_dup 0))]
11382 "peep2_reg_dead_p (2, operands[0])"
11383 [(set (match_dup 2) (match_dup 1))])
11385 \f
11386 ;; TLS support.
11388 ;; Mode attributes for different ABIs.
11389 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
11390 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
11391 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
11392 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
11394 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
11395 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11396 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11397 (match_operand 4 "" "g")))
11398 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11399 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11400 UNSPEC_TLSGD)
11401 (clobber (reg:SI LR_REGNO))]
11402 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11403 {
11404 if (TARGET_CMODEL != CMODEL_SMALL)
11405 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;bl %z3\;%.";
11406 else
11407 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;%.";
11408 }
11409 "&& TARGET_TLS_MARKERS"
11410 [(set (match_dup 0)
11411 (unspec:TLSmode [(match_dup 1)
11412 (match_dup 2)]
11413 UNSPEC_TLSGD))
11414 (parallel [(set (match_dup 0)
11415 (call (mem:TLSmode (match_dup 3))
11416 (match_dup 4)))
11417 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11418 (clobber (reg:SI LR_REGNO))])]
11419 ""
11420 [(set_attr "type" "two")
11421 (set (attr "length")
11422 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11423 (const_int 16)
11424 (const_int 12)))])
11426 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
11427 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11428 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11429 (match_operand 4 "" "g")))
11430 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11431 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11432 UNSPEC_TLSGD)
11433 (clobber (reg:SI LR_REGNO))]
11434 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11435 {
11436 if (flag_pic)
11437 {
11438 if (TARGET_SECURE_PLT && flag_pic == 2)
11439 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11440 else
11441 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11442 }
11443 else
11444 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11445 }
11446 "&& TARGET_TLS_MARKERS"
11447 [(set (match_dup 0)
11448 (unspec:TLSmode [(match_dup 1)
11449 (match_dup 2)]
11450 UNSPEC_TLSGD))
11451 (parallel [(set (match_dup 0)
11452 (call (mem:TLSmode (match_dup 3))
11453 (match_dup 4)))
11454 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11455 (clobber (reg:SI LR_REGNO))])]
11456 ""
11457 [(set_attr "type" "two")
11458 (set_attr "length" "8")])
11460 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
11461 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11462 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11463 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11464 UNSPEC_TLSGD))]
11465 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11466 "addi %0,%1,%2@got@tlsgd"
11467 "&& TARGET_CMODEL != CMODEL_SMALL"
11468 [(set (match_dup 3)
11469 (plus:TLSmode (match_dup 1)
11470 (high:TLSmode
11471 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD))))
11472 (set (match_dup 0)
11473 (lo_sum:TLSmode (match_dup 3)
11474 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
11475 "
11476 {
11477 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11478 }"
11479 [(set (attr "length")
11480 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11481 (const_int 8)
11482 (const_int 4)))])
11484 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
11485 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11486 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11487 (high:TLSmode
11488 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11489 UNSPEC_TLSGD))))]
11490 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11491 "addis %0,%1,%2@got@tlsgd@ha"
11492 [(set_attr "length" "4")])
11494 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
11495 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11496 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11497 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11498 UNSPEC_TLSGD)))]
11499 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11500 "addi %0,%1,%2@got@tlsgd@l"
11501 [(set_attr "length" "4")])
11503 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11504 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11505 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11506 (match_operand 2 "" "g")))
11507 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11508 UNSPEC_TLSGD)
11509 (clobber (reg:SI LR_REGNO))]
11510 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11511 "bl %z1(%3@tlsgd)\;%."
11512 [(set_attr "type" "branch")
11513 (set_attr "length" "8")])
11515 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11516 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11517 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11518 (match_operand 2 "" "g")))
11519 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11520 UNSPEC_TLSGD)
11521 (clobber (reg:SI LR_REGNO))]
11522 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11523 {
11524 if (flag_pic)
11525 {
11526 if (TARGET_SECURE_PLT && flag_pic == 2)
11527 return "bl %z1+32768(%3@tlsgd)@plt";
11528 return "bl %z1(%3@tlsgd)@plt";
11529 }
11530 return "bl %z1(%3@tlsgd)";
11531 }
11532 [(set_attr "type" "branch")
11533 (set_attr "length" "4")])
11535 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11536 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11537 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11538 (match_operand 3 "" "g")))
11539 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11540 UNSPEC_TLSLD)
11541 (clobber (reg:SI LR_REGNO))]
11542 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11543 {
11544 if (TARGET_CMODEL != CMODEL_SMALL)
11545 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;bl %z2\;%.";
11546 else
11547 return "addi %0,%1,%&@got@tlsld\;bl %z2\;%.";
11548 }
11549 "&& TARGET_TLS_MARKERS"
11550 [(set (match_dup 0)
11551 (unspec:TLSmode [(match_dup 1)]
11552 UNSPEC_TLSLD))
11553 (parallel [(set (match_dup 0)
11554 (call (mem:TLSmode (match_dup 2))
11555 (match_dup 3)))
11556 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11557 (clobber (reg:SI LR_REGNO))])]
11558 ""
11559 [(set_attr "type" "two")
11560 (set (attr "length")
11561 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11562 (const_int 16)
11563 (const_int 12)))])
11565 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11566 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11567 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11568 (match_operand 3 "" "g")))
11569 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11570 UNSPEC_TLSLD)
11571 (clobber (reg:SI LR_REGNO))]
11572 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11573 {
11574 if (flag_pic)
11575 {
11576 if (TARGET_SECURE_PLT && flag_pic == 2)
11577 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11578 else
11579 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11580 }
11581 else
11582 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11583 }
11584 "&& TARGET_TLS_MARKERS"
11585 [(set (match_dup 0)
11586 (unspec:TLSmode [(match_dup 1)]
11587 UNSPEC_TLSLD))
11588 (parallel [(set (match_dup 0)
11589 (call (mem:TLSmode (match_dup 2))
11590 (match_dup 3)))
11591 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11592 (clobber (reg:SI LR_REGNO))])]
11593 ""
11594 [(set_attr "length" "8")])
11596 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
11597 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11598 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11599 UNSPEC_TLSLD))]
11600 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11601 "addi %0,%1,%&@got@tlsld"
11602 "&& TARGET_CMODEL != CMODEL_SMALL"
11603 [(set (match_dup 2)
11604 (plus:TLSmode (match_dup 1)
11605 (high:TLSmode
11606 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD))))
11607 (set (match_dup 0)
11608 (lo_sum:TLSmode (match_dup 2)
11609 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11610 "
11611 {
11612 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11613 }"
11614 [(set (attr "length")
11615 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11616 (const_int 8)
11617 (const_int 4)))])
11619 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
11620 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11621 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11622 (high:TLSmode
11623 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD))))]
11624 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11625 "addis %0,%1,%&@got@tlsld@ha"
11626 [(set_attr "length" "4")])
11628 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
11629 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11630 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11631 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11632 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11633 "addi %0,%1,%&@got@tlsld@l"
11634 [(set_attr "length" "4")])
11636 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11637 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11638 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11639 (match_operand 2 "" "g")))
11640 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11641 (clobber (reg:SI LR_REGNO))]
11642 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11643 "bl %z1(%&@tlsld)\;%."
11644 [(set_attr "type" "branch")
11645 (set_attr "length" "8")])
11647 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11648 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11649 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11650 (match_operand 2 "" "g")))
11651 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11652 (clobber (reg:SI LR_REGNO))]
11653 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11654 {
11655 if (flag_pic)
11656 {
11657 if (TARGET_SECURE_PLT && flag_pic == 2)
11658 return "bl %z1+32768(%&@tlsld)@plt";
11659 return "bl %z1(%&@tlsld)@plt";
11660 }
11661 return "bl %z1(%&@tlsld)";
11662 }
11663 [(set_attr "type" "branch")
11664 (set_attr "length" "4")])
11666 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11667 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11668 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11669 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11670 UNSPEC_TLSDTPREL))]
11671 "HAVE_AS_TLS"
11672 "addi %0,%1,%2@dtprel")
11674 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11675 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11676 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11677 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11678 UNSPEC_TLSDTPRELHA))]
11679 "HAVE_AS_TLS"
11680 "addis %0,%1,%2@dtprel@ha")
11682 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11683 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11684 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11685 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11686 UNSPEC_TLSDTPRELLO))]
11687 "HAVE_AS_TLS"
11688 "addi %0,%1,%2@dtprel@l")
11690 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11691 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11692 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11693 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11694 UNSPEC_TLSGOTDTPREL))]
11695 "HAVE_AS_TLS"
11696 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
11697 "&& TARGET_CMODEL != CMODEL_SMALL"
11698 [(set (match_dup 3)
11699 (plus:TLSmode (match_dup 1)
11700 (high:TLSmode
11701 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL))))
11702 (set (match_dup 0)
11703 (lo_sum:TLSmode (match_dup 3)
11704 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
11705 "
11706 {
11707 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11708 }"
11709 [(set (attr "length")
11710 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11711 (const_int 8)
11712 (const_int 4)))])
11714 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
11715 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11716 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11717 (high:TLSmode
11718 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11719 UNSPEC_TLSGOTDTPREL))))]
11720 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11721 "addis %0,%1,%2@got@dtprel@ha"
11722 [(set_attr "length" "4")])
11724 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
11725 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11726 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11727 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11728 UNSPEC_TLSGOTDTPREL)))]
11729 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11730 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
11731 [(set_attr "length" "4")])
11733 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11734 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11735 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11736 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11737 UNSPEC_TLSTPREL))]
11738 "HAVE_AS_TLS"
11739 "addi %0,%1,%2@tprel")
11741 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11742 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11743 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11744 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11745 UNSPEC_TLSTPRELHA))]
11746 "HAVE_AS_TLS"
11747 "addis %0,%1,%2@tprel@ha")
11749 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11750 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11751 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11752 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11753 UNSPEC_TLSTPRELLO))]
11754 "HAVE_AS_TLS"
11755 "addi %0,%1,%2@tprel@l")
11757 ;; "b" output constraint here and on tls_tls input to support linker tls
11758 ;; optimization. The linker may edit the instructions emitted by a
11759 ;; tls_got_tprel/tls_tls pair to addis,addi.
11760 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11761 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11762 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11763 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11764 UNSPEC_TLSGOTTPREL))]
11765 "HAVE_AS_TLS"
11766 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
11767 "&& TARGET_CMODEL != CMODEL_SMALL"
11768 [(set (match_dup 3)
11769 (plus:TLSmode (match_dup 1)
11770 (high:TLSmode
11771 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL))))
11772 (set (match_dup 0)
11773 (lo_sum:TLSmode (match_dup 3)
11774 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
11775 "
11776 {
11777 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11778 }"
11779 [(set (attr "length")
11780 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11781 (const_int 8)
11782 (const_int 4)))])
11784 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
11785 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11786 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11787 (high:TLSmode
11788 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11789 UNSPEC_TLSGOTTPREL))))]
11790 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11791 "addis %0,%1,%2@got@tprel@ha"
11792 [(set_attr "length" "4")])
11794 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
11795 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11796 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11797 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11798 UNSPEC_TLSGOTTPREL)))]
11799 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11800 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
11801 [(set_attr "length" "4")])
11803 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11804 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11805 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11806 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11807 UNSPEC_TLSTLS))]
11808 "HAVE_AS_TLS"
11809 "add %0,%1,%2@tls")
11810 \f
11811 ;; Next come insns related to the calling sequence.
11812 ;;
11813 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11814 ;; We move the back-chain and decrement the stack pointer.
11816 (define_expand "allocate_stack"
11817 [(set (match_operand 0 "gpc_reg_operand" "")
11818 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11819 (set (reg 1)
11820 (minus (reg 1) (match_dup 1)))]
11821 ""
11822 "
11823 { rtx chain = gen_reg_rtx (Pmode);
11824 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11825 rtx neg_op0;
11826 rtx insn, par, set, mem;
11828 emit_move_insn (chain, stack_bot);
11830 /* Check stack bounds if necessary. */
11831 if (crtl->limit_stack)
11832 {
11833 rtx available;
11834 available = expand_binop (Pmode, sub_optab,
11835 stack_pointer_rtx, stack_limit_rtx,
11836 NULL_RTX, 1, OPTAB_WIDEN);
11837 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11838 }
11840 if (GET_CODE (operands[1]) != CONST_INT
11841 || INTVAL (operands[1]) < -32767
11842 || INTVAL (operands[1]) > 32768)
11843 {
11844 neg_op0 = gen_reg_rtx (Pmode);
11845 if (TARGET_32BIT)
11846 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11847 else
11848 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11849 }
11850 else
11851 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11853 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11854 : gen_movdi_di_update_stack))
11855 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11856 chain));
11857 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11858 it now and set the alias set/attributes. The above gen_*_update
11859 calls will generate a PARALLEL with the MEM set being the first
11860 operation. */
11861 par = PATTERN (insn);
11862 gcc_assert (GET_CODE (par) == PARALLEL);
11863 set = XVECEXP (par, 0, 0);
11864 gcc_assert (GET_CODE (set) == SET);
11865 mem = SET_DEST (set);
11866 gcc_assert (MEM_P (mem));
11867 MEM_NOTRAP_P (mem) = 1;
11868 set_mem_alias_set (mem, get_frame_alias_set ());
11870 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11871 DONE;
11872 }")
11874 ;; These patterns say how to save and restore the stack pointer. We need not
11875 ;; save the stack pointer at function level since we are careful to
11876 ;; preserve the backchain. At block level, we have to restore the backchain
11877 ;; when we restore the stack pointer.
11878 ;;
11879 ;; For nonlocal gotos, we must save both the stack pointer and its
11880 ;; backchain and restore both. Note that in the nonlocal case, the
11881 ;; save area is a memory location.
11883 (define_expand "save_stack_function"
11884 [(match_operand 0 "any_operand" "")
11885 (match_operand 1 "any_operand" "")]
11886 ""
11887 "DONE;")
11889 (define_expand "restore_stack_function"
11890 [(match_operand 0 "any_operand" "")
11891 (match_operand 1 "any_operand" "")]
11892 ""
11893 "DONE;")
11895 ;; Adjust stack pointer (op0) to a new value (op1).
11896 ;; First copy old stack backchain to new location, and ensure that the
11897 ;; scheduler won't reorder the sp assignment before the backchain write.
11898 (define_expand "restore_stack_block"
11899 [(set (match_dup 2) (match_dup 3))
11900 (set (match_dup 4) (match_dup 2))
11901 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
11902 (set (match_operand 0 "register_operand" "")
11903 (match_operand 1 "register_operand" ""))]
11904 ""
11905 "
11906 {
11907 operands[1] = force_reg (Pmode, operands[1]);
11908 operands[2] = gen_reg_rtx (Pmode);
11909 operands[3] = gen_frame_mem (Pmode, operands[0]);
11910 operands[4] = gen_frame_mem (Pmode, operands[1]);
11911 operands[5] = gen_frame_mem (BLKmode, operands[0]);
11912 }")
11914 (define_expand "save_stack_nonlocal"
11915 [(set (match_dup 3) (match_dup 4))
11916 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11917 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11918 ""
11919 "
11920 {
11921 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11923 /* Copy the backchain to the first word, sp to the second. */
11924 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11925 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11926 operands[3] = gen_reg_rtx (Pmode);
11927 operands[4] = gen_frame_mem (Pmode, operands[1]);
11928 }")
11930 (define_expand "restore_stack_nonlocal"
11931 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11932 (set (match_dup 3) (match_dup 4))
11933 (set (match_dup 5) (match_dup 2))
11934 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
11935 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11936 ""
11937 "
11938 {
11939 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11941 /* Restore the backchain from the first word, sp from the second. */
11942 operands[2] = gen_reg_rtx (Pmode);
11943 operands[3] = gen_reg_rtx (Pmode);
11944 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11945 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11946 operands[5] = gen_frame_mem (Pmode, operands[3]);
11947 operands[6] = gen_frame_mem (BLKmode, operands[0]);
11948 }")
11949 \f
11950 ;; TOC register handling.
11952 ;; Code to initialize the TOC register...
11954 (define_insn "load_toc_aix_si"
11955 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11956 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11957 (use (reg:SI 2))])]
11958 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11959 "*
11960 {
11961 char buf[30];
11962 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11963 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11964 operands[2] = gen_rtx_REG (Pmode, 2);
11965 return \"{l|lwz} %0,%1(%2)\";
11966 }"
11967 [(set_attr "type" "load")])
11969 (define_insn "load_toc_aix_di"
11970 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11971 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11972 (use (reg:DI 2))])]
11973 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
11974 "*
11975 {
11976 char buf[30];
11977 #ifdef TARGET_RELOCATABLE
11978 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11979 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11980 #else
11981 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11982 #endif
11983 if (TARGET_ELF)
11984 strcat (buf, \"@toc\");
11985 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11986 operands[2] = gen_rtx_REG (Pmode, 2);
11987 return \"ld %0,%1(%2)\";
11988 }"
11989 [(set_attr "type" "load")])
11991 (define_insn "load_toc_v4_pic_si"
11992 [(set (reg:SI LR_REGNO)
11993 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11994 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11995 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11996 [(set_attr "type" "branch")
11997 (set_attr "length" "4")])
11999 (define_insn "load_toc_v4_PIC_1"
12000 [(set (reg:SI LR_REGNO)
12001 (match_operand:SI 0 "immediate_operand" "s"))
12002 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
12003 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
12004 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
12005 "bcl 20,31,%0\\n%0:"
12006 [(set_attr "type" "branch")
12007 (set_attr "length" "4")])
12009 (define_insn "load_toc_v4_PIC_1b"
12010 [(set (reg:SI LR_REGNO)
12011 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
12012 (label_ref (match_operand 1 "" ""))]
12013 UNSPEC_TOCPTR))
12014 (match_dup 1)]
12015 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12016 "bcl 20,31,$+8\;.long %0-$"
12017 [(set_attr "type" "branch")
12018 (set_attr "length" "8")])
12020 (define_insn "load_toc_v4_PIC_2"
12021 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12022 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12023 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
12024 (match_operand:SI 3 "immediate_operand" "s")))))]
12025 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12026 "{l|lwz} %0,%2-%3(%1)"
12027 [(set_attr "type" "load")])
12029 (define_insn "load_toc_v4_PIC_3b"
12030 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
12031 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12032 (high:SI
12033 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
12034 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
12035 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
12036 "{cau|addis} %0,%1,%2-%3@ha")
12038 (define_insn "load_toc_v4_PIC_3c"
12039 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12040 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12041 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
12042 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
12043 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
12044 "{cal %0,%2-%3@l(%1)|addi %0,%1,%2-%3@l}")
12046 ;; If the TOC is shared over a translation unit, as happens with all
12047 ;; the kinds of PIC that we support, we need to restore the TOC
12048 ;; pointer only when jumping over units of translation.
12049 ;; On Darwin, we need to reload the picbase.
12051 (define_expand "builtin_setjmp_receiver"
12052 [(use (label_ref (match_operand 0 "" "")))]
12053 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12054 || (TARGET_TOC && TARGET_MINIMAL_TOC)
12055 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
12056 "
12057 {
12058 #if TARGET_MACHO
12059 if (DEFAULT_ABI == ABI_DARWIN)
12060 {
12061 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
12062 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
12063 rtx tmplabrtx;
12064 char tmplab[20];
12066 crtl->uses_pic_offset_table = 1;
12067 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
12068 CODE_LABEL_NUMBER (operands[0]));
12069 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
12071 emit_insn (gen_load_macho_picbase (tmplabrtx));
12072 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
12073 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
12074 }
12075 else
12076 #endif
12077 rs6000_emit_load_toc_table (FALSE);
12078 DONE;
12079 }")
12081 ;; Elf specific ways of loading addresses for non-PIC code.
12082 ;; The output of this could be r0, but we make a very strong
12083 ;; preference for a base register because it will usually
12084 ;; be needed there.
12085 (define_insn "elf_high"
12086 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
12087 (high:SI (match_operand 1 "" "")))]
12088 "TARGET_ELF && ! TARGET_64BIT"
12089 "{liu|lis} %0,%1@ha")
12091 (define_insn "elf_low"
12092 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12093 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
12094 (match_operand 2 "" "")))]
12095 "TARGET_ELF && ! TARGET_64BIT"
12096 "@
12097 {cal|la} %0,%2@l(%1)
12098 {ai|addic} %0,%1,%K2")
12100 ;; Largetoc support
12101 (define_insn "largetoc_high"
12102 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
12103 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
12104 (high:DI (match_operand:DI 2 "" ""))))]
12105 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12106 "{cau|addis} %0,%1,%2@ha")
12108 (define_insn "largetoc_low"
12109 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12110 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
12111 (match_operand:DI 2 "" "")))]
12112 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12113 "{cal %0,%2@l(%1)|addi %0,%1,%2@l}")
12114 \f
12115 ;; A function pointer under AIX is a pointer to a data area whose first word
12116 ;; contains the actual address of the function, whose second word contains a
12117 ;; pointer to its TOC, and whose third word contains a value to place in the
12118 ;; static chain register (r11). Note that if we load the static chain, our
12119 ;; "trampoline" need not have any executable code.
12121 (define_expand "call_indirect_aix32"
12122 [(set (match_dup 2)
12123 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
12124 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
12125 (reg:SI 2))
12126 (set (reg:SI 11)
12127 (mem:SI (plus:SI (match_dup 0)
12128 (const_int 8))))
12129 (parallel [(call (mem:SI (match_dup 2))
12130 (match_operand 1 "" ""))
12131 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
12132 (use (reg:SI 11))
12133 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12134 (clobber (reg:SI LR_REGNO))])]
12135 "TARGET_32BIT"
12136 "
12137 { operands[2] = gen_reg_rtx (SImode); }")
12139 (define_expand "call_indirect_aix64"
12140 [(set (match_dup 2)
12141 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
12142 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
12143 (reg:DI 2))
12144 (set (reg:DI 11)
12145 (mem:DI (plus:DI (match_dup 0)
12146 (const_int 16))))
12147 (parallel [(call (mem:SI (match_dup 2))
12148 (match_operand 1 "" ""))
12149 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
12150 (use (reg:DI 11))
12151 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12152 (clobber (reg:SI LR_REGNO))])]
12153 "TARGET_64BIT"
12154 "
12155 { operands[2] = gen_reg_rtx (DImode); }")
12157 (define_expand "call_value_indirect_aix32"
12158 [(set (match_dup 3)
12159 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12160 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
12161 (reg:SI 2))
12162 (set (reg:SI 11)
12163 (mem:SI (plus:SI (match_dup 1)
12164 (const_int 8))))
12165 (parallel [(set (match_operand 0 "" "")
12166 (call (mem:SI (match_dup 3))
12167 (match_operand 2 "" "")))
12168 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
12169 (use (reg:SI 11))
12170 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12171 (clobber (reg:SI LR_REGNO))])]
12172 "TARGET_32BIT"
12173 "
12174 { operands[3] = gen_reg_rtx (SImode); }")
12176 (define_expand "call_value_indirect_aix64"
12177 [(set (match_dup 3)
12178 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12179 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
12180 (reg:DI 2))
12181 (set (reg:DI 11)
12182 (mem:DI (plus:DI (match_dup 1)
12183 (const_int 16))))
12184 (parallel [(set (match_operand 0 "" "")
12185 (call (mem:SI (match_dup 3))
12186 (match_operand 2 "" "")))
12187 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
12188 (use (reg:DI 11))
12189 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12190 (clobber (reg:SI LR_REGNO))])]
12191 "TARGET_64BIT"
12192 "
12193 { operands[3] = gen_reg_rtx (DImode); }")
12195 ;; Now the definitions for the call and call_value insns
12196 (define_expand "call"
12197 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12198 (match_operand 1 "" ""))
12199 (use (match_operand 2 "" ""))
12200 (clobber (reg:SI LR_REGNO))])]
12201 ""
12202 "
12203 {
12204 #if TARGET_MACHO
12205 if (MACHOPIC_INDIRECT)
12206 operands[0] = machopic_indirect_call_target (operands[0]);
12207 #endif
12209 gcc_assert (GET_CODE (operands[0]) == MEM);
12210 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12212 operands[0] = XEXP (operands[0], 0);
12214 if (GET_CODE (operands[0]) != SYMBOL_REF
12215 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
12216 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
12217 {
12218 if (INTVAL (operands[2]) & CALL_LONG)
12219 operands[0] = rs6000_longcall_ref (operands[0]);
12221 switch (DEFAULT_ABI)
12222 {
12223 case ABI_V4:
12224 case ABI_DARWIN:
12225 operands[0] = force_reg (Pmode, operands[0]);
12226 break;
12228 case ABI_AIX:
12229 /* AIX function pointers are really pointers to a three word
12230 area. */
12231 emit_call_insn (TARGET_32BIT
12232 ? gen_call_indirect_aix32 (force_reg (SImode,
12233 operands[0]),
12234 operands[1])
12235 : gen_call_indirect_aix64 (force_reg (DImode,
12236 operands[0]),
12237 operands[1]));
12238 DONE;
12240 default:
12241 gcc_unreachable ();
12242 }
12243 }
12244 }")
12246 (define_expand "call_value"
12247 [(parallel [(set (match_operand 0 "" "")
12248 (call (mem:SI (match_operand 1 "address_operand" ""))
12249 (match_operand 2 "" "")))
12250 (use (match_operand 3 "" ""))
12251 (clobber (reg:SI LR_REGNO))])]
12252 ""
12253 "
12254 {
12255 #if TARGET_MACHO
12256 if (MACHOPIC_INDIRECT)
12257 operands[1] = machopic_indirect_call_target (operands[1]);
12258 #endif
12260 gcc_assert (GET_CODE (operands[1]) == MEM);
12261 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12263 operands[1] = XEXP (operands[1], 0);
12265 if (GET_CODE (operands[1]) != SYMBOL_REF
12266 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
12267 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
12268 {
12269 if (INTVAL (operands[3]) & CALL_LONG)
12270 operands[1] = rs6000_longcall_ref (operands[1]);
12272 switch (DEFAULT_ABI)
12273 {
12274 case ABI_V4:
12275 case ABI_DARWIN:
12276 operands[1] = force_reg (Pmode, operands[1]);
12277 break;
12279 case ABI_AIX:
12280 /* AIX function pointers are really pointers to a three word
12281 area. */
12282 emit_call_insn (TARGET_32BIT
12283 ? gen_call_value_indirect_aix32 (operands[0],
12284 force_reg (SImode,
12285 operands[1]),
12286 operands[2])
12287 : gen_call_value_indirect_aix64 (operands[0],
12288 force_reg (DImode,
12289 operands[1]),
12290 operands[2]));
12291 DONE;
12293 default:
12294 gcc_unreachable ();
12295 }
12296 }
12297 }")
12299 ;; Call to function in current module. No TOC pointer reload needed.
12300 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12301 ;; either the function was not prototyped, or it was prototyped as a
12302 ;; variable argument function. It is > 0 if FP registers were passed
12303 ;; and < 0 if they were not.
12305 (define_insn "*call_local32"
12306 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12307 (match_operand 1 "" "g,g"))
12308 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12309 (clobber (reg:SI LR_REGNO))]
12310 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12311 "*
12312 {
12313 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12314 output_asm_insn (\"crxor 6,6,6\", operands);
12316 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12317 output_asm_insn (\"creqv 6,6,6\", operands);
12319 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12320 }"
12321 [(set_attr "type" "branch")
12322 (set_attr "length" "4,8")])
12324 (define_insn "*call_local64"
12325 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12326 (match_operand 1 "" "g,g"))
12327 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12328 (clobber (reg:SI LR_REGNO))]
12329 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12330 "*
12331 {
12332 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12333 output_asm_insn (\"crxor 6,6,6\", operands);
12335 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12336 output_asm_insn (\"creqv 6,6,6\", operands);
12338 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12339 }"
12340 [(set_attr "type" "branch")
12341 (set_attr "length" "4,8")])
12343 (define_insn "*call_value_local32"
12344 [(set (match_operand 0 "" "")
12345 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12346 (match_operand 2 "" "g,g")))
12347 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12348 (clobber (reg:SI LR_REGNO))]
12349 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12350 "*
12351 {
12352 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12353 output_asm_insn (\"crxor 6,6,6\", operands);
12355 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12356 output_asm_insn (\"creqv 6,6,6\", operands);
12358 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12359 }"
12360 [(set_attr "type" "branch")
12361 (set_attr "length" "4,8")])
12364 (define_insn "*call_value_local64"
12365 [(set (match_operand 0 "" "")
12366 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12367 (match_operand 2 "" "g,g")))
12368 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12369 (clobber (reg:SI LR_REGNO))]
12370 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12371 "*
12372 {
12373 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12374 output_asm_insn (\"crxor 6,6,6\", operands);
12376 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12377 output_asm_insn (\"creqv 6,6,6\", operands);
12379 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12380 }"
12381 [(set_attr "type" "branch")
12382 (set_attr "length" "4,8")])
12384 ;; Call to function which may be in another module. Restore the TOC
12385 ;; pointer (r2) after the call unless this is System V.
12386 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12387 ;; either the function was not prototyped, or it was prototyped as a
12388 ;; variable argument function. It is > 0 if FP registers were passed
12389 ;; and < 0 if they were not.
12391 (define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
12392 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
12393 (match_operand 1 "" "g,g"))
12394 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
12395 (use (reg:SI 11))
12396 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12397 (clobber (reg:SI LR_REGNO))]
12398 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
12399 "#"
12400 "&& reload_completed"
12401 [(set (reg:SI 2)
12402 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
12403 (parallel [(call (mem:SI (match_dup 0))
12404 (match_dup 1))
12405 (use (reg:SI 2))
12406 (use (reg:SI 11))
12407 (set (reg:SI 2)
12408 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12409 (clobber (reg:SI LR_REGNO))])]
12410 ""
12411 [(set_attr "type" "jmpreg")
12412 (set_attr "length" "12")])
12414 (define_insn "*call_indirect_nonlocal_aix32"
12415 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
12416 (match_operand 1 "" "g,g"))
12417 (use (reg:SI 2))
12418 (use (reg:SI 11))
12419 (set (reg:SI 2)
12420 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12421 (clobber (reg:SI LR_REGNO))]
12422 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12423 "b%T0l\;{l|lwz} 2,20(1)"
12424 [(set_attr "type" "jmpreg")
12425 (set_attr "length" "8")])
12427 (define_insn "*call_nonlocal_aix32"
12428 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12429 (match_operand 1 "" "g"))
12430 (use (match_operand:SI 2 "immediate_operand" "O"))
12431 (clobber (reg:SI LR_REGNO))]
12432 "TARGET_32BIT
12433 && DEFAULT_ABI == ABI_AIX
12434 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12435 "bl %z0\;%."
12436 [(set_attr "type" "branch")
12437 (set_attr "length" "8")])
12439 (define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
12440 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
12441 (match_operand 1 "" "g,g"))
12442 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
12443 (const_int 8))))
12444 (use (reg:DI 11))
12445 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12446 (clobber (reg:SI LR_REGNO))]
12447 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
12448 "#"
12449 "&& reload_completed"
12450 [(set (reg:DI 2)
12451 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
12452 (parallel [(call (mem:SI (match_dup 0))
12453 (match_dup 1))
12454 (use (reg:DI 2))
12455 (use (reg:DI 11))
12456 (set (reg:DI 2)
12457 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12458 (clobber (reg:SI LR_REGNO))])]
12459 ""
12460 [(set_attr "type" "jmpreg")
12461 (set_attr "length" "12")])
12463 (define_insn "*call_indirect_nonlocal_aix64"
12464 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
12465 (match_operand 1 "" "g,g"))
12466 (use (reg:DI 2))
12467 (use (reg:DI 11))
12468 (set (reg:DI 2)
12469 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12470 (clobber (reg:SI LR_REGNO))]
12471 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12472 "b%T0l\;ld 2,40(1)"
12473 [(set_attr "type" "jmpreg")
12474 (set_attr "length" "8")])
12476 (define_insn "*call_nonlocal_aix64"
12477 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12478 (match_operand 1 "" "g"))
12479 (use (match_operand:SI 2 "immediate_operand" "O"))
12480 (clobber (reg:SI LR_REGNO))]
12481 "TARGET_64BIT
12482 && DEFAULT_ABI == ABI_AIX
12483 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12484 "bl %z0\;%."
12485 [(set_attr "type" "branch")
12486 (set_attr "length" "8")])
12488 (define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
12489 [(set (match_operand 0 "" "")
12490 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
12491 (match_operand 2 "" "g,g")))
12492 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
12493 (const_int 4))))
12494 (use (reg:SI 11))
12495 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12496 (clobber (reg:SI LR_REGNO))]
12497 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
12498 "#"
12499 "&& reload_completed"
12500 [(set (reg:SI 2)
12501 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
12502 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
12503 (match_dup 2)))
12504 (use (reg:SI 2))
12505 (use (reg:SI 11))
12506 (set (reg:SI 2)
12507 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12508 (clobber (reg:SI LR_REGNO))])]
12509 ""
12510 [(set_attr "type" "jmpreg")
12511 (set_attr "length" "12")])
12513 (define_insn "*call_value_indirect_nonlocal_aix32"
12514 [(set (match_operand 0 "" "")
12515 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
12516 (match_operand 2 "" "g,g")))
12517 (use (reg:SI 2))
12518 (use (reg:SI 11))
12519 (set (reg:SI 2)
12520 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
12521 (clobber (reg:SI LR_REGNO))]
12522 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12523 "b%T1l\;{l|lwz} 2,20(1)"
12524 [(set_attr "type" "jmpreg")
12525 (set_attr "length" "8")])
12527 (define_insn "*call_value_nonlocal_aix32"
12528 [(set (match_operand 0 "" "")
12529 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12530 (match_operand 2 "" "g")))
12531 (use (match_operand:SI 3 "immediate_operand" "O"))
12532 (clobber (reg:SI LR_REGNO))]
12533 "TARGET_32BIT
12534 && DEFAULT_ABI == ABI_AIX
12535 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12536 "bl %z1\;%."
12537 [(set_attr "type" "branch")
12538 (set_attr "length" "8")])
12540 (define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
12541 [(set (match_operand 0 "" "")
12542 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
12543 (match_operand 2 "" "g,g")))
12544 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
12545 (const_int 8))))
12546 (use (reg:DI 11))
12547 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12548 (clobber (reg:SI LR_REGNO))]
12549 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
12550 "#"
12551 "&& reload_completed"
12552 [(set (reg:DI 2)
12553 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
12554 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
12555 (match_dup 2)))
12556 (use (reg:DI 2))
12557 (use (reg:DI 11))
12558 (set (reg:DI 2)
12559 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12560 (clobber (reg:SI LR_REGNO))])]
12561 ""
12562 [(set_attr "type" "jmpreg")
12563 (set_attr "length" "12")])
12565 (define_insn "*call_value_indirect_nonlocal_aix64"
12566 [(set (match_operand 0 "" "")
12567 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
12568 (match_operand 2 "" "g,g")))
12569 (use (reg:DI 2))
12570 (use (reg:DI 11))
12571 (set (reg:DI 2)
12572 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
12573 (clobber (reg:SI LR_REGNO))]
12574 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
12575 "b%T1l\;ld 2,40(1)"
12576 [(set_attr "type" "jmpreg")
12577 (set_attr "length" "8")])
12579 (define_insn "*call_value_nonlocal_aix64"
12580 [(set (match_operand 0 "" "")
12581 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12582 (match_operand 2 "" "g")))
12583 (use (match_operand:SI 3 "immediate_operand" "O"))
12584 (clobber (reg:SI LR_REGNO))]
12585 "TARGET_64BIT
12586 && DEFAULT_ABI == ABI_AIX
12587 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12588 "bl %z1\;%."
12589 [(set_attr "type" "branch")
12590 (set_attr "length" "8")])
12592 ;; A function pointer under System V is just a normal pointer
12593 ;; operands[0] is the function pointer
12594 ;; operands[1] is the stack size to clean up
12595 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12596 ;; which indicates how to set cr1
12598 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12599 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12600 (match_operand 1 "" "g,g,g,g"))
12601 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12602 (clobber (reg:SI LR_REGNO))]
12603 "DEFAULT_ABI == ABI_V4
12604 || DEFAULT_ABI == ABI_DARWIN"
12605 {
12606 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12607 output_asm_insn ("crxor 6,6,6", operands);
12609 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12610 output_asm_insn ("creqv 6,6,6", operands);
12612 return "b%T0l";
12613 }
12614 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12615 (set_attr "length" "4,4,8,8")])
12617 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12618 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12619 (match_operand 1 "" "g,g"))
12620 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12621 (clobber (reg:SI LR_REGNO))]
12622 "(DEFAULT_ABI == ABI_DARWIN
12623 || (DEFAULT_ABI == ABI_V4
12624 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12625 {
12626 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12627 output_asm_insn ("crxor 6,6,6", operands);
12629 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12630 output_asm_insn ("creqv 6,6,6", operands);
12632 #if TARGET_MACHO
12633 return output_call(insn, operands, 0, 2);
12634 #else
12635 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12636 {
12637 gcc_assert (!TARGET_SECURE_PLT);
12638 return "bl %z0@plt";
12639 }
12640 else
12641 return "bl %z0";
12642 #endif
12643 }
12644 "DEFAULT_ABI == ABI_V4
12645 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12646 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12647 [(parallel [(call (mem:SI (match_dup 0))
12648 (match_dup 1))
12649 (use (match_dup 2))
12650 (use (match_dup 3))
12651 (clobber (reg:SI LR_REGNO))])]
12652 {
12653 operands[3] = pic_offset_table_rtx;
12654 }
12655 [(set_attr "type" "branch,branch")
12656 (set_attr "length" "4,8")])
12658 (define_insn "*call_nonlocal_sysv_secure<mode>"
12659 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12660 (match_operand 1 "" "g,g"))
12661 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12662 (use (match_operand:SI 3 "register_operand" "r,r"))
12663 (clobber (reg:SI LR_REGNO))]
12664 "(DEFAULT_ABI == ABI_V4
12665 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12666 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12667 {
12668 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12669 output_asm_insn ("crxor 6,6,6", operands);
12671 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12672 output_asm_insn ("creqv 6,6,6", operands);
12674 if (flag_pic == 2)
12675 /* The magic 32768 offset here and in the other sysv call insns
12676 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12677 See sysv4.h:toc_section. */
12678 return "bl %z0+32768@plt";
12679 else
12680 return "bl %z0@plt";
12681 }
12682 [(set_attr "type" "branch,branch")
12683 (set_attr "length" "4,8")])
12685 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12686 [(set (match_operand 0 "" "")
12687 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12688 (match_operand 2 "" "g,g,g,g")))
12689 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12690 (clobber (reg:SI LR_REGNO))]
12691 "DEFAULT_ABI == ABI_V4
12692 || DEFAULT_ABI == ABI_DARWIN"
12693 {
12694 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12695 output_asm_insn ("crxor 6,6,6", operands);
12697 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12698 output_asm_insn ("creqv 6,6,6", operands);
12700 return "b%T1l";
12701 }
12702 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12703 (set_attr "length" "4,4,8,8")])
12705 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12706 [(set (match_operand 0 "" "")
12707 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12708 (match_operand 2 "" "g,g")))
12709 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12710 (clobber (reg:SI LR_REGNO))]
12711 "(DEFAULT_ABI == ABI_DARWIN
12712 || (DEFAULT_ABI == ABI_V4
12713 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12714 {
12715 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12716 output_asm_insn ("crxor 6,6,6", operands);
12718 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12719 output_asm_insn ("creqv 6,6,6", operands);
12721 #if TARGET_MACHO
12722 return output_call(insn, operands, 1, 3);
12723 #else
12724 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12725 {
12726 gcc_assert (!TARGET_SECURE_PLT);
12727 return "bl %z1@plt";
12728 }
12729 else
12730 return "bl %z1";
12731 #endif
12732 }
12733 "DEFAULT_ABI == ABI_V4
12734 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12735 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12736 [(parallel [(set (match_dup 0)
12737 (call (mem:SI (match_dup 1))
12738 (match_dup 2)))
12739 (use (match_dup 3))
12740 (use (match_dup 4))
12741 (clobber (reg:SI LR_REGNO))])]
12742 {
12743 operands[4] = pic_offset_table_rtx;
12744 }
12745 [(set_attr "type" "branch,branch")
12746 (set_attr "length" "4,8")])
12748 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12749 [(set (match_operand 0 "" "")
12750 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12751 (match_operand 2 "" "g,g")))
12752 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12753 (use (match_operand:SI 4 "register_operand" "r,r"))
12754 (clobber (reg:SI LR_REGNO))]
12755 "(DEFAULT_ABI == ABI_V4
12756 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12757 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12758 {
12759 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12760 output_asm_insn ("crxor 6,6,6", operands);
12762 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12763 output_asm_insn ("creqv 6,6,6", operands);
12765 if (flag_pic == 2)
12766 return "bl %z1+32768@plt";
12767 else
12768 return "bl %z1@plt";
12769 }
12770 [(set_attr "type" "branch,branch")
12771 (set_attr "length" "4,8")])
12773 ;; Call subroutine returning any type.
12774 (define_expand "untyped_call"
12775 [(parallel [(call (match_operand 0 "" "")
12776 (const_int 0))
12777 (match_operand 1 "" "")
12778 (match_operand 2 "" "")])]
12779 ""
12780 "
12781 {
12782 int i;
12784 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12786 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12787 {
12788 rtx set = XVECEXP (operands[2], 0, i);
12789 emit_move_insn (SET_DEST (set), SET_SRC (set));
12790 }
12792 /* The optimizer does not know that the call sets the function value
12793 registers we stored in the result block. We avoid problems by
12794 claiming that all hard registers are used and clobbered at this
12795 point. */
12796 emit_insn (gen_blockage ());
12798 DONE;
12799 }")
12801 ;; sibling call patterns
12802 (define_expand "sibcall"
12803 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12804 (match_operand 1 "" ""))
12805 (use (match_operand 2 "" ""))
12806 (use (reg:SI LR_REGNO))
12807 (return)])]
12808 ""
12809 "
12810 {
12811 #if TARGET_MACHO
12812 if (MACHOPIC_INDIRECT)
12813 operands[0] = machopic_indirect_call_target (operands[0]);
12814 #endif
12816 gcc_assert (GET_CODE (operands[0]) == MEM);
12817 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12819 operands[0] = XEXP (operands[0], 0);
12820 }")
12822 ;; this and similar patterns must be marked as using LR, otherwise
12823 ;; dataflow will try to delete the store into it. This is true
12824 ;; even when the actual reg to jump to is in CTR, when LR was
12825 ;; saved and restored around the PIC-setting BCL.
12826 (define_insn "*sibcall_local32"
12827 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12828 (match_operand 1 "" "g,g"))
12829 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12830 (use (reg:SI LR_REGNO))
12831 (return)]
12832 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12833 "*
12834 {
12835 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12836 output_asm_insn (\"crxor 6,6,6\", operands);
12838 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12839 output_asm_insn (\"creqv 6,6,6\", operands);
12841 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12842 }"
12843 [(set_attr "type" "branch")
12844 (set_attr "length" "4,8")])
12846 (define_insn "*sibcall_local64"
12847 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12848 (match_operand 1 "" "g,g"))
12849 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12850 (use (reg:SI LR_REGNO))
12851 (return)]
12852 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12853 "*
12854 {
12855 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12856 output_asm_insn (\"crxor 6,6,6\", operands);
12858 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12859 output_asm_insn (\"creqv 6,6,6\", operands);
12861 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12862 }"
12863 [(set_attr "type" "branch")
12864 (set_attr "length" "4,8")])
12866 (define_insn "*sibcall_value_local32"
12867 [(set (match_operand 0 "" "")
12868 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12869 (match_operand 2 "" "g,g")))
12870 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12871 (use (reg:SI LR_REGNO))
12872 (return)]
12873 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12874 "*
12875 {
12876 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12877 output_asm_insn (\"crxor 6,6,6\", operands);
12879 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12880 output_asm_insn (\"creqv 6,6,6\", operands);
12882 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12883 }"
12884 [(set_attr "type" "branch")
12885 (set_attr "length" "4,8")])
12888 (define_insn "*sibcall_value_local64"
12889 [(set (match_operand 0 "" "")
12890 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12891 (match_operand 2 "" "g,g")))
12892 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12893 (use (reg:SI LR_REGNO))
12894 (return)]
12895 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12896 "*
12897 {
12898 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12899 output_asm_insn (\"crxor 6,6,6\", operands);
12901 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12902 output_asm_insn (\"creqv 6,6,6\", operands);
12904 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12905 }"
12906 [(set_attr "type" "branch")
12907 (set_attr "length" "4,8")])
12909 (define_insn "*sibcall_nonlocal_aix32"
12910 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12911 (match_operand 1 "" "g"))
12912 (use (match_operand:SI 2 "immediate_operand" "O"))
12913 (use (reg:SI LR_REGNO))
12914 (return)]
12915 "TARGET_32BIT
12916 && DEFAULT_ABI == ABI_AIX
12917 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12918 "b %z0"
12919 [(set_attr "type" "branch")
12920 (set_attr "length" "4")])
12922 (define_insn "*sibcall_nonlocal_aix64"
12923 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12924 (match_operand 1 "" "g"))
12925 (use (match_operand:SI 2 "immediate_operand" "O"))
12926 (use (reg:SI LR_REGNO))
12927 (return)]
12928 "TARGET_64BIT
12929 && DEFAULT_ABI == ABI_AIX
12930 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12931 "b %z0"
12932 [(set_attr "type" "branch")
12933 (set_attr "length" "4")])
12935 (define_insn "*sibcall_value_nonlocal_aix32"
12936 [(set (match_operand 0 "" "")
12937 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12938 (match_operand 2 "" "g")))
12939 (use (match_operand:SI 3 "immediate_operand" "O"))
12940 (use (reg:SI LR_REGNO))
12941 (return)]
12942 "TARGET_32BIT
12943 && DEFAULT_ABI == ABI_AIX
12944 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12945 "b %z1"
12946 [(set_attr "type" "branch")
12947 (set_attr "length" "4")])
12949 (define_insn "*sibcall_value_nonlocal_aix64"
12950 [(set (match_operand 0 "" "")
12951 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12952 (match_operand 2 "" "g")))
12953 (use (match_operand:SI 3 "immediate_operand" "O"))
12954 (use (reg:SI LR_REGNO))
12955 (return)]
12956 "TARGET_64BIT
12957 && DEFAULT_ABI == ABI_AIX
12958 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12959 "b %z1"
12960 [(set_attr "type" "branch")
12961 (set_attr "length" "4")])
12963 (define_insn "*sibcall_nonlocal_sysv<mode>"
12964 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12965 (match_operand 1 "" ""))
12966 (use (match_operand 2 "immediate_operand" "O,n"))
12967 (use (reg:SI LR_REGNO))
12968 (return)]
12969 "(DEFAULT_ABI == ABI_DARWIN
12970 || DEFAULT_ABI == ABI_V4)
12971 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12972 "*
12973 {
12974 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12975 output_asm_insn (\"crxor 6,6,6\", operands);
12977 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12978 output_asm_insn (\"creqv 6,6,6\", operands);
12980 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12981 {
12982 gcc_assert (!TARGET_SECURE_PLT);
12983 return \"b %z0@plt\";
12984 }
12985 else
12986 return \"b %z0\";
12987 }"
12988 [(set_attr "type" "branch,branch")
12989 (set_attr "length" "4,8")])
12991 (define_expand "sibcall_value"
12992 [(parallel [(set (match_operand 0 "register_operand" "")
12993 (call (mem:SI (match_operand 1 "address_operand" ""))
12994 (match_operand 2 "" "")))
12995 (use (match_operand 3 "" ""))
12996 (use (reg:SI LR_REGNO))
12997 (return)])]
12998 ""
12999 "
13000 {
13001 #if TARGET_MACHO
13002 if (MACHOPIC_INDIRECT)
13003 operands[1] = machopic_indirect_call_target (operands[1]);
13004 #endif
13006 gcc_assert (GET_CODE (operands[1]) == MEM);
13007 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
13009 operands[1] = XEXP (operands[1], 0);
13010 }")
13012 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
13013 [(set (match_operand 0 "" "")
13014 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
13015 (match_operand 2 "" "")))
13016 (use (match_operand:SI 3 "immediate_operand" "O,n"))
13017 (use (reg:SI LR_REGNO))
13018 (return)]
13019 "(DEFAULT_ABI == ABI_DARWIN
13020 || DEFAULT_ABI == ABI_V4)
13021 && (INTVAL (operands[3]) & CALL_LONG) == 0"
13022 "*
13023 {
13024 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
13025 output_asm_insn (\"crxor 6,6,6\", operands);
13027 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
13028 output_asm_insn (\"creqv 6,6,6\", operands);
13030 if (DEFAULT_ABI == ABI_V4 && flag_pic)
13031 {
13032 gcc_assert (!TARGET_SECURE_PLT);
13033 return \"b %z1@plt\";
13034 }
13035 else
13036 return \"b %z1\";
13037 }"
13038 [(set_attr "type" "branch,branch")
13039 (set_attr "length" "4,8")])
13041 (define_expand "sibcall_epilogue"
13042 [(use (const_int 0))]
13043 "TARGET_SCHED_PROLOG"
13044 "
13045 {
13046 rs6000_emit_epilogue (TRUE);
13047 DONE;
13048 }")
13050 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13051 ;; all of memory. This blocks insns from being moved across this point.
13053 (define_insn "blockage"
13054 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
13055 ""
13056 "")
13058 (define_insn "probe_stack"
13059 [(set (match_operand 0 "memory_operand" "=m")
13060 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
13061 ""
13062 "{st%U0%X0|stw%U0%X0} 0,%0"
13063 [(set_attr "type" "store")
13064 (set_attr "length" "4")])
13066 (define_insn "probe_stack_range<P:mode>"
13067 [(set (match_operand:P 0 "register_operand" "=r")
13068 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
13069 (match_operand:P 2 "register_operand" "r")]
13070 UNSPECV_PROBE_STACK_RANGE))]
13071 ""
13072 "* return output_probe_stack_range (operands[0], operands[2]);"
13073 [(set_attr "type" "three")])
13074 \f
13075 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
13076 ;; signed & unsigned, and one type of branch.
13077 ;;
13078 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
13079 ;; insns, and branches.
13081 (define_expand "cbranch<mode>4"
13082 [(use (match_operator 0 "rs6000_cbranch_operator"
13083 [(match_operand:GPR 1 "gpc_reg_operand" "")
13084 (match_operand:GPR 2 "reg_or_short_operand" "")]))
13085 (use (match_operand 3 ""))]
13086 ""
13087 "
13088 {
13089 /* Take care of the possibility that operands[2] might be negative but
13090 this might be a logical operation. That insn doesn't exist. */
13091 if (GET_CODE (operands[2]) == CONST_INT
13092 && INTVAL (operands[2]) < 0)
13093 {
13094 operands[2] = force_reg (<MODE>mode, operands[2]);
13095 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
13096 GET_MODE (operands[0]),
13097 operands[1], operands[2]);
13098 }
13100 rs6000_emit_cbranch (<MODE>mode, operands);
13101 DONE;
13102 }")
13104 (define_expand "cbranch<mode>4"
13105 [(use (match_operator 0 "rs6000_cbranch_operator"
13106 [(match_operand:FP 1 "gpc_reg_operand" "")
13107 (match_operand:FP 2 "gpc_reg_operand" "")]))
13108 (use (match_operand 3 ""))]
13109 ""
13110 "
13111 {
13112 rs6000_emit_cbranch (<MODE>mode, operands);
13113 DONE;
13114 }")
13116 (define_expand "cstore<mode>4"
13117 [(use (match_operator 1 "rs6000_cbranch_operator"
13118 [(match_operand:GPR 2 "gpc_reg_operand" "")
13119 (match_operand:GPR 3 "reg_or_short_operand" "")]))
13120 (clobber (match_operand:SI 0 "register_operand"))]
13121 ""
13122 "
13123 {
13124 /* Take care of the possibility that operands[3] might be negative but
13125 this might be a logical operation. That insn doesn't exist. */
13126 if (GET_CODE (operands[3]) == CONST_INT
13127 && INTVAL (operands[3]) < 0)
13128 {
13129 operands[3] = force_reg (<MODE>mode, operands[3]);
13130 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
13131 GET_MODE (operands[1]),
13132 operands[2], operands[3]);
13133 }
13135 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
13136 For SEQ, likewise, except that comparisons with zero should be done
13137 with an scc insns. However, due to the order that combine see the
13138 resulting insns, we must, in fact, allow SEQ for integers. Fail in
13139 the cases we don't want to handle or are best handled by portable
13140 code. */
13141 if (GET_CODE (operands[1]) == NE)
13142 FAIL;
13143 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
13144 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
13145 && operands[3] == const0_rtx)
13146 FAIL;
13147 rs6000_emit_sCOND (<MODE>mode, operands);
13148 DONE;
13149 }")
13151 (define_expand "cstore<mode>4"
13152 [(use (match_operator 1 "rs6000_cbranch_operator"
13153 [(match_operand:FP 2 "gpc_reg_operand" "")
13154 (match_operand:FP 3 "gpc_reg_operand" "")]))
13155 (clobber (match_operand:SI 0 "register_operand"))]
13156 ""
13157 "
13158 {
13159 rs6000_emit_sCOND (<MODE>mode, operands);
13160 DONE;
13161 }")
13164 (define_expand "stack_protect_set"
13165 [(match_operand 0 "memory_operand" "")
13166 (match_operand 1 "memory_operand" "")]
13167 ""
13168 {
13169 #ifdef TARGET_THREAD_SSP_OFFSET
13170 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
13171 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
13172 operands[1] = gen_rtx_MEM (Pmode, addr);
13173 #endif
13174 if (TARGET_64BIT)
13175 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
13176 else
13177 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
13178 DONE;
13179 })
13181 (define_insn "stack_protect_setsi"
13182 [(set (match_operand:SI 0 "memory_operand" "=m")
13183 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13184 (set (match_scratch:SI 2 "=&r") (const_int 0))]
13185 "TARGET_32BIT"
13186 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
13187 [(set_attr "type" "three")
13188 (set_attr "length" "12")])
13190 (define_insn "stack_protect_setdi"
13191 [(set (match_operand:DI 0 "memory_operand" "=m")
13192 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13193 (set (match_scratch:DI 2 "=&r") (const_int 0))]
13194 "TARGET_64BIT"
13195 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
13196 [(set_attr "type" "three")
13197 (set_attr "length" "12")])
13199 (define_expand "stack_protect_test"
13200 [(match_operand 0 "memory_operand" "")
13201 (match_operand 1 "memory_operand" "")
13202 (match_operand 2 "" "")]
13203 ""
13204 {
13205 rtx test, op0, op1;
13206 #ifdef TARGET_THREAD_SSP_OFFSET
13207 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
13208 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
13209 operands[1] = gen_rtx_MEM (Pmode, addr);
13210 #endif
13211 op0 = operands[0];
13212 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
13213 test = gen_rtx_EQ (VOIDmode, op0, op1);
13214 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
13215 DONE;
13216 })
13218 (define_insn "stack_protect_testsi"
13219 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13220 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
13221 (match_operand:SI 2 "memory_operand" "m,m")]
13222 UNSPEC_SP_TEST))
13223 (set (match_scratch:SI 4 "=r,r") (const_int 0))
13224 (clobber (match_scratch:SI 3 "=&r,&r"))]
13225 "TARGET_32BIT"
13226 "@
13227 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
13228 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
13229 [(set_attr "length" "16,20")])
13231 (define_insn "stack_protect_testdi"
13232 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13233 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
13234 (match_operand:DI 2 "memory_operand" "m,m")]
13235 UNSPEC_SP_TEST))
13236 (set (match_scratch:DI 4 "=r,r") (const_int 0))
13237 (clobber (match_scratch:DI 3 "=&r,&r"))]
13238 "TARGET_64BIT"
13239 "@
13240 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
13241 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
13242 [(set_attr "length" "16,20")])
13244 \f
13245 ;; Here are the actual compare insns.
13246 (define_insn "*cmp<mode>_internal1"
13247 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13248 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
13249 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
13250 ""
13251 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
13252 [(set_attr "type" "cmp")])
13254 ;; If we are comparing a register for equality with a large constant,
13255 ;; we can do this with an XOR followed by a compare. But this is profitable
13256 ;; only if the large constant is only used for the comparison (and in this
13257 ;; case we already have a register to reuse as scratch).
13258 ;;
13259 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
13260 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
13262 (define_peephole2
13263 [(set (match_operand:SI 0 "register_operand")
13264 (match_operand:SI 1 "logical_const_operand" ""))
13265 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
13266 [(match_dup 0)
13267 (match_operand:SI 2 "logical_const_operand" "")]))
13268 (set (match_operand:CC 4 "cc_reg_operand" "")
13269 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
13270 (match_dup 0)))
13271 (set (pc)
13272 (if_then_else (match_operator 6 "equality_operator"
13273 [(match_dup 4) (const_int 0)])
13274 (match_operand 7 "" "")
13275 (match_operand 8 "" "")))]
13276 "peep2_reg_dead_p (3, operands[0])
13277 && peep2_reg_dead_p (4, operands[4])"
13278 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
13279 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
13280 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
13282 {
13283 /* Get the constant we are comparing against, and see what it looks like
13284 when sign-extended from 16 to 32 bits. Then see what constant we could
13285 XOR with SEXTC to get the sign-extended value. */
13286 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
13287 SImode,
13288 operands[1], operands[2]);
13289 HOST_WIDE_INT c = INTVAL (cnst);
13290 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
13291 HOST_WIDE_INT xorv = c ^ sextc;
13293 operands[9] = GEN_INT (xorv);
13294 operands[10] = GEN_INT (sextc);
13295 })
13297 (define_insn "*cmpsi_internal2"
13298 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13299 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13300 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
13301 ""
13302 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
13303 [(set_attr "type" "cmp")])
13305 (define_insn "*cmpdi_internal2"
13306 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13307 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
13308 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
13309 ""
13310 "cmpld%I2 %0,%1,%b2"
13311 [(set_attr "type" "cmp")])
13313 ;; The following two insns don't exist as single insns, but if we provide
13314 ;; them, we can swap an add and compare, which will enable us to overlap more
13315 ;; of the required delay between a compare and branch. We generate code for
13316 ;; them by splitting.
13318 (define_insn ""
13319 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13320 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
13321 (match_operand:SI 2 "short_cint_operand" "i")))
13322 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13323 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13324 ""
13325 "#"
13326 [(set_attr "length" "8")])
13328 (define_insn ""
13329 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
13330 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13331 (match_operand:SI 2 "u_short_cint_operand" "i")))
13332 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13333 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13334 ""
13335 "#"
13336 [(set_attr "length" "8")])
13338 (define_split
13339 [(set (match_operand:CC 3 "cc_reg_operand" "")
13340 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
13341 (match_operand:SI 2 "short_cint_operand" "")))
13342 (set (match_operand:SI 0 "gpc_reg_operand" "")
13343 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13344 ""
13345 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
13346 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13348 (define_split
13349 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
13350 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
13351 (match_operand:SI 2 "u_short_cint_operand" "")))
13352 (set (match_operand:SI 0 "gpc_reg_operand" "")
13353 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13354 ""
13355 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
13356 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13358 (define_insn "*cmpsf_internal1"
13359 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13360 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
13361 (match_operand:SF 2 "gpc_reg_operand" "f")))]
13362 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
13363 "fcmpu %0,%1,%2"
13364 [(set_attr "type" "fpcompare")])
13366 (define_insn "*cmpdf_internal1"
13367 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13368 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
13369 (match_operand:DF 2 "gpc_reg_operand" "d")))]
13370 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
13371 && !VECTOR_UNIT_VSX_P (DFmode)"
13372 "fcmpu %0,%1,%2"
13373 [(set_attr "type" "fpcompare")])
13375 ;; Only need to compare second words if first words equal
13376 (define_insn "*cmptf_internal1"
13377 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13378 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13379 (match_operand:TF 2 "gpc_reg_operand" "d")))]
13380 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
13381 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13382 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
13383 [(set_attr "type" "fpcompare")
13384 (set_attr "length" "12")])
13386 (define_insn_and_split "*cmptf_internal2"
13387 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13388 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13389 (match_operand:TF 2 "gpc_reg_operand" "d")))
13390 (clobber (match_scratch:DF 3 "=d"))
13391 (clobber (match_scratch:DF 4 "=d"))
13392 (clobber (match_scratch:DF 5 "=d"))
13393 (clobber (match_scratch:DF 6 "=d"))
13394 (clobber (match_scratch:DF 7 "=d"))
13395 (clobber (match_scratch:DF 8 "=d"))
13396 (clobber (match_scratch:DF 9 "=d"))
13397 (clobber (match_scratch:DF 10 "=d"))
13398 (clobber (match_scratch:GPR 11 "=b"))]
13399 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
13400 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13401 "#"
13402 "&& reload_completed"
13403 [(set (match_dup 3) (match_dup 14))
13404 (set (match_dup 4) (match_dup 15))
13405 (set (match_dup 9) (abs:DF (match_dup 5)))
13406 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
13407 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
13408 (label_ref (match_dup 12))
13409 (pc)))
13410 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
13411 (set (pc) (label_ref (match_dup 13)))
13412 (match_dup 12)
13413 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
13414 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
13415 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
13416 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
13417 (match_dup 13)]
13418 {
13419 REAL_VALUE_TYPE rv;
13420 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
13421 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
13423 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
13424 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
13425 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
13426 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
13427 operands[12] = gen_label_rtx ();
13428 operands[13] = gen_label_rtx ();
13429 real_inf (&rv);
13430 operands[14] = force_const_mem (DFmode,
13431 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
13432 operands[15] = force_const_mem (DFmode,
13433 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
13434 DFmode));
13435 if (TARGET_TOC)
13436 {
13437 rtx tocref;
13438 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
13439 operands[14] = gen_const_mem (DFmode, tocref);
13440 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
13441 operands[15] = gen_const_mem (DFmode, tocref);
13442 set_mem_alias_set (operands[14], get_TOC_alias_set ());
13443 set_mem_alias_set (operands[15], get_TOC_alias_set ());
13444 }
13445 })
13446 \f
13447 ;; Now we have the scc insns. We can do some combinations because of the
13448 ;; way the machine works.
13449 ;;
13450 ;; Note that this is probably faster if we can put an insn between the
13451 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
13452 ;; cases the insns below which don't use an intermediate CR field will
13453 ;; be used instead.
13454 (define_insn ""
13455 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13456 (match_operator:SI 1 "scc_comparison_operator"
13457 [(match_operand 2 "cc_reg_operand" "y")
13458 (const_int 0)]))]
13459 ""
13460 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
13461 [(set (attr "type")
13462 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13463 (const_string "mfcrf")
13464 ]
13465 (const_string "mfcr")))
13466 (set_attr "length" "8")])
13468 ;; Same as above, but get the GT bit.
13469 (define_insn "move_from_CR_gt_bit"
13470 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13471 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
13472 "TARGET_HARD_FLOAT && !TARGET_FPRS"
13473 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
13474 [(set_attr "type" "mfcr")
13475 (set_attr "length" "8")])
13477 ;; Same as above, but get the OV/ORDERED bit.
13478 (define_insn "move_from_CR_ov_bit"
13479 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13480 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
13481 "TARGET_ISEL"
13482 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
13483 [(set_attr "type" "mfcr")
13484 (set_attr "length" "8")])
13486 (define_insn ""
13487 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13488 (match_operator:DI 1 "scc_comparison_operator"
13489 [(match_operand 2 "cc_reg_operand" "y")
13490 (const_int 0)]))]
13491 "TARGET_POWERPC64"
13492 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
13493 [(set (attr "type")
13494 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13495 (const_string "mfcrf")
13496 ]
13497 (const_string "mfcr")))
13498 (set_attr "length" "8")])
13500 (define_insn ""
13501 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13502 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13503 [(match_operand 2 "cc_reg_operand" "y,y")
13504 (const_int 0)])
13505 (const_int 0)))
13506 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
13507 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13508 "TARGET_32BIT"
13509 "@
13510 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
13511 #"
13512 [(set_attr "type" "delayed_compare")
13513 (set_attr "length" "8,16")])
13515 (define_split
13516 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13517 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13518 [(match_operand 2 "cc_reg_operand" "")
13519 (const_int 0)])
13520 (const_int 0)))
13521 (set (match_operand:SI 3 "gpc_reg_operand" "")
13522 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13523 "TARGET_32BIT && reload_completed"
13524 [(set (match_dup 3)
13525 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
13526 (set (match_dup 0)
13527 (compare:CC (match_dup 3)
13528 (const_int 0)))]
13529 "")
13531 (define_insn ""
13532 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13533 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13534 [(match_operand 2 "cc_reg_operand" "y")
13535 (const_int 0)])
13536 (match_operand:SI 3 "const_int_operand" "n")))]
13537 ""
13538 "*
13539 {
13540 int is_bit = ccr_bit (operands[1], 1);
13541 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13542 int count;
13544 if (is_bit >= put_bit)
13545 count = is_bit - put_bit;
13546 else
13547 count = 32 - (put_bit - is_bit);
13549 operands[4] = GEN_INT (count);
13550 operands[5] = GEN_INT (put_bit);
13552 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
13553 }"
13554 [(set (attr "type")
13555 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
13556 (const_string "mfcrf")
13557 ]
13558 (const_string "mfcr")))
13559 (set_attr "length" "8")])
13561 (define_insn ""
13562 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13563 (compare:CC
13564 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13565 [(match_operand 2 "cc_reg_operand" "y,y")
13566 (const_int 0)])
13567 (match_operand:SI 3 "const_int_operand" "n,n"))
13568 (const_int 0)))
13569 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13570 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13571 (match_dup 3)))]
13572 ""
13573 "*
13574 {
13575 int is_bit = ccr_bit (operands[1], 1);
13576 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13577 int count;
13579 /* Force split for non-cc0 compare. */
13580 if (which_alternative == 1)
13581 return \"#\";
13583 if (is_bit >= put_bit)
13584 count = is_bit - put_bit;
13585 else
13586 count = 32 - (put_bit - is_bit);
13588 operands[5] = GEN_INT (count);
13589 operands[6] = GEN_INT (put_bit);
13591 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
13592 }"
13593 [(set_attr "type" "delayed_compare")
13594 (set_attr "length" "8,16")])
13596 (define_split
13597 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13598 (compare:CC
13599 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13600 [(match_operand 2 "cc_reg_operand" "")
13601 (const_int 0)])
13602 (match_operand:SI 3 "const_int_operand" ""))
13603 (const_int 0)))
13604 (set (match_operand:SI 4 "gpc_reg_operand" "")
13605 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13606 (match_dup 3)))]
13607 "reload_completed"
13608 [(set (match_dup 4)
13609 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13610 (match_dup 3)))
13611 (set (match_dup 0)
13612 (compare:CC (match_dup 4)
13613 (const_int 0)))]
13614 "")
13616 ;; There is a 3 cycle delay between consecutive mfcr instructions
13617 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13619 (define_peephole
13620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13621 (match_operator:SI 1 "scc_comparison_operator"
13622 [(match_operand 2 "cc_reg_operand" "y")
13623 (const_int 0)]))
13624 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13625 (match_operator:SI 4 "scc_comparison_operator"
13626 [(match_operand 5 "cc_reg_operand" "y")
13627 (const_int 0)]))]
13628 "REGNO (operands[2]) != REGNO (operands[5])"
13629 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13630 [(set_attr "type" "mfcr")
13631 (set_attr "length" "12")])
13633 (define_peephole
13634 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13635 (match_operator:DI 1 "scc_comparison_operator"
13636 [(match_operand 2 "cc_reg_operand" "y")
13637 (const_int 0)]))
13638 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13639 (match_operator:DI 4 "scc_comparison_operator"
13640 [(match_operand 5 "cc_reg_operand" "y")
13641 (const_int 0)]))]
13642 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13643 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13644 [(set_attr "type" "mfcr")
13645 (set_attr "length" "12")])
13647 ;; There are some scc insns that can be done directly, without a compare.
13648 ;; These are faster because they don't involve the communications between
13649 ;; the FXU and branch units. In fact, we will be replacing all of the
13650 ;; integer scc insns here or in the portable methods in emit_store_flag.
13651 ;;
13652 ;; Also support (neg (scc ..)) since that construct is used to replace
13653 ;; branches, (plus (scc ..) ..) since that construct is common and
13654 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13655 ;; cases where it is no more expensive than (neg (scc ..)).
13657 ;; Have reload force a constant into a register for the simple insns that
13658 ;; otherwise won't accept constants. We do this because it is faster than
13659 ;; the cmp/mfcr sequence we would otherwise generate.
13661 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13662 (DI "rKJI")])
13664 (define_insn_and_split "*eq<mode>"
13665 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13666 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13667 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13668 "!TARGET_POWER"
13669 "#"
13670 "!TARGET_POWER"
13671 [(set (match_dup 0)
13672 (clz:GPR (match_dup 3)))
13673 (set (match_dup 0)
13674 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13675 {
13676 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13677 {
13678 /* Use output operand as intermediate. */
13679 operands[3] = operands[0];
13681 if (logical_operand (operands[2], <MODE>mode))
13682 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13683 gen_rtx_XOR (<MODE>mode,
13684 operands[1], operands[2])));
13685 else
13686 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13687 gen_rtx_PLUS (<MODE>mode, operands[1],
13688 negate_rtx (<MODE>mode,
13689 operands[2]))));
13690 }
13691 else
13692 operands[3] = operands[1];
13694 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13695 })
13697 (define_insn_and_split "*eq<mode>_compare"
13698 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13699 (compare:CC
13700 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13701 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13702 (const_int 0)))
13703 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13704 (eq:P (match_dup 1) (match_dup 2)))]
13705 "!TARGET_POWER && optimize_size"
13706 "#"
13707 "!TARGET_POWER && optimize_size"
13708 [(set (match_dup 0)
13709 (clz:P (match_dup 4)))
13710 (parallel [(set (match_dup 3)
13711 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13712 (const_int 0)))
13713 (set (match_dup 0)
13714 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13715 {
13716 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13717 {
13718 /* Use output operand as intermediate. */
13719 operands[4] = operands[0];
13721 if (logical_operand (operands[2], <MODE>mode))
13722 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13723 gen_rtx_XOR (<MODE>mode,
13724 operands[1], operands[2])));
13725 else
13726 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13727 gen_rtx_PLUS (<MODE>mode, operands[1],
13728 negate_rtx (<MODE>mode,
13729 operands[2]))));
13730 }
13731 else
13732 operands[4] = operands[1];
13734 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13735 })
13737 (define_insn "*eqsi_power"
13738 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
13739 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13740 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
13741 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
13742 "TARGET_POWER"
13743 "@
13744 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13745 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
13746 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13747 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13748 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
13749 [(set_attr "type" "three,two,three,three,three")
13750 (set_attr "length" "12,8,12,12,12")])
13752 ;; We have insns of the form shown by the first define_insn below. If
13753 ;; there is something inside the comparison operation, we must split it.
13754 (define_split
13755 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13756 (plus:SI (match_operator 1 "comparison_operator"
13757 [(match_operand:SI 2 "" "")
13758 (match_operand:SI 3
13759 "reg_or_cint_operand" "")])
13760 (match_operand:SI 4 "gpc_reg_operand" "")))
13761 (clobber (match_operand:SI 5 "register_operand" ""))]
13762 "! gpc_reg_operand (operands[2], SImode)"
13763 [(set (match_dup 5) (match_dup 2))
13764 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
13765 (match_dup 4)))])
13767 (define_insn "*plus_eqsi"
13768 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13769 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13770 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13771 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13772 "TARGET_32BIT"
13773 "@
13774 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13775 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
13776 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13777 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13778 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13779 [(set_attr "type" "three,two,three,three,three")
13780 (set_attr "length" "12,8,12,12,12")])
13782 (define_insn "*compare_plus_eqsi"
13783 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13784 (compare:CC
13785 (plus:SI
13786 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13787 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13788 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13789 (const_int 0)))
13790 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13791 "TARGET_32BIT && optimize_size"
13792 "@
13793 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13794 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
13795 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13796 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13797 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13798 #
13799 #
13800 #
13801 #
13802 #"
13803 [(set_attr "type" "compare")
13804 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13806 (define_split
13807 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13808 (compare:CC
13809 (plus:SI
13810 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13811 (match_operand:SI 2 "scc_eq_operand" ""))
13812 (match_operand:SI 3 "gpc_reg_operand" ""))
13813 (const_int 0)))
13814 (clobber (match_scratch:SI 4 ""))]
13815 "TARGET_32BIT && optimize_size && reload_completed"
13816 [(set (match_dup 4)
13817 (plus:SI (eq:SI (match_dup 1)
13818 (match_dup 2))
13819 (match_dup 3)))
13820 (set (match_dup 0)
13821 (compare:CC (match_dup 4)
13822 (const_int 0)))]
13823 "")
13825 (define_insn "*plus_eqsi_compare"
13826 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13827 (compare:CC
13828 (plus:SI
13829 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13830 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13831 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13832 (const_int 0)))
13833 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13834 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13835 "TARGET_32BIT && optimize_size"
13836 "@
13837 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13838 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
13839 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13840 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13841 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13842 #
13843 #
13844 #
13845 #
13846 #"
13847 [(set_attr "type" "compare")
13848 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13850 (define_split
13851 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13852 (compare:CC
13853 (plus:SI
13854 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13855 (match_operand:SI 2 "scc_eq_operand" ""))
13856 (match_operand:SI 3 "gpc_reg_operand" ""))
13857 (const_int 0)))
13858 (set (match_operand:SI 0 "gpc_reg_operand" "")
13859 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13860 "TARGET_32BIT && optimize_size && reload_completed"
13861 [(set (match_dup 0)
13862 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13863 (set (match_dup 4)
13864 (compare:CC (match_dup 0)
13865 (const_int 0)))]
13866 "")
13868 (define_insn "*neg_eq0<mode>"
13869 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13870 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13871 (const_int 0))))]
13872 ""
13873 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
13874 [(set_attr "type" "two")
13875 (set_attr "length" "8")])
13877 (define_insn_and_split "*neg_eq<mode>"
13878 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13879 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13880 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13881 ""
13882 "#"
13883 ""
13884 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13885 {
13886 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13887 {
13888 /* Use output operand as intermediate. */
13889 operands[3] = operands[0];
13891 if (logical_operand (operands[2], <MODE>mode))
13892 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13893 gen_rtx_XOR (<MODE>mode,
13894 operands[1], operands[2])));
13895 else
13896 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13897 gen_rtx_PLUS (<MODE>mode, operands[1],
13898 negate_rtx (<MODE>mode,
13899 operands[2]))));
13900 }
13901 else
13902 operands[3] = operands[1];
13903 })
13905 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
13906 ;; since it nabs/sr is just as fast.
13907 (define_insn "*ne0si"
13908 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13909 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13910 (const_int 31)))
13911 (clobber (match_scratch:SI 2 "=&r"))]
13912 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
13913 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
13914 [(set_attr "type" "two")
13915 (set_attr "length" "8")])
13917 (define_insn "*ne0di"
13918 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13919 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13920 (const_int 63)))
13921 (clobber (match_scratch:DI 2 "=&r"))]
13922 "TARGET_64BIT"
13923 "addic %2,%1,-1\;subfe %0,%2,%1"
13924 [(set_attr "type" "two")
13925 (set_attr "length" "8")])
13927 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
13928 (define_insn "*plus_ne0si"
13929 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13930 (plus:SI (lshiftrt:SI
13931 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13932 (const_int 31))
13933 (match_operand:SI 2 "gpc_reg_operand" "r")))
13934 (clobber (match_scratch:SI 3 "=&r"))]
13935 "TARGET_32BIT"
13936 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
13937 [(set_attr "type" "two")
13938 (set_attr "length" "8")])
13940 (define_insn "*plus_ne0di"
13941 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13942 (plus:DI (lshiftrt:DI
13943 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13944 (const_int 63))
13945 (match_operand:DI 2 "gpc_reg_operand" "r")))
13946 (clobber (match_scratch:DI 3 "=&r"))]
13947 "TARGET_64BIT"
13948 "addic %3,%1,-1\;addze %0,%2"
13949 [(set_attr "type" "two")
13950 (set_attr "length" "8")])
13952 (define_insn "*compare_plus_ne0si"
13953 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13954 (compare:CC
13955 (plus:SI (lshiftrt:SI
13956 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13957 (const_int 31))
13958 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13959 (const_int 0)))
13960 (clobber (match_scratch:SI 3 "=&r,&r"))
13961 (clobber (match_scratch:SI 4 "=X,&r"))]
13962 "TARGET_32BIT"
13963 "@
13964 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
13965 #"
13966 [(set_attr "type" "compare")
13967 (set_attr "length" "8,12")])
13969 (define_split
13970 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13971 (compare:CC
13972 (plus:SI (lshiftrt:SI
13973 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13974 (const_int 31))
13975 (match_operand:SI 2 "gpc_reg_operand" ""))
13976 (const_int 0)))
13977 (clobber (match_scratch:SI 3 ""))
13978 (clobber (match_scratch:SI 4 ""))]
13979 "TARGET_32BIT && reload_completed"
13980 [(parallel [(set (match_dup 3)
13981 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
13982 (const_int 31))
13983 (match_dup 2)))
13984 (clobber (match_dup 4))])
13985 (set (match_dup 0)
13986 (compare:CC (match_dup 3)
13987 (const_int 0)))]
13988 "")
13990 (define_insn "*compare_plus_ne0di"
13991 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13992 (compare:CC
13993 (plus:DI (lshiftrt:DI
13994 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13995 (const_int 63))
13996 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13997 (const_int 0)))
13998 (clobber (match_scratch:DI 3 "=&r,&r"))]
13999 "TARGET_64BIT"
14000 "@
14001 addic %3,%1,-1\;addze. %3,%2
14002 #"
14003 [(set_attr "type" "compare")
14004 (set_attr "length" "8,12")])
14006 (define_split
14007 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14008 (compare:CC
14009 (plus:DI (lshiftrt:DI
14010 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
14011 (const_int 63))
14012 (match_operand:DI 2 "gpc_reg_operand" ""))
14013 (const_int 0)))
14014 (clobber (match_scratch:DI 3 ""))]
14015 "TARGET_64BIT && reload_completed"
14016 [(set (match_dup 3)
14017 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
14018 (const_int 63))
14019 (match_dup 2)))
14020 (set (match_dup 0)
14021 (compare:CC (match_dup 3)
14022 (const_int 0)))]
14023 "")
14025 (define_insn "*plus_ne0si_compare"
14026 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14027 (compare:CC
14028 (plus:SI (lshiftrt:SI
14029 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
14030 (const_int 31))
14031 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14032 (const_int 0)))
14033 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14034 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14035 (match_dup 2)))
14036 (clobber (match_scratch:SI 3 "=&r,&r"))]
14037 "TARGET_32BIT"
14038 "@
14039 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
14040 #"
14041 [(set_attr "type" "compare")
14042 (set_attr "length" "8,12")])
14044 (define_split
14045 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14046 (compare:CC
14047 (plus:SI (lshiftrt:SI
14048 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
14049 (const_int 31))
14050 (match_operand:SI 2 "gpc_reg_operand" ""))
14051 (const_int 0)))
14052 (set (match_operand:SI 0 "gpc_reg_operand" "")
14053 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14054 (match_dup 2)))
14055 (clobber (match_scratch:SI 3 ""))]
14056 "TARGET_32BIT && reload_completed"
14057 [(parallel [(set (match_dup 0)
14058 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14059 (match_dup 2)))
14060 (clobber (match_dup 3))])
14061 (set (match_dup 4)
14062 (compare:CC (match_dup 0)
14063 (const_int 0)))]
14064 "")
14066 (define_insn "*plus_ne0di_compare"
14067 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14068 (compare:CC
14069 (plus:DI (lshiftrt:DI
14070 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
14071 (const_int 63))
14072 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14073 (const_int 0)))
14074 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
14075 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14076 (match_dup 2)))
14077 (clobber (match_scratch:DI 3 "=&r,&r"))]
14078 "TARGET_64BIT"
14079 "@
14080 addic %3,%1,-1\;addze. %0,%2
14081 #"
14082 [(set_attr "type" "compare")
14083 (set_attr "length" "8,12")])
14085 (define_split
14086 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
14087 (compare:CC
14088 (plus:DI (lshiftrt:DI
14089 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
14090 (const_int 63))
14091 (match_operand:DI 2 "gpc_reg_operand" ""))
14092 (const_int 0)))
14093 (set (match_operand:DI 0 "gpc_reg_operand" "")
14094 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14095 (match_dup 2)))
14096 (clobber (match_scratch:DI 3 ""))]
14097 "TARGET_64BIT && reload_completed"
14098 [(parallel [(set (match_dup 0)
14099 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14100 (match_dup 2)))
14101 (clobber (match_dup 3))])
14102 (set (match_dup 4)
14103 (compare:CC (match_dup 0)
14104 (const_int 0)))]
14105 "")
14107 (define_insn ""
14108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14109 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14110 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
14111 (clobber (match_scratch:SI 3 "=r,X"))]
14112 "TARGET_POWER"
14113 "@
14114 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
14115 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
14116 [(set_attr "length" "12")])
14118 (define_insn ""
14119 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14120 (compare:CC
14121 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14122 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14123 (const_int 0)))
14124 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
14125 (le:SI (match_dup 1) (match_dup 2)))
14126 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
14127 "TARGET_POWER"
14128 "@
14129 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14130 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
14131 #
14132 #"
14133 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
14134 (set_attr "length" "12,12,16,16")])
14136 (define_split
14137 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14138 (compare:CC
14139 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14140 (match_operand:SI 2 "reg_or_short_operand" ""))
14141 (const_int 0)))
14142 (set (match_operand:SI 0 "gpc_reg_operand" "")
14143 (le:SI (match_dup 1) (match_dup 2)))
14144 (clobber (match_scratch:SI 3 ""))]
14145 "TARGET_POWER && reload_completed"
14146 [(parallel [(set (match_dup 0)
14147 (le:SI (match_dup 1) (match_dup 2)))
14148 (clobber (match_dup 3))])
14149 (set (match_dup 4)
14150 (compare:CC (match_dup 0)
14151 (const_int 0)))]
14152 "")
14154 (define_insn ""
14155 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14156 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14157 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
14158 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
14159 "TARGET_POWER"
14160 "@
14161 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
14162 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
14163 [(set_attr "length" "12")])
14165 (define_insn ""
14166 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14167 (compare:CC
14168 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14169 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14170 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14171 (const_int 0)))
14172 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14173 "TARGET_POWER"
14174 "@
14175 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14176 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
14177 #
14178 #"
14179 [(set_attr "type" "compare")
14180 (set_attr "length" "12,12,16,16")])
14182 (define_split
14183 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14184 (compare:CC
14185 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14186 (match_operand:SI 2 "reg_or_short_operand" ""))
14187 (match_operand:SI 3 "gpc_reg_operand" ""))
14188 (const_int 0)))
14189 (clobber (match_scratch:SI 4 ""))]
14190 "TARGET_POWER && reload_completed"
14191 [(set (match_dup 4)
14192 (plus:SI (le:SI (match_dup 1) (match_dup 2))
14193 (match_dup 3)))
14194 (set (match_dup 0)
14195 (compare:CC (match_dup 4)
14196 (const_int 0)))]
14197 "")
14199 (define_insn ""
14200 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14201 (compare:CC
14202 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14203 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14204 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14205 (const_int 0)))
14206 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14207 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14208 "TARGET_POWER"
14209 "@
14210 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14211 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
14212 #
14213 #"
14214 [(set_attr "type" "compare")
14215 (set_attr "length" "12,12,16,16")])
14217 (define_split
14218 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14219 (compare:CC
14220 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14221 (match_operand:SI 2 "reg_or_short_operand" ""))
14222 (match_operand:SI 3 "gpc_reg_operand" ""))
14223 (const_int 0)))
14224 (set (match_operand:SI 0 "gpc_reg_operand" "")
14225 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14226 "TARGET_POWER && reload_completed"
14227 [(set (match_dup 0)
14228 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14229 (set (match_dup 4)
14230 (compare:CC (match_dup 0)
14231 (const_int 0)))]
14232 "")
14234 (define_insn ""
14235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14236 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14237 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
14238 "TARGET_POWER"
14239 "@
14240 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
14241 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
14242 [(set_attr "length" "12")])
14244 (define_insn "*leu<mode>"
14245 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14246 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14247 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14248 ""
14249 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14250 [(set_attr "type" "three")
14251 (set_attr "length" "12")])
14253 (define_insn "*leu<mode>_compare"
14254 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14255 (compare:CC
14256 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14257 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14258 (const_int 0)))
14259 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14260 (leu:P (match_dup 1) (match_dup 2)))]
14261 ""
14262 "@
14263 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14264 #"
14265 [(set_attr "type" "compare")
14266 (set_attr "length" "12,16")])
14268 (define_split
14269 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14270 (compare:CC
14271 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
14272 (match_operand:P 2 "reg_or_short_operand" ""))
14273 (const_int 0)))
14274 (set (match_operand:P 0 "gpc_reg_operand" "")
14275 (leu:P (match_dup 1) (match_dup 2)))]
14276 "reload_completed"
14277 [(set (match_dup 0)
14278 (leu:P (match_dup 1) (match_dup 2)))
14279 (set (match_dup 3)
14280 (compare:CC (match_dup 0)
14281 (const_int 0)))]
14282 "")
14284 (define_insn "*plus_leu<mode>"
14285 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14286 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14287 (match_operand:P 2 "reg_or_short_operand" "rI"))
14288 (match_operand:P 3 "gpc_reg_operand" "r")))]
14289 ""
14290 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
14291 [(set_attr "type" "two")
14292 (set_attr "length" "8")])
14294 (define_insn ""
14295 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14296 (compare:CC
14297 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14298 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14299 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14300 (const_int 0)))
14301 (clobber (match_scratch:SI 4 "=&r,&r"))]
14302 "TARGET_32BIT"
14303 "@
14304 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
14305 #"
14306 [(set_attr "type" "compare")
14307 (set_attr "length" "8,12")])
14309 (define_split
14310 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14311 (compare:CC
14312 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14313 (match_operand:SI 2 "reg_or_short_operand" ""))
14314 (match_operand:SI 3 "gpc_reg_operand" ""))
14315 (const_int 0)))
14316 (clobber (match_scratch:SI 4 ""))]
14317 "TARGET_32BIT && reload_completed"
14318 [(set (match_dup 4)
14319 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
14320 (match_dup 3)))
14321 (set (match_dup 0)
14322 (compare:CC (match_dup 4)
14323 (const_int 0)))]
14324 "")
14326 (define_insn ""
14327 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14328 (compare:CC
14329 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14330 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14331 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14332 (const_int 0)))
14333 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14334 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14335 "TARGET_32BIT"
14336 "@
14337 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
14338 #"
14339 [(set_attr "type" "compare")
14340 (set_attr "length" "8,12")])
14342 (define_split
14343 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14344 (compare:CC
14345 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14346 (match_operand:SI 2 "reg_or_short_operand" ""))
14347 (match_operand:SI 3 "gpc_reg_operand" ""))
14348 (const_int 0)))
14349 (set (match_operand:SI 0 "gpc_reg_operand" "")
14350 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14351 "TARGET_32BIT && reload_completed"
14352 [(set (match_dup 0)
14353 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14354 (set (match_dup 4)
14355 (compare:CC (match_dup 0)
14356 (const_int 0)))]
14357 "")
14359 (define_insn "*neg_leu<mode>"
14360 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14361 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14362 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14363 ""
14364 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
14365 [(set_attr "type" "three")
14366 (set_attr "length" "12")])
14368 (define_insn "*and_neg_leu<mode>"
14369 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14370 (and:P (neg:P
14371 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14372 (match_operand:P 2 "reg_or_short_operand" "rI")))
14373 (match_operand:P 3 "gpc_reg_operand" "r")))]
14374 ""
14375 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14376 [(set_attr "type" "three")
14377 (set_attr "length" "12")])
14379 (define_insn ""
14380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14381 (compare:CC
14382 (and:SI (neg:SI
14383 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14384 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14385 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14386 (const_int 0)))
14387 (clobber (match_scratch:SI 4 "=&r,&r"))]
14388 "TARGET_32BIT"
14389 "@
14390 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14391 #"
14392 [(set_attr "type" "compare")
14393 (set_attr "length" "12,16")])
14395 (define_split
14396 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14397 (compare:CC
14398 (and:SI (neg:SI
14399 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14400 (match_operand:SI 2 "reg_or_short_operand" "")))
14401 (match_operand:SI 3 "gpc_reg_operand" ""))
14402 (const_int 0)))
14403 (clobber (match_scratch:SI 4 ""))]
14404 "TARGET_32BIT && reload_completed"
14405 [(set (match_dup 4)
14406 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14407 (match_dup 3)))
14408 (set (match_dup 0)
14409 (compare:CC (match_dup 4)
14410 (const_int 0)))]
14411 "")
14413 (define_insn ""
14414 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14415 (compare:CC
14416 (and:SI (neg:SI
14417 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14418 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14419 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14420 (const_int 0)))
14421 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14422 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14423 "TARGET_32BIT"
14424 "@
14425 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14426 #"
14427 [(set_attr "type" "compare")
14428 (set_attr "length" "12,16")])
14430 (define_split
14431 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14432 (compare:CC
14433 (and:SI (neg:SI
14434 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14435 (match_operand:SI 2 "reg_or_short_operand" "")))
14436 (match_operand:SI 3 "gpc_reg_operand" ""))
14437 (const_int 0)))
14438 (set (match_operand:SI 0 "gpc_reg_operand" "")
14439 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14440 "TARGET_32BIT && reload_completed"
14441 [(set (match_dup 0)
14442 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14443 (match_dup 3)))
14444 (set (match_dup 4)
14445 (compare:CC (match_dup 0)
14446 (const_int 0)))]
14447 "")
14449 (define_insn ""
14450 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14451 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14452 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
14453 "TARGET_POWER"
14454 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14455 [(set_attr "length" "12")])
14457 (define_insn ""
14458 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14459 (compare:CC
14460 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14461 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14462 (const_int 0)))
14463 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14464 (lt:SI (match_dup 1) (match_dup 2)))]
14465 "TARGET_POWER"
14466 "@
14467 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14468 #"
14469 [(set_attr "type" "delayed_compare")
14470 (set_attr "length" "12,16")])
14472 (define_split
14473 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14474 (compare:CC
14475 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14476 (match_operand:SI 2 "reg_or_short_operand" ""))
14477 (const_int 0)))
14478 (set (match_operand:SI 0 "gpc_reg_operand" "")
14479 (lt:SI (match_dup 1) (match_dup 2)))]
14480 "TARGET_POWER && reload_completed"
14481 [(set (match_dup 0)
14482 (lt:SI (match_dup 1) (match_dup 2)))
14483 (set (match_dup 3)
14484 (compare:CC (match_dup 0)
14485 (const_int 0)))]
14486 "")
14488 (define_insn ""
14489 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14490 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14491 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14492 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14493 "TARGET_POWER"
14494 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14495 [(set_attr "length" "12")])
14497 (define_insn ""
14498 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14499 (compare:CC
14500 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14501 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14502 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14503 (const_int 0)))
14504 (clobber (match_scratch:SI 4 "=&r,&r"))]
14505 "TARGET_POWER"
14506 "@
14507 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14508 #"
14509 [(set_attr "type" "compare")
14510 (set_attr "length" "12,16")])
14512 (define_split
14513 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14514 (compare:CC
14515 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14516 (match_operand:SI 2 "reg_or_short_operand" ""))
14517 (match_operand:SI 3 "gpc_reg_operand" ""))
14518 (const_int 0)))
14519 (clobber (match_scratch:SI 4 ""))]
14520 "TARGET_POWER && reload_completed"
14521 [(set (match_dup 4)
14522 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
14523 (match_dup 3)))
14524 (set (match_dup 0)
14525 (compare:CC (match_dup 4)
14526 (const_int 0)))]
14527 "")
14529 (define_insn ""
14530 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14531 (compare:CC
14532 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14533 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14534 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14535 (const_int 0)))
14536 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14537 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14538 "TARGET_POWER"
14539 "@
14540 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14541 #"
14542 [(set_attr "type" "compare")
14543 (set_attr "length" "12,16")])
14545 (define_split
14546 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14547 (compare:CC
14548 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14549 (match_operand:SI 2 "reg_or_short_operand" ""))
14550 (match_operand:SI 3 "gpc_reg_operand" ""))
14551 (const_int 0)))
14552 (set (match_operand:SI 0 "gpc_reg_operand" "")
14553 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14554 "TARGET_POWER && reload_completed"
14555 [(set (match_dup 0)
14556 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14557 (set (match_dup 4)
14558 (compare:CC (match_dup 0)
14559 (const_int 0)))]
14560 "")
14562 (define_insn ""
14563 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14564 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14565 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14566 "TARGET_POWER"
14567 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14568 [(set_attr "length" "12")])
14570 (define_insn_and_split "*ltu<mode>"
14571 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14572 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14573 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14574 ""
14575 "#"
14576 ""
14577 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14578 (set (match_dup 0) (neg:P (match_dup 0)))]
14579 "")
14581 (define_insn_and_split "*ltu<mode>_compare"
14582 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14583 (compare:CC
14584 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14585 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14586 (const_int 0)))
14587 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14588 (ltu:P (match_dup 1) (match_dup 2)))]
14589 ""
14590 "#"
14591 ""
14592 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14593 (parallel [(set (match_dup 3)
14594 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14595 (set (match_dup 0) (neg:P (match_dup 0)))])]
14596 "")
14598 (define_insn_and_split "*plus_ltu<mode>"
14599 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14600 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14601 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14602 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14603 ""
14604 "#"
14605 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14606 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14607 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14608 "")
14610 (define_insn_and_split "*plus_ltu<mode>_compare"
14611 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14612 (compare:CC
14613 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14614 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14615 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14616 (const_int 0)))
14617 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14618 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14619 ""
14620 "#"
14621 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14622 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14623 (parallel [(set (match_dup 4)
14624 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14625 (const_int 0)))
14626 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14627 "")
14629 (define_insn "*neg_ltu<mode>"
14630 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14631 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14632 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14633 ""
14634 "@
14635 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
14636 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
14637 [(set_attr "type" "two")
14638 (set_attr "length" "8")])
14640 (define_insn ""
14641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14642 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14643 (match_operand:SI 2 "reg_or_short_operand" "rI")))
14644 (clobber (match_scratch:SI 3 "=r"))]
14645 "TARGET_POWER"
14646 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
14647 [(set_attr "length" "12")])
14649 (define_insn ""
14650 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14651 (compare:CC
14652 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14653 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14654 (const_int 0)))
14655 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14656 (ge:SI (match_dup 1) (match_dup 2)))
14657 (clobber (match_scratch:SI 3 "=r,r"))]
14658 "TARGET_POWER"
14659 "@
14660 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14661 #"
14662 [(set_attr "type" "compare")
14663 (set_attr "length" "12,16")])
14665 (define_split
14666 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14667 (compare:CC
14668 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14669 (match_operand:SI 2 "reg_or_short_operand" ""))
14670 (const_int 0)))
14671 (set (match_operand:SI 0 "gpc_reg_operand" "")
14672 (ge:SI (match_dup 1) (match_dup 2)))
14673 (clobber (match_scratch:SI 3 ""))]
14674 "TARGET_POWER && reload_completed"
14675 [(parallel [(set (match_dup 0)
14676 (ge:SI (match_dup 1) (match_dup 2)))
14677 (clobber (match_dup 3))])
14678 (set (match_dup 4)
14679 (compare:CC (match_dup 0)
14680 (const_int 0)))]
14681 "")
14683 (define_insn ""
14684 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14685 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14686 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14687 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14688 "TARGET_POWER"
14689 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
14690 [(set_attr "length" "12")])
14692 (define_insn ""
14693 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14694 (compare:CC
14695 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14696 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14697 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14698 (const_int 0)))
14699 (clobber (match_scratch:SI 4 "=&r,&r"))]
14700 "TARGET_POWER"
14701 "@
14702 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14703 #"
14704 [(set_attr "type" "compare")
14705 (set_attr "length" "12,16")])
14707 (define_split
14708 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14709 (compare:CC
14710 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14711 (match_operand:SI 2 "reg_or_short_operand" ""))
14712 (match_operand:SI 3 "gpc_reg_operand" ""))
14713 (const_int 0)))
14714 (clobber (match_scratch:SI 4 ""))]
14715 "TARGET_POWER && reload_completed"
14716 [(set (match_dup 4)
14717 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
14718 (match_dup 3)))
14719 (set (match_dup 0)
14720 (compare:CC (match_dup 4)
14721 (const_int 0)))]
14722 "")
14724 (define_insn ""
14725 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14726 (compare:CC
14727 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14728 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14729 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14730 (const_int 0)))
14731 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14732 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14733 "TARGET_POWER"
14734 "@
14735 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14736 #"
14737 [(set_attr "type" "compare")
14738 (set_attr "length" "12,16")])
14740 (define_split
14741 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14742 (compare:CC
14743 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14744 (match_operand:SI 2 "reg_or_short_operand" ""))
14745 (match_operand:SI 3 "gpc_reg_operand" ""))
14746 (const_int 0)))
14747 (set (match_operand:SI 0 "gpc_reg_operand" "")
14748 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14749 "TARGET_POWER && reload_completed"
14750 [(set (match_dup 0)
14751 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14752 (set (match_dup 4)
14753 (compare:CC (match_dup 0)
14754 (const_int 0)))]
14755 "")
14757 (define_insn ""
14758 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14759 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14760 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14761 "TARGET_POWER"
14762 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
14763 [(set_attr "length" "12")])
14765 (define_insn "*geu<mode>"
14766 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14767 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14768 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14769 ""
14770 "@
14771 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
14772 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14773 [(set_attr "type" "three")
14774 (set_attr "length" "12")])
14776 (define_insn "*geu<mode>_compare"
14777 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14778 (compare:CC
14779 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14780 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14781 (const_int 0)))
14782 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14783 (geu:P (match_dup 1) (match_dup 2)))]
14784 ""
14785 "@
14786 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14787 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14788 #
14789 #"
14790 [(set_attr "type" "compare")
14791 (set_attr "length" "12,12,16,16")])
14793 (define_split
14794 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14795 (compare:CC
14796 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14797 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14798 (const_int 0)))
14799 (set (match_operand:P 0 "gpc_reg_operand" "")
14800 (geu:P (match_dup 1) (match_dup 2)))]
14801 "reload_completed"
14802 [(set (match_dup 0)
14803 (geu:P (match_dup 1) (match_dup 2)))
14804 (set (match_dup 3)
14805 (compare:CC (match_dup 0)
14806 (const_int 0)))]
14807 "")
14809 (define_insn "*plus_geu<mode>"
14810 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14811 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14812 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14813 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14814 ""
14815 "@
14816 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
14817 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
14818 [(set_attr "type" "two")
14819 (set_attr "length" "8")])
14821 (define_insn ""
14822 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14823 (compare:CC
14824 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14825 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14826 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14827 (const_int 0)))
14828 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14829 "TARGET_32BIT"
14830 "@
14831 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
14832 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
14833 #
14834 #"
14835 [(set_attr "type" "compare")
14836 (set_attr "length" "8,8,12,12")])
14838 (define_split
14839 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14840 (compare:CC
14841 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14842 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14843 (match_operand:SI 3 "gpc_reg_operand" ""))
14844 (const_int 0)))
14845 (clobber (match_scratch:SI 4 ""))]
14846 "TARGET_32BIT && reload_completed"
14847 [(set (match_dup 4)
14848 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14849 (match_dup 3)))
14850 (set (match_dup 0)
14851 (compare:CC (match_dup 4)
14852 (const_int 0)))]
14853 "")
14855 (define_insn ""
14856 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14857 (compare:CC
14858 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14859 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14860 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14861 (const_int 0)))
14862 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14863 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14864 "TARGET_32BIT"
14865 "@
14866 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
14867 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
14868 #
14869 #"
14870 [(set_attr "type" "compare")
14871 (set_attr "length" "8,8,12,12")])
14873 (define_split
14874 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14875 (compare:CC
14876 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14877 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14878 (match_operand:SI 3 "gpc_reg_operand" ""))
14879 (const_int 0)))
14880 (set (match_operand:SI 0 "gpc_reg_operand" "")
14881 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14882 "TARGET_32BIT && reload_completed"
14883 [(set (match_dup 0)
14884 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14885 (set (match_dup 4)
14886 (compare:CC (match_dup 0)
14887 (const_int 0)))]
14888 "")
14890 (define_insn "*neg_geu<mode>"
14891 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14892 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14893 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14894 ""
14895 "@
14896 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
14897 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
14898 [(set_attr "type" "three")
14899 (set_attr "length" "12")])
14901 (define_insn "*and_neg_geu<mode>"
14902 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14903 (and:P (neg:P
14904 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14905 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14906 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14907 ""
14908 "@
14909 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
14910 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14911 [(set_attr "type" "three")
14912 (set_attr "length" "12")])
14914 (define_insn ""
14915 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14916 (compare:CC
14917 (and:SI (neg:SI
14918 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14919 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14920 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14921 (const_int 0)))
14922 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14923 "TARGET_32BIT"
14924 "@
14925 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14926 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14927 #
14928 #"
14929 [(set_attr "type" "compare")
14930 (set_attr "length" "12,12,16,16")])
14932 (define_split
14933 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14934 (compare:CC
14935 (and:SI (neg:SI
14936 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14937 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14938 (match_operand:SI 3 "gpc_reg_operand" ""))
14939 (const_int 0)))
14940 (clobber (match_scratch:SI 4 ""))]
14941 "TARGET_32BIT && reload_completed"
14942 [(set (match_dup 4)
14943 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14944 (match_dup 3)))
14945 (set (match_dup 0)
14946 (compare:CC (match_dup 4)
14947 (const_int 0)))]
14948 "")
14950 (define_insn ""
14951 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14952 (compare:CC
14953 (and:SI (neg:SI
14954 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14955 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14956 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14957 (const_int 0)))
14958 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14959 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14960 "TARGET_32BIT"
14961 "@
14962 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14963 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14964 #
14965 #"
14966 [(set_attr "type" "compare")
14967 (set_attr "length" "12,12,16,16")])
14969 (define_split
14970 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14971 (compare:CC
14972 (and:SI (neg:SI
14973 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14974 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14975 (match_operand:SI 3 "gpc_reg_operand" ""))
14976 (const_int 0)))
14977 (set (match_operand:SI 0 "gpc_reg_operand" "")
14978 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14979 "TARGET_32BIT && reload_completed"
14980 [(set (match_dup 0)
14981 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14982 (set (match_dup 4)
14983 (compare:CC (match_dup 0)
14984 (const_int 0)))]
14985 "")
14987 (define_insn ""
14988 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14989 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14990 (match_operand:SI 2 "reg_or_short_operand" "r")))]
14991 "TARGET_POWER"
14992 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14993 [(set_attr "length" "12")])
14995 (define_insn ""
14996 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14997 (compare:CC
14998 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14999 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15000 (const_int 0)))
15001 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
15002 (gt:SI (match_dup 1) (match_dup 2)))]
15003 "TARGET_POWER"
15004 "@
15005 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
15006 #"
15007 [(set_attr "type" "delayed_compare")
15008 (set_attr "length" "12,16")])
15010 (define_split
15011 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
15012 (compare:CC
15013 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15014 (match_operand:SI 2 "reg_or_short_operand" ""))
15015 (const_int 0)))
15016 (set (match_operand:SI 0 "gpc_reg_operand" "")
15017 (gt:SI (match_dup 1) (match_dup 2)))]
15018 "TARGET_POWER && reload_completed"
15019 [(set (match_dup 0)
15020 (gt:SI (match_dup 1) (match_dup 2)))
15021 (set (match_dup 3)
15022 (compare:CC (match_dup 0)
15023 (const_int 0)))]
15024 "")
15026 (define_insn "*plus_gt0<mode>"
15027 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
15028 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
15029 (const_int 0))
15030 (match_operand:P 2 "gpc_reg_operand" "r")))]
15031 ""
15032 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
15033 [(set_attr "type" "three")
15034 (set_attr "length" "12")])
15036 (define_insn ""
15037 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15038 (compare:CC
15039 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15040 (const_int 0))
15041 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
15042 (const_int 0)))
15043 (clobber (match_scratch:SI 3 "=&r,&r"))]
15044 "TARGET_32BIT"
15045 "@
15046 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
15047 #"
15048 [(set_attr "type" "compare")
15049 (set_attr "length" "12,16")])
15051 (define_split
15052 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
15053 (compare:CC
15054 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15055 (const_int 0))
15056 (match_operand:SI 2 "gpc_reg_operand" ""))
15057 (const_int 0)))
15058 (clobber (match_scratch:SI 3 ""))]
15059 "TARGET_32BIT && reload_completed"
15060 [(set (match_dup 3)
15061 (plus:SI (gt:SI (match_dup 1) (const_int 0))
15062 (match_dup 2)))
15063 (set (match_dup 0)
15064 (compare:CC (match_dup 3)
15065 (const_int 0)))]
15066 "")
15068 (define_insn ""
15069 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15070 (compare:CC
15071 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
15072 (const_int 0))
15073 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
15074 (const_int 0)))
15075 (clobber (match_scratch:DI 3 "=&r,&r"))]
15076 "TARGET_64BIT"
15077 "@
15078 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
15079 #"
15080 [(set_attr "type" "compare")
15081 (set_attr "length" "12,16")])
15083 (define_split
15084 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
15085 (compare:CC
15086 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
15087 (const_int 0))
15088 (match_operand:DI 2 "gpc_reg_operand" ""))
15089 (const_int 0)))
15090 (clobber (match_scratch:DI 3 ""))]
15091 "TARGET_64BIT && reload_completed"
15092 [(set (match_dup 3)
15093 (plus:DI (gt:DI (match_dup 1) (const_int 0))
15094 (match_dup 2)))
15095 (set (match_dup 0)
15096 (compare:CC (match_dup 3)
15097 (const_int 0)))]
15098 "")
15100 (define_insn ""
15101 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15102 (compare:CC
15103 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15104 (const_int 0))
15105 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
15106 (const_int 0)))
15107 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
15108 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
15109 "TARGET_32BIT"
15110 "@
15111 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
15112 #"
15113 [(set_attr "type" "compare")
15114 (set_attr "length" "12,16")])
15116 (define_split
15117 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
15118 (compare:CC
15119 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15120 (const_int 0))
15121 (match_operand:SI 2 "gpc_reg_operand" ""))
15122 (const_int 0)))
15123 (set (match_operand:SI 0 "gpc_reg_operand" "")
15124 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
15125 "TARGET_32BIT && reload_completed"
15126 [(set (match_dup 0)
15127 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
15128 (set (match_dup 3)
15129 (compare:CC (match_dup 0)
15130 (const_int 0)))]
15131 "")
15133 (define_insn ""
15134 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15135 (compare:CC
15136 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
15137 (const_int 0))
15138 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
15139 (const_int 0)))
15140 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
15141 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
15142 "TARGET_64BIT"
15143 "@
15144 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
15145 #"
15146 [(set_attr "type" "compare")
15147 (set_attr "length" "12,16")])
15149 (define_split
15150 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
15151 (compare:CC
15152 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
15153 (const_int 0))
15154 (match_operand:DI 2 "gpc_reg_operand" ""))
15155 (const_int 0)))
15156 (set (match_operand:DI 0 "gpc_reg_operand" "")
15157 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
15158 "TARGET_64BIT && reload_completed"
15159 [(set (match_dup 0)
15160 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
15161 (set (match_dup 3)
15162 (compare:CC (match_dup 0)
15163 (const_int 0)))]
15164 "")
15166 (define_insn ""
15167 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
15168 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15169 (match_operand:SI 2 "reg_or_short_operand" "r"))
15170 (match_operand:SI 3 "gpc_reg_operand" "r")))]
15171 "TARGET_POWER"
15172 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
15173 [(set_attr "length" "12")])
15175 (define_insn ""
15176 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15177 (compare:CC
15178 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15179 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15180 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
15181 (const_int 0)))
15182 (clobber (match_scratch:SI 4 "=&r,&r"))]
15183 "TARGET_POWER"
15184 "@
15185 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
15186 #"
15187 [(set_attr "type" "compare")
15188 (set_attr "length" "12,16")])
15190 (define_split
15191 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
15192 (compare:CC
15193 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15194 (match_operand:SI 2 "reg_or_short_operand" ""))
15195 (match_operand:SI 3 "gpc_reg_operand" ""))
15196 (const_int 0)))
15197 (clobber (match_scratch:SI 4 ""))]
15198 "TARGET_POWER && reload_completed"
15199 [(set (match_dup 4)
15200 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
15201 (set (match_dup 0)
15202 (compare:CC (match_dup 4)
15203 (const_int 0)))]
15204 "")
15206 (define_insn ""
15207 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
15208 (compare:CC
15209 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15210 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15211 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
15212 (const_int 0)))
15213 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
15214 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
15215 "TARGET_POWER"
15216 "@
15217 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
15218 #"
15219 [(set_attr "type" "compare")
15220 (set_attr "length" "12,16")])
15222 (define_split
15223 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
15224 (compare:CC
15225 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15226 (match_operand:SI 2 "reg_or_short_operand" ""))
15227 (match_operand:SI 3 "gpc_reg_operand" ""))
15228 (const_int 0)))
15229 (set (match_operand:SI 0 "gpc_reg_operand" "")
15230 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
15231 "TARGET_POWER && reload_completed"
15232 [(set (match_dup 0)
15233 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
15234 (set (match_dup 4)
15235 (compare:CC (match_dup 0)
15236 (const_int 0)))]
15237 "")
15239 (define_insn ""
15240 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15241 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15242 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
15243 "TARGET_POWER"
15244 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
15245 [(set_attr "length" "12")])
15247 (define_insn_and_split "*gtu<mode>"
15248 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15249 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15250 (match_operand:P 2 "reg_or_short_operand" "rI")))]
15251 ""
15252 "#"
15253 ""
15254 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15255 (set (match_dup 0) (neg:P (match_dup 0)))]
15256 "")
15258 (define_insn_and_split "*gtu<mode>_compare"
15259 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15260 (compare:CC
15261 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
15262 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
15263 (const_int 0)))
15264 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
15265 (gtu:P (match_dup 1) (match_dup 2)))]
15266 ""
15267 "#"
15268 ""
15269 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15270 (parallel [(set (match_dup 3)
15271 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
15272 (set (match_dup 0) (neg:P (match_dup 0)))])]
15273 "")
15275 (define_insn_and_split "*plus_gtu<mode>"
15276 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
15277 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15278 (match_operand:P 2 "reg_or_short_operand" "rI"))
15279 (match_operand:P 3 "reg_or_short_operand" "rI")))]
15280 ""
15281 "#"
15282 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
15283 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15284 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
15285 "")
15287 (define_insn_and_split "*plus_gtu<mode>_compare"
15288 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
15289 (compare:CC
15290 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
15291 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
15292 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
15293 (const_int 0)))
15294 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
15295 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
15296 ""
15297 "#"
15298 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
15299 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15300 (parallel [(set (match_dup 4)
15301 (compare:CC (minus:P (match_dup 3) (match_dup 0))
15302 (const_int 0)))
15303 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
15304 "")
15306 (define_insn "*neg_gtu<mode>"
15307 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15308 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15309 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
15310 ""
15311 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
15312 [(set_attr "type" "two")
15313 (set_attr "length" "8")])
15315 \f
15316 ;; Define both directions of branch and return. If we need a reload
15317 ;; register, we'd rather use CR0 since it is much easier to copy a
15318 ;; register CC value to there.
15320 (define_insn ""
15321 [(set (pc)
15322 (if_then_else (match_operator 1 "branch_comparison_operator"
15323 [(match_operand 2
15324 "cc_reg_operand" "y")
15325 (const_int 0)])
15326 (label_ref (match_operand 0 "" ""))
15327 (pc)))]
15328 ""
15329 "*
15330 {
15331 return output_cbranch (operands[1], \"%l0\", 0, insn);
15332 }"
15333 [(set_attr "type" "branch")])
15335 (define_insn ""
15336 [(set (pc)
15337 (if_then_else (match_operator 0 "branch_comparison_operator"
15338 [(match_operand 1
15339 "cc_reg_operand" "y")
15340 (const_int 0)])
15341 (return)
15342 (pc)))]
15343 "direct_return ()"
15344 "*
15345 {
15346 return output_cbranch (operands[0], NULL, 0, insn);
15347 }"
15348 [(set_attr "type" "jmpreg")
15349 (set_attr "length" "4")])
15351 (define_insn ""
15352 [(set (pc)
15353 (if_then_else (match_operator 1 "branch_comparison_operator"
15354 [(match_operand 2
15355 "cc_reg_operand" "y")
15356 (const_int 0)])
15357 (pc)
15358 (label_ref (match_operand 0 "" ""))))]
15359 ""
15360 "*
15361 {
15362 return output_cbranch (operands[1], \"%l0\", 1, insn);
15363 }"
15364 [(set_attr "type" "branch")])
15366 (define_insn ""
15367 [(set (pc)
15368 (if_then_else (match_operator 0 "branch_comparison_operator"
15369 [(match_operand 1
15370 "cc_reg_operand" "y")
15371 (const_int 0)])
15372 (pc)
15373 (return)))]
15374 "direct_return ()"
15375 "*
15376 {
15377 return output_cbranch (operands[0], NULL, 1, insn);
15378 }"
15379 [(set_attr "type" "jmpreg")
15380 (set_attr "length" "4")])
15382 ;; Logic on condition register values.
15384 ; This pattern matches things like
15385 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
15386 ; (eq:SI (reg:CCFP 68) (const_int 0)))
15387 ; (const_int 1)))
15388 ; which are generated by the branch logic.
15389 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
15391 (define_insn "*cceq_ior_compare"
15392 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15393 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
15394 [(match_operator:SI 2
15395 "branch_positive_comparison_operator"
15396 [(match_operand 3
15397 "cc_reg_operand" "y,y")
15398 (const_int 0)])
15399 (match_operator:SI 4
15400 "branch_positive_comparison_operator"
15401 [(match_operand 5
15402 "cc_reg_operand" "0,y")
15403 (const_int 0)])])
15404 (const_int 1)))]
15405 ""
15406 "cr%q1 %E0,%j2,%j4"
15407 [(set_attr "type" "cr_logical,delayed_cr")])
15409 ; Why is the constant -1 here, but 1 in the previous pattern?
15410 ; Because ~1 has all but the low bit set.
15411 (define_insn ""
15412 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15413 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
15414 [(not:SI (match_operator:SI 2
15415 "branch_positive_comparison_operator"
15416 [(match_operand 3
15417 "cc_reg_operand" "y,y")
15418 (const_int 0)]))
15419 (match_operator:SI 4
15420 "branch_positive_comparison_operator"
15421 [(match_operand 5
15422 "cc_reg_operand" "0,y")
15423 (const_int 0)])])
15424 (const_int -1)))]
15425 ""
15426 "cr%q1 %E0,%j2,%j4"
15427 [(set_attr "type" "cr_logical,delayed_cr")])
15429 (define_insn "*cceq_rev_compare"
15430 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15431 (compare:CCEQ (match_operator:SI 1
15432 "branch_positive_comparison_operator"
15433 [(match_operand 2
15434 "cc_reg_operand" "0,y")
15435 (const_int 0)])
15436 (const_int 0)))]
15437 ""
15438 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
15439 [(set_attr "type" "cr_logical,delayed_cr")])
15441 ;; If we are comparing the result of two comparisons, this can be done
15442 ;; using creqv or crxor.
15444 (define_insn_and_split ""
15445 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
15446 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
15447 [(match_operand 2 "cc_reg_operand" "y")
15448 (const_int 0)])
15449 (match_operator 3 "branch_comparison_operator"
15450 [(match_operand 4 "cc_reg_operand" "y")
15451 (const_int 0)])))]
15452 ""
15453 "#"
15454 ""
15455 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
15456 (match_dup 5)))]
15457 "
15458 {
15459 int positive_1, positive_2;
15461 positive_1 = branch_positive_comparison_operator (operands[1],
15462 GET_MODE (operands[1]));
15463 positive_2 = branch_positive_comparison_operator (operands[3],
15464 GET_MODE (operands[3]));
15466 if (! positive_1)
15467 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
15468 GET_CODE (operands[1])),
15469 SImode,
15470 operands[2], const0_rtx);
15471 else if (GET_MODE (operands[1]) != SImode)
15472 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
15473 operands[2], const0_rtx);
15475 if (! positive_2)
15476 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
15477 GET_CODE (operands[3])),
15478 SImode,
15479 operands[4], const0_rtx);
15480 else if (GET_MODE (operands[3]) != SImode)
15481 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
15482 operands[4], const0_rtx);
15484 if (positive_1 == positive_2)
15485 {
15486 operands[1] = gen_rtx_NOT (SImode, operands[1]);
15487 operands[5] = constm1_rtx;
15488 }
15489 else
15490 {
15491 operands[5] = const1_rtx;
15492 }
15493 }")
15495 ;; Unconditional branch and return.
15497 (define_insn "jump"
15498 [(set (pc)
15499 (label_ref (match_operand 0 "" "")))]
15500 ""
15501 "b %l0"
15502 [(set_attr "type" "branch")])
15504 (define_insn "return"
15505 [(return)]
15506 "direct_return ()"
15507 "{br|blr}"
15508 [(set_attr "type" "jmpreg")])
15510 (define_expand "indirect_jump"
15511 [(set (pc) (match_operand 0 "register_operand" ""))])
15513 (define_insn "*indirect_jump<mode>"
15514 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
15515 ""
15516 "@
15517 bctr
15518 {br|blr}"
15519 [(set_attr "type" "jmpreg")])
15521 ;; Table jump for switch statements:
15522 (define_expand "tablejump"
15523 [(use (match_operand 0 "" ""))
15524 (use (label_ref (match_operand 1 "" "")))]
15525 ""
15526 "
15527 {
15528 if (TARGET_32BIT)
15529 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
15530 else
15531 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
15532 DONE;
15533 }")
15535 (define_expand "tablejumpsi"
15536 [(set (match_dup 3)
15537 (plus:SI (match_operand:SI 0 "" "")
15538 (match_dup 2)))
15539 (parallel [(set (pc) (match_dup 3))
15540 (use (label_ref (match_operand 1 "" "")))])]
15541 "TARGET_32BIT"
15542 "
15543 { operands[0] = force_reg (SImode, operands[0]);
15544 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
15545 operands[3] = gen_reg_rtx (SImode);
15546 }")
15548 (define_expand "tablejumpdi"
15549 [(set (match_dup 4)
15550 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
15551 (set (match_dup 3)
15552 (plus:DI (match_dup 4)
15553 (match_dup 2)))
15554 (parallel [(set (pc) (match_dup 3))
15555 (use (label_ref (match_operand 1 "" "")))])]
15556 "TARGET_64BIT"
15557 "
15558 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
15559 operands[3] = gen_reg_rtx (DImode);
15560 operands[4] = gen_reg_rtx (DImode);
15561 }")
15563 (define_insn "*tablejump<mode>_internal1"
15564 [(set (pc)
15565 (match_operand:P 0 "register_operand" "c,*l"))
15566 (use (label_ref (match_operand 1 "" "")))]
15567 ""
15568 "@
15569 bctr
15570 {br|blr}"
15571 [(set_attr "type" "jmpreg")])
15573 (define_insn "nop"
15574 [(const_int 0)]
15575 ""
15576 "{cror 0,0,0|nop}")
15577 \f
15578 ;; Define the subtract-one-and-jump insns, starting with the template
15579 ;; so loop.c knows what to generate.
15581 (define_expand "doloop_end"
15582 [(use (match_operand 0 "" "")) ; loop pseudo
15583 (use (match_operand 1 "" "")) ; iterations; zero if unknown
15584 (use (match_operand 2 "" "")) ; max iterations
15585 (use (match_operand 3 "" "")) ; loop level
15586 (use (match_operand 4 "" ""))] ; label
15587 ""
15588 "
15589 {
15590 /* Only use this on innermost loops. */
15591 if (INTVAL (operands[3]) > 1)
15592 FAIL;
15593 if (TARGET_64BIT)
15594 {
15595 if (GET_MODE (operands[0]) != DImode)
15596 FAIL;
15597 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
15598 }
15599 else
15600 {
15601 if (GET_MODE (operands[0]) != SImode)
15602 FAIL;
15603 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
15604 }
15605 DONE;
15606 }")
15608 (define_expand "ctr<mode>"
15609 [(parallel [(set (pc)
15610 (if_then_else (ne (match_operand:P 0 "register_operand" "")
15611 (const_int 1))
15612 (label_ref (match_operand 1 "" ""))
15613 (pc)))
15614 (set (match_dup 0)
15615 (plus:P (match_dup 0)
15616 (const_int -1)))
15617 (clobber (match_scratch:CC 2 ""))
15618 (clobber (match_scratch:P 3 ""))])]
15619 ""
15620 "")
15622 ;; We need to be able to do this for any operand, including MEM, or we
15623 ;; will cause reload to blow up since we don't allow output reloads on
15624 ;; JUMP_INSNs.
15625 ;; For the length attribute to be calculated correctly, the
15626 ;; label MUST be operand 0.
15628 (define_insn "*ctr<mode>_internal1"
15629 [(set (pc)
15630 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15631 (const_int 1))
15632 (label_ref (match_operand 0 "" ""))
15633 (pc)))
15634 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15635 (plus:P (match_dup 1)
15636 (const_int -1)))
15637 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15638 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15639 ""
15640 "*
15641 {
15642 if (which_alternative != 0)
15643 return \"#\";
15644 else if (get_attr_length (insn) == 4)
15645 return \"{bdn|bdnz} %l0\";
15646 else
15647 return \"bdz $+8\;b %l0\";
15648 }"
15649 [(set_attr "type" "branch")
15650 (set_attr "length" "*,12,16,16")])
15652 (define_insn "*ctr<mode>_internal2"
15653 [(set (pc)
15654 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15655 (const_int 1))
15656 (pc)
15657 (label_ref (match_operand 0 "" ""))))
15658 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15659 (plus:P (match_dup 1)
15660 (const_int -1)))
15661 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15662 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15663 ""
15664 "*
15665 {
15666 if (which_alternative != 0)
15667 return \"#\";
15668 else if (get_attr_length (insn) == 4)
15669 return \"bdz %l0\";
15670 else
15671 return \"{bdn|bdnz} $+8\;b %l0\";
15672 }"
15673 [(set_attr "type" "branch")
15674 (set_attr "length" "*,12,16,16")])
15676 ;; Similar but use EQ
15678 (define_insn "*ctr<mode>_internal5"
15679 [(set (pc)
15680 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15681 (const_int 1))
15682 (label_ref (match_operand 0 "" ""))
15683 (pc)))
15684 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15685 (plus:P (match_dup 1)
15686 (const_int -1)))
15687 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15688 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15689 ""
15690 "*
15691 {
15692 if (which_alternative != 0)
15693 return \"#\";
15694 else if (get_attr_length (insn) == 4)
15695 return \"bdz %l0\";
15696 else
15697 return \"{bdn|bdnz} $+8\;b %l0\";
15698 }"
15699 [(set_attr "type" "branch")
15700 (set_attr "length" "*,12,16,16")])
15702 (define_insn "*ctr<mode>_internal6"
15703 [(set (pc)
15704 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15705 (const_int 1))
15706 (pc)
15707 (label_ref (match_operand 0 "" ""))))
15708 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15709 (plus:P (match_dup 1)
15710 (const_int -1)))
15711 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15712 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15713 ""
15714 "*
15715 {
15716 if (which_alternative != 0)
15717 return \"#\";
15718 else if (get_attr_length (insn) == 4)
15719 return \"{bdn|bdnz} %l0\";
15720 else
15721 return \"bdz $+8\;b %l0\";
15722 }"
15723 [(set_attr "type" "branch")
15724 (set_attr "length" "*,12,16,16")])
15726 ;; Now the splitters if we could not allocate the CTR register
15728 (define_split
15729 [(set (pc)
15730 (if_then_else (match_operator 2 "comparison_operator"
15731 [(match_operand:P 1 "gpc_reg_operand" "")
15732 (const_int 1)])
15733 (match_operand 5 "" "")
15734 (match_operand 6 "" "")))
15735 (set (match_operand:P 0 "gpc_reg_operand" "")
15736 (plus:P (match_dup 1) (const_int -1)))
15737 (clobber (match_scratch:CC 3 ""))
15738 (clobber (match_scratch:P 4 ""))]
15739 "reload_completed"
15740 [(parallel [(set (match_dup 3)
15741 (compare:CC (plus:P (match_dup 1)
15742 (const_int -1))
15743 (const_int 0)))
15744 (set (match_dup 0)
15745 (plus:P (match_dup 1)
15746 (const_int -1)))])
15747 (set (pc) (if_then_else (match_dup 7)
15748 (match_dup 5)
15749 (match_dup 6)))]
15750 "
15751 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15752 operands[3], const0_rtx); }")
15754 (define_split
15755 [(set (pc)
15756 (if_then_else (match_operator 2 "comparison_operator"
15757 [(match_operand:P 1 "gpc_reg_operand" "")
15758 (const_int 1)])
15759 (match_operand 5 "" "")
15760 (match_operand 6 "" "")))
15761 (set (match_operand:P 0 "nonimmediate_operand" "")
15762 (plus:P (match_dup 1) (const_int -1)))
15763 (clobber (match_scratch:CC 3 ""))
15764 (clobber (match_scratch:P 4 ""))]
15765 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15766 [(parallel [(set (match_dup 3)
15767 (compare:CC (plus:P (match_dup 1)
15768 (const_int -1))
15769 (const_int 0)))
15770 (set (match_dup 4)
15771 (plus:P (match_dup 1)
15772 (const_int -1)))])
15773 (set (match_dup 0)
15774 (match_dup 4))
15775 (set (pc) (if_then_else (match_dup 7)
15776 (match_dup 5)
15777 (match_dup 6)))]
15778 "
15779 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15780 operands[3], const0_rtx); }")
15781 \f
15782 (define_insn "trap"
15783 [(trap_if (const_int 1) (const_int 0))]
15784 ""
15785 "{t 31,0,0|trap}"
15786 [(set_attr "type" "trap")])
15788 (define_expand "ctrap<mode>4"
15789 [(trap_if (match_operator 0 "ordered_comparison_operator"
15790 [(match_operand:GPR 1 "register_operand")
15791 (match_operand:GPR 2 "reg_or_short_operand")])
15792 (match_operand 3 "zero_constant" ""))]
15793 ""
15794 "")
15796 (define_insn ""
15797 [(trap_if (match_operator 0 "ordered_comparison_operator"
15798 [(match_operand:GPR 1 "register_operand" "r")
15799 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15800 (const_int 0))]
15801 ""
15802 "{t|t<wd>}%V0%I2 %1,%2"
15803 [(set_attr "type" "trap")])
15804 \f
15805 ;; Insns related to generating the function prologue and epilogue.
15807 (define_expand "prologue"
15808 [(use (const_int 0))]
15809 "TARGET_SCHED_PROLOG"
15810 "
15811 {
15812 rs6000_emit_prologue ();
15813 DONE;
15814 }")
15816 (define_insn "*movesi_from_cr_one"
15817 [(match_parallel 0 "mfcr_operation"
15818 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15819 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15820 (match_operand 3 "immediate_operand" "n")]
15821 UNSPEC_MOVESI_FROM_CR))])]
15822 "TARGET_MFCRF"
15823 "*
15824 {
15825 int mask = 0;
15826 int i;
15827 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15828 {
15829 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15830 operands[4] = GEN_INT (mask);
15831 output_asm_insn (\"mfcr %1,%4\", operands);
15832 }
15833 return \"\";
15834 }"
15835 [(set_attr "type" "mfcrf")])
15837 (define_insn "movesi_from_cr"
15838 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15839 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15840 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15841 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15842 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15843 UNSPEC_MOVESI_FROM_CR))]
15844 ""
15845 "mfcr %0"
15846 [(set_attr "type" "mfcr")])
15848 (define_insn "*stmw"
15849 [(match_parallel 0 "stmw_operation"
15850 [(set (match_operand:SI 1 "memory_operand" "=m")
15851 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15852 "TARGET_MULTIPLE"
15853 "{stm|stmw} %2,%1"
15854 [(set_attr "type" "store_ux")])
15856 (define_insn "*save_gpregs_<mode>"
15857 [(match_parallel 0 "any_parallel_operand"
15858 [(clobber (reg:P 65))
15859 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15860 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15861 (set (match_operand:P 3 "memory_operand" "=m")
15862 (match_operand:P 4 "gpc_reg_operand" "r"))])]
15863 ""
15864 "bl %1"
15865 [(set_attr "type" "branch")
15866 (set_attr "length" "4")])
15868 (define_insn "*save_fpregs_<mode>"
15869 [(match_parallel 0 "any_parallel_operand"
15870 [(clobber (reg:P 65))
15871 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15872 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15873 (set (match_operand:DF 3 "memory_operand" "=m")
15874 (match_operand:DF 4 "gpc_reg_operand" "d"))])]
15875 ""
15876 "bl %1"
15877 [(set_attr "type" "branch")
15878 (set_attr "length" "4")])
15880 ; These are to explain that changes to the stack pointer should
15881 ; not be moved over stores to stack memory.
15882 (define_insn "stack_tie"
15883 [(set (match_operand:BLK 0 "memory_operand" "+m")
15884 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
15885 ""
15886 ""
15887 [(set_attr "length" "0")])
15889 ; Like stack_tie, but depend on both fp and sp based memory.
15890 (define_insn "frame_tie"
15891 [(set (match_operand:BLK 0 "memory_operand" "+m")
15892 (unspec:BLK [(match_dup 0)
15893 (match_operand:BLK 1 "memory_operand" "m")] UNSPEC_TIE))]
15894 ""
15895 ""
15896 [(set_attr "length" "0")])
15899 (define_expand "epilogue"
15900 [(use (const_int 0))]
15901 "TARGET_SCHED_PROLOG"
15902 "
15903 {
15904 rs6000_emit_epilogue (FALSE);
15905 DONE;
15906 }")
15908 ; On some processors, doing the mtcrf one CC register at a time is
15909 ; faster (like on the 604e). On others, doing them all at once is
15910 ; faster; for instance, on the 601 and 750.
15912 (define_expand "movsi_to_cr_one"
15913 [(set (match_operand:CC 0 "cc_reg_operand" "")
15914 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15915 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15916 ""
15917 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15919 (define_insn "*movsi_to_cr"
15920 [(match_parallel 0 "mtcrf_operation"
15921 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15922 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15923 (match_operand 3 "immediate_operand" "n")]
15924 UNSPEC_MOVESI_TO_CR))])]
15925 ""
15926 "*
15927 {
15928 int mask = 0;
15929 int i;
15930 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15931 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15932 operands[4] = GEN_INT (mask);
15933 return \"mtcrf %4,%2\";
15934 }"
15935 [(set_attr "type" "mtcr")])
15937 (define_insn "*mtcrfsi"
15938 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15939 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15940 (match_operand 2 "immediate_operand" "n")]
15941 UNSPEC_MOVESI_TO_CR))]
15942 "GET_CODE (operands[0]) == REG
15943 && CR_REGNO_P (REGNO (operands[0]))
15944 && GET_CODE (operands[2]) == CONST_INT
15945 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15946 "mtcrf %R0,%1"
15947 [(set_attr "type" "mtcr")])
15949 ; The load-multiple instructions have similar properties.
15950 ; Note that "load_multiple" is a name known to the machine-independent
15951 ; code that actually corresponds to the PowerPC load-string.
15953 (define_insn "*lmw"
15954 [(match_parallel 0 "lmw_operation"
15955 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15956 (match_operand:SI 2 "memory_operand" "m"))])]
15957 "TARGET_MULTIPLE"
15958 "{lm|lmw} %1,%2"
15959 [(set_attr "type" "load_ux")
15960 (set_attr "cell_micro" "always")])
15962 (define_insn "*return_internal_<mode>"
15963 [(return)
15964 (use (match_operand:P 0 "register_operand" "lc"))]
15965 ""
15966 "b%T0"
15967 [(set_attr "type" "jmpreg")])
15969 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
15970 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
15972 (define_insn "*restore_gpregs_<mode>"
15973 [(match_parallel 0 "any_parallel_operand"
15974 [(clobber (match_operand:P 1 "register_operand" "=l"))
15975 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15976 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15977 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15978 (match_operand:P 5 "memory_operand" "m"))])]
15979 ""
15980 "bl %2"
15981 [(set_attr "type" "branch")
15982 (set_attr "length" "4")])
15984 (define_insn "*return_and_restore_gpregs_<mode>"
15985 [(match_parallel 0 "any_parallel_operand"
15986 [(return)
15987 (clobber (match_operand:P 1 "register_operand" "=l"))
15988 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15989 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15990 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15991 (match_operand:P 5 "memory_operand" "m"))])]
15992 ""
15993 "b %2"
15994 [(set_attr "type" "branch")
15995 (set_attr "length" "4")])
15997 (define_insn "*return_and_restore_fpregs_<mode>"
15998 [(match_parallel 0 "any_parallel_operand"
15999 [(return)
16000 (clobber (match_operand:P 1 "register_operand" "=l"))
16001 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16002 (use (match_operand:P 3 "gpc_reg_operand" "r"))
16003 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
16004 (match_operand:DF 5 "memory_operand" "m"))])]
16005 ""
16006 "b %2"
16007 [(set_attr "type" "branch")
16008 (set_attr "length" "4")])
16010 (define_insn "*return_and_restore_fpregs_aix_<mode>"
16011 [(match_parallel 0 "any_parallel_operand"
16012 [(return)
16013 (use (match_operand:P 1 "register_operand" "l"))
16014 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16015 (use (match_operand:P 3 "gpc_reg_operand" "r"))
16016 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
16017 (match_operand:DF 5 "memory_operand" "m"))])]
16018 ""
16019 "b %2"
16020 [(set_attr "type" "branch")
16021 (set_attr "length" "4")])
16023 ; This is used in compiling the unwind routines.
16024 (define_expand "eh_return"
16025 [(use (match_operand 0 "general_operand" ""))]
16026 ""
16027 "
16028 {
16029 if (TARGET_32BIT)
16030 emit_insn (gen_eh_set_lr_si (operands[0]));
16031 else
16032 emit_insn (gen_eh_set_lr_di (operands[0]));
16033 DONE;
16034 }")
16036 ; We can't expand this before we know where the link register is stored.
16037 (define_insn "eh_set_lr_<mode>"
16038 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
16039 UNSPECV_EH_RR)
16040 (clobber (match_scratch:P 1 "=&b"))]
16041 ""
16042 "#")
16044 (define_split
16045 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
16046 (clobber (match_scratch 1 ""))]
16047 "reload_completed"
16048 [(const_int 0)]
16049 "
16050 {
16051 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
16052 DONE;
16053 }")
16055 (define_insn "prefetch"
16056 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
16057 (match_operand:SI 1 "const_int_operand" "n")
16058 (match_operand:SI 2 "const_int_operand" "n"))]
16059 "TARGET_POWERPC"
16060 "*
16061 {
16062 if (GET_CODE (operands[0]) == REG)
16063 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
16064 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
16065 }"
16066 [(set_attr "type" "load")])
16067 \f
16068 (define_insn "bpermd_<mode>"
16069 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
16070 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
16071 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
16072 "TARGET_POPCNTD"
16073 "bpermd %0,%1,%2"
16074 [(set_attr "type" "integer")])
16076 \f
16078 (include "sync.md")
16079 (include "vector.md")
16080 (include "vsx.md")
16081 (include "altivec.md")
16082 (include "spe.md")
16083 (include "dfp.md")
16084 (include "paired.md")