1 /* Subroutines used for code generation on picoChip processors.
2 Copyright (C) 2001, 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by picoChip Designs Ltd. (http://www.picochip.com)
4 Maintained by Daniel Towner (daniel.towner@picochip.com) and
5 Hariharan Sandanagobalane (hariharan@picochip.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not, see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
42 #include "basic-block.h"
43 #include "integrate.h"
44 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "langhooks.h"
55 #include "picochip-protos.h"
57 #include "insn-attr.h" /* For DFA state_t. */
58 #include "insn-config.h" /* Required by recog.h */
59 #include "insn-codes.h" /* For CODE_FOR_? */
60 #include "optabs.h" /* For GEN_FCN */
61 #include "basic-block.h" /* UPDATE_LIFE_GLOBAL* for picochip_reorg. */
62 #include "timevar.h" /* For TV_SCHED2, in picochip_reorg. */
63 #include "libfuncs.h" /* For memcpy_libfuncs, etc. */
64 #include "df.h" /* For df_regs_ever_live_df_regs_ever_live_pp, etc. */
67 /* Target AE ISA information. */
68 enum picochip_dfa_type picochip_schedule_type
;
70 bool picochip_has_mul_unit
= false;
71 bool picochip_has_mac_unit
= false;
73 /* targetm hook function prototypes. */
75 void picochip_asm_file_start (void);
76 void picochip_asm_file_end (void);
78 void picochip_init_libfuncs (void);
79 void picochip_reorg (void);
81 int picochip_arg_partial_bytes (CUMULATIVE_ARGS
* p_cum
,
82 enum machine_mode mode
,
83 tree type
, bool named
);
85 int picochip_sched_lookahead (void);
86 int picochip_sched_issue_rate (void);
87 int picochip_sched_adjust_cost (rtx insn
, rtx link
,
88 rtx dep_insn
, int cost
);
89 int picochip_sched_reorder (FILE * file
, int verbose
, rtx
* ready
,
90 int *n_readyp
, int clock
);
92 void picochip_init_builtins (void);
93 rtx
picochip_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
95 bool picochip_rtx_costs (rtx x
, int code
, int outer_code
, int* total
, bool speed
);
96 bool picochip_return_in_memory(const_tree type
,
97 const_tree fntype ATTRIBUTE_UNUSED
);
98 bool picochip_legitimate_address_p (enum machine_mode
, rtx
, bool);
99 rtx
picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
100 enum machine_mode mode
);
101 int picochip_legitimize_reload_address (rtx
*x
, enum machine_mode mode
,
102 int opnum
, int type
, int ind_levels
);
104 rtx
picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED
, int incoming ATTRIBUTE_UNUSED
);
105 rtx
picochip_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
106 bool outgoing ATTRIBUTE_UNUSED
);
108 picochip_secondary_reload (bool in_p
,
109 rtx x ATTRIBUTE_UNUSED
,
110 reg_class_t cla ATTRIBUTE_UNUSED
,
111 enum machine_mode mode
,
112 secondary_reload_info
*sri
);
114 picochip_asm_named_section (const char *name
,
115 unsigned int flags ATTRIBUTE_UNUSED
,
116 tree decl ATTRIBUTE_UNUSED
);
118 static rtx
picochip_static_chain (const_tree
, bool);
120 static void picochip_option_override (void);
122 /* Lookup table mapping a register number to the earliest containing
123 class. Used by REGNO_REG_CLASS. */
124 const enum reg_class picochip_regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
126 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
127 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
128 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
129 GR_REGS
, FRAME_REGS
, PTR_REGS
, CONST_REGS
,
130 ACC_REGS
, CC_REGS
, GR_REGS
, GR_REGS
133 /* picoChip register names. */
134 const char *picochip_regnames
[] = REGISTER_NAMES
;
136 /* Define the maximum number of registers which may be used to pass
137 * parameters to functions. */
138 #define MAX_CALL_PARAMETER_REGS 6
141 /* Target scheduling information. */
143 /* Determine whether we run our final scheduling pass or not. We always
144 avoid the normal second scheduling pass. */
145 int picochip_flag_schedule_insns2
;
147 /* Check if variable tracking needs to be run. */
148 int picochip_flag_var_tracking
;
150 /* This flag indicates whether the next instruction to be output is a
151 VLIW continuation instruction. It is used to communicate between
152 final_prescan_insn and asm_output_opcode. */
153 static int picochip_vliw_continuation
= 0;
155 /* This variable is used to communicate the current instruction
156 between final_prescan_insn and functions such as asm_output_opcode,
157 and picochip_get_vliw_alu_id (which are otherwise unable to determine the
158 current instruction. */
159 static rtx picochip_current_prescan_insn
;
161 static bool picochip_is_delay_slot_pending
= 0;
163 /* When final_prescan_insn is called, it computes information about
164 the current VLIW packet, and stores it in this structure. When
165 instructions are output, this state is used to make sure that the
166 instructions are output in the correct way (e.g., which ALU to use,
167 whether a macro branch was ever previously a real branch, etc.). */
170 int contains_pico_alu_insn
;
171 int contains_non_cc_alu_insn
;
172 int num_alu_insns_so_far
;
174 /* Record how many instructions are contained in the packet. */
175 int num_insns_in_packet
;
177 /* There was a case for this to be more than 1 */
178 int num_cfi_labels_deferred
;
179 char cfi_label_name
[2][256]; /* Used to record the name of a CFI label
180 emitted inside a VLIW packet. */
181 char lm_label_name
[256]; /* Used to record the name of an LM label. */
184 struct vliw_state picochip_current_vliw_state
;
186 /* Save/restore recog_data. */
187 static int picochip_saved_which_alternative
;
188 static struct recog_data picochip_saved_recog_data
;
190 /* Determine which ALU to use for the instruction in
191 picochip_current_prescan_insn. */
192 static char picochip_get_vliw_alu_id (void);
194 /* Initialize the GCC target structure. */
196 #undef TARGET_ASM_FUNCTION_PROLOGUE
197 #define TARGET_ASM_FUNCTION_PROLOGUE picochip_function_prologue
199 #undef TARGET_ASM_FUNCTION_EPILOGUE
200 #define TARGET_ASM_FUNCTION_EPILOGUE picochip_function_epilogue
202 #undef TARGET_ASM_INTERNAL_LABEL
203 #define TARGET_ASM_INTERNAL_LABEL picochip_output_internal_label
205 #undef TARGET_ASM_GLOBALIZE_LABEL
206 #define TARGET_ASM_GLOBALIZE_LABEL picochip_output_global
208 #undef TARGET_ASM_BYTE_OP
209 #define TARGET_ASM_BYTE_OP ".initByte "
210 #undef TARGET_ASM_ALIGNED_HI_OP
211 #define TARGET_ASM_ALIGNED_HI_OP ".initWord "
212 #undef TARGET_ASM_UNALIGNED_HI_OP
213 #define TARGET_ASM_UNALIGNED_HI_OP ".unalignedInitWord "
214 #undef TARGET_ASM_ALIGNED_SI_OP
215 #define TARGET_ASM_ALIGNED_SI_OP ".initLong "
216 #undef TARGET_ASM_UNALIGNED_SI_OP
217 #define TARGET_ASM_UNALIGNED_SI_OP ".unalignedInitLong "
219 #undef TARGET_INIT_BUILTINS
220 #define TARGET_INIT_BUILTINS picochip_init_builtins
222 #undef TARGET_EXPAND_BUILTIN
223 #define TARGET_EXPAND_BUILTIN picochip_expand_builtin
225 #undef TARGET_RTX_COSTS
226 #define TARGET_RTX_COSTS picochip_rtx_costs
228 #undef TARGET_SCHED_ISSUE_RATE
229 #define TARGET_SCHED_ISSUE_RATE picochip_sched_issue_rate
231 #undef TARGET_SCHED_REORDER
232 #define TARGET_SCHED_REORDER picochip_sched_reorder
234 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
235 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
236 picochip_sched_lookahead
238 #undef TARGET_SCHED_ADJUST_COST
239 #define TARGET_SCHED_ADJUST_COST picochip_sched_adjust_cost
241 #undef TARGET_ASM_NAMED_SECTION
242 #define TARGET_ASM_NAMED_SECTION picochip_asm_named_section
244 #undef TARGET_HAVE_NAMED_SECTIONS
245 #define TARGET_HAVE_NAMED_SECTIONS 1
247 #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
248 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS 1
250 #undef TARGET_INIT_LIBFUNCS
251 #define TARGET_INIT_LIBFUNCS picochip_init_libfuncs
253 #undef TARGET_ASM_FILE_START
254 #define TARGET_ASM_FILE_START picochip_asm_file_start
256 #undef TARGET_ASM_FILE_END
257 #define TARGET_ASM_FILE_END picochip_asm_file_end
259 #undef TARGET_MACHINE_DEPENDENT_REORG
260 #define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg
262 #undef TARGET_ARG_PARTIAL_BYTES
263 #define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes
265 #undef TARGET_PROMOTE_FUNCTION_MODE
266 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
267 #undef TARGET_PROMOTE_PROTOTYPES
268 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
270 /* Target support for Anchored Addresses optimization */
271 #undef TARGET_MIN_ANCHOR_OFFSET
272 #define TARGET_MIN_ANCHOR_OFFSET 0
273 #undef TARGET_MAX_ANCHOR_OFFSET
274 #define TARGET_MAX_ANCHOR_OFFSET 7
275 #undef TARGET_ASM_OUTPUT_ANCHOR
276 #define TARGET_ASM_OUTPUT_ANCHOR picochip_asm_output_anchor
278 #undef TARGET_FUNCTION_VALUE
279 #define TARGET_FUNCTION_VALUE picochip_function_value
281 #undef TARGET_LIBGCC_CMP_RETURN_MODE
282 #define TARGET_LIBGCC_CMP_RETURN_MODE picochip_libgcc_cmp_return_mode
285 #undef TARGET_LEGITIMATE_ADDRESS_P
286 #define TARGET_LEGITIMATE_ADDRESS_P picochip_legitimate_address_p
288 #undef TARGET_LEGITIMIZE_ADDRESS
289 #define TARGET_LEGITIMIZE_ADDRESS picochip_legitimize_address
291 /* Loading and storing QImode values to and from memory
292 usually requires a scratch register. */
293 #undef TARGET_SECONDARY_RELOAD
294 #define TARGET_SECONDARY_RELOAD picochip_secondary_reload
295 #undef DONT_USE_BUILTIN_SETJMP
296 #define DONT_USE_BUILTIN_SETJMP 1
298 /* How Large Values are Returned */
300 #undef TARGET_RETURN_IN_MEMORY
301 #define TARGET_RETURN_IN_MEMORY picochip_return_in_memory
303 #undef TARGET_STATIC_CHAIN
304 #define TARGET_STATIC_CHAIN picochip_static_chain
306 #undef TARGET_OPTION_OVERRIDE
307 #define TARGET_OPTION_OVERRIDE picochip_option_override
309 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
310 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE picochip_option_override
312 struct gcc_target targetm
= TARGET_INITIALIZER
;
315 /* Only return a value in memory if it is greater than 4 bytes.
316 int_size_in_bytes returns -1 for variable size objects, which go in
317 memory always. The cast to unsigned makes -1 > 8. */
320 picochip_return_in_memory(const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
322 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 4);
325 /* Allow some options to be overriden. In particular, the 2nd
326 scheduling pass option is switched off, and a machine dependent
327 reorganisation ensures that it is run later on, after the second
328 jump optimisation. */
331 picochip_option_override (void)
333 /* If we are optimizing for stack, dont let inliner to inline functions
334 that could potentially increase stack size.*/
335 if (flag_conserve_stack
)
337 PARAM_VALUE (PARAM_LARGE_STACK_FRAME
) = 0;
338 PARAM_VALUE (PARAM_STACK_FRAME_GROWTH
) = 0;
341 /* Turn off the elimination of unused types. The elaborator
342 generates various interesting types to represent constants,
343 generics, and so on, and it is useful to retain this information
344 in the debug output. The increased size of the debug information
345 is not really an issue for us. */
346 flag_eliminate_unused_debug_types
= 0;
348 /* Even if the user specifies a -fno-omit-frame-pointer on the
349 command line, we still want to go ahead and omit frame pointer
350 usages, since we dont really have a frame pointer register.
351 So, all accesses to FP need to be converted to accesses off
353 flag_omit_frame_pointer
= 1;
355 /* Turning on anchored addresses by default. This is an optimization
356 that could decrease the code size by placing anchors in data and
357 accessing offsets from the anchor for file local data variables.*/
359 flag_section_anchors
= 1;
361 /* Turn off the second scheduling pass, and move it to
362 picochip_reorg, to avoid having the second jump optimisation
363 trash the instruction modes (e.g., instructions are changed to
364 TImode to mark the beginning of cycles). Two types of DFA
365 scheduling are possible: space and speed. In both cases,
366 instructions are reordered to avoid stalls (e.g., memory loads
367 stall for one cycle). Speed scheduling will also enable VLIW
368 instruction packing. VLIW instructions use more code space, so
369 VLIW scheduling is disabled when scheduling for size. */
370 picochip_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
371 flag_schedule_insns_after_reload
= 0;
372 if (picochip_flag_schedule_insns2
)
375 picochip_schedule_type
= DFA_TYPE_SPACE
;
378 picochip_schedule_type
= DFA_TYPE_SPEED
;
379 flag_delayed_branch
= 0;
383 picochip_schedule_type
= DFA_TYPE_NONE
;
385 /* Ensure that the debug level is always at least -g2. The flow
386 analyser works at its best if it always has debug
387 information. DWARF is non-intrusive, so it makes no difference to
388 code quality if debug is always enabled. */
389 if (debug_info_level
< DINFO_LEVEL_NORMAL
)
391 debug_info_level
= DINFO_LEVEL_NORMAL
;
392 write_symbols
= DWARF2_DEBUG
;
395 /* Options of the form -mae=mac, and so on will be substituted by
396 the compiler driver for the appropriate byte access and multiply
397 unit ISA options. Any unrecognised AE types will end up being
398 passed to the compiler, which should reject them as invalid. */
399 if (picochip_ae_type_string
!= NULL
)
400 error ("invalid AE type specified (%s)\n", picochip_ae_type_string
);
402 /* Override any specific capabilities of the instruction set. These
403 take precedence over any capabilities inferred from the AE type,
404 regardless of where the options appear on the command line. */
405 if (picochip_mul_type_string
== NULL
)
407 /* Default to MEM-type multiply, for historical compatibility. */
408 picochip_has_mac_unit
= false;
409 picochip_has_mul_unit
= true;
413 picochip_has_mac_unit
= false;
414 picochip_has_mul_unit
= false;
416 if (strcmp (picochip_mul_type_string
, "mul") == 0)
417 picochip_has_mul_unit
= true;
418 else if (strcmp (picochip_mul_type_string
, "mac") == 0)
419 picochip_has_mac_unit
= true;
420 else if (strcmp (picochip_mul_type_string
, "none") == 0)
421 { /* Do nothing. Unit types already set to false. */ }
423 error ("Invalid mul type specified (%s) - expected mac, mul or none",
424 picochip_mul_type_string
);
430 /* Initialise the library functions to handle arithmetic on some of
433 picochip_init_libfuncs (void)
436 set_optab_libfunc (ashr_optab
, DImode
, "__ashrdi3");
437 set_optab_libfunc (ashl_optab
, DImode
, "__ashldi3");
438 set_optab_libfunc (lshr_optab
, DImode
, "__lshrdi3");
440 /* 64-bit signed multiplication. */
441 set_optab_libfunc (smul_optab
, DImode
, "__muldi3");
443 /* Signed division */
444 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
445 set_optab_libfunc (sdiv_optab
, DImode
, "__divdi3");
448 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
449 set_optab_libfunc (smod_optab
, DImode
, "__moddi3");
451 /* 32-bit count leading Zeros*/
452 set_optab_libfunc (clz_optab
, SImode
, "_clzsi2");
454 /* 64-bit comparison */
455 set_optab_libfunc (ucmp_optab
, DImode
, "__ucmpdi2");
456 set_optab_libfunc (cmp_optab
, DImode
, "__cmpdi2");
458 /* 64-bit addition and subtraction*/
459 set_optab_libfunc (add_optab
, DImode
, "_adddi3");
460 set_optab_libfunc (sub_optab
, DImode
, "_subdi3");
463 /* Memcpy function */
465 picochip_expand_movmemhi (rtx
*operands
)
467 rtx src_addr_reg
, dst_addr_reg
, count_reg
, src_mem
, dst_mem
, tmp_reg
;
470 src_addr_reg
= gen_reg_rtx(HImode
);
471 dst_addr_reg
= gen_reg_rtx(HImode
);
472 count_reg
= gen_reg_rtx(HImode
);
473 emit_insn (gen_movhi (count_reg
, operands
[2]));
474 emit_insn (gen_movqi (src_addr_reg
, XEXP(operands
[1], 0)));
475 emit_insn (gen_movqi (dst_addr_reg
, XEXP(operands
[0], 0)));
476 gcc_assert (GET_CODE(count_reg
) == REG
);
477 start_label
= gen_label_rtx ();
478 emit_label (start_label
);
480 /* We can specialise the code for different alignments */
481 align
= INTVAL(operands
[3]);
482 size
= INTVAL(operands
[2]);
483 gcc_assert(align
>= 0 && size
>= 0);
486 if (size
% 4 == 0 && align
% 4 == 0)
488 src_mem
= gen_rtx_MEM(SImode
, src_addr_reg
);
489 dst_mem
= gen_rtx_MEM(SImode
, dst_addr_reg
);
490 tmp_reg
= gen_reg_rtx(SImode
);
491 emit_insn (gen_movsi (tmp_reg
, src_mem
));
492 emit_insn (gen_movsi (dst_mem
, tmp_reg
));
493 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, GEN_INT(4)));
494 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, GEN_INT(4)));
495 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-4)));
496 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
497 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
499 else if (size
% 2 == 0 && align
% 2 == 0)
501 src_mem
= gen_rtx_MEM(HImode
, src_addr_reg
);
502 dst_mem
= gen_rtx_MEM(HImode
, dst_addr_reg
);
503 tmp_reg
= gen_reg_rtx(HImode
);
504 emit_insn (gen_movhi (tmp_reg
, src_mem
));
505 emit_insn (gen_movhi (dst_mem
, tmp_reg
));
506 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, const2_rtx
));
507 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, const2_rtx
));
508 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-2)));
509 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
510 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
514 src_mem
= gen_rtx_MEM(QImode
, src_addr_reg
);
515 dst_mem
= gen_rtx_MEM(QImode
, dst_addr_reg
);
516 tmp_reg
= gen_reg_rtx(QImode
);
517 emit_insn (gen_movqi (tmp_reg
, src_mem
));
518 emit_insn (gen_movqi (dst_mem
, tmp_reg
));
519 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, const1_rtx
));
520 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, const1_rtx
));
521 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-1)));
522 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
523 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
530 /* Return the register class for letter C. */
532 picochip_reg_class_from_letter (unsigned c
)
550 pico_leaf_reg_alloc_order
[] = LEAF_REG_ALLOC_ORDER
;
552 pico_nonleaf_reg_alloc_order
[] = REG_ALLOC_ORDER
;
555 picochip_order_regs_for_local_alloc (void)
557 /* We change the order for leaf functions alone. We put r12 at
558 the end since using it will prevent us to combine stw/ldws to
559 stl/ldl and it gives no benefit. In non-leaf functions, we
560 would anyway saveup/restore r12, so it makes sense to use it.*/
562 if (leaf_function_p())
564 memcpy ((char *)reg_alloc_order
, (const char *) pico_leaf_reg_alloc_order
,
565 FIRST_PSEUDO_REGISTER
* sizeof (int));
569 memcpy ((char *)reg_alloc_order
, (const char *) pico_nonleaf_reg_alloc_order
,
570 FIRST_PSEUDO_REGISTER
* sizeof (int));
574 /* Check that VALUE (an INT_CST) is ok as a constant of type C. */
576 picochip_const_ok_for_letter_p (unsigned HOST_WIDE_INT value
, unsigned c
)
581 case 'I': /* 4 bits signed. */
582 return value
+ 8 < 16;
583 case 'J': /* 4 bits unsigned. */
585 case 'K': /* 8 bits signed. */
586 return value
+ 128 < 256;
587 case 'M': /* 4-bit magnitude. */
588 return abs (value
) < 16;
589 case 'N': /* 10 bits signed. */
590 return value
+ 512 > 1024;
591 case 'O': /* 16 bits signed. */
592 return value
+ 32768 < 65536;
593 default: /* Unknown letter. */
598 /* Stack utility functions. */
600 picochip_return_addr_rtx(int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
603 return gen_rtx_REG (Pmode
, LINK_REGNUM
);
609 /* Emit a set of parallel register expressions used to store
610 blockmode values to pass to functions. */
612 picochip_emit_register_parallel (int size_in_units
, int offset
)
616 rtx vector
[MAX_CALL_PARAMETER_REGS
];
620 /* Compute the base register, and number of required registers. */
621 base_reg
= offset
/ 2;
622 num_regs
= size_in_units
/ 2;
623 if (size_in_units
% 2 == 1)
626 /* Emit a register for each part of the block mode value to be
627 passed in a register. */
628 for (i
= 0; i
< num_regs
; i
++)
629 vector
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
630 gen_rtx_REG (HImode
, base_reg
+ i
),
632 result
= gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (num_regs
, vector
));
638 /* Emit an instruction to allocate a suitable amount of space on the
639 stack, by decrementing the stack pointer. */
641 picochip_emit_stack_allocate (int adjustment
)
644 rtx stack_pointer_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
646 /* Use an addition of a negative value. */
647 insn
= emit_insn (gen_addhi3 (stack_pointer_reg
, stack_pointer_reg
,
648 GEN_INT (-adjustment
)));
650 /* Make the instruction frame related. Also add an expression note,
651 so that the correct Dwarf information is generated (see documention
652 for RTX_FRAME_RELATED_P for more details). */
653 RTX_FRAME_RELATED_P (insn
) = 1;
655 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
656 gen_rtx_SET (VOIDmode
, stack_pointer_reg
,
657 gen_rtx_PLUS (Pmode
, stack_pointer_reg
,
658 GEN_INT (-adjustment
))),
663 /* Emit an instruction to save a register of the given mode. The
664 offset at which to save the register is given relative to the stack
667 picochip_emit_save_register (rtx reg
, int offset
)
669 rtx stack_pointer
, address
, mem
, insn
;
671 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
673 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
675 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
677 insn
= emit_move_insn (mem
, reg
);
678 RTX_FRAME_RELATED_P (insn
) = 1;
680 /* For modes other than HImode, create a note explaining that
681 multiple registers have been saved. This allows the correct DWARF
682 call frame information to be generated. */
683 switch (GET_MODE (reg
))
686 /* The RTL is sufficient to explain HImode register saves. */
690 /* SImode must be broken down into parallel HImode register saves. */
698 gen_rtx_PLUS (Pmode
, stack_pointer
,
700 gen_rtx_REG (HImode
, REGNO (reg
)));
701 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 0)) = 1;
704 gen_rtx_SET (HImode
, gen_rtx_MEM (HImode
,
709 gen_rtx_REG (HImode
, REGNO (reg
) + 1));
710 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 1)) = 1;
713 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
714 gen_rtx_PARALLEL (VOIDmode
, p
),
722 ("unexpected mode %s encountered in picochip_emit_save_register\n",
723 GET_MODE_NAME (GET_MODE (reg
)));
728 /* Emit an instruction to restore a register of the given mode. The
729 offset from which to restore the register is given relative to the
732 picochip_emit_restore_register (rtx reg
, int offset
)
734 rtx stack_pointer
, address
, mem
, insn
;
736 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
738 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
740 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
742 insn
= emit_move_insn (reg
, mem
);
746 /* Check that the given byte offset is aligned to the given number of
749 picochip_is_aligned (int byte_offset
, int bit_alignment
)
751 int byte_alignment
= bit_alignment
/ BITS_PER_UNIT
;
752 return (byte_offset
% byte_alignment
) == 0;
755 /*****************************************************************************
758 * The following section contains code which controls how the stack is
761 * The stack is laid out as follows (high addresses first):
764 * Pretend arguments (ARG PTR)
768 * Outgoing arguments (SP)
770 * The (constant) offsets of the different areas must be calculated
771 * relative to the stack area immediately below, and aligned
772 * appropriately. For example, the frame offset is computed by
773 * determining the offset of the special register area, adding the
774 * size of the special register area, and then aligning the resulting
775 * offset correctly. In turn, the special register offset is computed
776 * from the general register offset, and so on. This enables the
777 * different offsets to change size and alignment, without requiring
778 * the code for other offset calculations to be rewritten.
780 * The argument pointer, and the frame pointer are eliminated wherever
781 * possible, by replacing them with a constant offset from the stack
782 * pointer. In the rare cases where constant offsets from the stack
783 * pointer cannot be computed, another register will be allocated to
784 * serve as the argument pointer, or the frame pointer.
786 * The save registers are stored at small offsets from the caller, to
787 * enable the more efficient SP-based ISA instructions to be used.
789 ****************************************************************************/
791 /* Compute the size of an argument in units. */
793 picochip_compute_arg_size (tree type
, enum machine_mode mode
)
795 int type_size_in_units
= 0;
798 type_size_in_units
= tree_low_cst (TYPE_SIZE_UNIT (type
), 1);
800 type_size_in_units
= GET_MODE_SIZE (mode
);
802 return type_size_in_units
;
806 /* Determine where the next outgoing arg should be placed. */
808 picochip_function_arg (CUMULATIVE_ARGS cum
, int mode
, tree type
,
809 int named ATTRIBUTE_UNUSED
)
812 int type_align_in_units
= 0;
813 int type_size_in_units
;
815 int offset_overflow
= 0;
817 /* VOIDmode is passed when computing the second argument to a `call'
818 pattern. This can be ignored. */
819 if (mode
== VOIDmode
)
822 /* Compute the alignment and size of the parameter. */
823 type_align_in_units
=
824 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
825 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
827 /* Compute the correct offset (i.e., ensure that the offset meets
828 the alignment requirements). */
829 offset_overflow
= cum
% type_align_in_units
;
830 if (offset_overflow
== 0)
833 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
837 printf ("Function arg:\n");
838 printf (" Type valid: %s\n", (type
? "yes" : "no"));
839 printf (" Cumulative Value: %d\n", cum
);
840 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
841 printf (" Type size: %i units\n", type_size_in_units
);
842 printf (" Alignment: %i units\n", type_align_in_units
);
843 printf (" New offset: %i\n", new_offset
);
847 /* If the new offset is outside the register space, return. */
848 if (new_offset
>= MAX_CALL_PARAMETER_REGS
* 2)
851 /* If the end of the argument is outside the register space, then
852 the argument must overlap the register space. Return the first
853 available register. */
854 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
855 return gen_rtx_REG (HImode
, new_offset
/ 2);
857 /* Create a register of the required mode to hold the parameter. */
858 reg
= new_offset
/ 2;
873 return gen_rtx_REG ((enum machine_mode
) mode
, reg
);
877 /* Empty blockmode values can be passed as arguments (e.g.,
878 * empty structs). These require no registers
879 * whatsoever. Non-empty blockmode values are passed in a set
880 * of parallel registers. */
881 if (type_size_in_units
== 0)
884 return picochip_emit_register_parallel (type_size_in_units
, new_offset
);
889 (0, "Defaulting to stack for %s register creation\n",
890 GET_MODE_NAME (mode
));
898 /* Determine where the next incoming function argument will
899 appear. Normally, this works in exactly the same way as
900 picochip_function_arg, except when the function in question is a
901 varadic function. In this case, the incoming arguments all appear
902 to be passed on the stack (actually, some of the arguments are
903 passed in registers, which are then pushed onto the stack by the
904 function prologue). */
906 picochip_incoming_function_arg (CUMULATIVE_ARGS cum
, int mode
,
907 tree type
, int named
)
913 return picochip_function_arg (cum
, mode
, type
, named
);
917 /* Gives the alignment boundary, in bits, of an argument with the
920 picochip_get_function_arg_boundary (enum machine_mode mode
)
925 align
= STACK_BOUNDARY
;
927 align
= GET_MODE_ALIGNMENT (mode
);
929 if (align
< PARM_BOUNDARY
)
930 align
= PARM_BOUNDARY
;
936 /* Compute partial registers. */
938 picochip_arg_partial_bytes (CUMULATIVE_ARGS
* p_cum
, enum machine_mode mode
,
939 tree type
, bool named ATTRIBUTE_UNUSED
)
941 int type_align_in_units
= 0;
942 int type_size_in_units
;
944 int offset_overflow
= 0;
946 unsigned cum
= *((unsigned *) p_cum
);
948 /* VOIDmode is passed when computing the second argument to a `call'
949 pattern. This can be ignored. */
950 if (mode
== VOIDmode
)
953 /* Compute the alignment and size of the parameter. */
954 type_align_in_units
=
955 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
956 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
958 /* Compute the correct offset (i.e., ensure that the offset meets
959 the alignment requirements). */
960 offset_overflow
= cum
% type_align_in_units
;
961 if (offset_overflow
== 0)
964 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
968 printf ("Partial function arg nregs:\n");
969 printf (" Type valid: %s\n", (type
? "yes" : "no"));
970 printf (" Cumulative Value: %d\n", cum
);
971 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
972 printf (" Type size: %i units\n", type_size_in_units
);
973 printf (" Alignment: %i units\n", type_align_in_units
);
974 printf (" New offset: %i\n", new_offset
);
978 /* If the new offset is outside the register space, return. */
979 if (new_offset
>= (MAX_CALL_PARAMETER_REGS
* 2))
982 /* If the end of the argument is outside the register space, then
983 the argument must overlap the register space. Return the number
984 of bytes which are passed in registers. */
985 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
986 return ((MAX_CALL_PARAMETER_REGS
* 2) - new_offset
);
992 /* Advance the cumulative args counter, returning the new counter. */
994 picochip_arg_advance (const CUMULATIVE_ARGS cum
, int mode
,
995 tree type
, int named ATTRIBUTE_UNUSED
)
997 int type_align_in_units
= 0;
998 int type_size_in_units
;
1000 int offset_overflow
= 0;
1002 /* VOIDmode is passed when computing the second argument to a `call'
1003 pattern. This can be ignored. */
1004 if (mode
== VOIDmode
)
1007 /* Compute the alignment and size of the parameter. */
1008 type_align_in_units
=
1009 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
1010 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
1012 /* Compute the correct offset (i.e., ensure that the offset meets
1013 the alignment requirements). */
1014 offset_overflow
= cum
% type_align_in_units
;
1015 if (offset_overflow
== 0)
1018 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
1020 /* Advance past the last argument. */
1021 new_offset
+= type_size_in_units
;
1027 /* Determine whether a register needs saving/restoring. It does if it
1028 is live in a function, and isn't a call-used register. */
1030 picochip_reg_needs_saving (int reg_num
)
1032 return df_regs_ever_live_p(reg_num
) && !call_used_regs
[reg_num
];
1035 /* Compute and return offset of the main frame. */
1037 picochip_frame_byte_offset (void)
1039 gcc_assert(picochip_is_aligned
1040 (crtl
->outgoing_args_size
, BITS_PER_WORD
));
1042 return crtl
->outgoing_args_size
;
1045 /* Return the size of the main frame. */
1047 picochip_frame_size_in_bytes (void)
1049 int frame_size
= get_frame_size();
1050 int stack_align
= STACK_BOUNDARY
/BITS_PER_UNIT
;
1051 if (!picochip_is_aligned (frame_size
, STACK_BOUNDARY
))
1052 frame_size
= frame_size
+ (stack_align
- frame_size
%stack_align
);
1053 gcc_assert(picochip_is_aligned (frame_size
, STACK_BOUNDARY
));
1057 /* Compute and return the size (in bytes) of the register save/restore
1058 area for the current function. This only includes the general
1059 purpose registers - the special purpose stack pointer and link
1060 registers are not included in this area. */
1062 picochip_save_area_size_in_bytes (void)
1064 int num_regs_to_save
= 0;
1067 /* Read through all the registers, determining which need to be saved. */
1068 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1070 if (picochip_reg_needs_saving (i
))
1071 num_regs_to_save
+= 1;
1074 return num_regs_to_save
* UNITS_PER_WORD
;
1078 /* Compute and return offset of the save area base. */
1080 picochip_save_area_byte_offset (void)
1082 int base_offset
= (picochip_frame_byte_offset () +
1083 picochip_frame_size_in_bytes ());
1085 gcc_assert(picochip_is_aligned (base_offset
, BITS_PER_WORD
));
1091 /* Compute and return offset of the special register save area. This
1092 area can be found immediately above the normal save area. It must
1093 be aligned, to allow the registers to be saved and restored as a
1096 picochip_special_save_area_byte_offset (void)
1098 int byte_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
1099 int offset
= (picochip_save_area_byte_offset () +
1100 picochip_save_area_size_in_bytes ());
1102 if ((offset
% byte_alignment
) != 0)
1103 offset
= ((offset
/ byte_alignment
) + 1) * byte_alignment
;
1109 /* Determine whether the LNK/SP register save/restores can be eliminated. */
1111 picochip_can_eliminate_link_sp_save (void)
1113 /* This deserves some reasoning. The df_regs_ever_live_p call keeps
1114 changing during optimizations phases. So, this function returns different
1115 values when called from initial_elimination_offset and then again when it
1116 is called from prologue/epilogue generation. This means that argument
1117 accesses become wrong. This wouldnt happen only if we were not using the
1118 stack at all. The following conditions ensures that.*/
1120 return (current_function_is_leaf
&&
1121 !df_regs_ever_live_p(LINK_REGNUM
) &&
1122 !df_regs_ever_live_p(STACK_POINTER_REGNUM
) &&
1123 (picochip_special_save_area_byte_offset() == 0) &&
1124 (crtl
->args
.size
== 0) &&
1125 (crtl
->args
.pretend_args_size
== 0));
1128 /* Compute the size of the special reg save area (SP and LNK). If the
1129 SP/LNK registers don't need to be saved, this area can shrink to
1132 picochip_special_save_area_size_in_bytes (void)
1136 if (picochip_can_eliminate_link_sp_save ())
1139 return 2 * UNITS_PER_WORD
;
1142 /* Return the number of pretend arguments. If this function is
1143 varadic, all the incoming arguments are effectively passed on the
1144 stack. If this function has real pretend arguments (caused by a
1145 value being passed partially on the stack and partially in
1146 registers), then return the number of registers used. */
1148 picochip_pretend_arg_area_size (void)
1151 if (crtl
->args
.pretend_args_size
!= 0)
1153 gcc_assert(crtl
->args
.pretend_args_size
% 4 == 0);
1155 return crtl
->args
.pretend_args_size
;
1157 else if (cfun
->stdarg
)
1164 /* Compute and return the offset of the pretend arguments. The pretend
1165 arguments are contiguous with the incoming arguments, and must be
1166 correctly aligned. */
1168 picochip_pretend_arg_area_byte_offset (void)
1170 int base_offset
= 0;
1172 base_offset
= (picochip_special_save_area_byte_offset () +
1173 picochip_special_save_area_size_in_bytes ());
1175 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1176 gcc_assert(picochip_is_aligned
1177 (base_offset
+ picochip_pretend_arg_area_size (), STACK_BOUNDARY
));
1183 /* Compute and return the offset of the incoming arguments. If a
1184 static chain is in use, this will be passed just before the other
1185 arguments. This means that the pretend argument mechanism, used in
1186 variadic functions, doesn't work properly. Thus, static chains work
1187 on their own, as do variadic functions, but not the combination of
1188 the two. This isn't really a problem. */
1190 picochip_arg_area_byte_offset (void)
1192 int base_offset
= (picochip_pretend_arg_area_byte_offset () +
1193 picochip_pretend_arg_area_size ());
1195 /* Add an extra 4 bytes - only an extra 16-bits are required, but
1196 the alignment on a 32-bit boundary must be maintained. */
1197 if (cfun
->static_chain_decl
!= NULL
)
1199 gcc_assert (!cfun
->stdarg
);
1203 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1210 picochip_regno_nregs (int regno ATTRIBUTE_UNUSED
, int mode
)
1213 /* Special case - only one register needed. */
1214 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1217 /* We actually do not allocate acc0 ever. But, it seems like we need to
1218 make it look like a allocatable register for the dataflow checks to work
1219 properly. Note that hard_regno_mode_ok will always return 0 for acc0*/
1224 /* General case - compute how much space in terms of units. */
1225 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1230 picochip_class_max_nregs (int reg_class
, int mode
)
1232 int size
= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1234 if (reg_class
== ACC_REGS
)
1237 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1244 /* Eliminate a register that addresses the stack (e.g., frame pointer,
1245 argument pointer) by replacing it with a constant offset from the
1246 main stack register. */
1248 initial_elimination_offset (int from
, int to
)
1250 int offset_from_sp
= 0;
1252 if (FRAME_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1253 offset_from_sp
= picochip_frame_byte_offset ();
1254 else if (ARG_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1255 offset_from_sp
= picochip_pretend_arg_area_byte_offset ();
1259 return offset_from_sp
;
1263 /* Compute and return the size of the incoming argument area. */
1265 picochip_arg_area_size_in_bytes (void)
1267 return crtl
->args
.size
;
1270 /* Determine whether the given register is valid. When the strict mode
1271 is used, only hard registers are valid, otherwise any register is
1274 picochip_legitimate_address_register (rtx x
, unsigned strict
)
1277 /* Sanity check - non-registers shouldn't make it here, but... */
1278 if (REG
!= GET_CODE (x
))
1282 return REGNO (x
) < FIRST_NONHARD_REGISTER
;
1288 /* Determine whether the given constant is in the range required for
1289 the given base register. */
1291 picochip_const_ok_for_base (enum machine_mode mode
, int regno
, int offset
)
1293 HOST_WIDE_INT corrected_offset
;
1295 if (GET_MODE_SIZE (mode
) != 0)
1297 if (GET_MODE_SIZE(mode
) <= 4)
1299 /* We used to allow incorrect offsets if strict is 0. But, this would
1300 then rely on reload doing the right thing. We have had problems
1301 there before, and on > 4.3 compiler, there are no benefits. */
1302 if (offset
% GET_MODE_SIZE (mode
) != 0)
1304 corrected_offset
= offset
/ GET_MODE_SIZE (mode
);
1308 if (offset
% 4 != 0)
1310 corrected_offset
= offset
/ 4;
1315 /* Default to the byte offset as supplied. */
1316 corrected_offset
= offset
;
1319 /* The offset from the base register can be different depending upon
1320 the base register. The stack/frame/argument pointer offsets can
1321 all be greater than a simple register-based offset. Note that the
1322 frame/argument pointer registers are actually eliminations of the
1323 stack pointer, so a value which is valid for an offset to, for
1324 example, the frame pointer, might be invalid for the stack
1325 pointer once the elimination has occurred. However, there is no
1326 need to handle this special case here, as the stack offset is
1327 always checked after elimination anyway, and the generated code
1328 seems to have identical performance. */
1329 if (regno
== STACK_POINTER_REGNUM
||
1330 regno
== FRAME_POINTER_REGNUM
|| regno
== ARG_POINTER_REGNUM
)
1331 return picochip_const_ok_for_letter_p (corrected_offset
, 'K');
1333 return picochip_const_ok_for_letter_p (corrected_offset
, 'J');
1337 /* Determine whether a given rtx is a legitimate address for machine_mode
1338 MODE. STRICT is non-zero if we're being strict - any pseudo that
1339 is not a hard register must be a memory reference. */
1341 picochip_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
1345 switch (GET_CODE (x
))
1348 valid
= picochip_legitimate_address_register (x
, strict
);
1353 rtx base
= XEXP (x
, 0);
1354 rtx offset
= XEXP (x
, 1);
1355 if (strict
&& !REGNO_OK_FOR_BASE_P (REGNO(base
)))
1361 valid
= (REG
== GET_CODE (base
) &&
1362 picochip_legitimate_address_register (base
, strict
) &&
1363 CONST_INT
== GET_CODE (offset
) &&
1364 picochip_const_ok_for_base (mode
, REGNO (base
),
1370 /* The user can select whether a symbol can be used as a memory
1371 address. Typically, this will decrease execution time (no
1372 register load is required first), but will increase code size
1373 (because the symbol will be used several times, rather than
1374 loaded once into a register.*/
1375 valid
= TARGET_SYMBOL_AS_ADDRESS
;
1380 /* A constant memory address must be a (plus (symbol_ref)
1381 (const_int)), and is only allowed when the symbols are
1382 permitted addresses. */
1383 rtx inner
= XEXP (x
, 0);
1385 valid
= (TARGET_SYMBOL_AS_ADDRESS
&&
1386 PLUS
== GET_CODE (inner
) &&
1387 SYMBOL_REF
== GET_CODE (XEXP (inner
, 0)) &&
1388 CONST_INT
== GET_CODE (XEXP (inner
, 1)));
1402 /* For all memory operations, picochip allows a uconst4 offset value. It
1403 is hence beneficial to turn an
1404 addr = <reg + long_const>
1409 X = reg + long_const & FFF0
1410 diff = long_const - (long_const & FFF0)
1413 X can be reused in subsequent memory operations.
1416 picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1417 enum machine_mode mode
)
1424 /* Depending on mode, the offsets allowed are either 16/32/64.*/
1440 if (GET_CODE (x
) == PLUS
1441 && GET_CODE (XEXP (x
, 0)) == REG
1442 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1444 int high_val
, low_val
, offset
;
1445 offset
= INTVAL (XEXP (x
, 1));
1446 // Ignore cases with negative offsets.
1449 high_val
= offset
& mask_val
;
1450 low_val
= offset
- high_val
;
1453 rtx temp_reg
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, XEXP (x
, 0), GEN_INT(high_val
)));
1454 x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1461 /* For all memory operations, picochip allows a uconst4 offset value. It
1462 is hence beneficial to turn an
1463 addr = <reg + long_const>
1468 X = reg + long_const & FFF0
1469 diff = long_const - (long_const & FFF0)
1472 X can be reused in subsequent memory operations.
1475 picochip_legitimize_reload_address (rtx
*x
,
1476 enum machine_mode mode
,
1477 int opnum
, int type
,
1478 int ind_levels ATTRIBUTE_UNUSED
)
1482 if (picochip_symbol_offset(*x
))
1484 *x
= gen_rtx_CONST(mode
, *x
);
1490 /* We should recognise addresses that we created.*/
1491 if (GET_CODE (*x
) == PLUS
1492 && GET_CODE (XEXP (*x
, 0)) == PLUS
1493 && GET_CODE (XEXP (XEXP (*x
, 0), 0)) == REG
1494 && GET_CODE (XEXP (XEXP (*x
, 0), 1)) == CONST_INT
1495 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1497 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1498 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1499 opnum
, (enum reload_type
)type
);
1503 // Depending on mode, the offsets allowed are either 16/32/64.
1519 if (GET_CODE (*x
) == PLUS
1520 && GET_CODE (XEXP (*x
, 0)) == REG
1521 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1523 int high_val
, low_val
, offset
;
1524 offset
= INTVAL (XEXP (*x
, 1));
1525 // Ignore cases with negative offsets.
1528 high_val
= offset
& mask_val
;
1529 low_val
= offset
- high_val
;
1532 rtx temp_reg
= gen_rtx_PLUS (Pmode
, XEXP (*x
, 0), GEN_INT(high_val
));
1533 *x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1534 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1535 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1536 opnum
, (enum reload_type
)type
);
1544 /* Detect an rtx which matches (plus (symbol_ref) (const_int)). */
1546 picochip_symbol_offset (rtx operand
)
1549 return (PLUS
== GET_CODE (operand
) &&
1550 SYMBOL_REF
== GET_CODE (XEXP (operand
, 0)) &&
1551 CONST_INT
== GET_CODE (XEXP (operand
, 1)));
1555 /* Assembly output. */
1557 /* The format here should match the format used in the output of
1558 symbol_ref's elsewhere in this file. */
1560 picochip_output_label (FILE * stream
, const char name
[])
1562 int is_cfi_label
= (strncmp (name
, "picoMark_LCFI", 13) == 0);
1564 /* If VLIW scheduling is in use, any Call Frame Information labels
1565 generated inside a packet must have their output deferred until
1566 the end of the packet. */
1567 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1568 is_cfi_label
&& picochip_vliw_continuation
)
1570 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1572 internal_error ("LCFI labels have already been deferred.");
1574 strcpy (picochip_current_vliw_state
.cfi_label_name
[
1575 picochip_current_vliw_state
.num_cfi_labels_deferred
], name
);
1576 picochip_current_vliw_state
.num_cfi_labels_deferred
++;
1580 assemble_name (stream
, name
);
1582 if (strncmp (name
, "picoMark_", 9) == 0)
1583 fprintf (stream
, "=\n");
1585 fprintf (stream
, ":\n");
1591 /* The format here should match the format used in the output of
1592 symbol_ref's elsewhere in this file. */
1594 picochip_output_labelref (FILE * stream
, const char name
[])
1596 fprintf (stream
, "_%s", name
);
1600 picochip_weaken_label (FILE * stream
, const char name
[])
1602 fprintf (stream
, ".weak ");
1603 assemble_name (stream
, name
);
1604 fprintf (stream
, "\n");
1607 /* Return true if the given label (or label prefix) denotes a marker
1608 label which should be emitted in the form LABEL= */
1610 picochip_is_marker_prefix (const char *prefix
)
1612 return (strcmp (prefix
, "L") != 0 && strcmp (prefix
, "LC") != 0
1613 && strcmp (prefix
, "LP") != 0);
1617 picochip_output_internal_label (FILE * stream
, const char *prefix
,
1621 /* Emit different types of label, based upon their prefix. They
1622 are handled differently to allow the assembler to ensure that
1623 branch target labels are properly aligned, while other labels
1624 will only serve as code markers, not branch targets. Aligning
1625 labels unnecessarily can result in much code wastage. */
1626 if (picochip_is_marker_prefix (prefix
))
1628 /* Special label marker. If it appears in the middle of a VLIW
1629 packet, defer it until the end of the packet. There has
1630 never been a need to handle more than one lm label at a time. */
1631 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1632 (strcmp (prefix
, "LM")) == 0 && picochip_vliw_continuation
)
1634 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
1635 internal_error ("LM label has already been deferred.");
1637 sprintf (picochip_current_vliw_state
.lm_label_name
,
1638 "picoMark_%s%ld", prefix
, num
);
1643 fprintf (stream
, "_picoMark_%s%ld=\n", prefix
, num
);
1650 fprintf (stream
, "_%s%ld:\n", prefix
, num
);
1656 picochip_generate_internal_label (char *str
, const char *prefix
, long num
)
1658 /* Two types of internal label can be generated: branch target
1659 labels and code marker labels. Branch target labels must always
1660 be aligned (since code will execute at these
1661 points). Differentiate between the two by prepending markers with
1662 a unique prefix, which can later be used in output_label to
1663 figure out which label syntax to use. */
1664 if (picochip_is_marker_prefix (prefix
))
1665 sprintf (str
, "picoMark_%s%ld", prefix
, num
);
1667 sprintf (str
, "%s%ld", prefix
, num
);
1672 picochip_asm_output_anchor (rtx symbol
)
1674 fprintf (asm_out_file
, ".offsetData _%s, ",XSTR (symbol
, 0));
1675 fprintf (asm_out_file
, "+ " HOST_WIDE_INT_PRINT_DEC
"\n",SYMBOL_REF_BLOCK_OFFSET(symbol
));
1679 picochip_output_aligned_common (FILE * stream
, const char *name
,
1680 unsigned size
, unsigned alignment
)
1683 fprintf (stream
, ".commonData ");
1684 assemble_name (stream
, name
);
1685 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1686 picochip_output_global (stream
, name
);
1691 picochip_output_aligned_local (FILE * stream
, const char *name
,
1692 unsigned size
, unsigned alignment
)
1695 fprintf (stream
, ".commonData ");
1696 assemble_name (stream
, name
);
1697 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1702 picochip_output_global (FILE * stream
, const char *name
)
1704 fprintf (stream
, ".global ");
1705 assemble_name (stream
, name
);
1706 fprintf (stream
, "\n");
1709 /* Output an assembly language string. Output as a sequence of decimal
1710 numbers, followed by the literal string to make it obvious what the
1711 numbers represent. */
1713 picochip_output_ascii (FILE * file
, const char *str
, int length
)
1717 fprintf (file
, ".ascii ");
1719 for (i
= 0; i
< length
; ++i
)
1721 fprintf (file
, "16#%x# ", (char) (str
[i
]));
1724 fprintf (file
, " ; ");
1726 for (i
= 0; i
< length
; ++i
)
1733 fprintf (file
, "\\n");
1736 fprintf (file
, "\\t");
1739 fprintf (file
, "\\0");
1742 fprintf (file
, "%c", c
);
1747 fprintf (file
, "\n");
1751 /* Output the beginning of an ASM file. */
1753 picochip_asm_file_start (void)
1755 default_file_start ();
1757 fprintf (asm_out_file
, "// picoChip ASM file\n");
1758 fprintf (asm_out_file
, "//.file \"%s\"\n", main_input_filename
);
1760 fprintf (asm_out_file
, "// Has byte access: %s\n",
1761 (TARGET_HAS_BYTE_ACCESS
? "Yes" : "No"));
1763 if (TARGET_HAS_MUL_UNIT
)
1764 fprintf (asm_out_file
, "// Has multiply: Yes (Multiply unit)\n");
1765 else if (TARGET_HAS_MAC_UNIT
)
1766 fprintf (asm_out_file
, "// Has multiply: Yes (Mac unit)\n");
1768 fprintf (asm_out_file
, "// Has multiply: No\n");
1770 /* Variable tracking should be run after all optimizations which change order
1771 of insns. It also needs a valid CFG. This can't be done in
1772 picochip_option_override, because flag_var_tracking is finalized after
1774 picochip_flag_var_tracking
= flag_var_tracking
;
1775 flag_var_tracking
= 0;
1778 /* Output the end of an ASM file. */
1780 picochip_asm_file_end (void)
1782 /* Include a segment end to make it easy for PERL scripts to grab
1783 segments. This is now done by assembler*/
1785 fprintf (asm_out_file
, "// End of picoChip ASM file\n");
1789 /* Output frame debug information to the given stream. */
1791 picochip_output_frame_debug (FILE * file
)
1795 if (current_function_is_leaf
)
1796 fprintf (file
, "\t\t// Leaf function\n");
1798 fprintf (file
, "\t\t// Non-leaf function\n");
1800 if (picochip_can_eliminate_link_sp_save ())
1801 fprintf (file
, "\t\t// Link/fp save/restore can be eliminated\n");
1803 if (cfun
->static_chain_decl
!= NULL
)
1804 fprintf (file
, "\t\t// Static chain in use\n");
1806 fprintf (file
, "\t\t// Incoming argument size: %d bytes\n",
1807 picochip_arg_area_size_in_bytes ());
1808 fprintf (file
, "\t\t// Incoming arg offset: %d\n",
1809 picochip_arg_area_byte_offset ());
1810 fprintf (file
, "\t\t// Pretend arg size: %d\n",
1811 picochip_pretend_arg_area_size ());
1812 fprintf (file
, "\t\t// Pretend arg offset (ARGP): %d\n",
1813 picochip_pretend_arg_area_byte_offset ());
1814 fprintf (file
, "\t\t// Special reg area size: %d bytes\n",
1815 picochip_special_save_area_size_in_bytes ());
1816 fprintf (file
, "\t\t// Special reg area offset: %d\n",
1817 picochip_special_save_area_byte_offset ());
1819 /* Output which registers are saved. */
1820 fprintf (file
, "\t\t// Saved regs: ");
1821 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1823 if (picochip_reg_needs_saving (i
))
1824 fprintf (file
, "%s ", picochip_regnames
[i
]);
1826 fprintf (file
, "\t\t\n");
1828 fprintf (file
, "\t\t// Save area size: %d bytes\n",
1829 picochip_save_area_size_in_bytes ());
1830 fprintf (file
, "\t\t// Save area offset: %d\n",
1831 picochip_save_area_byte_offset ());
1833 fprintf (file
, "\t\t// Frame size: %ld bytes\n", get_frame_size ());
1834 fprintf (file
, "\t\t// Frame offset (FP): %d\n",
1835 picochip_frame_byte_offset ());
1837 fprintf (file
, "\t\t// Outgoing argument area size: %d bytes\n",
1838 crtl
->outgoing_args_size
);
1842 /* Output picoChip function prologue. This contains human-readable
1843 information about the function. */
1845 picochip_function_prologue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1847 /* Get the function's name, as described by its RTL. This may be
1848 different from the DECL_NAME name used in the source file. The
1849 real declaration name must be used, to ensure that the prologue
1850 emits the right information for the linker. */
1853 x
= DECL_RTL (current_function_decl
);
1854 gcc_assert (MEM_P (x
));
1856 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1857 fnname
= XSTR (x
, 0);
1859 /* Note that the name of the function is given in the &_%s
1860 form. This matches the name of the function as used in labels,
1861 and function calls, and enables processCallGraph to match
1862 function calls to the name of the function, as defined here. */
1863 fprintf (file
, "// picoChip Function Prologue : &_%s = %d bytes\n",
1864 fnname
, picochip_arg_area_byte_offset ());
1866 picochip_output_frame_debug (file
);
1867 fprintf (file
, "\n");
1871 /* Output picoChip function epilogue. */
1873 picochip_function_epilogue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1878 x
= DECL_RTL (current_function_decl
);
1879 gcc_assert (MEM_P (x
));
1881 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1882 fnname
= XSTR (x
, 0);
1883 fprintf (file
, "\n// picoChip Function Epilogue : %s\n\n",
1887 /* Manipulate the asm output. Some machines only execute the code when
1888 there is actually a chance of needing it (e.g., FRV doesn't execute
1889 it if the scheduling pass wasn't used). We always execute it,
1890 simple to ensure that it is exercised more often, and bugs are more
1893 This function's prime reason for existence is to insert the VLIW
1894 separators where appropriate. The separators must be inserted
1895 before any comments which appear at the end of the file.
1899 picochip_asm_output_opcode (FILE * f
, const char *ptr
)
1903 /* Flag to specify when a VLIW continuation has been inserted onto
1904 the line. Continuations are either inserted before any comments,
1905 or before the end of the line is reached. The flag ensures that
1906 we don't insert continuations twice (i.e., at the comment and the
1908 int continuation_inserted
= 0;
1910 /* If the instruction uses multiple lines (i.e., a new line
1911 character appears in the opcode), then ensure that no attempt is
1912 made to pack it into a VLIW. */
1913 if (strchr (ptr
, '\n') != NULL
&& picochip_vliw_continuation
)
1915 ("picochip_asm_output_opcode - Found multiple lines in VLIW packet %s\n",
1919 /* If a delay slot is pending, output the directive to the assembler
1920 before the instruction. */
1921 if (picochip_is_delay_slot_pending
)
1923 picochip_is_delay_slot_pending
= 0;
1927 /* Keep going for entire opcode. All substitution performed ourselves. */
1932 /* Determine whether a VLIW continuation must be inserted before
1933 any comments, or the end of the opcode. A flag is set to show
1934 that we have inserted a continuation on this line, so that we
1935 don't try to insert another continuation when the end of the
1936 opcode is reached. The only other case for a continuation
1937 might have been a newline, but these aren't allowed in
1938 conjunction with VLIW continuations (see above code). */
1939 if (picochip_vliw_continuation
&&
1940 !continuation_inserted
&&
1941 ((c
== '/' && (*ptr
== '/')) || *ptr
== '\0'))
1944 continuation_inserted
= 1;
1947 /* Detect an explicit VLIW separator. */
1948 if (c
== '%' && (*ptr
== '|'))
1953 /* Detect the need for an ALU id operand. */
1954 else if (c
== '%' && (*ptr
== '#'))
1956 fputc (picochip_get_vliw_alu_id (), f
);
1959 printf ("Generated ALU char at %s for insn %d\n", ptr
,
1960 INSN_UID (picochip_current_prescan_insn
));
1962 /* Skip past unwanted # */
1965 /* Detect the need for branch delay slot. */
1966 else if (c
== '%' && (*ptr
== '>'))
1968 /* Only emit delay slots (NOP's, or otherwise) when delay
1969 * slot scheduling has actually been enabled, otherwise VLIW
1970 * scheduling and delay slot scheduling output combine to
1971 * produce nasty effects. */
1972 if (flag_delayed_branch
)
1974 if (dbr_sequence_length () == 0)
1975 fputs ("\n=->\tNOP", f
);
1977 picochip_is_delay_slot_pending
= 1;
1980 /* Skip past unwanted > */
1983 /* Detect any %digit specifiers. */
1984 else if (c
== '%' && (*ptr
>= '0' && *ptr
<= '9'))
1987 picochip_print_operand (f
, recog_data
.operand
[c
], 0);
1988 while ((c
= *ptr
) >= '0' && c
<= '9')
1991 /* Detect any %letterdigit specifiers. */
1992 else if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
1993 || (*ptr
>= 'A' && *ptr
<= 'Z')))
1995 int letter
= *ptr
++;
2002 output_asm_label (recog_data
.operand
[c
]);
2006 output_address (recog_data
.operand
[c
]);
2010 picochip_print_operand (f
, recog_data
.operand
[c
], letter
);
2013 while ((c
= *ptr
) >= '0' && c
<= '9')
2018 ("picochip_asm_output_opcode - can't output unknown operator %c\n",
2024 /* Reached the end of the packet. If any labels were deferred
2025 during output, emit them now. */
2026 if (!picochip_vliw_continuation
)
2028 if (picochip_current_vliw_state
.num_cfi_labels_deferred
!= 0)
2031 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[0]);
2033 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
2036 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[1]);
2041 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
2044 assemble_name (f
, picochip_current_vliw_state
.lm_label_name
);
2049 /* Output an end-of-packet marker if requested. */
2050 if (!picochip_vliw_continuation
&&
2051 TARGET_DEBUG
&& picochip_schedule_type
== DFA_TYPE_SPEED
)
2052 fprintf (f
, "\n\t//-------------- End of VLIW packet -----------------");
2057 /* Function RTL expansion. */
2059 /* Expand the prologue into RTL. */
2061 picochip_expand_prologue (void)
2063 int stack_adjustment
= 0;
2064 int special_save_offset
= 0;
2065 int general_save_offset
= 0;
2066 int reg_save_offset
= 0;
2069 stack_adjustment
= picochip_arg_area_byte_offset ();
2070 general_save_offset
=
2071 -(stack_adjustment
- picochip_save_area_byte_offset ());
2072 special_save_offset
=
2073 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
2075 /* Save the link registers. We could try to save just one register
2076 here. This would reduce the amount of stack space required.
2077 There hasnt been a good reason to do that so far. */
2078 if (!picochip_can_eliminate_link_sp_save ())
2079 picochip_emit_save_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2080 special_save_offset
);
2082 /* Save callee-save registers. */
2083 reg_save_offset
= 0;
2084 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2086 if (picochip_reg_needs_saving (i
))
2089 /* If this register is an even numbered register, and the
2090 next register also needs to be saved, use a SImode save,
2091 which does both in one instruction. Note that a special
2092 check is performed to ensure that the double word aligned
2093 store is valid (e.g., it is possible that r6, r8, r9 need
2094 to be saved, in which case once r6 has been saved, the
2095 stored offset is no longer aligned, and an STL/LDL
2096 instruction becomes invalid). Alternately, we could store all
2097 aligned registers first and then save the single one(s). */
2099 picochip_reg_needs_saving (i
+ 1) &&
2100 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2102 picochip_emit_save_register (gen_rtx_REG (SImode
, i
),
2103 general_save_offset
+
2105 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2110 picochip_emit_save_register (gen_rtx_REG (HImode
, i
),
2111 general_save_offset
+
2113 reg_save_offset
+= UNITS_PER_WORD
;
2119 /* Emit a stack adjustment where required. */
2120 if (stack_adjustment
!= 0)
2121 picochip_emit_stack_allocate (stack_adjustment
);
2123 /* If this function uses varadic arguments, write any unnamed
2124 registers to the stack. */
2127 int stdarg_offset
= picochip_pretend_arg_area_byte_offset ();
2129 /* Sanity check. The pretend argument offset should be 32-bit aligned. */
2130 gcc_assert(picochip_pretend_arg_area_byte_offset () % 4 == 0);
2132 picochip_emit_save_register (gen_rtx_REG (SImode
, 0), stdarg_offset
);
2133 picochip_emit_save_register (gen_rtx_REG (SImode
, 2),
2135 picochip_emit_save_register (gen_rtx_REG (SImode
, 4),
2142 /* Expand the epilogue into RTL. */
2144 picochip_expand_epilogue (int is_sibling_call ATTRIBUTE_UNUSED
)
2146 int stack_adjustment
= 0;
2147 int special_save_offset
= 0;
2148 int general_save_offset
= 0;
2149 int reg_save_offset
= 0;
2151 int use_link_fp_restore_stack_adjust
= 0; /* Default to using an explicit
2154 stack_adjustment
= picochip_arg_area_byte_offset ();
2155 general_save_offset
=
2156 -(stack_adjustment
- picochip_save_area_byte_offset ());
2157 special_save_offset
=
2158 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
2160 /* Emit a stack adjustment where required. */
2161 if (stack_adjustment
!= 0)
2163 /* If the link/fp is already being restored, and the offset to
2164 their save location is small enough, don't bother adjusting
2165 the stack explicitly. */
2166 if (picochip_special_save_area_byte_offset () < 512 &&
2167 !picochip_can_eliminate_link_sp_save ())
2168 use_link_fp_restore_stack_adjust
= 1;
2170 /* Explicitly restore the stack. */
2171 picochip_emit_stack_allocate (-stack_adjustment
);
2174 /* Restore the Link/FP registers. Only save the link register? */
2175 if (!picochip_can_eliminate_link_sp_save ())
2177 if (use_link_fp_restore_stack_adjust
)
2178 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2179 picochip_special_save_area_byte_offset
2182 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2183 special_save_offset
);
2186 /* Restore callee-save registers. */
2187 reg_save_offset
= 0;
2188 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2190 if (picochip_reg_needs_saving (i
))
2193 /* If this register is an even numbered register, and the
2194 next register also needs to be saved, use a SImode save,
2195 which does both in one instruction. Note that a special
2196 check is performed to ensure that the double word aligned
2197 store is valid (e.g., it is possible that r6, r8, r9 need
2198 to be saved, in which case once r6 has been saved, the
2199 stored offset is no longer aligned, and an STL/LDL
2200 instruction becomes invalid). We could store all aligned
2201 registers first, and then save the single one(s). */
2203 picochip_reg_needs_saving (i
+ 1) &&
2204 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2206 picochip_emit_restore_register (gen_rtx_REG (SImode
, i
),
2207 general_save_offset
+
2209 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2214 picochip_emit_restore_register (gen_rtx_REG (HImode
, i
),
2215 general_save_offset
+
2217 reg_save_offset
+= UNITS_PER_WORD
;
2223 /* Emit a return instruction, which matches a (parallel
2224 [(return) (use r12)]) */
2227 p
= rtvec_alloc (2);
2229 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
2230 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
2231 gen_rtx_REG (Pmode
, LINK_REGNUM
));
2232 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
2237 /* Assembly instruction output. */
2239 /* Test whether the given branch instruction is short, or long. Short
2240 * branches are equivalent to real branches, and may be DFA
2241 * scheduled. Long branches expand to a macro which is handled by the
2242 * elaborator, and cannot be scheduled. Occasionally, the branch
2243 * shortening pass, which is run after DFA scheduling, will change the
2244 * code layout and cause the short branch to be reverted into a long
2245 * branch. Instead of having to fix this up by emitting new assembly,
2246 * the short branch is emitted anyway. There is plenty of slack in the
2247 * calculation of long and short branches (10-bit offset, but only
2248 * 9-bits used in computation), so there is enough slack for this to
2251 picochip_is_short_branch (rtx insn
)
2253 int isRealShortBranch
= (get_attr_length(insn
) == SHORT_BRANCH_LENGTH
);
2255 return (isRealShortBranch
||
2256 (!isRealShortBranch
&&
2257 picochip_current_vliw_state
.num_insns_in_packet
> 1));
2260 /* Output a compare-and-branch instruction (matching the cbranch
2263 picochip_output_cbranch (rtx operands
[])
2266 if (HImode
!= GET_MODE (operands
[1]) ||
2267 (HImode
!= GET_MODE (operands
[2]) &&
2268 GET_CODE (operands
[2]) != CONST_INT
))
2270 internal_error ("%s: At least one operand can't be handled",
2274 /* Use the type of comparison to output the appropriate condition
2276 switch (GET_CODE (operands
[0]))
2279 return ("// if (%1 != %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPNE %l3");
2282 return ("// if (%1 == %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPEQ %l3");
2285 /* Reverse the operand order to be GE */
2286 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPGE %l3");
2289 /* Reverse operand order of GEU. */
2290 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPHS %l3");
2293 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPGE %l3");
2296 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPHS %l3");
2299 return ("// if (%1 < %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLT %l3");
2302 return ("// if (%1 <{U} %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLO %l3");
2305 /* Reversed operand version of LT. */
2306 return ("// if (%1 > %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLT %l3");
2309 /* Reverse an LTU. */
2310 return ("// if (%1 >{U} %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLO %l3");
2317 /* Output a compare-and-branch instruction (matching the cbranch
2318 pattern). This function is current unused since the cbranch
2319 split is disabled. The function is kept around so we can use
2320 it when we understand how to do cbranch split safely. */
2322 picochip_output_compare (rtx operands
[])
2326 if (HImode
!= GET_MODE (operands
[1]) ||
2327 (HImode
!= GET_MODE (operands
[2]) &&
2328 GET_CODE (operands
[2]) != CONST_INT
))
2330 internal_error ("%s: At least one operand can't be handled",
2334 code
= GET_CODE (operands
[0]);
2335 /* Use the type of comparison to output the appropriate condition
2340 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2343 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2346 /* Reverse the operand order to be GE */
2347 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2350 /* Reverse operand order of GEU. */
2351 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2354 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2357 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2360 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2363 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2366 /* Reversed operand version of LT. */
2367 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2370 /* Reverse an LTU. */
2371 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2378 /* Output the branch insn part of a compare-and-branch split. */
2380 picochip_output_branch (rtx operands
[], rtx insn
)
2383 int code
= GET_CODE(operands
[2]);
2384 if (picochip_is_short_branch (insn
))
2386 /* Short branches can be output directly using the
2387 appropriate instruction. */
2391 return ("BNE %l0 %>");
2393 return ("BEQ %l0 %>");
2395 return ("BGE %l0 %>");
2397 return ("BHS %l0 %>");
2399 return ("BGE %l0 %>");
2401 return ("BHS %l0 %>");
2403 return ("BLT %l0 %>");
2405 return ("BLO %l0 %>");
2407 return ("BLT %l0 %>");
2409 return ("BLO %l0 %>");
2411 internal_error ("Unknown short branch in %s (type %d)\n",
2412 __FUNCTION__
, (int) INTVAL (operands
[1]));
2413 return "UNKNOWN_BRANCH";
2418 /* Long branches result in the emission of a special
2419 instruction, which the assembler expands into a suitable long
2422 /* Use the type of comparison to output the appropriate condition
2427 return ("JMPNE %l0 %>");
2429 return ("JMPEQ %l0 %>");
2431 return ("JMPGE %l0 %>");
2433 return ("JMPHS %l0 %>");
2435 return ("JMPGE %l0 %>");
2437 return ("JMPHS %l0 %>");
2439 return ("JMPLT %l0 %>");
2441 return ("JMPLO %l0 %>");
2443 return ("JMPLT %l0 %>");
2445 return ("JMPLO %l0 %>");
2448 internal_error ("Unknown long branch in %s (type %d)\n",
2449 __FUNCTION__
, (int) INTVAL (operands
[1]));
2450 return "UNKNOWN_BRANCH";
2456 /* Output a jump instruction. */
2458 picochip_output_jump (rtx insn
)
2460 if (picochip_is_short_branch (insn
))
2463 return "JMPRA %l0%>";
2467 picochip_output_put_array (int alternative
, rtx operands
[])
2469 /* Local output buffer. */
2472 int portArraySize
= INTVAL(operands
[1]);
2473 int portBaseIndex
= INTVAL(operands
[2]);
2475 if (alternative
== 0)
2477 sprintf (buf
, "// Array put\n\tadd.0 [lsl %%0,2],&__commTable_put_%d_%d,lr\n\tjl (lr)",
2478 portArraySize
, portBaseIndex
);
2479 output_asm_insn (buf
, operands
);
2481 else if (alternative
== 1)
2483 /* Constant port id. Emit a real instruction. */
2484 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2485 if (portIndex
< portBaseIndex
||
2486 portIndex
>= (portBaseIndex
+ portArraySize
))
2488 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2489 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2491 sprintf(buf
, "PUT R[0:1],%d", portIndex
);
2492 output_asm_insn (buf
, operands
);
2497 /* Both alternatives output the insn directly. */
2501 const char *picochip_output_get_array (int alternative
, rtx operands
[])
2503 /* Local output buffer. */
2506 int portArraySize
= INTVAL(operands
[1]);
2507 int portBaseIndex
= INTVAL(operands
[2]);
2509 if (alternative
== 0)
2511 sprintf (buf
, "// Array get\n\tadd.0 [lsl %%0,2],&__commTable_get_%d_%d,lr\n\tjl (lr)",
2512 portArraySize
, portBaseIndex
);
2513 output_asm_insn (buf
, operands
);
2515 else if (alternative
== 1)
2517 /* Constant port id. Emit a real instruction. */
2518 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2519 if (portIndex
< portBaseIndex
||
2520 portIndex
>= (portBaseIndex
+ portArraySize
))
2522 error ("GET uses port array index %d, which is out of range [%d..%d)",
2523 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2525 sprintf(buf
, "GET %d,R[0:1]", portIndex
);
2526 output_asm_insn (buf
, operands
);
2531 /* Both alternatives output the insn directly. */
2535 const char *picochip_output_testport_array (int alternative
, rtx operands
[])
2537 /* Local output buffer. */
2540 int portArraySize
= INTVAL(operands
[2]);
2541 int portBaseIndex
= INTVAL(operands
[3]);
2543 if (alternative
== 0)
2545 sprintf (buf
, "// Array tstport\n\tadd.0 [lsl %%1,2],&__commTable_tstport_%d_%d,lr\n\tjl (lr)\n=->\tcopy.0 0,%%0\n\tcopyeq 1,%%0",
2546 portArraySize
, portBaseIndex
);
2547 output_asm_insn (buf
, operands
);
2549 else if (alternative
== 1)
2551 /* Constant port id. Emit a real instruction. */
2552 int portIndex
= INTVAL(operands
[1]) + portBaseIndex
;
2553 if (portIndex
< portBaseIndex
||
2554 portIndex
>= (portBaseIndex
+ portArraySize
))
2556 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2557 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2559 sprintf(buf
, "copy.1 0,%%0 %%| TSTPORT %d\n\tcopyeq 1,%%0", portIndex
);
2560 output_asm_insn (buf
, operands
);
2565 /* Both alternatives output the insn directly. */
2569 /* Output a comparison operand as a symbol (e.g., >). */
2571 picochip_print_comparison (FILE * file
, rtx operand
, int letter
)
2576 /* Output just the comparison symbol. */
2577 switch (GET_CODE (operand
))
2580 fprintf (file
, "!=");
2583 fprintf (file
, "==");
2586 fprintf (file
, ">=");
2589 fprintf (file
, ">={U}");
2592 fprintf (file
, "<");
2595 fprintf (file
, "<{U}");
2598 fprintf (file
, "<=");
2601 fprintf (file
, "<={U}");
2604 fprintf (file
, ">");
2607 fprintf (file
, ">{U}");
2615 /* Output the comparison formatted as operand,symbol,operand */
2616 rtx op0
= XEXP (operand
, 0);
2617 rtx op1
= XEXP (operand
, 1);
2619 picochip_print_operand (file
, op0
, 0);
2620 picochip_print_comparison (file
, operand
, 'i');
2621 picochip_print_operand (file
, op1
, 0);
2625 /* This function generates a memory address operand in the given
2626 mode. That is, if the address contains a constant offset, then the
2627 offset is divided by the required mode size to compute the
2628 mode specific offset. By default, picochip_print_operand_address calls
2629 this function using the natural mode of the operand, but special
2630 operand codes can be used to invoke the computation using an
2631 unnatural mode (e.g., compute the HI aligned address of an SI mode
2634 picochip_print_memory_address (FILE * file
, rtx operand
,
2635 enum machine_mode mode
)
2637 rtx address
= XEXP (operand
, 0);
2640 if (MEM
!= GET_CODE (operand
))
2641 fatal_insn ("picochip_print_memory_address - Operand isn't memory based",
2646 printf ("picochip_print_memory_address: ");
2647 print_rtl (stdout
, operand
);
2651 switch (GET_CODE (address
))
2655 /* Grab the address components. */
2656 rtx base
= XEXP (address
, 0);
2657 rtx offset
= XEXP (address
, 1);
2659 /* Only handle reg+const addresses */
2660 if (REG
== GET_CODE (base
) && CONST_INT
== GET_CODE (offset
))
2662 /* Sanity check. If an FP+offset address is given, ensure
2663 that the offset lies within the given frame, or a lower
2665 if (REGNO (base
) == STACK_POINTER_REGNUM
)
2666 gcc_assert (INTVAL (offset
) <= (picochip_arg_area_byte_offset () +
2669 /* Print the base register - identical for all modes. */
2670 fprintf (file
, "(");
2671 picochip_print_operand (file
, base
, 'r');
2672 fprintf (file
, ")");
2674 /* Print the constant offset with compensation for the mode. */
2678 picochip_print_operand (file
, offset
, 'Q');
2682 picochip_print_operand (file
, offset
, 'H');
2687 picochip_print_operand (file
, offset
, 'S');
2691 picochip_print_operand (file
, offset
, 'D');
2705 picochip_print_operand (file
, address
, 's');
2714 inner
= XEXP (address
, 0);
2716 /* Sanity check - the CONST memory address must be a base+offset. */
2717 gcc_assert (PLUS
== GET_CODE (inner
));
2719 base
= XEXP (inner
, 0);
2720 offset
= XEXP (inner
, 1);
2722 fprintf (file
, "&_%s%+d", XSTR (base
, 0), XINT (offset
, 0));
2728 /* Register operand. Provide a zero offset. */
2729 fprintf (file
, "(");
2730 picochip_print_operand (file
, address
, 'r');
2731 fprintf (file
, ")0");
2740 /* Output an operand. Formatting letters allow particular parts of
2741 the operand to be output. */
2743 picochip_print_operand (FILE * file
, rtx operand
, int letter
)
2746 /* Handle special cases. */
2749 /* VLIW continuation, for explicit VLIW sequences. */
2751 fprintf (file
, "\\");
2756 fputc (picochip_get_vliw_alu_id (), file
);
2759 /* Delay slot specifier. */
2761 /* This should be handled in asm_output_opcode. */
2764 /* Instruction mnemonics (e.g., lshift becomes LSL). */
2766 switch (GET_CODE (operand
))
2769 fprintf (file
, "AND");
2772 fprintf (file
, "OR");
2775 fprintf (file
, "XOR");
2778 fprintf (file
, "ADD");
2781 fprintf (file
, "SUB");
2788 /* Symbolic instructions (e.g., lshift becomes <<). */
2790 switch (GET_CODE (operand
))
2793 fprintf (file
, "&");
2796 fprintf (file
, "|");
2799 fprintf (file
, "^");
2802 fprintf (file
, "+");
2805 fprintf (file
, "-");
2808 fprintf (file
, "UNKNOWN_INSN");
2813 default: /* Not a punctuation character - process as normal. */
2817 switch (GET_CODE (operand
))
2823 /* Write a range of registers. */
2824 fprintf (file
, "R[%d:%d]", REGNO (operand
) + 1, REGNO (operand
));
2828 /* The upper register of a pair is requested. */
2829 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 1]);
2833 /* The lower register of a pair is requested. Equivalent to the
2834 default, but included for completeness. */
2835 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2839 /* The 3rd register of a DI mode register. */
2840 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 2]);
2844 /* The 4th register of a DI mode register. */
2845 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 3]);
2849 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2854 /* A range of letters can be used to format integers. The
2855 letters Q/H/S are used to divide the constant by the width of
2856 QI/HI/SI mode integers in bytes. The U/L modifiers are used
2857 to obtain the upper and lower 16-bits of a 32-bit
2858 constant. Where possible, signed numbers are used, since
2859 signed representations of numbers may be more compact (e.g.,
2860 65535 can be represented as -1, which fits into a small
2861 constant, whereas 65535 requires a large constant). */
2865 fprintf (file
, "%ld", INTVAL (operand
));
2869 fprintf (file
, "%ld", INTVAL (operand
) / 2);
2873 fprintf (file
, "%ld", INTVAL (operand
) / 4);
2877 fprintf (file
, "%d", exact_log2 (INTVAL(operand
)));
2881 fprintf (file
, "%hi", (short) ((INTVAL (operand
) >> 16) & 0xFFFF));
2885 fprintf (file
, "%hi", (short) (INTVAL (operand
) & 0xFFFF));
2889 fprintf (file
, "%ld", INTVAL (operand
));
2899 if (GET_MODE (operand
) != SFmode
)
2900 fatal_insn ("Unknown mode in print_operand (CONST_DOUBLE) :",
2902 REAL_VALUE_FROM_CONST_DOUBLE (rv
, operand
);
2903 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
2908 fprintf (file
, "%hi", (short) ((val
>> 16) & 0xFFFF));
2912 fprintf (file
, "%hi", (short) (val
& 0xFFFF));
2920 /* Output a symbol. The output format must match that of
2921 picochip_output_label. */
2923 /* Ensure that the symbol is marked as referenced. Gcc can
2924 occasionally omit the function bodies when it believes them
2925 to be unreferenced. */
2926 if (SYMBOL_REF_DECL (operand
))
2927 mark_decl_referenced (SYMBOL_REF_DECL (operand
));
2928 fprintf (file
, "&");
2929 assemble_name (file
, XSTR (operand
, 0));
2933 /* This format must match that of picochip_output_label. */
2934 fprintf (file
, "&");
2935 output_asm_label (operand
);
2940 rtx addr
= XEXP (operand
, 0);
2945 if (PLUS
!= GET_CODE (addr
))
2946 fatal_insn ("Bad address, not (reg+disp):", addr
);
2948 picochip_print_operand (file
, XEXP (addr
, 1), 0);
2952 /* Output a memory address in byte mode notation (i.e., the
2953 constant address (if any) is the actual byte address. */
2954 picochip_print_memory_address (file
, operand
, QImode
);
2957 /* Output a constant offset of the given mode (i.e., divide
2958 the constant by the number of units in the mode to get the
2961 picochip_print_memory_address (file
, operand
, QImode
);
2965 picochip_print_memory_address (file
, operand
, HImode
);
2969 picochip_print_memory_address (file
, operand
, SImode
);
2973 picochip_print_memory_address (file
, operand
, SFmode
);
2977 if (PLUS
!= GET_CODE (addr
))
2978 fatal_insn ("Bad address, not (reg+disp):", addr
);
2980 picochip_print_operand (file
, XEXP (addr
, 0), 0);
2983 /* When the mem operand is (reg + big offset) which cannot
2984 be represented in an instruction as operand, the compiler
2985 automatically generates the instruction to put in (reg +
2986 big offset) into another register. In such cases, it
2987 returns '0' as the character. This needs to be handled
2991 if (REG
!= GET_CODE (addr
))
2992 fatal_insn ("Bad address, not register:", addr
);
2994 picochip_print_operand (file
, addr
, 0);
2998 fprintf (file
, "Unknown mem operand - letter %c ",
3000 print_rtl (file
, operand
);
3008 rtx const_exp
= XEXP (operand
, 0);
3010 /* Handle constant offsets to symbol references. */
3011 if (PLUS
== GET_CODE (const_exp
) &&
3012 SYMBOL_REF
== GET_CODE (XEXP (const_exp
, 0)) &&
3013 CONST_INT
== GET_CODE (XEXP (const_exp
, 1)))
3016 picochip_print_operand (file
, XEXP (const_exp
, 0), 0);
3017 if (INTVAL (XEXP (const_exp
, 1)) >= 0)
3018 fprintf (file
, "+");
3019 /* else use the - from the operand (i.e., AP-2)) */
3021 picochip_print_operand (file
, XEXP (const_exp
, 1), letter
);
3030 /* PLUS expressions are of the form (base + offset). Different
3031 options (analagous to those of memory PLUS expressions) are used
3032 to extract the base and offset components. */
3037 picochip_print_operand (file
, XEXP (operand
, 0), 0);
3041 picochip_print_operand (file
, XEXP (operand
, 1), 0);
3046 /* If the expression is composed entirely of constants,
3047 evaluate the result. This should only occur with the
3048 picoChip specific comms instructions, which are emitted as
3049 base+offset expressions. */
3050 if (CONST_INT
== GET_CODE (XEXP (operand
, 0)) &&
3051 CONST_INT
== GET_CODE (XEXP (operand
, 1)))
3053 HOST_WIDE_INT result
= (XINT (XEXP (operand
, 0), 0) +
3054 XINT (XEXP (operand
, 1), 0));
3055 fprintf (file
, "%ld", result
);
3059 fprintf (file
, "(");
3060 picochip_print_operand (file
, XEXP (operand
, 0), 0);
3061 fprintf (file
, "+");
3062 picochip_print_operand (file
, XEXP (operand
, 1), 0);
3063 fprintf (file
, ")");
3070 /* Comparison operations. */
3081 picochip_print_comparison (file
, operand
, letter
);
3085 fprintf (stderr
, "Unknown operand encountered in %s\n", __FUNCTION__
);
3086 print_rtl (file
, operand
);
3093 /* Output an operand address */
3095 picochip_print_operand_address (FILE * file
, rtx operand
)
3098 switch (GET_CODE (operand
))
3102 /* This format must match that of picochip_output_label. */
3103 assemble_name (file
, XSTR (operand
, 0));
3107 /* Note this format must match that of picochip_output_label. */
3108 fprintf (file
, "_L%d", XINT (operand
, 5));
3112 /* Pass on to a specialised memory address generator. */
3113 picochip_print_memory_address (file
, operand
, GET_MODE (operand
));
3124 /* Scheduling functions. */
3126 /* Save some of the contents of recog_data. */
3128 picochip_save_recog_data (void)
3130 picochip_saved_which_alternative
= which_alternative
;
3131 memcpy (&picochip_saved_recog_data
, &recog_data
,
3132 sizeof (struct recog_data
));
3135 /* Restore some of the contents of global variable recog_data. */
3137 picochip_restore_recog_data (void)
3139 which_alternative
= picochip_saved_which_alternative
;
3140 memcpy (&recog_data
, &picochip_saved_recog_data
,
3141 sizeof (struct recog_data
));
3144 /* Ensure that no var tracking notes are emitted in the middle of a
3145 three-instruction bundle. */
3147 reorder_var_tracking_notes (void)
3153 rtx insn
, next
, last_insn
= NULL_RTX
;
3154 rtx vliw_start
= NULL_RTX
;
3155 rtx queue
= NULL_RTX
;
3157 /* Iterate through the bb and find the last non-debug insn */
3158 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN(BB_END (bb
)); insn
= NEXT_INSN(insn
))
3160 if (NONDEBUG_INSN_P(insn
))
3164 /* In all normal cases, queue up notes and emit them just before a TImode
3165 instruction. For the last instruction, emit the queued notes just after
3166 the last instruction. */
3167 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN(BB_END (bb
)); insn
= next
)
3169 next
= NEXT_INSN (insn
);
3171 if (insn
== last_insn
)
3175 rtx next_queue
= PREV_INSN (queue
);
3176 PREV_INSN (NEXT_INSN(insn
)) = queue
;
3177 NEXT_INSN(queue
) = NEXT_INSN(insn
);
3178 PREV_INSN(queue
) = insn
;
3179 NEXT_INSN(insn
) = queue
;
3182 /* There is no more to do for this bb. break*/
3185 else if (NONDEBUG_INSN_P (insn
))
3187 /* Emit queued up notes before the first instruction of a bundle. */
3188 if (GET_MODE (insn
) == TImode
)
3192 rtx next_queue
= PREV_INSN (queue
);
3193 NEXT_INSN (PREV_INSN(insn
)) = queue
;
3194 PREV_INSN (queue
) = PREV_INSN(insn
);
3195 PREV_INSN (insn
) = queue
;
3196 NEXT_INSN (queue
) = insn
;
3201 else if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_VAR_LOCATION
)
3203 rtx prev
= PREV_INSN (insn
);
3204 PREV_INSN (next
) = prev
;
3205 NEXT_INSN (prev
) = next
;
3206 PREV_INSN (insn
) = queue
;
3210 /* Make sure we are not dropping debug instructions.*/
3211 gcc_assert (queue
== NULL_RTX
);
3215 /* Perform machine dependent operations on the rtl chain INSNS. */
3217 picochip_reorg (void)
3219 rtx insn
, insn1
, vliw_start
= NULL_RTX
;
3220 int vliw_insn_location
= 0;
3222 /* We are freeing block_for_insn in the toplev to keep compatibility
3223 with old MDEP_REORGS that are not CFG based. Recompute it now. */
3224 compute_bb_for_insn ();
3229 if (picochip_schedule_type
!= DFA_TYPE_NONE
)
3231 timevar_push (TV_SCHED2
);
3233 /* Process the instruction list, computing the sizes of each
3234 instruction, and consequently branch distances. This can
3235 result in some branches becoming short enough to be treated
3236 as a real branch instruction, rather than an assembly branch
3237 macro which may expand into multiple instructions. The
3238 benefit of shortening branches is that real branch
3239 instructions can be properly DFA scheduled, whereas macro
3241 shorten_branches (get_insns ());
3243 /* Do control and data sched analysis again,
3244 and write some more of the results to dump file. */
3250 timevar_pop (TV_SCHED2
);
3254 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3256 /* Whenever a VLIW packet is generated, all instructions in
3257 that packet must appear to come from the same source
3258 location. The following code finds all the VLIW packets,
3259 and tags their instructions with the location of the first
3260 instruction from the packet. Clearly this will result in
3261 strange behaviour when debugging the code, but since
3262 debugging and optimisation are being used in conjunction,
3263 strange behaviour is certain to occur anyway. */
3264 /* Slight bit of change. If the vliw set contains a branch
3265 or call instruction, we pick its location.*/
3266 for (insn
= get_insns (); insn
; insn
= next_real_insn (insn
))
3269 /* If this is the first instruction in the VLIW packet,
3270 extract its location. */
3271 if (GET_MODE (insn
) == TImode
)
3274 vliw_insn_location
= INSN_LOCATOR (insn
);
3276 if (JUMP_P (insn
) || CALL_P(insn
))
3278 vliw_insn_location
= INSN_LOCATOR (insn
);
3279 for (insn1
= vliw_start
; insn1
!= insn
; insn1
= next_real_insn (insn1
))
3280 INSN_LOCATOR (insn1
) = vliw_insn_location
;
3282 /* Tag subsequent instructions with the same location. */
3283 INSN_LOCATOR (insn
) = vliw_insn_location
;
3289 /* Locate the note marking the end of the function's prologue. If
3290 the note appears in the middle of a VLIW packet, move the note to
3291 the end. This avoids unpleasant consequences such as trying to
3292 emit prologue markers (e.g., .loc/.file directives) in the middle
3294 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3296 rtx prologue_end_note
= NULL
;
3297 rtx last_insn_in_packet
= NULL
;
3299 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
3301 /* The prologue end must be moved to the end of the VLIW packet. */
3302 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_PROLOGUE_END
)
3304 prologue_end_note
= insn
;
3309 /* Find the last instruction in this packet. */
3310 for (insn
= prologue_end_note
; insn
; insn
= next_real_insn (insn
))
3312 if (GET_MODE (insn
) == TImode
)
3315 last_insn_in_packet
= insn
;
3318 if (last_insn_in_packet
!= NULL
)
3320 rtx tmp_note
= emit_note_after (NOTE_KIND(prologue_end_note
), last_insn_in_packet
);
3321 memcpy(&NOTE_DATA (tmp_note
), &NOTE_DATA(prologue_end_note
), sizeof(NOTE_DATA(prologue_end_note
)));
3322 delete_insn (prologue_end_note
);
3325 if (picochip_flag_var_tracking
)
3327 timevar_push (TV_VAR_TRACKING
);
3328 variable_tracking_main ();
3329 /* We also have to deal with variable tracking notes in the middle
3331 reorder_var_tracking_notes();
3332 timevar_pop (TV_VAR_TRACKING
);
3336 /* Return the ALU character identifier for the current
3337 instruction. This will be 0 or 1. */
3339 picochip_get_vliw_alu_id (void)
3343 /* Always use ALU 0 if VLIW scheduling is disabled. */
3344 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3347 /* Get the attribute type of the instruction. Note that this can
3348 ruin the contents of recog_data, so save/restore around the
3350 picochip_save_recog_data ();
3351 attr_type
= get_attr_type (picochip_current_prescan_insn
);
3352 picochip_restore_recog_data ();
3354 if (picochip_current_vliw_state
.contains_pico_alu_insn
)
3357 /* If this a picoAlu insn? If it is, then stuff it into ALU 0,
3358 else it must be the other ALU (either basic or nonCc)
3359 instruction which goes into 1. */
3360 if (attr_type
== TYPE_PICOALU
)
3366 else if (picochip_current_vliw_state
.contains_non_cc_alu_insn
)
3368 /* Is this the non CC instruction? If it is, then stuff it into
3369 ALU 1, else it must be a picoAlu or basicAlu, in which case
3370 it goes into ALU 0. */
3371 if (attr_type
== TYPE_NONCCALU
)
3378 /* No picoAlu/nonCc instructions in use, so purely dependent upon
3379 whether an ALU instruction has already been scheduled in this
3381 switch (picochip_current_vliw_state
.num_alu_insns_so_far
)
3384 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3388 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3392 internal_error ("Too many ALU instructions emitted (%d)\n",
3393 picochip_current_vliw_state
.num_alu_insns_so_far
);
3400 /* Reset any information about the current VLIW packing status. */
3402 picochip_reset_vliw (rtx insn
)
3404 rtx local_insn
= insn
;
3406 /* Nothing to do if VLIW scheduling isn't being used. */
3407 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3411 printf ("%s on insn %d\n", __FUNCTION__
, INSN_UID (insn
));
3414 picochip_current_vliw_state
.contains_pico_alu_insn
= 0;
3415 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 0;
3416 picochip_current_vliw_state
.num_alu_insns_so_far
= 0;
3417 picochip_current_vliw_state
.num_cfi_labels_deferred
= 0;
3418 picochip_current_vliw_state
.lm_label_name
[0] = 0;
3419 picochip_current_vliw_state
.num_insns_in_packet
= 0;
3421 /* Read through the VLIW packet, classifying the instructions where
3426 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3428 local_insn
= NEXT_INSN (local_insn
);
3431 else if (!INSN_P (local_insn
))
3435 /* It is an instruction, but is it ours? */
3436 if (INSN_CODE (local_insn
) != -1)
3440 picochip_current_vliw_state
.num_insns_in_packet
+= 1;
3442 /* Is it a picoAlu or nonCcAlu instruction? Note that the
3443 get_attr_type function can overwrite the values in
3444 the recog_data global, hence this is saved and
3445 restored around the call. Not doing so results in
3446 asm_output_opcode being called with a different
3447 instruction to final_prescan_insn, which is fatal. */
3448 picochip_save_recog_data ();
3449 attr_type
= get_attr_type (local_insn
);
3450 picochip_restore_recog_data ();
3452 if (attr_type
== TYPE_PICOALU
)
3453 picochip_current_vliw_state
.contains_pico_alu_insn
= 1;
3454 if (attr_type
== TYPE_NONCCALU
)
3455 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 1;
3460 /* Get the next instruction. */
3461 local_insn
= NEXT_INSN (local_insn
);
3463 /* Keep going while the next instruction is part of the same
3464 VLIW packet (i.e., its a valid instruction and doesn't mark
3465 the start of a new VLIW packet. */
3467 while (local_insn
&&
3468 (GET_MODE (local_insn
) != TImode
) && (INSN_CODE (local_insn
) != -1));
3473 picochip_sched_reorder (FILE * file
, int verbose
,
3474 rtx
* ready ATTRIBUTE_UNUSED
,
3475 int *n_readyp ATTRIBUTE_UNUSED
, int clock
)
3479 fprintf (file
, ";;\tClock %d\n", clock
);
3481 return picochip_sched_issue_rate ();
3486 picochip_sched_lookahead (void)
3488 /* It should always be enough to lookahead by 2 insns. Only slot0/1 could
3494 picochip_sched_issue_rate (void)
3499 /* Adjust the scheduling cost between the two given instructions,
3500 which have the given dependency. */
3502 picochip_sched_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
3507 printf ("Sched Adjust Cost: %d->%d is %d\n",
3508 INSN_UID (insn
), INSN_UID (dep_insn
), cost
);
3510 printf (" Dependency type:");
3511 switch (REG_NOTE_KIND (link
))
3519 case REG_DEP_OUTPUT
:
3520 printf ("OUTPUT\n");
3523 printf ("Unknown (%d)\n", REG_NOTE_KIND (link
));
3527 /* Anti-dependencies are used to enforce the ordering between a
3528 * branch, and any subsequent instructions. For example:
3533 * The ADD instruction must execute after the branch, and this is
3534 * enforced using an anti-dependency. Unfortunately, VLIW machines
3535 * are happy to execute anti-dependent instructions in the same
3536 * cycle, which then results in a schedule like the following being
3539 * BNE someLabel \ ADD.0 r0,r1,r2
3541 * The instruction which would normally be conditionally executed
3542 * depending upon the outcome of the branch, is now unconditionally
3543 * executed every time. To prevent this happening, any
3544 * anti-dependencies between a branch and another instruction are
3545 * promoted to become real dependencies.
3547 if ((JUMP_P (dep_insn
) || CALL_P(dep_insn
)) && REG_NOTE_KIND (link
) == REG_DEP_ANTI
)
3551 printf ("Promoting anti-dependency %d->%d to a true-dependency\n",
3552 INSN_UID (insn
), INSN_UID (dep_insn
));
3561 /* Return the minimum of the two values */
3563 minimum (int a
, int b
)
3569 /* I dont expect to get to this function with a==b.*/
3574 /* This function checks if the memory of the two stores are just off by 2 bytes.
3575 It returns the lower memory operand's index.*/
3578 memory_just_off (rtx opnd1
, rtx opnd2
)
3580 int offset1
= 0, offset2
= 0;
3583 if (GET_CODE(XEXP(opnd1
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
, 0),1)) == CONST_INT
)
3585 offset1
= INTVAL(XEXP(XEXP(opnd1
, 0), 1));
3586 reg1
= REGNO(XEXP(XEXP(opnd1
, 0), 0));
3590 reg1
= REGNO(XEXP(opnd1
, 0));
3592 if (GET_CODE(XEXP(opnd2
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
, 0), 1)) == CONST_INT
)
3594 offset2
= INTVAL(XEXP(XEXP(opnd2
, 0), 1));
3595 reg2
= REGNO(XEXP(XEXP(opnd2
, 0), 0));
3599 reg2
= REGNO(XEXP(opnd2
, 0));
3602 /* Peepholing 2 STW/LDWs has the restriction that the resulting STL/LDL's address
3603 should be 4 byte aligned. We can currently guarentee that only if the base
3604 address is FP(R13) and the offset is aligned. */
3606 if (reg1
== reg2
&& reg1
== 13 && abs(offset1
-offset2
) == 2 && minimum(offset1
, offset2
) % 4 == 0)
3607 return (minimum(offset1
, offset2
) == offset1
) ? 1:2;
3613 registers_just_off (rtx opnd1
, rtx opnd2
)
3616 reg1
= REGNO(opnd1
);
3617 reg2
= REGNO(opnd2
);
3618 if (abs(reg1
-reg2
) == 1 && minimum(reg1
, reg2
) % 2 == 0)
3619 return (minimum(reg1
, reg2
) == reg1
)?1:2;
3623 /* Check to see if the two LDWs can be peepholed together into a LDL
3624 They can be if the registers getting loaded into are contiguous
3625 and the memory addresses are contiguous as well.
3629 can be merged together into
3633 1. The LDWs themselves only guarentee that r11 will be a 2-byte
3634 aligned address. Only FP can be assumed to be 4 byte aligned.
3635 2. The progression of addresses and the register numbers should
3636 be similar. For eg., if you swap r2 and r3 in the above instructions,
3637 the resultant pair cannot be merged.
3641 ok_to_peephole_ldw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3643 int memtest
=0,regtest
=0;
3644 regtest
= registers_just_off(opnd1
,opnd3
);
3648 memtest
= memory_just_off(opnd0
,opnd2
);
3652 if (regtest
== memtest
)
3659 /* Similar to LDW peephole */
3661 ok_to_peephole_stw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3663 int memtest
=0,regtest
=0;
3664 regtest
= registers_just_off(opnd1
,opnd3
);
3668 memtest
= memory_just_off(opnd0
,opnd2
);
3672 if (regtest
== memtest
)
3680 /* Generate a SImode register with the register number that is the smaller of the two */
3682 gen_min_reg(rtx opnd1
,rtx opnd2
)
3684 return gen_rtx_REG (SImode
, minimum(REGNO(opnd1
),REGNO(opnd2
)));
3687 /* Generate a SImode memory with the address that is the smaller of the two */
3689 gen_SImode_mem(rtx opnd1
,rtx opnd2
)
3691 int offset1
=0,offset2
=0;
3694 if (GET_CODE(XEXP(opnd1
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
,0),1)) == CONST_INT
)
3696 offset1
= INTVAL(XEXP(XEXP(opnd1
,0),1));
3697 reg
= XEXP(XEXP(opnd1
,0),0);
3701 reg
= XEXP(opnd1
,0);
3703 if (GET_CODE(XEXP(opnd2
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
,0),1)) == CONST_INT
)
3705 offset2
= INTVAL(XEXP(XEXP(opnd2
,0),1));
3707 address
= gen_rtx_PLUS (HImode
, reg
, GEN_INT(minimum(offset1
,offset2
)));
3708 return gen_rtx_MEM(SImode
,address
);
3712 picochip_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
, int* total
, bool speed
)
3719 /* Need to penalize immediates that need to be encoded as long constants.*/
3720 if (code
== CONST_INT
&& !(INTVAL (x
) >= 0 && INTVAL (x
) < 16))
3722 *total
= COSTS_N_INSNS(1);
3730 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
3735 /* if_then_else come out of cbranch instructions. It will get split into
3736 a condition code generating subtraction and a branch */
3737 *total
= COSTS_N_INSNS (2);
3744 if (GET_MODE(x
) == SImode
)
3745 *total
= COSTS_N_INSNS (2);
3746 if (GET_MODE(x
) == DImode
)
3747 *total
= COSTS_N_INSNS (4);
3751 /* Byte Memory access on a NO_BYTE_ACCESS machine would be expensive */
3752 if (GET_MODE(x
) == QImode
&& !TARGET_HAS_BYTE_ACCESS
)
3753 *total
= COSTS_N_INSNS (10);
3755 /* 64-bit accesses have to be done through 2 32-bit access */
3756 if (GET_MODE(x
) == DImode
)
3757 *total
= COSTS_N_INSNS (2);
3763 /* SImode shifts are expensive */
3764 if (GET_MODE(x
) == SImode
)
3765 *total
= COSTS_N_INSNS (10);
3767 /* Register shift by constant is cheap. */
3768 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3769 && GET_CODE(XEXP(x
, 0)) == REG
3770 && GET_CODE(XEXP(x
, 1)) == CONST_INT
)
3771 *total
= COSTS_N_INSNS (1);
3773 *total
= COSTS_N_INSNS (4);
3780 /* Divisions are more expensive than the default 7*/
3781 if (GET_MODE(x
) == SImode
)
3782 *total
= COSTS_N_INSNS (20);
3784 *total
= COSTS_N_INSNS (12);
3789 /* Look for the simple cases of multiplying register*register or
3790 register*constant. */
3791 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3792 && ((GET_CODE(XEXP(x
, 0)) == REG
3793 && (GET_CODE(XEXP(x
, 1)) == REG
|| GET_CODE(XEXP(x
,1)) == CONST_INT
))
3794 || (GET_CODE(XEXP(x
, 0)) == ZERO_EXTEND
3795 && GET_CODE(XEXP(XEXP(x
, 0),0)) == REG
3796 && GET_CODE(XEXP(x
, 1)) == ZERO_EXTEND
3797 && GET_CODE(XEXP(XEXP(x
, 1),0)) == REG
)))
3800 /* When optimising for size, multiplication by constant
3801 should be discouraged slightly over multiplication by a
3803 if (picochip_has_mac_unit
)
3805 /* Single cycle multiplication, but the result must be
3806 loaded back into a general register afterwards. */
3807 *total
= COSTS_N_INSNS(2);
3810 else if (picochip_has_mul_unit
)
3812 /* Single cycle multiplication. */
3813 *total
= COSTS_N_INSNS(1);
3816 /* Else no multiply available. Use default cost. */
3826 if (localTotal
!= 0)
3828 *total
= localTotal
;
3839 picochip_final_prescan_insn (rtx insn
, rtx
* opvec ATTRIBUTE_UNUSED
,
3840 int num_operands ATTRIBUTE_UNUSED
)
3844 picochip_current_prescan_insn
= insn
;
3847 printf ("Final prescan on INSN %d with mode %s\n",
3848 INSN_UID (insn
), GET_MODE_NAME (GET_MODE (insn
)));
3850 /* If this is the start of a new instruction cycle, or no scheduling
3851 is used, then reset the VLIW status. */
3852 if (GET_MODE (insn
) == TImode
|| !picochip_schedule_type
== DFA_TYPE_SPEED
)
3853 picochip_reset_vliw (insn
);
3855 /* No VLIW scheduling occured, so don't go any further. */
3856 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3859 /* Look for the next printable instruction. This loop terminates on
3860 any recognisable instruction, and on any unrecognisable
3861 instruction with TImode. */
3863 for (local_insn
= NEXT_INSN (local_insn
); local_insn
;
3864 local_insn
= NEXT_INSN (local_insn
))
3866 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3868 else if (!INSN_P (local_insn
))
3870 else if (GET_MODE (local_insn
) == TImode
3871 || INSN_CODE (local_insn
) != -1)
3875 /* Set the continuation flag if the next instruction can be packed
3876 with the current instruction (i.e., the next instruction is
3877 valid, and isn't the start of a new cycle). */
3878 picochip_vliw_continuation
= (local_insn
&& NONDEBUG_INSN_P (local_insn
) &&
3879 (GET_MODE (local_insn
) != TImode
));
3883 /* Builtin functions. */
3884 /* Given a builtin function taking 2 operands (i.e., target + source),
3885 emit the RTL for the underlying instruction. */
3887 picochip_expand_builtin_2op (enum insn_code icode
, tree call
, rtx target
)
3891 enum machine_mode tmode
, mode0
;
3893 /* Grab the incoming argument and emit its RTL. */
3894 arg0
= CALL_EXPR_ARG (call
, 0);
3895 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3897 /* Determine the modes of the instruction operands. */
3898 tmode
= insn_data
[icode
].operand
[0].mode
;
3899 mode0
= insn_data
[icode
].operand
[1].mode
;
3901 /* Ensure that the incoming argument RTL is in a register of the
3903 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3904 op0
= copy_to_mode_reg (mode0
, op0
);
3906 /* If there isn't a suitable target, emit a target register. */
3908 || GET_MODE (target
) != tmode
3909 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3910 target
= gen_reg_rtx (tmode
);
3912 /* Emit and return the new instruction. */
3913 pat
= GEN_FCN (icode
) (target
, op0
);
3922 /* Given a builtin function taking 3 operands (i.e., target + two
3923 source), emit the RTL for the underlying instruction. */
3925 picochip_expand_builtin_3op (enum insn_code icode
, tree call
, rtx target
)
3929 enum machine_mode tmode
, mode0
, mode1
;
3931 /* Grab the function's arguments. */
3932 arg0
= CALL_EXPR_ARG (call
, 0);
3933 arg1
= CALL_EXPR_ARG (call
, 1);
3935 /* Emit rtl sequences for the function arguments. */
3936 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3937 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
3939 /* Get the mode's of each of the instruction operands. */
3940 tmode
= insn_data
[icode
].operand
[0].mode
;
3941 mode0
= insn_data
[icode
].operand
[1].mode
;
3942 mode1
= insn_data
[icode
].operand
[2].mode
;
3944 /* Ensure that each of the function argument rtl sequences are in a
3945 register of the correct mode. */
3946 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3947 op0
= copy_to_mode_reg (mode0
, op0
);
3948 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
3949 op1
= copy_to_mode_reg (mode1
, op1
);
3951 /* If no target has been given, create a register to use as the target. */
3953 || GET_MODE (target
) != tmode
3954 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3955 target
= gen_reg_rtx (tmode
);
3957 /* Emit and return the new instruction. */
3958 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
3967 /* Expand a builtin function which takes two arguments, and returns a void. */
3969 picochip_expand_builtin_2opvoid (enum insn_code icode
, tree call
)
3973 enum machine_mode mode0
, mode1
;
3975 /* Grab the function's arguments. */
3976 arg0
= CALL_EXPR_ARG (call
, 0);
3977 arg1
= CALL_EXPR_ARG (call
, 1);
3979 /* Emit rtl sequences for the function arguments. */
3980 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3981 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
3983 /* Get the mode's of each of the instruction operands. */
3984 mode0
= insn_data
[icode
].operand
[0].mode
;
3985 mode1
= insn_data
[icode
].operand
[1].mode
;
3987 /* Ensure that each of the function argument rtl sequences are in a
3988 register of the correct mode. */
3989 if (!(*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
3990 op0
= copy_to_mode_reg (mode0
, op0
);
3991 if (!(*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
3992 op1
= copy_to_mode_reg (mode1
, op1
);
3994 /* Emit and return the new instruction. */
3995 pat
= GEN_FCN (icode
) (op0
, op1
);
4004 /* Expand an array get into the corresponding RTL. */
4006 picochip_expand_array_get (tree call
, rtx target
)
4008 tree arg0
, arg1
, arg2
;
4009 rtx op0
, op1
, op2
, pat
;
4011 /* Grab the function's arguments. */
4012 arg0
= CALL_EXPR_ARG (call
, 0);
4013 arg1
= CALL_EXPR_ARG (call
, 1);
4014 arg2
= CALL_EXPR_ARG (call
, 2) ;
4016 /* Emit rtl sequences for the function arguments. */
4017 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
4018 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
4019 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
4021 /* The second and third operands must be constant. Nothing else will
4023 if (CONST_INT
!= GET_CODE (op1
))
4024 internal_error ("%s: Second source operand is not a constant",
4026 if (CONST_INT
!= GET_CODE (op2
))
4027 internal_error ("%s: Third source operand is not a constant",
4030 /* If no target has been given, create a register to use as the target. */
4031 if (target
== 0 || GET_MODE (target
) != SImode
)
4032 target
= gen_reg_rtx (SImode
);
4034 /* The first operand must be a HImode register or a constant. If it
4035 isn't, force it into a HImode register. */
4036 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
4037 op0
= copy_to_mode_reg (HImode
, op0
);
4040 /* Emit and return the new instruction. */
4041 pat
= gen_commsArrayGet (target
, op0
, op1
, op2
);
4048 /* Expand an array put into the corresponding RTL. */
4050 picochip_expand_array_put (tree call
, rtx target
)
4052 tree arg0
, arg1
, arg2
, arg3
;
4053 rtx op0
, op1
, op2
, op3
, pat
;
4055 /* Grab the function's arguments. */
4056 arg0
= CALL_EXPR_ARG (call
, 0);
4057 arg1
= CALL_EXPR_ARG (call
, 1);
4058 arg2
= CALL_EXPR_ARG (call
, 2);
4059 arg3
= CALL_EXPR_ARG (call
, 3);
4061 /* Emit rtl sequences for the function arguments. */
4062 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
4063 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
4064 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
4065 op3
= expand_expr (arg3
, NULL_RTX
, VOIDmode
, 0);
4067 /* The first operand must be an SImode register. */
4068 if (GET_MODE (op0
) != SImode
|| REG
!= GET_CODE (op0
))
4069 op0
= copy_to_mode_reg (SImode
, op0
);
4071 /* The second (index) operand must be a HImode register, or a
4072 constant. If it isn't, force it into a HImode register. */
4073 if (GET_MODE (op1
) != HImode
|| REG
!= GET_CODE (op1
))
4074 op1
= copy_to_mode_reg (HImode
, op1
);
4076 /* The remaining operands must be constant. Nothing else will do. */
4077 if (CONST_INT
!= GET_CODE (op2
))
4078 internal_error ("%s: Third source operand is not a constant",
4080 if (CONST_INT
!= GET_CODE (op3
))
4081 internal_error ("%s: Fourth source operand is not a constant",
4084 /* Emit and return the new instruction. */
4085 pat
= gen_commsArrayPut (op0
, op1
, op2
, op3
);
4092 /* Expand an array testport into the corresponding RTL. */
4094 picochip_expand_array_testport (tree call
, rtx target
)
4096 tree arg0
, arg1
, arg2
;
4097 rtx op0
, op1
, op2
, pat
;
4099 /* Grab the function's arguments. */
4100 arg0
= CALL_EXPR_ARG (call
, 0);
4101 arg1
= CALL_EXPR_ARG (call
, 1);
4102 arg2
= CALL_EXPR_ARG (call
, 2);
4104 /* Emit rtl sequences for the function arguments. */
4105 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
4106 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
4107 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
4109 /* The first operand must be a HImode register, or a constant. If it
4110 isn't, force it into a HImode register. */
4111 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
4112 op0
= copy_to_mode_reg (HImode
, op0
);
4114 /* The second and third operands must be constant. Nothing else will
4116 if (CONST_INT
!= GET_CODE (op1
))
4117 internal_error ("%s: Second source operand is not a constant",
4119 if (CONST_INT
!= GET_CODE (op2
))
4120 internal_error ("%s: Third source operand is not a constant",
4123 /* If no target has been given, create a HImode register to use as
4125 if (target
== 0 || GET_MODE (target
) != HImode
)
4126 target
= gen_reg_rtx (HImode
);
4128 /* Emit and return the new instruction. */
4129 pat
= gen_commsArrayTestPort (target
, op0
, op1
, op2
);
4136 /* Generate a unique HALT instruction by giving the instruction a
4137 unique integer. This integer makes no difference to the assembly
4138 output (other than a comment indicating the supplied id), but the
4139 presence of the unique integer prevents the compiler from combining
4140 several different halt instructions into one instruction. This
4141 means that each use of the halt instruction is unique, which in
4142 turn means that assertions work as expected. */
4144 picochip_generate_halt (void)
4146 static int currentId
= 0;
4148 rtx id
= GEN_INT (currentId
);
4152 emit_insn (gen_halt (id
));
4154 /* A barrier is inserted to prevent the compiler from thinking that
4155 it has to continue execution after the HALT.*/
4158 insns
= get_insns();
4165 /* Initialise the builtin functions. Start by initialising
4166 descriptions of different types of functions (e.g., void fn(int),
4167 int fn(void)), and then use these to define the builtins. */
4169 picochip_init_builtins (void)
4172 tree endlink
= void_list_node
;
4173 tree int_endlink
= tree_cons (NULL_TREE
, integer_type_node
, endlink
);
4174 tree unsigned_endlink
= tree_cons (NULL_TREE
, unsigned_type_node
, endlink
);
4175 tree long_endlink
= tree_cons (NULL_TREE
, long_integer_type_node
, endlink
);
4176 tree int_int_endlink
=
4177 tree_cons (NULL_TREE
, integer_type_node
, int_endlink
);
4178 tree int_int_int_endlink
=
4179 tree_cons (NULL_TREE
, integer_type_node
, int_int_endlink
);
4180 tree int_long_endlink
=
4181 tree_cons (NULL_TREE
, integer_type_node
, long_endlink
);
4182 tree pchar_type_node
= build_pointer_type (char_type_node
);
4183 tree long_int_int_int_endlink
=
4184 tree_cons (NULL_TREE
, long_integer_type_node
, int_int_int_endlink
);
4186 tree int_ftype_void
, int_ftype_int
, int_ftype_int_int
, void_ftype_pchar
;
4187 tree long_ftype_int
, long_ftype_int_int
, long_ftype_int_int_int
;
4188 tree void_ftype_int_long
, int_ftype_int_int_int
,
4189 void_ftype_long_int_int_int
;
4190 tree void_ftype_void
, void_ftype_int
, unsigned_ftype_unsigned
;
4192 /* void func (void) */
4193 void_ftype_void
= build_function_type (void_type_node
, endlink
);
4195 /* void func (void *) */
4197 = build_function_type (void_type_node
,
4198 tree_cons (NULL_TREE
, pchar_type_node
, endlink
));
4200 /* int func (void) */
4201 int_ftype_void
= build_function_type (integer_type_node
, endlink
);
4203 /* void func (int) */
4204 void_ftype_int
= build_function_type (void_type_node
, int_endlink
);
4206 /* int func (int) */
4207 int_ftype_int
= build_function_type (integer_type_node
, int_endlink
);
4209 /* unsigned int func (unsigned int) */
4210 unsigned_ftype_unsigned
= build_function_type (unsigned_type_node
, unsigned_endlink
);
4212 /* int func(int, int) */
4214 = build_function_type (integer_type_node
, int_int_endlink
);
4216 /* long func(int) */
4217 long_ftype_int
= build_function_type (long_integer_type_node
, int_endlink
);
4219 /* long func(int, int) */
4221 = build_function_type (long_integer_type_node
, int_int_endlink
);
4223 /* long func(int, int, int) */
4224 long_ftype_int_int_int
4225 = build_function_type (long_integer_type_node
, int_int_int_endlink
);
4227 /* int func(int, int, int) */
4228 int_ftype_int_int_int
4229 = build_function_type (integer_type_node
, int_int_int_endlink
);
4231 /* void func(int, long) */
4233 = build_function_type (void_type_node
, int_long_endlink
);
4235 /* void func(long, int, int, int) */
4236 void_ftype_long_int_int_int
4237 = build_function_type (void_type_node
, long_int_int_int_endlink
);
4239 /* Initialise the sign-bit-count function. */
4240 add_builtin_function ("__builtin_sbc", int_ftype_int
,
4241 PICOCHIP_BUILTIN_SBC
, BUILT_IN_MD
, NULL
,
4243 add_builtin_function ("picoSbc", int_ftype_int
, PICOCHIP_BUILTIN_SBC
,
4244 BUILT_IN_MD
, NULL
, NULL_TREE
);
4246 /* Initialise the bit reverse function. */
4247 add_builtin_function ("__builtin_brev", unsigned_ftype_unsigned
,
4248 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4250 add_builtin_function ("picoBrev", unsigned_ftype_unsigned
,
4251 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4254 /* Initialise the byte swap function. */
4255 add_builtin_function ("__builtin_byteswap", unsigned_ftype_unsigned
,
4256 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4258 add_builtin_function ("picoByteSwap", unsigned_ftype_unsigned
,
4259 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4262 /* Initialise the ASRI function (note that while this can be coded
4263 using a signed shift in C, extra scratch registers are required,
4264 which we avoid by having a direct builtin to map to the
4266 add_builtin_function ("__builtin_asri", int_ftype_int_int
,
4267 PICOCHIP_BUILTIN_ASRI
, BUILT_IN_MD
, NULL
,
4270 /* Initialise saturating addition. */
4271 add_builtin_function ("__builtin_adds", int_ftype_int_int
,
4272 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4274 add_builtin_function ("picoAdds", int_ftype_int_int
,
4275 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4278 /* Initialise saturating subtraction. */
4279 add_builtin_function ("__builtin_subs", int_ftype_int_int
,
4280 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4282 add_builtin_function ("picoSubs", int_ftype_int_int
,
4283 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4286 /* Scalar comms builtins. */
4287 add_builtin_function ("__builtin_get", long_ftype_int
,
4288 PICOCHIP_BUILTIN_GET
, BUILT_IN_MD
, NULL
,
4290 add_builtin_function ("__builtin_put", void_ftype_int_long
,
4291 PICOCHIP_BUILTIN_PUT
, BUILT_IN_MD
, NULL
,
4293 add_builtin_function ("__builtin_testport", int_ftype_int
,
4294 PICOCHIP_BUILTIN_TESTPORT
, BUILT_IN_MD
, NULL
,
4297 /* Array comms builtins. */
4298 add_builtin_function ("__builtin_put_array",
4299 void_ftype_long_int_int_int
,
4300 PICOCHIP_BUILTIN_PUT_ARRAY
, BUILT_IN_MD
, NULL
,
4302 add_builtin_function ("__builtin_get_array", long_ftype_int_int_int
,
4303 PICOCHIP_BUILTIN_GET_ARRAY
, BUILT_IN_MD
, NULL
,
4305 add_builtin_function ("__builtin_testport_array",
4306 int_ftype_int_int_int
,
4307 PICOCHIP_BUILTIN_TESTPORT_ARRAY
, BUILT_IN_MD
,
4310 /* Halt instruction. Note that the builtin function is marked as
4311 having the attribute `noreturn' so that the compiler realises
4312 that the halt stops the program dead. */
4313 noreturn
= tree_cons (get_identifier ("noreturn"), NULL
, NULL
);
4314 add_builtin_function ("__builtin_halt", void_ftype_void
,
4315 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4317 add_builtin_function ("picoHalt", void_ftype_void
,
4318 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4323 /* Expand a call to a builtin function. */
4325 picochip_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
4326 enum machine_mode mode ATTRIBUTE_UNUSED
,
4327 int ignore ATTRIBUTE_UNUSED
)
4329 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
4330 int fcode
= DECL_FUNCTION_CODE (fndecl
);
4334 case PICOCHIP_BUILTIN_ASRI
:
4335 return picochip_expand_builtin_3op (CODE_FOR_builtin_asri
, exp
,
4338 case PICOCHIP_BUILTIN_ADDS
:
4339 return picochip_expand_builtin_3op (CODE_FOR_sataddhi3
, exp
,
4342 case PICOCHIP_BUILTIN_SUBS
:
4343 return picochip_expand_builtin_3op (CODE_FOR_satsubhi3
, exp
,
4346 case PICOCHIP_BUILTIN_SBC
:
4347 return picochip_expand_builtin_2op (CODE_FOR_sbc
, exp
, target
);
4349 case PICOCHIP_BUILTIN_BREV
:
4350 return picochip_expand_builtin_2op (CODE_FOR_brev
, exp
, target
);
4352 case PICOCHIP_BUILTIN_BYTESWAP
:
4353 return picochip_expand_builtin_2op (CODE_FOR_bswaphi2
, exp
, target
);
4355 case PICOCHIP_BUILTIN_GET
:
4356 return picochip_expand_builtin_2op (CODE_FOR_commsGet
, exp
, target
);
4358 case PICOCHIP_BUILTIN_PUT
:
4359 return picochip_expand_builtin_2opvoid (CODE_FOR_commsPut
, exp
);
4361 case PICOCHIP_BUILTIN_TESTPORT
:
4362 return picochip_expand_builtin_2op (CODE_FOR_commsTestPort
, exp
,
4365 case PICOCHIP_BUILTIN_PUT_ARRAY
:
4366 return picochip_expand_array_put (exp
, target
);
4368 case PICOCHIP_BUILTIN_GET_ARRAY
:
4369 return picochip_expand_array_get (exp
, target
);
4371 case PICOCHIP_BUILTIN_TESTPORT_ARRAY
:
4372 return picochip_expand_array_testport (exp
, target
);
4374 case PICOCHIP_BUILTIN_HALT
:
4375 return picochip_generate_halt ();
4382 /* Should really do something sensible here. */
4386 /* Emit warnings. */
4388 picochip_warn_inefficient (const char *msg
)
4390 if (TARGET_INEFFICIENT_WARNINGS
)
4391 warning (OPT_minefficient_warnings
,
4392 "%s (disable warning using -mno-inefficient-warnings)", msg
);
4396 warn_of_byte_access (void)
4398 static int warned
= 0;
4402 picochip_warn_inefficient
4403 ("byte access is synthesised - consider using MUL AE");
4410 picochip_function_value (const_tree valtype
, const_tree func
,
4411 bool outgoing ATTRIBUTE_UNUSED
)
4413 enum machine_mode mode
= TYPE_MODE (valtype
);
4414 int unsignedp
= TYPE_UNSIGNED (valtype
);
4416 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
4417 just as PROMOTE_MODE does. */
4418 mode
= promote_function_mode (valtype
, mode
, &unsignedp
, func
, 1);
4420 return gen_rtx_REG (mode
, 0);
4424 /* Check that the value of the given mode will fit in the register of
4427 picochip_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
4430 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4431 return regno
== CC_REGNUM
;
4433 /* If the CC register is being used, then only CC mode values are
4434 allowed (which have already been tested). */
4435 if (regno
== CC_REGNUM
|| regno
== ACC_REGNUM
)
4438 /* Must be a valid register. */
4442 /* Modes QI and HI may be placed in any register except the CC. */
4443 if (mode
== QImode
|| mode
== HImode
)
4446 /* DI must be in a quad register. */
4448 return (regno
% 4 == 0);
4450 /* All other modes must be placed in a even numbered register. */
4451 return !(regno
& 1);
4455 /* Extract the lower and upper components of a constant value. */
4458 picochip_get_low_const (rtx value
)
4460 return gen_int_mode (INTVAL (value
) & 0xFFFF, HImode
);
4464 picochip_get_high_const (rtx value
)
4466 /*return GEN_INT ((((INTVAL (value) >> 16) & 0xFFFF) ^ 0x8000) - 0x8000); */
4467 return gen_int_mode ((INTVAL (value
) >> 16) & 0xFFFF, HImode
);
4471 /* Loading and storing QImode values to and from memory in a machine
4472 without byte access requires might require a scratch
4473 register. However, the scratch register might correspond to the
4474 register in which the value is being loaded. To ensure that a
4475 scratch register is supplied which is definitely different to the
4476 output register, request a register pair. This effectively gives a
4477 choice of two registers to choose from, so that we a guaranteed to
4478 get at least one register which is different to the output
4479 register. This trick is taken from the alpha implementation. */
4481 picochip_secondary_reload (bool in_p
,
4482 rtx x ATTRIBUTE_UNUSED
,
4483 reg_class_t cla ATTRIBUTE_UNUSED
,
4484 enum machine_mode mode
,
4485 secondary_reload_info
*sri
)
4487 if (mode
== QImode
&& !TARGET_HAS_BYTE_ACCESS
)
4490 sri
->icode
= CODE_FOR_reload_outqi
;
4492 sri
->icode
= CODE_FOR_reload_inqi
;
4495 /* We dont need to return a register class type when we need only a
4496 scratch register. It realizes the scratch register type by looking
4497 at the instruction definition for sri->icode. We only need to
4498 return the register type when we need intermediaries for copies.*/
4502 /* Return true if the given memory operand can be aligned to a
4503 word+offset memory reference (e.g., FP+3 can be converted into the
4504 memory operand FP+2, with the offset 1). */
4506 picochip_alignable_memory_operand (rtx mem_operand
,
4507 enum machine_mode mode ATTRIBUTE_UNUSED
)
4511 /* Not a mem operand. Refuse immediately. */
4512 if (MEM
!= GET_CODE (mem_operand
))
4515 address
= XEXP (mem_operand
, 0);
4517 /* Return true if a PLUS of the SP and a (valid) constant, or SP itself. */
4518 return ((PLUS
== GET_CODE (address
) &&
4519 REGNO (XEXP (address
, 0)) == STACK_POINTER_REGNUM
&&
4520 CONST_INT
== GET_CODE (XEXP (address
, 1)) &&
4521 picochip_const_ok_for_letter_p (INTVAL (XEXP (address
, 1)), 'K'))
4522 || (REG
== GET_CODE (address
)
4523 && REGNO (address
) == STACK_POINTER_REGNUM
));
4527 /* Return true if the given memory reference is to a word aligned
4528 address. Currently this means it must be either SP, or
4529 SP+offset. We could replace this function with alignable
4530 memory references in the above function?. */
4532 picochip_word_aligned_memory_reference (rtx operand
)
4536 /* The address must be the SP register, or a constant, aligned
4537 offset from SP which doesn't exceed the FP+offset
4539 return ((PLUS
== GET_CODE (operand
)
4540 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
4541 && picochip_is_aligned (INTVAL (XEXP (operand
, 1)), 16)
4542 && picochip_const_ok_for_letter_p (INTVAL (XEXP (operand
, 1)),
4544 || (REG
== GET_CODE (operand
)
4545 && REGNO (operand
) == STACK_POINTER_REGNUM
));
4549 /* Given an alignable memory location, convert the memory location
4550 into a HI mode access, storing the new memory reference in
4551 paligned_mem, and the number of bits by which to shift in pbitnum
4552 (i.e., given a reference to FP+3, this creates an aligned reference
4553 of FP+2, with an 8-bit shift). This code is a modification of that
4554 found in the Alpha port. */
4556 picochip_get_hi_aligned_mem (rtx ref
, rtx
* paligned_mem
, rtx
* pbitnum
)
4559 HOST_WIDE_INT offset
= 0;
4561 gcc_assert (GET_CODE (ref
) == MEM
);
4563 if (reload_in_progress
&& !memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
4565 base
= find_replacement (&XEXP (ref
, 0));
4567 gcc_assert(memory_address_p (GET_MODE (ref
), base
));
4571 base
= XEXP (ref
, 0);
4574 if (GET_CODE (base
) == PLUS
)
4576 offset
+= INTVAL (XEXP (base
, 1));
4577 base
= XEXP (base
, 0);
4580 *paligned_mem
= widen_memory_access (ref
, HImode
, (offset
& ~1) - offset
);
4587 ("Found non-zero offset in get_hi_aligned_mem - check that the correct value is being used (as this functionality hasn't been exploited yet).\n");
4591 *pbitnum
= GEN_INT ((offset
& 1) * 8);
4595 /* Return true if the given operand is an absolute address in memory
4596 (i.e., a symbolic offset). */
4598 picochip_absolute_memory_operand (rtx op
,
4599 enum machine_mode mode ATTRIBUTE_UNUSED
)
4602 if (MEM
== GET_CODE (op
))
4604 rtx address
= XEXP (op
, 0);
4606 /* Symbols are valid absolute addresses. */
4607 if (SYMBOL_REF
== GET_CODE (address
))
4610 /* Constant offsets to symbols are valid absolute addresses. */
4611 if (CONST
== GET_CODE (address
) &&
4612 PLUS
== GET_CODE (XEXP (address
, 0)) &&
4613 SYMBOL_REF
== GET_CODE (XEXP (XEXP (address
, 0), 0)) &&
4614 CONST_INT
== GET_CODE (XEXP (XEXP (address
, 0), 1)))
4621 /* Symbols are valid absolute addresses. */
4622 if (SYMBOL_REF
== GET_CODE (XEXP (op
, 0)))
4631 picochip_asm_named_section (const char *name
,
4632 unsigned int flags ATTRIBUTE_UNUSED
,
4633 tree decl ATTRIBUTE_UNUSED
)
4635 fprintf (asm_out_file
, ".section %s\n", name
);
4639 /* Check if we can make a conditional copy instruction. This is emitted as an
4640 instruction to set the condition register, followed by an instruction which
4641 uses the condition registers to perform the conditional move. */
4643 picochip_check_conditional_copy (rtx
* operands
)
4646 rtx branch_op_0
= XEXP (operands
[1], 0);
4647 rtx branch_op_1
= XEXP (operands
[1], 1);
4649 /* Only HI mode conditional moves are currently allowed. Can we add
4651 if (GET_CODE (operands
[1]) != EQ
&& GET_CODE (operands
[1]) != NE
)
4654 /* Is the comparison valid? Only allow operands which are registers
4655 if they are HImode. SI mode comparisons against 0 could be
4656 handled using logical operations (e.g., SIreg != 0 when low ||
4657 high). Need to find test cases to provoke this though (fixunssfdi
4658 in libgcc does, but is complicated). */
4659 if (register_operand(branch_op_0
, GET_MODE(branch_op_0
)) &&
4660 GET_MODE(branch_op_0
) != HImode
)
4662 if (register_operand(branch_op_1
, GET_MODE(branch_op_1
)) &&
4663 GET_MODE(branch_op_1
) != HImode
)
4672 picochip_static_chain (const_tree
ARG_UNUSED (fndecl
), bool incoming_p
)
4676 addr
= arg_pointer_rtx
;
4678 addr
= plus_constant (stack_pointer_rtx
, -2 * UNITS_PER_WORD
);
4679 return gen_frame_mem (Pmode
, addr
);