1 /* Subroutines used for code generation on picoChip processors.
2 Copyright (C) 2001,2008, 2009 Free Software Foundation, Inc.
3 Contributed by picoChip Designs Ltd. (http://www.picochip.com)
4 Maintained by Daniel Towner (daniel.towner@picochip.com) and
5 Hariharan Sandanagobalane (hariharan@picochip.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not, see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
42 #include "basic-block.h"
43 #include "integrate.h"
49 #include "target-def.h"
50 #include "langhooks.h"
54 #include "picochip-protos.h"
56 #include "insn-attr.h" /* For DFA state_t. */
57 #include "insn-config.h" /* Required by recog.h */
58 #include "insn-codes.h" /* For CODE_FOR_? */
59 #include "optabs.h" /* For GEN_FCN */
60 #include "basic-block.h" /* UPDATE_LIFE_GLOBAL* for picochip_reorg. */
61 #include "timevar.h" /* For TV_SCHED2, in picochip_reorg. */
62 #include "libfuncs.h" /* For memcpy_libfuncs, etc. */
63 #include "df.h" /* For df_regs_ever_live_df_regs_ever_live_pp, etc. */
66 /* Target AE ISA information. */
67 enum picochip_dfa_type picochip_schedule_type
;
69 bool picochip_has_mul_unit
= false;
70 bool picochip_has_mac_unit
= false;
72 /* targetm hook function prototypes. */
74 void picochip_asm_file_start (void);
75 void picochip_asm_file_end (void);
77 void picochip_init_libfuncs (void);
78 void picochip_reorg (void);
80 int picochip_arg_partial_bytes (CUMULATIVE_ARGS
* p_cum
,
81 enum machine_mode mode
,
82 tree type
, bool named
);
84 int picochip_sched_lookahead (void);
85 int picochip_sched_issue_rate (void);
86 int picochip_sched_adjust_cost (rtx insn
, rtx link
,
87 rtx dep_insn
, int cost
);
88 int picochip_sched_reorder (FILE * file
, int verbose
, rtx
* ready
,
89 int *n_readyp
, int clock
);
91 void picochip_init_builtins (void);
92 rtx
picochip_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
94 bool picochip_rtx_costs (rtx x
, int code
, int outer_code
, int* total
, bool speed
);
95 bool picochip_return_in_memory(const_tree type
,
96 const_tree fntype ATTRIBUTE_UNUSED
);
97 bool picochip_legitimate_address_p (enum machine_mode
, rtx
, bool);
98 rtx
picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
99 enum machine_mode mode
);
100 int picochip_legitimize_reload_address (rtx
*x
, enum machine_mode mode
,
101 int opnum
, int type
, int ind_levels
);
103 rtx
picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED
, int incoming ATTRIBUTE_UNUSED
);
104 rtx
picochip_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
105 bool outgoing ATTRIBUTE_UNUSED
);
107 picochip_secondary_reload (bool in_p
,
108 rtx x ATTRIBUTE_UNUSED
,
109 enum reg_class cla ATTRIBUTE_UNUSED
,
110 enum machine_mode mode
,
111 secondary_reload_info
*sri
);
113 picochip_asm_named_section (const char *name
,
114 unsigned int flags ATTRIBUTE_UNUSED
,
115 tree decl ATTRIBUTE_UNUSED
);
117 static rtx
picochip_static_chain (const_tree
, bool);
119 /* Lookup table mapping a register number to the earliest containing
120 class. Used by REGNO_REG_CLASS. */
121 const enum reg_class picochip_regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
123 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
124 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
125 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
126 GR_REGS
, FRAME_REGS
, PTR_REGS
, CONST_REGS
,
127 ACC_REGS
, CC_REGS
, GR_REGS
, GR_REGS
130 /* picoChip register names. */
131 const char *picochip_regnames
[] = REGISTER_NAMES
;
133 /* Define the maximum number of registers which may be used to pass
134 * parameters to functions. */
135 #define MAX_CALL_PARAMETER_REGS 6
138 /* Target scheduling information. */
140 /* Determine whether we run our final scheduling pass or not. We always
141 avoid the normal second scheduling pass. */
142 int picochip_flag_schedule_insns2
;
144 /* Check if variable tracking needs to be run. */
145 int picochip_flag_var_tracking
;
147 /* This flag indicates whether the next instruction to be output is a
148 VLIW continuation instruction. It is used to communicate between
149 final_prescan_insn and asm_output_opcode. */
150 static int picochip_vliw_continuation
= 0;
152 /* This variable is used to communicate the current instruction
153 between final_prescan_insn and functions such as asm_output_opcode,
154 and picochip_get_vliw_alu_id (which are otherwise unable to determine the
155 current instruction. */
156 static rtx picochip_current_prescan_insn
;
158 static bool picochip_is_delay_slot_pending
= 0;
160 /* When final_prescan_insn is called, it computes information about
161 the current VLIW packet, and stores it in this structure. When
162 instructions are output, this state is used to make sure that the
163 instructions are output in the correct way (e.g., which ALU to use,
164 whether a macro branch was ever previously a real branch, etc.). */
167 int contains_pico_alu_insn
;
168 int contains_non_cc_alu_insn
;
169 int num_alu_insns_so_far
;
171 /* Record how many instructions are contained in the packet. */
172 int num_insns_in_packet
;
174 /* There was a case for this to be more than 1 */
175 int num_cfi_labels_deferred
;
176 char cfi_label_name
[2][256]; /* Used to record the name of a CFI label
177 emitted inside a VLIW packet. */
178 char lm_label_name
[256]; /* Used to record the name of an LM label. */
181 struct vliw_state picochip_current_vliw_state
;
183 /* Save/restore recog_data. */
184 static int picochip_saved_which_alternative
;
185 static struct recog_data picochip_saved_recog_data
;
187 /* Determine which ALU to use for the instruction in
188 picochip_current_prescan_insn. */
189 static char picochip_get_vliw_alu_id (void);
191 /* Initialize the GCC target structure. */
193 #undef TARGET_ASM_FUNCTION_PROLOGUE
194 #define TARGET_ASM_FUNCTION_PROLOGUE picochip_function_prologue
196 #undef TARGET_ASM_FUNCTION_EPILOGUE
197 #define TARGET_ASM_FUNCTION_EPILOGUE picochip_function_epilogue
199 #undef TARGET_ASM_INTERNAL_LABEL
200 #define TARGET_ASM_INTERNAL_LABEL picochip_output_internal_label
202 #undef TARGET_ASM_GLOBALIZE_LABEL
203 #define TARGET_ASM_GLOBALIZE_LABEL picochip_output_global
205 #undef TARGET_ASM_BYTE_OP
206 #define TARGET_ASM_BYTE_OP ".initByte "
207 #undef TARGET_ASM_ALIGNED_HI_OP
208 #define TARGET_ASM_ALIGNED_HI_OP ".initWord "
209 #undef TARGET_ASM_UNALIGNED_HI_OP
210 #define TARGET_ASM_UNALIGNED_HI_OP ".unalignedInitWord "
211 #undef TARGET_ASM_ALIGNED_SI_OP
212 #define TARGET_ASM_ALIGNED_SI_OP ".initLong "
213 #undef TARGET_ASM_UNALIGNED_SI_OP
214 #define TARGET_ASM_UNALIGNED_SI_OP ".unalignedInitLong "
216 #undef TARGET_INIT_BUILTINS
217 #define TARGET_INIT_BUILTINS picochip_init_builtins
219 #undef TARGET_EXPAND_BUILTIN
220 #define TARGET_EXPAND_BUILTIN picochip_expand_builtin
222 #undef TARGET_RTX_COSTS
223 #define TARGET_RTX_COSTS picochip_rtx_costs
225 #undef TARGET_SCHED_ISSUE_RATE
226 #define TARGET_SCHED_ISSUE_RATE picochip_sched_issue_rate
228 #undef TARGET_SCHED_REORDER
229 #define TARGET_SCHED_REORDER picochip_sched_reorder
231 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
232 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
233 picochip_sched_lookahead
235 #undef TARGET_SCHED_ADJUST_COST
236 #define TARGET_SCHED_ADJUST_COST picochip_sched_adjust_cost
238 #undef TARGET_ASM_NAMED_SECTION
239 #define TARGET_ASM_NAMED_SECTION picochip_asm_named_section
241 #undef TARGET_HAVE_NAMED_SECTIONS
242 #define TARGET_HAVE_NAMED_SECTIONS 1
244 #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
245 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS 1
247 #undef TARGET_INIT_LIBFUNCS
248 #define TARGET_INIT_LIBFUNCS picochip_init_libfuncs
250 #undef TARGET_ASM_FILE_START
251 #define TARGET_ASM_FILE_START picochip_asm_file_start
253 #undef TARGET_ASM_FILE_END
254 #define TARGET_ASM_FILE_END picochip_asm_file_end
256 #undef TARGET_MACHINE_DEPENDENT_REORG
257 #define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg
259 #undef TARGET_ARG_PARTIAL_BYTES
260 #define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes
262 #undef TARGET_PROMOTE_FUNCTION_MODE
263 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
264 #undef TARGET_PROMOTE_PROTOTYPES
265 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
267 /* Target support for Anchored Addresses optimization */
268 #undef TARGET_MIN_ANCHOR_OFFSET
269 #define TARGET_MIN_ANCHOR_OFFSET 0
270 #undef TARGET_MAX_ANCHOR_OFFSET
271 #define TARGET_MAX_ANCHOR_OFFSET 7
272 #undef TARGET_ASM_OUTPUT_ANCHOR
273 #define TARGET_ASM_OUTPUT_ANCHOR picochip_asm_output_anchor
275 #undef TARGET_FUNCTION_VALUE
276 #define TARGET_FUNCTION_VALUE picochip_function_value
278 #undef TARGET_LIBGCC_CMP_RETURN_MODE
279 #define TARGET_LIBGCC_CMP_RETURN_MODE picochip_libgcc_cmp_return_mode
282 #undef TARGET_LEGITIMATE_ADDRESS_P
283 #define TARGET_LEGITIMATE_ADDRESS_P picochip_legitimate_address_p
285 #undef TARGET_LEGITIMIZE_ADDRESS
286 #define TARGET_LEGITIMIZE_ADDRESS picochip_legitimize_address
288 /* Loading and storing QImode values to and from memory
289 usually requires a scratch register. */
290 #undef TARGET_SECONDARY_RELOAD
291 #define TARGET_SECONDARY_RELOAD picochip_secondary_reload
292 #undef DONT_USE_BUILTIN_SETJMP
293 #define DONT_USE_BUILTIN_SETJMP 1
295 /* How Large Values are Returned */
297 #undef TARGET_RETURN_IN_MEMORY
298 #define TARGET_RETURN_IN_MEMORY picochip_return_in_memory
300 #undef TARGET_STATIC_CHAIN
301 #define TARGET_STATIC_CHAIN picochip_static_chain
303 struct gcc_target targetm
= TARGET_INITIALIZER
;
306 /* Only return a value in memory if it is greater than 4 bytes.
307 int_size_in_bytes returns -1 for variable size objects, which go in
308 memory always. The cast to unsigned makes -1 > 8. */
311 picochip_return_in_memory(const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
313 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 4);
316 /* Allow certain command options to be overriden. */
318 picochip_override_options (void)
320 /* If we are optimizing for stack, dont let inliner to inline functions
321 that could potentially increase stack size.*/
322 if (flag_conserve_stack
)
324 PARAM_VALUE (PARAM_LARGE_STACK_FRAME
) = 0;
325 PARAM_VALUE (PARAM_STACK_FRAME_GROWTH
) = 0;
328 /* Turn off the elimination of unused types. The elaborator
329 generates various interesting types to represent constants,
330 generics, and so on, and it is useful to retain this information
331 in the debug output. The increased size of the debug information
332 is not really an issue for us. */
333 flag_eliminate_unused_debug_types
= 0;
335 /* Even if the user specifies a -fno-omit-frame-pointer on the
336 command line, we still want to go ahead and omit frame pointer
337 usages, since we dont really have a frame pointer register.
338 So, all accesses to FP need to be converted to accesses off
340 flag_omit_frame_pointer
= 1;
342 /* Turning on anchored addresses by default. This is an optimization
343 that could decrease the code size by placing anchors in data and
344 accessing offsets from the anchor for file local data variables.*/
346 flag_section_anchors
= 1;
348 /* Turn off the second scheduling pass, and move it to
349 picochip_reorg, to avoid having the second jump optimisation
350 trash the instruction modes (e.g., instructions are changed to
351 TImode to mark the beginning of cycles). Two types of DFA
352 scheduling are possible: space and speed. In both cases,
353 instructions are reordered to avoid stalls (e.g., memory loads
354 stall for one cycle). Speed scheduling will also enable VLIW
355 instruction packing. VLIW instructions use more code space, so
356 VLIW scheduling is disabled when scheduling for size. */
357 picochip_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
358 flag_schedule_insns_after_reload
= 0;
359 if (picochip_flag_schedule_insns2
)
363 picochip_schedule_type
= DFA_TYPE_SPACE
;
366 picochip_schedule_type
= DFA_TYPE_SPEED
;
367 flag_delayed_branch
= 0;
372 picochip_schedule_type
= DFA_TYPE_NONE
;
374 /* Ensure that the debug level is always at least -g2. The flow
375 analyser works at its best if it always has debug
376 information. DWARF is non-intrusive, so it makes no difference to
377 code quality if debug is always enabled. */
378 if (debug_info_level
< DINFO_LEVEL_NORMAL
)
380 debug_info_level
= DINFO_LEVEL_NORMAL
;
381 write_symbols
= DWARF2_DEBUG
;
384 /* Options of the form -mae=mac, and so on will be substituted by
385 the compiler driver for the appropriate byte access and multiply
386 unit ISA options. Any unrecognised AE types will end up being
387 passed to the compiler, which should reject them as invalid. */
388 if (picochip_ae_type_string
!= NULL
)
389 error ("invalid AE type specified (%s)\n", picochip_ae_type_string
);
391 /* Override any specific capabilities of the instruction set. These
392 take precedence over any capabilities inferred from the AE type,
393 regardless of where the options appear on the command line. */
394 if (picochip_mul_type_string
== NULL
)
396 /* Default to MEM-type multiply, for historical compatibility. */
397 picochip_has_mac_unit
= false;
398 picochip_has_mul_unit
= true;
402 picochip_has_mac_unit
= false;
403 picochip_has_mul_unit
= false;
405 if (strcmp (picochip_mul_type_string
, "mul") == 0)
406 picochip_has_mul_unit
= true;
407 else if (strcmp (picochip_mul_type_string
, "mac") == 0)
408 picochip_has_mac_unit
= true;
409 else if (strcmp (picochip_mul_type_string
, "none") == 0)
410 { /* Do nothing. Unit types already set to false. */ }
412 error ("Invalid mul type specified (%s) - expected mac, mul or none",
413 picochip_mul_type_string
);
419 /* Initialise the library functions to handle arithmetic on some of
422 picochip_init_libfuncs (void)
425 set_optab_libfunc (ashr_optab
, DImode
, "__ashrdi3");
426 set_optab_libfunc (ashl_optab
, DImode
, "__ashldi3");
427 set_optab_libfunc (lshr_optab
, DImode
, "__lshrdi3");
429 /* 64-bit signed multiplication. */
430 set_optab_libfunc (smul_optab
, DImode
, "__muldi3");
432 /* Signed division */
433 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
434 set_optab_libfunc (sdiv_optab
, DImode
, "__divdi3");
437 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
438 set_optab_libfunc (smod_optab
, DImode
, "__moddi3");
440 /* 32-bit count leading Zeros*/
441 set_optab_libfunc (clz_optab
, SImode
, "_clzsi2");
443 /* 64-bit comparison */
444 set_optab_libfunc (ucmp_optab
, DImode
, "__ucmpdi2");
445 set_optab_libfunc (cmp_optab
, DImode
, "__cmpdi2");
447 /* 64-bit addition and subtraction*/
448 set_optab_libfunc (add_optab
, DImode
, "_adddi3");
449 set_optab_libfunc (sub_optab
, DImode
, "_subdi3");
452 /* Return the register class for letter C. */
454 picochip_reg_class_from_letter (unsigned c
)
472 pico_leaf_reg_alloc_order
[] = LEAF_REG_ALLOC_ORDER
;
474 pico_nonleaf_reg_alloc_order
[] = REG_ALLOC_ORDER
;
477 picochip_order_regs_for_local_alloc (void)
479 /* We change the order for leaf functions alone. We put r12 at
480 the end since using it will prevent us to combine stw/ldws to
481 stl/ldl and it gives no benefit. In non-leaf functions, we
482 would anyway saveup/restore r12, so it makes sense to use it.*/
484 if (leaf_function_p())
486 memcpy ((char *)reg_alloc_order
, (const char *) pico_leaf_reg_alloc_order
,
487 FIRST_PSEUDO_REGISTER
* sizeof (int));
491 memcpy ((char *)reg_alloc_order
, (const char *) pico_nonleaf_reg_alloc_order
,
492 FIRST_PSEUDO_REGISTER
* sizeof (int));
496 /* Check that VALUE (an INT_CST) is ok as a constant of type C. */
498 picochip_const_ok_for_letter_p (unsigned HOST_WIDE_INT value
, unsigned c
)
503 case 'I': /* 4 bits signed. */
504 return value
+ 8 < 16;
505 case 'J': /* 4 bits unsigned. */
507 case 'K': /* 8 bits signed. */
508 return value
+ 128 < 256;
509 case 'M': /* 4-bit magnitude. */
510 return abs (value
) < 16;
511 case 'N': /* 10 bits signed. */
512 return value
+ 512 > 1024;
513 case 'O': /* 16 bits signed. */
514 return value
+ 32768 < 65536;
515 default: /* Unknown letter. */
520 /* Stack utility functions. */
522 picochip_return_addr_rtx(int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
525 return gen_rtx_REG (Pmode
, LINK_REGNUM
);
531 /* Emit a set of parallel register expressions used to store
532 blockmode values to pass to functions. */
534 picochip_emit_register_parallel (int size_in_units
, int offset
)
538 rtx vector
[MAX_CALL_PARAMETER_REGS
];
542 /* Compute the base register, and number of required registers. */
543 base_reg
= offset
/ 2;
544 num_regs
= size_in_units
/ 2;
545 if (size_in_units
% 2 == 1)
548 /* Emit a register for each part of the block mode value to be
549 passed in a register. */
550 for (i
= 0; i
< num_regs
; i
++)
551 vector
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
552 gen_rtx_REG (HImode
, base_reg
+ i
),
554 result
= gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (num_regs
, vector
));
560 /* Emit an instruction to allocate a suitable amount of space on the
561 stack, by decrementing the stack pointer. */
563 picochip_emit_stack_allocate (int adjustment
)
566 rtx stack_pointer_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
568 /* Use an addition of a negative value. */
569 insn
= emit_insn (gen_addhi3 (stack_pointer_reg
, stack_pointer_reg
,
570 GEN_INT (-adjustment
)));
572 /* Make the instruction frame related. Also add an expression note,
573 so that the correct Dwarf information is generated (see documention
574 for RTX_FRAME_RELATED_P for more details). */
575 RTX_FRAME_RELATED_P (insn
) = 1;
577 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
578 gen_rtx_SET (VOIDmode
, stack_pointer_reg
,
579 gen_rtx_PLUS (Pmode
, stack_pointer_reg
,
580 GEN_INT (-adjustment
))),
585 /* Emit an instruction to save a register of the given mode. The
586 offset at which to save the register is given relative to the stack
589 picochip_emit_save_register (rtx reg
, int offset
)
591 rtx stack_pointer
, address
, mem
, insn
;
593 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
595 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
597 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
599 insn
= emit_move_insn (mem
, reg
);
600 RTX_FRAME_RELATED_P (insn
) = 1;
602 /* For modes other than HImode, create a note explaining that
603 multiple registers have been saved. This allows the correct DWARF
604 call frame information to be generated. */
605 switch (GET_MODE (reg
))
608 /* The RTL is sufficient to explain HImode register saves. */
612 /* SImode must be broken down into parallel HImode register saves. */
620 gen_rtx_PLUS (Pmode
, stack_pointer
,
622 gen_rtx_REG (HImode
, REGNO (reg
)));
623 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 0)) = 1;
626 gen_rtx_SET (HImode
, gen_rtx_MEM (HImode
,
631 gen_rtx_REG (HImode
, REGNO (reg
) + 1));
632 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 1)) = 1;
635 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
636 gen_rtx_PARALLEL (VOIDmode
, p
),
644 ("unexpected mode %s encountered in picochip_emit_save_register\n",
645 GET_MODE_NAME (GET_MODE (reg
)));
650 /* Emit an instruction to restore a register of the given mode. The
651 offset from which to restore the register is given relative to the
654 picochip_emit_restore_register (rtx reg
, int offset
)
656 rtx stack_pointer
, address
, mem
, insn
;
658 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
660 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
662 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
664 insn
= emit_move_insn (reg
, mem
);
668 /* Check that the given byte offset is aligned to the given number of
671 picochip_is_aligned (int byte_offset
, int bit_alignment
)
673 int byte_alignment
= bit_alignment
/ BITS_PER_UNIT
;
674 return (byte_offset
% byte_alignment
) == 0;
677 /*****************************************************************************
680 * The following section contains code which controls how the stack is
683 * The stack is laid out as follows (high addresses first):
686 * Pretend arguments (ARG PTR)
690 * Outgoing arguments (SP)
692 * The (constant) offsets of the different areas must be calculated
693 * relative to the stack area immediately below, and aligned
694 * appropriately. For example, the frame offset is computed by
695 * determining the offset of the special register area, adding the
696 * size of the special register area, and then aligning the resulting
697 * offset correctly. In turn, the special register offset is computed
698 * from the general register offset, and so on. This enables the
699 * different offsets to change size and alignment, without requiring
700 * the code for other offset calculations to be rewritten.
702 * The argument pointer, and the frame pointer are eliminated wherever
703 * possible, by replacing them with a constant offset from the stack
704 * pointer. In the rare cases where constant offsets from the stack
705 * pointer cannot be computed, another register will be allocated to
706 * serve as the argument pointer, or the frame pointer.
708 * The save registers are stored at small offsets from the caller, to
709 * enable the more efficient SP-based ISA instructions to be used.
711 ****************************************************************************/
713 /* Compute the size of an argument in units. */
715 picochip_compute_arg_size (tree type
, enum machine_mode mode
)
717 int type_size_in_units
= 0;
720 type_size_in_units
= tree_low_cst (TYPE_SIZE_UNIT (type
), 1);
722 type_size_in_units
= GET_MODE_SIZE (mode
);
724 return type_size_in_units
;
728 /* Determine where the next outgoing arg should be placed. */
730 picochip_function_arg (CUMULATIVE_ARGS cum
, int mode
, tree type
,
731 int named ATTRIBUTE_UNUSED
)
734 int type_align_in_units
= 0;
735 int type_size_in_units
;
737 int offset_overflow
= 0;
739 /* VOIDmode is passed when computing the second argument to a `call'
740 pattern. This can be ignored. */
741 if (mode
== VOIDmode
)
744 /* Compute the alignment and size of the parameter. */
745 type_align_in_units
=
746 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
747 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
749 /* Compute the correct offset (i.e., ensure that the offset meets
750 the alignment requirements). */
751 offset_overflow
= cum
% type_align_in_units
;
752 if (offset_overflow
== 0)
755 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
759 printf ("Function arg:\n");
760 printf (" Type valid: %s\n", (type
? "yes" : "no"));
761 printf (" Cumulative Value: %d\n", cum
);
762 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
763 printf (" Type size: %i units\n", type_size_in_units
);
764 printf (" Alignment: %i units\n", type_align_in_units
);
765 printf (" New offset: %i\n", new_offset
);
769 /* If the new offset is outside the register space, return. */
770 if (new_offset
>= MAX_CALL_PARAMETER_REGS
* 2)
773 /* If the end of the argument is outside the register space, then
774 the argument must overlap the register space. Return the first
775 available register. */
776 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
777 return gen_rtx_REG (HImode
, new_offset
/ 2);
779 /* Create a register of the required mode to hold the parameter. */
780 reg
= new_offset
/ 2;
795 return gen_rtx_REG ((enum machine_mode
) mode
, reg
);
799 /* Empty blockmode values can be passed as arguments (e.g.,
800 * empty structs). These require no registers
801 * whatsoever. Non-empty blockmode values are passed in a set
802 * of parallel registers. */
803 if (type_size_in_units
== 0)
806 return picochip_emit_register_parallel (type_size_in_units
, new_offset
);
811 (0, "Defaulting to stack for %s register creation\n",
812 GET_MODE_NAME (mode
));
820 /* Determine where the next incoming function argument will
821 appear. Normally, this works in exactly the same way as
822 picochip_function_arg, except when the function in question is a
823 varadic function. In this case, the incoming arguments all appear
824 to be passed on the stack (actually, some of the arguments are
825 passed in registers, which are then pushed onto the stack by the
826 function prologue). */
828 picochip_incoming_function_arg (CUMULATIVE_ARGS cum
, int mode
,
829 tree type
, int named
)
835 return picochip_function_arg (cum
, mode
, type
, named
);
839 /* Gives the alignment boundary, in bits, of an argument with the
842 picochip_get_function_arg_boundary (enum machine_mode mode
)
847 align
= STACK_BOUNDARY
;
849 align
= GET_MODE_ALIGNMENT (mode
);
851 if (align
< PARM_BOUNDARY
)
852 align
= PARM_BOUNDARY
;
858 /* Compute partial registers. */
860 picochip_arg_partial_bytes (CUMULATIVE_ARGS
* p_cum
, enum machine_mode mode
,
861 tree type
, bool named ATTRIBUTE_UNUSED
)
863 int type_align_in_units
= 0;
864 int type_size_in_units
;
866 int offset_overflow
= 0;
868 unsigned cum
= *((unsigned *) p_cum
);
870 /* VOIDmode is passed when computing the second argument to a `call'
871 pattern. This can be ignored. */
872 if (mode
== VOIDmode
)
875 /* Compute the alignment and size of the parameter. */
876 type_align_in_units
=
877 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
878 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
880 /* Compute the correct offset (i.e., ensure that the offset meets
881 the alignment requirements). */
882 offset_overflow
= cum
% type_align_in_units
;
883 if (offset_overflow
== 0)
886 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
890 printf ("Partial function arg nregs:\n");
891 printf (" Type valid: %s\n", (type
? "yes" : "no"));
892 printf (" Cumulative Value: %d\n", cum
);
893 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
894 printf (" Type size: %i units\n", type_size_in_units
);
895 printf (" Alignment: %i units\n", type_align_in_units
);
896 printf (" New offset: %i\n", new_offset
);
900 /* If the new offset is outside the register space, return. */
901 if (new_offset
>= (MAX_CALL_PARAMETER_REGS
* 2))
904 /* If the end of the argument is outside the register space, then
905 the argument must overlap the register space. Return the number
906 of bytes which are passed in registers. */
907 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
908 return ((MAX_CALL_PARAMETER_REGS
* 2) - new_offset
);
914 /* Advance the cumulative args counter, returning the new counter. */
916 picochip_arg_advance (const CUMULATIVE_ARGS cum
, int mode
,
917 tree type
, int named ATTRIBUTE_UNUSED
)
919 int type_align_in_units
= 0;
920 int type_size_in_units
;
922 int offset_overflow
= 0;
924 /* VOIDmode is passed when computing the second argument to a `call'
925 pattern. This can be ignored. */
926 if (mode
== VOIDmode
)
929 /* Compute the alignment and size of the parameter. */
930 type_align_in_units
=
931 picochip_get_function_arg_boundary (mode
) / BITS_PER_UNIT
;
932 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
934 /* Compute the correct offset (i.e., ensure that the offset meets
935 the alignment requirements). */
936 offset_overflow
= cum
% type_align_in_units
;
937 if (offset_overflow
== 0)
940 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
942 /* Advance past the last argument. */
943 new_offset
+= type_size_in_units
;
949 /* Determine whether a register needs saving/restoring. It does if it
950 is live in a function, and isn't a call-used register. */
952 picochip_reg_needs_saving (int reg_num
)
954 return df_regs_ever_live_p(reg_num
) && !call_used_regs
[reg_num
];
957 /* Compute and return offset of the main frame. */
959 picochip_frame_byte_offset (void)
961 gcc_assert(picochip_is_aligned
962 (crtl
->outgoing_args_size
, BITS_PER_WORD
));
964 return crtl
->outgoing_args_size
;
967 /* Return the size of the main frame. */
969 picochip_frame_size_in_bytes (void)
971 int frame_size
= get_frame_size();
972 int stack_align
= STACK_BOUNDARY
/BITS_PER_UNIT
;
973 if (!picochip_is_aligned (frame_size
, STACK_BOUNDARY
))
974 frame_size
= frame_size
+ (stack_align
- frame_size
%stack_align
);
975 gcc_assert(picochip_is_aligned (frame_size
, STACK_BOUNDARY
));
979 /* Compute and return the size (in bytes) of the register save/restore
980 area for the current function. This only includes the general
981 purpose registers - the special purpose stack pointer and link
982 registers are not included in this area. */
984 picochip_save_area_size_in_bytes (void)
986 int num_regs_to_save
= 0;
989 /* Read through all the registers, determining which need to be saved. */
990 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
992 if (picochip_reg_needs_saving (i
))
993 num_regs_to_save
+= 1;
996 return num_regs_to_save
* UNITS_PER_WORD
;
1000 /* Compute and return offset of the save area base. */
1002 picochip_save_area_byte_offset (void)
1004 int base_offset
= (picochip_frame_byte_offset () +
1005 picochip_frame_size_in_bytes ());
1007 gcc_assert(picochip_is_aligned (base_offset
, BITS_PER_WORD
));
1013 /* Compute and return offset of the special register save area. This
1014 area can be found immediately above the normal save area. It must
1015 be aligned, to allow the registers to be saved and restored as a
1018 picochip_special_save_area_byte_offset (void)
1020 int byte_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
1021 int offset
= (picochip_save_area_byte_offset () +
1022 picochip_save_area_size_in_bytes ());
1024 if ((offset
% byte_alignment
) != 0)
1025 offset
= ((offset
/ byte_alignment
) + 1) * byte_alignment
;
1031 /* Determine whether the LNK/SP register save/restores can be eliminated. */
1033 picochip_can_eliminate_link_sp_save (void)
1035 /* This deserves some reasoning. The df_regs_ever_live_p call keeps
1036 changing during optimizations phases. So, this function returns different
1037 values when called from initial_elimination_offset and then again when it
1038 is called from prologue/epilogue generation. This means that argument
1039 accesses become wrong. This wouldnt happen only if we were not using the
1040 stack at all. The following conditions ensures that.*/
1042 return (current_function_is_leaf
&&
1043 !df_regs_ever_live_p(LINK_REGNUM
) &&
1044 !df_regs_ever_live_p(STACK_POINTER_REGNUM
) &&
1045 (picochip_special_save_area_byte_offset() == 0) &&
1046 (crtl
->args
.size
== 0) &&
1047 (crtl
->args
.pretend_args_size
== 0));
1050 /* Compute the size of the special reg save area (SP and LNK). If the
1051 SP/LNK registers don't need to be saved, this area can shrink to
1054 picochip_special_save_area_size_in_bytes (void)
1058 if (picochip_can_eliminate_link_sp_save ())
1061 return 2 * UNITS_PER_WORD
;
1064 /* Return the number of pretend arguments. If this function is
1065 varadic, all the incoming arguments are effectively passed on the
1066 stack. If this function has real pretend arguments (caused by a
1067 value being passed partially on the stack and partially in
1068 registers), then return the number of registers used. */
1070 picochip_pretend_arg_area_size (void)
1073 if (crtl
->args
.pretend_args_size
!= 0)
1075 gcc_assert(crtl
->args
.pretend_args_size
% 4 == 0);
1077 return crtl
->args
.pretend_args_size
;
1079 else if (cfun
->stdarg
)
1086 /* Compute and return the offset of the pretend arguments. The pretend
1087 arguments are contiguous with the incoming arguments, and must be
1088 correctly aligned. */
1090 picochip_pretend_arg_area_byte_offset (void)
1092 int base_offset
= 0;
1094 base_offset
= (picochip_special_save_area_byte_offset () +
1095 picochip_special_save_area_size_in_bytes ());
1097 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1098 gcc_assert(picochip_is_aligned
1099 (base_offset
+ picochip_pretend_arg_area_size (), STACK_BOUNDARY
));
1105 /* Compute and return the offset of the incoming arguments. If a
1106 static chain is in use, this will be passed just before the other
1107 arguments. This means that the pretend argument mechanism, used in
1108 variadic functions, doesn't work properly. Thus, static chains work
1109 on their own, as do variadic functions, but not the combination of
1110 the two. This isn't really a problem. */
1112 picochip_arg_area_byte_offset (void)
1114 int base_offset
= (picochip_pretend_arg_area_byte_offset () +
1115 picochip_pretend_arg_area_size ());
1117 /* Add an extra 4 bytes - only an extra 16-bits are required, but
1118 the alignment on a 32-bit boundary must be maintained. */
1119 if (cfun
->static_chain_decl
!= NULL
)
1121 gcc_assert (!cfun
->stdarg
);
1125 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1132 picochip_regno_nregs (int regno ATTRIBUTE_UNUSED
, int mode
)
1135 /* Special case - only one register needed. */
1136 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1139 /* We actually do not allocate acc0 ever. But, it seems like we need to
1140 make it look like a allocatable register for the dataflow checks to work
1141 properly. Note that hard_regno_mode_ok will always return 0 for acc0*/
1146 /* General case - compute how much space in terms of units. */
1147 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1152 picochip_class_max_nregs (int class, int mode
)
1154 int size
= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1156 if (class == ACC_REGS
)
1159 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1166 /* Eliminate a register that addresses the stack (e.g., frame pointer,
1167 argument pointer) by replacing it with a constant offset from the
1168 main stack register. */
1170 initial_elimination_offset (int from
, int to
)
1172 int offset_from_sp
= 0;
1174 if (FRAME_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1175 offset_from_sp
= picochip_frame_byte_offset ();
1176 else if (ARG_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1177 offset_from_sp
= picochip_pretend_arg_area_byte_offset ();
1181 return offset_from_sp
;
1185 /* Compute and return the size of the incoming argument area. */
1187 picochip_arg_area_size_in_bytes (void)
1189 return crtl
->args
.size
;
1192 /* Determine whether the given register is valid. When the strict mode
1193 is used, only hard registers are valid, otherwise any register is
1196 picochip_legitimate_address_register (rtx x
, unsigned strict
)
1199 /* Sanity check - non-registers shouldn't make it here, but... */
1200 if (REG
!= GET_CODE (x
))
1204 return REGNO (x
) < FIRST_NONHARD_REGISTER
;
1210 /* Determine whether the given constant is in the range required for
1211 the given base register. */
1213 picochip_const_ok_for_base (enum machine_mode mode
, int regno
, int offset
)
1215 HOST_WIDE_INT corrected_offset
;
1217 if (GET_MODE_SIZE (mode
) != 0)
1219 if (GET_MODE_SIZE(mode
) <= 4)
1221 /* We used to allow incorrect offsets if strict is 0. But, this would
1222 then rely on reload doing the right thing. We have had problems
1223 there before, and on > 4.3 compiler, there are no benefits. */
1224 if (offset
% GET_MODE_SIZE (mode
) != 0)
1226 corrected_offset
= offset
/ GET_MODE_SIZE (mode
);
1230 if (offset
% 4 != 0)
1232 corrected_offset
= offset
/ 4;
1237 /* Default to the byte offset as supplied. */
1238 corrected_offset
= offset
;
1241 /* The offset from the base register can be different depending upon
1242 the base register. The stack/frame/argument pointer offsets can
1243 all be greater than a simple register-based offset. Note that the
1244 frame/argument pointer registers are actually eliminations of the
1245 stack pointer, so a value which is valid for an offset to, for
1246 example, the frame pointer, might be invalid for the stack
1247 pointer once the elimination has occurred. However, there is no
1248 need to handle this special case here, as the stack offset is
1249 always checked after elimination anyway, and the generated code
1250 seems to have identical performance. */
1251 if (regno
== STACK_POINTER_REGNUM
||
1252 regno
== FRAME_POINTER_REGNUM
|| regno
== ARG_POINTER_REGNUM
)
1253 return picochip_const_ok_for_letter_p (corrected_offset
, 'K');
1255 return picochip_const_ok_for_letter_p (corrected_offset
, 'J');
1259 /* Determine whether a given rtx is a legitimate address for machine_mode
1260 MODE. STRICT is non-zero if we're being strict - any pseudo that
1261 is not a hard register must be a memory reference. */
1263 picochip_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
1267 switch (GET_CODE (x
))
1270 valid
= picochip_legitimate_address_register (x
, strict
);
1275 rtx base
= XEXP (x
, 0);
1276 rtx offset
= XEXP (x
, 1);
1277 if (strict
&& !REGNO_OK_FOR_BASE_P (REGNO(base
)))
1283 valid
= (REG
== GET_CODE (base
) &&
1284 picochip_legitimate_address_register (base
, strict
) &&
1285 CONST_INT
== GET_CODE (offset
) &&
1286 picochip_const_ok_for_base (mode
, REGNO (base
),
1292 /* The user can select whether a symbol can be used as a memory
1293 address. Typically, this will decrease execution time (no
1294 register load is required first), but will increase code size
1295 (because the symbol will be used several times, rather than
1296 loaded once into a register.*/
1297 valid
= TARGET_SYMBOL_AS_ADDRESS
;
1302 /* A constant memory address must be a (plus (symbol_ref)
1303 (const_int)), and is only allowed when the symbols are
1304 permitted addresses. */
1305 rtx inner
= XEXP (x
, 0);
1307 valid
= (TARGET_SYMBOL_AS_ADDRESS
&&
1308 PLUS
== GET_CODE (inner
) &&
1309 SYMBOL_REF
== GET_CODE (XEXP (inner
, 0)) &&
1310 CONST_INT
== GET_CODE (XEXP (inner
, 1)));
1324 /* For all memory operations, picochip allows a uconst4 offset value. It
1325 is hence beneficial to turn an
1326 addr = <reg + long_const>
1331 X = reg + long_const & FFF0
1332 diff = long_const - (long_const & FFF0)
1335 X can be reused in subsequent memory operations.
1338 picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1339 enum machine_mode mode
)
1345 // Depending on mode, the offsets allowed are either 16/32/64.
1361 if (GET_CODE (x
) == PLUS
1362 && GET_CODE (XEXP (x
, 0)) == REG
1363 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1365 int offset
= INTVAL (XEXP (x
, 1));
1366 // Ignore cases with negative offsets.
1369 int high_val
= offset
& mask_val
;
1370 int low_val
= offset
- high_val
;
1373 rtx temp_reg
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, XEXP (x
, 0), GEN_INT(high_val
)));
1374 x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1381 /* For all memory operations, picochip allows a uconst4 offset value. It
1382 is hence beneficial to turn an
1383 addr = <reg + long_const>
1388 X = reg + long_const & FFF0
1389 diff = long_const - (long_const & FFF0)
1392 X can be reused in subsequent memory operations.
1395 picochip_legitimize_reload_address (rtx
*x
,
1396 enum machine_mode mode
,
1397 int opnum
, int type
,
1398 int ind_levels ATTRIBUTE_UNUSED
)
1400 if (picochip_symbol_offset(*x
))
1402 *x
= gen_rtx_CONST(mode
, *x
);
1408 /* We should recognise addresses that we created.*/
1409 if (GET_CODE (*x
) == PLUS
1410 && GET_CODE (XEXP (*x
, 0)) == PLUS
1411 && GET_CODE (XEXP (XEXP (*x
, 0), 0)) == REG
1412 && GET_CODE (XEXP (XEXP (*x
, 0), 1)) == CONST_INT
1413 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1415 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1416 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1417 opnum
, (enum reload_type
)type
);
1422 // Depending on mode, the offsets allowed are either 16/32/64.
1438 if (GET_CODE (*x
) == PLUS
1439 && GET_CODE (XEXP (*x
, 0)) == REG
1440 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1442 int offset
= INTVAL (XEXP (*x
, 1));
1443 // Ignore cases with negative offsets.
1446 int high_val
= offset
& mask_val
;
1447 int low_val
= offset
- high_val
;
1450 rtx temp_reg
= gen_rtx_PLUS (Pmode
, XEXP (*x
, 0), GEN_INT(high_val
));
1451 *x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1452 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1453 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1454 opnum
, (enum reload_type
)type
);
1462 /* Detect an rtx which matches (plus (symbol_ref) (const_int)). */
1464 picochip_symbol_offset (rtx operand
)
1467 return (PLUS
== GET_CODE (operand
) &&
1468 SYMBOL_REF
== GET_CODE (XEXP (operand
, 0)) &&
1469 CONST_INT
== GET_CODE (XEXP (operand
, 1)));
1473 /* Assembly output. */
1475 /* The format here should match the format used in the output of
1476 symbol_ref's elsewhere in this file. */
1478 picochip_output_label (FILE * stream
, const char name
[])
1480 int is_cfi_label
= (strncmp (name
, "picoMark_LCFI", 13) == 0);
1482 /* If VLIW scheduling is in use, any Call Frame Information labels
1483 generated inside a packet must have their output deferred until
1484 the end of the packet. */
1485 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1486 is_cfi_label
&& picochip_vliw_continuation
)
1488 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1490 internal_error ("LCFI labels have already been deferred.");
1492 strcpy (picochip_current_vliw_state
.cfi_label_name
[
1493 picochip_current_vliw_state
.num_cfi_labels_deferred
], name
);
1494 picochip_current_vliw_state
.num_cfi_labels_deferred
++;
1498 assemble_name (stream
, name
);
1500 if (strncmp (name
, "picoMark_", 9) == 0)
1501 fprintf (stream
, "=\n");
1503 fprintf (stream
, ":\n");
1509 /* The format here should match the format used in the output of
1510 symbol_ref's elsewhere in this file. */
1512 picochip_output_labelref (FILE * stream
, const char name
[])
1514 fprintf (stream
, "_%s", name
);
1518 picochip_weaken_label (FILE * stream
, const char name
[])
1520 fprintf (stream
, ".weak ");
1521 assemble_name (stream
, name
);
1522 fprintf (stream
, "\n");
1525 /* Return true if the given label (or label prefix) denotes a marker
1526 label which should be emitted in the form LABEL= */
1528 picochip_is_marker_prefix (const char *prefix
)
1530 return (strcmp (prefix
, "L") != 0 && strcmp (prefix
, "LC") != 0
1531 && strcmp (prefix
, "LP") != 0);
1535 picochip_output_internal_label (FILE * stream
, const char *prefix
,
1539 /* Emit different types of label, based upon their prefix. They
1540 are handled differently to allow the assembler to ensure that
1541 branch target labels are properly aligned, while other labels
1542 will only serve as code markers, not branch targets. Aligning
1543 labels unnecessarily can result in much code wastage. */
1544 if (picochip_is_marker_prefix (prefix
))
1546 /* Special label marker. If it appears in the middle of a VLIW
1547 packet, defer it until the end of the packet. There has
1548 never been a need to handle more than one lm label at a time. */
1549 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1550 (strcmp (prefix
, "LM")) == 0 && picochip_vliw_continuation
)
1552 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
1553 internal_error ("LM label has already been deferred.");
1555 sprintf (picochip_current_vliw_state
.lm_label_name
,
1556 "picoMark_%s%ld", prefix
, num
);
1561 fprintf (stream
, "_picoMark_%s%ld=\n", prefix
, num
);
1568 fprintf (stream
, "_%s%ld:\n", prefix
, num
);
1574 picochip_generate_internal_label (char *str
, const char *prefix
, long num
)
1576 /* Two types of internal label can be generated: branch target
1577 labels and code marker labels. Branch target labels must always
1578 be aligned (since code will execute at these
1579 points). Differentiate between the two by prepending markers with
1580 a unique prefix, which can later be used in output_label to
1581 figure out which label syntax to use. */
1582 if (picochip_is_marker_prefix (prefix
))
1583 sprintf (str
, "picoMark_%s%ld", prefix
, num
);
1585 sprintf (str
, "%s%ld", prefix
, num
);
1590 picochip_asm_output_anchor (rtx symbol
)
1592 fprintf (asm_out_file
, ".offsetData _%s, ",XSTR (symbol
, 0));
1593 fprintf (asm_out_file
, "+ " HOST_WIDE_INT_PRINT_DEC
"\n",SYMBOL_REF_BLOCK_OFFSET(symbol
));
1597 picochip_output_aligned_common (FILE * stream
, const char *name
,
1598 unsigned size
, unsigned alignment
)
1601 fprintf (stream
, ".commonData ");
1602 assemble_name (stream
, name
);
1603 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1604 picochip_output_global (stream
, name
);
1609 picochip_output_aligned_local (FILE * stream
, const char *name
,
1610 unsigned size
, unsigned alignment
)
1613 fprintf (stream
, ".commonData ");
1614 assemble_name (stream
, name
);
1615 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1620 picochip_output_global (FILE * stream
, const char *name
)
1622 fprintf (stream
, ".global ");
1623 assemble_name (stream
, name
);
1624 fprintf (stream
, "\n");
1627 /* Output an assembly language string. Output as a sequence of decimal
1628 numbers, followed by the literal string to make it obvious what the
1629 numbers represent. */
1631 picochip_output_ascii (FILE * file
, const char *str
, int length
)
1635 fprintf (file
, ".ascii ");
1637 for (i
= 0; i
< length
; ++i
)
1639 fprintf (file
, "16#%hhx# ", (char) (str
[i
]));
1642 fprintf (file
, " ; ");
1644 for (i
= 0; i
< length
; ++i
)
1651 fprintf (file
, "\\n");
1654 fprintf (file
, "\\t");
1657 fprintf (file
, "\\0");
1660 fprintf (file
, "%c", c
);
1665 fprintf (file
, "\n");
1669 /* Output the beginning of an ASM file. */
1671 picochip_asm_file_start (void)
1673 default_file_start ();
1675 fprintf (asm_out_file
, "// picoChip ASM file\n");
1676 fprintf (asm_out_file
, "//.file \"%s\"\n", main_input_filename
);
1678 fprintf (asm_out_file
, "// Has byte access: %s\n",
1679 (TARGET_HAS_BYTE_ACCESS
? "Yes" : "No"));
1681 if (TARGET_HAS_MUL_UNIT
)
1682 fprintf (asm_out_file
, "// Has multiply: Yes (Multiply unit)\n");
1683 else if (TARGET_HAS_MAC_UNIT
)
1684 fprintf (asm_out_file
, "// Has multiply: Yes (Mac unit)\n");
1686 fprintf (asm_out_file
, "// Has multiply: No\n");
1688 /* Variable tracking should be run after all optimizations which change order
1689 of insns. It also needs a valid CFG. This can't be done in
1690 picochip_override_options, because flag_var_tracking is finalized after
1692 picochip_flag_var_tracking
= flag_var_tracking
;
1693 flag_var_tracking
= 0;
1696 /* Output the end of an ASM file. */
1698 picochip_asm_file_end (void)
1700 /* Include a segment end to make it easy for PERL scripts to grab
1701 segments. This is now done by assembler*/
1703 fprintf (asm_out_file
, "// End of picoChip ASM file\n");
1707 /* Output frame debug information to the given stream. */
1709 picochip_output_frame_debug (FILE * file
)
1713 if (current_function_is_leaf
)
1714 fprintf (file
, "\t\t// Leaf function\n");
1716 fprintf (file
, "\t\t// Non-leaf function\n");
1718 if (picochip_can_eliminate_link_sp_save ())
1719 fprintf (file
, "\t\t// Link/fp save/restore can be eliminated\n");
1721 if (cfun
->static_chain_decl
!= NULL
)
1722 fprintf (file
, "\t\t// Static chain in use\n");
1724 fprintf (file
, "\t\t// Incoming argument size: %d bytes\n",
1725 picochip_arg_area_size_in_bytes ());
1726 fprintf (file
, "\t\t// Incoming arg offset: %d\n",
1727 picochip_arg_area_byte_offset ());
1728 fprintf (file
, "\t\t// Pretend arg size: %d\n",
1729 picochip_pretend_arg_area_size ());
1730 fprintf (file
, "\t\t// Pretend arg offset (ARGP): %d\n",
1731 picochip_pretend_arg_area_byte_offset ());
1732 fprintf (file
, "\t\t// Special reg area size: %d bytes\n",
1733 picochip_special_save_area_size_in_bytes ());
1734 fprintf (file
, "\t\t// Special reg area offset: %d\n",
1735 picochip_special_save_area_byte_offset ());
1737 /* Output which registers are saved. */
1738 fprintf (file
, "\t\t// Saved regs: ");
1739 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1741 if (picochip_reg_needs_saving (i
))
1742 fprintf (file
, "%s ", picochip_regnames
[i
]);
1744 fprintf (file
, "\t\t\n");
1746 fprintf (file
, "\t\t// Save area size: %d bytes\n",
1747 picochip_save_area_size_in_bytes ());
1748 fprintf (file
, "\t\t// Save area offset: %d\n",
1749 picochip_save_area_byte_offset ());
1751 fprintf (file
, "\t\t// Frame size: %ld bytes\n", get_frame_size ());
1752 fprintf (file
, "\t\t// Frame offset (FP): %d\n",
1753 picochip_frame_byte_offset ());
1755 fprintf (file
, "\t\t// Outgoing argument area size: %d bytes\n",
1756 crtl
->outgoing_args_size
);
1760 /* Output picoChip function prologue. This contains human-readable
1761 information about the function. */
1763 picochip_function_prologue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1765 /* Get the function's name, as described by its RTL. This may be
1766 different from the DECL_NAME name used in the source file. The
1767 real declaration name must be used, to ensure that the prologue
1768 emits the right information for the linker. */
1771 x
= DECL_RTL (current_function_decl
);
1772 gcc_assert (MEM_P (x
));
1774 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1775 fnname
= XSTR (x
, 0);
1777 /* Note that the name of the function is given in the &_%s
1778 form. This matches the name of the function as used in labels,
1779 and function calls, and enables processCallGraph to match
1780 function calls to the name of the function, as defined here. */
1781 fprintf (file
, "// picoChip Function Prologue : &_%s = %d bytes\n",
1782 fnname
, picochip_arg_area_byte_offset ());
1784 picochip_output_frame_debug (file
);
1785 fprintf (file
, "\n");
1789 /* Output picoChip function epilogue. */
1791 picochip_function_epilogue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1796 x
= DECL_RTL (current_function_decl
);
1797 gcc_assert (MEM_P (x
));
1799 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1800 fnname
= XSTR (x
, 0);
1801 fprintf (file
, "\n// picoChip Function Epilogue : %s\n\n",
1805 /* Manipulate the asm output. Some machines only execute the code when
1806 there is actually a chance of needing it (e.g., FRV doesn't execute
1807 it if the scheduling pass wasn't used). We always execute it,
1808 simple to ensure that it is exercised more often, and bugs are more
1811 This function's prime reason for existence is to insert the VLIW
1812 separators where appropriate. The separators must be inserted
1813 before any comments which appear at the end of the file.
1817 picochip_asm_output_opcode (FILE * f
, const char *ptr
)
1821 /* Flag to specify when a VLIW continuation has been inserted onto
1822 the line. Continuations are either inserted before any comments,
1823 or before the end of the line is reached. The flag ensures that
1824 we don't insert continuations twice (i.e., at the comment and the
1826 int continuation_inserted
= 0;
1828 /* If the instruction uses multiple lines (i.e., a new line
1829 character appears in the opcode), then ensure that no attempt is
1830 made to pack it into a VLIW. */
1831 if (strchr (ptr
, '\n') != NULL
&& picochip_vliw_continuation
)
1833 ("picochip_asm_output_opcode - Found multiple lines in VLIW packet %s\n",
1837 /* If a delay slot is pending, output the directive to the assembler
1838 before the instruction. */
1839 if (picochip_is_delay_slot_pending
)
1841 picochip_is_delay_slot_pending
= 0;
1845 /* Keep going for entire opcode. All substitution performed ourselves. */
1850 /* Determine whether a VLIW continuation must be inserted before
1851 any comments, or the end of the opcode. A flag is set to show
1852 that we have inserted a continuation on this line, so that we
1853 don't try to insert another continuation when the end of the
1854 opcode is reached. The only other case for a continuation
1855 might have been a newline, but these aren't allowed in
1856 conjunction with VLIW continuations (see above code). */
1857 if (picochip_vliw_continuation
&&
1858 !continuation_inserted
&&
1859 ((c
== '/' && (*ptr
== '/')) || *ptr
== '\0'))
1862 continuation_inserted
= 1;
1865 /* Detect an explicit VLIW separator. */
1866 if (c
== '%' && (*ptr
== '|'))
1871 /* Detect the need for an ALU id operand. */
1872 else if (c
== '%' && (*ptr
== '#'))
1874 fputc (picochip_get_vliw_alu_id (), f
);
1877 printf ("Generated ALU char at %s for insn %d\n", ptr
,
1878 INSN_UID (picochip_current_prescan_insn
));
1880 /* Skip past unwanted # */
1883 /* Detect the need for branch delay slot. */
1884 else if (c
== '%' && (*ptr
== '>'))
1886 /* Only emit delay slots (NOP's, or otherwise) when delay
1887 * slot scheduling has actually been enabled, otherwise VLIW
1888 * scheduling and delay slot scheduling output combine to
1889 * produce nasty effects. */
1890 if (flag_delayed_branch
)
1892 if (dbr_sequence_length () == 0)
1893 fputs ("\n=->\tNOP", f
);
1895 picochip_is_delay_slot_pending
= 1;
1898 /* Skip past unwanted > */
1901 /* Detect any %digit specifiers. */
1902 else if (c
== '%' && (*ptr
>= '0' && *ptr
<= '9'))
1905 picochip_print_operand (f
, recog_data
.operand
[c
], 0);
1906 while ((c
= *ptr
) >= '0' && c
<= '9')
1909 /* Detect any %letterdigit specifiers. */
1910 else if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
1911 || (*ptr
>= 'A' && *ptr
<= 'Z')))
1913 int letter
= *ptr
++;
1920 output_asm_label (recog_data
.operand
[c
]);
1924 output_address (recog_data
.operand
[c
]);
1928 picochip_print_operand (f
, recog_data
.operand
[c
], letter
);
1931 while ((c
= *ptr
) >= '0' && c
<= '9')
1936 ("picochip_asm_output_opcode - can't output unknown operator %c\n",
1942 /* Reached the end of the packet. If any labels were deferred
1943 during output, emit them now. */
1944 if (!picochip_vliw_continuation
)
1946 if (picochip_current_vliw_state
.num_cfi_labels_deferred
!= 0)
1949 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[0]);
1951 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1954 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[1]);
1959 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
1962 assemble_name (f
, picochip_current_vliw_state
.lm_label_name
);
1967 /* Output an end-of-packet marker if requested. */
1968 if (!picochip_vliw_continuation
&&
1969 TARGET_DEBUG
&& picochip_schedule_type
== DFA_TYPE_SPEED
)
1970 fprintf (f
, "\n\t//-------------- End of VLIW packet -----------------");
1975 /* Function RTL expansion. */
1977 /* Expand the prologue into RTL. */
1979 picochip_expand_prologue (void)
1981 int stack_adjustment
= 0;
1982 int special_save_offset
= 0;
1983 int general_save_offset
= 0;
1984 int reg_save_offset
= 0;
1987 stack_adjustment
= picochip_arg_area_byte_offset ();
1988 general_save_offset
=
1989 -(stack_adjustment
- picochip_save_area_byte_offset ());
1990 special_save_offset
=
1991 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
1993 /* Save the link registers. We could try to save just one register
1994 here. This would reduce the amount of stack space required.
1995 There hasnt been a good reason to do that so far. */
1996 if (!picochip_can_eliminate_link_sp_save ())
1997 picochip_emit_save_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
1998 special_save_offset
);
2000 /* Save callee-save registers. */
2001 reg_save_offset
= 0;
2002 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2004 if (picochip_reg_needs_saving (i
))
2007 /* If this register is an even numbered register, and the
2008 next register also needs to be saved, use a SImode save,
2009 which does both in one instruction. Note that a special
2010 check is performed to ensure that the double word aligned
2011 store is valid (e.g., it is possible that r6, r8, r9 need
2012 to be saved, in which case once r6 has been saved, the
2013 stored offset is no longer aligned, and an STL/LDL
2014 instruction becomes invalid). Alternately, we could store all
2015 aligned registers first and then save the single one(s). */
2017 picochip_reg_needs_saving (i
+ 1) &&
2018 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2020 picochip_emit_save_register (gen_rtx_REG (SImode
, i
),
2021 general_save_offset
+
2023 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2028 picochip_emit_save_register (gen_rtx_REG (HImode
, i
),
2029 general_save_offset
+
2031 reg_save_offset
+= UNITS_PER_WORD
;
2037 /* Emit a stack adjustment where required. */
2038 if (stack_adjustment
!= 0)
2039 picochip_emit_stack_allocate (stack_adjustment
);
2041 /* If this function uses varadic arguments, write any unnamed
2042 registers to the stack. */
2045 int stdarg_offset
= picochip_pretend_arg_area_byte_offset ();
2047 /* Sanity check. The pretend argument offset should be 32-bit aligned. */
2048 gcc_assert(picochip_pretend_arg_area_byte_offset () % 4 == 0);
2050 picochip_emit_save_register (gen_rtx_REG (SImode
, 0), stdarg_offset
);
2051 picochip_emit_save_register (gen_rtx_REG (SImode
, 2),
2053 picochip_emit_save_register (gen_rtx_REG (SImode
, 4),
2060 /* Expand the epilogue into RTL. */
2062 picochip_expand_epilogue (int is_sibling_call ATTRIBUTE_UNUSED
)
2064 int stack_adjustment
= 0;
2065 int special_save_offset
= 0;
2066 int general_save_offset
= 0;
2067 int reg_save_offset
= 0;
2069 int use_link_fp_restore_stack_adjust
= 0; /* Default to using an explicit
2072 stack_adjustment
= picochip_arg_area_byte_offset ();
2073 general_save_offset
=
2074 -(stack_adjustment
- picochip_save_area_byte_offset ());
2075 special_save_offset
=
2076 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
2078 /* Emit a stack adjustment where required. */
2079 if (stack_adjustment
!= 0)
2081 /* If the link/fp is already being restored, and the offset to
2082 their save location is small enough, don't bother adjusting
2083 the stack explicitly. */
2084 if (picochip_special_save_area_byte_offset () < 512 &&
2085 !picochip_can_eliminate_link_sp_save ())
2086 use_link_fp_restore_stack_adjust
= 1;
2088 /* Explicitly restore the stack. */
2089 picochip_emit_stack_allocate (-stack_adjustment
);
2092 /* Restore the Link/FP registers. Only save the link register? */
2093 if (!picochip_can_eliminate_link_sp_save ())
2095 if (use_link_fp_restore_stack_adjust
)
2096 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2097 picochip_special_save_area_byte_offset
2100 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2101 special_save_offset
);
2104 /* Restore callee-save registers. */
2105 reg_save_offset
= 0;
2106 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2108 if (picochip_reg_needs_saving (i
))
2111 /* If this register is an even numbered register, and the
2112 next register also needs to be saved, use a SImode save,
2113 which does both in one instruction. Note that a special
2114 check is performed to ensure that the double word aligned
2115 store is valid (e.g., it is possible that r6, r8, r9 need
2116 to be saved, in which case once r6 has been saved, the
2117 stored offset is no longer aligned, and an STL/LDL
2118 instruction becomes invalid). We could store all aligned
2119 registers first, and then save the single one(s). */
2121 picochip_reg_needs_saving (i
+ 1) &&
2122 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2124 picochip_emit_restore_register (gen_rtx_REG (SImode
, i
),
2125 general_save_offset
+
2127 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2132 picochip_emit_restore_register (gen_rtx_REG (HImode
, i
),
2133 general_save_offset
+
2135 reg_save_offset
+= UNITS_PER_WORD
;
2141 /* Emit a return instruction, which matches a (parallel
2142 [(return) (use r12)]) */
2145 p
= rtvec_alloc (2);
2147 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
2148 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
2149 gen_rtx_REG (Pmode
, LINK_REGNUM
));
2150 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
2155 /* Assembly instruction output. */
2157 /* Test whether the given branch instruction is short, or long. Short
2158 * branches are equivalent to real branches, and may be DFA
2159 * scheduled. Long branches expand to a macro which is handled by the
2160 * elaborator, and cannot be scheduled. Occasionally, the branch
2161 * shortening pass, which is run after DFA scheduling, will change the
2162 * code layout and cause the short branch to be reverted into a long
2163 * branch. Instead of having to fix this up by emitting new assembly,
2164 * the short branch is emitted anyway. There is plenty of slack in the
2165 * calculation of long and short branches (10-bit offset, but only
2166 * 9-bits used in computation), so there is enough slack for this to
2169 picochip_is_short_branch (rtx insn
)
2171 int isRealShortBranch
= (get_attr_length(insn
) == SHORT_BRANCH_LENGTH
);
2173 return (isRealShortBranch
||
2174 (!isRealShortBranch
&&
2175 picochip_current_vliw_state
.num_insns_in_packet
> 1));
2178 /* Output a compare-and-branch instruction (matching the cbranch
2181 picochip_output_cbranch (rtx operands
[])
2184 if (HImode
!= GET_MODE (operands
[1]) ||
2185 (HImode
!= GET_MODE (operands
[2]) &&
2186 GET_CODE (operands
[2]) != CONST_INT
))
2188 internal_error ("%s: At least one operand can't be handled",
2192 /* Use the type of comparison to output the appropriate condition
2194 switch (GET_CODE (operands
[0]))
2197 return ("// if (%1 != %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPNE %l3");
2200 return ("// if (%1 == %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPEQ %l3");
2203 /* Reverse the operand order to be GE */
2204 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPGE %l3");
2207 /* Reverse operand order of GEU. */
2208 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPHS %l3");
2211 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPGE %l3");
2214 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPHS %l3");
2217 return ("// if (%1 < %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLT %l3");
2220 return ("// if (%1 <{U} %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLO %l3");
2223 /* Reversed operand version of LT. */
2224 return ("// if (%1 > %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLT %l3");
2227 /* Reverse an LTU. */
2228 return ("// if (%1 >{U} %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLO %l3");
2235 /* Output a compare-and-branch instruction (matching the cbranch
2236 pattern). This function is current unused since the cbranch
2237 split is disabled. The function is kept around so we can use
2238 it when we understand how to do cbranch split safely. */
2240 picochip_output_compare (rtx operands
[])
2243 if (HImode
!= GET_MODE (operands
[1]) ||
2244 (HImode
!= GET_MODE (operands
[2]) &&
2245 GET_CODE (operands
[2]) != CONST_INT
))
2247 internal_error ("%s: At least one operand can't be handled",
2251 /* Use the type of comparison to output the appropriate condition
2253 int code
= GET_CODE (operands
[0]);
2257 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2260 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2263 /* Reverse the operand order to be GE */
2264 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2267 /* Reverse operand order of GEU. */
2268 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2271 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2274 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2277 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2280 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2283 /* Reversed operand version of LT. */
2284 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2287 /* Reverse an LTU. */
2288 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2295 /* Output the branch insn part of a compare-and-branch split. */
2297 picochip_output_branch (rtx operands
[], rtx insn
)
2300 int code
= GET_CODE(operands
[2]);
2301 if (picochip_is_short_branch (insn
))
2303 /* Short branches can be output directly using the
2304 appropriate instruction. */
2308 return ("BNE %l0 %>");
2310 return ("BEQ %l0 %>");
2312 return ("BGE %l0 %>");
2314 return ("BHS %l0 %>");
2316 return ("BGE %l0 %>");
2318 return ("BHS %l0 %>");
2320 return ("BLT %l0 %>");
2322 return ("BLO %l0 %>");
2324 return ("BLT %l0 %>");
2326 return ("BLO %l0 %>");
2328 internal_error ("Unknown short branch in %s (type %d)\n",
2329 __FUNCTION__
, (int) INTVAL (operands
[1]));
2330 return "UNKNOWN_BRANCH";
2335 /* Long branches result in the emission of a special
2336 instruction, which the assembler expands into a suitable long
2339 /* Use the type of comparison to output the appropriate condition
2344 return ("JMPNE %l0 %>");
2346 return ("JMPEQ %l0 %>");
2348 return ("JMPGE %l0 %>");
2350 return ("JMPHS %l0 %>");
2352 return ("JMPGE %l0 %>");
2354 return ("JMPHS %l0 %>");
2356 return ("JMPLT %l0 %>");
2358 return ("JMPLO %l0 %>");
2360 return ("JMPLT %l0 %>");
2362 return ("JMPLO %l0 %>");
2365 internal_error ("Unknown long branch in %s (type %d)\n",
2366 __FUNCTION__
, (int) INTVAL (operands
[1]));
2367 return "UNKNOWN_BRANCH";
2373 /* Output a jump instruction. */
2375 picochip_output_jump (rtx insn
)
2377 if (picochip_is_short_branch (insn
))
2380 return "JMPRA %l0%>";
2384 picochip_output_put_array (int alternative
, rtx operands
[])
2386 /* Local output buffer. */
2389 int portArraySize
= INTVAL(operands
[1]);
2390 int portBaseIndex
= INTVAL(operands
[2]);
2392 if (alternative
== 0)
2394 sprintf (buf
, "// Array put\n\tadd.0 [lsl %%0,2],&__commTable_put_%d_%d,lr\n\tjl (lr)",
2395 portArraySize
, portBaseIndex
);
2396 output_asm_insn (buf
, operands
);
2398 else if (alternative
== 1)
2400 /* Constant port id. Emit a real instruction. */
2401 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2402 if (portIndex
< portBaseIndex
||
2403 portIndex
>= (portBaseIndex
+ portArraySize
))
2405 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2406 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2408 sprintf(buf
, "PUT R[0:1],%d", portIndex
);
2409 output_asm_insn (buf
, operands
);
2414 /* Both alternatives output the insn directly. */
2418 const char *picochip_output_get_array (int alternative
, rtx operands
[])
2420 /* Local output buffer. */
2423 int portArraySize
= INTVAL(operands
[1]);
2424 int portBaseIndex
= INTVAL(operands
[2]);
2426 if (alternative
== 0)
2428 sprintf (buf
, "// Array get\n\tadd.0 [lsl %%0,2],&__commTable_get_%d_%d,lr\n\tjl (lr)",
2429 portArraySize
, portBaseIndex
);
2430 output_asm_insn (buf
, operands
);
2432 else if (alternative
== 1)
2434 /* Constant port id. Emit a real instruction. */
2435 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2436 if (portIndex
< portBaseIndex
||
2437 portIndex
>= (portBaseIndex
+ portArraySize
))
2439 error ("GET uses port array index %d, which is out of range [%d..%d)",
2440 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2442 sprintf(buf
, "GET %d,R[0:1]", portIndex
);
2443 output_asm_insn (buf
, operands
);
2448 /* Both alternatives output the insn directly. */
2452 const char *picochip_output_testport_array (int alternative
, rtx operands
[])
2454 /* Local output buffer. */
2457 int portArraySize
= INTVAL(operands
[2]);
2458 int portBaseIndex
= INTVAL(operands
[3]);
2460 if (alternative
== 0)
2462 sprintf (buf
, "// Array tstport\n\tadd.0 [lsl %%1,2],&__commTable_tstport_%d_%d,lr\n\tjl (lr)\n=->\tcopy.0 0,%%0\n\tcopyeq 1,%%0",
2463 portArraySize
, portBaseIndex
);
2464 output_asm_insn (buf
, operands
);
2466 else if (alternative
== 1)
2468 /* Constant port id. Emit a real instruction. */
2469 int portIndex
= INTVAL(operands
[1]) + portBaseIndex
;
2470 if (portIndex
< portBaseIndex
||
2471 portIndex
>= (portBaseIndex
+ portArraySize
))
2473 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2474 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2476 sprintf(buf
, "copy.1 0,%%0 %%| TSTPORT %d\n\tcopyeq 1,%%0", portIndex
);
2477 output_asm_insn (buf
, operands
);
2482 /* Both alternatives output the insn directly. */
2486 /* Output a comparison operand as a symbol (e.g., >). */
2488 picochip_print_comparison (FILE * file
, rtx operand
, int letter
)
2493 /* Output just the comparison symbol. */
2494 switch (GET_CODE (operand
))
2497 fprintf (file
, "!=");
2500 fprintf (file
, "==");
2503 fprintf (file
, ">=");
2506 fprintf (file
, ">={U}");
2509 fprintf (file
, "<");
2512 fprintf (file
, "<{U}");
2515 fprintf (file
, "<=");
2518 fprintf (file
, "<={U}");
2521 fprintf (file
, ">");
2524 fprintf (file
, ">{U}");
2532 /* Output the comparison formatted as operand,symbol,operand */
2533 rtx op0
= XEXP (operand
, 0);
2534 rtx op1
= XEXP (operand
, 1);
2536 picochip_print_operand (file
, op0
, 0);
2537 picochip_print_comparison (file
, operand
, 'i');
2538 picochip_print_operand (file
, op1
, 0);
2542 /* This function generates a memory address operand in the given
2543 mode. That is, if the address contains a constant offset, then the
2544 offset is divided by the required mode size to compute the
2545 mode specific offset. By default, picochip_print_operand_address calls
2546 this function using the natural mode of the operand, but special
2547 operand codes can be used to invoke the computation using an
2548 unnatural mode (e.g., compute the HI aligned address of an SI mode
2551 picochip_print_memory_address (FILE * file
, rtx operand
,
2552 enum machine_mode mode
)
2554 rtx address
= XEXP (operand
, 0);
2557 if (MEM
!= GET_CODE (operand
))
2558 fatal_insn ("picochip_print_memory_address - Operand isn't memory based",
2563 printf ("picochip_print_memory_address: ");
2564 print_rtl (stdout
, operand
);
2568 switch (GET_CODE (address
))
2572 /* Grab the address components. */
2573 rtx base
= XEXP (address
, 0);
2574 rtx offset
= XEXP (address
, 1);
2576 /* Only handle reg+const addresses */
2577 if (REG
== GET_CODE (base
) && CONST_INT
== GET_CODE (offset
))
2579 /* Sanity check. If an FP+offset address is given, ensure
2580 that the offset lies within the given frame, or a lower
2582 if (REGNO (base
) == STACK_POINTER_REGNUM
)
2583 gcc_assert (INTVAL (offset
) <= (picochip_arg_area_byte_offset () +
2586 /* Print the base register - identical for all modes. */
2587 fprintf (file
, "(");
2588 picochip_print_operand (file
, base
, 'r');
2589 fprintf (file
, ")");
2591 /* Print the constant offset with compensation for the mode. */
2595 picochip_print_operand (file
, offset
, 'Q');
2599 picochip_print_operand (file
, offset
, 'H');
2604 picochip_print_operand (file
, offset
, 'S');
2608 picochip_print_operand (file
, offset
, 'D');
2622 picochip_print_operand (file
, address
, 's');
2631 inner
= XEXP (address
, 0);
2633 /* Sanity check - the CONST memory address must be a base+offset. */
2634 gcc_assert (PLUS
== GET_CODE (inner
));
2636 base
= XEXP (inner
, 0);
2637 offset
= XEXP (inner
, 1);
2639 fprintf (file
, "&_%s%+d", XSTR (base
, 0), XINT (offset
, 0));
2645 /* Register operand. Provide a zero offset. */
2646 fprintf (file
, "(");
2647 picochip_print_operand (file
, address
, 'r');
2648 fprintf (file
, ")0");
2657 /* Output an operand. Formatting letters allow particular parts of
2658 the operand to be output. */
2660 picochip_print_operand (FILE * file
, rtx operand
, int letter
)
2663 /* Handle special cases. */
2666 /* VLIW continuation, for explicit VLIW sequences. */
2668 fprintf (file
, "\\");
2673 fputc (picochip_get_vliw_alu_id (), file
);
2676 /* Delay slot specifier. */
2678 /* This should be handled in asm_output_opcode. */
2681 /* Instruction mnemonics (e.g., lshift becomes LSL). */
2683 switch (GET_CODE (operand
))
2686 fprintf (file
, "AND");
2689 fprintf (file
, "OR");
2692 fprintf (file
, "XOR");
2695 fprintf (file
, "ADD");
2698 fprintf (file
, "SUB");
2705 /* Symbolic instructions (e.g., lshift becomes <<). */
2707 switch (GET_CODE (operand
))
2710 fprintf (file
, "&");
2713 fprintf (file
, "|");
2716 fprintf (file
, "^");
2719 fprintf (file
, "+");
2722 fprintf (file
, "-");
2725 fprintf (file
, "UNKNOWN_INSN");
2730 default: /* Not a punctuation character - process as normal. */
2734 switch (GET_CODE (operand
))
2740 /* Write a range of registers. */
2741 fprintf (file
, "R[%d:%d]", REGNO (operand
) + 1, REGNO (operand
));
2745 /* The upper register of a pair is requested. */
2746 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 1]);
2750 /* The lower register of a pair is requested. Equivalent to the
2751 default, but included for completeness. */
2752 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2756 /* The 3rd register of a DI mode register. */
2757 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 2]);
2761 /* The 4th register of a DI mode register. */
2762 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 3]);
2766 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2771 /* A range of letters can be used to format integers. The
2772 letters Q/H/S are used to divide the constant by the width of
2773 QI/HI/SI mode integers in bytes. The U/L modifiers are used
2774 to obtain the upper and lower 16-bits of a 32-bit
2775 constant. Where possible, signed numbers are used, since
2776 signed representations of numbers may be more compact (e.g.,
2777 65535 can be represented as -1, which fits into a small
2778 constant, whereas 65535 requires a large constant). */
2782 fprintf (file
, "%ld", INTVAL (operand
));
2786 fprintf (file
, "%ld", INTVAL (operand
) / 2);
2790 fprintf (file
, "%ld", INTVAL (operand
) / 4);
2794 fprintf (file
, "%d", exact_log2 (INTVAL(operand
)));
2798 fprintf (file
, "%hi", (short) ((INTVAL (operand
) >> 16) & 0xFFFF));
2802 fprintf (file
, "%hi", (short) (INTVAL (operand
) & 0xFFFF));
2806 fprintf (file
, "%ld", INTVAL (operand
));
2816 if (GET_MODE (operand
) != SFmode
)
2817 fatal_insn ("Unknown mode in print_operand (CONST_DOUBLE) :",
2819 REAL_VALUE_FROM_CONST_DOUBLE (rv
, operand
);
2820 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
2825 fprintf (file
, "%hi", (short) ((val
>> 16) & 0xFFFF));
2829 fprintf (file
, "%hi", (short) (val
& 0xFFFF));
2837 /* Output a symbol. The output format must match that of
2838 picochip_output_label. */
2840 /* Ensure that the symbol is marked as referenced. Gcc can
2841 occasionally omit the function bodies when it believes them
2842 to be unreferenced. */
2843 if (SYMBOL_REF_DECL (operand
))
2844 mark_decl_referenced (SYMBOL_REF_DECL (operand
));
2845 fprintf (file
, "&");
2846 assemble_name (file
, XSTR (operand
, 0));
2850 /* This format must match that of picochip_output_label. */
2851 fprintf (file
, "&");
2852 output_asm_label (operand
);
2857 rtx addr
= XEXP (operand
, 0);
2862 if (PLUS
!= GET_CODE (addr
))
2863 fatal_insn ("Bad address, not (reg+disp):", addr
);
2865 picochip_print_operand (file
, XEXP (addr
, 1), 0);
2869 /* Output a memory address in byte mode notation (i.e., the
2870 constant address (if any) is the actual byte address. */
2871 picochip_print_memory_address (file
, operand
, QImode
);
2874 /* Output a constant offset of the given mode (i.e., divide
2875 the constant by the number of units in the mode to get the
2878 picochip_print_memory_address (file
, operand
, QImode
);
2882 picochip_print_memory_address (file
, operand
, HImode
);
2886 picochip_print_memory_address (file
, operand
, SImode
);
2890 picochip_print_memory_address (file
, operand
, SFmode
);
2894 if (PLUS
!= GET_CODE (addr
))
2895 fatal_insn ("Bad address, not (reg+disp):", addr
);
2897 picochip_print_operand (file
, XEXP (addr
, 0), 0);
2900 /* When the mem operand is (reg + big offset) which cannot
2901 be represented in an instruction as operand, the compiler
2902 automatically generates the instruction to put in (reg +
2903 big offset) into another register. In such cases, it
2904 returns '0' as the character. This needs to be handled
2908 if (REG
!= GET_CODE (addr
))
2909 fatal_insn ("Bad address, not register:", addr
);
2911 picochip_print_operand (file
, addr
, 0);
2915 fprintf (file
, "Unknown mem operand - letter %c ",
2917 print_rtl (file
, operand
);
2925 rtx const_exp
= XEXP (operand
, 0);
2927 /* Handle constant offsets to symbol references. */
2928 if (PLUS
== GET_CODE (const_exp
) &&
2929 SYMBOL_REF
== GET_CODE (XEXP (const_exp
, 0)) &&
2930 CONST_INT
== GET_CODE (XEXP (const_exp
, 1)))
2933 picochip_print_operand (file
, XEXP (const_exp
, 0), 0);
2934 if (INTVAL (XEXP (const_exp
, 1)) >= 0)
2935 fprintf (file
, "+");
2936 /* else use the - from the operand (i.e., AP-2)) */
2938 picochip_print_operand (file
, XEXP (const_exp
, 1), letter
);
2947 /* PLUS expressions are of the form (base + offset). Different
2948 options (analagous to those of memory PLUS expressions) are used
2949 to extract the base and offset components. */
2954 picochip_print_operand (file
, XEXP (operand
, 0), 0);
2958 picochip_print_operand (file
, XEXP (operand
, 1), 0);
2963 /* If the expression is composed entirely of constants,
2964 evaluate the result. This should only occur with the
2965 picoChip specific comms instructions, which are emitted as
2966 base+offset expressions. */
2967 if (CONST_INT
== GET_CODE (XEXP (operand
, 0)) &&
2968 CONST_INT
== GET_CODE (XEXP (operand
, 1)))
2970 HOST_WIDE_INT result
= (XINT (XEXP (operand
, 0), 0) +
2971 XINT (XEXP (operand
, 1), 0));
2972 fprintf (file
, "%ld", result
);
2976 fprintf (file
, "(");
2977 picochip_print_operand (file
, XEXP (operand
, 0), 0);
2978 fprintf (file
, "+");
2979 picochip_print_operand (file
, XEXP (operand
, 1), 0);
2980 fprintf (file
, ")");
2987 /* Comparison operations. */
2998 picochip_print_comparison (file
, operand
, letter
);
3002 fprintf (stderr
, "Unknown operand encountered in %s\n", __FUNCTION__
);
3003 print_rtl (file
, operand
);
3010 /* Output an operand address */
3012 picochip_print_operand_address (FILE * file
, rtx operand
)
3015 switch (GET_CODE (operand
))
3019 /* This format must match that of picochip_output_label. */
3020 assemble_name (file
, XSTR (operand
, 0));
3024 /* Note this format must match that of picochip_output_label. */
3025 fprintf (file
, "_L%d", XINT (operand
, 5));
3029 /* Pass on to a specialised memory address generator. */
3030 picochip_print_memory_address (file
, operand
, GET_MODE (operand
));
3041 /* Scheduling functions. */
3043 /* Save some of the contents of recog_data. */
3045 picochip_save_recog_data (void)
3047 picochip_saved_which_alternative
= which_alternative
;
3048 memcpy (&picochip_saved_recog_data
, &recog_data
,
3049 sizeof (struct recog_data
));
3052 /* Restore some of the contents of global variable recog_data. */
3054 picochip_restore_recog_data (void)
3056 which_alternative
= picochip_saved_which_alternative
;
3057 memcpy (&recog_data
, &picochip_saved_recog_data
,
3058 sizeof (struct recog_data
));
3061 /* Ensure that no var tracking notes are emitted in the middle of a
3062 three-instruction bundle. */
3064 reorder_var_tracking_notes (void)
3070 rtx queue
= NULL_RTX
;
3072 for (insn
= BB_HEAD (bb
); insn
!= BB_END (bb
); insn
= next
)
3074 next
= NEXT_INSN (insn
);
3076 if (NONDEBUG_INSN_P (insn
))
3078 /* Emit queued up notes before the first instruction of a bundle. */
3079 if (GET_MODE (insn
) == TImode
)
3083 rtx next_queue
= PREV_INSN (queue
);
3084 NEXT_INSN (PREV_INSN(insn
)) = queue
;
3085 PREV_INSN (queue
) = PREV_INSN(insn
);
3086 PREV_INSN (insn
) = queue
;
3087 NEXT_INSN (queue
) = insn
;
3092 else if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_VAR_LOCATION
)
3094 rtx prev
= PREV_INSN (insn
);
3095 PREV_INSN (next
) = prev
;
3096 NEXT_INSN (prev
) = next
;
3097 PREV_INSN (insn
) = queue
;
3104 /* Perform machine dependent operations on the rtl chain INSNS. */
3106 picochip_reorg (void)
3108 rtx insn
, insn1
, vliw_start
= NULL_RTX
;
3109 int vliw_insn_location
= 0;
3111 /* We are freeing block_for_insn in the toplev to keep compatibility
3112 with old MDEP_REORGS that are not CFG based. Recompute it now. */
3113 compute_bb_for_insn ();
3118 if (picochip_schedule_type
!= DFA_TYPE_NONE
)
3120 timevar_push (TV_SCHED2
);
3122 /* Process the instruction list, computing the sizes of each
3123 instruction, and consequently branch distances. This can
3124 result in some branches becoming short enough to be treated
3125 as a real branch instruction, rather than an assembly branch
3126 macro which may expand into multiple instructions. The
3127 benefit of shortening branches is that real branch
3128 instructions can be properly DFA scheduled, whereas macro
3130 shorten_branches (get_insns ());
3132 /* Do control and data sched analysis again,
3133 and write some more of the results to dump file. */
3139 timevar_pop (TV_SCHED2
);
3143 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3145 /* Whenever a VLIW packet is generated, all instructions in
3146 that packet must appear to come from the same source
3147 location. The following code finds all the VLIW packets,
3148 and tags their instructions with the location of the first
3149 instruction from the packet. Clearly this will result in
3150 strange behaviour when debugging the code, but since
3151 debugging and optimisation are being used in conjunction,
3152 strange behaviour is certain to occur anyway. */
3153 /* Slight bit of change. If the vliw set contains a branch
3154 or call instruction, we pick its location.*/
3155 for (insn
= get_insns (); insn
; insn
= next_real_insn (insn
))
3158 /* If this is the first instruction in the VLIW packet,
3159 extract its location. */
3160 if (GET_MODE (insn
) == TImode
)
3163 vliw_insn_location
= INSN_LOCATOR (insn
);
3165 if (JUMP_P (insn
) || CALL_P(insn
))
3167 vliw_insn_location
= INSN_LOCATOR (insn
);
3168 for (insn1
= vliw_start
; insn1
!= insn
; insn1
= next_real_insn (insn1
))
3169 INSN_LOCATOR (insn1
) = vliw_insn_location
;
3171 /* Tag subsequent instructions with the same location. */
3172 INSN_LOCATOR (insn
) = vliw_insn_location
;
3178 /* Locate the note marking the end of the function's prologue. If
3179 the note appears in the middle of a VLIW packet, move the note to
3180 the end. This avoids unpleasant consequences such as trying to
3181 emit prologue markers (e.g., .loc/.file directives) in the middle
3183 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3185 rtx prologue_end_note
= NULL
;
3186 rtx last_insn_in_packet
= NULL
;
3188 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
3190 /* The prologue end must be moved to the end of the VLIW packet. */
3191 if (NOTE_KIND (insn
) == NOTE_INSN_PROLOGUE_END
)
3193 prologue_end_note
= insn
;
3198 /* Find the last instruction in this packet. */
3199 for (insn
= prologue_end_note
; insn
; insn
= next_real_insn (insn
))
3201 if (GET_MODE (insn
) == TImode
)
3204 last_insn_in_packet
= insn
;
3207 if (last_insn_in_packet
!= NULL
)
3209 rtx tmp_note
= emit_note_after (NOTE_KIND(prologue_end_note
), last_insn_in_packet
);
3210 memcpy(&NOTE_DATA (tmp_note
), &NOTE_DATA(prologue_end_note
), sizeof(NOTE_DATA(prologue_end_note
)));
3211 delete_insn (prologue_end_note
);
3214 if (picochip_flag_var_tracking
)
3216 timevar_push (TV_VAR_TRACKING
);
3217 variable_tracking_main ();
3218 /* We also have to deal with variable tracking notes in the middle
3220 reorder_var_tracking_notes();
3221 timevar_pop (TV_VAR_TRACKING
);
3225 /* Return the ALU character identifier for the current
3226 instruction. This will be 0 or 1. */
3228 picochip_get_vliw_alu_id (void)
3232 /* Always use ALU 0 if VLIW scheduling is disabled. */
3233 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3236 /* Get the attribute type of the instruction. Note that this can
3237 ruin the contents of recog_data, so save/restore around the
3239 picochip_save_recog_data ();
3240 attr_type
= get_attr_type (picochip_current_prescan_insn
);
3241 picochip_restore_recog_data ();
3243 if (picochip_current_vliw_state
.contains_pico_alu_insn
)
3246 /* If this a picoAlu insn? If it is, then stuff it into ALU 0,
3247 else it must be the other ALU (either basic or nonCc)
3248 instruction which goes into 1. */
3249 if (attr_type
== TYPE_PICOALU
)
3255 else if (picochip_current_vliw_state
.contains_non_cc_alu_insn
)
3257 /* Is this the non CC instruction? If it is, then stuff it into
3258 ALU 1, else it must be a picoAlu or basicAlu, in which case
3259 it goes into ALU 0. */
3260 if (attr_type
== TYPE_NONCCALU
)
3267 /* No picoAlu/nonCc instructions in use, so purely dependent upon
3268 whether an ALU instruction has already been scheduled in this
3270 switch (picochip_current_vliw_state
.num_alu_insns_so_far
)
3273 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3277 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3281 internal_error ("Too many ALU instructions emitted (%d)\n",
3282 picochip_current_vliw_state
.num_alu_insns_so_far
);
3289 /* Reset any information about the current VLIW packing status. */
3291 picochip_reset_vliw (rtx insn
)
3293 rtx local_insn
= insn
;
3295 /* Nothing to do if VLIW scheduling isn't being used. */
3296 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3300 printf ("%s on insn %d\n", __FUNCTION__
, INSN_UID (insn
));
3303 picochip_current_vliw_state
.contains_pico_alu_insn
= 0;
3304 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 0;
3305 picochip_current_vliw_state
.num_alu_insns_so_far
= 0;
3306 picochip_current_vliw_state
.num_cfi_labels_deferred
= 0;
3307 picochip_current_vliw_state
.lm_label_name
[0] = 0;
3308 picochip_current_vliw_state
.num_insns_in_packet
= 0;
3310 /* Read through the VLIW packet, classifying the instructions where
3315 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3317 local_insn
= NEXT_INSN (local_insn
);
3320 else if (!INSN_P (local_insn
))
3324 /* It is an instruction, but is it ours? */
3325 if (INSN_CODE (local_insn
) != -1)
3329 picochip_current_vliw_state
.num_insns_in_packet
+= 1;
3331 /* Is it a picoAlu or nonCcAlu instruction? Note that the
3332 get_attr_type function can overwrite the values in
3333 the recog_data global, hence this is saved and
3334 restored around the call. Not doing so results in
3335 asm_output_opcode being called with a different
3336 instruction to final_prescan_insn, which is fatal. */
3337 picochip_save_recog_data ();
3338 attr_type
= get_attr_type (local_insn
);
3339 picochip_restore_recog_data ();
3341 if (attr_type
== TYPE_PICOALU
)
3342 picochip_current_vliw_state
.contains_pico_alu_insn
= 1;
3343 if (attr_type
== TYPE_NONCCALU
)
3344 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 1;
3349 /* Get the next instruction. */
3350 local_insn
= NEXT_INSN (local_insn
);
3352 /* Keep going while the next instruction is part of the same
3353 VLIW packet (i.e., its a valid instruction and doesn't mark
3354 the start of a new VLIW packet. */
3356 while (local_insn
&&
3357 (GET_MODE (local_insn
) != TImode
) && (INSN_CODE (local_insn
) != -1));
3362 picochip_sched_reorder (FILE * file
, int verbose
,
3363 rtx
* ready ATTRIBUTE_UNUSED
,
3364 int *n_readyp ATTRIBUTE_UNUSED
, int clock
)
3368 fprintf (file
, ";;\tClock %d\n", clock
);
3370 return picochip_sched_issue_rate ();
3375 picochip_sched_lookahead (void)
3377 /* It should always be enough to lookahead by 2 insns. Only slot0/1 could
3383 picochip_sched_issue_rate (void)
3388 /* Adjust the scheduling cost between the two given instructions,
3389 which have the given dependency. */
3391 picochip_sched_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
3396 printf ("Sched Adjust Cost: %d->%d is %d\n",
3397 INSN_UID (insn
), INSN_UID (dep_insn
), cost
);
3399 printf (" Dependency type:");
3400 switch (REG_NOTE_KIND (link
))
3408 case REG_DEP_OUTPUT
:
3409 printf ("OUTPUT\n");
3412 printf ("Unknown (%d)\n", REG_NOTE_KIND (link
));
3416 /* Anti-dependencies are used to enforce the ordering between a
3417 * branch, and any subsequent instructions. For example:
3422 * The ADD instruction must execute after the branch, and this is
3423 * enforced using an anti-dependency. Unfortunately, VLIW machines
3424 * are happy to execute anti-dependent instructions in the same
3425 * cycle, which then results in a schedule like the following being
3428 * BNE someLabel \ ADD.0 r0,r1,r2
3430 * The instruction which would normally be conditionally executed
3431 * depending upon the outcome of the branch, is now unconditionally
3432 * executed every time. To prevent this happening, any
3433 * anti-dependencies between a branch and another instruction are
3434 * promoted to become real dependencies.
3436 if ((JUMP_P (dep_insn
) || CALL_P(dep_insn
)) && REG_NOTE_KIND (link
) == REG_DEP_ANTI
)
3440 printf ("Promoting anti-dependency %d->%d to a true-dependency\n",
3441 INSN_UID (insn
), INSN_UID (dep_insn
));
3450 /* Return the minimum of the two values */
3452 minimum (int a
, int b
)
3458 /* I dont expect to get to this function with a==b.*/
3463 /* This function checks if the memory of the two stores are just off by 2 bytes.
3464 It returns the lower memory operand's index.*/
3467 memory_just_off (rtx opnd1
, rtx opnd2
)
3469 int offset1
= 0, offset2
= 0;
3472 if (GET_CODE(XEXP(opnd1
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
, 0),1)) == CONST_INT
)
3474 offset1
= INTVAL(XEXP(XEXP(opnd1
, 0), 1));
3475 reg1
= REGNO(XEXP(XEXP(opnd1
, 0), 0));
3479 reg1
= REGNO(XEXP(opnd1
, 0));
3481 if (GET_CODE(XEXP(opnd2
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
, 0), 1)) == CONST_INT
)
3483 offset2
= INTVAL(XEXP(XEXP(opnd2
, 0), 1));
3484 reg2
= REGNO(XEXP(XEXP(opnd2
, 0), 0));
3488 reg2
= REGNO(XEXP(opnd2
, 0));
3491 /* Peepholing 2 STW/LDWs has the restriction that the resulting STL/LDL's address
3492 should be 4 byte aligned. We can currently guarentee that only if the base
3493 address is FP(R13) and the offset is aligned. */
3495 if (reg1
== reg2
&& reg1
== 13 && abs(offset1
-offset2
) == 2 && minimum(offset1
, offset2
) % 4 == 0)
3496 return (minimum(offset1
, offset2
) == offset1
) ? 1:2;
3502 registers_just_off (rtx opnd1
, rtx opnd2
)
3505 reg1
= REGNO(opnd1
);
3506 reg2
= REGNO(opnd2
);
3507 if (abs(reg1
-reg2
) == 1 && minimum(reg1
, reg2
) % 2 == 0)
3508 return (minimum(reg1
, reg2
) == reg1
)?1:2;
3512 /* Check to see if the two LDWs can be peepholed together into a LDL
3513 They can be if the registers getting loaded into are contiguous
3514 and the memory addresses are contiguous as well.
3518 can be merged together into
3522 1. The LDWs themselves only guarentee that r11 will be a 2-byte
3523 aligned address. Only FP can be assumed to be 4 byte aligned.
3524 2. The progression of addresses and the register numbers should
3525 be similar. For eg., if you swap r2 and r3 in the above instructions,
3526 the resultant pair cannot be merged.
3530 ok_to_peephole_ldw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3532 int memtest
=0,regtest
=0;
3533 regtest
= registers_just_off(opnd1
,opnd3
);
3537 memtest
= memory_just_off(opnd0
,opnd2
);
3541 if (regtest
== memtest
)
3548 /* Similar to LDW peephole */
3550 ok_to_peephole_stw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3552 int memtest
=0,regtest
=0;
3553 regtest
= registers_just_off(opnd1
,opnd3
);
3557 memtest
= memory_just_off(opnd0
,opnd2
);
3561 if (regtest
== memtest
)
3569 /* Generate a SImode register with the register number that is the smaller of the two */
3571 gen_min_reg(rtx opnd1
,rtx opnd2
)
3573 return gen_rtx_REG (SImode
, minimum(REGNO(opnd1
),REGNO(opnd2
)));
3576 /* Generate a SImode memory with the address that is the smaller of the two */
3578 gen_SImode_mem(rtx opnd1
,rtx opnd2
)
3580 int offset1
=0,offset2
=0;
3582 if (GET_CODE(XEXP(opnd1
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
,0),1)) == CONST_INT
)
3584 offset1
= INTVAL(XEXP(XEXP(opnd1
,0),1));
3585 reg
= XEXP(XEXP(opnd1
,0),0);
3589 reg
= XEXP(opnd1
,0);
3591 if (GET_CODE(XEXP(opnd2
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
,0),1)) == CONST_INT
)
3593 offset2
= INTVAL(XEXP(XEXP(opnd2
,0),1));
3595 rtx address
= gen_rtx_PLUS (HImode
, reg
, GEN_INT(minimum(offset1
,offset2
)));
3596 return gen_rtx_MEM(SImode
,address
);
3600 picochip_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
, int* total
, bool speed
)
3607 /* Need to penalize immediates that need to be encoded as long constants.*/
3608 if (code
== CONST_INT
&& !(INTVAL (x
) >= 0 && INTVAL (x
) < 16))
3610 *total
= COSTS_N_INSNS(1);
3618 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
3623 /* if_then_else come out of cbranch instructions. It will get split into
3624 a condition code generating subtraction and a branch */
3625 *total
= COSTS_N_INSNS (2);
3632 if (GET_MODE(x
) == SImode
)
3633 *total
= COSTS_N_INSNS (2);
3634 if (GET_MODE(x
) == DImode
)
3635 *total
= COSTS_N_INSNS (4);
3639 /* Byte Memory access on a NO_BYTE_ACCESS machine would be expensive */
3640 if (GET_MODE(x
) == QImode
&& !TARGET_HAS_BYTE_ACCESS
)
3641 *total
= COSTS_N_INSNS (10);
3643 /* 64-bit accesses have to be done through 2 32-bit access */
3644 if (GET_MODE(x
) == DImode
)
3645 *total
= COSTS_N_INSNS (2);
3651 /* SImode shifts are expensive */
3652 if (GET_MODE(x
) == SImode
)
3653 *total
= COSTS_N_INSNS (10);
3655 /* Register shift by constant is cheap. */
3656 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3657 && GET_CODE(XEXP(x
, 0)) == REG
3658 && GET_CODE(XEXP(x
, 1)) == CONST_INT
)
3659 *total
= COSTS_N_INSNS (1);
3661 *total
= COSTS_N_INSNS (4);
3668 /* Divisions are more expensive than the default 7*/
3669 if (GET_MODE(x
) == SImode
)
3670 *total
= COSTS_N_INSNS (20);
3672 *total
= COSTS_N_INSNS (12);
3677 /* Look for the simple cases of multiplying register*register or
3678 register*constant. */
3679 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3680 && ((GET_CODE(XEXP(x
, 0)) == REG
3681 && (GET_CODE(XEXP(x
, 1)) == REG
|| GET_CODE(XEXP(x
,1)) == CONST_INT
))
3682 || (GET_CODE(XEXP(x
, 0)) == ZERO_EXTEND
3683 && GET_CODE(XEXP(XEXP(x
, 0),0)) == REG
3684 && GET_CODE(XEXP(x
, 1)) == ZERO_EXTEND
3685 && GET_CODE(XEXP(XEXP(x
, 1),0)) == REG
)))
3688 /* When optimising for size, multiplication by constant
3689 should be discouraged slightly over multiplication by a
3691 if (picochip_has_mac_unit
)
3693 /* Single cycle multiplication, but the result must be
3694 loaded back into a general register afterwards. */
3695 *total
= COSTS_N_INSNS(2);
3698 else if (picochip_has_mul_unit
)
3700 /* Single cycle multiplication. */
3701 *total
= COSTS_N_INSNS(1);
3704 /* Else no multiply available. Use default cost. */
3714 if (localTotal
!= 0)
3716 *total
= localTotal
;
3727 picochip_final_prescan_insn (rtx insn
, rtx
* opvec ATTRIBUTE_UNUSED
,
3728 int num_operands ATTRIBUTE_UNUSED
)
3732 picochip_current_prescan_insn
= insn
;
3735 printf ("Final prescan on INSN %d with mode %s\n",
3736 INSN_UID (insn
), GET_MODE_NAME (GET_MODE (insn
)));
3738 /* If this is the start of a new instruction cycle, or no scheduling
3739 is used, then reset the VLIW status. */
3740 if (GET_MODE (insn
) == TImode
|| !picochip_schedule_type
== DFA_TYPE_SPEED
)
3741 picochip_reset_vliw (insn
);
3743 /* No VLIW scheduling occured, so don't go any further. */
3744 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3747 /* Look for the next printable instruction. This loop terminates on
3748 any recognisable instruction, and on any unrecognisable
3749 instruction with TImode. */
3751 for (local_insn
= NEXT_INSN (local_insn
); local_insn
;
3752 local_insn
= NEXT_INSN (local_insn
))
3754 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3756 else if (!INSN_P (local_insn
))
3758 else if (GET_MODE (local_insn
) == TImode
3759 || INSN_CODE (local_insn
) != -1)
3763 /* Set the continuation flag if the next instruction can be packed
3764 with the current instruction (i.e., the next instruction is
3765 valid, and isn't the start of a new cycle). */
3766 picochip_vliw_continuation
= (local_insn
&& NONDEBUG_INSN_P (local_insn
) &&
3767 (GET_MODE (local_insn
) != TImode
));
3771 /* Builtin functions. */
3772 /* Given a builtin function taking 2 operands (i.e., target + source),
3773 emit the RTL for the underlying instruction. */
3775 picochip_expand_builtin_2op (enum insn_code icode
, tree call
, rtx target
)
3779 enum machine_mode tmode
, mode0
;
3781 /* Grab the incoming argument and emit its RTL. */
3782 arg0
= CALL_EXPR_ARG (call
, 0);
3783 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3785 /* Determine the modes of the instruction operands. */
3786 tmode
= insn_data
[icode
].operand
[0].mode
;
3787 mode0
= insn_data
[icode
].operand
[1].mode
;
3789 /* Ensure that the incoming argument RTL is in a register of the
3791 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3792 op0
= copy_to_mode_reg (mode0
, op0
);
3794 /* If there isn't a suitable target, emit a target register. */
3796 || GET_MODE (target
) != tmode
3797 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3798 target
= gen_reg_rtx (tmode
);
3800 /* Emit and return the new instruction. */
3801 pat
= GEN_FCN (icode
) (target
, op0
);
3810 /* Given a builtin function taking 3 operands (i.e., target + two
3811 source), emit the RTL for the underlying instruction. */
3813 picochip_expand_builtin_3op (enum insn_code icode
, tree call
, rtx target
)
3817 enum machine_mode tmode
, mode0
, mode1
;
3819 /* Grab the function's arguments. */
3820 arg0
= CALL_EXPR_ARG (call
, 0);
3821 arg1
= CALL_EXPR_ARG (call
, 1);
3823 /* Emit rtl sequences for the function arguments. */
3824 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3825 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
3827 /* Get the mode's of each of the instruction operands. */
3828 tmode
= insn_data
[icode
].operand
[0].mode
;
3829 mode0
= insn_data
[icode
].operand
[1].mode
;
3830 mode1
= insn_data
[icode
].operand
[2].mode
;
3832 /* Ensure that each of the function argument rtl sequences are in a
3833 register of the correct mode. */
3834 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3835 op0
= copy_to_mode_reg (mode0
, op0
);
3836 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
3837 op1
= copy_to_mode_reg (mode1
, op1
);
3839 /* If no target has been given, create a register to use as the target. */
3841 || GET_MODE (target
) != tmode
3842 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3843 target
= gen_reg_rtx (tmode
);
3845 /* Emit and return the new instruction. */
3846 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
3855 /* Expand a builtin function which takes two arguments, and returns a void. */
3857 picochip_expand_builtin_2opvoid (enum insn_code icode
, tree call
)
3861 enum machine_mode mode0
, mode1
;
3863 /* Grab the function's arguments. */
3864 arg0
= CALL_EXPR_ARG (call
, 0);
3865 arg1
= CALL_EXPR_ARG (call
, 1);
3867 /* Emit rtl sequences for the function arguments. */
3868 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3869 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
3871 /* Get the mode's of each of the instruction operands. */
3872 mode0
= insn_data
[icode
].operand
[0].mode
;
3873 mode1
= insn_data
[icode
].operand
[1].mode
;
3875 /* Ensure that each of the function argument rtl sequences are in a
3876 register of the correct mode. */
3877 if (!(*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
3878 op0
= copy_to_mode_reg (mode0
, op0
);
3879 if (!(*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
3880 op1
= copy_to_mode_reg (mode1
, op1
);
3882 /* Emit and return the new instruction. */
3883 pat
= GEN_FCN (icode
) (op0
, op1
);
3892 /* Expand an array get into the corresponding RTL. */
3894 picochip_expand_array_get (tree call
, rtx target
)
3896 tree arg0
, arg1
, arg2
;
3897 rtx op0
, op1
, op2
, pat
;
3899 /* Grab the function's arguments. */
3900 arg0
= CALL_EXPR_ARG (call
, 0);
3901 arg1
= CALL_EXPR_ARG (call
, 1);
3902 arg2
= CALL_EXPR_ARG (call
, 2) ;
3904 /* Emit rtl sequences for the function arguments. */
3905 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3906 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
3907 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
3909 /* The second and third operands must be constant. Nothing else will
3911 if (CONST_INT
!= GET_CODE (op1
))
3912 internal_error ("%s: Second source operand is not a constant",
3914 if (CONST_INT
!= GET_CODE (op2
))
3915 internal_error ("%s: Third source operand is not a constant",
3918 /* If no target has been given, create a register to use as the target. */
3919 if (target
== 0 || GET_MODE (target
) != SImode
)
3920 target
= gen_reg_rtx (SImode
);
3922 /* The first operand must be a HImode register or a constant. If it
3923 isn't, force it into a HImode register. */
3924 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
3925 op0
= copy_to_mode_reg (HImode
, op0
);
3928 /* Emit and return the new instruction. */
3929 pat
= gen_commsArrayGet (target
, op0
, op1
, op2
);
3936 /* Expand an array put into the corresponding RTL. */
3938 picochip_expand_array_put (tree call
, rtx target
)
3940 tree arg0
, arg1
, arg2
, arg3
;
3941 rtx op0
, op1
, op2
, op3
, pat
;
3943 /* Grab the function's arguments. */
3944 arg0
= CALL_EXPR_ARG (call
, 0);
3945 arg1
= CALL_EXPR_ARG (call
, 1);
3946 arg2
= CALL_EXPR_ARG (call
, 2);
3947 arg3
= CALL_EXPR_ARG (call
, 3);
3949 /* Emit rtl sequences for the function arguments. */
3950 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3951 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
3952 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
3953 op3
= expand_expr (arg3
, NULL_RTX
, VOIDmode
, 0);
3955 /* The first operand must be an SImode register. */
3956 if (GET_MODE (op0
) != SImode
|| REG
!= GET_CODE (op0
))
3957 op0
= copy_to_mode_reg (SImode
, op0
);
3959 /* The second (index) operand must be a HImode register, or a
3960 constant. If it isn't, force it into a HImode register. */
3961 if (GET_MODE (op1
) != HImode
|| REG
!= GET_CODE (op1
))
3962 op1
= copy_to_mode_reg (HImode
, op1
);
3964 /* The remaining operands must be constant. Nothing else will do. */
3965 if (CONST_INT
!= GET_CODE (op2
))
3966 internal_error ("%s: Third source operand is not a constant",
3968 if (CONST_INT
!= GET_CODE (op3
))
3969 internal_error ("%s: Fourth source operand is not a constant",
3972 /* Emit and return the new instruction. */
3973 pat
= gen_commsArrayPut (op0
, op1
, op2
, op3
);
3980 /* Expand an array testport into the corresponding RTL. */
3982 picochip_expand_array_testport (tree call
, rtx target
)
3984 tree arg0
, arg1
, arg2
;
3985 rtx op0
, op1
, op2
, pat
;
3987 /* Grab the function's arguments. */
3988 arg0
= CALL_EXPR_ARG (call
, 0);
3989 arg1
= CALL_EXPR_ARG (call
, 1);
3990 arg2
= CALL_EXPR_ARG (call
, 2);
3992 /* Emit rtl sequences for the function arguments. */
3993 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
3994 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
3995 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
3997 /* The first operand must be a HImode register, or a constant. If it
3998 isn't, force it into a HImode register. */
3999 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
4000 op0
= copy_to_mode_reg (HImode
, op0
);
4002 /* The second and third operands must be constant. Nothing else will
4004 if (CONST_INT
!= GET_CODE (op1
))
4005 internal_error ("%s: Second source operand is not a constant",
4007 if (CONST_INT
!= GET_CODE (op2
))
4008 internal_error ("%s: Third source operand is not a constant",
4011 /* If no target has been given, create a HImode register to use as
4013 if (target
== 0 || GET_MODE (target
) != HImode
)
4014 target
= gen_reg_rtx (HImode
);
4016 /* Emit and return the new instruction. */
4017 pat
= gen_commsArrayTestPort (target
, op0
, op1
, op2
);
4024 /* Generate a unique HALT instruction by giving the instruction a
4025 unique integer. This integer makes no difference to the assembly
4026 output (other than a comment indicating the supplied id), but the
4027 presence of the unique integer prevents the compiler from combining
4028 several different halt instructions into one instruction. This
4029 means that each use of the halt instruction is unique, which in
4030 turn means that assertions work as expected. */
4032 picochip_generate_halt (void)
4034 static int currentId
= 0;
4035 rtx id
= GEN_INT (currentId
);
4039 emit_insn (gen_halt (id
));
4041 /* A barrier is inserted to prevent the compiler from thinking that
4042 it has to continue execution after the HALT.*/
4045 rtx insns
= get_insns();
4052 /* Initialise the builtin functions. Start by initialising
4053 descriptions of different types of functions (e.g., void fn(int),
4054 int fn(void)), and then use these to define the builtins. */
4056 picochip_init_builtins (void)
4058 tree endlink
= void_list_node
;
4059 tree int_endlink
= tree_cons (NULL_TREE
, integer_type_node
, endlink
);
4060 tree unsigned_endlink
= tree_cons (NULL_TREE
, unsigned_type_node
, endlink
);
4061 tree long_endlink
= tree_cons (NULL_TREE
, long_integer_type_node
, endlink
);
4062 tree int_int_endlink
=
4063 tree_cons (NULL_TREE
, integer_type_node
, int_endlink
);
4064 tree int_int_int_endlink
=
4065 tree_cons (NULL_TREE
, integer_type_node
, int_int_endlink
);
4066 tree int_long_endlink
=
4067 tree_cons (NULL_TREE
, integer_type_node
, long_endlink
);
4068 tree pchar_type_node
= build_pointer_type (char_type_node
);
4069 tree long_int_int_int_endlink
=
4070 tree_cons (NULL_TREE
, long_integer_type_node
, int_int_int_endlink
);
4072 tree int_ftype_void
, int_ftype_int
, int_ftype_int_int
, void_ftype_pchar
;
4073 tree long_ftype_int
, long_ftype_int_int
, long_ftype_int_int_int
;
4074 tree void_ftype_int_long
, int_ftype_int_int_int
,
4075 void_ftype_long_int_int_int
;
4076 tree void_ftype_void
, void_ftype_int
, unsigned_ftype_unsigned
;
4078 /* void func (void) */
4079 void_ftype_void
= build_function_type (void_type_node
, endlink
);
4081 /* void func (void *) */
4083 = build_function_type (void_type_node
,
4084 tree_cons (NULL_TREE
, pchar_type_node
, endlink
));
4086 /* int func (void) */
4087 int_ftype_void
= build_function_type (integer_type_node
, endlink
);
4089 /* void func (int) */
4090 void_ftype_int
= build_function_type (void_type_node
, int_endlink
);
4092 /* int func (int) */
4093 int_ftype_int
= build_function_type (integer_type_node
, int_endlink
);
4095 /* unsigned int func (unsigned int) */
4096 unsigned_ftype_unsigned
= build_function_type (unsigned_type_node
, unsigned_endlink
);
4098 /* int func(int, int) */
4100 = build_function_type (integer_type_node
, int_int_endlink
);
4102 /* long func(int) */
4103 long_ftype_int
= build_function_type (long_integer_type_node
, int_endlink
);
4105 /* long func(int, int) */
4107 = build_function_type (long_integer_type_node
, int_int_endlink
);
4109 /* long func(int, int, int) */
4110 long_ftype_int_int_int
4111 = build_function_type (long_integer_type_node
, int_int_int_endlink
);
4113 /* int func(int, int, int) */
4114 int_ftype_int_int_int
4115 = build_function_type (integer_type_node
, int_int_int_endlink
);
4117 /* void func(int, long) */
4119 = build_function_type (void_type_node
, int_long_endlink
);
4121 /* void func(long, int, int, int) */
4122 void_ftype_long_int_int_int
4123 = build_function_type (void_type_node
, long_int_int_int_endlink
);
4125 /* Initialise the sign-bit-count function. */
4126 add_builtin_function ("__builtin_sbc", int_ftype_int
,
4127 PICOCHIP_BUILTIN_SBC
, BUILT_IN_MD
, NULL
,
4129 add_builtin_function ("picoSbc", int_ftype_int
, PICOCHIP_BUILTIN_SBC
,
4130 BUILT_IN_MD
, NULL
, NULL_TREE
);
4132 /* Initialise the bit reverse function. */
4133 add_builtin_function ("__builtin_brev", unsigned_ftype_unsigned
,
4134 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4136 add_builtin_function ("picoBrev", unsigned_ftype_unsigned
,
4137 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4140 /* Initialise the byte swap function. */
4141 add_builtin_function ("__builtin_byteswap", unsigned_ftype_unsigned
,
4142 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4144 add_builtin_function ("picoByteSwap", unsigned_ftype_unsigned
,
4145 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4148 /* Initialise the ASRI function (note that while this can be coded
4149 using a signed shift in C, extra scratch registers are required,
4150 which we avoid by having a direct builtin to map to the
4152 add_builtin_function ("__builtin_asri", int_ftype_int_int
,
4153 PICOCHIP_BUILTIN_ASRI
, BUILT_IN_MD
, NULL
,
4156 /* Initialise saturating addition. */
4157 add_builtin_function ("__builtin_adds", int_ftype_int_int
,
4158 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4160 add_builtin_function ("picoAdds", int_ftype_int_int
,
4161 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4164 /* Initialise saturating subtraction. */
4165 add_builtin_function ("__builtin_subs", int_ftype_int_int
,
4166 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4168 add_builtin_function ("picoSubs", int_ftype_int_int
,
4169 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4172 /* Scalar comms builtins. */
4173 add_builtin_function ("__builtin_get", long_ftype_int
,
4174 PICOCHIP_BUILTIN_GET
, BUILT_IN_MD
, NULL
,
4176 add_builtin_function ("__builtin_put", void_ftype_int_long
,
4177 PICOCHIP_BUILTIN_PUT
, BUILT_IN_MD
, NULL
,
4179 add_builtin_function ("__builtin_testport", int_ftype_int
,
4180 PICOCHIP_BUILTIN_TESTPORT
, BUILT_IN_MD
, NULL
,
4183 /* Array comms builtins. */
4184 add_builtin_function ("__builtin_put_array",
4185 void_ftype_long_int_int_int
,
4186 PICOCHIP_BUILTIN_PUT_ARRAY
, BUILT_IN_MD
, NULL
,
4188 add_builtin_function ("__builtin_get_array", long_ftype_int_int_int
,
4189 PICOCHIP_BUILTIN_GET_ARRAY
, BUILT_IN_MD
, NULL
,
4191 add_builtin_function ("__builtin_testport_array",
4192 int_ftype_int_int_int
,
4193 PICOCHIP_BUILTIN_TESTPORT_ARRAY
, BUILT_IN_MD
,
4196 /* Halt instruction. Note that the builtin function is marked as
4197 having the attribute `noreturn' so that the compiler realises
4198 that the halt stops the program dead. */
4199 tree noreturn
= tree_cons (get_identifier ("noreturn"), NULL
, NULL
);
4200 add_builtin_function ("__builtin_halt", void_ftype_void
,
4201 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4203 add_builtin_function ("picoHalt", void_ftype_void
,
4204 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4209 /* Expand a call to a builtin function. */
4211 picochip_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
4212 enum machine_mode mode ATTRIBUTE_UNUSED
,
4213 int ignore ATTRIBUTE_UNUSED
)
4215 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
4216 int fcode
= DECL_FUNCTION_CODE (fndecl
);
4220 case PICOCHIP_BUILTIN_ASRI
:
4221 return picochip_expand_builtin_3op (CODE_FOR_builtin_asri
, exp
,
4224 case PICOCHIP_BUILTIN_ADDS
:
4225 return picochip_expand_builtin_3op (CODE_FOR_sataddhi3
, exp
,
4228 case PICOCHIP_BUILTIN_SUBS
:
4229 return picochip_expand_builtin_3op (CODE_FOR_satsubhi3
, exp
,
4232 case PICOCHIP_BUILTIN_SBC
:
4233 return picochip_expand_builtin_2op (CODE_FOR_sbc
, exp
, target
);
4235 case PICOCHIP_BUILTIN_BREV
:
4236 return picochip_expand_builtin_2op (CODE_FOR_brev
, exp
, target
);
4238 case PICOCHIP_BUILTIN_BYTESWAP
:
4239 return picochip_expand_builtin_2op (CODE_FOR_bswaphi2
, exp
, target
);
4241 case PICOCHIP_BUILTIN_GET
:
4242 return picochip_expand_builtin_2op (CODE_FOR_commsGet
, exp
, target
);
4244 case PICOCHIP_BUILTIN_PUT
:
4245 return picochip_expand_builtin_2opvoid (CODE_FOR_commsPut
, exp
);
4247 case PICOCHIP_BUILTIN_TESTPORT
:
4248 return picochip_expand_builtin_2op (CODE_FOR_commsTestPort
, exp
,
4251 case PICOCHIP_BUILTIN_PUT_ARRAY
:
4252 return picochip_expand_array_put (exp
, target
);
4254 case PICOCHIP_BUILTIN_GET_ARRAY
:
4255 return picochip_expand_array_get (exp
, target
);
4257 case PICOCHIP_BUILTIN_TESTPORT_ARRAY
:
4258 return picochip_expand_array_testport (exp
, target
);
4260 case PICOCHIP_BUILTIN_HALT
:
4261 return picochip_generate_halt ();
4268 /* Should really do something sensible here. */
4272 /* Emit warnings. */
4274 picochip_warn_inefficient (const char *msg
)
4276 if (TARGET_INEFFICIENT_WARNINGS
)
4277 warning (OPT_minefficient_warnings
,
4278 "%s (disable warning using -mno-inefficient-warnings)", msg
);
4282 warn_of_byte_access (void)
4284 static int warned
= 0;
4288 picochip_warn_inefficient
4289 ("byte access is synthesised - consider using MUL AE");
4296 picochip_function_value (const_tree valtype
, const_tree func
,
4297 bool outgoing ATTRIBUTE_UNUSED
)
4299 enum machine_mode mode
= TYPE_MODE (valtype
);
4300 int unsignedp
= TYPE_UNSIGNED (valtype
);
4302 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
4303 just as PROMOTE_MODE does. */
4304 mode
= promote_function_mode (valtype
, mode
, &unsignedp
, func
, 1);
4306 return gen_rtx_REG (mode
, 0);
4310 /* Check that the value of the given mode will fit in the register of
4313 picochip_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
4316 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4317 return regno
== CC_REGNUM
;
4319 /* If the CC register is being used, then only CC mode values are
4320 allowed (which have already been tested). */
4321 if (regno
== CC_REGNUM
|| regno
== ACC_REGNUM
)
4324 /* Must be a valid register. */
4328 /* Modes QI and HI may be placed in any register except the CC. */
4329 if (mode
== QImode
|| mode
== HImode
)
4332 /* DI must be in a quad register. */
4334 return (regno
% 4 == 0);
4336 /* All other modes must be placed in a even numbered register. */
4337 return !(regno
& 1);
4341 /* Extract the lower and upper components of a constant value. */
4344 picochip_get_low_const (rtx value
)
4346 return gen_int_mode (INTVAL (value
) & 0xFFFF, HImode
);
4350 picochip_get_high_const (rtx value
)
4352 /*return GEN_INT ((((INTVAL (value) >> 16) & 0xFFFF) ^ 0x8000) - 0x8000); */
4353 return gen_int_mode ((INTVAL (value
) >> 16) & 0xFFFF, HImode
);
4357 /* Loading and storing QImode values to and from memory in a machine
4358 without byte access requires might require a scratch
4359 register. However, the scratch register might correspond to the
4360 register in which the value is being loaded. To ensure that a
4361 scratch register is supplied which is definitely different to the
4362 output register, request a register pair. This effectively gives a
4363 choice of two registers to choose from, so that we a guaranteed to
4364 get at least one register which is different to the output
4365 register. This trick is taken from the alpha implementation. */
4367 picochip_secondary_reload (bool in_p
,
4368 rtx x ATTRIBUTE_UNUSED
,
4369 enum reg_class cla ATTRIBUTE_UNUSED
,
4370 enum machine_mode mode
,
4371 secondary_reload_info
*sri
)
4373 if (mode
== QImode
&& !TARGET_HAS_BYTE_ACCESS
)
4376 sri
->icode
= CODE_FOR_reload_outqi
;
4378 sri
->icode
= CODE_FOR_reload_inqi
;
4381 /* We dont need to return a register class type when we need only a
4382 scratch register. It realizes the scratch register type by looking
4383 at the instruction definition for sri->icode. We only need to
4384 return the register type when we need intermediaries for copies.*/
4388 /* Return true if the given memory operand can be aligned to a
4389 word+offset memory reference (e.g., FP+3 can be converted into the
4390 memory operand FP+2, with the offset 1). */
4392 picochip_alignable_memory_operand (rtx mem_operand
,
4393 enum machine_mode mode ATTRIBUTE_UNUSED
)
4397 /* Not a mem operand. Refuse immediately. */
4398 if (MEM
!= GET_CODE (mem_operand
))
4401 address
= XEXP (mem_operand
, 0);
4403 /* Return true if a PLUS of the SP and a (valid) constant, or SP itself. */
4404 return ((PLUS
== GET_CODE (address
) &&
4405 REGNO (XEXP (address
, 0)) == STACK_POINTER_REGNUM
&&
4406 CONST_INT
== GET_CODE (XEXP (address
, 1)) &&
4407 picochip_const_ok_for_letter_p (INTVAL (XEXP (address
, 1)), 'K'))
4408 || (REG
== GET_CODE (address
)
4409 && REGNO (address
) == STACK_POINTER_REGNUM
));
4413 /* Return true if the given memory reference is to a word aligned
4414 address. Currently this means it must be either SP, or
4415 SP+offset. We could replace this function with alignable
4416 memory references in the above function?. */
4418 picochip_word_aligned_memory_reference (rtx operand
)
4422 /* The address must be the SP register, or a constant, aligned
4423 offset from SP which doesn't exceed the FP+offset
4425 return ((PLUS
== GET_CODE (operand
)
4426 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
4427 && picochip_is_aligned (INTVAL (XEXP (operand
, 1)), 16)
4428 && picochip_const_ok_for_letter_p (INTVAL (XEXP (operand
, 1)),
4430 || (REG
== GET_CODE (operand
)
4431 && REGNO (operand
) == STACK_POINTER_REGNUM
));
4435 /* Given an alignable memory location, convert the memory location
4436 into a HI mode access, storing the new memory reference in
4437 paligned_mem, and the number of bits by which to shift in pbitnum
4438 (i.e., given a reference to FP+3, this creates an aligned reference
4439 of FP+2, with an 8-bit shift). This code is a modification of that
4440 found in the Alpha port. */
4442 picochip_get_hi_aligned_mem (rtx ref
, rtx
* paligned_mem
, rtx
* pbitnum
)
4445 HOST_WIDE_INT offset
= 0;
4447 gcc_assert (GET_CODE (ref
) == MEM
);
4449 if (reload_in_progress
&& !memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
4451 base
= find_replacement (&XEXP (ref
, 0));
4453 gcc_assert(memory_address_p (GET_MODE (ref
), base
));
4457 base
= XEXP (ref
, 0);
4460 if (GET_CODE (base
) == PLUS
)
4462 offset
+= INTVAL (XEXP (base
, 1));
4463 base
= XEXP (base
, 0);
4466 *paligned_mem
= widen_memory_access (ref
, HImode
, (offset
& ~1) - offset
);
4473 ("Found non-zero offset in get_hi_aligned_mem - check that the correct value is being used (as this functionality hasn't been exploited yet).\n");
4477 *pbitnum
= GEN_INT ((offset
& 1) * 8);
4481 /* Return true if the given operand is an absolute address in memory
4482 (i.e., a symbolic offset). */
4484 picochip_absolute_memory_operand (rtx op
,
4485 enum machine_mode mode ATTRIBUTE_UNUSED
)
4488 if (MEM
== GET_CODE (op
))
4490 rtx address
= XEXP (op
, 0);
4492 /* Symbols are valid absolute addresses. */
4493 if (SYMBOL_REF
== GET_CODE (address
))
4496 /* Constant offsets to symbols are valid absolute addresses. */
4497 if (CONST
== GET_CODE (address
) &&
4498 PLUS
== GET_CODE (XEXP (address
, 0)) &&
4499 SYMBOL_REF
== GET_CODE (XEXP (XEXP (address
, 0), 0)) &&
4500 CONST_INT
== GET_CODE (XEXP (XEXP (address
, 0), 1)))
4507 /* Symbols are valid absolute addresses. */
4508 if (SYMBOL_REF
== GET_CODE (XEXP (op
, 0)))
4517 picochip_asm_named_section (const char *name
,
4518 unsigned int flags ATTRIBUTE_UNUSED
,
4519 tree decl ATTRIBUTE_UNUSED
)
4521 fprintf (asm_out_file
, ".section %s\n", name
);
4525 /* Check if we can make a conditional copy instruction. This is emitted as an
4526 instruction to set the condition register, followed by an instruction which
4527 uses the condition registers to perform the conditional move. */
4529 picochip_check_conditional_copy (rtx
* operands
)
4532 rtx branch_op_0
= XEXP (operands
[1], 0);
4533 rtx branch_op_1
= XEXP (operands
[1], 1);
4535 /* Only HI mode conditional moves are currently allowed. Can we add
4537 if (GET_CODE (operands
[1]) != EQ
&& GET_CODE (operands
[1]) != NE
)
4540 /* Is the comparison valid? Only allow operands which are registers
4541 if they are HImode. SI mode comparisons against 0 could be
4542 handled using logical operations (e.g., SIreg != 0 when low ||
4543 high). Need to find test cases to provoke this though (fixunssfdi
4544 in libgcc does, but is complicated). */
4545 if (register_operand(branch_op_0
, GET_MODE(branch_op_0
)) &&
4546 GET_MODE(branch_op_0
) != HImode
)
4548 if (register_operand(branch_op_1
, GET_MODE(branch_op_1
)) &&
4549 GET_MODE(branch_op_1
) != HImode
)
4558 picochip_static_chain (const_tree
ARG_UNUSED (fndecl
), bool incoming_p
)
4562 addr
= arg_pointer_rtx
;
4564 addr
= plus_constant (stack_pointer_rtx
, -2 * UNITS_PER_WORD
);
4565 return gen_frame_mem (Pmode
, addr
);