| blob | 9bd1c69e849b21a8506c612d8bd98809d2cc3c7a |
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
29 /* We can't use enum machine_mode inside a generator file because it
30 hasn't been created yet; we shouldn't be using any code that
31 needs the real definition though, so this ought to be safe. */
32 #ifdef GENERATOR_FILE
33 #define MACHMODE int
34 #else
36 #define MACHMODE enum machine_mode
37 #endif
41 /* The architecture define. */
44 /* Target CPU builtins. */
45 #define TARGET_CPU_CPP_BUILTINS() \
46 do \
47 { \
48 /* Define __arm__ even when in thumb mode, for \
52 if (TARGET_THUMB) \
54 if (TARGET_THUMB2) \
56 \
57 if (TARGET_BIG_END) \
58 { \
60 if (TARGET_THUMB) \
62 if (TARGET_LITTLE_WORDS) \
64 } \
65 else \
66 { \
68 if (TARGET_THUMB) \
70 } \
71 \
72 if (TARGET_SOFT_FLOAT) \
74 \
75 if (TARGET_VFP) \
77 \
78 if (TARGET_NEON) \
80 \
81 /* Add a define for interworking. \
83 if (arm_cpp_interwork) \
85 \
88 \
89 builtin_define (arm_arch_name); \
90 if (arm_arch_cirrus) \
92 if (arm_arch_xscale) \
94 if (arm_arch_iwmmxt) \
96 if (TARGET_AAPCS_BASED) \
97 { \
98 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
100 else if (arm_pcs_default == ARM_PCS_AAPCS) \
103 } \
104 } while (0)
106 /* The various ARM cores. */
107 enum processor_type
108 {
109 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
110 IDENT,
112 #undef ARM_CORE
113 /* Used to indicate that no processor has been specified. */
114 arm_none
115 };
117 enum target_cpus
118 {
119 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
120 TARGET_CPU_##IDENT,
122 #undef ARM_CORE
123 TARGET_CPU_generic
124 };
126 /* The processor for which instructions should be scheduled. */
129 enum arm_sync_generator_tag
130 {
131 arm_sync_generator_omn,
132 arm_sync_generator_omrn
133 };
135 /* Wrapper to pass around a polymorphic pointer to a sync instruction
136 generator and. */
137 struct arm_sync_generator
138 {
140 union
141 {
145 };
148 {
151 }
152 arm_cc;
156 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
161 /* The label of the current constant pool. */
163 /* Set to 1 when a return insn is output, this means that the epilogue
164 is not needed. */
166 /* Callback to output language specific object attributes. */
168 \f
169 /* Just in case configure has failed to define anything. */
170 #ifndef TARGET_CPU_DEFAULT
171 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
172 #endif
175 #undef CPP_SPEC
177 %{msoft-float:%{mhard-float: \
178 %e-msoft-float and -mhard_float may not be used together}} \
179 %{mbig-endian:%{mlittle-endian: \
180 %e-mbig-endian and -mlittle-endian may not be used together}}"
182 #ifndef CC1_SPEC
184 #endif
186 /* This macro defines names of additional specifications to put in the specs
187 that can be used in various specifications like CC1_SPEC. Its definition
188 is an initializer with a subgrouping for each command option.
190 Each subgrouping contains a string constant, that defines the
191 specification name, and a string constant that used by the GCC driver
192 program.
194 Do not define this macro if it does not need to do anything. */
195 #define EXTRA_SPECS \
197 SUBTARGET_EXTRA_SPECS
199 #ifndef SUBTARGET_EXTRA_SPECS
200 #define SUBTARGET_EXTRA_SPECS
201 #endif
203 #ifndef SUBTARGET_CPP_SPEC
205 #endif
206 \f
207 /* Run-time Target Specification. */
208 #ifndef TARGET_VERSION
210 #endif
212 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
213 /* Use hardware floating point instructions. */
214 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
215 /* Use hardware floating point calling convention. */
216 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
217 #define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA)
218 #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
219 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
220 #define TARGET_IWMMXT (arm_arch_iwmmxt)
221 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
222 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
223 #define TARGET_ARM (! TARGET_THUMB)
225 #define TARGET_BACKTRACE (leaf_function_p () \
226 ? TARGET_TPCS_LEAF_FRAME \
227 : TARGET_TPCS_FRAME)
228 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
229 #define TARGET_AAPCS_BASED \
230 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
232 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
233 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
235 /* Only 16-bit thumb code. */
236 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
237 /* Arm or Thumb-2 32-bit code. */
238 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
239 /* 32-bit Thumb-2 code. */
240 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
241 /* Thumb-1 only. */
242 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
243 /* FPA emulator without LFM. */
244 #define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
246 /* The following two macros concern the ability to execute coprocessor
247 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
248 only ever tested when we know we are generating for VFP hardware; we need
249 to be more careful with TARGET_NEON as noted below. */
251 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
252 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
254 /* FPU supports VFPv3 instructions. */
255 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
257 /* FPU only supports VFP single-precision instructions. */
258 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
260 /* FPU supports VFP double-precision instructions. */
261 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
263 /* FPU supports half-precision floating-point with NEON element load/store. */
264 #define TARGET_NEON_FP16 \
265 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
267 /* FPU supports VFP half-precision floating-point. */
268 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
270 /* FPU supports Neon instructions. The setting of this macro gets
271 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
272 and TARGET_HARD_FLOAT to ensure that NEON instructions are
273 available. */
274 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
275 && TARGET_VFP && arm_fpu_desc->neon)
277 /* "DSP" multiply instructions, eg. SMULxy. */
278 #define TARGET_DSP_MULTIPLY \
279 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
280 /* Integer SIMD instructions, and extend-accumulate instructions. */
281 #define TARGET_INT_SIMD \
282 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
284 /* Should MOVW/MOVT be used in preference to a constant pool. */
285 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
287 /* We could use unified syntax for arm mode, but for now we just use it
288 for Thumb-2. */
289 #define TARGET_UNIFIED_ASM TARGET_THUMB2
291 /* Nonzero if this chip provides the DMB instruction. */
292 #define TARGET_HAVE_DMB (arm_arch7)
294 /* Nonzero if this chip implements a memory barrier via CP15. */
295 #define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
297 /* Nonzero if this chip implements a memory barrier instruction. */
298 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
300 /* Nonzero if this chip supports ldrex and strex */
301 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
303 /* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */
304 #define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7)
306 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
307 then TARGET_AAPCS_BASED must be true -- but the converse does not
308 hold. TARGET_BPABI implies the use of the BPABI runtime library,
309 etc., in addition to just the AAPCS calling conventions. */
310 #ifndef TARGET_BPABI
311 #define TARGET_BPABI false
312 #endif
314 /* Support for a compile-time default CPU, et cetera. The rules are:
315 --with-arch is ignored if -march or -mcpu are specified.
316 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
317 by --with-arch.
318 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
319 by -march).
320 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
321 specified.
322 --with-fpu is ignored if -mfpu is specified.
323 --with-abi is ignored is -mabi is specified. */
324 #define OPTION_DEFAULT_SPECS \
334 /* Which floating point model to use. */
335 enum arm_fp_model
336 {
337 ARM_FP_MODEL_UNKNOWN,
338 /* FPA model (Hardware or software). */
339 ARM_FP_MODEL_FPA,
340 /* Cirrus Maverick floating point model. */
341 ARM_FP_MODEL_MAVERICK,
342 /* VFP floating point model. */
343 ARM_FP_MODEL_VFP
344 };
346 enum vfp_reg_type
347 {
349 VFP_REG_D16,
350 VFP_REG_D32,
351 VFP_REG_SINGLE
352 };
355 {
364 /* Which floating point hardware to schedule for. */
367 enum float_abi_type
368 {
369 ARM_FLOAT_ABI_SOFT,
370 ARM_FLOAT_ABI_SOFTFP,
371 ARM_FLOAT_ABI_HARD
372 };
376 #ifndef TARGET_DEFAULT_FLOAT_ABI
377 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
378 #endif
380 /* Which __fp16 format to use.
381 The enumeration values correspond to the numbering for the
382 Tag_ABI_FP_16bit_format attribute.
383 */
384 enum arm_fp16_format_type
385 {
389 };
392 #define LARGEST_EXPONENT_IS_NORMAL(bits) \
393 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
395 /* Which ABI to use. */
396 enum arm_abi_type
397 {
398 ARM_ABI_APCS,
399 ARM_ABI_ATPCS,
400 ARM_ABI_AAPCS,
401 ARM_ABI_IWMMXT,
402 ARM_ABI_AAPCS_LINUX
403 };
407 #ifndef ARM_DEFAULT_ABI
408 #define ARM_DEFAULT_ABI ARM_ABI_APCS
409 #endif
411 /* Which thread pointer access sequence to use. */
413 TP_AUTO,
414 TP_SOFT,
415 TP_CP15
416 };
420 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
423 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
426 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
429 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
432 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
435 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
438 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */
441 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */
444 /* Nonzero if instructions not present in the 'M' profile can be used. */
447 /* Nonzero if instructions present in ARMv7E-M can be used. */
450 /* Nonzero if this chip can benefit from load scheduling. */
453 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
456 /* Nonzero if generating Thumb-1 code. */
459 /* Nonzero if this chip is a StrongARM. */
462 /* Nonzero if this chip is a Cirrus variant. */
465 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
468 /* Nonzero if this chip is an XScale. */
471 /* Nonzero if tuning for XScale. */
474 /* Nonzero if tuning for stores via the write buffer. */
477 /* Nonzero if tuning for Cortex-A9. */
480 /* Nonzero if we should define __THUMB_INTERWORK__ in the
481 preprocessor.
482 XXX This is a bit of a hack, it's intended to help work around
483 problems in GLD which doesn't understand that armv5t code is
484 interworking clean. */
487 /* Nonzero if chip supports Thumb 2. */
490 /* Nonzero if chip supports integer division instruction. */
493 #ifndef TARGET_DEFAULT
494 #define TARGET_DEFAULT (MASK_APCS_FRAME)
495 #endif
497 /* The frame pointer register used in gcc has nothing to do with debugging;
498 that is controlled by the APCS-FRAME option. */
499 #define CAN_DEBUG_WITHOUT_FP
501 /* Nonzero if PIC code requires explicit qualifiers to generate
502 PLT and GOT relocs rather than the assembler doing so implicitly.
503 Subtargets can override these if required. */
504 #ifndef NEED_GOT_RELOC
505 #define NEED_GOT_RELOC 0
506 #endif
507 #ifndef NEED_PLT_RELOC
508 #define NEED_PLT_RELOC 0
509 #endif
511 /* Nonzero if we need to refer to the GOT with a PC-relative
512 offset. In other words, generate
514 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
516 rather than
518 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
520 The default is true, which matches NetBSD. Subtargets can
521 override this if required. */
522 #ifndef GOT_PCREL
523 #define GOT_PCREL 1
524 #endif
525 \f
526 /* Target machine storage Layout. */
529 /* Define this macro if it is advisable to hold scalars in registers
530 in a wider mode than that declared by the program. In such cases,
531 the value is constrained to be within the bounds of the declared
532 type, but kept valid in the wider mode. The signedness of the
533 extension may differ from that of the type. */
535 /* It is far faster to zero extend chars than to sign extend them */
537 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
538 if (GET_MODE_CLASS (MODE) == MODE_INT \
539 && GET_MODE_SIZE (MODE) < 4) \
540 { \
541 if (MODE == QImode) \
542 UNSIGNEDP = 1; \
543 else if (MODE == HImode) \
544 UNSIGNEDP = 1; \
545 (MODE) = SImode; \
546 }
548 /* Define this if most significant bit is lowest numbered
549 in instructions that operate on numbered bit-fields. */
550 #define BITS_BIG_ENDIAN 0
552 /* Define this if most significant byte of a word is the lowest numbered.
553 Most ARM processors are run in little endian mode, so that is the default.
554 If you want to have it run-time selectable, change the definition in a
555 cover file to be TARGET_BIG_ENDIAN. */
556 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
558 /* Define this if most significant word of a multiword number is the lowest
559 numbered.
560 This is always false, even when in big-endian mode. */
561 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
563 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
564 on processor pre-defineds when compiling libgcc2.c. */
565 #if defined(__ARMEB__) && !defined(__ARMWEL__)
566 #define LIBGCC2_WORDS_BIG_ENDIAN 1
567 #else
568 #define LIBGCC2_WORDS_BIG_ENDIAN 0
569 #endif
571 /* Define this if most significant word of doubles is the lowest numbered.
572 The rules are different based on whether or not we use FPA-format,
573 VFP-format or some other floating point co-processor's format doubles. */
574 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
576 #define UNITS_PER_WORD 4
578 /* True if natural alignment is used for doubleword types. */
579 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
581 #define DOUBLEWORD_ALIGNMENT 64
583 #define PARM_BOUNDARY 32
585 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
587 #define PREFERRED_STACK_BOUNDARY \
588 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
590 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
592 /* The lowest bit is used to indicate Thumb-mode functions, so the
593 vbit must go into the delta field of pointers to member
594 functions. */
595 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
597 #define EMPTY_FIELD_BOUNDARY 32
599 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
601 /* XXX Blah -- this macro is used directly by libobjc. Since it
602 supports no vector modes, cut out the complexity and fall back
603 on BIGGEST_FIELD_ALIGNMENT. */
604 #ifdef IN_TARGET_LIBS
605 #define BIGGEST_FIELD_ALIGNMENT 64
606 #endif
608 /* Make strings word-aligned so strcpy from constants will be faster. */
609 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
611 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
612 ((TREE_CODE (EXP) == STRING_CST \
613 && !optimize_size \
614 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
615 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
617 /* Align definitions of arrays, unions and structures so that
618 initializations and copies can be made more efficient. This is not
619 ABI-changing, so it only affects places where we can see the
620 definition. */
621 #define DATA_ALIGNMENT(EXP, ALIGN) \
622 ((((ALIGN) < BITS_PER_WORD) \
623 && (TREE_CODE (EXP) == ARRAY_TYPE \
624 || TREE_CODE (EXP) == UNION_TYPE \
625 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
627 /* Similarly, make sure that objects on the stack are sensibly aligned. */
628 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
630 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
631 value set in previous versions of this toolchain was 8, which produces more
632 compact structures. The command line option -mstructure_size_boundary=<n>
633 can be used to change this value. For compatibility with the ARM SDK
634 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
635 0020D) page 2-20 says "Structures are aligned on word boundaries".
636 The AAPCS specifies a value of 8. */
637 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
640 /* This is the value used to initialize arm_structure_size_boundary. If a
641 particular arm target wants to change the default value it should change
642 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
643 for an example of this. */
644 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
645 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
646 #endif
648 /* Nonzero if move instructions will actually fail to work
649 when given unaligned data. */
650 #define STRICT_ALIGNMENT 1
652 /* wchar_t is unsigned under the AAPCS. */
653 #ifndef WCHAR_TYPE
656 #define WCHAR_TYPE_SIZE BITS_PER_WORD
657 #endif
659 #ifndef SIZE_TYPE
661 #endif
663 #ifndef PTRDIFF_TYPE
665 #endif
667 /* AAPCS requires that structure alignment is affected by bitfields. */
668 #ifndef PCC_BITFIELD_TYPE_MATTERS
669 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
670 #endif
672 \f
673 /* Standard register usage. */
675 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
676 (S - saved over call).
678 r0 * argument word/integer result
679 r1-r3 argument word
681 r4-r8 S register variable
682 r9 S (rfp) register variable (real frame pointer)
684 r10 F S (sl) stack limit (used by -mapcs-stack-check)
685 r11 F S (fp) argument pointer
686 r12 (ip) temp workspace
687 r13 F S (sp) lower end of current stack frame
688 r14 (lr) link address/workspace
689 r15 F (pc) program counter
691 f0 floating point result
692 f1-f3 floating point scratch
694 f4-f7 S floating point variable
696 cc This is NOT a real register, but is used internally
697 to represent things that use or set the condition
698 codes.
699 sfp This isn't either. It is used during rtl generation
700 since the offset between the frame pointer and the
701 auto's isn't known until after register allocation.
702 afp Nor this, we only need this because of non-local
703 goto. Without it fp appears to be used and the
704 elimination code won't get rid of sfp. It tracks
705 fp exactly at all times.
707 *: See CONDITIONAL_REGISTER_USAGE */
709 /*
710 mvf0 Cirrus floating point result
711 mvf1-mvf3 Cirrus floating point scratch
712 mvf4-mvf15 S Cirrus floating point variable. */
714 /* s0-s15 VFP scratch (aka d0-d7).
715 s16-s31 S VFP variable (aka d8-d15).
716 vfpcc Not a real register. Represents the VFP condition
717 code flags. */
719 /* The stack backtrace structure is as follows:
720 fp points to here: | save code pointer | [fp]
721 | return link value | [fp, #-4]
722 | return sp value | [fp, #-8]
723 | return fp value | [fp, #-12]
724 [| saved r10 value |]
725 [| saved r9 value |]
726 [| saved r8 value |]
727 [| saved r7 value |]
728 [| saved r6 value |]
729 [| saved r5 value |]
730 [| saved r4 value |]
731 [| saved r3 value |]
732 [| saved r2 value |]
733 [| saved r1 value |]
734 [| saved r0 value |]
735 [| saved f7 value |] three words
736 [| saved f6 value |] three words
737 [| saved f5 value |] three words
738 [| saved f4 value |] three words
739 r0-r3 are not normally saved in a C function. */
741 /* 1 for registers that have pervasive standard uses
742 and are not available for the register allocator. */
743 #define FIXED_REGISTERS \
744 { \
745 0,0,0,0,0,0,0,0, \
746 0,0,0,0,0,1,0,1, \
747 0,0,0,0,0,0,0,0, \
748 1,1,1, \
749 1,1,1,1,1,1,1,1, \
750 1,1,1,1,1,1,1,1, \
751 1,1,1,1,1,1,1,1, \
752 1,1,1,1,1,1,1,1, \
753 1,1,1,1, \
754 1,1,1,1,1,1,1,1, \
755 1,1,1,1,1,1,1,1, \
756 1,1,1,1,1,1,1,1, \
757 1,1,1,1,1,1,1,1, \
758 1,1,1,1,1,1,1,1, \
759 1,1,1,1,1,1,1,1, \
760 1,1,1,1,1,1,1,1, \
761 1,1,1,1,1,1,1,1, \
762 1 \
763 }
765 /* 1 for registers not available across function calls.
766 These must include the FIXED_REGISTERS and also any
767 registers that can be used without being saved.
768 The latter must include the registers where values are returned
769 and the register where structure-value addresses are passed.
770 Aside from that, you can include as many other registers as you like.
771 The CC is not preserved over function calls on the ARM 6, so it is
772 easier to assume this for all. SFP is preserved, since FP is. */
773 #define CALL_USED_REGISTERS \
774 { \
775 1,1,1,1,0,0,0,0, \
776 0,0,0,0,1,1,1,1, \
777 1,1,1,1,0,0,0,0, \
778 1,1,1, \
779 1,1,1,1,1,1,1,1, \
780 1,1,1,1,1,1,1,1, \
781 1,1,1,1,1,1,1,1, \
782 1,1,1,1,1,1,1,1, \
783 1,1,1,1, \
784 1,1,1,1,1,1,1,1, \
785 1,1,1,1,1,1,1,1, \
786 1,1,1,1,1,1,1,1, \
787 1,1,1,1,1,1,1,1, \
788 1,1,1,1,1,1,1,1, \
789 1,1,1,1,1,1,1,1, \
790 1,1,1,1,1,1,1,1, \
791 1,1,1,1,1,1,1,1, \
792 1 \
793 }
795 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
796 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
797 #endif
799 #define CONDITIONAL_REGISTER_USAGE \
800 { \
801 int regno; \
802 \
803 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
804 { \
805 for (regno = FIRST_FPA_REGNUM; \
806 regno <= LAST_FPA_REGNUM; ++regno) \
807 fixed_regs[regno] = call_used_regs[regno] = 1; \
808 } \
809 \
810 if (TARGET_THUMB1 && optimize_size) \
811 { \
812 /* When optimizing for size on Thumb-1, it's better not \
813 to use the HI regs, because of the overhead of \
815 for (regno = FIRST_HI_REGNUM; \
816 regno <= LAST_HI_REGNUM; ++regno) \
817 fixed_regs[regno] = call_used_regs[regno] = 1; \
818 } \
819 \
820 /* The link register can be clobbered by any branch insn, \
821 but we have no way to track that at present, so mark \
823 if (TARGET_THUMB1) \
824 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
825 \
826 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
827 { \
828 if (TARGET_MAVERICK) \
829 { \
830 for (regno = FIRST_FPA_REGNUM; \
831 regno <= LAST_FPA_REGNUM; ++ regno) \
832 fixed_regs[regno] = call_used_regs[regno] = 1; \
833 for (regno = FIRST_CIRRUS_FP_REGNUM; \
834 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
835 { \
836 fixed_regs[regno] = 0; \
837 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
838 } \
839 } \
840 if (TARGET_VFP) \
841 { \
842 /* VFPv3 registers are disabled when earlier VFP \
843 versions are selected due to the definition of \
845 for (regno = FIRST_VFP_REGNUM; \
846 regno <= LAST_VFP_REGNUM; ++ regno) \
847 { \
848 fixed_regs[regno] = 0; \
849 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
850 || regno >= FIRST_VFP_REGNUM + 32; \
851 } \
852 } \
853 } \
854 \
855 if (TARGET_REALLY_IWMMXT) \
856 { \
857 regno = FIRST_IWMMXT_GR_REGNUM; \
858 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
859 and wCG1 as call-preserved registers. The 2002/11/21 \
860 revision changed this so that all wCG registers are \
862 for (regno = FIRST_IWMMXT_GR_REGNUM; \
863 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
864 fixed_regs[regno] = 0; \
865 /* The XScale ABI has wR0 - wR9 as scratch registers, \
867 for (regno = FIRST_IWMMXT_REGNUM; \
868 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
869 { \
870 fixed_regs[regno] = 0; \
871 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
872 } \
873 } \
874 \
875 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
876 { \
877 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
878 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
879 } \
880 else if (TARGET_APCS_STACK) \
881 { \
882 fixed_regs[10] = 1; \
883 call_used_regs[10] = 1; \
884 } \
885 /* -mcaller-super-interworking reserves r11 for calls to \
886 _interwork_r11_call_via_rN(). Making the register global \
887 is an easy way of ensuring that it remains valid for all \
889 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
890 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
891 { \
892 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
893 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
894 if (TARGET_CALLER_INTERWORKING) \
895 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
896 } \
897 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
898 }
900 /* These are a couple of extensions to the formats accepted
901 by asm_fprintf:
902 %@ prints out ASM_COMMENT_START
903 %r prints out REGISTER_PREFIX reg_names[arg] */
904 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
906 fputs (ASM_COMMENT_START, FILE); \
907 break; \
908 \
910 fputs (REGISTER_PREFIX, FILE); \
911 fputs (reg_names [va_arg (ARGS, int)], FILE); \
912 break;
914 /* Round X up to the nearest word. */
915 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
917 /* Convert fron bytes to ints. */
918 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
920 /* The number of (integer) registers required to hold a quantity of type MODE.
921 Also used for VFP registers. */
922 #define ARM_NUM_REGS(MODE) \
923 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
925 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
926 #define ARM_NUM_REGS2(MODE, TYPE) \
927 ARM_NUM_INTS ((MODE) == BLKmode ? \
928 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
930 /* The number of (integer) argument register available. */
931 #define NUM_ARG_REGS 4
933 /* And similarly for the VFP. */
934 #define NUM_VFP_ARG_REGS 16
936 /* Return the register number of the N'th (integer) argument. */
937 #define ARG_REGISTER(N) (N - 1)
939 /* Specify the registers used for certain standard purposes.
940 The values of these macros are register numbers. */
942 /* The number of the last argument register. */
943 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
945 /* The numbers of the Thumb register ranges. */
946 #define FIRST_LO_REGNUM 0
947 #define LAST_LO_REGNUM 7
948 #define FIRST_HI_REGNUM 8
949 #define LAST_HI_REGNUM 11
951 #ifndef TARGET_UNWIND_INFO
952 /* We use sjlj exceptions for backwards compatibility. */
953 #define MUST_USE_SJLJ_EXCEPTIONS 1
954 #endif
956 /* We can generate DWARF2 Unwind info, even though we don't use it. */
957 #define DWARF2_UNWIND_INFO 1
959 /* Use r0 and r1 to pass exception handling information. */
960 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
962 /* The register that holds the return address in exception handlers. */
963 #define ARM_EH_STACKADJ_REGNUM 2
964 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
966 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
967 as an invisible last argument (possible since varargs don't exist in
968 Pascal), so the following is not true. */
969 #define STATIC_CHAIN_REGNUM 12
971 /* Define this to be where the real frame pointer is if it is not possible to
972 work out the offset between the frame pointer and the automatic variables
973 until after register allocation has taken place. FRAME_POINTER_REGNUM
974 should point to a special register that we will make sure is eliminated.
976 For the Thumb we have another problem. The TPCS defines the frame pointer
977 as r11, and GCC believes that it is always possible to use the frame pointer
978 as base register for addressing purposes. (See comments in
979 find_reloads_address()). But - the Thumb does not allow high registers,
980 including r11, to be used as base address registers. Hence our problem.
982 The solution used here, and in the old thumb port is to use r7 instead of
983 r11 as the hard frame pointer and to have special code to generate
984 backtrace structures on the stack (if required to do so via a command line
985 option) using r11. This is the only 'user visible' use of r11 as a frame
986 pointer. */
987 #define ARM_HARD_FRAME_POINTER_REGNUM 11
988 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
990 #define HARD_FRAME_POINTER_REGNUM \
991 (TARGET_ARM \
992 ? ARM_HARD_FRAME_POINTER_REGNUM \
993 : THUMB_HARD_FRAME_POINTER_REGNUM)
995 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
997 /* Register to use for pushing function arguments. */
998 #define STACK_POINTER_REGNUM SP_REGNUM
1000 /* ARM floating pointer registers. */
1001 #define FIRST_FPA_REGNUM 16
1002 #define LAST_FPA_REGNUM 23
1003 #define IS_FPA_REGNUM(REGNUM) \
1004 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
1006 #define FIRST_IWMMXT_GR_REGNUM 43
1007 #define LAST_IWMMXT_GR_REGNUM 46
1008 #define FIRST_IWMMXT_REGNUM 47
1009 #define LAST_IWMMXT_REGNUM 62
1010 #define IS_IWMMXT_REGNUM(REGNUM) \
1011 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1012 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1013 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1015 /* Base register for access to local variables of the function. */
1016 #define FRAME_POINTER_REGNUM 25
1018 /* Base register for access to arguments of the function. */
1019 #define ARG_POINTER_REGNUM 26
1021 #define FIRST_CIRRUS_FP_REGNUM 27
1022 #define LAST_CIRRUS_FP_REGNUM 42
1023 #define IS_CIRRUS_REGNUM(REGNUM) \
1024 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1026 #define FIRST_VFP_REGNUM 63
1028 #define LAST_VFP_REGNUM \
1029 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
1031 #define IS_VFP_REGNUM(REGNUM) \
1032 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1034 /* VFP registers are split into two types: those defined by VFP versions < 3
1035 have D registers overlaid on consecutive pairs of S registers. VFP version 3
1036 defines 16 new D registers (d16-d31) which, for simplicity and correctness
1037 in various parts of the backend, we implement as "fake" single-precision
1038 registers (which would be S32-S63, but cannot be used in that way). The
1039 following macros define these ranges of registers. */
1040 #define LAST_LO_VFP_REGNUM 94
1041 #define FIRST_HI_VFP_REGNUM 95
1042 #define LAST_HI_VFP_REGNUM 126
1044 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
1045 ((REGNUM) <= LAST_LO_VFP_REGNUM)
1047 /* DFmode values are only valid in even register pairs. */
1048 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1049 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1051 /* Neon Quad values must start at a multiple of four registers. */
1052 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1053 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1055 /* Neon structures of vectors must be in even register pairs and there
1056 must be enough registers available. Because of various patterns
1057 requiring quad registers, we require them to start at a multiple of
1058 four. */
1059 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1060 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1061 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1063 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1064 /* + 16 Cirrus registers take us up to 43. */
1065 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1066 /* VFP (VFP3) adds 32 (64) + 1 more. */
1067 #define FIRST_PSEUDO_REGISTER 128
1069 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1071 /* Value should be nonzero if functions must have frame pointers.
1072 Zero means the frame pointer need not be set up (and parms may be accessed
1073 via the stack pointer) in functions that seem suitable.
1074 If we have to have a frame pointer we might as well make use of it.
1075 APCS says that the frame pointer does not need to be pushed in leaf
1076 functions, or simple tail call functions. */
1078 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1079 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1080 #endif
1082 /* Return number of consecutive hard regs needed starting at reg REGNO
1083 to hold something of mode MODE.
1084 This is ordinarily the length in words of a value of mode MODE
1085 but can be less for certain modes in special long registers.
1087 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1088 mode. */
1089 #define HARD_REGNO_NREGS(REGNO, MODE) \
1090 ((TARGET_32BIT \
1091 && REGNO >= FIRST_FPA_REGNUM \
1092 && REGNO != FRAME_POINTER_REGNUM \
1093 && REGNO != ARG_POINTER_REGNUM) \
1094 && !IS_VFP_REGNUM (REGNO) \
1095 ? 1 : ARM_NUM_REGS (MODE))
1097 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1098 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1099 arm_hard_regno_mode_ok ((REGNO), (MODE))
1101 /* Value is 1 if it is a good idea to tie two pseudo registers
1102 when one has mode MODE1 and one has mode MODE2.
1103 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1104 for any hard reg, then this must be 0 for correct output. */
1105 #define MODES_TIEABLE_P(MODE1, MODE2) \
1106 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1108 #define VALID_IWMMXT_REG_MODE(MODE) \
1109 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1111 /* Modes valid for Neon D registers. */
1112 #define VALID_NEON_DREG_MODE(MODE) \
1113 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1114 || (MODE) == V2SFmode || (MODE) == DImode)
1116 /* Modes valid for Neon Q registers. */
1117 #define VALID_NEON_QREG_MODE(MODE) \
1118 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1119 || (MODE) == V4SFmode || (MODE) == V2DImode)
1121 /* Structure modes valid for Neon registers. */
1122 #define VALID_NEON_STRUCT_MODE(MODE) \
1123 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1124 || (MODE) == CImode || (MODE) == XImode)
1126 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1129 /* The order in which register should be allocated. It is good to use ip
1130 since no saving is required (though calls clobber it) and it never contains
1131 function parameters. It is quite good to use lr since other calls may
1132 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1133 least likely to contain a function parameter; in addition results are
1134 returned in r0.
1135 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1136 then D8-D15. The reason for doing this is to attempt to reduce register
1137 pressure when both single- and double-precision registers are used in a
1138 function. */
1140 #define REG_ALLOC_ORDER \
1141 { \
1142 3, 2, 1, 0, 12, 14, 4, 5, \
1143 6, 7, 8, 10, 9, 11, 13, 15, \
1144 16, 17, 18, 19, 20, 21, 22, 23, \
1145 27, 28, 29, 30, 31, 32, 33, 34, \
1146 35, 36, 37, 38, 39, 40, 41, 42, \
1147 43, 44, 45, 46, 47, 48, 49, 50, \
1148 51, 52, 53, 54, 55, 56, 57, 58, \
1149 59, 60, 61, 62, \
1150 24, 25, 26, \
1151 95, 96, 97, 98, 99, 100, 101, 102, \
1152 103, 104, 105, 106, 107, 108, 109, 110, \
1153 111, 112, 113, 114, 115, 116, 117, 118, \
1154 119, 120, 121, 122, 123, 124, 125, 126, \
1155 78, 77, 76, 75, 74, 73, 72, 71, \
1156 70, 69, 68, 67, 66, 65, 64, 63, \
1157 79, 80, 81, 82, 83, 84, 85, 86, \
1158 87, 88, 89, 90, 91, 92, 93, 94, \
1159 127 \
1160 }
1162 /* Use different register alloc ordering for Thumb. */
1163 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1165 /* Tell IRA to use the order we define rather than messing it up with its
1166 own cost calculations. */
1167 #define HONOR_REG_ALLOC_ORDER
1169 /* Interrupt functions can only use registers that have already been
1170 saved by the prologue, even if they would normally be
1171 call-clobbered. */
1172 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1173 (! IS_INTERRUPT (cfun->machine->func_type) || \
1174 df_regs_ever_live_p (DST))
1175 \f
1176 /* Register and constant classes. */
1178 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1179 Now that the Thumb is involved it has become more complicated. */
1180 enum reg_class
1181 {
1182 NO_REGS,
1183 FPA_REGS,
1184 CIRRUS_REGS,
1185 VFP_D0_D7_REGS,
1186 VFP_LO_REGS,
1187 VFP_HI_REGS,
1188 VFP_REGS,
1189 IWMMXT_GR_REGS,
1190 IWMMXT_REGS,
1191 LO_REGS,
1192 STACK_REG,
1193 BASE_REGS,
1194 HI_REGS,
1195 CC_REG,
1196 VFPCC_REG,
1197 GENERAL_REGS,
1198 CORE_REGS,
1199 ALL_REGS,
1200 LIM_REG_CLASSES
1201 };
1203 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1205 /* Give names of register classes as strings for dump file. */
1206 #define REG_CLASS_NAMES \
1207 { \
1226 }
1228 /* Define which registers fit in which classes.
1229 This is an initializer for a vector of HARD_REG_SET
1230 of length N_REG_CLASSES. */
1231 #define REG_CLASS_CONTENTS \
1232 { \
1251 }
1253 /* Any of the VFP register classes. */
1254 #define IS_VFP_CLASS(X) \
1255 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1256 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1258 /* The same information, inverted:
1259 Return the class number of the smallest class containing
1260 reg number REGNO. This could be a conditional expression
1261 or could index an array. */
1262 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1264 /* The following macro defines cover classes for Integrated Register
1265 Allocator. Cover classes is a set of non-intersected register
1266 classes covering all hard registers used for register allocation
1267 purpose. Any move between two registers of a cover class should be
1268 cheaper than load or store of the registers. The macro value is
1269 array of register classes with LIM_REG_CLASSES used as the end
1270 marker. */
1272 #define IRA_COVER_CLASSES \
1273 { \
1274 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1275 LIM_REG_CLASSES \
1276 }
1278 /* FPA registers can't do subreg as all values are reformatted to internal
1279 precision. VFP registers may only be accessed in the mode they
1280 were set. */
1281 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1282 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1283 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1284 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1285 : 0)
1287 /* The class value for index registers, and the one for base regs. */
1288 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1289 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1291 /* For the Thumb the high registers cannot be used as base registers
1292 when addressing quantities in QI or HI mode; if we don't know the
1293 mode, then we must be conservative. */
1294 #define MODE_BASE_REG_CLASS(MODE) \
1295 (TARGET_32BIT ? CORE_REGS : \
1296 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1298 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1299 instead of BASE_REGS. */
1300 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1302 /* When this hook returns true for MODE, the compiler allows
1303 registers explicitly used in the rtl to be used as spill registers
1304 but prevents the compiler from extending the lifetime of these
1305 registers. */
1306 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1307 arm_small_register_classes_for_mode_p
1309 /* Given an rtx X being reloaded into a reg required to be
1310 in class CLASS, return the class of reg to actually use.
1311 In general this is just CLASS, but for the Thumb core registers and
1312 immediate constants we prefer a LO_REGS class or a subset. */
1313 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1314 (TARGET_32BIT ? (CLASS) : \
1315 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1316 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1317 ? LO_REGS : (CLASS)))
1319 /* Must leave BASE_REGS reloads alone */
1320 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1321 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1322 ? ((true_regnum (X) == -1 ? LO_REGS \
1323 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1324 : NO_REGS)) \
1325 : NO_REGS)
1327 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1328 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1329 ? ((true_regnum (X) == -1 ? LO_REGS \
1330 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1331 : NO_REGS)) \
1332 : NO_REGS)
1334 /* Return the register class of a scratch register needed to copy IN into
1335 or out of a register in CLASS in MODE. If it can be done directly,
1336 NO_REGS is returned. */
1337 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1339 ((TARGET_VFP && TARGET_HARD_FLOAT \
1340 && IS_VFP_CLASS (CLASS)) \
1341 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1342 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1343 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1344 : TARGET_32BIT \
1345 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1346 ? GENERAL_REGS : NO_REGS) \
1347 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1349 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1350 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1352 ((TARGET_VFP && TARGET_HARD_FLOAT \
1353 && IS_VFP_CLASS (CLASS)) \
1354 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1355 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1356 coproc_secondary_reload_class (MODE, X, TRUE) : \
1358 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1359 && (CLASS) == CIRRUS_REGS \
1360 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1361 ? GENERAL_REGS : \
1362 (TARGET_32BIT ? \
1363 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1364 && CONSTANT_P (X)) \
1365 ? GENERAL_REGS : \
1366 (((MODE) == HImode && ! arm_arch4 \
1367 && (GET_CODE (X) == MEM \
1368 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1369 && true_regnum (X) == -1))) \
1370 ? GENERAL_REGS : NO_REGS) \
1371 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1373 /* Try a machine-dependent way of reloading an illegitimate address
1374 operand. If we find one, push the reload and jump to WIN. This
1375 macro is used in only one place: `find_reloads_address' in reload.c.
1377 For the ARM, we wish to handle large displacements off a base
1378 register by splitting the addend across a MOV and the mem insn.
1379 This can cut the number of reloads needed. */
1380 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1381 do \
1382 { \
1383 if (GET_CODE (X) == PLUS \
1384 && GET_CODE (XEXP (X, 0)) == REG \
1385 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1386 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1387 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1388 { \
1389 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1390 HOST_WIDE_INT low, high; \
1391 \
1392 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1393 low = ((val & 0xf) ^ 0x8) - 0x8; \
1394 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1396 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1397 else if (MODE == SImode \
1398 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1399 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1401 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1402 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1404 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1405 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1406 && TARGET_HARD_FLOAT && TARGET_FPA) \
1408 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1409 else \
1410 break; \
1411 \
1412 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1413 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1414 - (unsigned HOST_WIDE_INT) 0x80000000); \
1416 if (low == 0 || high == 0 || (high + low != val)) \
1417 break; \
1418 \
1419 /* Reload the high part into a base reg; leave the low part \
1421 X = gen_rtx_PLUS (GET_MODE (X), \
1422 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1423 GEN_INT (high)), \
1424 GEN_INT (low)); \
1425 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1426 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1427 VOIDmode, 0, 0, OPNUM, TYPE); \
1428 goto WIN; \
1429 } \
1430 } \
1431 while (0)
1433 /* XXX If an HImode FP+large_offset address is converted to an HImode
1434 SP+large_offset address, then reload won't know how to fix it. It sees
1435 only that SP isn't valid for HImode, and so reloads the SP into an index
1436 register, but the resulting address is still invalid because the offset
1437 is too big. We fix it here instead by reloading the entire address. */
1438 /* We could probably achieve better results by defining PROMOTE_MODE to help
1439 cope with the variances between the Thumb's signed and unsigned byte and
1440 halfword load instructions. */
1441 /* ??? This should be safe for thumb2, but we may be able to do better. */
1442 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1443 do { \
1444 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1445 if (new_x) \
1446 { \
1447 X = new_x; \
1448 goto WIN; \
1449 } \
1450 } while (0)
1452 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1453 if (TARGET_ARM) \
1454 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1455 else \
1456 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1458 /* Return the maximum number of consecutive registers
1459 needed to represent mode MODE in a register of class CLASS.
1460 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1461 #define CLASS_MAX_NREGS(CLASS, MODE) \
1462 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1464 /* If defined, gives a class of registers that cannot be used as the
1465 operand of a SUBREG that changes the mode of the object illegally. */
1467 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns.
1468 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
1469 it is typically more expensive than a single memory access. We set
1470 the cost to less than two memory accesses so that floating
1471 point to integer conversion does not go through memory. */
1472 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1473 (TARGET_32BIT ? \
1474 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1475 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1476 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \
1477 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \
1478 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1479 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1480 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1481 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1482 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1483 2) \
1484 : \
1485 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1486 \f
1487 /* Stack layout; function entry, exit and calling. */
1489 /* Define this if pushing a word on the stack
1490 makes the stack pointer a smaller address. */
1491 #define STACK_GROWS_DOWNWARD 1
1493 /* Define this to nonzero if the nominal address of the stack frame
1494 is at the high-address end of the local variables;
1495 that is, each additional local variable allocated
1496 goes at a more negative offset in the frame. */
1497 #define FRAME_GROWS_DOWNWARD 1
1499 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1500 When present, it is one word in size, and sits at the top of the frame,
1501 between the soft frame pointer and either r7 or r11.
1503 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1504 and only then if some outgoing arguments are passed on the stack. It would
1505 be tempting to also check whether the stack arguments are passed by indirect
1506 calls, but there seems to be no reason in principle why a post-reload pass
1507 couldn't convert a direct call into an indirect one. */
1508 #define CALLER_INTERWORKING_SLOT_SIZE \
1509 (TARGET_CALLER_INTERWORKING \
1510 && crtl->outgoing_args_size != 0 \
1511 ? UNITS_PER_WORD : 0)
1513 /* Offset within stack frame to start allocating local variables at.
1514 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1515 first local allocated. Otherwise, it is the offset to the BEGINNING
1516 of the first local allocated. */
1517 #define STARTING_FRAME_OFFSET 0
1519 /* If we generate an insn to push BYTES bytes,
1520 this says how many the stack pointer really advances by. */
1521 /* The push insns do not do this rounding implicitly.
1522 So don't define this. */
1523 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1525 /* Define this if the maximum size of all the outgoing args is to be
1526 accumulated and pushed during the prologue. The amount can be
1527 found in the variable crtl->outgoing_args_size. */
1528 #define ACCUMULATE_OUTGOING_ARGS 1
1530 /* Offset of first parameter from the argument pointer register value. */
1531 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1533 /* Define how to find the value returned by a library function
1534 assuming the value has mode MODE. */
1535 #define LIBCALL_VALUE(MODE) \
1536 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \
1537 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1538 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1539 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1540 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1541 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1542 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1543 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1544 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1545 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1547 /* 1 if REGNO is a possible register number for a function value. */
1548 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1549 ((REGNO) == ARG_REGISTER (1) \
1550 || (TARGET_AAPCS_BASED && TARGET_32BIT \
1551 && TARGET_VFP && TARGET_HARD_FLOAT \
1552 && (REGNO) == FIRST_VFP_REGNUM) \
1553 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1554 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1555 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1556 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1557 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1559 /* Amount of memory needed for an untyped call to save all possible return
1560 registers. */
1561 #define APPLY_RESULT_SIZE arm_apply_result_size()
1563 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1564 values must be in memory. On the ARM, they need only do so if larger
1565 than a word, or if they contain elements offset from zero in the struct. */
1566 #define DEFAULT_PCC_STRUCT_RETURN 0
1568 /* These bits describe the different types of function supported
1569 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1570 normal function and an interworked function, for example. Knowing the
1571 type of a function is important for determining its prologue and
1572 epilogue sequences.
1573 Note value 7 is currently unassigned. Also note that the interrupt
1574 function types all have bit 2 set, so that they can be tested for easily.
1575 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1576 machine_function structure is initialized (to zero) func_type will
1577 default to unknown. This will force the first use of arm_current_func_type
1578 to call arm_compute_func_type. */
1586 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1588 /* In addition functions can have several type modifiers,
1589 outlined by these bit masks: */
1596 /* Some macros to test these flags. */
1597 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1598 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1599 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1600 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1601 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1602 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1605 /* Structure used to hold the function stack frame layout. Offsets are
1606 relative to the stack pointer on function entry. Positive offsets are
1607 in the direction of stack growth.
1608 Only soft_frame is used in thumb mode. */
1611 {
1619 }
1620 arm_stack_offsets;
1622 #ifndef GENERATOR_FILE
1623 /* A C structure for machine-specific, per-function data.
1624 This is added to the cfun structure. */
1626 {
1627 /* Additional stack adjustment in __builtin_eh_throw. */
1628 rtx eh_epilogue_sp_ofs;
1629 /* Records if LR has to be saved for far jumps. */
1631 /* Records if ARG_POINTER was ever live. */
1633 /* Records if the save of LR has been eliminated. */
1635 /* The size of the stack frame. Only valid after reload. */
1636 arm_stack_offsets stack_offsets;
1637 /* Records the type of the current function. */
1639 /* Record if the function has a variable argument list. */
1641 /* Records if sibcalls are blocked because an argument
1642 register is needed to preserve stack alignment. */
1644 /* The PIC register for this function. This might be a pseudo. */
1645 rtx pic_reg;
1646 /* Labels for per-function Thumb call-via stubs. One per potential calling
1647 register. We can never call via LR or PC. We can call via SP if a
1648 trampoline happens to be on the top of the stack. */
1650 /* Set to 1 when a return insn is output, this means that the epilogue
1651 is not needed. */
1653 /* When outputting Thumb-1 code, record the last insn that provides
1654 information about condition codes, and the comparison operands. */
1655 rtx thumb1_cc_insn;
1656 rtx thumb1_cc_op0;
1657 rtx thumb1_cc_op1;
1658 /* Also record the CC mode that is supported. */
1660 }
1661 machine_function;
1662 #endif
1664 /* As in the machine_function, a global set of call-via labels, for code
1665 that is in text_section. */
1668 /* The number of potential ways of assigning to a co-processor. */
1669 #define ARM_NUM_COPROC_SLOTS 1
1671 /* Enumeration of procedure calling standard variants. We don't really
1672 support all of these yet. */
1673 enum arm_pcs
1674 {
1678 /* This must be the last AAPCS variant. */
1682 ARM_PCS_UNKNOWN
1683 };
1685 /* Default procedure calling standard of current compilation unit. */
1688 /* A C type for declaring a variable that is used as the first argument of
1689 `FUNCTION_ARG' and other related values. */
1691 {
1692 /* This is the number of registers of arguments scanned so far. */
1694 /* This is the number of iWMMXt register arguments scanned so far. */
1698 /* Which procedure call variant to use for this call. */
1701 /* AAPCS related state tracking. */
1704 this argument, or -1 if using core
1705 registers. */
1710 split between core regs and stack.
1711 Zero otherwise. */
1714 and the stack. */
1715 /* Private data for tracking VFP register allocation */
1719 MACHMODE aapcs_vfp_rmode;
1722 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1723 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1725 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1726 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1728 /* For AAPCS, padding should never be below the argument. For other ABIs,
1729 * mimic the default. */
1730 #define PAD_VARARGS_DOWN \
1731 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1733 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1734 for a call to a function whose data type is FNTYPE.
1735 For a library call, FNTYPE is 0.
1736 On the ARM, the offset starts at 0. */
1737 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1738 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1740 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1741 argument with the specified mode and type. If it is not defined,
1742 `PARM_BOUNDARY' is used for all arguments. */
1743 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1744 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1745 ? DOUBLEWORD_ALIGNMENT \
1746 : PARM_BOUNDARY )
1748 /* 1 if N is a possible register number for function argument passing.
1749 On the ARM, r0-r3 are used to pass args. */
1750 #define FUNCTION_ARG_REGNO_P(REGNO) \
1751 (IN_RANGE ((REGNO), 0, 3) \
1752 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1753 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1754 || (TARGET_IWMMXT_ABI \
1755 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1757 \f
1758 /* If your target environment doesn't prefix user functions with an
1759 underscore, you may wish to re-define this to prevent any conflicts. */
1760 #ifndef ARM_MCOUNT_NAME
1762 #endif
1764 /* Call the function profiler with a given profile label. The Acorn
1765 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1766 On the ARM the full profile code will look like:
1767 .data
1768 LP1
1769 .word 0
1770 .text
1771 mov ip, lr
1772 bl mcount
1773 .word LP1
1775 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1776 will output the .text section.
1778 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1779 ``prof'' doesn't seem to mind about this!
1781 Note - this version of the code is designed to work in both ARM and
1782 Thumb modes. */
1783 #ifndef ARM_FUNCTION_PROFILER
1784 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1785 { \
1786 char temp[20]; \
1787 rtx sym; \
1788 \
1790 IP_REGNUM, LR_REGNUM); \
1791 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1794 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1795 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1796 }
1797 #endif
1799 #ifdef THUMB_FUNCTION_PROFILER
1800 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1801 if (TARGET_ARM) \
1802 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1803 else \
1804 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1805 #else
1806 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1807 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1808 #endif
1810 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1811 the stack pointer does not matter. The value is tested only in
1812 functions that have frame pointers.
1813 No definition is equivalent to always zero.
1815 On the ARM, the function epilogue recovers the stack pointer from the
1816 frame. */
1817 #define EXIT_IGNORE_STACK 1
1819 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1821 /* Determine if the epilogue should be output as RTL.
1822 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1823 #define USE_RETURN_INSN(ISCOND) \
1824 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1826 /* Definitions for register eliminations.
1828 This is an array of structures. Each structure initializes one pair
1829 of eliminable registers. The "from" register number is given first,
1830 followed by "to". Eliminations of the same "from" register are listed
1831 in order of preference.
1833 We have two registers that can be eliminated on the ARM. First, the
1834 arg pointer register can often be eliminated in favor of the stack
1835 pointer register. Secondly, the pseudo frame pointer register can always
1836 be eliminated; it is replaced with either the stack or the real frame
1837 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1838 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1840 #define ELIMINABLE_REGS \
1841 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1842 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1843 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1844 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1845 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1846 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1847 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1849 /* Define the offset between two registers, one to be eliminated, and the
1850 other its replacement, at the start of a routine. */
1851 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1852 if (TARGET_ARM) \
1853 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1854 else \
1855 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1857 /* Special case handling of the location of arguments passed on the stack. */
1858 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1860 /* Initialize data used by insn expanders. This is called from insn_emit,
1861 once for every function before code is generated. */
1862 #define INIT_EXPANDERS arm_init_expanders ()
1864 /* Length in units of the trampoline for entering a nested function. */
1865 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1867 /* Alignment required for a trampoline in bits. */
1868 #define TRAMPOLINE_ALIGNMENT 32
1869 \f
1870 /* Addressing modes, and classification of registers for them. */
1871 #define HAVE_POST_INCREMENT 1
1872 #define HAVE_PRE_INCREMENT TARGET_32BIT
1873 #define HAVE_POST_DECREMENT TARGET_32BIT
1874 #define HAVE_PRE_DECREMENT TARGET_32BIT
1875 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1876 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1877 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1878 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1880 /* Macros to check register numbers against specific register classes. */
1882 /* These assume that REGNO is a hard or pseudo reg number.
1883 They give nonzero only if REGNO is a hard reg of the suitable class
1884 or a pseudo reg currently allocated to a suitable hard reg.
1885 Since they use reg_renumber, they are safe only once reg_renumber
1886 has been allocated, which happens in local-alloc.c. */
1887 #define TEST_REGNO(R, TEST, VALUE) \
1888 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1890 /* Don't allow the pc to be used. */
1891 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1892 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1893 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1894 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1896 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1897 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1898 || (GET_MODE_SIZE (MODE) >= 4 \
1899 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1901 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1902 (TARGET_THUMB1 \
1903 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1904 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1906 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1907 For Thumb, we can not use SP + reg, so reject SP. */
1908 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1909 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1911 /* For ARM code, we don't care about the mode, but for Thumb, the index
1912 must be suitable for use in a QImode load. */
1913 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1914 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1915 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1917 /* Maximum number of registers that can appear in a valid memory address.
1918 Shifts in addresses can't be by a register. */
1919 #define MAX_REGS_PER_ADDRESS 2
1921 /* Recognize any constant value that is a valid address. */
1922 /* XXX We can address any constant, eventually... */
1923 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1924 #define CONSTANT_ADDRESS_P(X) \
1925 (GET_CODE (X) == SYMBOL_REF \
1926 && (CONSTANT_POOL_ADDRESS_P (X) \
1927 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1929 /* True if SYMBOL + OFFSET constants must refer to something within
1930 SYMBOL's section. */
1931 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1933 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1934 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1935 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1936 #endif
1938 /* Nonzero if the constant value X is a legitimate general operand.
1939 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1941 On the ARM, allow any integer (invalid ones are removed later by insn
1942 patterns), nice doubles and symbol_refs which refer to the function's
1943 constant pool XXX.
1945 When generating pic allow anything. */
1946 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1948 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1949 ( GET_CODE (X) == CONST_INT \
1950 || GET_CODE (X) == CONST_DOUBLE \
1951 || CONSTANT_ADDRESS_P (X) \
1952 || flag_pic)
1954 #define LEGITIMATE_CONSTANT_P(X) \
1955 (!arm_cannot_force_const_mem (X) \
1956 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1957 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1959 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1960 #define SUBTARGET_NAME_ENCODING_LENGTHS
1961 #endif
1963 /* This is a C fragment for the inside of a switch statement.
1964 Each case label should return the number of characters to
1965 be stripped from the start of a function's name, if that
1966 name starts with the indicated character. */
1967 #define ARM_NAME_ENCODING_LENGTHS \
1969 SUBTARGET_NAME_ENCODING_LENGTHS
1971 /* This is how to output a reference to a user-level label named NAME.
1972 `assemble_name' uses this. */
1973 #undef ASM_OUTPUT_LABELREF
1974 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1975 arm_asm_output_labelref (FILE, NAME)
1977 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1978 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1979 if (TARGET_THUMB2) \
1980 thumb2_asm_output_opcode (STREAM);
1982 /* The EABI specifies that constructors should go in .init_array.
1983 Other targets use .ctors for compatibility. */
1984 #ifndef ARM_EABI_CTORS_SECTION_OP
1985 #define ARM_EABI_CTORS_SECTION_OP \
1987 #endif
1988 #ifndef ARM_EABI_DTORS_SECTION_OP
1989 #define ARM_EABI_DTORS_SECTION_OP \
1991 #endif
1992 #define ARM_CTORS_SECTION_OP \
1994 #define ARM_DTORS_SECTION_OP \
1997 /* Define CTORS_SECTION_ASM_OP. */
1998 #undef CTORS_SECTION_ASM_OP
1999 #undef DTORS_SECTION_ASM_OP
2000 #ifndef IN_LIBGCC2
2001 # define CTORS_SECTION_ASM_OP \
2002 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2003 # define DTORS_SECTION_ASM_OP \
2004 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2006 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2007 so we cannot use the definition above. */
2008 # ifdef __ARM_EABI__
2009 /* The .ctors section is not part of the EABI, so we do not define
2010 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2011 from trying to use it. We do define it when doing normal
2012 compilation, as .init_array can be used instead of .ctors. */
2013 /* There is no need to emit begin or end markers when using
2014 init_array; the dynamic linker will compute the size of the
2015 array itself based on special symbols created by the static
2016 linker. However, we do need to arrange to set up
2017 exception-handling here. */
2018 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2020 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2023 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2024 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2028 /* True if the operating system can merge entities with vague linkage
2029 (e.g., symbols in COMDAT group) during dynamic linking. */
2030 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2031 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2032 #endif
2034 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2036 #ifdef TARGET_UNWIND_INFO
2037 #define ARM_EABI_UNWIND_TABLES \
2038 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2039 #else
2040 #define ARM_EABI_UNWIND_TABLES 0
2041 #endif
2043 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2044 and check its validity for a certain class.
2045 We have two alternate definitions for each of them.
2046 The usual definition accepts all pseudo regs; the other rejects
2047 them unless they have been allocated suitable hard regs.
2048 The symbol REG_OK_STRICT causes the latter definition to be used.
2049 Thumb-2 has the same restrictions as arm. */
2050 #ifndef REG_OK_STRICT
2052 #define ARM_REG_OK_FOR_BASE_P(X) \
2053 (REGNO (X) <= LAST_ARM_REGNUM \
2054 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2055 || REGNO (X) == FRAME_POINTER_REGNUM \
2056 || REGNO (X) == ARG_POINTER_REGNUM)
2058 #define ARM_REG_OK_FOR_INDEX_P(X) \
2059 ((REGNO (X) <= LAST_ARM_REGNUM \
2060 && REGNO (X) != STACK_POINTER_REGNUM) \
2061 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2062 || REGNO (X) == FRAME_POINTER_REGNUM \
2063 || REGNO (X) == ARG_POINTER_REGNUM)
2065 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2066 (REGNO (X) <= LAST_LO_REGNUM \
2067 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2068 || (GET_MODE_SIZE (MODE) >= 4 \
2069 && (REGNO (X) == STACK_POINTER_REGNUM \
2070 || (X) == hard_frame_pointer_rtx \
2071 || (X) == arg_pointer_rtx)))
2073 #define REG_STRICT_P 0
2077 #define ARM_REG_OK_FOR_BASE_P(X) \
2078 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2080 #define ARM_REG_OK_FOR_INDEX_P(X) \
2081 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2083 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2084 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2086 #define REG_STRICT_P 1
2090 /* Now define some helpers in terms of the above. */
2092 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2093 (TARGET_THUMB1 \
2094 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2095 : ARM_REG_OK_FOR_BASE_P (X))
2097 /* For 16-bit Thumb, a valid index register is anything that can be used in
2098 a byte load instruction. */
2099 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2100 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2102 /* Nonzero if X is a hard reg that can be used as an index
2103 or if it is a pseudo reg. On the Thumb, the stack pointer
2104 is not suitable. */
2105 #define REG_OK_FOR_INDEX_P(X) \
2106 (TARGET_THUMB1 \
2107 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2108 : ARM_REG_OK_FOR_INDEX_P (X))
2110 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2111 For Thumb, we can not use SP + reg, so reject SP. */
2112 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2113 REG_OK_FOR_INDEX_P (X)
2114 \f
2115 #define ARM_BASE_REGISTER_RTX_P(X) \
2116 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2118 #define ARM_INDEX_REGISTER_RTX_P(X) \
2119 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2120 \f
2121 /* Define this for compatibility reasons. */
2122 #define HANDLE_PRAGMA_PACK_PUSH_POP
2124 /* Specify the machine mode that this machine uses
2125 for the index in the tablejump instruction. */
2126 #define CASE_VECTOR_MODE Pmode
2128 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
2129 || (TARGET_THUMB1 \
2130 && (optimize_size || flag_pic)))
2132 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2133 (TARGET_THUMB1 \
2134 ? (min >= 0 && max < 512 \
2135 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2136 : min >= -256 && max < 256 \
2137 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2138 : min >= 0 && max < 8192 \
2139 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2140 : min >= -4096 && max < 4096 \
2141 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2142 : SImode) \
2143 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2144 : (max >= 0x200) ? HImode \
2145 : QImode))
2147 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2148 unsigned is probably best, but may break some code. */
2149 #ifndef DEFAULT_SIGNED_CHAR
2150 #define DEFAULT_SIGNED_CHAR 0
2151 #endif
2153 /* Max number of bytes we can move from memory to memory
2154 in one reasonably fast instruction. */
2155 #define MOVE_MAX 4
2157 #undef MOVE_RATIO
2158 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2160 /* Define if operations between registers always perform the operation
2161 on the full register even if a narrower mode is specified. */
2162 #define WORD_REGISTER_OPERATIONS
2164 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2165 will either zero-extend or sign-extend. The value of this macro should
2166 be the code that says which one of the two operations is implicitly
2167 done, UNKNOWN if none. */
2168 #define LOAD_EXTEND_OP(MODE) \
2169 (TARGET_THUMB ? ZERO_EXTEND : \
2170 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2171 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2173 /* Nonzero if access to memory by bytes is slow and undesirable. */
2174 #define SLOW_BYTE_ACCESS 0
2176 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2178 /* Immediate shift counts are truncated by the output routines (or was it
2179 the assembler?). Shift counts in a register are truncated by ARM. Note
2180 that the native compiler puts too large (> 32) immediate shift counts
2181 into a register and shifts by the register, letting the ARM decide what
2182 to do instead of doing that itself. */
2183 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2184 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2185 On the arm, Y in a register is used modulo 256 for the shift. Only for
2186 rotates is modulo 32 used. */
2187 /* #define SHIFT_COUNT_TRUNCATED 1 */
2189 /* All integers have the same format so truncation is easy. */
2190 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2192 /* Calling from registers is a massive pain. */
2193 #define NO_FUNCTION_CSE 1
2195 /* The machine modes of pointers and functions */
2196 #define Pmode SImode
2197 #define FUNCTION_MODE Pmode
2199 #define ARM_FRAME_RTX(X) \
2200 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2201 || (X) == arg_pointer_rtx)
2203 /* Moves to and from memory are quite expensive */
2204 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2205 (TARGET_32BIT ? 10 : \
2206 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2207 * (CLASS == LO_REGS ? 1 : 2)))
2209 /* Try to generate sequences that don't involve branches, we can then use
2210 conditional instructions */
2211 #define BRANCH_COST(speed_p, predictable_p) \
2212 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2213 \f
2214 /* Position Independent Code. */
2215 /* We decide which register to use based on the compilation options and
2216 the assembler in use; this is more general than the APCS restriction of
2217 using sb (r9) all the time. */
2220 /* The register number of the register used to address a table of static
2221 data addresses in memory. */
2222 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2224 /* We can't directly access anything that contains a symbol,
2225 nor can we indirect via the constant pool. One exception is
2226 UNSPEC_TLS, which is always PIC. */
2227 #define LEGITIMATE_PIC_OPERAND_P(X) \
2228 (!(symbol_mentioned_p (X) \
2229 || label_mentioned_p (X) \
2230 || (GET_CODE (X) == SYMBOL_REF \
2231 && CONSTANT_POOL_ADDRESS_P (X) \
2232 && (symbol_mentioned_p (get_pool_constant (X)) \
2233 || label_mentioned_p (get_pool_constant (X))))) \
2234 || tls_mentioned_p (X))
2236 /* We need to know when we are making a constant pool; this determines
2237 whether data needs to be in the GOT or can be referenced via a GOT
2238 offset. */
2240 \f
2241 /* Handle pragmas for compatibility with Intel's compilers. */
2242 /* Also abuse this to register additional C specific EABI attributes. */
2243 #define REGISTER_TARGET_PRAGMAS() do { \
2247 arm_lang_object_attributes_init(); \
2248 } while (0)
2250 /* Condition code information. */
2251 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2252 return the mode to be used for the comparison. */
2254 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2256 #define REVERSIBLE_CC_MODE(MODE) 1
2258 #define REVERSE_CONDITION(CODE,MODE) \
2259 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2260 ? reverse_condition_maybe_unordered (code) \
2261 : reverse_condition (code))
2263 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2264 (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1))
2266 /* The arm5 clz instruction returns 32. */
2267 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2268 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2269 \f
2270 #define CC_STATUS_INIT \
2271 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2273 #undef ASM_APP_OFF
2277 /* Output a push or a pop instruction (only used when profiling).
2278 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2279 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2280 that r7 isn't used by the function profiler, so we can use it as a
2281 scratch reg. WARNING: This isn't safe in the general case! It may be
2282 sensitive to future changes in final.c:profile_function. */
2283 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2284 do \
2285 { \
2286 if (TARGET_ARM) \
2288 STACK_POINTER_REGNUM, REGNO); \
2289 else if (TARGET_THUMB1 \
2290 && (REGNO) == STATIC_CHAIN_REGNUM) \
2291 { \
2295 } \
2296 else \
2298 } while (0)
2301 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2302 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2303 do \
2304 { \
2305 if (TARGET_ARM) \
2307 STACK_POINTER_REGNUM, REGNO); \
2308 else if (TARGET_THUMB1 \
2309 && (REGNO) == STATIC_CHAIN_REGNUM) \
2310 { \
2314 } \
2315 else \
2317 } while (0)
2319 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2320 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2322 /* This is how to output a label which precedes a jumptable. Since
2323 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2324 #undef ASM_OUTPUT_CASE_LABEL
2325 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2326 do \
2327 { \
2328 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2329 ASM_OUTPUT_ALIGN (FILE, 2); \
2330 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2331 } \
2332 while (0)
2334 /* Make sure subsequent insns are aligned after a TBB. */
2335 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2336 do \
2337 { \
2338 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2339 ASM_OUTPUT_ALIGN (FILE, 1); \
2340 } \
2341 while (0)
2343 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2344 do \
2345 { \
2346 if (TARGET_THUMB) \
2347 { \
2348 if (is_called_in_ARM_mode (DECL) \
2349 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2350 && cfun->is_thunk)) \
2352 else if (TARGET_THUMB1) \
2354 else \
2356 } \
2357 if (TARGET_POKE_FUNCTION_NAME) \
2358 arm_poke_function_name (STREAM, (const char *) NAME); \
2359 } \
2360 while (0)
2362 /* For aliases of functions we use .thumb_set instead. */
2363 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2364 do \
2365 { \
2366 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2367 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2368 \
2369 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2370 { \
2372 assemble_name (FILE, LABEL1); \
2374 assemble_name (FILE, LABEL2); \
2376 } \
2377 else \
2378 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2379 } \
2380 while (0)
2382 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2383 /* To support -falign-* switches we need to use .p2align so
2384 that alignment directives in code sections will be padded
2385 with no-op instructions, rather than zeroes. */
2386 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2387 if ((LOG) != 0) \
2388 { \
2389 if ((MAX_SKIP) == 0) \
2391 else \
2393 (int) (LOG), (int) (MAX_SKIP)); \
2394 }
2395 #endif
2396 \f
2397 /* Add two bytes to the length of conditionally executed Thumb-2
2398 instructions for the IT instruction. */
2399 #define ADJUST_INSN_LENGTH(insn, length) \
2400 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2401 length += 2;
2403 /* Only perform branch elimination (by making instructions conditional) if
2404 we're optimizing. For Thumb-2 check if any IT instructions need
2405 outputting. */
2406 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2407 if (TARGET_ARM && optimize) \
2408 arm_final_prescan_insn (INSN); \
2409 else if (TARGET_THUMB2) \
2410 thumb2_final_prescan_insn (INSN); \
2411 else if (TARGET_THUMB1) \
2412 thumb1_final_prescan_insn (INSN)
2414 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2415 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2416 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2417 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2418 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2419 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2420 : 0))))
2422 /* A C expression whose value is RTL representing the value of the return
2423 address for the frame COUNT steps up from the current frame. */
2425 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2426 arm_return_addr (COUNT, FRAME)
2428 /* Mask of the bits in the PC that contain the real return address
2429 when running in 26-bit mode. */
2430 #define RETURN_ADDR_MASK26 (0x03fffffc)
2432 /* Pick up the return address upon entry to a procedure. Used for
2433 dwarf2 unwind information. This also enables the table driven
2434 mechanism. */
2435 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2436 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2438 /* Used to mask out junk bits from the return address, such as
2439 processor state, interrupt status, condition codes and the like. */
2440 #define MASK_RETURN_ADDR \
2441 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2442 in 26 bit mode, the condition codes must be masked out of the \
2443 return address. This does not apply to ARM6 and later processors \
2445 ((arm_arch4 || TARGET_THUMB) \
2446 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2447 : arm_gen_return_addr_mask ())
2449 \f
2450 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2451 symbolic names defined here (which would require too much duplication).
2452 FIXME? */
2453 enum arm_builtins
2454 {
2455 ARM_BUILTIN_GETWCX,
2456 ARM_BUILTIN_SETWCX,
2458 ARM_BUILTIN_WZERO,
2460 ARM_BUILTIN_WAVG2BR,
2461 ARM_BUILTIN_WAVG2HR,
2462 ARM_BUILTIN_WAVG2B,
2463 ARM_BUILTIN_WAVG2H,
2465 ARM_BUILTIN_WACCB,
2466 ARM_BUILTIN_WACCH,
2467 ARM_BUILTIN_WACCW,
2469 ARM_BUILTIN_WMACS,
2470 ARM_BUILTIN_WMACSZ,
2471 ARM_BUILTIN_WMACU,
2472 ARM_BUILTIN_WMACUZ,
2474 ARM_BUILTIN_WSADB,
2475 ARM_BUILTIN_WSADBZ,
2476 ARM_BUILTIN_WSADH,
2477 ARM_BUILTIN_WSADHZ,
2479 ARM_BUILTIN_WALIGN,
2481 ARM_BUILTIN_TMIA,
2482 ARM_BUILTIN_TMIAPH,
2483 ARM_BUILTIN_TMIABB,
2484 ARM_BUILTIN_TMIABT,
2485 ARM_BUILTIN_TMIATB,
2486 ARM_BUILTIN_TMIATT,
2488 ARM_BUILTIN_TMOVMSKB,
2489 ARM_BUILTIN_TMOVMSKH,
2490 ARM_BUILTIN_TMOVMSKW,
2492 ARM_BUILTIN_TBCSTB,
2493 ARM_BUILTIN_TBCSTH,
2494 ARM_BUILTIN_TBCSTW,
2496 ARM_BUILTIN_WMADDS,
2497 ARM_BUILTIN_WMADDU,
2499 ARM_BUILTIN_WPACKHSS,
2500 ARM_BUILTIN_WPACKWSS,
2501 ARM_BUILTIN_WPACKDSS,
2502 ARM_BUILTIN_WPACKHUS,
2503 ARM_BUILTIN_WPACKWUS,
2504 ARM_BUILTIN_WPACKDUS,
2506 ARM_BUILTIN_WADDB,
2507 ARM_BUILTIN_WADDH,
2508 ARM_BUILTIN_WADDW,
2509 ARM_BUILTIN_WADDSSB,
2510 ARM_BUILTIN_WADDSSH,
2511 ARM_BUILTIN_WADDSSW,
2512 ARM_BUILTIN_WADDUSB,
2513 ARM_BUILTIN_WADDUSH,
2514 ARM_BUILTIN_WADDUSW,
2515 ARM_BUILTIN_WSUBB,
2516 ARM_BUILTIN_WSUBH,
2517 ARM_BUILTIN_WSUBW,
2518 ARM_BUILTIN_WSUBSSB,
2519 ARM_BUILTIN_WSUBSSH,
2520 ARM_BUILTIN_WSUBSSW,
2521 ARM_BUILTIN_WSUBUSB,
2522 ARM_BUILTIN_WSUBUSH,
2523 ARM_BUILTIN_WSUBUSW,
2525 ARM_BUILTIN_WAND,
2526 ARM_BUILTIN_WANDN,
2527 ARM_BUILTIN_WOR,
2528 ARM_BUILTIN_WXOR,
2530 ARM_BUILTIN_WCMPEQB,
2531 ARM_BUILTIN_WCMPEQH,
2532 ARM_BUILTIN_WCMPEQW,
2533 ARM_BUILTIN_WCMPGTUB,
2534 ARM_BUILTIN_WCMPGTUH,
2535 ARM_BUILTIN_WCMPGTUW,
2536 ARM_BUILTIN_WCMPGTSB,
2537 ARM_BUILTIN_WCMPGTSH,
2538 ARM_BUILTIN_WCMPGTSW,
2540 ARM_BUILTIN_TEXTRMSB,
2541 ARM_BUILTIN_TEXTRMSH,
2542 ARM_BUILTIN_TEXTRMSW,
2543 ARM_BUILTIN_TEXTRMUB,
2544 ARM_BUILTIN_TEXTRMUH,
2545 ARM_BUILTIN_TEXTRMUW,
2546 ARM_BUILTIN_TINSRB,
2547 ARM_BUILTIN_TINSRH,
2548 ARM_BUILTIN_TINSRW,
2550 ARM_BUILTIN_WMAXSW,
2551 ARM_BUILTIN_WMAXSH,
2552 ARM_BUILTIN_WMAXSB,
2553 ARM_BUILTIN_WMAXUW,
2554 ARM_BUILTIN_WMAXUH,
2555 ARM_BUILTIN_WMAXUB,
2556 ARM_BUILTIN_WMINSW,
2557 ARM_BUILTIN_WMINSH,
2558 ARM_BUILTIN_WMINSB,
2559 ARM_BUILTIN_WMINUW,
2560 ARM_BUILTIN_WMINUH,
2561 ARM_BUILTIN_WMINUB,
2563 ARM_BUILTIN_WMULUM,
2564 ARM_BUILTIN_WMULSM,
2565 ARM_BUILTIN_WMULUL,
2567 ARM_BUILTIN_PSADBH,
2568 ARM_BUILTIN_WSHUFH,
2570 ARM_BUILTIN_WSLLH,
2571 ARM_BUILTIN_WSLLW,
2572 ARM_BUILTIN_WSLLD,
2573 ARM_BUILTIN_WSRAH,
2574 ARM_BUILTIN_WSRAW,
2575 ARM_BUILTIN_WSRAD,
2576 ARM_BUILTIN_WSRLH,
2577 ARM_BUILTIN_WSRLW,
2578 ARM_BUILTIN_WSRLD,
2579 ARM_BUILTIN_WRORH,
2580 ARM_BUILTIN_WRORW,
2581 ARM_BUILTIN_WRORD,
2582 ARM_BUILTIN_WSLLHI,
2583 ARM_BUILTIN_WSLLWI,
2584 ARM_BUILTIN_WSLLDI,
2585 ARM_BUILTIN_WSRAHI,
2586 ARM_BUILTIN_WSRAWI,
2587 ARM_BUILTIN_WSRADI,
2588 ARM_BUILTIN_WSRLHI,
2589 ARM_BUILTIN_WSRLWI,
2590 ARM_BUILTIN_WSRLDI,
2591 ARM_BUILTIN_WRORHI,
2592 ARM_BUILTIN_WRORWI,
2593 ARM_BUILTIN_WRORDI,
2595 ARM_BUILTIN_WUNPCKIHB,
2596 ARM_BUILTIN_WUNPCKIHH,
2597 ARM_BUILTIN_WUNPCKIHW,
2598 ARM_BUILTIN_WUNPCKILB,
2599 ARM_BUILTIN_WUNPCKILH,
2600 ARM_BUILTIN_WUNPCKILW,
2602 ARM_BUILTIN_WUNPCKEHSB,
2603 ARM_BUILTIN_WUNPCKEHSH,
2604 ARM_BUILTIN_WUNPCKEHSW,
2605 ARM_BUILTIN_WUNPCKEHUB,
2606 ARM_BUILTIN_WUNPCKEHUH,
2607 ARM_BUILTIN_WUNPCKEHUW,
2608 ARM_BUILTIN_WUNPCKELSB,
2609 ARM_BUILTIN_WUNPCKELSH,
2610 ARM_BUILTIN_WUNPCKELSW,
2611 ARM_BUILTIN_WUNPCKELUB,
2612 ARM_BUILTIN_WUNPCKELUH,
2613 ARM_BUILTIN_WUNPCKELUW,
2615 ARM_BUILTIN_THREAD_POINTER,
2617 ARM_BUILTIN_NEON_BASE,
2620 };
2622 /* Do not emit .note.GNU-stack by default. */
2623 #ifndef NEED_INDICATE_EXEC_STACK
2624 #define NEED_INDICATE_EXEC_STACK 0
2625 #endif
2627 /* The maximum number of parallel loads or stores we support in an ldm/stm
2628 instruction. */
2629 #define MAX_LDM_STM_OPS 4