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2023-09-05	Christoph Müllner	riscv: Synthesize all 11-bit-rotate constants with...	commit \| commitdiff \| tree
2023-09-05	Christoph Müllner	riscv: xtheadbb: Enable constant synthesis with th...	commit \| commitdiff \| tree
2023-09-05	Christoph Müllner	riscv: xtheadcondmov: Don't run tests with -Oz	commit \| commitdiff \| tree
2023-08-07	Manolis Tsamis	cprop_hardreg: Allow propagation of stack pointer in...	commit \| commitdiff \| tree
2023-07-12	Christoph Müllner	riscv: thead: Fix failing XTheadCondMov tests (indirect...	commit \| commitdiff \| tree
2023-07-03	Christoph Müllner	RISC-V: Add support for vector crypto extensions	commit \| commitdiff \| tree
2023-06-28	Manolis Tsamis	cprop_hardreg: fix ORIGINAL_REGNO/REG_ATTRS/REG_POINTER... Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>	commit \| commitdiff \| tree
2023-06-15	Manolis Tsamis	cprop_hardreg: Enable propagation of the stack pointer...	commit \| commitdiff \| tree
2023-05-11	mtsamis	aarch64: convert vector shift + bitwise and + multiply... Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>	commit \| commitdiff \| tree
2023-04-17	Philipp Tomsich	aarch64: disable LDP via tuning structure for -mcpu... Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>	commit \| commitdiff \| tree
2023-03-27	Christoph Müllner	target/109296 - riscv: Add missing mode specifiers...	commit \| commitdiff \| tree
2023-03-27	Philipp Tomsich	aarch64: update ampere1 vectorization cost	commit \| commitdiff \| tree
2023-03-15	Christoph Müllner	riscv: thead: Add support for the XTheadMemPair ISA...	commit \| commitdiff \| tree
2023-03-15	Christoph Müllner	riscv: thead: Add support for the XTheadFmv ISA extension	commit \| commitdiff \| tree
2023-03-15	Christoph Müllner	riscv: thead: Add support for the XTheadMac ISA extension	commit \| commitdiff \| tree
2023-03-15	Christoph Müllner	riscv: thead: Add support for the XTheadCondMov ISA...	commit \| commitdiff \| tree
2023-03-15	Christoph Müllner	riscv: thead: Add support for the XTheadBb ISA extension	commit \| commitdiff \| tree
2023-03-15	Christoph Müllner	riscv: thead: Add support for the XTheadBs ISA extension	commit \| commitdiff \| tree
2023-03-15	Christoph Müllner	riscv: thead: Add support for the XTheadBa ISA extension	commit \| commitdiff \| tree
2023-03-15	Christoph Müllner	riscv: riscv-cores.def: Add T-Head XuanTie C906	commit \| commitdiff \| tree
2023-03-15	Christoph Müllner	riscv: Add basic XThead* vendor extension support	commit \| commitdiff \| tree
2023-01-31	Philipp Tomsich	PR target/108589 - Check REG_P for AARCH64_FUSE_ADDSUB_2REG_...	commit \| commitdiff \| tree
2023-01-30	Philipp Tomsich	aarch64: Update Ampere-1A (-mcpu=ampere1a) to include SM4	commit \| commitdiff \| tree
2023-01-28	Philipp Tomsich	aarch64: Correct the maximum shift amount for shifted...	commit \| commitdiff \| tree
2022-12-27	Christoph Müllner	riscv: Restructure callee-saved register save/restore...	commit \| commitdiff \| tree
2022-12-27	Christoph Müllner	riscv: attr: Synchronize comments with code	commit \| commitdiff \| tree
2022-11-21	Philipp Tomsich	RISC-V: Fix ICE in branch<ANYI:mode>_shiftedarith_equals_zero	commit \| commitdiff \| tree
2022-11-18	Philipp Tomsich	RISC-V: No extensions for SImode min/max against safe...	commit \| commitdiff \| tree
2022-11-18	Philipp Tomsich	RISC-V: Handle "(a & twobits) == singlebit" in branches...	commit \| commitdiff \| tree
2022-11-18	Philipp Tomsich	RISC-V: Use bseti/bclri/binvi to extend reach of ori...	commit \| commitdiff \| tree
2022-11-18	Philipp Tomsich	RISC-V: Optimize slli(.uw)? + addw + zext.w into sh...	commit \| commitdiff \| tree
2022-11-18	Philipp Tomsich	RISC-V: split to allow formation of sh[123]add before...	commit \| commitdiff \| tree
2022-11-18	Philipp Tomsich	RISC-V: Optimize branches testing a bit-range or a...	commit \| commitdiff \| tree
2022-11-18	Philipp Tomsich	RISC-V: allow bseti on SImode without sign-extension	commit \| commitdiff \| tree
2022-11-17	Philipp Tomsich	RISC-V: Optimize masking with two clear bits not a...	commit \| commitdiff \| tree
2022-11-17	Philipp Tomsich	RISC-V: bitmanip: add splitter to use bexti for "(a...	commit \| commitdiff \| tree
2022-11-17	mtsamis	Enable shrink wrapping for the RISC-V target.	commit \| commitdiff \| tree
2022-11-16	Philipp Tomsich	RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext... Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>	commit \| commitdiff \| tree
2022-11-16	Philipp Tomsich	RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext...	commit \| commitdiff \| tree
2022-11-16	Christoph Müllner	doc: invoke: pru/riscv: Fix option list formatting	commit \| commitdiff \| tree
2022-11-15	Philipp Tomsich	RISC-V: Zihintpause: add __builtin_riscv_pause	commit \| commitdiff \| tree
2022-11-14	Philipp Tomsich	Revert "RISC-V: Add basic support for the Ventana-VT1...	commit \| commitdiff \| tree
2022-11-14	Philipp Tomsich	Revert "RISC-V: Add instruction fusion (for ventana...	commit \| commitdiff \| tree
2022-11-14	Philipp Tomsich	riscv: bitmanip: add orc.b as an unspec Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>	commit \| commitdiff \| tree
2022-11-14	Philipp Tomsich	RISC-V: Add instruction fusion (for ventana-vt1)	commit \| commitdiff \| tree
2022-11-14	Philipp Tomsich	RISC-V: Add basic support for the Ventana-VT1 core	commit \| commitdiff \| tree
2022-11-14	Philipp Tomsich	aarch64: Add support for Ampere-1A (-mcpu=ampere1a...	commit \| commitdiff \| tree
2022-11-13	Philipp Tomsich	RISC-V: optimize '(a >= 0) ? b : 0' to srai + andn...	commit \| commitdiff \| tree
2022-11-13	Philipp Tomsich	doc: Update Jeff Law's email-address in contrib.rst	commit \| commitdiff \| tree
2022-11-13	Philipp Tomsich	RISC-V: costs: support shift-and-add in strength-reduction	commit \| commitdiff \| tree
2022-11-10	Philipp Tomsich	RISC-V: Fix selection of pipeline model for sifive...	commit \| commitdiff \| tree
2022-11-09	Philipp Tomsich	RISC-V: costs: handle BSWAP	commit \| commitdiff \| tree
2022-11-02	Christoph Müllner	RISC-V: Add Zawrs ISA extension support	commit \| commitdiff \| tree
2022-10-06	Philipp Tomsich	aarch64: update Ampere-1 core definition Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>	commit \| commitdiff \| tree
2022-10-06	Philipp Tomsich	aarch64: fix off-by-one in reading cpuinfo Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>	commit \| commitdiff \| tree
2022-06-14	Philipp Tomsich	RISC-V: Split slli+sh[123]add.uw opportunities to avoid... Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>	commit \| commitdiff \| tree
2022-06-14	Philipp Tomsich	RISC-V: add consecutive_bits_operand predicate Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>	commit \| commitdiff \| tree
2022-06-02	Philipp Tomsich	RISC-V: bitmanip: improve constant-loading for (1ULL... Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>	commit \| commitdiff \| tree
2022-05-13	Philipp Tomsich	RISC-V: Implement C[LT]Z_DEFINED_VALUE_AT_ZERO Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>	commit \| commitdiff \| tree
2021-11-03	Philipp Tomsich	aarch64: enable Ampere-1 CPU	commit \| commitdiff \| tree
2021-01-04	Philipp Tomsich	MAINTAINERS: Update my email address. 2021-01-04 Philipp Tomsich <philipp.tomsich@vrull.eu>	commit \| commitdiff \| tree

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