gcc/config/riscv/riscv.h

   1 /* Definition of RISC-V target for GNU compiler.
   2    Copyright (C) 2011-2019 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4    Based on MIPS target for GNU compiler.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3, or (at your option)
  11 any later version.
  12
  13 GCC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_RISCV_H
  23 #define GCC_RISCV_H
  24
  25 #include "config/riscv/riscv-opts.h"
  26
  27 /* Target CPU builtins.  */
  28 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
  29
  30 /* Target CPU versions for D.  */
  31 #define TARGET_D_CPU_VERSIONS riscv_d_target_versions
  32
  33 /* Default target_flags if no switches are specified  */
  34
  35 #ifndef TARGET_DEFAULT
  36 #define TARGET_DEFAULT 0
  37 #endif
  38
  39 #ifndef RISCV_TUNE_STRING_DEFAULT
  40 #define RISCV_TUNE_STRING_DEFAULT "rocket"
  41 #endif
  42
  43 /* Support for a compile-time default CPU, et cetera.  The rules are:
  44    --with-arch is ignored if -march is specified.
  45    --with-abi is ignored if -mabi is specified.
  46    --with-tune is ignored if -mtune is specified.  */
  47 #define OPTION_DEFAULT_SPECS \
  48   {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
  49   {"arch", "%{!march=*:-march=%(VALUE)}" }, \
  50   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
  51
  52 #ifdef IN_LIBGCC2
  53 #undef TARGET_64BIT
  54 /* Make this compile time constant for libgcc2 */
  55 #define TARGET_64BIT           (__riscv_xlen == 64)
  56 #endif /* IN_LIBGCC2 */
  57
  58 #undef ASM_SPEC
  59 #define ASM_SPEC "\
  60 %(subtarget_asm_debugging_spec) \
  61 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
  62 %{march=*} \
  63 %{mabi=*} \
  64 %(subtarget_asm_spec)"
  65
  66 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
  67
  68 #define LOCAL_LABEL_PREFIX      "."
  69 #define USER_LABEL_PREFIX       ""
  70
  71 /* Offsets recorded in opcodes are a multiple of this alignment factor.
  72    The default for this in 64-bit mode is 8, which causes problems with
  73    SFmode register saves.  */
  74 #define DWARF_CIE_DATA_ALIGNMENT -4
  75
  76 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
  77 #define DWARF_FRAME_REGNUM(REGNO) \
  78   (GP_REG_P (REGNO) || FP_REG_P (REGNO) ? REGNO : INVALID_REGNUM)
  79
  80 /* The DWARF 2 CFA column which tracks the return address.  */
  81 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
  82 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
  83
  84 /* Describe how we implement __builtin_eh_return.  */
  85 #define EH_RETURN_DATA_REGNO(N) \
  86   ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
  87
  88 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
  89
  90 /* Target machine storage layout */
  91
  92 #define BITS_BIG_ENDIAN 0
  93 #define BYTES_BIG_ENDIAN 0
  94 #define WORDS_BIG_ENDIAN 0
  95
  96 #define MAX_BITS_PER_WORD 64
  97
  98 /* Width of a word, in units (bytes).  */
  99 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
 100 #ifndef IN_LIBGCC2
 101 #define MIN_UNITS_PER_WORD 4
 102 #endif
 103
 104 /* The `Q' extension is not yet supported.  */
 105 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
 106
 107 /* The largest type that can be passed in floating-point registers.  */
 108 #define UNITS_PER_FP_ARG                                                \
 109   ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E                   \
 110     || riscv_abi == ABI_LP64)                                           \
 111    ? 0                                                                  \
 112    : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8))
 113
 114 /* Set the sizes of the core types.  */
 115 #define SHORT_TYPE_SIZE 16
 116 #define INT_TYPE_SIZE 32
 117 #define LONG_LONG_TYPE_SIZE 64
 118 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
 119 #define LONG_TYPE_SIZE POINTER_SIZE
 120
 121 #define FLOAT_TYPE_SIZE 32
 122 #define DOUBLE_TYPE_SIZE 64
 123 #define LONG_DOUBLE_TYPE_SIZE 128
 124
 125 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 126 #define PARM_BOUNDARY BITS_PER_WORD
 127
 128 /* Allocation boundary (in *bits*) for the code of a function.  */
 129 #define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
 130
 131 /* The smallest supported stack boundary the calling convention supports.  */
 132 #define STACK_BOUNDARY \
 133   (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 2 * BITS_PER_WORD)
 134
 135 /* The ABI stack alignment.  */
 136 #define ABI_STACK_BOUNDARY (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 128)
 137
 138 /* There is no point aligning anything to a rounder boundary than this.  */
 139 #define BIGGEST_ALIGNMENT 128
 140
 141 /* The user-level ISA permits unaligned accesses, but they are not required
 142    of the privileged architecture.  */
 143 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
 144
 145 /* Define this if you wish to imitate the way many other C compilers
 146    handle alignment of bitfields and the structures that contain
 147    them.
 148
 149    The behavior is that the type written for a bit-field (`int',
 150    `short', or other integer type) imposes an alignment for the
 151    entire structure, as if the structure really did contain an
 152    ordinary field of that type.  In addition, the bit-field is placed
 153    within the structure so that it would fit within such a field,
 154    not crossing a boundary for it.
 155
 156    Thus, on most machines, a bit-field whose type is written as `int'
 157    would not cross a four-byte boundary, and would force four-byte
 158    alignment for the whole structure.  (The alignment used may not
 159    be four bytes; it is controlled by the other alignment
 160    parameters.)
 161
 162    If the macro is defined, its definition should be a C expression;
 163    a nonzero value for the expression enables this behavior.  */
 164
 165 #define PCC_BITFIELD_TYPE_MATTERS 1
 166
 167 /* An integer expression for the size in bits of the largest integer machine
 168    mode that should actually be used.  We allow pairs of registers.  */
 169 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
 170
 171 /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition.  */
 172 #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN)                       \
 173   (((COND) && ((ALIGN) < BITS_PER_WORD)                                 \
 174     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 175         || TREE_CODE (TYPE) == UNION_TYPE                               \
 176         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 177
 178 /* If defined, a C expression to compute the alignment for a static
 179    variable.  TYPE is the data type, and ALIGN is the alignment that
 180    the object would ordinarily have.  The value of this macro is used
 181    instead of that alignment to align the object.
 182
 183    If this macro is not defined, then ALIGN is used.
 184
 185    One use of this macro is to increase alignment of medium-size
 186    data to make it all fit in fewer cache lines.  Another is to
 187    cause character arrays to be word-aligned so that `strcpy' calls
 188    that copy constants to character arrays can be done inline.  */
 189
 190 #define DATA_ALIGNMENT(TYPE, ALIGN)                                             \
 191   RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen,  \
 192                           TYPE, ALIGN)
 193
 194 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
 195    character arrays to be word-aligned so that `strcpy' calls that copy
 196    constants to character arrays can be done inline, and 'strcmp' can be
 197    optimised to use word loads. */
 198 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
 199   RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN)
 200
 201 /* Define if operations between registers always perform the operation
 202    on the full register even if a narrower mode is specified.  */
 203 #define WORD_REGISTER_OPERATIONS 1
 204
 205 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
 206    moves.  All other references are zero extended.  */
 207 #define LOAD_EXTEND_OP(MODE) \
 208   (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
 209
 210 /* Define this macro if it is advisable to hold scalars in registers
 211    in a wider mode than that declared by the program.  In such cases,
 212    the value is constrained to be within the bounds of the declared
 213    type, but kept valid in the wider mode.  The signedness of the
 214    extension may differ from that of the type.  */
 215
 216 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
 217   if (GET_MODE_CLASS (MODE) == MODE_INT         \
 218       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
 219     {                                           \
 220       if ((MODE) == SImode)                     \
 221         (UNSIGNEDP) = 0;                        \
 222       (MODE) = word_mode;                       \
 223     }
 224
 225 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
 226    Extensions of pointers to word_mode must be signed.  */
 227 #define POINTERS_EXTEND_UNSIGNED false
 228
 229 /* Define if loading short immediate values into registers sign extends.  */
 230 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
 231
 232 /* Standard register usage.  */
 233
 234 /* Number of hardware registers.  We have:
 235
 236    - 32 integer registers
 237    - 32 floating point registers
 238    - 2 fake registers:
 239         - ARG_POINTER_REGNUM
 240         - FRAME_POINTER_REGNUM */
 241
 242 #define FIRST_PSEUDO_REGISTER 66
 243
 244 /* x0, sp, gp, and tp are fixed.  */
 245
 246 #define FIXED_REGISTERS                                                 \
 247 { /* General registers.  */                                             \
 248   1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 249   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 250   /* Floating-point registers.  */                                      \
 251   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 252   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 253   /* Others.  */                                                        \
 254   1, 1                                                                  \
 255 }
 256
 257 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls.
 258    The call RTLs themselves clobber ra.  */
 259
 260 #define CALL_USED_REGISTERS                                             \
 261 { /* General registers.  */                                             \
 262   1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 263   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 264   /* Floating-point registers.  */                                      \
 265   1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 266   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 267   /* Others.  */                                                        \
 268   1, 1                                                                  \
 269 }
 270
 271 /* Internal macros to classify an ISA register's type.  */
 272
 273 #define GP_REG_FIRST 0
 274 #define GP_REG_LAST  (TARGET_RVE ? 15 : 31)
 275 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 276
 277 #define FP_REG_FIRST 32
 278 #define FP_REG_LAST  63
 279 #define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
 280
 281 /* The DWARF 2 CFA column which tracks the return address from a
 282    signal handler context.  This means that to maintain backwards
 283    compatibility, no hard register can be assigned this column if it
 284    would need to be handled by the DWARF unwinder.  */
 285 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
 286
 287 #define GP_REG_P(REGNO) \
 288   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 289 #define FP_REG_P(REGNO)  \
 290   ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
 291
 292 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
 293
 294 /* Use s0 as the frame pointer if it is so requested.  */
 295 #define HARD_FRAME_POINTER_REGNUM 8
 296 #define STACK_POINTER_REGNUM 2
 297 #define THREAD_POINTER_REGNUM 4
 298
 299 /* These two registers don't really exist: they get eliminated to either
 300    the stack or hard frame pointer.  */
 301 #define ARG_POINTER_REGNUM 64
 302 #define FRAME_POINTER_REGNUM 65
 303
 304 /* Register in which static-chain is passed to a function.  */
 305 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
 306
 307 /* Registers used as temporaries in prologue/epilogue code.
 308
 309    The prologue registers mustn't conflict with any
 310    incoming arguments, the static chain pointer, or the frame pointer.
 311    The epilogue temporary mustn't conflict with the return registers,
 312    the frame pointer, the EH stack adjustment, or the EH data registers. */
 313
 314 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST + 1)
 315 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
 316
 317 #define MCOUNT_NAME "_mcount"
 318
 319 #define NO_PROFILE_COUNTERS 1
 320
 321 /* Emit rtl for profiling.  Output assembler code to FILE
 322    to call "_mcount" for profiling a function entry.  */
 323 #define PROFILE_HOOK(LABEL)                                             \
 324   {                                                                     \
 325     rtx fun, ra;                                                        \
 326     ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);          \
 327     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 328     emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode);           \
 329   }
 330
 331 /* All the work done in PROFILE_HOOK, but still required.  */
 332 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 333
 334 /* Define this macro if it is as good or better to call a constant
 335    function address than to call an address kept in a register.  */
 336 #define NO_FUNCTION_CSE 1
 337
 338 /* Define the classes of registers for register constraints in the
 339    machine description.  Also define ranges of constants.
 340
 341    One of the classes must always be named ALL_REGS and include all hard regs.
 342    If there is more than one class, another class must be named NO_REGS
 343    and contain no registers.
 344
 345    The name GENERAL_REGS must be the name of a class (or an alias for
 346    another name such as ALL_REGS).  This is the class of registers
 347    that is allowed by "g" or "r" in a register constraint.
 348    Also, registers outside this class are allocated only when
 349    instructions express preferences for them.
 350
 351    The classes must be numbered in nondecreasing order; that is,
 352    a larger-numbered class must never be contained completely
 353    in a smaller-numbered class.
 354
 355    For any two classes, it is very desirable that there be another
 356    class that represents their union.  */
 357
 358 enum reg_class
 359 {
 360   NO_REGS,                      /* no registers in set */
 361   SIBCALL_REGS,                 /* registers used by indirect sibcalls */
 362   JALR_REGS,                    /* registers used by indirect calls */
 363   GR_REGS,                      /* integer registers */
 364   FP_REGS,                      /* floating-point registers */
 365   FRAME_REGS,                   /* arg pointer and frame pointer */
 366   ALL_REGS,                     /* all registers */
 367   LIM_REG_CLASSES               /* max value + 1 */
 368 };
 369
 370 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 371
 372 #define GENERAL_REGS GR_REGS
 373
 374 /* An initializer containing the names of the register classes as C
 375    string constants.  These names are used in writing some of the
 376    debugging dumps.  */
 377
 378 #define REG_CLASS_NAMES                                                 \
 379 {                                                                       \
 380   "NO_REGS",                                                            \
 381   "SIBCALL_REGS",                                                       \
 382   "JALR_REGS",                                                          \
 383   "GR_REGS",                                                            \
 384   "FP_REGS",                                                            \
 385   "FRAME_REGS",                                                         \
 386   "ALL_REGS"                                                            \
 387 }
 388
 389 /* An initializer containing the contents of the register classes,
 390    as integers which are bit masks.  The Nth integer specifies the
 391    contents of class N.  The way the integer MASK is interpreted is
 392    that register R is in the class if `MASK & (1 << R)' is 1.
 393
 394    When the machine has more than 32 registers, an integer does not
 395    suffice.  Then the integers are replaced by sub-initializers,
 396    braced groupings containing several integers.  Each
 397    sub-initializer must be suitable as an initializer for the type
 398    `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
 399
 400 #define REG_CLASS_CONTENTS                                              \
 401 {                                                                       \
 402   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 403   { 0xf00000c0, 0x00000000, 0x00000000 },       /* SIBCALL_REGS */      \
 404   { 0xffffffc0, 0x00000000, 0x00000000 },       /* JALR_REGS */         \
 405   { 0xffffffff, 0x00000000, 0x00000000 },       /* GR_REGS */           \
 406   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS */           \
 407   { 0x00000000, 0x00000000, 0x00000003 },       /* FRAME_REGS */        \
 408   { 0xffffffff, 0xffffffff, 0x00000003 }        /* ALL_REGS */          \
 409 }
 410
 411 /* A C expression whose value is a register class containing hard
 412    register REGNO.  In general there is more that one such class;
 413    choose a class which is "minimal", meaning that no smaller class
 414    also contains the register.  */
 415
 416 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
 417
 418 /* A macro whose definition is the name of the class to which a
 419    valid base register must belong.  A base register is one used in
 420    an address which is the register value plus a displacement.  */
 421
 422 #define BASE_REG_CLASS GR_REGS
 423
 424 /* A macro whose definition is the name of the class to which a
 425    valid index register must belong.  An index register is one used
 426    in an address where its value is either multiplied by a scale
 427    factor or added to another register (as well as added to a
 428    displacement).  */
 429
 430 #define INDEX_REG_CLASS NO_REGS
 431
 432 /* We generally want to put call-clobbered registers ahead of
 433    call-saved ones.  (IRA expects this.)  */
 434
 435 #define REG_ALLOC_ORDER                                                 \
 436 { \
 437   /* Call-clobbered GPRs.  */                                           \
 438   15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1,           \
 439   /* Call-saved GPRs.  */                                               \
 440   8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,                         \
 441   /* GPRs that can never be exposed to the register allocator.  */      \
 442   0, 2, 3, 4,                                                           \
 443   /* Call-clobbered FPRs.  */                                           \
 444   47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49,       \
 445   60, 61, 62, 63,                                                       \
 446   /* Call-saved FPRs.  */                                               \
 447   40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,                       \
 448   /* None of the remaining classes have defined call-saved              \
 449      registers.  */                                                     \
 450   64, 65                                                                \
 451 }
 452
 453 /* True if VALUE is a signed 12-bit number.  */
 454
 455 #define SMALL_OPERAND(VALUE) \
 456   ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
 457
 458 /* True if VALUE can be loaded into a register using LUI.  */
 459
 460 #define LUI_OPERAND(VALUE)                                              \
 461   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)       \
 462    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
 463
 464 /* Stack layout; function entry, exit and calling.  */
 465
 466 #define STACK_GROWS_DOWNWARD 1
 467
 468 #define FRAME_GROWS_DOWNWARD 1
 469
 470 #define RETURN_ADDR_RTX riscv_return_addr
 471
 472 #define ELIMINABLE_REGS                                                 \
 473 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 474  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 475  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 476  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}                            \
 477
 478 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 479   (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
 480
 481 /* Allocate stack space for arguments at the beginning of each function.  */
 482 #define ACCUMULATE_OUTGOING_ARGS 1
 483
 484 /* The argument pointer always points to the first argument.  */
 485 #define FIRST_PARM_OFFSET(FNDECL) 0
 486
 487 #define REG_PARM_STACK_SPACE(FNDECL) 0
 488
 489 /* Define this if it is the responsibility of the caller to
 490    allocate the area reserved for arguments passed in registers.
 491    If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
 492    of this macro is to determine whether the space is included in
 493    `crtl->outgoing_args_size'.  */
 494 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 495
 496 #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary
 497
 498 /* Symbolic macros for the registers used to return integer and floating
 499    point values.  */
 500
 501 #define GP_RETURN GP_ARG_FIRST
 502 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
 503
 504 #define MAX_ARGS_IN_REGISTERS (riscv_abi == ABI_ILP32E ? 6 : 8)
 505
 506 /* Symbolic macros for the first/last argument registers.  */
 507
 508 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
 509 #define GP_ARG_LAST  (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 510 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
 511 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
 512 #define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 513
 514 #define CALLEE_SAVED_REG_NUMBER(REGNO)                  \
 515   ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 :         \
 516    (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
 517
 518 #define LIBCALL_VALUE(MODE) \
 519   riscv_function_value (NULL_TREE, NULL_TREE, MODE)
 520
 521 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 522   riscv_function_value (VALTYPE, FUNC, VOIDmode)
 523
 524 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
 525
 526 /* 1 if N is a possible register number for function argument passing.
 527    We have no FP argument registers when soft-float.  */
 528
 529 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI.  */
 530 #define FUNCTION_ARG_REGNO_P(N)                                         \
 531   (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST)                            \
 532    || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
 533
 534 typedef struct {
 535   /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
 536   unsigned int num_gprs;
 537
 538   /* Number of floating-point registers used so far, likewise.  */
 539   unsigned int num_fprs;
 540 } CUMULATIVE_ARGS;
 541
 542 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 543    for a call to a function whose data type is FNTYPE.
 544    For a library call, FNTYPE is 0.  */
 545
 546 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 547   memset (&(CUM), 0, sizeof (CUM))
 548
 549 #define EPILOGUE_USES(REGNO)    riscv_epilogue_uses (REGNO)
 550
 551 /* Align based on stack boundary, which might have been set by the user.  */
 552 #define RISCV_STACK_ALIGN(LOC) \
 553   (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8))
 554
 555 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 556    the stack pointer does not matter.  The value is tested only in
 557    functions that have frame pointers.
 558    No definition is equivalent to always zero.  */
 559
 560 #define EXIT_IGNORE_STACK 1
 561
 562
 563 /* Trampolines are a block of code followed by two pointers.  */
 564
 565 #define TRAMPOLINE_CODE_SIZE 16
 566 #define TRAMPOLINE_SIZE         \
 567   ((Pmode == SImode)            \
 568    ? TRAMPOLINE_CODE_SIZE       \
 569    : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
 570 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
 571
 572 /* Addressing modes, and classification of registers for them.  */
 573
 574 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
 575 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
 576   riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
 577
 578 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 579    and check its validity for a certain class.
 580    We have two alternate definitions for each of them.
 581    The usual definition accepts all pseudo regs; the other rejects them all.
 582    The symbol REG_OK_STRICT causes the latter definition to be used.
 583
 584    Most source files want to accept pseudo regs in the hope that
 585    they will get allocated to the class that the insn wants them to be in.
 586    Some source files that are used after register allocation
 587    need to be strict.  */
 588
 589 #ifndef REG_OK_STRICT
 590 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 591   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
 592 #else
 593 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 594   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
 595 #endif
 596
 597 #define REG_OK_FOR_INDEX_P(X) 0
 598
 599 /* Maximum number of registers that can appear in a valid memory address.  */
 600
 601 #define MAX_REGS_PER_ADDRESS 1
 602
 603 #define CONSTANT_ADDRESS_P(X) \
 604   (CONSTANT_P (X) && memory_address_p (SImode, X))
 605
 606 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
 607    'the start of the function that this code is output in'.  */
 608
 609 #define ASM_OUTPUT_LABELREF(FILE,NAME)                                  \
 610   do {                                                                  \
 611     if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)                       \
 612       asm_fprintf ((FILE), "%U%s",                                      \
 613                    XSTR (XEXP (DECL_RTL (current_function_decl),        \
 614                                0), 0));                                 \
 615     else                                                                \
 616       asm_fprintf ((FILE), "%U%s", (NAME));                             \
 617   } while (0)
 618
 619 #define JUMP_TABLES_IN_TEXT_SECTION 0
 620 #define CASE_VECTOR_MODE SImode
 621 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
 622
 623 /* The load-address macro is used for PC-relative addressing of symbols
 624    that bind locally.  Don't use it for symbols that should be addressed
 625    via the GOT.  Also, avoid it for CM_MEDLOW, where LUI addressing
 626    currently results in more opportunities for linker relaxation.  */
 627 #define USE_LOAD_ADDRESS_MACRO(sym)                                     \
 628   (!TARGET_EXPLICIT_RELOCS &&                                           \
 629    ((flag_pic                                                           \
 630      && ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym))               \
 631          || ((GET_CODE (sym) == CONST)                                  \
 632              && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0))                   \
 633              && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0)))))          \
 634      || riscv_cmodel == CM_MEDANY))
 635
 636 /* Define this as 1 if `char' should by default be signed; else as 0.  */
 637 #define DEFAULT_SIGNED_CHAR 0
 638
 639 #define MOVE_MAX UNITS_PER_WORD
 640 #define MAX_MOVE_MAX 8
 641
 642 /* The SPARC port says:
 643    Nonzero if access to memory by bytes is slow and undesirable.
 644    For RISC chips, it means that access to memory by bytes is no
 645    better than access by words when possible, so grab a whole word
 646    and maybe make use of that.  */
 647 #define SLOW_BYTE_ACCESS 1
 648
 649 /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns
 650    in the md file instead.  */
 651 #define SHIFT_COUNT_TRUNCATED 0
 652
 653 /* Specify the machine mode that pointers have.
 654    After generation of rtl, the compiler makes no further distinction
 655    between pointers and any other objects of this machine mode.  */
 656
 657 #define Pmode word_mode
 658
 659 /* Give call MEMs SImode since it is the "most permissive" mode
 660    for both 32-bit and 64-bit targets.  */
 661
 662 #define FUNCTION_MODE SImode
 663
 664 /* A C expression for the cost of a branch instruction.  A value of 2
 665    seems to minimize code size.  */
 666
 667 #define BRANCH_COST(speed_p, predictable_p) \
 668   ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
 669
 670 /* True if the target optimizes short forward branches around integer
 671    arithmetic instructions into predicated operations, e.g., for
 672    conditional-move operations.  The macro assumes that all branch
 673    instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ)
 674    support this feature.  The macro further assumes that any integer
 675    arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I],
 676    SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed
 677    counterparts, including C.MV and C.LI) can be in the branch shadow.  */
 678
 679 #define TARGET_SFB_ALU (riscv_microarchitecture == sifive_7)
 680
 681 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 682
 683 /* Control the assembler format that we output.  */
 684
 685 /* Output to assembler file text saying following lines
 686    may contain character constants, extra white space, comments, etc.  */
 687
 688 #ifndef ASM_APP_ON
 689 #define ASM_APP_ON " #APP\n"
 690 #endif
 691
 692 /* Output to assembler file text saying following lines
 693    no longer contain unusual constructs.  */
 694
 695 #ifndef ASM_APP_OFF
 696 #define ASM_APP_OFF " #NO_APP\n"
 697 #endif
 698
 699 #define REGISTER_NAMES                                          \
 700 { "zero","ra",  "sp",  "gp",  "tp",  "t0",  "t1",  "t2",        \
 701   "s0",  "s1",  "a0",  "a1",  "a2",  "a3",  "a4",  "a5",        \
 702   "a6",  "a7",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",        \
 703   "s8",  "s9",  "s10", "s11", "t3",  "t4",  "t5",  "t6",        \
 704   "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",       \
 705   "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",       \
 706   "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",       \
 707   "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11",      \
 708   "arg", "frame", }
 709
 710 #define ADDITIONAL_REGISTER_NAMES                                       \
 711 {                                                                       \
 712   { "x0",        0 + GP_REG_FIRST },                                    \
 713   { "x1",        1 + GP_REG_FIRST },                                    \
 714   { "x2",        2 + GP_REG_FIRST },                                    \
 715   { "x3",        3 + GP_REG_FIRST },                                    \
 716   { "x4",        4 + GP_REG_FIRST },                                    \
 717   { "x5",        5 + GP_REG_FIRST },                                    \
 718   { "x6",        6 + GP_REG_FIRST },                                    \
 719   { "x7",        7 + GP_REG_FIRST },                                    \
 720   { "x8",        8 + GP_REG_FIRST },                                    \
 721   { "x9",        9 + GP_REG_FIRST },                                    \
 722   { "x10",      10 + GP_REG_FIRST },                                    \
 723   { "x11",      11 + GP_REG_FIRST },                                    \
 724   { "x12",      12 + GP_REG_FIRST },                                    \
 725   { "x13",      13 + GP_REG_FIRST },                                    \
 726   { "x14",      14 + GP_REG_FIRST },                                    \
 727   { "x15",      15 + GP_REG_FIRST },                                    \
 728   { "x16",      16 + GP_REG_FIRST },                                    \
 729   { "x17",      17 + GP_REG_FIRST },                                    \
 730   { "x18",      18 + GP_REG_FIRST },                                    \
 731   { "x19",      19 + GP_REG_FIRST },                                    \
 732   { "x20",      20 + GP_REG_FIRST },                                    \
 733   { "x21",      21 + GP_REG_FIRST },                                    \
 734   { "x22",      22 + GP_REG_FIRST },                                    \
 735   { "x23",      23 + GP_REG_FIRST },                                    \
 736   { "x24",      24 + GP_REG_FIRST },                                    \
 737   { "x25",      25 + GP_REG_FIRST },                                    \
 738   { "x26",      26 + GP_REG_FIRST },                                    \
 739   { "x27",      27 + GP_REG_FIRST },                                    \
 740   { "x28",      28 + GP_REG_FIRST },                                    \
 741   { "x29",      29 + GP_REG_FIRST },                                    \
 742   { "x30",      30 + GP_REG_FIRST },                                    \
 743   { "x31",      31 + GP_REG_FIRST },                                    \
 744   { "f0",        0 + FP_REG_FIRST },                                    \
 745   { "f1",        1 + FP_REG_FIRST },                                    \
 746   { "f2",        2 + FP_REG_FIRST },                                    \
 747   { "f3",        3 + FP_REG_FIRST },                                    \
 748   { "f4",        4 + FP_REG_FIRST },                                    \
 749   { "f5",        5 + FP_REG_FIRST },                                    \
 750   { "f6",        6 + FP_REG_FIRST },                                    \
 751   { "f7",        7 + FP_REG_FIRST },                                    \
 752   { "f8",        8 + FP_REG_FIRST },                                    \
 753   { "f9",        9 + FP_REG_FIRST },                                    \
 754   { "f10",      10 + FP_REG_FIRST },                                    \
 755   { "f11",      11 + FP_REG_FIRST },                                    \
 756   { "f12",      12 + FP_REG_FIRST },                                    \
 757   { "f13",      13 + FP_REG_FIRST },                                    \
 758   { "f14",      14 + FP_REG_FIRST },                                    \
 759   { "f15",      15 + FP_REG_FIRST },                                    \
 760   { "f16",      16 + FP_REG_FIRST },                                    \
 761   { "f17",      17 + FP_REG_FIRST },                                    \
 762   { "f18",      18 + FP_REG_FIRST },                                    \
 763   { "f19",      19 + FP_REG_FIRST },                                    \
 764   { "f20",      20 + FP_REG_FIRST },                                    \
 765   { "f21",      21 + FP_REG_FIRST },                                    \
 766   { "f22",      22 + FP_REG_FIRST },                                    \
 767   { "f23",      23 + FP_REG_FIRST },                                    \
 768   { "f24",      24 + FP_REG_FIRST },                                    \
 769   { "f25",      25 + FP_REG_FIRST },                                    \
 770   { "f26",      26 + FP_REG_FIRST },                                    \
 771   { "f27",      27 + FP_REG_FIRST },                                    \
 772   { "f28",      28 + FP_REG_FIRST },                                    \
 773   { "f29",      29 + FP_REG_FIRST },                                    \
 774   { "f30",      30 + FP_REG_FIRST },                                    \
 775   { "f31",      31 + FP_REG_FIRST },                                    \
 776 }
 777
 778 /* Globalizing directive for a label.  */
 779 #define GLOBAL_ASM_OP "\t.globl\t"
 780
 781 /* This is how to store into the string LABEL
 782    the symbol_ref name of an internal numbered label where
 783    PREFIX is the class of label and NUM is the number within the class.
 784    This is suitable for output with `assemble_name'.  */
 785
 786 #undef ASM_GENERATE_INTERNAL_LABEL
 787 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 788   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
 789
 790 /* This is how to output an element of a case-vector that is absolute.  */
 791
 792 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 793   fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
 794
 795 /* This is how to output an element of a PIC case-vector. */
 796
 797 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 798   fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n",                            \
 799            LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
 800
 801 /* This is how to output an assembler line
 802    that says to advance the location counter
 803    to a multiple of 2**LOG bytes.  */
 804
 805 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 806   fprintf (STREAM, "\t.align\t%d\n", (LOG))
 807
 808 /* Define the strings to put out for each section in the object file.  */
 809 #define TEXT_SECTION_ASM_OP     "\t.text"       /* instructions */
 810 #define DATA_SECTION_ASM_OP     "\t.data"       /* large data */
 811 #define READONLY_DATA_SECTION_ASM_OP    "\t.section\t.rodata"
 812 #define BSS_SECTION_ASM_OP      "\t.bss"
 813 #define SBSS_SECTION_ASM_OP     "\t.section\t.sbss,\"aw\",@nobits"
 814 #define SDATA_SECTION_ASM_OP    "\t.section\t.sdata,\"aw\",@progbits"
 815
 816 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)                               \
 817 do                                                                      \
 818   {                                                                     \
 819     fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n",              \
 820              reg_names[STACK_POINTER_REGNUM],                           \
 821              reg_names[STACK_POINTER_REGNUM],                           \
 822              TARGET_64BIT ? "sd" : "sw",                                \
 823              reg_names[REGNO],                                          \
 824              reg_names[STACK_POINTER_REGNUM]);                          \
 825   }                                                                     \
 826 while (0)
 827
 828 #define ASM_OUTPUT_REG_POP(STREAM,REGNO)                                \
 829 do                                                                      \
 830   {                                                                     \
 831     fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n",               \
 832              TARGET_64BIT ? "ld" : "lw",                                \
 833              reg_names[REGNO],                                          \
 834              reg_names[STACK_POINTER_REGNUM],                           \
 835              reg_names[STACK_POINTER_REGNUM],                           \
 836              reg_names[STACK_POINTER_REGNUM]);                          \
 837   }                                                                     \
 838 while (0)
 839
 840 #define ASM_COMMENT_START "#"
 841
 842 #undef SIZE_TYPE
 843 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
 844
 845 #undef PTRDIFF_TYPE
 846 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
 847
 848 /* The maximum number of bytes copied by one iteration of a cpymemsi loop.  */
 849
 850 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4)
 851
 852 /* The maximum number of bytes that can be copied by a straight-line
 853    cpymemsi implementation.  */
 854
 855 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3)
 856
 857 /* If a memory-to-memory move would take MOVE_RATIO or more simple
 858    move-instruction pairs, we will do a cpymem or libcall instead.
 859    Do not use move_by_pieces at all when strict alignment is not
 860    in effect but the target has slow unaligned accesses; in this
 861    case, cpymem or libcall is more efficient.  */
 862
 863 #define MOVE_RATIO(speed)                                               \
 864   (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 :             \
 865    (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD :      \
 866    CLEAR_RATIO (speed) / 2)
 867
 868 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
 869    of the length of a memset call, but use the default otherwise.  */
 870
 871 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
 872
 873 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
 874    optimizing for size adjust the ratio to account for the overhead of
 875    loading the constant and replicating it across the word.  */
 876
 877 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
 878
 879 #ifndef USED_FOR_TARGET
 880 extern const enum reg_class riscv_regno_to_class[];
 881 extern bool riscv_slow_unaligned_access_p;
 882 extern unsigned riscv_stack_boundary;
 883 #endif
 884
 885 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 886   (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
 887
 888 #define XLEN_SPEC \
 889   "%{march=rv32*:32}" \
 890   "%{march=rv64*:64}" \
 891
 892 #define ABI_SPEC \
 893   "%{mabi=ilp32:ilp32}" \
 894   "%{mabi=ilp32e:ilp32e}" \
 895   "%{mabi=ilp32f:ilp32f}" \
 896   "%{mabi=ilp32d:ilp32d}" \
 897   "%{mabi=lp64:lp64}" \
 898   "%{mabi=lp64f:lp64f}" \
 899   "%{mabi=lp64d:lp64d}" \
 900
 901 /* ISA constants needed for code generation.  */
 902 #define OPCODE_LW    0x2003
 903 #define OPCODE_LD    0x3003
 904 #define OPCODE_AUIPC 0x17
 905 #define OPCODE_JALR  0x67
 906 #define OPCODE_LUI   0x37
 907 #define OPCODE_ADDI  0x13
 908 #define SHIFT_RD  7
 909 #define SHIFT_RS1 15
 910 #define SHIFT_IMM 20
 911 #define IMM_BITS 12
 912 #define C_SxSP_BITS 6
 913
 914 #define IMM_REACH (1LL << IMM_BITS)
 915 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
 916 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
 917
 918 #define SWSP_REACH (4LL << C_SxSP_BITS)
 919 #define SDSP_REACH (8LL << C_SxSP_BITS)
 920
 921 #endif /* ! GCC_RISCV_H */