gcc/config/riscv/riscv.h

   1 /* Definition of RISC-V target for GNU compiler.
   2    Copyright (C) 2011-2017 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4    Based on MIPS target for GNU compiler.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3, or (at your option)
  11 any later version.
  12
  13 GCC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_RISCV_H
  23 #define GCC_RISCV_H
  24
  25 #include "config/riscv/riscv-opts.h"
  26
  27 /* Target CPU builtins.  */
  28 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
  29
  30 /* Default target_flags if no switches are specified  */
  31
  32 #ifndef TARGET_DEFAULT
  33 #define TARGET_DEFAULT 0
  34 #endif
  35
  36 #ifndef RISCV_TUNE_STRING_DEFAULT
  37 #define RISCV_TUNE_STRING_DEFAULT "rocket"
  38 #endif
  39
  40 /* Support for a compile-time default CPU, et cetera.  The rules are:
  41    --with-arch is ignored if -march is specified.
  42    --with-abi is ignored if -mabi is specified.
  43    --with-tune is ignored if -mtune is specified.  */
  44 #define OPTION_DEFAULT_SPECS \
  45   {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
  46   {"arch", "%{!march=*:-march=%(VALUE)}" }, \
  47   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
  48
  49 #ifdef IN_LIBGCC2
  50 #undef TARGET_64BIT
  51 /* Make this compile time constant for libgcc2 */
  52 #define TARGET_64BIT           (__riscv_xlen == 64)
  53 #endif /* IN_LIBGCC2 */
  54
  55 #undef ASM_SPEC
  56 #define ASM_SPEC "\
  57 %(subtarget_asm_debugging_spec) \
  58 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
  59 %{march=*} \
  60 %{mabi=*} \
  61 %(subtarget_asm_spec)"
  62
  63 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
  64
  65 #define LOCAL_LABEL_PREFIX      "."
  66 #define USER_LABEL_PREFIX       ""
  67
  68 /* Offsets recorded in opcodes are a multiple of this alignment factor.
  69    The default for this in 64-bit mode is 8, which causes problems with
  70    SFmode register saves.  */
  71 #define DWARF_CIE_DATA_ALIGNMENT -4
  72
  73 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
  74 #define DWARF_FRAME_REGNUM(REGNO) \
  75   (GP_REG_P (REGNO) || FP_REG_P (REGNO) ? REGNO : INVALID_REGNUM)
  76
  77 /* The DWARF 2 CFA column which tracks the return address.  */
  78 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
  79 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
  80
  81 /* Describe how we implement __builtin_eh_return.  */
  82 #define EH_RETURN_DATA_REGNO(N) \
  83   ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
  84
  85 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
  86
  87 /* Target machine storage layout */
  88
  89 #define BITS_BIG_ENDIAN 0
  90 #define BYTES_BIG_ENDIAN 0
  91 #define WORDS_BIG_ENDIAN 0
  92
  93 #define MAX_BITS_PER_WORD 64
  94
  95 /* Width of a word, in units (bytes).  */
  96 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
  97 #ifndef IN_LIBGCC2
  98 #define MIN_UNITS_PER_WORD 4
  99 #endif
 100
 101 /* The `Q' extension is not yet supported.  */
 102 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
 103
 104 /* The largest type that can be passed in floating-point registers.  */
 105 #define UNITS_PER_FP_ARG                                        \
 106   (riscv_abi == ABI_ILP32 || riscv_abi == ABI_LP64 ? 0 :        \
 107    riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F ? 4 : 8)   \
 108
 109 /* Set the sizes of the core types.  */
 110 #define SHORT_TYPE_SIZE 16
 111 #define INT_TYPE_SIZE 32
 112 #define LONG_LONG_TYPE_SIZE 64
 113 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
 114 #define LONG_TYPE_SIZE POINTER_SIZE
 115
 116 #define FLOAT_TYPE_SIZE 32
 117 #define DOUBLE_TYPE_SIZE 64
 118 #define LONG_DOUBLE_TYPE_SIZE 128
 119
 120 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 121 #define PARM_BOUNDARY BITS_PER_WORD
 122
 123 /* Allocation boundary (in *bits*) for the code of a function.  */
 124 #define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
 125
 126 /* There is no point aligning anything to a rounder boundary than this.  */
 127 #define BIGGEST_ALIGNMENT 128
 128
 129 /* The user-level ISA permits unaligned accesses, but they are not required
 130    of the privileged architecture.  */
 131 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
 132
 133 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) riscv_slow_unaligned_access
 134
 135 /* Define this if you wish to imitate the way many other C compilers
 136    handle alignment of bitfields and the structures that contain
 137    them.
 138
 139    The behavior is that the type written for a bit-field (`int',
 140    `short', or other integer type) imposes an alignment for the
 141    entire structure, as if the structure really did contain an
 142    ordinary field of that type.  In addition, the bit-field is placed
 143    within the structure so that it would fit within such a field,
 144    not crossing a boundary for it.
 145
 146    Thus, on most machines, a bit-field whose type is written as `int'
 147    would not cross a four-byte boundary, and would force four-byte
 148    alignment for the whole structure.  (The alignment used may not
 149    be four bytes; it is controlled by the other alignment
 150    parameters.)
 151
 152    If the macro is defined, its definition should be a C expression;
 153    a nonzero value for the expression enables this behavior.  */
 154
 155 #define PCC_BITFIELD_TYPE_MATTERS 1
 156
 157 /* If defined, a C expression to compute the alignment given to a
 158    constant that is being placed in memory.  CONSTANT is the constant
 159    and ALIGN is the alignment that the object would ordinarily have.
 160    The value of this macro is used instead of that alignment to align
 161    the object.
 162
 163    If this macro is not defined, then ALIGN is used.
 164
 165    The typical use of this macro is to increase alignment for string
 166    constants to be word aligned so that `strcpy' calls that copy
 167    constants can be done inline.  */
 168
 169 #define CONSTANT_ALIGNMENT(EXP, ALIGN)                                  \
 170   ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)   \
 171    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
 172
 173 /* If defined, a C expression to compute the alignment for a static
 174    variable.  TYPE is the data type, and ALIGN is the alignment that
 175    the object would ordinarily have.  The value of this macro is used
 176    instead of that alignment to align the object.
 177
 178    If this macro is not defined, then ALIGN is used.
 179
 180    One use of this macro is to increase alignment of medium-size
 181    data to make it all fit in fewer cache lines.  Another is to
 182    cause character arrays to be word-aligned so that `strcpy' calls
 183    that copy constants to character arrays can be done inline.  */
 184
 185 #define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
 186   ((((ALIGN) < BITS_PER_WORD)                                           \
 187     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 188         || TREE_CODE (TYPE) == UNION_TYPE                               \
 189         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 190
 191 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
 192    character arrays to be word-aligned so that `strcpy' calls that copy
 193    constants to character arrays can be done inline, and 'strcmp' can be
 194    optimised to use word loads. */
 195 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
 196   DATA_ALIGNMENT (TYPE, ALIGN)
 197
 198 /* Define if operations between registers always perform the operation
 199    on the full register even if a narrower mode is specified.  */
 200 #define WORD_REGISTER_OPERATIONS 1
 201
 202 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
 203    moves.  All other references are zero extended.  */
 204 #define LOAD_EXTEND_OP(MODE) \
 205   (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
 206
 207 /* Define this macro if it is advisable to hold scalars in registers
 208    in a wider mode than that declared by the program.  In such cases,
 209    the value is constrained to be within the bounds of the declared
 210    type, but kept valid in the wider mode.  The signedness of the
 211    extension may differ from that of the type.  */
 212
 213 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
 214   if (GET_MODE_CLASS (MODE) == MODE_INT         \
 215       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
 216     {                                           \
 217       if ((MODE) == SImode)                     \
 218         (UNSIGNEDP) = 0;                        \
 219       (MODE) = word_mode;                       \
 220     }
 221
 222 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
 223    Extensions of pointers to word_mode must be signed.  */
 224 #define POINTERS_EXTEND_UNSIGNED false
 225
 226 /* When floating-point registers are wider than integer ones, moves between
 227    them must go through memory.  */
 228 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE)     \
 229   (GET_MODE_SIZE (MODE) > UNITS_PER_WORD                \
 230    && ((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS))
 231
 232 /* Define if loading short immediate values into registers sign extends.  */
 233 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
 234
 235 /* Standard register usage.  */
 236
 237 /* Number of hardware registers.  We have:
 238
 239    - 32 integer registers
 240    - 32 floating point registers
 241    - 2 fake registers:
 242         - ARG_POINTER_REGNUM
 243         - FRAME_POINTER_REGNUM */
 244
 245 #define FIRST_PSEUDO_REGISTER 66
 246
 247 /* x0, sp, gp, and tp are fixed.  */
 248
 249 #define FIXED_REGISTERS                                                 \
 250 { /* General registers.  */                                             \
 251   1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 252   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 253   /* Floating-point registers.  */                                      \
 254   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 255   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 256   /* Others.  */                                                        \
 257   1, 1                                                                  \
 258 }
 259
 260 /* a0-a7, t0-a6, fa0-fa7, and ft0-ft11 are volatile across calls.
 261    The call RTLs themselves clobber ra.  */
 262
 263 #define CALL_USED_REGISTERS                                             \
 264 { /* General registers.  */                                             \
 265   1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 266   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 267   /* Floating-point registers.  */                                      \
 268   1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 269   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 270   /* Others.  */                                                        \
 271   1, 1                                                                  \
 272 }
 273
 274 /* Internal macros to classify an ISA register's type.  */
 275
 276 #define GP_REG_FIRST 0
 277 #define GP_REG_LAST  31
 278 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 279
 280 #define FP_REG_FIRST 32
 281 #define FP_REG_LAST  63
 282 #define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
 283
 284 /* The DWARF 2 CFA column which tracks the return address from a
 285    signal handler context.  This means that to maintain backwards
 286    compatibility, no hard register can be assigned this column if it
 287    would need to be handled by the DWARF unwinder.  */
 288 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
 289
 290 #define GP_REG_P(REGNO) \
 291   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 292 #define FP_REG_P(REGNO)  \
 293   ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
 294
 295 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
 296
 297 #define HARD_REGNO_NREGS(REGNO, MODE) riscv_hard_regno_nregs (REGNO, MODE)
 298
 299 #define HARD_REGNO_MODE_OK(REGNO, MODE)                                 \
 300   riscv_hard_regno_mode_ok_p (REGNO, MODE)
 301
 302 /* Don't allow floating-point modes to be tied, since type punning of
 303    single-precision and double-precision is implementation defined.  */
 304 #define MODES_TIEABLE_P(MODE1, MODE2)                   \
 305   ((MODE1) == (MODE2)                                   \
 306    || !(GET_MODE_CLASS (MODE1) == MODE_FLOAT            \
 307         && GET_MODE_CLASS (MODE2) == MODE_FLOAT))
 308
 309 /* Use s0 as the frame pointer if it is so requested.  */
 310 #define HARD_FRAME_POINTER_REGNUM 8
 311 #define STACK_POINTER_REGNUM 2
 312 #define THREAD_POINTER_REGNUM 4
 313
 314 /* These two registers don't really exist: they get eliminated to either
 315    the stack or hard frame pointer.  */
 316 #define ARG_POINTER_REGNUM 64
 317 #define FRAME_POINTER_REGNUM 65
 318
 319 /* Register in which static-chain is passed to a function.  */
 320 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
 321
 322 /* Registers used as temporaries in prologue/epilogue code.
 323
 324    The prologue registers mustn't conflict with any
 325    incoming arguments, the static chain pointer, or the frame pointer.
 326    The epilogue temporary mustn't conflict with the return registers,
 327    the frame pointer, the EH stack adjustment, or the EH data registers. */
 328
 329 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST + 1)
 330 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
 331
 332 #define MCOUNT_NAME "_mcount"
 333
 334 #define NO_PROFILE_COUNTERS 1
 335
 336 /* Emit rtl for profiling.  Output assembler code to FILE
 337    to call "_mcount" for profiling a function entry.  */
 338 #define PROFILE_HOOK(LABEL)                                             \
 339   {                                                                     \
 340     rtx fun, ra;                                                        \
 341     ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);          \
 342     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 343     emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, ra, Pmode);        \
 344   }
 345
 346 /* All the work done in PROFILE_HOOK, but still required.  */
 347 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 348
 349 /* Define this macro if it is as good or better to call a constant
 350    function address than to call an address kept in a register.  */
 351 #define NO_FUNCTION_CSE 1
 352
 353 /* Define the classes of registers for register constraints in the
 354    machine description.  Also define ranges of constants.
 355
 356    One of the classes must always be named ALL_REGS and include all hard regs.
 357    If there is more than one class, another class must be named NO_REGS
 358    and contain no registers.
 359
 360    The name GENERAL_REGS must be the name of a class (or an alias for
 361    another name such as ALL_REGS).  This is the class of registers
 362    that is allowed by "g" or "r" in a register constraint.
 363    Also, registers outside this class are allocated only when
 364    instructions express preferences for them.
 365
 366    The classes must be numbered in nondecreasing order; that is,
 367    a larger-numbered class must never be contained completely
 368    in a smaller-numbered class.
 369
 370    For any two classes, it is very desirable that there be another
 371    class that represents their union.  */
 372
 373 enum reg_class
 374 {
 375   NO_REGS,                      /* no registers in set */
 376   SIBCALL_REGS,                 /* registers used by indirect sibcalls */
 377   JALR_REGS,                    /* registers used by indirect calls */
 378   GR_REGS,                      /* integer registers */
 379   FP_REGS,                      /* floating-point registers */
 380   FRAME_REGS,                   /* arg pointer and frame pointer */
 381   ALL_REGS,                     /* all registers */
 382   LIM_REG_CLASSES               /* max value + 1 */
 383 };
 384
 385 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 386
 387 #define GENERAL_REGS GR_REGS
 388
 389 /* An initializer containing the names of the register classes as C
 390    string constants.  These names are used in writing some of the
 391    debugging dumps.  */
 392
 393 #define REG_CLASS_NAMES                                                 \
 394 {                                                                       \
 395   "NO_REGS",                                                            \
 396   "SIBCALL_REGS",                                                       \
 397   "JALR_REGS",                                                          \
 398   "GR_REGS",                                                            \
 399   "FP_REGS",                                                            \
 400   "FRAME_REGS",                                                         \
 401   "ALL_REGS"                                                            \
 402 }
 403
 404 /* An initializer containing the contents of the register classes,
 405    as integers which are bit masks.  The Nth integer specifies the
 406    contents of class N.  The way the integer MASK is interpreted is
 407    that register R is in the class if `MASK & (1 << R)' is 1.
 408
 409    When the machine has more than 32 registers, an integer does not
 410    suffice.  Then the integers are replaced by sub-initializers,
 411    braced groupings containing several integers.  Each
 412    sub-initializer must be suitable as an initializer for the type
 413    `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
 414
 415 #define REG_CLASS_CONTENTS                                              \
 416 {                                                                       \
 417   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 418   { 0xf00000c0, 0x00000000, 0x00000000 },       /* SIBCALL_REGS */      \
 419   { 0xffffffc0, 0x00000000, 0x00000000 },       /* JALR_REGS */         \
 420   { 0xffffffff, 0x00000000, 0x00000000 },       /* GR_REGS */           \
 421   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS */           \
 422   { 0x00000000, 0x00000000, 0x00000003 },       /* FRAME_REGS */        \
 423   { 0xffffffff, 0xffffffff, 0x00000003 }        /* ALL_REGS */          \
 424 }
 425
 426 /* A C expression whose value is a register class containing hard
 427    register REGNO.  In general there is more that one such class;
 428    choose a class which is "minimal", meaning that no smaller class
 429    also contains the register.  */
 430
 431 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
 432
 433 /* A macro whose definition is the name of the class to which a
 434    valid base register must belong.  A base register is one used in
 435    an address which is the register value plus a displacement.  */
 436
 437 #define BASE_REG_CLASS GR_REGS
 438
 439 /* A macro whose definition is the name of the class to which a
 440    valid index register must belong.  An index register is one used
 441    in an address where its value is either multiplied by a scale
 442    factor or added to another register (as well as added to a
 443    displacement).  */
 444
 445 #define INDEX_REG_CLASS NO_REGS
 446
 447 /* We generally want to put call-clobbered registers ahead of
 448    call-saved ones.  (IRA expects this.)  */
 449
 450 #define REG_ALLOC_ORDER                                                 \
 451 { \
 452   /* Call-clobbered GPRs.  */                                           \
 453   15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1,           \
 454   /* Call-saved GPRs.  */                                               \
 455   8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,                         \
 456   /* GPRs that can never be exposed to the register allocator.  */      \
 457   0, 2, 3, 4,                                                           \
 458   /* Call-clobbered FPRs.  */                                           \
 459   47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49,       \
 460   60, 61, 62, 63,                                                       \
 461   /* Call-saved FPRs.  */                                               \
 462   40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,                       \
 463   /* None of the remaining classes have defined call-saved              \
 464      registers.  */                                                     \
 465   64, 65                                                                \
 466 }
 467
 468 /* True if VALUE is a signed 12-bit number.  */
 469
 470 #define SMALL_OPERAND(VALUE) \
 471   ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
 472
 473 /* True if VALUE can be loaded into a register using LUI.  */
 474
 475 #define LUI_OPERAND(VALUE)                                              \
 476   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)       \
 477    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
 478
 479 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
 480   reg_classes_intersect_p (FP_REGS, CLASS)
 481
 482 /* Stack layout; function entry, exit and calling.  */
 483
 484 #define STACK_GROWS_DOWNWARD 1
 485
 486 #define FRAME_GROWS_DOWNWARD 1
 487
 488 #define STARTING_FRAME_OFFSET 0
 489
 490 #define RETURN_ADDR_RTX riscv_return_addr
 491
 492 #define ELIMINABLE_REGS                                                 \
 493 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 494  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 495  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 496  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}                            \
 497
 498 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 499   (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
 500
 501 /* Allocate stack space for arguments at the beginning of each function.  */
 502 #define ACCUMULATE_OUTGOING_ARGS 1
 503
 504 /* The argument pointer always points to the first argument.  */
 505 #define FIRST_PARM_OFFSET(FNDECL) 0
 506
 507 #define REG_PARM_STACK_SPACE(FNDECL) 0
 508
 509 /* Define this if it is the responsibility of the caller to
 510    allocate the area reserved for arguments passed in registers.
 511    If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
 512    of this macro is to determine whether the space is included in
 513    `crtl->outgoing_args_size'.  */
 514 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 515
 516 #define STACK_BOUNDARY 128
 517 \f
 518 /* Symbolic macros for the registers used to return integer and floating
 519    point values.  */
 520
 521 #define GP_RETURN GP_ARG_FIRST
 522 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
 523
 524 #define MAX_ARGS_IN_REGISTERS 8
 525
 526 /* Symbolic macros for the first/last argument registers.  */
 527
 528 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
 529 #define GP_ARG_LAST  (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 530 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
 531 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
 532 #define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 533
 534 #define CALLEE_SAVED_REG_NUMBER(REGNO)                  \
 535   ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 :         \
 536    (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
 537
 538 #define LIBCALL_VALUE(MODE) \
 539   riscv_function_value (NULL_TREE, NULL_TREE, MODE)
 540
 541 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 542   riscv_function_value (VALTYPE, FUNC, VOIDmode)
 543
 544 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
 545
 546 /* 1 if N is a possible register number for function argument passing.
 547    We have no FP argument registers when soft-float.  When FP registers
 548    are 32 bits, we can't directly reference the odd numbered ones.  */
 549
 550 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI.  */
 551 #define FUNCTION_ARG_REGNO_P(N)                                         \
 552   (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST)                            \
 553    || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
 554
 555 typedef struct {
 556   /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
 557   unsigned int num_gprs;
 558
 559   /* Number of floating-point registers used so far, likewise.  */
 560   unsigned int num_fprs;
 561 } CUMULATIVE_ARGS;
 562
 563 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 564    for a call to a function whose data type is FNTYPE.
 565    For a library call, FNTYPE is 0.  */
 566
 567 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 568   memset (&(CUM), 0, sizeof (CUM))
 569
 570 #define EPILOGUE_USES(REGNO)    ((REGNO) == RETURN_ADDR_REGNUM)
 571
 572 /* ABI requires 16-byte alignment, even on RV32. */
 573 #define RISCV_STACK_ALIGN(LOC) (((LOC) + 15) & -16)
 574
 575 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 576    the stack pointer does not matter.  The value is tested only in
 577    functions that have frame pointers.
 578    No definition is equivalent to always zero.  */
 579
 580 #define EXIT_IGNORE_STACK 1
 581
 582
 583 /* Trampolines are a block of code followed by two pointers.  */
 584
 585 #define TRAMPOLINE_CODE_SIZE 16
 586 #define TRAMPOLINE_SIZE         \
 587   ((Pmode == SImode)            \
 588    ? TRAMPOLINE_CODE_SIZE       \
 589    : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
 590 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
 591
 592 /* Addressing modes, and classification of registers for them.  */
 593
 594 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
 595 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
 596   riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
 597
 598 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 599    and check its validity for a certain class.
 600    We have two alternate definitions for each of them.
 601    The usual definition accepts all pseudo regs; the other rejects them all.
 602    The symbol REG_OK_STRICT causes the latter definition to be used.
 603
 604    Most source files want to accept pseudo regs in the hope that
 605    they will get allocated to the class that the insn wants them to be in.
 606    Some source files that are used after register allocation
 607    need to be strict.  */
 608
 609 #ifndef REG_OK_STRICT
 610 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 611   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
 612 #else
 613 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 614   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
 615 #endif
 616
 617 #define REG_OK_FOR_INDEX_P(X) 0
 618
 619 /* Maximum number of registers that can appear in a valid memory address.  */
 620
 621 #define MAX_REGS_PER_ADDRESS 1
 622
 623 #define CONSTANT_ADDRESS_P(X) \
 624   (CONSTANT_P (X) && memory_address_p (SImode, X))
 625
 626 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
 627    'the start of the function that this code is output in'.  */
 628
 629 #define ASM_OUTPUT_LABELREF(FILE,NAME)  \
 630   if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)                         \
 631     asm_fprintf ((FILE), "%U%s",                                        \
 632                  XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
 633   else                                                                  \
 634     asm_fprintf ((FILE), "%U%s", (NAME))
 635
 636 #define JUMP_TABLES_IN_TEXT_SECTION 0
 637 #define CASE_VECTOR_MODE SImode
 638 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
 639
 640 /* The load-address macro is used for PC-relative addressing of symbols
 641    that bind locally.  Don't use it for symbols that should be addressed
 642    via the GOT.  Also, avoid it for CM_MEDLOW, where LUI addressing
 643    currently results in more opportunities for linker relaxation.  */
 644 #define USE_LOAD_ADDRESS_MACRO(sym)                                     \
 645   (!TARGET_EXPLICIT_RELOCS &&                                           \
 646    ((flag_pic                                                           \
 647      && ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym))               \
 648          || ((GET_CODE (sym) == CONST)                                  \
 649              && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0))                   \
 650              && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0)))))          \
 651      || riscv_cmodel == CM_MEDANY))
 652
 653 /* Define this as 1 if `char' should by default be signed; else as 0.  */
 654 #define DEFAULT_SIGNED_CHAR 0
 655
 656 #define MOVE_MAX UNITS_PER_WORD
 657 #define MAX_MOVE_MAX 8
 658
 659 #define SLOW_BYTE_ACCESS 0
 660
 661 #define SHIFT_COUNT_TRUNCATED 1
 662
 663 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 664
 665 /* Specify the machine mode that pointers have.
 666    After generation of rtl, the compiler makes no further distinction
 667    between pointers and any other objects of this machine mode.  */
 668
 669 #define Pmode word_mode
 670
 671 /* Give call MEMs SImode since it is the "most permissive" mode
 672    for both 32-bit and 64-bit targets.  */
 673
 674 #define FUNCTION_MODE SImode
 675
 676 /* A C expression for the cost of a branch instruction.  A value of 2
 677    seems to minimize code size.  */
 678
 679 #define BRANCH_COST(speed_p, predictable_p) \
 680   ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
 681
 682 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 683
 684 /* Control the assembler format that we output.  */
 685
 686 /* Output to assembler file text saying following lines
 687    may contain character constants, extra white space, comments, etc.  */
 688
 689 #ifndef ASM_APP_ON
 690 #define ASM_APP_ON " #APP\n"
 691 #endif
 692
 693 /* Output to assembler file text saying following lines
 694    no longer contain unusual constructs.  */
 695
 696 #ifndef ASM_APP_OFF
 697 #define ASM_APP_OFF " #NO_APP\n"
 698 #endif
 699
 700 #define REGISTER_NAMES                                          \
 701 { "zero","ra",  "sp",  "gp",  "tp",  "t0",  "t1",  "t2",        \
 702   "s0",  "s1",  "a0",  "a1",  "a2",  "a3",  "a4",  "a5",        \
 703   "a6",  "a7",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",        \
 704   "s8",  "s9",  "s10", "s11", "t3",  "t4",  "t5",  "t6",        \
 705   "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",       \
 706   "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",       \
 707   "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",       \
 708   "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11",      \
 709   "arg", "frame", }
 710
 711 #define ADDITIONAL_REGISTER_NAMES                                       \
 712 {                                                                       \
 713   { "x0",        0 + GP_REG_FIRST },                                    \
 714   { "x1",        1 + GP_REG_FIRST },                                    \
 715   { "x2",        2 + GP_REG_FIRST },                                    \
 716   { "x3",        3 + GP_REG_FIRST },                                    \
 717   { "x4",        4 + GP_REG_FIRST },                                    \
 718   { "x5",        5 + GP_REG_FIRST },                                    \
 719   { "x6",        6 + GP_REG_FIRST },                                    \
 720   { "x7",        7 + GP_REG_FIRST },                                    \
 721   { "x8",        8 + GP_REG_FIRST },                                    \
 722   { "x9",        9 + GP_REG_FIRST },                                    \
 723   { "x10",      10 + GP_REG_FIRST },                                    \
 724   { "x11",      11 + GP_REG_FIRST },                                    \
 725   { "x12",      12 + GP_REG_FIRST },                                    \
 726   { "x13",      13 + GP_REG_FIRST },                                    \
 727   { "x14",      14 + GP_REG_FIRST },                                    \
 728   { "x15",      15 + GP_REG_FIRST },                                    \
 729   { "x16",      16 + GP_REG_FIRST },                                    \
 730   { "x17",      17 + GP_REG_FIRST },                                    \
 731   { "x18",      18 + GP_REG_FIRST },                                    \
 732   { "x19",      19 + GP_REG_FIRST },                                    \
 733   { "x20",      20 + GP_REG_FIRST },                                    \
 734   { "x21",      21 + GP_REG_FIRST },                                    \
 735   { "x22",      22 + GP_REG_FIRST },                                    \
 736   { "x23",      23 + GP_REG_FIRST },                                    \
 737   { "x24",      24 + GP_REG_FIRST },                                    \
 738   { "x25",      25 + GP_REG_FIRST },                                    \
 739   { "x26",      26 + GP_REG_FIRST },                                    \
 740   { "x27",      27 + GP_REG_FIRST },                                    \
 741   { "x28",      28 + GP_REG_FIRST },                                    \
 742   { "x29",      29 + GP_REG_FIRST },                                    \
 743   { "x30",      30 + GP_REG_FIRST },                                    \
 744   { "x31",      31 + GP_REG_FIRST },                                    \
 745   { "f0",        0 + FP_REG_FIRST },                                    \
 746   { "f1",        1 + FP_REG_FIRST },                                    \
 747   { "f2",        2 + FP_REG_FIRST },                                    \
 748   { "f3",        3 + FP_REG_FIRST },                                    \
 749   { "f4",        4 + FP_REG_FIRST },                                    \
 750   { "f5",        5 + FP_REG_FIRST },                                    \
 751   { "f6",        6 + FP_REG_FIRST },                                    \
 752   { "f7",        7 + FP_REG_FIRST },                                    \
 753   { "f8",        8 + FP_REG_FIRST },                                    \
 754   { "f9",        9 + FP_REG_FIRST },                                    \
 755   { "f10",      10 + FP_REG_FIRST },                                    \
 756   { "f11",      11 + FP_REG_FIRST },                                    \
 757   { "f12",      12 + FP_REG_FIRST },                                    \
 758   { "f13",      13 + FP_REG_FIRST },                                    \
 759   { "f14",      14 + FP_REG_FIRST },                                    \
 760   { "f15",      15 + FP_REG_FIRST },                                    \
 761   { "f16",      16 + FP_REG_FIRST },                                    \
 762   { "f17",      17 + FP_REG_FIRST },                                    \
 763   { "f18",      18 + FP_REG_FIRST },                                    \
 764   { "f19",      19 + FP_REG_FIRST },                                    \
 765   { "f20",      20 + FP_REG_FIRST },                                    \
 766   { "f21",      21 + FP_REG_FIRST },                                    \
 767   { "f22",      22 + FP_REG_FIRST },                                    \
 768   { "f23",      23 + FP_REG_FIRST },                                    \
 769   { "f24",      24 + FP_REG_FIRST },                                    \
 770   { "f25",      25 + FP_REG_FIRST },                                    \
 771   { "f26",      26 + FP_REG_FIRST },                                    \
 772   { "f27",      27 + FP_REG_FIRST },                                    \
 773   { "f28",      28 + FP_REG_FIRST },                                    \
 774   { "f29",      29 + FP_REG_FIRST },                                    \
 775   { "f30",      30 + FP_REG_FIRST },                                    \
 776   { "f31",      31 + FP_REG_FIRST },                                    \
 777 }
 778
 779 /* Globalizing directive for a label.  */
 780 #define GLOBAL_ASM_OP "\t.globl\t"
 781
 782 /* This is how to store into the string LABEL
 783    the symbol_ref name of an internal numbered label where
 784    PREFIX is the class of label and NUM is the number within the class.
 785    This is suitable for output with `assemble_name'.  */
 786
 787 #undef ASM_GENERATE_INTERNAL_LABEL
 788 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 789   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
 790
 791 /* This is how to output an element of a case-vector that is absolute.  */
 792
 793 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 794   fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
 795
 796 /* This is how to output an element of a PIC case-vector. */
 797
 798 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 799   fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n",                            \
 800            LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
 801
 802 /* This is how to output an assembler line
 803    that says to advance the location counter
 804    to a multiple of 2**LOG bytes.  */
 805
 806 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 807   fprintf (STREAM, "\t.align\t%d\n", (LOG))
 808
 809 /* Define the strings to put out for each section in the object file.  */
 810 #define TEXT_SECTION_ASM_OP     "\t.text"       /* instructions */
 811 #define DATA_SECTION_ASM_OP     "\t.data"       /* large data */
 812 #define READONLY_DATA_SECTION_ASM_OP    "\t.section\t.rodata"
 813 #define BSS_SECTION_ASM_OP      "\t.bss"
 814 #define SBSS_SECTION_ASM_OP     "\t.section\t.sbss,\"aw\",@nobits"
 815 #define SDATA_SECTION_ASM_OP    "\t.section\t.sdata,\"aw\",@progbits"
 816
 817 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)                               \
 818 do                                                                      \
 819   {                                                                     \
 820     fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n",              \
 821              reg_names[STACK_POINTER_REGNUM],                           \
 822              reg_names[STACK_POINTER_REGNUM],                           \
 823              TARGET_64BIT ? "sd" : "sw",                                \
 824              reg_names[REGNO],                                          \
 825              reg_names[STACK_POINTER_REGNUM]);                          \
 826   }                                                                     \
 827 while (0)
 828
 829 #define ASM_OUTPUT_REG_POP(STREAM,REGNO)                                \
 830 do                                                                      \
 831   {                                                                     \
 832     fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n",               \
 833              TARGET_64BIT ? "ld" : "lw",                                \
 834              reg_names[REGNO],                                          \
 835              reg_names[STACK_POINTER_REGNUM],                           \
 836              reg_names[STACK_POINTER_REGNUM],                           \
 837              reg_names[STACK_POINTER_REGNUM]);                          \
 838   }                                                                     \
 839 while (0)
 840
 841 #define ASM_COMMENT_START "#"
 842
 843 #undef SIZE_TYPE
 844 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
 845
 846 #undef PTRDIFF_TYPE
 847 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
 848
 849 /* If a memory-to-memory move would take MOVE_RATIO or more simple
 850    move-instruction pairs, we will do a movmem or libcall instead.  */
 851
 852 #define MOVE_RATIO(speed) (CLEAR_RATIO (speed) / 2)
 853
 854 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
 855    of the length of a memset call, but use the default otherwise.  */
 856
 857 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
 858
 859 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
 860    optimizing for size adjust the ratio to account for the overhead of
 861    loading the constant and replicating it across the word.  */
 862
 863 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
 864
 865 #ifndef USED_FOR_TARGET
 866 extern const enum reg_class riscv_regno_to_class[];
 867 extern bool riscv_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
 868 extern bool riscv_slow_unaligned_access;
 869 #endif
 870
 871 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 872   (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
 873
 874 #define XLEN_SPEC \
 875   "%{march=rv32*:32}" \
 876   "%{march=rv64*:64}" \
 877
 878 #define ABI_SPEC \
 879   "%{mabi=ilp32:ilp32}" \
 880   "%{mabi=ilp32f:ilp32f}" \
 881   "%{mabi=ilp32d:ilp32d}" \
 882   "%{mabi=lp64:lp64}" \
 883   "%{mabi=lp64f:lp64f}" \
 884   "%{mabi=lp64d:lp64d}" \
 885
 886 #define STARTFILE_PREFIX_SPEC                   \
 887    "/lib" XLEN_SPEC "/" ABI_SPEC "/ "           \
 888    "/usr/lib" XLEN_SPEC "/" ABI_SPEC "/ "       \
 889    "/lib/ "                                     \
 890    "/usr/lib/ "
 891
 892 /* ISA constants needed for code generation.  */
 893 #define OPCODE_LW    0x2003
 894 #define OPCODE_LD    0x3003
 895 #define OPCODE_AUIPC 0x17
 896 #define OPCODE_JALR  0x67
 897 #define OPCODE_LUI   0x37
 898 #define OPCODE_ADDI  0x13
 899 #define SHIFT_RD  7
 900 #define SHIFT_RS1 15
 901 #define SHIFT_IMM 20
 902 #define IMM_BITS 12
 903
 904 #define IMM_REACH (1LL << IMM_BITS)
 905 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
 906 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
 907
 908 #endif /* ! GCC_RISCV_H */