| blob | fc1cfb4161084ce79bdc221679526363bb9feadb |
1 /* Definitions of target machine for GNU compiler for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
27 #define TARGET_VERSION \
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because hconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do { \
40 switch ((int) sh_cpu) \
41 { \
42 case PROCESSOR_SH1: \
44 break; \
45 case PROCESSOR_SH2: \
47 break; \
48 case PROCESSOR_SH3: \
51 if (TARGET_HARD_SH4) \
53 break; \
54 case PROCESSOR_SH3E: \
56 break; \
57 case PROCESSOR_SH4: \
59 break; \
60 case PROCESSOR_SH5: \
61 { \
66 if (! TARGET_FPU_DOUBLE) \
68 } \
69 } \
70 if (TARGET_HITACHI) \
72 builtin_define (TARGET_LITTLE_ENDIAN \
74 if (flag_pic) \
75 { \
78 } \
79 TARGET_OBJFMT_CPP_BUILTINS (); \
80 } while (0)
82 /* We can not debug without a frame pointer. */
83 /* #define CAN_DEBUG_WITHOUT_FP */
85 #define CONDITIONAL_REGISTER_USAGE do \
86 { \
87 int regno; \
88 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
89 if (! VALID_REGISTER_P (regno)) \
90 fixed_regs[regno] = call_used_regs[regno] = 1; \
92 if (TARGET_SH5) \
93 call_used_regs[FIRST_GENERAL_REG + 8] \
94 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
95 if (TARGET_SHMEDIA) \
96 { \
97 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
98 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
99 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
100 } \
101 if (flag_pic) \
102 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
104 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
105 { \
106 call_used_regs[MACH_REG] = 0; \
107 call_used_regs[MACL_REG] = 0; \
108 } \
109 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
110 regno <= LAST_FP_REG; regno += 2) \
111 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
112 if (TARGET_SHMEDIA) \
113 { \
114 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
115 if (! fixed_regs[regno] && call_used_regs[regno]) \
116 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
117 } \
118 else \
119 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
120 if (! fixed_regs[regno] && call_used_regs[regno]) \
121 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
122 } while (0)
123 \f
124 /* ??? Need to write documentation for all SH options and add it to the
125 invoke.texi file. */
127 /* Run-time compilation parameters selecting different hardware subsets. */
130 #define ISIZE_BIT (1<<1)
131 #define DALIGN_BIT (1<<6)
132 #define SH1_BIT (1<<8)
133 #define SH2_BIT (1<<9)
134 #define SH3_BIT (1<<10)
135 #define SH3E_BIT (1<<11)
136 #define HARD_SH4_BIT (1<<5)
137 #define FPU_SINGLE_BIT (1<<7)
138 #define SH4_BIT (1<<12)
139 #define FMOVD_BIT (1<<4)
140 #define SH5_BIT (1<<0)
141 #define SPACE_BIT (1<<13)
142 #define BIGTABLE_BIT (1<<14)
143 #define RELAX_BIT (1<<15)
144 #define USERMODE_BIT (1<<16)
145 #define HITACHI_BIT (1<<22)
146 #define NOMACSAVE_BIT (1<<23)
147 #define PREFERGOT_BIT (1<<24)
148 #define PADSTRUCT_BIT (1<<28)
149 #define LITTLE_ENDIAN_BIT (1<<29)
150 #define IEEE_BIT (1<<30)
152 /* Nonzero if we should dump out instruction size info. */
153 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
155 /* Nonzero to align doubles on 64 bit boundaries. */
156 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
158 /* Nonzero if we should generate code using type 1 insns. */
159 #define TARGET_SH1 (target_flags & SH1_BIT)
161 /* Nonzero if we should generate code using type 2 insns. */
162 #define TARGET_SH2 (target_flags & SH2_BIT)
164 /* Nonzero if we should generate code using type 3 insns. */
165 #define TARGET_SH3 (target_flags & SH3_BIT)
167 /* Nonzero if we should generate code using type 3E insns. */
168 #define TARGET_SH3E ((target_flags & SH3E_BIT) && (target_flags & SH1_BIT))
170 /* Nonzero if the cache line size is 32. */
171 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
173 /* Nonzero if we schedule for a superscalar implementation. */
174 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
176 /* Nonzero if the target has separate instruction and data caches. */
177 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
179 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
180 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
182 /* Nonzero if the default precision of th FPU is single */
183 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
185 /* Nonzero if a double-precision FPU is available. */
186 #define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
188 /* Nonzero if an FPU is available. */
189 #define TARGET_FPU_ANY (TARGET_SH3E || TARGET_FPU_DOUBLE)
191 /* Nonzero if we should generate code using type 4 insns. */
192 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
194 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
195 #define TARGET_SH5 (target_flags & SH5_BIT)
197 /* Nonzero if we should generate code using the SHcompact instruction
198 set and 32-bit ABI. */
199 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
201 /* Nonzero if we should generate code using the SHmedia instruction
202 set and ABI. */
203 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
205 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
206 ABI. */
207 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
208 && (target_flags & SH3E_BIT))
210 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
211 ABI. */
212 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
213 && ! (target_flags & SH3E_BIT))
215 /* Nonzero if we should generate code using SHmedia FPU instructions. */
216 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
217 /* Nonzero if we should generate fmovd. */
218 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
220 /* Nonzero if we respect NANs. */
221 #define TARGET_IEEE (target_flags & IEEE_BIT)
223 /* Nonzero if we should generate smaller code rather than faster code. */
224 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
226 /* Nonzero to use long jump tables. */
227 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
229 /* Nonzero to generate pseudo-ops needed by the assembler and linker
230 to do function call relaxing. */
231 #define TARGET_RELAX (target_flags & RELAX_BIT)
233 /* Nonzero if using Hitachi's calling convention. */
234 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
236 /* Nonzero if not saving macl/mach when using -mhitachi */
237 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
239 /* Nonzero if padding structures to a multiple of 4 bytes. This is
240 incompatible with Hitachi's compiler, and gives unusual structure layouts
241 which confuse programmers.
242 ??? This option is not useful, but is retained in case there are people
243 who are still relying on it. It may be deleted in the future. */
244 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
246 /* Nonzero if generating code for a little endian SH. */
247 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
249 /* Nonzero if we should do everything in userland. */
250 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
252 /* Nonzero if we should prefer @GOT calls when generating PIC. */
253 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
255 #define SELECT_SH1 (SH1_BIT)
256 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
257 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
258 #define SELECT_SH3E (SH3E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
259 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
260 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
261 #define SELECT_SH4 (SH4_BIT|SH3E_BIT|HARD_SH4_BIT | SELECT_SH3)
262 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
263 #define SELECT_SH5_64 (SH5_BIT | SH4_BIT)
264 #define SELECT_SH5_64_NOFPU (SH5_BIT)
265 #define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH3E_BIT)
266 #define SELECT_SH5_32_NOFPU (SH5_BIT | SH3E_BIT)
267 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
268 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
270 /* Reset all target-selection flags. */
271 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH3E_BIT | SH4_BIT \
272 | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
274 #define TARGET_SWITCHES \
318 SUBTARGET_SWITCHES \
320 }
322 /* This are meant to be redefined in the host dependent files */
323 #define SUBTARGET_SWITCHES
325 /* This defaults us to big-endian. */
326 #ifndef TARGET_ENDIAN_DEFAULT
327 #define TARGET_ENDIAN_DEFAULT 0
328 #endif
330 #ifndef TARGET_CPU_DEFAULT
331 #define TARGET_CPU_DEFAULT SELECT_SH1
332 #endif
334 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
338 #ifndef SUBTARGET_CPP_SPEC
340 #endif
342 #ifndef SUBTARGET_EXTRA_SPECS
343 #define SUBTARGET_EXTRA_SPECS
344 #endif
346 #define EXTRA_SPECS \
353 SUBTARGET_EXTRA_SPECS
357 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
358 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
360 #else
362 #endif
363 #endif
367 #if TARGET_CPU_DEFAULT & SH5_BIT
368 #if TARGET_CPU_DEFAULT & SH3E_BIT
370 #else
373 #else
380 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
381 so that we can undo the damage without code replication. */
382 #define LINK_SPEC SH_LINK_SPEC
385 -m %(link_emul_prefix)\
386 %{m5-compact*|m5-32media*:32}\
387 %{m5-64media*:64}\
388 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
389 %(subtarget_link_emul_suffix) \
390 %{mrelax:-relax} %(subtarget_link_spec)"
392 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
393 do { \
394 if (LEVEL) \
395 flag_omit_frame_pointer = -1; \
396 if (SIZE) \
397 target_flags |= SPACE_BIT; \
398 } while (0)
400 #define ASSEMBLER_DIALECT assembler_dialect
404 #define OVERRIDE_OPTIONS \
405 do { \
406 int regno; \
407 \
408 sh_cpu = CPU_SH1; \
409 assembler_dialect = 0; \
410 if (TARGET_SH2) \
411 sh_cpu = CPU_SH2; \
412 if (TARGET_SH3) \
413 sh_cpu = CPU_SH3; \
414 if (TARGET_SH3E) \
415 sh_cpu = CPU_SH3E; \
416 if (TARGET_SH4) \
417 { \
418 assembler_dialect = 1; \
419 sh_cpu = CPU_SH4; \
420 } \
421 if (TARGET_SH5) \
422 { \
423 sh_cpu = CPU_SH5; \
424 target_flags |= DALIGN_BIT; \
425 if (TARGET_FPU_ANY \
426 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN)) \
427 target_flags |= FMOVD_BIT; \
428 if (TARGET_SHMEDIA) \
429 { \
431 flag_delayed_branch = 0; \
433 target_flags &= ~RELAX_BIT; \
434 } \
435 if (profile_flag || profile_arc_flag) \
436 { \
438 profile_flag = profile_arc_flag = 0; \
439 } \
440 } \
441 else \
442 { \
444 targetm.asm_out.aligned_op.di = NULL; \
445 targetm.asm_out.unaligned_op.di = NULL; \
446 } \
447 \
448 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
449 if (! VALID_REGISTER_P (regno)) \
451 \
452 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
453 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
455 \
456 if (flag_omit_frame_pointer < 0) \
457 { \
458 /* The debugging information is sufficient, \
460 if (0) \
461 flag_omit_frame_pointer \
462 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
463 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
464 else \
465 flag_omit_frame_pointer = 0; \
466 } \
467 \
468 if (flag_pic && ! TARGET_PREFERGOT) \
469 flag_no_function_cse = 1; \
470 \
471 /* Never run scheduling before reload, since that can \
472 break global alloc, and generates slower code anyway due \
474 flag_schedule_insns = 0; \
475 } while (0)
476 \f
477 /* Target machine storage layout. */
479 /* Define this if most significant bit is lowest numbered
480 in instructions that operate on numbered bit-fields. */
482 #define BITS_BIG_ENDIAN 0
484 /* Define this if most significant byte of a word is the lowest numbered. */
485 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
487 /* Define this if most significant word of a multiword number is the lowest
488 numbered. */
489 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
491 /* Define this to set the endianness to use in libgcc2.c, which can
492 not depend on target_flags. */
493 #if defined(__LITTLE_ENDIAN__)
494 #define LIBGCC2_WORDS_BIG_ENDIAN 0
495 #else
496 #define LIBGCC2_WORDS_BIG_ENDIAN 1
497 #endif
499 #define MAX_BITS_PER_WORD 64
501 #define MAX_LONG_TYPE_SIZE MAX_BITS_PER_WORD
503 /* Width in bits of an `int'. We want just 32-bits, even if words are
504 longer. */
505 #define INT_TYPE_SIZE 32
507 /* Width in bits of a `long'. */
508 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
510 /* Width in bits of a `long long'. */
511 #define LONG_LONG_TYPE_SIZE 64
513 /* Width in bits of a `long double'. */
514 #define LONG_DOUBLE_TYPE_SIZE 64
516 /* Width of a word, in units (bytes). */
517 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
518 #define MIN_UNITS_PER_WORD 4
520 /* Width in bits of a pointer.
521 See also the macro `Pmode' defined below. */
522 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
524 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
525 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
527 /* Boundary (in *bits*) on which stack pointer should be aligned. */
528 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
530 /* The log (base 2) of the cache line size, in bytes. Processors prior to
531 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
532 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
533 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
535 /* Allocation boundary (in *bits*) for the code of a function.
536 32 bit alignment is faster, because instructions are always fetched as a
537 pair from a longword boundary. */
538 #define FUNCTION_BOUNDARY \
539 (TARGET_SMALLCODE ? 16 << TARGET_SHMEDIA : (1 << CACHE_LOG) * 8)
541 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
542 the vbit must go into the delta field of
543 pointers-to-member-functions. */
544 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
545 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
547 /* Alignment of field after `int : 0' in a structure. */
548 #define EMPTY_FIELD_BOUNDARY 32
550 /* No data type wants to be aligned rounder than this. */
551 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
553 /* The best alignment to use in cases where we have a choice. */
554 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
556 /* Make strings word-aligned so strcpy from constants will be faster. */
557 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
558 ((TREE_CODE (EXP) == STRING_CST \
559 && (ALIGN) < FASTEST_ALIGNMENT) \
560 ? FASTEST_ALIGNMENT : (ALIGN))
562 /* Make arrays of chars word-aligned for the same reasons. */
563 #define DATA_ALIGNMENT(TYPE, ALIGN) \
564 (TREE_CODE (TYPE) == ARRAY_TYPE \
565 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
566 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
568 /* Number of bits which any structure or union's size must be a
569 multiple of. Each structure or union's size is rounded up to a
570 multiple of this. */
571 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
573 /* Set this nonzero if move instructions will actually fail to work
574 when given unaligned data. */
575 #define STRICT_ALIGNMENT 1
577 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
578 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
579 barrier_align (LABEL_AFTER_BARRIER)
581 #define LOOP_ALIGN(A_LABEL) \
582 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
583 ? 0 : sh_loop_align (A_LABEL))
585 #define LABEL_ALIGN(A_LABEL) \
586 ( \
587 (PREV_INSN (A_LABEL) \
588 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
589 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
590 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
592 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
593 : 0)
595 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
596 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
598 /* The base two logarithm of the known minimum alignment of an insn length. */
599 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
600 (GET_CODE (A_INSN) == INSN \
601 ? 1 << TARGET_SHMEDIA \
602 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
603 ? 1 << TARGET_SHMEDIA \
604 : CACHE_LOG)
605 \f
606 /* Standard register usage. */
608 /* Register allocation for the Hitachi calling convention:
610 r0 arg return
611 r1..r3 scratch
612 r4..r7 args in
613 r8..r13 call saved
614 r14 frame pointer/call saved
615 r15 stack pointer
616 ap arg pointer (doesn't really exist, always eliminated)
617 pr subroutine return address
618 t t bit
619 mach multiply/accumulate result, high part
620 macl multiply/accumulate result, low part.
621 fpul fp/int communication register
622 rap return address pointer register
623 fr0 fp arg return
624 fr1..fr3 scratch floating point registers
625 fr4..fr11 fp args in
626 fr12..fr15 call saved floating point registers */
628 #define MAX_REGISTER_NAME_LENGTH 5
631 #define SH_REGISTER_NAMES_INITIALIZER \
632 { \
653 }
655 #define DEBUG_REGISTER_NAMES SH_REGISTER_NAMES_INITIALIZER
657 #define REGNAMES_ARR_INDEX_1(index) \
658 (sh_register_names[index])
659 #define REGNAMES_ARR_INDEX_2(index) \
660 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
661 #define REGNAMES_ARR_INDEX_4(index) \
662 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
663 #define REGNAMES_ARR_INDEX_8(index) \
664 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
665 #define REGNAMES_ARR_INDEX_16(index) \
666 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
667 #define REGNAMES_ARR_INDEX_32(index) \
668 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
669 #define REGNAMES_ARR_INDEX_64(index) \
670 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
672 #define REGISTER_NAMES \
673 { \
674 REGNAMES_ARR_INDEX_64 (0), \
675 REGNAMES_ARR_INDEX_64 (64), \
676 REGNAMES_ARR_INDEX_8 (128), \
677 REGNAMES_ARR_INDEX_8 (136), \
678 REGNAMES_ARR_INDEX_8 (144), \
679 REGNAMES_ARR_INDEX_1 (152) \
680 }
682 #define ADDREGNAMES_SIZE 32
683 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
687 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
688 { \
693 }
695 #define ADDREGNAMES_REGNO(index) \
696 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
697 : (-1))
699 #define ADDREGNAMES_ARR_INDEX_1(index) \
700 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
701 #define ADDREGNAMES_ARR_INDEX_2(index) \
702 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
703 #define ADDREGNAMES_ARR_INDEX_4(index) \
704 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
705 #define ADDREGNAMES_ARR_INDEX_8(index) \
706 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
707 #define ADDREGNAMES_ARR_INDEX_16(index) \
708 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
709 #define ADDREGNAMES_ARR_INDEX_32(index) \
710 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
712 #define ADDITIONAL_REGISTER_NAMES \
713 { \
714 ADDREGNAMES_ARR_INDEX_32 (0) \
715 }
717 /* Number of actual hardware registers.
718 The hardware registers are assigned numbers for the compiler
719 from 0 to just below FIRST_PSEUDO_REGISTER.
720 All registers that the compiler knows about must be given numbers,
721 even those that are not normally considered general registers. */
723 /* There are many other relevant definitions in sh.md's md_constants. */
725 #define FIRST_GENERAL_REG R0_REG
726 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
727 #define FIRST_FP_REG DR0_REG
728 #define LAST_FP_REG (FIRST_FP_REG + \
729 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH3E ? 15 : -1))
730 #define FIRST_XD_REG XD0_REG
731 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
732 #define FIRST_TARGET_REG TR0_REG
733 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
735 #define GENERAL_REGISTER_P(REGNO) \
736 IN_RANGE ((REGNO), FIRST_GENERAL_REG, LAST_GENERAL_REG)
738 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
739 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
741 #define FP_REGISTER_P(REGNO) \
742 ((REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG)
744 #define XD_REGISTER_P(REGNO) \
745 ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG)
747 #define FP_OR_XD_REGISTER_P(REGNO) \
748 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
750 #define FP_ANY_REGISTER_P(REGNO) \
751 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
753 #define SPECIAL_REGISTER_P(REGNO) \
754 ((REGNO) == GBR_REG || (REGNO) == T_REG \
755 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
757 #define TARGET_REGISTER_P(REGNO) \
758 ((REGNO) >= FIRST_TARGET_REG && (REGNO) <= LAST_TARGET_REG)
760 #define SHMEDIA_REGISTER_P(REGNO) \
761 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
762 || TARGET_REGISTER_P (REGNO))
764 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
765 that should be fixed. */
766 #define VALID_REGISTER_P(REGNO) \
767 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
768 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
769 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
770 || (TARGET_SH3E && (REGNO) == FPUL_REG))
772 /* The mode that should be generally used to store a register by
773 itself in the stack, or to load it back. */
774 #define REGISTER_NATURAL_MODE(REGNO) \
775 (FP_REGISTER_P (REGNO) ? SFmode \
776 : XD_REGISTER_P (REGNO) ? DFmode \
777 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
778 ? DImode \
779 : SImode)
781 #define FIRST_PSEUDO_REGISTER 153
783 /* 1 for registers that have pervasive standard uses
784 and are not available for the register allocator.
786 Mach register is fixed 'cause it's only 10 bits wide for SH1.
787 It is 32 bits wide for SH2. */
789 #define FIXED_REGISTERS \
790 { \
792 0, 0, 0, 0, 0, 0, 0, 0, \
793 0, 0, 0, 0, 0, 0, 0, 1, \
795 1, 0, 0, 0, 0, 0, 0, 0, \
798 1, 1, 1, 1, 0, 0, 0, 0, \
799 0, 0, 0, 0, 0, 0, 0, 0, \
800 0, 0, 0, 0, 0, 0, 0, 0, \
801 0, 0, 0, 0, 0, 0, 0, 0, \
802 0, 0, 0, 0, 0, 0, 0, 1, \
804 0, 0, 0, 0, 0, 0, 0, 0, \
805 0, 0, 0, 0, 0, 0, 0, 0, \
806 0, 0, 0, 0, 0, 0, 0, 0, \
807 0, 0, 0, 0, 0, 0, 0, 0, \
808 0, 0, 0, 0, 0, 0, 0, 0, \
809 0, 0, 0, 0, 0, 0, 0, 0, \
810 0, 0, 0, 0, 0, 0, 0, 0, \
811 0, 0, 0, 0, 0, 0, 0, 0, \
813 0, 0, 0, 0, 0, 0, 0, 0, \
815 0, 0, 0, 0, 0, 0, 0, 0, \
817 1, 1, 1, 1, 1, 1, 0, 1, \
819 1, \
820 }
822 /* 1 for registers not available across function calls.
823 These must include the FIXED_REGISTERS and also any
824 registers that can be used without being saved.
825 The latter must include the registers where values are returned
826 and the register where structure-value addresses are passed.
827 Aside from that, you can include as many other registers as you like. */
829 #define CALL_USED_REGISTERS \
830 { \
832 1, 1, 1, 1, 1, 1, 1, 1, \
833 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
834 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
836 0, 0, 0, 0, 0, 0, 0, 1, \
837 1, 1, 0, 1, 1, 1, 1, 1, \
838 1, 1, 1, 1, 0, 0, 0, 0, \
839 0, 0, 0, 0, 1, 1, 1, 1, \
840 1, 1, 1, 1, 0, 0, 0, 0, \
841 0, 0, 0, 0, 0, 0, 0, 0, \
842 0, 0, 0, 0, 1, 1, 1, 1, \
844 1, 1, 1, 1, 1, 1, 1, 1, \
845 1, 1, 1, 1, 0, 0, 0, 0, \
846 1, 1, 1, 1, 1, 1, 1, 1, \
847 1, 1, 1, 1, 1, 1, 1, 1, \
848 1, 1, 1, 1, 0, 0, 0, 0, \
849 0, 0, 0, 0, 0, 0, 0, 0, \
850 0, 0, 0, 0, 0, 0, 0, 0, \
851 0, 0, 0, 0, 0, 0, 0, 0, \
853 1, 1, 1, 1, 1, 0, 0, 0, \
855 1, 1, 1, 1, 1, 1, 0, 0, \
857 1, 1, 0, 1, 1, 1, 1, 1, \
859 1, \
860 }
862 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
863 across SHcompact function calls. We can't tell whether a called
864 function is SHmedia or SHcompact, so we assume it may be when
865 compiling SHmedia code with the 32-bit ABI, since that's the only
866 ABI that can be linked with SHcompact code. */
867 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
868 (TARGET_SHMEDIA32 \
869 && GET_MODE_SIZE (MODE) > 4 \
870 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
871 && (REGNO) <= FIRST_GENERAL_REG + 14) \
872 || (REGNO) == PR_MEDIA_REG))
874 /* Return number of consecutive hard regs needed starting at reg REGNO
875 to hold something of mode MODE.
876 This is ordinarily the length in words of a value of mode MODE
877 but can be less for certain modes in special long registers.
879 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
881 #define HARD_REGNO_NREGS(REGNO, MODE) \
882 (XD_REGISTER_P (REGNO) \
883 ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \
884 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
885 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
886 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
888 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
889 We can allow any mode in any general register. The special registers
890 only allow SImode. Don't allow any mode in the PR. */
892 /* We cannot hold DCmode values in the XD registers because alter_reg
893 handles subregs of them incorrectly. We could work around this by
894 spacing the XD registers like the DR registers, but this would require
895 additional memory in every compilation to hold larger register vectors.
896 We could hold SFmode / SCmode values in XD registers, but that
897 would require a tertiary reload when reloading from / to memory,
898 and a secondary reload to reload from / to general regs; that
899 seems to be a loosing proposition. */
900 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
901 it won't be ferried through GP registers first. */
902 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
903 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
904 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
905 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
906 ? 1 \
907 : (MODE) == V2SFmode \
908 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
909 || (TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
910 : (MODE) == V4SFmode \
911 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
912 : (MODE) == V16SFmode \
913 ? (TARGET_SHMEDIA \
914 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
915 : (REGNO) == FIRST_XD_REG) \
916 : FP_REGISTER_P (REGNO) \
917 ? ((MODE) == SFmode \
918 || (TARGET_SHMEDIA && (MODE) == SImode) \
919 || ((TARGET_SH3E || TARGET_SHMEDIA) && (MODE) == SCmode) \
920 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
921 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
922 || (MODE) == V2SFmode || (MODE) == TImode))) \
923 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
924 : XD_REGISTER_P (REGNO) \
925 ? (MODE) == DFmode \
926 : TARGET_REGISTER_P (REGNO) \
927 ? ((MODE) == DImode || (MODE) == SImode) \
928 : (REGNO) == PR_REG ? 0 \
929 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
930 : 1)
932 /* Value is 1 if MODE is a supported vector mode. */
933 #define VECTOR_MODE_SUPPORTED_P(MODE) \
934 ((TARGET_FPU_ANY \
935 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
936 || (TARGET_SHMEDIA \
937 && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
938 || (MODE) == V2SImode)))
940 /* Value is 1 if it is a good idea to tie two pseudo registers
941 when one has mode MODE1 and one has mode MODE2.
942 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
943 for any hard reg, then this must be 0 for correct output.
944 That's the case for xd registers: we don't hold SFmode values in
945 them, so we can't tie an SFmode pseudos with one in another
946 floating-point mode. */
948 #define MODES_TIEABLE_P(MODE1, MODE2) \
949 ((MODE1) == (MODE2) \
950 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
951 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
952 && (GET_MODE_SIZE (MODE2) <= 4)) \
953 : ((MODE1) != SFmode && (MODE2) != SFmode))))
955 /* A C expression that is nonzero if hard register NEW_REG can be
956 considered for use as a rename register for OLD_REG register */
958 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
959 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
961 /* Specify the registers used for certain standard purposes.
962 The values of these macros are register numbers. */
964 /* Define this if the program counter is overloaded on a register. */
965 /* #define PC_REGNUM 15*/
967 /* Register to use for pushing function arguments. */
968 #define STACK_POINTER_REGNUM SP_REG
970 /* Base register for access to local variables of the function. */
971 #define FRAME_POINTER_REGNUM FP_REG
973 /* Fake register that holds the address on the stack of the
974 current function's return address. */
975 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
977 /* Register to hold the addressing base for position independent
978 code access to data items. */
979 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
983 /* Value should be nonzero if functions must have frame pointers.
984 Zero means the frame pointer need not be set up (and parms may be accessed
985 via the stack pointer) in functions that seem suitable. */
987 #define FRAME_POINTER_REQUIRED 0
989 /* Definitions for register eliminations.
991 We have three registers that can be eliminated on the SH. First, the
992 frame pointer register can often be eliminated in favor of the stack
993 pointer register. Secondly, the argument pointer register can always be
994 eliminated; it is replaced with either the stack or frame pointer.
995 Third, there is the return address pointer, which can also be replaced
996 with either the stack or the frame pointer. */
998 /* This is an array of structures. Each structure initializes one pair
999 of eliminable registers. The "from" register number is given first,
1000 followed by "to". Eliminations of the same "from" register are listed
1001 in order of preference. */
1003 /* If you add any registers here that are not actually hard registers,
1004 and that have any alternative of elimination that doesn't always
1005 apply, you need to amend calc_live_regs to exclude it, because
1006 reload spills all eliminable registers where it sees an
1007 can_eliminate == 0 entry, thus making them 'live' .
1008 If you add any hard registers that can be eliminated in different
1009 ways, you have to patch reload to spill them only when all alternatives
1010 of elimination fail. */
1012 #define ELIMINABLE_REGS \
1013 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1014 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1015 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1016 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1017 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1019 /* Given FROM and TO register numbers, say whether this elimination
1020 is allowed. */
1021 #define CAN_ELIMINATE(FROM, TO) \
1022 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1024 /* Define the offset between two registers, one to be eliminated, and the other
1025 its replacement, at the start of a routine. */
1027 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1028 OFFSET = initial_elimination_offset ((FROM), (TO))
1030 /* Base register for access to arguments of the function. */
1031 #define ARG_POINTER_REGNUM AP_REG
1033 /* Register in which the static-chain is passed to a function. */
1034 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1036 /* The register in which a struct value address is passed. */
1038 #define STRUCT_VALUE_REGNUM 2
1040 /* If the structure value address is not passed in a register, define
1041 `STRUCT_VALUE' as an expression returning an RTX for the place
1042 where the address is passed. If it returns 0, the address is
1043 passed as an "invisible" first argument. */
1045 /* The Hitachi calling convention doesn't quite fit into this scheme since
1046 the address is passed like an invisible argument, but one that is always
1047 passed in memory. */
1048 #define STRUCT_VALUE \
1049 (TARGET_HITACHI ? 0 : gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM))
1051 #define RETURN_IN_MEMORY(TYPE) \
1052 (TARGET_SH5 \
1053 ? ((TYPE_MODE (TYPE) == BLKmode \
1054 ? (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
1055 : GET_MODE_SIZE (TYPE_MODE (TYPE))) > 8) \
1056 : (TYPE_MODE (TYPE) == BLKmode \
1057 || TARGET_HITACHI && TREE_CODE (TYPE) == RECORD_TYPE))
1059 /* Don't default to pcc-struct-return, because we have already specified
1060 exactly how to return structures in the RETURN_IN_MEMORY macro. */
1062 #define DEFAULT_PCC_STRUCT_RETURN 0
1064 #define SHMEDIA_REGS_STACK_ADJUST() \
1065 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1068 : 0)
1070 \f
1071 /* Define the classes of registers for register constraints in the
1072 machine description. Also define ranges of constants.
1074 One of the classes must always be named ALL_REGS and include all hard regs.
1075 If there is more than one class, another class must be named NO_REGS
1076 and contain no registers.
1078 The name GENERAL_REGS must be the name of a class (or an alias for
1079 another name such as ALL_REGS). This is the class of registers
1080 that is allowed by "g" or "r" in a register constraint.
1081 Also, registers outside this class are allocated only when
1082 instructions express preferences for them.
1084 The classes must be numbered in nondecreasing order; that is,
1085 a larger-numbered class must never be contained completely
1086 in a smaller-numbered class.
1088 For any two classes, it is very desirable that there be another
1089 class that represents their union. */
1091 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1092 be used as the destination of some of the arithmetic ops. There are
1093 also some special purpose registers; the T bit register, the
1094 Procedure Return Register and the Multiply Accumulate Registers. */
1095 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1096 reg_class_subunion. We don't want to have an actual union class
1097 of these, because it would only be used when both classes are calculated
1098 to give the same cost, but there is only one FPUL register.
1099 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1100 applying to the actual instruction alternative considered. E.g., the
1101 y/r alternative of movsi_ie is considered to have no more cost that
1102 the r/r alternative, which is patently untrue. */
1104 enum reg_class
1105 {
1106 NO_REGS,
1107 R0_REGS,
1108 PR_REGS,
1109 T_REGS,
1110 MAC_REGS,
1111 FPUL_REGS,
1112 SIBCALL_REGS,
1113 GENERAL_REGS,
1114 FP0_REGS,
1115 FP_REGS,
1116 DF_HI_REGS,
1117 DF_REGS,
1118 FPSCR_REGS,
1119 GENERAL_FP_REGS,
1120 TARGET_REGS,
1121 ALL_REGS,
1122 LIM_REG_CLASSES
1123 };
1125 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1127 /* Give names of register classes as strings for dump file. */
1128 #define REG_CLASS_NAMES \
1129 { \
1146 }
1148 /* Define which registers fit in which classes.
1149 This is an initializer for a vector of HARD_REG_SET
1150 of length N_REG_CLASSES. */
1152 #define REG_CLASS_CONTENTS \
1153 { \
1155 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1157 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1159 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1161 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1163 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1165 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1167 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1169 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1171 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1173 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1175 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1177 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1179 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1181 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1183 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1185 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1186 }
1188 /* The same information, inverted:
1189 Return the class number of the smallest class containing
1190 reg number REGNO. This could be a conditional expression
1191 or could index an array. */
1194 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1196 /* When defined, the compiler allows registers explicitly used in the
1197 rtl to be used as spill registers but prevents the compiler from
1198 extending the lifetime of these registers. */
1200 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1202 /* The order in which register should be allocated. */
1203 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1204 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1205 spilled or used otherwise, we better have the FP_REGS allocated first. */
1206 #define REG_ALLOC_ORDER \
1207 { 65, 66, 67, 68, 69, 70, 71, 64, \
1208 72, 73, 74, 75, 76, 77, 78, 79, \
1209 136,137,138,139,140,141,142,143, \
1210 80, 81, 82, 83, 84, 85, 86, 87, \
1211 88, 89, 90, 91, 92, 93, 94, 95, \
1212 96, 97, 98, 99,100,101,102,103, \
1213 104,105,106,107,108,109,110,111, \
1214 112,113,114,115,116,117,118,119, \
1215 120,121,122,123,124,125,126,127, \
1216 151, 1, 2, 3, 7, 6, 5, 4, \
1217 0, 8, 9, 10, 11, 12, 13, 14, \
1218 16, 17, 18, 19, 20, 21, 22, 23, \
1219 24, 25, 26, 27, 28, 29, 30, 31, \
1220 32, 33, 34, 35, 36, 37, 38, 39, \
1221 40, 41, 42, 43, 44, 45, 46, 47, \
1222 48, 49, 50, 51, 52, 53, 54, 55, \
1223 56, 57, 58, 59, 60, 61, 62, 63, \
1224 150, 15,145,146,147,144,148,149, \
1225 128,129,130,131,132,133,134,135, \
1226 152 }
1228 /* The class value for index registers, and the one for base regs. */
1229 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1230 #define BASE_REG_CLASS GENERAL_REGS
1232 /* Get reg_class from a letter such as appears in the machine
1233 description. */
1236 #define REG_CLASS_FROM_LETTER(C) \
1238 \f
1239 /* The letters I, J, K, L and M in a register constraint string
1240 can be used to stand for particular ranges of immediate operands.
1241 This macro defines what the ranges are.
1242 C is the letter, and VALUE is a constant value.
1243 Return 1 if VALUE is in the range specified by C.
1244 I: arithmetic operand -127..128, as used in add, sub, etc
1245 J: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1246 K: shift operand 1,2,8 or 16
1247 L: logical operand 0..255, as used in and, or, etc.
1248 M: constant 1
1249 N: constant 0
1250 O: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1251 P: arithmetic operand -512..511, as used in SHmedia andi, ori
1252 */
1254 #define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1255 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1256 #define CONST_OK_FOR_J(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1257 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1258 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1259 #define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1260 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1261 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1262 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1263 #define CONST_OK_FOR_O(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1264 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1265 #define CONST_OK_FOR_P(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1266 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1267 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1276 : 0)
1278 /* Similar, but for floating constants, and defining letters G and H.
1279 Here VALUE is the CONST_DOUBLE rtx itself. */
1281 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1286 /* Given an rtx X being reloaded into a reg required to be
1287 in class CLASS, return the class of reg to actually use.
1288 In general this is just CLASS; but on some machines
1289 in some cases it is preferable to use a more restrictive class. */
1291 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1292 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1293 && (GET_CODE (X) == CONST_DOUBLE \
1294 || GET_CODE (X) == SYMBOL_REF) \
1295 ? GENERAL_REGS \
1296 : (CLASS)) \
1298 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1299 ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \
1300 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS) \
1301 && (GET_CODE (X) == REG && GENERAL_OR_AP_REGISTER_P (REGNO (X)))) \
1302 || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \
1303 && GET_CODE (X) == REG \
1304 && FP_REGISTER_P (REGNO (X)))) \
1305 && ! TARGET_SHMEDIA \
1306 && MODE == SFmode) \
1307 ? FPUL_REGS \
1308 : ((CLASS) == FPUL_REGS \
1309 && (GET_CODE (X) == MEM \
1310 || (GET_CODE (X) == REG \
1311 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1312 || REGNO (X) == T_REG \
1313 || system_reg_operand (X, VOIDmode))))) \
1314 ? GENERAL_REGS \
1315 : ((CLASS) == TARGET_REGS \
1316 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1317 ? ((target_operand ((X), (MODE)) \
1318 && ! target_reg_operand ((X), (MODE))) \
1319 ? NO_REGS : GENERAL_REGS) \
1320 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1321 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1322 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1323 ? GENERAL_REGS \
1324 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1325 && TARGET_REGISTER_P (REGNO (X))) \
1326 ? GENERAL_REGS : NO_REGS)
1328 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1329 ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS \
1330 || (CLASS) == DF_HI_REGS) \
1331 && ! TARGET_SHMEDIA \
1332 && immediate_operand ((X), (MODE)) \
1333 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1334 && (MODE) == SFmode && fldi_ok ())) \
1335 ? R0_REGS \
1336 : (CLASS == FPUL_REGS \
1337 && ((GET_CODE (X) == REG \
1338 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1339 || REGNO (X) == T_REG)))) \
1340 ? GENERAL_REGS \
1341 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1342 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \
1343 ? GENERAL_REGS \
1344 : R0_REGS) \
1345 : (CLASS == FPSCR_REGS \
1346 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1347 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1348 ? GENERAL_REGS \
1349 : (((CLASS) == FP_REGS || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)\
1350 && TARGET_SHMEDIA \
1351 && immediate_operand ((X), (MODE)) \
1352 && (X) != CONST0_RTX (GET_MODE (X)) \
1353 && GET_MODE (X) != V4SFmode) \
1354 ? GENERAL_REGS \
1355 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1357 /* Return the maximum number of consecutive registers
1358 needed to represent mode MODE in a register of class CLASS.
1360 On SH this is the size of MODE in words. */
1361 #define CLASS_MAX_NREGS(CLASS, MODE) \
1362 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1364 /* If defined, gives a class of registers that cannot be used as the
1365 operand of a SUBREG that changes the mode of the object illegally. */
1366 /* ??? We need to renumber the internal numbers for the frnn registers
1367 when in little endian in order to allow mode size changes. */
1369 #define CLASS_CANNOT_CHANGE_MODE (TARGET_LITTLE_ENDIAN ? DF_REGS : DF_HI_REGS)
1371 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1373 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1374 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1375 && ((TARGET_LITTLE_ENDIAN && GET_MODE_SIZE (TO) < 8) \
1376 || GET_MODE_SIZE (FROM) < 8))
1377 \f
1378 /* Stack layout; function entry, exit and calling. */
1380 /* Define the number of registers that can hold parameters.
1381 These macros are used only in other macro definitions below. */
1383 #define NPARM_REGS(MODE) \
1384 (TARGET_FPU_ANY && (MODE) == SFmode \
1385 ? (TARGET_SH5 ? 12 : 8) \
1386 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1387 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1388 ? (TARGET_SH5 ? 12 : 8) \
1389 : (TARGET_SH5 ? 8 : 4))
1391 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1392 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1394 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1395 #define FIRST_FP_RET_REG FIRST_FP_REG
1397 /* Define this if pushing a word on the stack
1398 makes the stack pointer a smaller address. */
1399 #define STACK_GROWS_DOWNWARD
1401 /* Define this macro if the addresses of local variable slots are at
1402 negative offsets from the frame pointer.
1404 The SH only has positive indexes, so grow the frame up. */
1405 /* #define FRAME_GROWS_DOWNWARD */
1407 /* Offset from the frame pointer to the first local variable slot to
1408 be allocated. */
1409 #define STARTING_FRAME_OFFSET 0
1411 /* If we generate an insn to push BYTES bytes,
1412 this says how many the stack pointer really advances by. */
1413 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1414 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1415 do correct alignment. */
1416 #if 0
1417 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1418 #endif
1420 /* Offset of first parameter from the argument pointer register value. */
1421 #define FIRST_PARM_OFFSET(FNDECL) 0
1423 /* Value is the number of byte of arguments automatically
1424 popped when returning from a subroutine call.
1425 FUNDECL is the declaration node of the function (as a tree),
1426 FUNTYPE is the data type of the function (as a tree),
1427 or for a library call it is an identifier node for the subroutine name.
1428 SIZE is the number of bytes of arguments passed on the stack.
1430 On the SH, the caller does not pop any of its arguments that were passed
1431 on the stack. */
1432 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1434 /* Value is the number of bytes of arguments automatically popped when
1435 calling a subroutine.
1436 CUM is the accumulated argument list.
1438 On SHcompact, the call trampoline pops arguments off the stack. */
1439 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1441 /* Nonzero if we do not know how to pass TYPE solely in registers.
1442 Values that come in registers with inconvenient padding are stored
1443 to memory at the function start. */
1445 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1446 ((TYPE) != 0 \
1447 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1448 || TREE_ADDRESSABLE (TYPE)))
1449 /* Some subroutine macros specific to this machine. */
1451 #define BASE_RETURN_VALUE_REG(MODE) \
1452 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1453 ? FIRST_FP_RET_REG \
1454 : TARGET_FPU_ANY && (MODE) == SCmode \
1455 ? FIRST_FP_RET_REG \
1456 : (TARGET_FPU_DOUBLE \
1457 && ((MODE) == DFmode || (MODE) == SFmode \
1458 || (MODE) == DCmode || (MODE) == SCmode )) \
1459 ? FIRST_FP_RET_REG \
1460 : FIRST_RET_REG)
1462 #define BASE_ARG_REG(MODE) \
1463 ((TARGET_SH3E && ((MODE) == SFmode)) \
1464 ? FIRST_FP_PARM_REG \
1465 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1466 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1467 ? FIRST_FP_PARM_REG \
1468 : FIRST_PARM_REG)
1470 /* Define how to find the value returned by a function.
1471 VALTYPE is the data type of the value (as a tree).
1472 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1473 otherwise, FUNC is 0.
1474 For the SH, this is like LIBCALL_VALUE, except that we must change the
1475 mode like PROMOTE_MODE does.
1476 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1477 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1479 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1480 gen_rtx (REG, \
1481 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1482 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1483 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1484 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1485 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1486 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1487 || TREE_CODE (VALTYPE) == REAL_TYPE \
1488 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1489 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1490 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1492 /* Define how to find the value returned by a library function
1493 assuming the value has mode MODE. */
1494 #define LIBCALL_VALUE(MODE) \
1495 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1497 /* 1 if N is a possible register number for a function value. */
1498 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1499 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG) \
1500 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1502 /* 1 if N is a possible register number for function argument passing. */
1503 #define FUNCTION_ARG_REGNO_P(REGNO) \
1504 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG \
1505 + NPARM_REGS (SImode))) \
1506 || (TARGET_FPU_ANY \
1507 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG \
1508 + NPARM_REGS (SFmode))))
1509 \f
1510 /* Define a data type for recording info about an argument list
1511 during the scan of that argument list. This data type should
1512 hold all necessary information about the function itself
1513 and about the args processed so far, enough to enable macros
1514 such as FUNCTION_ARG to determine where the next arg should go.
1516 On SH, this is a single integer, which is a number of words
1517 of arguments scanned so far (including the invisible argument,
1518 if any, which holds the structure-value-address).
1519 Thus NARGREGS or more means all following args should go on the stack. */
1525 /* Non-zero if a prototype is available for the function. */
1527 /* The number of an odd floating-point register, that should be used
1528 for the next argument of type float. */
1530 /* Whether we're processing an outgoing function call. */
1532 /* The number of general-purpose registers that should have been
1533 used to pass partial arguments, that are passed totally on the
1534 stack. On SHcompact, a call trampoline will pop them off the
1535 stack before calling the actual function, and, if the called
1536 function is implemented in SHcompact mode, the incoming arguments
1537 decoder will push such arguments back onto the stack. For
1538 incoming arguments, STACK_REGS also takes into account other
1539 arguments passed by reference, that the decoder will also push
1540 onto the stack. */
1542 /* The number of general-purpose registers that should have been
1543 used to pass arguments, if the arguments didn't have to be passed
1544 by reference. */
1546 /* Set by SHCOMPACT_BYREF if the current argument is to be passed by
1547 reference. */
1550 /* call_cookie is a bitmask used by call expanders, as well as
1551 function prologue and epilogues, to allow SHcompact to comply
1552 with the SH5 32-bit ABI, that requires 64-bit registers to be
1553 used even though only the lower 32-bit half is visible in
1554 SHcompact mode. The strategy is to call SHmedia trampolines.
1556 The alternatives for each of the argument-passing registers are
1557 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1558 contents from the address in it; (d) add 8 to it, storing the
1559 result in the next register, then (c); (e) copy it from some
1560 floating-point register,
1562 Regarding copies from floating-point registers, r2 may only be
1563 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1564 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1565 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1566 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1567 dr10.
1569 The bit mask is structured as follows:
1571 - 1 bit to tell whether to set up a return trampoline.
1573 - 3 bits to count the number consecutive registers to pop off the
1574 stack.
1576 - 4 bits for each of r9, r8, r7 and r6.
1578 - 3 bits for each of r5, r4, r3 and r2.
1580 - 3 bits set to 0 (the most significant ones)
1582 3 2 1 0
1583 1098 7654 3210 9876 5432 1098 7654 3210
1584 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1585 2223 3344 4555 6666 7777 8888 9999 SSS-
1587 - If F is set, the register must be copied from an FP register,
1588 whose number is encoded in the remaining bits.
1590 - Else, if L is set, the register must be loaded from the address
1591 contained in it. If the P bit is *not* set, the address of the
1592 following dword should be computed first, and stored in the
1593 following register.
1595 - Else, if P is set, the register alone should be popped off the
1596 stack.
1598 - After all this processing, the number of registers represented
1599 in SSS will be popped off the stack. This is an optimization
1600 for pushing/popping consecutive registers, typically used for
1601 varargs and large arguments partially passed in registers.
1603 - If T is set, a return trampoline will be set up for 64-bit
1604 return values to be split into 2 32-bit registers. */
1605 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1606 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1607 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1608 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1609 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1610 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1611 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1612 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1613 #define CALL_COOKIE_INT_REG(REG, VAL) \
1614 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1615 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1616 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1618 };
1620 #define CUMULATIVE_ARGS struct sh_args
1622 #define GET_SH_ARG_CLASS(MODE) \
1623 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1624 ? SH_ARG_FLOAT \
1625 /* There's no mention of complex float types in the SH5 ABI, so we
1627 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1628 ? SH_ARG_INT \
1629 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1630 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1631 ? SH_ARG_FLOAT : SH_ARG_INT)
1633 #define ROUND_ADVANCE(SIZE) \
1634 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1636 /* Round a register number up to a proper boundary for an arg of mode
1637 MODE.
1639 The SH doesn't care about double alignment, so we only
1640 round doubles to even regs when asked to explicitly. */
1642 #define ROUND_REG(CUM, MODE) \
1643 (((TARGET_ALIGN_DOUBLE \
1644 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1645 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1646 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1647 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1648 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1649 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1651 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1652 for a call to a function whose data type is FNTYPE.
1653 For a library call, FNTYPE is 0.
1655 On SH, the offset always starts at 0: the first parm reg is always
1656 the same reg for a given argument class.
1658 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1660 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1661 do { \
1662 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1663 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
1664 (CUM).force_mem \
1665 = (TARGET_HITACHI && FNTYPE \
1666 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1667 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
1668 (CUM).arg_count[(int) SH_ARG_INT] \
1669 = (TARGET_SH5 && (FNTYPE) \
1670 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1671 (CUM).free_single_fp_reg = 0; \
1672 (CUM).outgoing = 1; \
1673 (CUM).stack_regs = 0; \
1674 (CUM).byref_regs = 0; \
1675 (CUM).byref = 0; \
1676 (CUM).call_cookie \
1677 = (CALL_COOKIE_RET_TRAMP \
1678 (TARGET_SHCOMPACT && (FNTYPE) \
1679 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
1680 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
1681 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
1682 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
1683 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
1684 (FNTYPE))) \
1685 == FIRST_RET_REG))); \
1686 } while (0)
1688 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1689 do { \
1690 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0); \
1691 (CUM).call_cookie \
1692 = (CALL_COOKIE_RET_TRAMP \
1693 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
1694 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
1695 } while (0)
1697 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1698 do { \
1699 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0); \
1700 (CUM).outgoing = 0; \
1701 } while (0)
1703 /* FIXME: This is overly conservative. A SHcompact function that
1704 receives arguments ``by reference'' will have them stored in its
1705 own stack frame, so it must not pass pointers or references to
1706 these arguments to other functions by means of sibling calls. */
1707 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1708 (! TARGET_SHCOMPACT || current_function_args_info.stack_regs == 0)
1710 /* Update the data in CUM to advance over an argument
1711 of mode MODE and data type TYPE.
1712 (TYPE is null for libcalls where that information may not be
1713 available.) */
1715 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1716 if ((CUM).force_mem) \
1717 (CUM).force_mem = 0; \
1718 else if (TARGET_SH5) \
1719 { \
1720 tree TYPE_ = ((CUM).byref && (TYPE) \
1721 ? TREE_TYPE (TYPE) \
1722 : (TYPE)); \
1723 enum machine_mode MODE_ = ((CUM).byref && (TYPE) \
1724 ? TYPE_MODE (TYPE_) \
1725 : (MODE)); \
1726 int dwords = (((CUM).byref \
1727 ? (CUM).byref \
1728 : (MODE_) == BLKmode \
1729 ? int_size_in_bytes (TYPE_) \
1730 : GET_MODE_SIZE (MODE_)) + 7) / 8; \
1731 int numregs = MIN (dwords, NPARM_REGS (SImode) \
1732 - (CUM).arg_count[(int) SH_ARG_INT]); \
1733 \
1734 if (numregs) \
1735 { \
1736 (CUM).arg_count[(int) SH_ARG_INT] += numregs; \
1737 if (TARGET_SHCOMPACT \
1738 && SHCOMPACT_FORCE_ON_STACK (MODE_, TYPE_)) \
1739 { \
1740 (CUM).call_cookie \
1741 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1742 - numregs), 1); \
1744 (CUM).stack_regs += numregs; \
1745 } \
1746 else if ((CUM).byref) \
1747 { \
1748 if (! (CUM).outgoing) \
1749 (CUM).stack_regs += numregs; \
1750 (CUM).byref_regs += numregs; \
1751 (CUM).byref = 0; \
1752 do \
1753 (CUM).call_cookie \
1754 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1755 - numregs), 2); \
1756 while (--numregs); \
1757 (CUM).call_cookie \
1758 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1759 - 1), 1); \
1760 } \
1761 else if (dwords > numregs) \
1762 { \
1763 int pushregs = numregs; \
1764 \
1765 if (TARGET_SHCOMPACT) \
1766 (CUM).stack_regs += numregs; \
1767 while (pushregs < NPARM_REGS (SImode) - 1 \
1768 && (CALL_COOKIE_INT_REG_GET \
1769 ((CUM).call_cookie, \
1770 NPARM_REGS (SImode) - pushregs) \
1771 == 1)) \
1772 { \
1773 (CUM).call_cookie \
1774 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) \
1775 - pushregs, 1); \
1776 pushregs++; \
1777 } \
1778 if (numregs == NPARM_REGS (SImode)) \
1779 (CUM).call_cookie \
1780 |= CALL_COOKIE_INT_REG (0, 1) \
1781 | CALL_COOKIE_STACKSEQ (numregs - 1); \
1782 else \
1783 (CUM).call_cookie \
1784 |= CALL_COOKIE_STACKSEQ (numregs); \
1785 } \
1786 } \
1787 if (GET_SH_ARG_CLASS (MODE_) == SH_ARG_FLOAT \
1788 && ((NAMED) || ! (CUM).prototype_p)) \
1789 { \
1790 if ((MODE_) == SFmode && (CUM).free_single_fp_reg) \
1791 (CUM).free_single_fp_reg = 0; \
1792 else if ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1793 < NPARM_REGS (SFmode)) \
1794 { \
1795 int numfpregs \
1796 = MIN ((GET_MODE_SIZE (MODE_) + 7) / 8 * 2, \
1797 NPARM_REGS (SFmode) \
1798 - (CUM).arg_count[(int) SH_ARG_FLOAT]); \
1799 \
1800 (CUM).arg_count[(int) SH_ARG_FLOAT] += numfpregs; \
1801 \
1802 if (TARGET_SHCOMPACT && ! (CUM).prototype_p) \
1803 { \
1804 if ((CUM).outgoing && numregs > 0) \
1805 do \
1806 { \
1807 (CUM).call_cookie \
1808 |= (CALL_COOKIE_INT_REG \
1809 ((CUM).arg_count[(int) SH_ARG_INT] \
1810 - numregs + ((numfpregs - 2) / 2), \
1811 4 + ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1812 - numfpregs) / 2)); \
1813 } \
1814 while (numfpregs -= 2); \
1815 } \
1816 else if ((MODE_) == SFmode && (NAMED) \
1817 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1818 < NPARM_REGS (SFmode))) \
1819 (CUM).free_single_fp_reg \
1820 = FIRST_FP_PARM_REG - numfpregs \
1821 + (CUM).arg_count[(int) SH_ARG_FLOAT] + 1; \
1822 } \
1823 } \
1824 } \
1825 else if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \
1826 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1827 = (ROUND_REG ((CUM), (MODE)) \
1828 + ((MODE) == BLKmode \
1829 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1830 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
1832 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1833 This macro is only used in this file. */
1835 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1836 (((TYPE) == 0 \
1837 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1838 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
1839 && ! (CUM).force_mem \
1840 && (TARGET_SH3E \
1841 ? ((MODE) == BLKmode \
1842 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1843 + int_size_in_bytes (TYPE)) \
1844 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1845 : ((ROUND_REG((CUM), (MODE)) \
1846 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1847 <= NPARM_REGS (MODE))) \
1848 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1850 /* Define where to put the arguments to a function.
1851 Value is zero to push the argument on the stack,
1852 or a hard register in which to store the argument.
1854 MODE is the argument's machine mode.
1855 TYPE is the data type of the argument (as a tree).
1856 This is null for libcalls where that information may
1857 not be available.
1858 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1859 the preceding args and about the function being called.
1860 NAMED is nonzero if this argument is a named parameter
1861 (otherwise it is an extra parameter matching an ellipsis).
1863 On SH the first args are normally in registers
1864 and the rest are pushed. Any arg that starts within the first
1865 NPARM_REGS words is at least partially passed in a register unless
1866 its data type forbids. */
1868 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1869 ((! TARGET_SH5 \
1870 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1871 && ((NAMED) || !TARGET_HITACHI)) \
1872 ? gen_rtx_REG ((MODE), \
1873 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
1874 ^ ((MODE) == SFmode && TARGET_SH4 \
1875 && TARGET_LITTLE_ENDIAN != 0))) \
1876 : TARGET_SH5 \
1877 ? ((MODE) == VOIDmode && TARGET_SHCOMPACT \
1878 ? GEN_INT ((CUM).call_cookie) \
1879 /* The following test assumes unnamed arguments are promoted to \
1881 : (MODE) == SFmode && (CUM).free_single_fp_reg \
1882 ? SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), (CUM).free_single_fp_reg) \
1883 : (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
1884 && ((NAMED) || ! (CUM).prototype_p) \
1885 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode)) \
1886 ? ((! (CUM).prototype_p && TARGET_SHMEDIA) \
1887 ? SH5_PROTOTYPELESS_FLOAT_ARG ((CUM), (MODE)) \
1888 : SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), \
1889 FIRST_FP_PARM_REG \
1890 + (CUM).arg_count[(int) SH_ARG_FLOAT])) \
1891 : ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1892 && (! TARGET_SHCOMPACT \
1893 || (! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
1894 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
1895 (TYPE), (NAMED))))) \
1896 ? gen_rtx_REG ((MODE), (FIRST_PARM_REG \
1897 + (CUM).arg_count[(int) SH_ARG_INT])) \
1898 : 0) \
1899 : 0)
1901 /* Whether an argument must be passed by reference. On SHcompact, we
1902 pretend arguments wider than 32-bits that would have been passed in
1903 registers are passed by reference, so that an SHmedia trampoline
1904 loads them into the full 64-bits registers. */
1905 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM,MODE,TYPE,NAMED) \
1906 (MUST_PASS_IN_STACK ((MODE), (TYPE)) \
1907 || SHCOMPACT_BYREF ((CUM), (MODE), (TYPE), (NAMED)))
1909 #define SHCOMPACT_BYREF(CUM, MODE, TYPE, NAMED) \
1910 ((CUM).byref \
1911 = (TARGET_SHCOMPACT \
1912 && (CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1913 && (! (NAMED) || GET_SH_ARG_CLASS (MODE) == SH_ARG_INT \
1914 || (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
1915 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1916 >= NPARM_REGS (SFmode)))) \
1917 && ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1918 : GET_MODE_SIZE (MODE)) > 4 \
1919 && ! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
1920 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
1921 (TYPE), (NAMED))) \
1922 ? ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1923 : GET_MODE_SIZE (MODE)) \
1924 : 0)
1926 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1927 register in SHcompact mode, it must be padded in the most
1928 significant end. This means that passing it by reference wouldn't
1929 pad properly on a big-endian machine. In this particular case, we
1930 pass this argument on the stack, in a way that the call trampoline
1931 will load its value into the appropriate register. */
1932 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1933 ((MODE) == BLKmode \
1934 && TARGET_SHCOMPACT \
1935 && ! TARGET_LITTLE_ENDIAN \
1936 && int_size_in_bytes (TYPE) > 4 \
1937 && int_size_in_bytes (TYPE) < 8)
1939 /* Minimum alignment for an argument to be passed by callee-copy
1940 reference. We need such arguments to be aligned to 8 byte
1941 boundaries, because they'll be loaded using quad loads. */
1942 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1944 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
1945 ((CUM).outgoing \
1946 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
1947 : GET_MODE_ALIGNMENT (MODE)) \
1948 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
1950 /* The SH5 ABI requires floating-point arguments to be passed to
1951 functions without a prototype in both an FP register and a regular
1952 register or the stack. When passing the argument in both FP and
1953 general-purpose registers, list the FP register first. */
1954 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1955 (gen_rtx_PARALLEL \
1956 ((MODE), \
1957 gen_rtvec (2, \
1958 gen_rtx_EXPR_LIST \
1959 (VOIDmode, \
1960 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1961 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1962 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1963 : NULL_RTX), \
1964 const0_rtx), \
1965 gen_rtx_EXPR_LIST \
1966 (VOIDmode, \
1967 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1968 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1969 + (CUM).arg_count[(int) SH_ARG_INT]) \
1970 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1971 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1972 const0_rtx))))
1974 /* The SH5 ABI requires regular registers or stack slots to be
1975 reserved for floating-point arguments. Registers are taken care of
1976 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1977 Unfortunately, there's no way to just reserve a stack slot, so
1978 we'll end up needlessly storing a copy of the argument in the
1979 stack. For incoming arguments, however, the PARALLEL will be
1980 optimized to the register-only form, and the value in the stack
1981 slot won't be used at all. */
1982 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1983 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1984 ? gen_rtx_REG ((MODE), (REG)) \
1985 : gen_rtx_PARALLEL ((MODE), \
1986 gen_rtvec (2, \
1987 gen_rtx_EXPR_LIST \
1988 (VOIDmode, NULL_RTX, \
1989 const0_rtx), \
1990 gen_rtx_EXPR_LIST \
1991 (VOIDmode, gen_rtx_REG ((MODE), \
1992 (REG)), \
1993 const0_rtx))))
1995 #define STRICT_ARGUMENT_NAMING TARGET_SH5
1997 #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI && ! TARGET_SH5)
1999 /* For an arg passed partly in registers and partly in memory,
2000 this is the number of registers used.
2001 For args passed entirely in registers or entirely in memory, zero.
2003 We sometimes split args. */
2005 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2006 ((! TARGET_SH5 \
2007 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2008 && ! TARGET_SH4 \
2009 && (ROUND_REG ((CUM), (MODE)) \
2010 + ((MODE) != BLKmode \
2011 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
2012 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
2013 > NPARM_REGS (MODE))) \
2014 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
2015 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
2016 && ! TARGET_SHCOMPACT) \
2017 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
2018 : 0)
2020 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2021 (TARGET_SH5 && (MODE) == BLKmode \
2022 && ((CUM).arg_count[(int) SH_ARG_INT] \
2023 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2025 /* Perform any needed actions needed for a function that is receiving a
2026 variable number of arguments. */
2028 /* We actually emit the code in sh_expand_prologue. We used to use
2029 a static variable to flag that we need to emit this code, but that
2030 doesn't when inlining, when functions are deferred and then emitted
2031 later. Fortunately, we already have two flags that are part of struct
2032 function that tell if a function uses varargs or stdarg. */
2033 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) do \
2034 if (! current_function_stdarg) \
2035 abort (); \
2036 while (0)
2038 /* Define the `__builtin_va_list' type for the ABI. */
2039 #define BUILD_VA_LIST_TYPE(VALIST) \
2040 (VALIST) = sh_build_va_list ()
2042 /* Implement `va_start' for varargs and stdarg. */
2043 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2044 sh_va_start (valist, nextarg)
2046 /* Implement `va_arg'. */
2047 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2048 sh_va_arg (valist, type)
2050 /* Call the function profiler with a given profile label.
2051 We use two .aligns, so as to make sure that both the .long is aligned
2052 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2053 from the trapa instruction. */
2055 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2056 { \
2061 }
2063 /* Define this macro if the code for function profiling should come
2064 before the function prologue. Normally, the profiling code comes
2065 after. */
2067 #define PROFILE_BEFORE_PROLOGUE
2069 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2070 the stack pointer does not matter. The value is tested only in
2071 functions that have frame pointers.
2072 No definition is equivalent to always zero. */
2074 #define EXIT_IGNORE_STACK 1
2076 /*
2077 On the SH, the trampoline looks like
2078 2 0002 D202 mov.l l2,r2
2079 1 0000 D301 mov.l l1,r3
2080 3 0004 422B jmp @r2
2081 4 0006 0009 nop
2082 5 0008 00000000 l1: .long area
2083 6 000c 00000000 l2: .long function */
2085 /* Length in units of the trampoline for entering a nested function. */
2086 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2088 /* Alignment required for a trampoline in bits . */
2089 #define TRAMPOLINE_ALIGNMENT \
2090 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2091 : TARGET_SHMEDIA ? 256 : 64)
2093 /* Emit RTL insns to initialize the variable parts of a trampoline.
2094 FNADDR is an RTX for the address of the function's pure code.
2095 CXT is an RTX for the static chain value for the function. */
2097 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2098 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2100 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2102 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2103 { \
2104 if (TARGET_SHMEDIA) \
2105 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), GEN_INT (1), \
2106 gen_reg_rtx (Pmode), 0, \
2107 OPTAB_LIB_WIDEN); \
2108 } while (0)
2110 /* A C expression whose value is RTL representing the value of the return
2111 address for the frame COUNT steps up from the current frame.
2112 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2113 can ignore COUNT. */
2115 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2116 (((COUNT) == 0) \
2117 ? get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
2118 : (rtx) 0)
2120 /* A C expression whose value is RTL representing the location of the
2121 incoming return address at the beginning of any function, before the
2122 prologue. This RTL is either a REG, indicating that the return
2123 value is saved in REG, or a MEM representing a location in
2124 the stack. */
2125 #define INCOMING_RETURN_ADDR_RTX \
2126 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2127 \f
2128 /* Generate necessary RTL for __builtin_saveregs(). */
2129 #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
2130 \f
2131 /* Addressing modes, and classification of registers for them. */
2132 #define HAVE_POST_INCREMENT TARGET_SH1
2133 /*#define HAVE_PRE_INCREMENT 1*/
2134 /*#define HAVE_POST_DECREMENT 1*/
2135 #define HAVE_PRE_DECREMENT TARGET_SH1
2137 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2138 ? 0 : TARGET_SH1)
2139 #define USE_LOAD_PRE_DECREMENT(mode) 0
2140 #define USE_STORE_POST_INCREMENT(mode) 0
2141 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2142 ? 0 : TARGET_SH1)
2144 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2145 < (TARGET_SMALLCODE ? 2 : \
2146 ((ALIGN >= 32) ? 16 : 2)))
2148 /* Macros to check register numbers against specific register classes. */
2150 /* These assume that REGNO is a hard or pseudo reg number.
2151 They give nonzero only if REGNO is a hard reg of the suitable class
2152 or a pseudo reg currently allocated to a suitable hard reg.
2153 Since they use reg_renumber, they are safe only once reg_renumber
2154 has been allocated, which happens in local-alloc.c. */
2156 #define REGNO_OK_FOR_BASE_P(REGNO) \
2157 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2158 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2159 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2160 (TARGET_SHMEDIA \
2161 ? (GENERAL_REGISTER_P (REGNO) \
2162 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2163 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2165 /* Maximum number of registers that can appear in a valid memory
2166 address. */
2168 #define MAX_REGS_PER_ADDRESS 2
2170 /* Recognize any constant value that is a valid address. */
2172 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2174 /* Nonzero if the constant value X is a legitimate general operand. */
2176 #define LEGITIMATE_CONSTANT_P(X) \
2177 (TARGET_SHMEDIA \
2178 ? ((GET_MODE (X) != DFmode \
2179 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2180 || (X) == CONST0_RTX (GET_MODE (X)) \
2181 || ! TARGET_SHMEDIA_FPU \
2182 || TARGET_SHMEDIA64) \
2183 : (GET_CODE (X) != CONST_DOUBLE \
2184 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2185 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X)))))
2187 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2188 and check its validity for a certain class.
2189 We have two alternate definitions for each of them.
2190 The usual definition accepts all pseudo regs; the other rejects
2191 them unless they have been allocated suitable hard regs.
2192 The symbol REG_OK_STRICT causes the latter definition to be used. */
2194 #ifndef REG_OK_STRICT
2196 /* Nonzero if X is a hard reg that can be used as a base reg
2197 or if it is a pseudo reg. */
2198 #define REG_OK_FOR_BASE_P(X) \
2199 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2201 /* Nonzero if X is a hard reg that can be used as an index
2202 or if it is a pseudo reg. */
2203 #define REG_OK_FOR_INDEX_P(X) \
2204 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2205 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2207 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2208 or if X is a pseudo reg. */
2209 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2210 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2211 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2213 #else
2215 /* Nonzero if X is a hard reg that can be used as a base reg. */
2216 #define REG_OK_FOR_BASE_P(X) \
2217 REGNO_OK_FOR_BASE_P (REGNO (X))
2219 /* Nonzero if X is a hard reg that can be used as an index. */
2220 #define REG_OK_FOR_INDEX_P(X) \
2221 REGNO_OK_FOR_INDEX_P (REGNO (X))
2223 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2224 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2225 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2227 #endif
2229 /* The 'Q' constraint is a pc relative load operand. */
2230 #define EXTRA_CONSTRAINT_Q(OP) \
2231 (GET_CODE (OP) == MEM \
2232 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2233 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2234 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2235 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2236 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2238 /* The `S' constraint is a 16-bit constant, literal or symbolic. */
2239 #define EXTRA_CONSTRAINT_S(OP) \
2240 (GET_CODE (OP) == CONST \
2241 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2242 && GET_MODE (XEXP ((OP), 0)) == DImode \
2243 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2244 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2245 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2246 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2247 && (MOVI_SHORI_BASE_OPERAND_P \
2248 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2249 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2250 1)) == CONST_INT)))
2252 /* Check whether OP is a datalabel unspec. */
2253 #define DATALABEL_REF_NO_CONST_P(OP) \
2254 (GET_CODE (OP) == UNSPEC \
2255 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2256 && XVECLEN ((OP), 0) == 1 \
2257 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2258 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2260 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2261 CONST. */
2262 #define DATALABEL_REF_P(OP) \
2263 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2264 || DATALABEL_REF_NO_CONST_P (OP))
2266 #define GOT_ENTRY_P(OP) \
2267 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2268 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2270 #define GOTPLT_ENTRY_P(OP) \
2271 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2272 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2274 #define GOTOFF_P(OP) \
2275 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2276 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTOFF)
2278 #define PIC_ADDR_P(OP) \
2279 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2280 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2282 #define NON_PIC_REFERENCE_P(OP) \
2283 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2284 || DATALABEL_REF_P (OP) \
2285 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2286 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2287 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2288 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2290 #define PIC_REFERENCE_P(OP) \
2291 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2292 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2294 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2295 (flag_pic ? PIC_REFERENCE_P (OP) : NON_PIC_REFERENCE_P (OP))
2297 /* The `T' constraint is a label or a symbol. */
2298 #define EXTRA_CONSTRAINT_T(OP) \
2299 (NON_PIC_REFERENCE_P (OP))
2301 /* A zero in any shape or form. */
2302 #define EXTRA_CONSTRAINT_U(OP) \
2303 ((OP) == CONST0_RTX (GET_MODE (OP)))
2305 /* Any vector constant we can handle. */
2306 #define EXTRA_CONSTRAINT_W(OP) \
2307 (GET_CODE (OP) == CONST_VECTOR \
2308 && (sh_rep_vec ((OP), VOIDmode) \
2309 || (HOST_BITS_PER_WIDE_INT >= 64 \
2310 ? sh_const_vec ((OP), VOIDmode) \
2311 : sh_1el_vec ((OP), VOIDmode))))
2313 #define EXTRA_CONSTRAINT(OP, C) \
2319 : 0)
2320 \f
2321 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2322 that is a valid memory address for an instruction.
2323 The MODE argument is the machine mode for the MEM expression
2324 that wants to use this address. */
2326 #define MODE_DISP_OK_4(X,MODE) \
2327 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2328 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode))
2330 #define MODE_DISP_OK_8(X,MODE) \
2331 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2332 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2334 #define BASE_REGISTER_RTX_P(X) \
2335 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2336 || (GET_CODE (X) == SUBREG \
2337 && GET_CODE (SUBREG_REG (X)) == REG \
2338 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2340 /* Since this must be r0, which is a single register class, we must check
2341 SUBREGs more carefully, to be sure that we don't accept one that extends
2342 outside the class. */
2343 #define INDEX_REGISTER_RTX_P(X) \
2344 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2345 || (GET_CODE (X) == SUBREG \
2346 && GET_CODE (SUBREG_REG (X)) == REG \
2347 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2349 /* Jump to LABEL if X is a valid address RTX. This must also take
2350 REG_OK_STRICT into account when deciding about valid registers, but it uses
2351 the above macros so we are in luck.
2353 Allow REG
2354 REG+disp
2355 REG+r0
2356 REG++
2357 --REG */
2359 /* ??? The SH3e does not have the REG+disp addressing mode when loading values
2360 into the FRx registers. We implement this by setting the maximum offset
2361 to zero when the value is SFmode. This also restricts loading of SFmode
2362 values into the integer registers, but that can't be helped. */
2364 /* The SH allows a displacement in a QI or HI amode, but only when the
2365 other operand is R0. GCC doesn't handle this very well, so we forgo
2366 all of that.
2368 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2369 DI can be any number 0..60. */
2371 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2372 do { \
2373 if (GET_CODE (OP) == CONST_INT) \
2374 { \
2375 if (TARGET_SHMEDIA) \
2376 { \
2377 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2378 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2379 && INTVAL (OP) >= -512 * MODE_SIZE \
2380 && INTVAL (OP) < 512 * MODE_SIZE) \
2381 goto LABEL; \
2382 else \
2383 break; \
2384 } \
2385 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2386 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2387 } \
2388 } while(0)
2390 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2391 { \
2392 if (BASE_REGISTER_RTX_P (X)) \
2393 goto LABEL; \
2394 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2395 && ! TARGET_SHMEDIA \
2396 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2397 goto LABEL; \
2398 else if (GET_CODE (X) == PLUS \
2399 && ((MODE) != PSImode || reload_completed)) \
2400 { \
2401 rtx xop0 = XEXP ((X), 0); \
2402 rtx xop1 = XEXP ((X), 1); \
2403 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2404 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2405 if (GET_MODE_SIZE (MODE) <= 4 \
2406 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2407 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
2408 { \
2409 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2410 goto LABEL; \
2411 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2412 goto LABEL; \
2413 } \
2414 } \
2415 }
2416 \f
2417 /* Try machine-dependent ways of modifying an illegitimate address
2418 to be legitimate. If we find one, return the new, valid address.
2419 This macro is used in only one place: `memory_address' in explow.c.
2421 OLDX is the address as it was before break_out_memory_refs was called.
2422 In some cases it is useful to look at this to decide what needs to be done.
2424 MODE and WIN are passed so that this macro can use
2425 GO_IF_LEGITIMATE_ADDRESS.
2427 It is always safe for this macro to do nothing. It exists to recognize
2428 opportunities to optimize the output.
2430 For the SH, if X is almost suitable for indexing, but the offset is
2431 out of range, convert it into a normal form so that cse has a chance
2432 of reducing the number of address registers used. */
2434 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2435 { \
2436 if (flag_pic) \
2437 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2438 if (GET_CODE (X) == PLUS \
2439 && (GET_MODE_SIZE (MODE) == 4 \
2440 || GET_MODE_SIZE (MODE) == 8) \
2441 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2442 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2443 && ! TARGET_SHMEDIA \
2444 && ! (TARGET_SH4 && (MODE) == DFmode) \
2445 && ! (TARGET_SH3E && (MODE) == SFmode)) \
2446 { \
2447 rtx index_rtx = XEXP ((X), 1); \
2448 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2449 rtx sum; \
2450 \
2451 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2452 /* On rare occasions, we might get an unaligned pointer \
2453 that is indexed in a way to give an aligned address. \
2455 /* Instead of offset_base 128..131 use 124..127, so that \
2457 if (offset > 127) \
2458 { \
2459 offset_base = ((offset + 4) & ~60) - 4; \
2460 } \
2461 else \
2462 offset_base = offset & ~60; \
2463 /* Sometimes the normal form does not suit DImode. We \
2464 could avoid that by using smaller ranges, but that \
2465 would give less optimized code when SImode is \
2467 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2468 { \
2469 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2470 GEN_INT (offset_base), NULL_RTX, 0, \
2471 OPTAB_LIB_WIDEN); \
2472 \
2473 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2474 goto WIN; \
2475 } \
2476 } \
2477 }
2479 /* A C compound statement that attempts to replace X, which is an address
2480 that needs reloading, with a valid memory address for an operand of
2481 mode MODE. WIN is a C statement label elsewhere in the code.
2483 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2484 of the address. That will allow inheritance of the address reloads. */
2486 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2487 { \
2488 if (GET_CODE (X) == PLUS \
2489 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2490 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2491 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2492 && ! TARGET_SHMEDIA \
2493 && ! (TARGET_SH4 && (MODE) == DFmode) \
2494 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2495 { \
2496 rtx index_rtx = XEXP (X, 1); \
2497 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2498 rtx sum; \
2499 \
2500 if (TARGET_SH3E && MODE == SFmode) \
2501 { \
2502 X = copy_rtx (X); \
2503 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2504 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2505 (TYPE)); \
2506 goto WIN; \
2507 } \
2508 /* Instead of offset_base 128..131 use 124..127, so that \
2510 if (offset > 127) \
2511 { \
2512 offset_base = ((offset + 4) & ~60) - 4; \
2513 } \
2514 else \
2515 offset_base = offset & ~60; \
2516 /* Sometimes the normal form does not suit DImode. We \
2517 could avoid that by using smaller ranges, but that \
2518 would give less optimized code when SImode is \
2520 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2521 { \
2522 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2523 GEN_INT (offset_base)); \
2524 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
2525 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2526 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2527 (TYPE)); \
2528 goto WIN; \
2529 } \
2530 } \
2532 else if (GET_CODE (X) == PLUS \
2533 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2534 && GET_CODE (XEXP (X, 0)) == PLUS \
2535 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2536 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2537 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2538 && ! TARGET_SHMEDIA \
2539 && ! (TARGET_SH3E && MODE == SFmode)) \
2540 { \
2541 /* Because this address is so complex, we know it must have \
2542 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2544 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2545 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2546 goto WIN; \
2547 } \
2548 }
2550 /* Go to LABEL if ADDR (a legitimate address expression)
2551 has an effect that depends on the machine mode it is used for.
2553 ??? Strictly speaking, we should also include all indexed addressing,
2554 because the index scale factor is the length of the operand.
2555 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2556 high if we did that. So we rely on reload to fix things up. */
2558 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2559 { \
2560 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2561 goto LABEL; \
2562 }
2563 \f
2564 /* Specify the machine mode that this machine uses
2565 for the index in the tablejump instruction. */
2566 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
2568 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2569 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2570 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2571 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2572 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2573 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2574 : SImode)
2576 /* Define as C expression which evaluates to nonzero if the tablejump
2577 instruction expects the table to contain offsets from the address of the
2578 table.
2579 Do not define this if the table should contain absolute addresses. */
2580 #define CASE_VECTOR_PC_RELATIVE 1
2582 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2583 #define FLOAT_TYPE_SIZE 32
2585 /* Since the SH3e has only `float' support, it is desirable to make all
2586 floating point types equivalent to `float'. */
2587 #define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64)
2589 /* 'char' is signed by default. */
2590 #define DEFAULT_SIGNED_CHAR 1
2592 /* The type of size_t unsigned int. */
2595 #undef PTRDIFF_TYPE
2599 #define WCHAR_TYPE_SIZE 16
2603 /* Don't cse the address of the function being compiled. */
2604 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
2606 /* Max number of bytes we can move from memory to memory
2607 in one reasonably fast instruction. */
2608 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2610 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2611 MOVE_MAX is not a compile-time constant. */
2612 #define MAX_MOVE_MAX 8
2614 /* Max number of bytes we want move_by_pieces to be able to copy
2615 efficiently. */
2616 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2618 /* Define if operations between registers always perform the operation
2619 on the full register even if a narrower mode is specified. */
2620 #define WORD_REGISTER_OPERATIONS
2622 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2623 will either zero-extend or sign-extend. The value of this macro should
2624 be the code that says which one of the two operations is implicitly
2625 done, NIL if none. */
2626 /* FP registers can load SImode values, but don't implicitly sign-extend
2627 them to DImode. */
2628 #define LOAD_EXTEND_OP(MODE) ((MODE) != SImode ? SIGN_EXTEND : NIL)
2630 /* Define if loading short immediate values into registers sign extends. */
2631 #define SHORT_IMMEDIATES_SIGN_EXTEND
2633 /* Nonzero if access to memory by bytes is no faster than for words. */
2634 #define SLOW_BYTE_ACCESS 1
2636 /* We assume that the store-condition-codes instructions store 0 for false
2637 and some other value for true. This is the value stored for true. */
2639 #define STORE_FLAG_VALUE 1
2641 /* Immediate shift counts are truncated by the output routines (or was it
2642 the assembler?). Shift counts in a register are truncated by SH. Note
2643 that the native compiler puts too large (> 32) immediate shift counts
2644 into a register and shifts by the register, letting the SH decide what
2645 to do instead of doing that itself. */
2646 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2647 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2648 expects - the sign bit is significant - so it appears that we need to
2649 leave this zero for correct SH3 code. */
2650 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
2652 /* All integers have the same format so truncation is easy. */
2653 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2655 /* Define this if addresses of constant functions
2656 shouldn't be put through pseudo regs where they can be cse'd.
2657 Desirable on machines where ordinary constants are expensive
2658 but a CALL with constant address is cheap. */
2659 /*#define NO_FUNCTION_CSE 1*/
2661 /* Chars and shorts should be passed as ints. */
2662 #define PROMOTE_PROTOTYPES 1
2664 /* The machine modes of pointers and functions. */
2665 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2666 #define FUNCTION_MODE Pmode
2668 /* The relative costs of various types of constants. */
2670 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2671 case CONST_INT: \
2672 if (TARGET_SHMEDIA) \
2673 { \
2674 if (INTVAL (RTX) == 0) \
2675 return 0; \
2676 if ((OUTER_CODE) == AND && and_operand ((RTX), DImode)) \
2677 return 0; \
2678 if (((OUTER_CODE) == IOR || (OUTER_CODE) == XOR \
2679 || (OUTER_CODE) == PLUS) \
2680 && CONST_OK_FOR_P (INTVAL (RTX))) \
2681 return 0; \
2682 if (CONST_OK_FOR_J (INTVAL (RTX))) \
2683 return COSTS_N_INSNS ((OUTER_CODE) != SET); \
2684 else if (CONST_OK_FOR_J (INTVAL (RTX) >> 16)) \
2685 return COSTS_N_INSNS (2); \
2686 else if (CONST_OK_FOR_J ((INTVAL (RTX) >> 16) >> 16)) \
2687 return COSTS_N_INSNS (3); \
2688 else \
2689 return COSTS_N_INSNS (4); \
2690 } \
2691 if (CONST_OK_FOR_I (INTVAL (RTX))) \
2692 return 0; \
2693 else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \
2694 && CONST_OK_FOR_L (INTVAL (RTX))) \
2695 return 1; \
2696 else \
2697 return 8; \
2698 case CONST: \
2699 case LABEL_REF: \
2700 case SYMBOL_REF: \
2701 if (TARGET_SHMEDIA64) \
2702 return COSTS_N_INSNS (4); \
2703 if (TARGET_SHMEDIA32) \
2704 return COSTS_N_INSNS (2); \
2705 return 5; \
2706 case CONST_DOUBLE: \
2707 if (TARGET_SHMEDIA) \
2708 return COSTS_N_INSNS (4); \
2709 else \
2710 return 10;
2712 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2713 case PLUS: \
2714 return COSTS_N_INSNS (addsubcosts (X)); \
2715 case AND: \
2716 return COSTS_N_INSNS (andcosts (X)); \
2717 case MULT: \
2718 return COSTS_N_INSNS (multcosts (X)); \
2719 case ASHIFT: \
2720 case ASHIFTRT: \
2721 case LSHIFTRT: \
2722 return COSTS_N_INSNS (shiftcosts (X)); \
2723 case DIV: \
2724 case UDIV: \
2725 case MOD: \
2726 case UMOD: \
2727 return COSTS_N_INSNS (20); \
2728 case FLOAT: \
2729 case FIX: \
2730 return 100;
2732 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2733 are actually function calls with some special constraints on arguments
2734 and register usage.
2736 These macros tell reorg that the references to arguments and
2737 register clobbers for insns of type sfunc do not appear to happen
2738 until after the millicode call. This allows reorg to put insns
2739 which set the argument registers into the delay slot of the millicode
2740 call -- thus they act more like traditional CALL_INSNs.
2742 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2743 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2744 in particular. */
2746 #define INSN_SETS_ARE_DELAYED(X) \
2747 ((GET_CODE (X) == INSN \
2748 && GET_CODE (PATTERN (X)) != SEQUENCE \
2749 && GET_CODE (PATTERN (X)) != USE \
2750 && GET_CODE (PATTERN (X)) != CLOBBER \
2751 && get_attr_is_sfunc (X)))
2753 #define INSN_REFERENCES_ARE_DELAYED(X) \
2754 ((GET_CODE (X) == INSN \
2755 && GET_CODE (PATTERN (X)) != SEQUENCE \
2756 && GET_CODE (PATTERN (X)) != USE \
2757 && GET_CODE (PATTERN (X)) != CLOBBER \
2758 && get_attr_is_sfunc (X)))
2760 \f
2761 /* Position Independent Code. */
2763 /* The prefix used to mark SYMBOL_REFs that refer to data symbols. */
2766 /* Return true if SYM_NAME starts with SH_DATALABEL_ENCODING. */
2767 #define DATALABEL_SYMNAME_P(SYM_NAME) \
2768 (SH_DATALABEL_ENCODING[1] ? (abort (), 0) : \
2769 (SYM_NAME)[0] == SH_DATALABEL_ENCODING[0])
2771 /* Skip an optional SH_DATALABEL_ENCODING in the beginning of
2772 SYM_NAME. Then, remove a leading *, like the default definition in
2773 output.h. */
2774 #define STRIP_DATALABEL_ENCODING(VAR, SYM_NAME) \
2775 (VAR) = (SYM_NAME) + (DATALABEL_SYMNAME_P (SYM_NAME) \
2776 ? strlen (SH_DATALABEL_ENCODING) : 0)
2778 /* We can't directly access anything that contains a symbol,
2779 nor can we indirect via the constant pool. */
2780 #define LEGITIMATE_PIC_OPERAND_P(X) \
2781 (! nonpic_symbol_mentioned_p (X) \
2782 && (GET_CODE (X) != SYMBOL_REF \
2783 || ! CONSTANT_POOL_ADDRESS_P (X) \
2784 || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))
2786 #define SYMBOLIC_CONST_P(X) \
2787 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2788 && nonpic_symbol_mentioned_p (X))
2789 \f
2790 /* Compute the cost of an address. For the SH, all valid addresses are
2791 the same cost. Use a slightly higher cost for reg + reg addressing,
2792 since it increases pressure on r0. */
2794 #define ADDRESS_COST(X) (GET_CODE (X) == PLUS && ! CONSTANT_P (XEXP (X, 1)) \
2795 && ! TARGET_SHMEDIA \
2796 ? 1 : 0)
2798 /* Compute extra cost of moving data between one register class
2799 and another. */
2801 /* Regclass always uses 2 for moves in the same register class;
2802 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair,
2803 it uses this information. Hence, the general register <-> floating point
2804 register information here is not used for SFmode. */
2805 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2806 (((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \
2807 : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS \
2808 || (DSTCLASS) == DF_REGS || (DSTCLASS) == DF_HI_REGS) \
2809 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
2810 || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \
2811 && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \
2812 || (SRCCLASS) == DF_REGS || (SRCCLASS) == DF_HI_REGS))) \
2813 ? (TARGET_SHMEDIA ? 4 \
2814 : TARGET_FMOVD ? 8 : 12) \
2815 : (((DSTCLASS) == FPUL_REGS \
2816 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
2817 || (SRCCLASS == FPUL_REGS \
2818 && ((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS))) \
2819 ? 5 \
2820 : (((DSTCLASS) == FPUL_REGS \
2821 && ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS \
2822 || (SRCCLASS) == T_REGS)) \
2823 || ((SRCCLASS) == FPUL_REGS \
2824 && ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \
2825 ? 7 \
2826 : (((SRCCLASS) == TARGET_REGS && (DSTCLASS) != GENERAL_REGS) \
2827 || ((DSTCLASS) == TARGET_REGS && (SRCCLASS) != GENERAL_REGS)) \
2828 ? 20 \
2829 : (((SRCCLASS) == FPSCR_REGS && (DSTCLASS) != GENERAL_REGS) \
2830 || ((DSTCLASS) == FPSCR_REGS && (SRCCLASS) != GENERAL_REGS)) \
2831 ? 4 \
2832 : 2) * ((MODE) == V16SFmode ? 8 : (MODE) == V4SFmode ? 2 : 1))
2834 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2835 would be so that people with slow memory systems could generate
2836 different code that does fewer memory accesses. */
2838 /* A C expression for the cost of a branch instruction. A value of 1
2839 is the default; other values are interpreted relative to that.
2840 The SH1 does not have delay slots, hence we get a pipeline stall
2841 at every branch. The SH4 is superscalar, so the single delay slot
2842 is not sufficient to keep both pipelines filled. */
2843 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2844 \f
2845 /* Assembler output control. */
2847 /* A C string constant describing how to begin a comment in the target
2848 assembler language. The compiler assumes that the comment will end at
2849 the end of the line. */
2852 /* The text to go at the start of the assembler file. */
2853 #define ASM_FILE_START(STREAM) \
2854 output_file_start (STREAM)
2861 /* How to change between sections. */
2863 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2866 #if defined CRT_BEGIN || defined CRT_END
2867 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2868 # undef TEXT_SECTION_ASM_OP
2869 # if __SHMEDIA__ == 1 && __SH5__ == 32
2871 # else
2873 # endif
2874 #endif
2877 /* If defined, a C expression whose value is a string containing the
2878 assembler operation to identify the following data as
2879 uninitialized global data. If not defined, and neither
2880 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2881 uninitialized global data will be output in the data section if
2882 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2883 used. */
2884 #ifndef BSS_SECTION_ASM_OP
2886 #endif
2888 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2889 separate, explicit argument. If you define this macro, it is used
2890 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2891 handling the required alignment of the variable. The alignment is
2892 specified as the number of bits.
2894 Try to use function `asm_output_aligned_bss' defined in file
2895 `varasm.c' when defining this macro. */
2896 #ifndef ASM_OUTPUT_ALIGNED_BSS
2897 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2898 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2899 #endif
2901 /* Define this so that jump tables go in same section as the current function,
2902 which could be text or it could be a user defined section. */
2903 #define JUMP_TABLES_IN_TEXT_SECTION 1
2905 #undef DO_GLOBAL_CTORS_BODY
2906 #define DO_GLOBAL_CTORS_BODY \
2907 { \
2908 typedef (*pfunc)(); \
2909 extern pfunc __ctors[]; \
2910 extern pfunc __ctors_end[]; \
2911 pfunc *p; \
2912 for (p = __ctors_end; p > __ctors; ) \
2913 { \
2914 (*--p)(); \
2915 } \
2916 }
2918 #undef DO_GLOBAL_DTORS_BODY
2919 #define DO_GLOBAL_DTORS_BODY \
2920 { \
2921 typedef (*pfunc)(); \
2922 extern pfunc __dtors[]; \
2923 extern pfunc __dtors_end[]; \
2924 pfunc *p; \
2925 for (p = __dtors; p < __dtors_end; p++) \
2926 { \
2927 (*p)(); \
2928 } \
2929 }
2931 #define ASM_OUTPUT_REG_PUSH(file, v) \
2934 #define ASM_OUTPUT_REG_POP(file, v) \
2937 /* DBX register number for a given compiler register number. */
2938 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2939 to match gdb. */
2940 /* svr4.h undefines this macro, yet we really want to use the same numbers
2941 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2942 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2944 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2945 (GENERAL_REGISTER_P (REGNO) \
2946 ? ((REGNO) - FIRST_GENERAL_REG) \
2947 : FP_REGISTER_P (REGNO) \
2948 ? ((REGNO) - FIRST_FP_REG + (TARGET_SH5 ? (TARGET_SHCOMPACT ? 245 \
2949 : 77) : 25)) \
2950 : XD_REGISTER_P (REGNO) \
2951 ? ((REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2952 : TARGET_REGISTER_P (REGNO) \
2953 ? ((REGNO) - FIRST_TARGET_REG + 68) \
2954 : (REGNO) == PR_REG \
2955 ? (TARGET_SH5 ? 241 : 17) \
2956 : (REGNO) == T_REG \
2957 ? (TARGET_SH5 ? 242 : 18) \
2958 : (REGNO) == GBR_REG \
2959 ? (TARGET_SH5 ? 238 : 19) \
2960 : (REGNO) == MACH_REG \
2961 ? (TARGET_SH5 ? 239 : 20) \
2962 : (REGNO) == MACL_REG \
2963 ? (TARGET_SH5 ? 240 : 21) \
2964 : (REGNO) == FPUL_REG \
2965 ? (TARGET_SH5 ? 244 : 23) \
2966 : (abort(), -1))
2968 /* This is how to output a reference to a user-level label named NAME. */
2969 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2970 do \
2971 { \
2972 char * lname; \
2973 \
2974 STRIP_DATALABEL_ENCODING (lname, (NAME)); \
2976 fputs (lname + 1, (FILE)); \
2977 else \
2979 } \
2980 while (0)
2982 /* This is how to output a reference to a symbol_ref. On SH5,
2983 references to non-code symbols must be preceded by `datalabel'. */
2984 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2985 do \
2986 { \
2987 if (TARGET_SH5 \
2988 && (DATALABEL_SYMNAME_P (XSTR ((SYM), 0)) \
2989 || CONSTANT_POOL_ADDRESS_P (SYM))) \
2991 assemble_name ((FILE), XSTR ((SYM), 0)); \
2992 } \
2993 while (0)
2995 /* Output a label definition. */
2996 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2999 /* This is how to output an assembler line
3000 that says to advance the location counter
3001 to a multiple of 2**LOG bytes. */
3003 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3004 if ((LOG) != 0) \
3007 /* Output a globalising directive for a label. */
3008 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
3010 assemble_name ((STREAM), (NAME)), \
3013 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3015 /* Construct a private name. */
3016 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
3017 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
3020 /* Output a relative address table. */
3022 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3023 switch (GET_MODE (BODY)) \
3024 { \
3025 case SImode: \
3026 if (TARGET_SH5) \
3027 { \
3029 (VALUE), (REL)); \
3030 break; \
3031 } \
3033 break; \
3034 case HImode: \
3035 if (TARGET_SH5) \
3036 { \
3038 (VALUE), (REL)); \
3039 break; \
3040 } \
3042 break; \
3043 case QImode: \
3044 if (TARGET_SH5) \
3045 { \
3047 (VALUE), (REL)); \
3048 break; \
3049 } \
3051 break; \
3052 default: \
3053 break; \
3054 }
3056 /* Output an absolute table element. */
3058 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3059 if (TARGET_BIGTABLE) \
3061 else \
3064 \f
3065 /* A C statement to be executed just prior to the output of
3066 assembler code for INSN, to modify the extracted operands so
3067 they will be output differently.
3069 Here the argument OPVEC is the vector containing the operands
3070 extracted from INSN, and NOPERANDS is the number of elements of
3071 the vector which contain meaningful data for this insn.
3072 The contents of this vector are what will be used to convert the insn
3073 template into assembler code, so you can change the assembler output
3074 by changing the contents of the vector. */
3076 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3077 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3079 /* Print operand X (an rtx) in assembler syntax to file FILE.
3080 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3081 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3083 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3085 /* Print a memory address as an operand to reference that memory location. */
3087 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3089 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3093 /* Recognize machine-specific patterns that may appear within
3094 constants. Used for PIC-specific UNSPECs. */
3095 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3096 do \
3097 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3098 { \
3099 switch (XINT ((X), 1)) \
3100 { \
3101 case UNSPEC_DATALABEL: \
3103 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3104 break; \
3105 case UNSPEC_PIC: \
3107 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3108 break; \
3109 case UNSPEC_GOT: \
3110 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3112 break; \
3113 case UNSPEC_GOTOFF: \
3114 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3116 break; \
3117 case UNSPEC_PLT: \
3118 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3120 break; \
3121 case UNSPEC_GOTPLT: \
3122 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3124 break; \
3125 case UNSPEC_CALLER: \
3126 { \
3127 char name[32]; \
3129 ASM_GENERATE_INTERNAL_LABEL \
3131 assemble_name ((STREAM), name); \
3132 } \
3133 break; \
3134 default: \
3135 goto FAIL; \
3136 } \
3137 break; \
3138 } \
3139 else \
3140 goto FAIL; \
3141 while (0)
3143 \f
3147 /* Which processor to schedule for. The elements of the enumeration must
3148 match exactly the cpu attribute in the sh.md file. */
3151 PROCESSOR_SH1,
3152 PROCESSOR_SH2,
3153 PROCESSOR_SH3,
3154 PROCESSOR_SH3E,
3155 PROCESSOR_SH4,
3156 PROCESSOR_SH5
3157 };
3159 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3164 enum mdep_reorg_phase_e
3165 {
3166 SH_BEFORE_MDEP_REORG,
3167 SH_INSERT_USES_LABELS,
3168 SH_SHORTEN_BRANCHES0,
3169 SH_FIXUP_PCLOAD,
3170 SH_SHORTEN_BRANCHES1,
3171 SH_AFTER_MDEP_REORG
3172 };
3176 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
3178 /* Generate calls to memcpy, memcmp and memset. */
3180 #define TARGET_MEM_FUNCTIONS
3182 /* Handle Hitachi compiler's pragmas. */
3183 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
3187 } while (0)
3189 /* Set when processing a function with pragma interrupt turned on. */
3193 /* Set when processing a function with interrupt attribute. */
3197 /* Set to an RTX containing the address of the stack to switch to
3198 for interrupt functions. */
3203 \f
3204 /* Instructions with unfilled delay slots take up an
3205 extra two bytes for the nop in the delay slot.
3206 sh-dsp parallel processing insns are four bytes long. */
3208 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3209 (LENGTH) += sh_insn_length_adjustment (X);
3210 \f
3211 /* Define the codes that are matched by predicates in sh.c. */
3212 #define PREDICATE_CODES \
3248 #define SPECIAL_MODE_PREDICATES \
3252 /* This line intentionally left blank. */
3254 #define any_register_operand register_operand
3256 /* Define this macro if it is advisable to hold scalars in registers
3257 in a wider mode than that declared by the program. In such cases,
3258 the value is constrained to be within the bounds of the declared
3259 type, but kept valid in the wider mode. The signedness of the
3260 extension may differ from that of the type.
3262 Leaving the unsignedp unchanged gives better code than always setting it
3263 to 0. This is despite the fact that we have only signed char and short
3264 load instructions. */
3265 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3266 if (GET_MODE_CLASS (MODE) == MODE_INT \
3267 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3268 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3269 (MODE) = (TARGET_SH1 ? SImode : DImode);
3271 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
3272 extensions applied to char/short functions arguments. Defining
3273 PROMOTE_FUNCTION_RETURN does the same for function returns. */
3275 #define PROMOTE_FUNCTION_ARGS
3276 #define PROMOTE_FUNCTION_RETURN
3278 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3279 and poping arguments. However, we do have push/pop instructions, and
3280 rather limited offsets (4 bits) in load/store instructions, so it isn't
3281 clear if this would give better code. If implemented, should check for
3282 compatibility problems. */
3284 #define SH_DYNAMIC_SHIFT_COST \
3285 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3288 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3290 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
3292 #define NORMAL_MODE(ENTITY) \
3293 (sh_cfun_interrupt_handler_p () ? FP_MODE_NONE \
3294 : TARGET_FPU_SINGLE ? FP_MODE_SINGLE \
3295 : FP_MODE_DOUBLE)
3297 #define EPILOGUE_USES(REGNO) ((TARGET_SH3E || TARGET_SH4) \
3298 && (REGNO) == FPSCR_REG)
3300 #define MODE_NEEDED(ENTITY, INSN) \
3301 (recog_memoized (INSN) >= 0 \
3302 ? get_attr_fp_mode (INSN) \
3303 : FP_MODE_NONE)
3305 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3306 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3308 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3309 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3311 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3312 sh_can_redirect_branch ((INSN), (SEQ))
3314 #define DWARF_FRAME_RETURN_COLUMN (TARGET_SH5 ? PR_MEDIA_REG : PR_REG)
3316 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3317 /* SH constant pool breaks the devices in crtstuff.c to control section
3318 in where code resides. We have to write it as asm code. */
3319 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3330 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3331 (REGNO (hard_reg) == (TARGET_SH5 ? PR_MEDIA_REG : PR_REG) \
3332 ? (current_function_is_leaf && ! sh_pr_n_sets () \
3333 ? (hard_reg) \
3334 : gen_rtx_MEM (Pmode, TARGET_SH5 \
3335 ? (plus_constant (arg_pointer_rtx, \
3336 TARGET_SHMEDIA64 ? -8 : -4)) \
3337 : frame_pointer_rtx)) \
3338 : NULL_RTX)