?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Fix handling of ICF_NOVOPS in ipa-modref
[official-gcc.git] / gcc / config / sh / sh.h
blob53cad85d1229c6e4b5f624022c719e2172d25482
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993-2024 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #ifndef GCC_SH_H
23 #define GCC_SH_H
24
25 #include "config/vxworks-dummy.h"
26
27 /* Unfortunately, insn-attrtab.cc doesn't include insn-codes.h. We can't
28 include it here, because bconfig.h is also included by gencodes.cc . */
29 /* ??? No longer true. */
30 extern int code_for_indirect_jump_scratch;
31
32 #define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile)
33
34 /* Value should be nonzero if functions must have frame pointers.
35 Zero means the frame pointer need not be set up (and parms may be accessed
36 via the stack pointer) in functions that seem suitable. */
37
38 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
39 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
40 #endif
41
42 \f
43 /* Nonzero if this is an ELF target - compile time only */
44 #define TARGET_ELF 0
45
46 /* Nonzero if we should generate code using type 2E insns. */
47 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
48
49 /* Nonzero if we should generate code using type 2A insns. */
50 #define TARGET_SH2A TARGET_HARD_SH2A
51 /* Nonzero if we should generate code using type 2A SF insns. */
52 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
53 /* Nonzero if we should generate code using type 2A DF insns. */
54 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
55
56 /* Nonzero if we should generate code using type 3E insns. */
57 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
58
59 /* Nonzero if we schedule for a superscalar implementation. */
60 #define TARGET_SUPERSCALAR (TARGET_HARD_SH4 || TARGET_SH2A)
61
62 /* Nonzero if a double-precision FPU is available. */
63 #define TARGET_FPU_DOUBLE (TARGET_SH4 || TARGET_SH2A_DOUBLE)
64
65 /* Nonzero if an FPU is available. */
66 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
67
68 /* Nonzero if we're generating code for SH4a, unless the use of the
69 FPU is disabled (which makes it compatible with SH4al-dsp). */
70 #define TARGET_SH4A_FP (TARGET_SH4A && TARGET_FPU_ANY)
71
72 /* True if the FPU is a SH4-300 variant. */
73 #define TARGET_FPU_SH4_300 (TARGET_FPU_ANY && TARGET_SH4_300)
74
75 /* This is not used by the SH2E calling convention */
76 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
77 (! TARGET_SH2E \
78 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
79
80 #ifndef TARGET_CPU_DEFAULT
81 #define TARGET_CPU_DEFAULT SELECT_SH1
82 #define SUPPORT_SH1 1
83 #define SUPPORT_SH2E 1
84 #define SUPPORT_SH4 1
85 #define SUPPORT_SH4_SINGLE 1
86 #define SUPPORT_SH2A 1
87 #define SUPPORT_SH2A_SINGLE 1
88 #endif
89
90 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
91 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
92 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
93
94 #define SELECT_SH1 (MASK_SH1)
95 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
96 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
97 | MASK_FPU_SINGLE)
98 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
99 | MASK_HARD_SH2A_DOUBLE \
100 | MASK_SH2 | MASK_SH1)
101 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
102 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
103 | MASK_SH1 | MASK_FPU_SINGLE \
104 | MASK_FPU_SINGLE_ONLY)
105 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
106 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
107 | MASK_SH2 | MASK_SH1)
108 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
109 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
110 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
111 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E \
112 | MASK_FPU_SINGLE_ONLY)
113 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
114 | SELECT_SH3)
115 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
116 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
117 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
118 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
119 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
120
121 #if SUPPORT_SH1
122 #define SUPPORT_SH2 1
123 #endif
124 #if SUPPORT_SH2
125 #define SUPPORT_SH3 1
126 #define SUPPORT_SH2A_NOFPU 1
127 #endif
128 #if SUPPORT_SH3
129 #define SUPPORT_SH4_NOFPU 1
130 #endif
131 #if SUPPORT_SH4_NOFPU
132 #define SUPPORT_SH4A_NOFPU 1
133 #define SUPPORT_SH4AL 1
134 #endif
135
136 #if SUPPORT_SH2E
137 #define SUPPORT_SH3E 1
138 #define SUPPORT_SH2A_SINGLE_ONLY 1
139 #endif
140 #if SUPPORT_SH3E
141 #define SUPPORT_SH4_SINGLE_ONLY 1
142 #endif
143 #if SUPPORT_SH4_SINGLE_ONLY
144 #define SUPPORT_SH4A_SINGLE_ONLY 1
145 #endif
146
147 #if SUPPORT_SH4
148 #define SUPPORT_SH4A 1
149 #endif
150
151 #if SUPPORT_SH4_SINGLE
152 #define SUPPORT_SH4A_SINGLE 1
153 #endif
154
155 /* Reset all target-selection flags. */
156 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
157 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
158 | MASK_HARD_SH4 | MASK_FPU_SINGLE \
159 | MASK_FPU_SINGLE_ONLY)
160
161 /* This defaults us to big-endian. */
162 #ifndef TARGET_ENDIAN_DEFAULT
163 #define TARGET_ENDIAN_DEFAULT 0
164 #endif
165
166 #ifndef TARGET_OPT_DEFAULT
167 #define TARGET_OPT_DEFAULT 0
168 #endif
169
170 #define TARGET_DEFAULT \
171 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
172
173 #ifndef SH_MULTILIB_CPU_DEFAULT
174 #define SH_MULTILIB_CPU_DEFAULT "m1"
175 #endif
176
177 #if TARGET_ENDIAN_DEFAULT
178 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
179 #else
180 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
181 #endif
182
183 #define CPP_SPEC " %(subtarget_cpp_spec) "
184
185 #ifndef SUBTARGET_CPP_SPEC
186 #define SUBTARGET_CPP_SPEC ""
187 #endif
188
189 #ifndef SUBTARGET_EXTRA_SPECS
190 #define SUBTARGET_EXTRA_SPECS
191 #endif
192
193 #define EXTRA_SPECS \
194 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
195 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
196 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
197 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
198 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
199 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
200 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
201 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
202 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
203 SUBTARGET_EXTRA_SPECS
204
205 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
206 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:-isa=sh4-up}}}"
207 #else
208 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
209 #endif
210
211 /* Define which ISA type to pass to the assembler.
212 For SH4 we pass SH4A to allow using some instructions that are available
213 on some SH4 variants, but officially are part of the SH4A ISA. */
214 #define SH_ASM_SPEC \
215 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)} \
216 %(subtarget_asm_isa_spec) %(subtarget_asm_spec) \
217 %{m1:--isa=sh} \
218 %{m2:--isa=sh2} \
219 %{m2e:--isa=sh2e} \
220 %{m3:--isa=sh3} \
221 %{m3e:--isa=sh3e} \
222 %{m4:--isa=sh4a} \
223 %{m4-single:--isa=sh4a} \
224 %{m4-single-only:--isa=sh4a} \
225 %{m4-nofpu:--isa=sh4a-nofpu} \
226 %{m4a:--isa=sh4a} \
227 %{m4a-single:--isa=sh4a} \
228 %{m4a-single-only:--isa=sh4a} \
229 %{m4a-nofpu:--isa=sh4a-nofpu} \
230 %{m2a:--isa=sh2a} \
231 %{m2a-single:--isa=sh2a} \
232 %{m2a-single-only:--isa=sh2a} \
233 %{m2a-nofpu:--isa=sh2a-nofpu} \
234 %{m4al:-dsp}"
235
236 #define ASM_SPEC SH_ASM_SPEC
237
238 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
239 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
240 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
241 #else
242 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
243 #endif
244 #endif
245
246 #if STRICT_NOFPU == 1
247 /* Strict nofpu means that the compiler should tell the assembler
248 to reject FPU instructions. E.g. from ASM inserts. */
249 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}"
251 #else
252
253 #define SUBTARGET_ASM_ISA_SPEC \
254 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
255 #endif
256 #else /* ! STRICT_NOFPU */
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
258 #endif
259
260 #ifndef SUBTARGET_ASM_SPEC
261 #define SUBTARGET_ASM_SPEC "%{mfdpic:--fdpic}"
262 #endif
263
264 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
265 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
266 #else
267 #define LINK_EMUL_PREFIX "sh%{ml:l}"
268 #endif
269
270 #define LINK_DEFAULT_CPU_EMUL ""
271 #define ASM_ISA_DEFAULT_SPEC ""
272
273 #define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd}"
274 #define SUBTARGET_LINK_SPEC ""
275
276 /* Go via SH_LINK_SPEC to avoid code replication. */
277 #define LINK_SPEC SH_LINK_SPEC
278
279 #define SH_LINK_SPEC "\
280 -m %(link_emul_prefix)\
281 %{!m1:%{!m2:%{!m3*:%{!m4*:%(link_default_cpu_emul)}}}}\
282 %(subtarget_link_emul_suffix) \
283 %{mrelax:-relax} %(subtarget_link_spec)"
284
285 #ifndef SH_DIV_STR_FOR_SIZE
286 #define SH_DIV_STR_FOR_SIZE "call"
287 #endif
288
289 /* SH2A does not support little-endian. Catch such combinations
290 taking into account the default configuration. */
291 #if TARGET_ENDIAN_DEFAULT == MASK_BIG_ENDIAN
292 #define IS_LITTLE_ENDIAN_OPTION "%{ml:"
293 #else
294 #define IS_LITTLE_ENDIAN_OPTION "%{!mb:"
295 #endif
296
297 #if TARGET_CPU_DEFAULT & MASK_HARD_SH2A
298 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
299 "%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:%eSH2a does not support little-endian}}}}}"
300 #else
301 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
302 "%{m2a*:%eSH2a does not support little-endian}}"
303 #endif
304
305 #ifdef FDPIC_DEFAULT
306 #define FDPIC_SELF_SPECS "%{!mno-fdpic:-mfdpic}"
307 #else
308 #define FDPIC_SELF_SPECS
309 #endif
310
311 #undef DRIVER_SELF_SPECS
312 #define DRIVER_SELF_SPECS UNSUPPORTED_SH2A SUBTARGET_DRIVER_SELF_SPECS \
313 FDPIC_SELF_SPECS
314
315 #undef SUBTARGET_DRIVER_SELF_SPECS
316 #define SUBTARGET_DRIVER_SELF_SPECS
317
318 #define ASSEMBLER_DIALECT assembler_dialect
319
320 extern int assembler_dialect;
321
322 enum sh_divide_strategy_e {
323 /* SH1 .. SH4 strategies. Because of the small number of registers
324 available, the compiler uses knowledge of the actual set of registers
325 being clobbered by the different functions called. */
326 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
327 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
328 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
329 SH_DIV_INTRINSIC
330 };
331
332 extern enum sh_divide_strategy_e sh_div_strategy;
333
334 #ifndef SH_DIV_STRATEGY_DEFAULT
335 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL_DIV1
336 #endif
337
338 #ifdef __cplusplus
339
340 /* Atomic model. */
341 struct sh_atomic_model
342 {
343 enum enum_type
344 {
345 none = 0,
346 soft_gusa,
347 hard_llcs,
348 soft_tcb,
349 soft_imask,
350
351 num_models
352 };
353
354 /* If strict is set, disallow mixing of different models, as it would
355 happen on SH4A. */
356 bool strict;
357 enum_type type;
358
359 /* Name string as it was specified on the command line. */
360 const char* name;
361
362 /* Name string as it is used in C/C++ defines. */
363 const char* cdef_name;
364
365 /* GBR offset variable for TCB model. */
366 int tcb_gbr_offset;
367 };
368
369 extern const sh_atomic_model& selected_atomic_model (void);
370
371 /* Shortcuts to check the currently selected atomic model. */
372 #define TARGET_ATOMIC_ANY \
373 (selected_atomic_model ().type != sh_atomic_model::none)
374
375 #define TARGET_ATOMIC_STRICT \
376 (selected_atomic_model ().strict)
377
378 #define TARGET_ATOMIC_SOFT_GUSA \
379 (selected_atomic_model ().type == sh_atomic_model::soft_gusa)
380
381 #define TARGET_ATOMIC_HARD_LLCS \
382 (selected_atomic_model ().type == sh_atomic_model::hard_llcs)
383
384 #define TARGET_ATOMIC_SOFT_TCB \
385 (selected_atomic_model ().type == sh_atomic_model::soft_tcb)
386
387 #define TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX \
388 GEN_INT (selected_atomic_model ().tcb_gbr_offset)
389
390 #define TARGET_ATOMIC_SOFT_IMASK \
391 (selected_atomic_model ().type == sh_atomic_model::soft_imask)
392
393 #endif // __cplusplus
394
395 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
396
397 \f
398 /* Target machine storage layout. */
399
400 #define TARGET_BIG_ENDIAN (!TARGET_LITTLE_ENDIAN)
401
402 #define SH_REG_MSW_OFFSET (TARGET_LITTLE_ENDIAN ? 1 : 0)
403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1)
404
405 /* Define this if most significant bit is lowest numbered
406 in instructions that operate on numbered bit-fields. */
407 #define BITS_BIG_ENDIAN 0
408
409 /* Define this if most significant byte of a word is the lowest numbered. */
410 #define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN
411
412 /* Define this if most significant word of a multiword number is the lowest
413 numbered. */
414 #define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN
415
416 #define MAX_BITS_PER_WORD 64
417
418 /* Width in bits of an `int'. We want just 32-bits, even if words are
419 longer. */
420 #define INT_TYPE_SIZE 32
421
422 /* Width in bits of a `long'. */
423 #define LONG_TYPE_SIZE (32)
424
425 /* Width in bits of a `long long'. */
426 #define LONG_LONG_TYPE_SIZE 64
427
428 /* Width of a word, in units (bytes). */
429 #define UNITS_PER_WORD (4)
430 #define MIN_UNITS_PER_WORD 4
431
432 /* Scaling factor for Dwarf data offsets for CFI information.
433 The dwarf2out.cc default would use -UNITS_PER_WORD. */
434 #define DWARF_CIE_DATA_ALIGNMENT -4
435
436 /* Width in bits of a pointer.
437 See also the macro `Pmode' defined below. */
438 #define POINTER_SIZE (32)
439
440 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
441 #define PARM_BOUNDARY (32)
442
443 /* Boundary (in *bits*) on which stack pointer should be aligned. */
444 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
445
446 /* The log (base 2) of the cache line size, in bytes. Processors prior to
447 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
448 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
449 #define CACHE_LOG (TARGET_HARD_SH4 ? 5 : TARGET_SH2 ? 4 : 2)
450
451 /* ABI given & required minimum allocation boundary (in *bits*) for the
452 code of a function. */
453 #define FUNCTION_BOUNDARY (16)
454
455 /* Alignment of field after `int : 0' in a structure. */
456 #define EMPTY_FIELD_BOUNDARY 32
457
458 /* No data type wants to be aligned rounder than this. */
459 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
460
461 /* The best alignment to use in cases where we have a choice. */
462 #define FASTEST_ALIGNMENT (32)
463
464 /* get_mode_alignment assumes complex values are always held in multiple
465 registers, but that is not the case on the SH; CQImode and CHImode are
466 held in a single integer register. */
467 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
468 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
469 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
470 ? (unsigned) MIN (BIGGEST_ALIGNMENT, \
471 GET_MODE_BITSIZE (as_a <fixed_size_mode> \
472 (TYPE_MODE (TYPE)))) \
473 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
474
475 /* Make arrays of chars word-aligned for the same reasons. */
476 #define DATA_ALIGNMENT(TYPE, ALIGN) \
477 (TREE_CODE (TYPE) == ARRAY_TYPE \
478 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
479 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
480
481 /* Number of bits which any structure or union's size must be a
482 multiple of. Each structure or union's size is rounded up to a
483 multiple of this. */
484 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
485
486 /* Set this nonzero if move instructions will actually fail to work
487 when given unaligned data. */
488 #define STRICT_ALIGNMENT 1
489
490 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
491 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
492 barrier_align (LABEL_AFTER_BARRIER)
493
494 #define LOOP_ALIGN(A_LABEL) sh_loop_align (A_LABEL)
495
496 #define LABEL_ALIGN(A_LABEL) \
497 ( \
498 (PREV_INSN (A_LABEL) \
499 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
500 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
501 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
502 /* explicit alignment insn in constant tables. */ \
503 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
504 : 0)
505
506 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
507 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
508
509 /* The base two logarithm of the known minimum alignment of an insn length. */
510 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
511 (NONJUMP_INSN_P (A_INSN) \
512 ? 1 \
513 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
514 ? 1 \
515 : CACHE_LOG)
516 \f
517 /* Standard register usage. */
518
519 /* Register allocation for the Renesas calling convention:
520
521 r0 arg return
522 r1..r3 scratch
523 r4..r7 args in
524 r8..r13 call saved
525 r14 frame pointer/call saved
526 r15 stack pointer
527 ap arg pointer (doesn't really exist, always eliminated)
528 pr subroutine return address
529 t t bit
530 mach multiply/accumulate result, high part
531 macl multiply/accumulate result, low part.
532 fpul fp/int communication register
533 rap return address pointer register
534 fr0 fp arg return
535 fr1..fr3 scratch floating point registers
536 fr4..fr11 fp args in
537 fr12..fr15 call saved floating point registers */
538
539 #define MAX_REGISTER_NAME_LENGTH 6
540 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
541
542 #define SH_REGISTER_NAMES_INITIALIZER \
543 { \
544 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
545 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
546 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
547 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
548 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
549 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
550 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
551 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
552 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
553 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
554 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
555 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
556 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
557 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
558 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
559 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
560 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
561 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
562 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
563 "rap", "sfp", "fpscr0", "fpscr1" \
564 }
565
566 #define REGNAMES_ARR_INDEX_1(index) \
567 (sh_register_names[index])
568 #define REGNAMES_ARR_INDEX_2(index) \
569 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
570 #define REGNAMES_ARR_INDEX_4(index) \
571 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
572 #define REGNAMES_ARR_INDEX_8(index) \
573 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
574 #define REGNAMES_ARR_INDEX_16(index) \
575 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
576 #define REGNAMES_ARR_INDEX_32(index) \
577 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
578 #define REGNAMES_ARR_INDEX_64(index) \
579 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
580
581 #define REGISTER_NAMES \
582 { \
583 REGNAMES_ARR_INDEX_64 (0), \
584 REGNAMES_ARR_INDEX_64 (64), \
585 REGNAMES_ARR_INDEX_8 (128), \
586 REGNAMES_ARR_INDEX_8 (136), \
587 REGNAMES_ARR_INDEX_8 (144), \
588 REGNAMES_ARR_INDEX_4 (152) \
589 }
590
591 #define ADDREGNAMES_SIZE 32
592 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
593 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
594 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
595
596 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
597 { \
598 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
599 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
600 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
601 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
602 }
603
604 #define ADDREGNAMES_REGNO(index) \
605 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
606 : (-1))
607
608 #define ADDREGNAMES_ARR_INDEX_1(index) \
609 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
610 #define ADDREGNAMES_ARR_INDEX_2(index) \
611 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
612 #define ADDREGNAMES_ARR_INDEX_4(index) \
613 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
614 #define ADDREGNAMES_ARR_INDEX_8(index) \
615 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
616 #define ADDREGNAMES_ARR_INDEX_16(index) \
617 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
618 #define ADDREGNAMES_ARR_INDEX_32(index) \
619 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
620
621 #define ADDITIONAL_REGISTER_NAMES \
622 { \
623 ADDREGNAMES_ARR_INDEX_32 (0) \
624 }
625
626 /* Number of actual hardware registers.
627 The hardware registers are assigned numbers for the compiler
628 from 0 to just below FIRST_PSEUDO_REGISTER.
629 All registers that the compiler knows about must be given numbers,
630 even those that are not normally considered general registers. */
631
632 /* There are many other relevant definitions in sh.md's md_constants. */
633
634 #define FIRST_GENERAL_REG R0_REG
635 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (15))
636 #define FIRST_FP_REG DR0_REG
637 #define LAST_FP_REG (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1))
638 #define FIRST_XD_REG XD0_REG
639 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
640
641 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
642 #define FIRST_BANKED_REG R0_REG
643 #define LAST_BANKED_REG R7_REG
644
645 #define BANKED_REGISTER_P(REGNO) \
646 IN_RANGE ((REGNO), \
647 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
648 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
649
650 #define GENERAL_REGISTER_P(REGNO) \
651 IN_RANGE ((REGNO), \
652 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
653 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
654
655 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
656 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
657 || ((REGNO) == FRAME_POINTER_REGNUM))
658
659 #define FP_REGISTER_P(REGNO) \
660 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
661
662 #define XD_REGISTER_P(REGNO) \
663 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
664
665 #define FP_OR_XD_REGISTER_P(REGNO) \
666 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
667
668 #define FP_ANY_REGISTER_P(REGNO) \
669 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
670
671 #define SPECIAL_REGISTER_P(REGNO) \
672 ((REGNO) == GBR_REG || (REGNO) == T_REG \
673 || (REGNO) == MACH_REG || (REGNO) == MACL_REG \
674 || (REGNO) == FPSCR_MODES_REG || (REGNO) == FPSCR_STAT_REG)
675
676 #define VALID_REGISTER_P(REGNO) \
677 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
678 || XD_REGISTER_P (REGNO) \
679 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
680 || (REGNO) == FRAME_POINTER_REGNUM \
681 || ((SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
682 || (TARGET_SH2E && (REGNO) == FPUL_REG))
683
684 /* The mode that should be generally used to store a register by
685 itself in the stack, or to load it back. */
686 #define REGISTER_NATURAL_MODE(REGNO) \
687 (FP_REGISTER_P (REGNO) ? E_SFmode \
688 : XD_REGISTER_P (REGNO) ? E_DFmode : E_SImode)
689
690
691 #define FIRST_PSEUDO_REGISTER 156
692
693 /* Don't count soft frame pointer. */
694 #define DWARF_FRAME_REGISTERS (153)
695
696 /* 1 for registers that have pervasive standard uses
697 and are not available for the register allocator.
698
699 Mach register is fixed 'cause it's only 10 bits wide for SH1.
700 It is 32 bits wide for SH2. */
701 #define FIXED_REGISTERS \
702 { \
703 /* Regular registers. */ \
704 0, 0, 0, 0, 0, 0, 0, 0, \
705 0, 0, 0, 0, 0, 0, 0, 1, \
706 /* r16 is reserved, r18 is the former pr. */ \
707 1, 0, 0, 0, 0, 0, 0, 0, \
708 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
709 /* r26 is a global variable data pointer; r27 is for constants. */ \
710 1, 1, 1, 1, 0, 0, 0, 0, \
711 0, 0, 0, 0, 0, 0, 0, 0, \
712 0, 0, 0, 0, 0, 0, 0, 0, \
713 0, 0, 0, 0, 0, 0, 0, 0, \
714 0, 0, 0, 0, 0, 0, 0, 1, \
715 /* FP registers. */ \
716 0, 0, 0, 0, 0, 0, 0, 0, \
717 0, 0, 0, 0, 0, 0, 0, 0, \
718 0, 0, 0, 0, 0, 0, 0, 0, \
719 0, 0, 0, 0, 0, 0, 0, 0, \
720 0, 0, 0, 0, 0, 0, 0, 0, \
721 0, 0, 0, 0, 0, 0, 0, 0, \
722 0, 0, 0, 0, 0, 0, 0, 0, \
723 0, 0, 0, 0, 0, 0, 0, 0, \
724 /* Branch target registers. */ \
725 0, 0, 0, 0, 0, 0, 0, 0, \
726 /* XD registers. */ \
727 0, 0, 0, 0, 0, 0, 0, 0, \
728 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
729 1, 1, 1, 1, 1, 1, 0, 1, \
730 /*"rap", "sfp","fpscr0","fpscr1" */ \
731 1, 1, 1, 1, \
732 }
733
734 /* CALL_REALLY_USED_REGISTERS is used as a default setting, which is then
735 overridden by -fcall-saved-* and -fcall-used-* options and then by
736 TARGET_CONDITIONAL_REGISTER_USAGE. There we might want to make a
737 register call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */
738 #define CALL_REALLY_USED_REGISTERS \
739 { \
740 /* Regular registers. */ \
741 1, 1, 1, 1, 1, 1, 1, 1, \
742 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
743 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
744 across SH5 function calls. */ \
745 0, 0, 0, 0, 0, 0, 0, 1, \
746 1, 1, 1, 1, 1, 1, 1, 1, \
747 1, 1, 1, 1, 0, 0, 0, 0, \
748 0, 0, 0, 0, 1, 1, 1, 1, \
749 1, 1, 1, 1, 0, 0, 0, 0, \
750 0, 0, 0, 0, 0, 0, 0, 0, \
751 0, 0, 0, 0, 1, 1, 1, 1, \
752 /* FP registers. */ \
753 1, 1, 1, 1, 1, 1, 1, 1, \
754 1, 1, 1, 1, 0, 0, 0, 0, \
755 1, 1, 1, 1, 1, 1, 1, 1, \
756 1, 1, 1, 1, 1, 1, 1, 1, \
757 1, 1, 1, 1, 0, 0, 0, 0, \
758 0, 0, 0, 0, 0, 0, 0, 0, \
759 0, 0, 0, 0, 0, 0, 0, 0, \
760 0, 0, 0, 0, 0, 0, 0, 0, \
761 /* Branch target registers. */ \
762 1, 1, 1, 1, 1, 0, 0, 0, \
763 /* XD registers. */ \
764 1, 1, 1, 1, 1, 1, 0, 0, \
765 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
766 0, 1, 1, 1, 1, 1, 1, 1, \
767 /*"rap", "sfp","fpscr0","fpscr1" */ \
768 1, 1, 0, 0, \
769 }
770
771 /* Specify the modes required to caller save a given hard regno. */
772 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
773 sh_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
774
775 /* A C expression that is nonzero if hard register NEW_REG can be
776 considered for use as a rename register for OLD_REG register */
777 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
778 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
779
780 /* Specify the registers used for certain standard purposes.
781 The values of these macros are register numbers. */
782
783 /* Define this if the program counter is overloaded on a register. */
784 /* #define PC_REGNUM 15*/
785
786 /* Register to use for pushing function arguments. */
787 #define STACK_POINTER_REGNUM SP_REG
788
789 /* Base register for access to local variables of the function. */
790 #define HARD_FRAME_POINTER_REGNUM FP_REG
791
792 /* Base register for access to local variables of the function. */
793 #define FRAME_POINTER_REGNUM 153
794
795 /* Fake register that holds the address on the stack of the
796 current function's return address. */
797 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
798
799 /* Register to hold the addressing base for position independent
800 code access to data items. */
801 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
802
803 /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT
804 entries would need to handle saving and restoring it). */
805 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC
806
807 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
808
809 /* Definitions for register eliminations.
810
811 We have three registers that can be eliminated on the SH. First, the
812 frame pointer register can often be eliminated in favor of the stack
813 pointer register. Secondly, the argument pointer register can always be
814 eliminated; it is replaced with either the stack or frame pointer.
815 Third, there is the return address pointer, which can also be replaced
816 with either the stack or the frame pointer.
817
818 This is an array of structures. Each structure initializes one pair
819 of eliminable registers. The "from" register number is given first,
820 followed by "to". Eliminations of the same "from" register are listed
821 in order of preference.
822
823 If you add any registers here that are not actually hard registers,
824 and that have any alternative of elimination that doesn't always
825 apply, you need to amend calc_live_regs to exclude it, because
826 reload spills all eliminable registers where it sees an
827 can_eliminate == 0 entry, thus making them 'live' .
828 If you add any hard registers that can be eliminated in different
829 ways, you have to patch reload to spill them only when all alternatives
830 of elimination fail. */
831 #define ELIMINABLE_REGS \
832 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
833 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
834 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
835 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
836 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
837 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
838 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
839
840 /* Define the offset between two registers, one to be eliminated, and the other
841 its replacement, at the start of a routine. */
842 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
843 OFFSET = initial_elimination_offset ((FROM), (TO))
844
845 /* Base register for access to arguments of the function. */
846 #define ARG_POINTER_REGNUM AP_REG
847
848 /* Register in which the static-chain is passed to a function. */
849 #define STATIC_CHAIN_REGNUM (3)
850
851 /* Don't default to pcc-struct-return, because we have already specified
852 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
853 target hook. */
854 #define DEFAULT_PCC_STRUCT_RETURN 0
855
856 \f
857 /* Define the classes of registers for register constraints in the
858 machine description. Also define ranges of constants.
859
860 One of the classes must always be named ALL_REGS and include all hard regs.
861 If there is more than one class, another class must be named NO_REGS
862 and contain no registers.
863
864 The name GENERAL_REGS must be the name of a class (or an alias for
865 another name such as ALL_REGS). This is the class of registers
866 that is allowed by "g" or "r" in a register constraint.
867 Also, registers outside this class are allocated only when
868 instructions express preferences for them.
869
870 The classes must be numbered in nondecreasing order; that is,
871 a larger-numbered class must never be contained completely
872 in a smaller-numbered class.
873
874 For any two classes, it is very desirable that there be another
875 class that represents their union.
876
877 The SH has two sorts of general registers, R0 and the rest. R0 can
878 be used as the destination of some of the arithmetic ops. There are
879 also some special purpose registers; the T bit register, the
880 Procedure Return Register and the Multiply Accumulate Registers.
881
882 Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
883 reg_class_subunion. We don't want to have an actual union class
884 of these, because it would only be used when both classes are calculated
885 to give the same cost, but there is only one FPUL register.
886 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
887 applying to the actual instruction alternative considered. E.g., the
888 y/r alternative of movsi_ie is considered to have no more cost that
889 the r/r alternative, which is patently untrue. */
890 enum reg_class
891 {
892 NO_REGS,
893 R0_REGS,
894 PR_REGS,
895 T_REGS,
896 MAC_REGS,
897 FPUL_REGS,
898 SIBCALL_REGS,
899 NON_SP_REGS,
900 GENERAL_REGS,
901 FP0_REGS,
902 FP_REGS,
903 DF_REGS,
904 FPSCR_REGS,
905 GENERAL_FP_REGS,
906 GENERAL_DF_REGS,
907 TARGET_REGS,
908 ALL_REGS,
909 LIM_REG_CLASSES
910 };
911
912 #define N_REG_CLASSES (int) LIM_REG_CLASSES
913
914 /* Give names of register classes as strings for dump file. */
915 #define REG_CLASS_NAMES \
916 { \
917 "NO_REGS", \
918 "R0_REGS", \
919 "PR_REGS", \
920 "T_REGS", \
921 "MAC_REGS", \
922 "FPUL_REGS", \
923 "SIBCALL_REGS", \
924 "NON_SP_REGS", \
925 "GENERAL_REGS", \
926 "FP0_REGS", \
927 "FP_REGS", \
928 "DF_REGS", \
929 "FPSCR_REGS", \
930 "GENERAL_FP_REGS", \
931 "GENERAL_DF_REGS", \
932 "TARGET_REGS", \
933 "ALL_REGS", \
934 }
935
936 /* Define which registers fit in which classes.
937 This is an initializer for a vector of HARD_REG_SET
938 of length N_REG_CLASSES. */
939 #define REG_CLASS_CONTENTS \
940 { \
941 /* NO_REGS: */ \
942 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
943 /* R0_REGS: */ \
944 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
945 /* PR_REGS: */ \
946 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
947 /* T_REGS: */ \
948 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
949 /* MAC_REGS: */ \
950 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
951 /* FPUL_REGS: */ \
952 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
953 /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
954 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
955 /* NON_SP_REGS: */ \
956 { 0xffff7fff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
957 /* GENERAL_REGS: */ \
958 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
959 /* FP0_REGS: */ \
960 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
961 /* FP_REGS: */ \
962 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
963 /* DF_REGS: */ \
964 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
965 /* FPSCR_REGS: */ \
966 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
967 /* GENERAL_FP_REGS: */ \
968 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
969 /* GENERAL_DF_REGS: */ \
970 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
971 /* TARGET_REGS: */ \
972 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
973 /* ALL_REGS: */ \
974 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0fffffff }, \
975 }
976
977 /* The same information, inverted:
978 Return the class number of the smallest class containing
979 reg number REGNO. This could be a conditional expression
980 or could index an array. */
981 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
982 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
983
984 /* When this hook returns true for MODE, the compiler allows
985 registers explicitly used in the rtl to be used as spill registers
986 but prevents the compiler from extending the lifetime of these
987 registers. */
988 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
989 sh_small_register_classes_for_mode_p
990
991 /* The order in which register should be allocated. */
992 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
993 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
994 spilled or used otherwise, we better have the FP_REGS allocated first. */
995 #define REG_ALLOC_ORDER \
996 {/* Caller-saved FPRs */ \
997 65, 66, 67, 68, 69, 70, 71, 64, \
998 72, 73, 74, 75, 80, 81, 82, 83, \
999 84, 85, 86, 87, 88, 89, 90, 91, \
1000 92, 93, 94, 95, 96, 97, 98, 99, \
1001 /* Callee-saved FPRs */ \
1002 76, 77, 78, 79,100,101,102,103, \
1003 104,105,106,107,108,109,110,111, \
1004 112,113,114,115,116,117,118,119, \
1005 120,121,122,123,124,125,126,127, \
1006 136,137,138,139,140,141,142,143, \
1007 /* FPSCR */ 151, \
1008 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1009 1, 2, 3, 7, 6, 5, 4, 0, \
1010 8, 9, 17, 19, 20, 21, 22, 23, \
1011 36, 37, 38, 39, 40, 41, 42, 43, \
1012 60, 61, 62, \
1013 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1014 10, 11, 12, 13, 14, 18, \
1015 /* SH5 callee-saved GPRs */ \
1016 28, 29, 30, 31, 32, 33, 34, 35, \
1017 44, 45, 46, 47, 48, 49, 50, 51, \
1018 52, 53, 54, 55, 56, 57, 58, 59, \
1019 /* FPUL */ 150, \
1020 /* Fixed registers */ \
1021 15, 16, 24, 25, 26, 27, 63,144, \
1022 145,146,147,148,149,152,153,154,155 }
1023
1024 /* The class value for index registers, and the one for base regs. */
1025 #define INDEX_REG_CLASS R0_REGS
1026 #define BASE_REG_CLASS GENERAL_REGS
1027 \f
1028 /* Defines for sh.md and constraints.md. */
1029
1030 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1031 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1032
1033 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1034 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1035
1036 #define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\
1037 (((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX))
1038
1039 /* Return the maximum number of consecutive registers
1040 needed to represent mode MODE in a register of class CLASS.
1041
1042 If TARGET_SHMEDIA, we need two FP registers per word.
1043 Otherwise we will need at most one register per word. */
1044 #define CLASS_MAX_NREGS(CLASS, MODE) \
1045 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1046 \f
1047 /* Stack layout; function entry, exit and calling. */
1048
1049 /* Define the number of registers that can hold parameters.
1050 These macros are used only in other macro definitions below. */
1051 #define NPARM_REGS(MODE) \
1052 (TARGET_FPU_ANY && (MODE) == SFmode \
1053 ? 8 \
1054 : TARGET_FPU_DOUBLE \
1055 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1056 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1057 ? 8 \
1058 : 4)
1059
1060 #define FIRST_PARM_REG (FIRST_GENERAL_REG + 4)
1061 #define FIRST_RET_REG (FIRST_GENERAL_REG + 0)
1062
1063 #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
1064 #define FIRST_FP_RET_REG FIRST_FP_REG
1065
1066 /* Define this if pushing a word on the stack
1067 makes the stack pointer a smaller address. */
1068 #define STACK_GROWS_DOWNWARD 1
1069
1070 /* Define this macro to nonzero if the addresses of local variable slots
1071 are at negative offsets from the frame pointer. */
1072 #define FRAME_GROWS_DOWNWARD 1
1073
1074 /* If we generate an insn to push BYTES bytes,
1075 this says how many the stack pointer really advances by. */
1076 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1077 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1078 do correct alignment. */
1079 #if 0
1080 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1081 #endif
1082
1083 /* Offset of first parameter from the argument pointer register value. */
1084 #define FIRST_PARM_OFFSET(FNDECL) 0
1085
1086 /* Value is the number of bytes of arguments automatically popped when
1087 calling a subroutine.
1088 CUM is the accumulated argument list. */
1089 #define CALL_POPS_ARGS(CUM) (0)
1090
1091 /* Some subroutine macros specific to this machine. */
1092
1093 #define BASE_RETURN_VALUE_REG(MODE) \
1094 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1095 ? FIRST_FP_RET_REG \
1096 : TARGET_FPU_ANY && (MODE) == SCmode \
1097 ? FIRST_FP_RET_REG \
1098 : (TARGET_FPU_DOUBLE \
1099 && ((MODE) == DFmode || (MODE) == SFmode \
1100 || (MODE) == DCmode || (MODE) == SCmode )) \
1101 ? FIRST_FP_RET_REG \
1102 : FIRST_RET_REG)
1103
1104 #define BASE_ARG_REG(MODE) \
1105 ((TARGET_SH2E && ((MODE) == SFmode)) \
1106 ? FIRST_FP_PARM_REG \
1107 : TARGET_FPU_DOUBLE \
1108 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1109 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1110 ? FIRST_FP_PARM_REG \
1111 : FIRST_PARM_REG)
1112
1113 /* 1 if N is a possible register number for function argument passing. */
1114 /* ??? There are some callers that pass REGNO as int, and others that pass
1115 it as unsigned. We get warnings unless we do casts everywhere. */
1116 #define FUNCTION_ARG_REGNO_P(REGNO) \
1117 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1118 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1119 || (TARGET_FPU_ANY \
1120 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1121 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1122 + NPARM_REGS (SFmode))))
1123 \f
1124 #ifdef __cplusplus
1125
1126 /* Define a data type for recording info about an argument list
1127 during the scan of that argument list. This data type should
1128 hold all necessary information about the function itself
1129 and about the args processed so far, enough to enable macros
1130 such as FUNCTION_ARG to determine where the next arg should go.
1131
1132 On SH, this is a single integer, which is a number of words
1133 of arguments scanned so far (including the invisible argument,
1134 if any, which holds the structure-value-address).
1135 Thus NARGREGS or more means all following args should go on the stack. */
1136
1137 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1138
1139 struct sh_args
1140 {
1141 /* How many SH_ARG_INT and how many SH_ARG_FLOAT args there are. */
1142 int arg_count[2];
1143
1144 bool force_mem;
1145
1146 /* Nonzero if a prototype is available for the function. */
1147 bool prototype_p;
1148
1149 /* The number of an odd floating-point register, that should be used
1150 for the next argument of type float. */
1151 int free_single_fp_reg;
1152
1153 /* Whether we're processing an outgoing function call. */
1154 bool outgoing;
1155
1156 /* This is set to nonzero when the call in question must use the Renesas ABI,
1157 even without the -mrenesas option. */
1158 bool renesas_abi;
1159 };
1160
1161 typedef sh_args CUMULATIVE_ARGS;
1162
1163 /* Set when processing a function with interrupt attribute. */
1164 extern bool current_function_interrupt;
1165
1166 #endif // __cplusplus
1167
1168 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1169 for a call to a function whose data type is FNTYPE.
1170 For a library call, FNTYPE is 0.
1171
1172 On SH, the offset always starts at 0: the first parm reg is always
1173 the same reg for a given argument class.
1174
1175 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1176 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1177 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL),\
1178 (N_NAMED_ARGS), VOIDmode)
1179
1180 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1181 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1182
1183 /* By accident we got stuck with passing SCmode on SH4 little endian
1184 in two registers that are nominally successive - which is different from
1185 two single SFmode values, where we take endianness translation into
1186 account. That does not work at all if an odd number of registers is
1187 already in use, so that got fixed, but library functions are still more
1188 likely to use complex numbers without mixing them with SFmode arguments
1189 (which in C would have to be structures), so for the sake of ABI
1190 compatibility the way SCmode values are passed when an even number of
1191 FP registers is in use remains different from a pair of SFmode values for
1192 now.
1193 I.e.:
1194 foo (double); a: fr5,fr4
1195 foo (float a, float b); a: fr5 b: fr4
1196 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1197 this should be the other way round...
1198 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1199 #define FUNCTION_ARG_SCmode_WART 1
1200
1201 /* Minimum alignment for an argument to be passed by callee-copy
1202 reference. We need such arguments to be aligned to 8 byte
1203 boundaries, because they'll be loaded using quad loads. */
1204 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1205
1206 /* Perform any needed actions needed for a function that is receiving a
1207 variable number of arguments. */
1208
1209 /* Call the function profiler with a given profile label.
1210 We use two .aligns, so as to make sure that both the .long is aligned
1211 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1212 from the trapa instruction. */
1213 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1214 { \
1215 fprintf((STREAM), "\t.align\t2\n"); \
1216 fprintf((STREAM), "\ttrapa\t#33\n"); \
1217 fprintf((STREAM), "\t.align\t2\n"); \
1218 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1219 }
1220
1221 /* Define this macro if the code for function profiling should come
1222 before the function prologue. Normally, the profiling code comes
1223 after. */
1224 #define PROFILE_BEFORE_PROLOGUE
1225
1226 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1227 the stack pointer does not matter. The value is tested only in
1228 functions that have frame pointers.
1229 No definition is equivalent to always zero. */
1230 #define EXIT_IGNORE_STACK 1
1231
1232 /*
1233 On the SH, the trampoline looks like
1234 2 0002 D202 mov.l l2,r2
1235 1 0000 D301 mov.l l1,r3
1236 3 0004 422B jmp @r2
1237 4 0006 0009 nop
1238 5 0008 00000000 l1: .long area
1239 6 000c 00000000 l2: .long function */
1240
1241 /* Length in units of the trampoline for entering a nested function. */
1242 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : 16)
1243
1244 /* Alignment required for a trampoline in bits. */
1245 #define TRAMPOLINE_ALIGNMENT \
1246 ((CACHE_LOG < 3 \
1247 || (optimize_size && ! (TARGET_HARD_SH4))) ? 32 \
1248 : 64)
1249
1250 /* A C expression whose value is RTL representing the value of the return
1251 address for the frame COUNT steps up from the current frame.
1252 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1253 can ignore COUNT. */
1254 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1255 (((COUNT) == 0) ? sh_get_pr_initial_val () : NULL_RTX)
1256
1257 /* A C expression whose value is RTL representing the location of the
1258 incoming return address at the beginning of any function, before the
1259 prologue. This RTL is either a REG, indicating that the return
1260 value is saved in REG, or a MEM representing a location in
1261 the stack. */
1262 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, PR_REG)
1263 \f
1264 /* Addressing modes, and classification of registers for them. */
1265 #define HAVE_POST_INCREMENT TARGET_SH1
1266 #define HAVE_PRE_DECREMENT TARGET_SH1
1267
1268 #define USE_LOAD_POST_INCREMENT(mode) TARGET_SH1
1269 #define USE_LOAD_PRE_DECREMENT(mode) TARGET_SH2A
1270 #define USE_STORE_POST_INCREMENT(mode) TARGET_SH2A
1271 #define USE_STORE_PRE_DECREMENT(mode) TARGET_SH1
1272
1273 /* If a memory clear move would take CLEAR_RATIO or more simple
1274 move-instruction pairs, we will do a setmem instead. */
1275
1276 #define CLEAR_RATIO(speed) ((speed) ? 15 : 3)
1277
1278 /* Macros to check register numbers against specific register classes. */
1279
1280 /* These assume that REGNO is a hard or pseudo reg number.
1281 They give nonzero only if REGNO is a hard reg of the suitable class
1282 or a pseudo reg currently allocated to a suitable hard reg.
1283 Since they use reg_renumber, they are safe only once reg_renumber
1284 has been allocated, which happens in reginfo.cc during register
1285 allocation. */
1286 #define REGNO_OK_FOR_BASE_P(REGNO) \
1287 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1288 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1289 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1290 ((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1291
1292 /* True if SYMBOL + OFFSET constants must refer to something within
1293 SYMBOL's section. */
1294 #define SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P TARGET_FDPIC
1295
1296 /* Maximum number of registers that can appear in a valid memory
1297 address. */
1298 #define MAX_REGS_PER_ADDRESS 2
1299
1300 /* Recognize any constant value that is a valid address. */
1301 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1302
1303 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1304 and check its validity for a certain class.
1305 The suitable hard regs are always accepted and all pseudo regs
1306 are also accepted if STRICT is not set. */
1307
1308 /* Nonzero if X is a reg that can be used as a base reg. */
1309 #define REG_OK_FOR_BASE_P(X, STRICT) \
1310 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1311 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1312
1313 /* Nonzero if X is a reg that can be used as an index. */
1314 #define REG_OK_FOR_INDEX_P(X, STRICT) \
1315 ((REGNO (X) == R0_REG) \
1316 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1317
1318 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
1319 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
1320 ((REGNO (X) == R0_REG && OFFSET == 0) \
1321 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1322
1323 /* Macros for extra constraints. */
1324
1325 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
1326 ((GET_CODE ((OP)) == LABEL_REF) \
1327 || (GET_CODE ((OP)) == CONST \
1328 && GET_CODE (XEXP ((OP), 0)) == PLUS \
1329 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1330 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1331
1332 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
1333 (CONSTANT_P (OP) \
1334 && !CONST_INT_P (OP) \
1335 && GET_CODE (OP) != CONST_DOUBLE \
1336 && (!flag_pic \
1337 || (LEGITIMATE_PIC_OPERAND_P (OP) \
1338 && !PIC_ADDR_P (OP) \
1339 && GET_CODE (OP) != LABEL_REF)))
1340
1341 #define GOT_ENTRY_P(OP) \
1342 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1343 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
1344
1345 #define GOTPLT_ENTRY_P(OP) \
1346 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1347 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
1348
1349 #define UNSPEC_GOTOFF_P(OP) \
1350 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
1351
1352 #define GOTOFF_P(OP) \
1353 (GET_CODE (OP) == CONST \
1354 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
1355 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
1356 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
1357 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
1358
1359 #define PIC_ADDR_P(OP) \
1360 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1361 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
1362
1363 #define PCREL_SYMOFF_P(OP) \
1364 (GET_CODE (OP) == CONST \
1365 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1366 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
1367
1368 #define NON_PIC_REFERENCE_P(OP) \
1369 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
1370 || (GET_CODE (OP) == CONST \
1371 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
1372 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF)) \
1373 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
1374 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
1375 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF) \
1376 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1377
1378 #define PIC_REFERENCE_P(OP) \
1379 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
1380 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
1381
1382 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
1383 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
1384 || (GET_CODE (X) == SUBREG \
1385 && REG_P (SUBREG_REG (X)) \
1386 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
1387
1388 /* Since this must be r0, which is a single register class, we must check
1389 SUBREGs more carefully, to be sure that we don't accept one that extends
1390 outside the class. */
1391 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
1392 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
1393 || (GET_CODE (X) == SUBREG \
1394 && REG_P (SUBREG_REG (X)) \
1395 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
1396
1397 #ifdef REG_OK_STRICT
1398 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
1399 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
1400 #else
1401 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
1402 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
1403 #endif
1404
1405 \f
1406 /* A C compound statement that attempts to replace X, which is an address
1407 that needs reloading, with a valid memory address for an operand of
1408 mode MODE. WIN is a C statement label elsewhere in the code. */
1409 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1410 do { \
1411 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
1412 goto WIN; \
1413 } while (0)
1414 \f
1415 /* Specify the machine mode that this machine uses
1416 for the index in the tablejump instruction. */
1417 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
1418
1419 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1420 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1421 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1422 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1423 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1424 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1425 : SImode)
1426
1427 /* Define as C expression which evaluates to nonzero if the tablejump
1428 instruction expects the table to contain offsets from the address of the
1429 table.
1430 Do not define this if the table should contain absolute addresses. */
1431 #define CASE_VECTOR_PC_RELATIVE 1
1432
1433 /* 'char' is signed by default. */
1434 #define DEFAULT_SIGNED_CHAR 1
1435
1436 /* The type of size_t unsigned int. */
1437 #define SIZE_TYPE ("unsigned int")
1438
1439 #undef PTRDIFF_TYPE
1440 #define PTRDIFF_TYPE ("int")
1441
1442 #define WCHAR_TYPE "short unsigned int"
1443 #define WCHAR_TYPE_SIZE 16
1444
1445 #define SH_ELF_WCHAR_TYPE "long int"
1446
1447 /* Max number of bytes we can move from memory to memory
1448 in one reasonably fast instruction. */
1449 #define MOVE_MAX (4)
1450
1451 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
1452 MOVE_MAX is not a compile-time constant. */
1453 #define MAX_MOVE_MAX 8
1454
1455 /* Max number of bytes we want move_by_pieces to be able to copy
1456 efficiently. */
1457 #define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4)
1458
1459 /* Define if operations between registers always perform the operation
1460 on the full register even if a narrower mode is specified. */
1461 #define WORD_REGISTER_OPERATIONS 1
1462
1463 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1464 will either zero-extend or sign-extend. The value of this macro should
1465 be the code that says which one of the two operations is implicitly
1466 done, UNKNOWN if none. */
1467 #define LOAD_EXTEND_OP(MODE) ((MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
1468
1469 /* Define if loading short immediate values into registers sign extends. */
1470 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1471
1472 /* Nonzero if access to memory by bytes is no faster than for words. */
1473 #define SLOW_BYTE_ACCESS 1
1474
1475 /* Nonzero if the target supports dynamic shift instructions
1476 like shad and shld. */
1477 #define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
1478
1479 /* The cost of using the dynamic shift insns (shad, shld) are the same
1480 if they are available. If they are not available a library function will
1481 be emitted instead, which is more expensive. */
1482 #define SH_DYNAMIC_SHIFT_COST (TARGET_DYNSHIFT ? 1 : 20)
1483
1484 /* Defining SHIFT_COUNT_TRUNCATED tells the combine pass that code like
1485 (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1486 This is not generally true when hardware dynamic shifts (shad, shld) are
1487 used, because they check the sign bit _before_ the modulo op. The sign
1488 bit determines whether it is a left shift or a right shift:
1489 if (Y < 0)
1490 return X << (Y & 31);
1491 else
1492 return X >> (-Y) & 31);
1493
1494 The dynamic shift library routines in lib1funcs.S do not use the sign bit
1495 like the hardware dynamic shifts and truncate the shift count to 31.
1496 We define SHIFT_COUNT_TRUNCATED to 0 and express the implied shift count
1497 truncation in the library function call patterns, as this gives slightly
1498 more compact code. */
1499 #define SHIFT_COUNT_TRUNCATED (0)
1500
1501 /* Define this if addresses of constant functions
1502 shouldn't be put through pseudo regs where they can be cse'd.
1503 Desirable on machines where ordinary constants are expensive
1504 but a CALL with constant address is cheap. */
1505 /*#define NO_FUNCTION_CSE 1*/
1506
1507 /* The machine modes of pointers and functions. */
1508 #define Pmode (SImode)
1509 #define FUNCTION_MODE Pmode
1510
1511 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1512 are actually function calls with some special constraints on arguments
1513 and register usage.
1514
1515 These macros tell reorg that the references to arguments and
1516 register clobbers for insns of type sfunc do not appear to happen
1517 until after the millicode call. This allows reorg to put insns
1518 which set the argument registers into the delay slot of the millicode
1519 call -- thus they act more like traditional CALL_INSNs.
1520
1521 get_attr_is_sfunc will try to recognize the given insn, so make sure to
1522 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1523 in particular. */
1524
1525 #define INSN_SETS_ARE_DELAYED(X) \
1526 ((NONJUMP_INSN_P (X) \
1527 && GET_CODE (PATTERN (X)) != SEQUENCE \
1528 && GET_CODE (PATTERN (X)) != USE \
1529 && GET_CODE (PATTERN (X)) != CLOBBER \
1530 && get_attr_is_sfunc (X)))
1531
1532 #define INSN_REFERENCES_ARE_DELAYED(X) \
1533 ((NONJUMP_INSN_P (X) \
1534 && GET_CODE (PATTERN (X)) != SEQUENCE \
1535 && GET_CODE (PATTERN (X)) != USE \
1536 && GET_CODE (PATTERN (X)) != CLOBBER \
1537 && get_attr_is_sfunc (X)))
1538
1539 \f
1540 /* Position Independent Code. */
1541
1542 /* We can't directly access anything that contains a symbol,
1543 nor can we indirect via the constant pool. */
1544 #define LEGITIMATE_PIC_OPERAND_P(X) \
1545 ((! nonpic_symbol_mentioned_p (X) \
1546 && (GET_CODE (X) != SYMBOL_REF \
1547 || ! CONSTANT_POOL_ADDRESS_P (X) \
1548 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))))
1549
1550 #define SYMBOLIC_CONST_P(X) \
1551 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
1552 && nonpic_symbol_mentioned_p (X))
1553 \f
1554 /* Compute extra cost of moving data between one register class
1555 and another. */
1556
1557 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
1558 uses this information. Hence, the general register <-> floating point
1559 register information here is not used for SFmode. */
1560 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
1561 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \
1562 || ((CLASS) == SIBCALL_REGS))
1563
1564 #define REGCLASS_HAS_FP_REG(CLASS) \
1565 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
1566 || (CLASS) == DF_REGS)
1567
1568 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1569 would be so that people with slow memory systems could generate
1570 different code that does fewer memory accesses. */
1571
1572 /* A C expression for the cost of a branch instruction. A value of 1
1573 is the default; other values are interpreted relative to that. */
1574 #define BRANCH_COST(speed_p, predictable_p) sh_branch_cost
1575 \f
1576 /* Assembler output control. */
1577
1578 /* A C string constant describing how to begin a comment in the target
1579 assembler language. The compiler assumes that the comment will end at
1580 the end of the line. */
1581 #define ASM_COMMENT_START "!"
1582
1583 #define ASM_APP_ON ""
1584 #define ASM_APP_OFF ""
1585 #define FILE_ASM_OP "\t.file\n"
1586 #define SET_ASM_OP "\t.set\t"
1587
1588 /* How to change between sections. */
1589 #define TEXT_SECTION_ASM_OP "\t.text"
1590 #define DATA_SECTION_ASM_OP "\t.data"
1591
1592 #if defined CRT_BEGIN || defined CRT_END
1593 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
1594 #undef TEXT_SECTION_ASM_OP
1595 #define TEXT_SECTION_ASM_OP "\t.text"
1596 #endif
1597
1598 #ifndef BSS_SECTION_ASM_OP
1599 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1600 #endif
1601
1602 #ifndef ASM_OUTPUT_ALIGNED_BSS
1603 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1604 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1605 #endif
1606
1607 /* Define this so that jump tables go in same section as the current function,
1608 which could be text or it could be a user defined section. */
1609 #define JUMP_TABLES_IN_TEXT_SECTION 1
1610
1611 #undef DO_GLOBAL_CTORS_BODY
1612 #define DO_GLOBAL_CTORS_BODY \
1613 { \
1614 typedef void (*pfunc) (void); \
1615 extern pfunc __ctors[]; \
1616 extern pfunc __ctors_end[]; \
1617 pfunc *p; \
1618 for (p = __ctors_end; p > __ctors; ) \
1619 { \
1620 (*--p)(); \
1621 } \
1622 }
1623
1624 #undef DO_GLOBAL_DTORS_BODY
1625 #define DO_GLOBAL_DTORS_BODY \
1626 { \
1627 typedef void (*pfunc) (void); \
1628 extern pfunc __dtors[]; \
1629 extern pfunc __dtors_end[]; \
1630 pfunc *p; \
1631 for (p = __dtors; p < __dtors_end; p++) \
1632 { \
1633 (*p)(); \
1634 } \
1635 }
1636
1637 #define ASM_OUTPUT_REG_PUSH(file, v) \
1638 { \
1639 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
1640 }
1641
1642 #define ASM_OUTPUT_REG_POP(file, v) \
1643 { \
1644 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
1645 }
1646
1647 /* Debugger register number for a given compiler register number. */
1648 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
1649 to match gdb. */
1650 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
1651 register exists, so we should return -1 for invalid register numbers. */
1652 #define DEBUGGER_REGNO(REGNO) SH_DEBUGGER_REGNO (REGNO)
1653
1654 #define SH_DEBUGGER_REGNO(REGNO) \
1655 (IN_RANGE ((REGNO), \
1656 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1657 FIRST_GENERAL_REG + 15U) \
1658 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
1659 : ((int) (REGNO) >= FIRST_FP_REG \
1660 && ((int) (REGNO) \
1661 <= (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)))) \
1662 ? ((unsigned) (REGNO) - FIRST_FP_REG + 25) \
1663 : XD_REGISTER_P (REGNO) \
1664 ? ((unsigned) (REGNO) - FIRST_XD_REG + 87) \
1665 : (REGNO) == PR_REG \
1666 ? (17) \
1667 : (REGNO) == GBR_REG \
1668 ? (18) \
1669 : (REGNO) == MACH_REG \
1670 ? (20) \
1671 : (REGNO) == MACL_REG \
1672 ? (21) \
1673 : (REGNO) == T_REG \
1674 ? (22) \
1675 : (REGNO) == FPUL_REG \
1676 ? (23) \
1677 : (REGNO) == FPSCR_REG \
1678 ? (24) \
1679 : (unsigned) -1)
1680
1681 /* This is how to output an assembler line
1682 that says to advance the location counter
1683 to a multiple of 2**LOG bytes. */
1684
1685 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1686 if ((LOG) != 0) \
1687 fprintf ((FILE), "\t.align %d\n", (LOG))
1688
1689 /* Globalizing directive for a label. */
1690 #define GLOBAL_ASM_OP "\t.global\t"
1691
1692 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1693
1694 /* Output a relative address table. */
1695 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
1696 switch (GET_MODE (BODY)) \
1697 { \
1698 case E_SImode: \
1699 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1700 break; \
1701 case E_HImode: \
1702 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1703 break; \
1704 case E_QImode: \
1705 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1706 break; \
1707 default: \
1708 break; \
1709 }
1710
1711 /* Output an absolute table element. */
1712 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1713 do { \
1714 if (! optimize || TARGET_BIGTABLE) \
1715 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
1716 else \
1717 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); \
1718 } while (0)
1719 \f
1720 /* A C statement to be executed just prior to the output of
1721 assembler code for INSN, to modify the extracted operands so
1722 they will be output differently.
1723
1724 Here the argument OPVEC is the vector containing the operands
1725 extracted from INSN, and NOPERANDS is the number of elements of
1726 the vector which contain meaningful data for this insn.
1727 The contents of this vector are what will be used to convert the insn
1728 template into assembler code, so you can change the assembler output
1729 by changing the contents of the vector. */
1730 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1731 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
1732
1733 /* Which processor to schedule for. The elements of the enumeration must
1734 match exactly the cpu attribute in the sh.md file. */
1735 enum processor_type {
1736 PROCESSOR_SH1,
1737 PROCESSOR_SH2,
1738 PROCESSOR_SH2E,
1739 PROCESSOR_SH2A,
1740 PROCESSOR_SH3,
1741 PROCESSOR_SH3E,
1742 PROCESSOR_SH4,
1743 PROCESSOR_SH4A
1744 };
1745
1746 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
1747 extern enum processor_type sh_cpu;
1748
1749 enum mdep_reorg_phase_e
1750 {
1751 SH_BEFORE_MDEP_REORG,
1752 SH_INSERT_USES_LABELS,
1753 SH_SHORTEN_BRANCHES0,
1754 SH_FIXUP_PCLOAD,
1755 SH_SHORTEN_BRANCHES1,
1756 SH_AFTER_MDEP_REORG
1757 };
1758
1759 extern enum mdep_reorg_phase_e mdep_reorg_phase;
1760
1761 /* Handle Renesas compiler's pragmas. */
1762 #define REGISTER_TARGET_PRAGMAS() do { \
1763 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
1764 c_register_pragma (0, "trapa", sh_pr_trapa); \
1765 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
1766 } while (0)
1767
1768 extern tree sh_deferred_function_attributes;
1769 extern tree *sh_deferred_function_attributes_tail;
1770
1771
1772 \f
1773 /* Instructions with unfilled delay slots take up an
1774 extra two bytes for the nop in the delay slot.
1775 sh-dsp parallel processing insns are four bytes long. */
1776 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1777 (LENGTH) += sh_insn_length_adjustment (X);
1778 \f
1779 /* Define this macro if it is advisable to hold scalars in registers
1780 in a wider mode than that declared by the program. In such cases,
1781 the value is constrained to be within the bounds of the declared
1782 type, but kept valid in the wider mode. The signedness of the
1783 extension may differ from that of the type.
1784
1785 Leaving the unsignedp unchanged gives better code than always setting it
1786 to 0. This is despite the fact that we have only signed char and short
1787 load instructions. */
1788 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1789 if (GET_MODE_CLASS (MODE) == MODE_INT \
1790 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
1791 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), (MODE) = SImode;
1792
1793 #define MAX_FIXED_MODE_SIZE (64)
1794
1795 /* Better to allocate once the maximum space for outgoing args in the
1796 prologue rather than duplicate around each call. */
1797 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1798
1799 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
1800
1801 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_FPU_DOUBLE)
1802
1803 #define ACTUAL_NORMAL_MODE(ENTITY) \
1804 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
1805
1806 #define NORMAL_MODE(ENTITY) \
1807 (sh_cfun_interrupt_handler_p () \
1808 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
1809 : ACTUAL_NORMAL_MODE (ENTITY))
1810
1811 #define EPILOGUE_USES(REGNO) (TARGET_FPU_ANY && REGNO == FPSCR_REG)
1812
1813 #define DWARF_FRAME_RETURN_COLUMN (DWARF_FRAME_REGNUM (PR_REG))
1814
1815 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 4U : INVALID_REGNUM)
1816
1817 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
1818 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
1819
1820 /* We have to distinguish between code and data, so that we apply
1821 datalabel where and only where appropriate. Use sdataN for data. */
1822 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1823 ((TARGET_FDPIC \
1824 ? ((GLOBAL) ? DW_EH_PE_indirect | DW_EH_PE_datarel : DW_EH_PE_pcrel) \
1825 : ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
1826 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))) \
1827 | ((CODE) ? 0 : DW_EH_PE_sdata4))
1828
1829 /* Handle special EH pointer encodings. Absolute, pc-relative, and
1830 indirect are handled automatically. */
1831 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
1832 do { \
1833 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
1834 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
1835 { \
1836 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
1837 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
1838 if (0) goto DONE; \
1839 } \
1840 if (TARGET_FDPIC \
1841 && ((ENCODING) & 0xf0) == (DW_EH_PE_indirect | DW_EH_PE_datarel)) \
1842 { \
1843 fputs ("\t.ualong ", FILE); \
1844 output_addr_const (FILE, ADDR); \
1845 if (GET_CODE (ADDR) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (ADDR)) \
1846 fputs ("@GOTFUNCDESC", FILE); \
1847 else \
1848 fputs ("@GOT", FILE); \
1849 goto DONE; \
1850 } \
1851 } while (0)
1852
1853 #if (defined CRT_BEGIN || defined CRT_END)
1854 /* SH constant pool breaks the devices in crtstuff.c to control section
1855 in where code resides. We have to write it as asm code. */
1856 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1857 asm (SECTION_OP "\n\
1858 mov.l 1f,r1\n\
1859 mova 2f,r0\n\
1860 braf r1\n\
1861 lds r0,pr\n\
1862 0: .p2align 2\n\
1863 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
1864 2:\n" TEXT_SECTION_ASM_OP);
1865 #endif /* (defined CRT_BEGIN || defined CRT_END) */
1866
1867 #endif /* ! GCC_SH_H */
Mirror of the offical gcc git repository hosted at gcc.gnu.org