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testsuite: Correct vec-rlmi-rlnm.c testsuite expected result
[official-gcc.git] / gcc / config / mips / mips.h
blob3ce0c19a29a0139f7e491cafd2976a2a42e33a83
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY_SPEED
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target when optimizing code for speed, typically because
50 the branches are always predicted taken and so incur a large overhead
51 when not taken.
52
53 PTF_AVOID_BRANCHLIKELY_SIZE
54 As above but when optimizing for size.
55
56 PTF_AVOID_BRANCHLIKELY_ALWAYS
57 As above but regardless of whether we optimize for speed or size.
58
59 PTF_AVOID_IMADD
60 Set if it is usually not profitable to use the integer MADD or MSUB
61 instructions because of the overhead of getting the result out of
62 the HI/LO registers. */
63
64 #define PTF_AVOID_BRANCHLIKELY_SPEED 0x1
65 #define PTF_AVOID_BRANCHLIKELY_SIZE 0x2
66 #define PTF_AVOID_BRANCHLIKELY_ALWAYS (PTF_AVOID_BRANCHLIKELY_SPEED | \
67 PTF_AVOID_BRANCHLIKELY_SIZE)
68 #define PTF_AVOID_IMADD 0x4
69
70 /* Information about one recognized processor. Defined here for the
71 benefit of TARGET_CPU_CPP_BUILTINS. */
72 struct mips_cpu_info {
73 /* The 'canonical' name of the processor as far as GCC is concerned.
74 It's typically a manufacturer's prefix followed by a numerical
75 designation. It should be lowercase. */
76 const char *name;
77
78 /* The internal processor number that most closely matches this
79 entry. Several processors can have the same value, if there's no
80 difference between them from GCC's point of view. */
81 enum processor cpu;
82
83 /* The ISA level that the processor implements. */
84 int isa;
85
86 /* A mask of PTF_* values. */
87 unsigned int tune_flags;
88 };
89
90 #include "config/mips/mips-opts.h"
91
92 /* Macros to silence warnings about numbers being signed in traditional
93 C and unsigned in ISO C when compiled on 32-bit hosts. */
94
95 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
96 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
97 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
98
99 \f
100 /* Run-time compilation parameters selecting different hardware subsets. */
101
102 /* True if we are generating position-independent VxWorks RTP code. */
103 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
104
105 /* Compact branches must not be used if the user either selects the
106 'never' policy or the 'optimal' policy on a core that lacks
107 compact branch instructions. */
108 #define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER \
109 || (mips_cb == MIPS_CB_OPTIMAL \
110 && !ISA_HAS_COMPACT_BRANCHES))
111
112 /* Compact branches may be used if the user either selects the
113 'always' policy or the 'optimal' policy on a core that supports
114 compact branch instructions. */
115 #define TARGET_CB_MAYBE (TARGET_CB_ALWAYS \
116 || (mips_cb == MIPS_CB_OPTIMAL \
117 && ISA_HAS_COMPACT_BRANCHES))
118
119 /* Compact branches must always be generated if the user selects
120 the 'always' policy or the 'optimal' policy om a core that
121 lacks delay slot branch instructions. */
122 #define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS \
123 || (mips_cb == MIPS_CB_OPTIMAL \
124 && !ISA_HAS_DELAY_SLOTS))
125
126 /* Special handling for JRC that exists in microMIPSR3 as well as R6
127 ISAs with full compact branch support. */
128 #define ISA_HAS_JRC ((ISA_HAS_COMPACT_BRANCHES \
129 || TARGET_MICROMIPS) \
130 && mips_cb != MIPS_CB_NEVER)
131
132 /* True if the output file is marked as ".abicalls; .option pic0"
133 (-call_nonpic). */
134 #define TARGET_ABICALLS_PIC0 \
135 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
136
137 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
138 #define TARGET_ABICALLS_PIC2 \
139 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
140
141 /* True if the call patterns should be split into a jalr followed by
142 an instruction to restore $gp. It is only safe to split the load
143 from the call when every use of $gp is explicit.
144
145 See mips_must_initialize_gp_p for details about how we manage the
146 global pointer. */
147
148 #define TARGET_SPLIT_CALLS \
149 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
150
151 /* True if we're generating a form of -mabicalls in which we can use
152 operators like %hi and %lo to refer to locally-binding symbols.
153 We can only do this for -mno-shared, and only then if we can use
154 relocation operations instead of assembly macros. It isn't really
155 worth using absolute sequences for 64-bit symbols because GOT
156 accesses are so much shorter. */
157
158 #define TARGET_ABSOLUTE_ABICALLS \
159 (TARGET_ABICALLS \
160 && !TARGET_SHARED \
161 && TARGET_EXPLICIT_RELOCS \
162 && !ABI_HAS_64BIT_SYMBOLS)
163
164 /* True if we can optimize sibling calls. For simplicity, we only
165 handle cases in which call_insn_operand will reject invalid
166 sibcall addresses. There are two cases in which this isn't true:
167
168 - TARGET_MIPS16. call_insn_operand accepts constant addresses
169 but there is no direct jump instruction. It isn't worth
170 using sibling calls in this case anyway; they would usually
171 be longer than normal calls.
172
173 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
174 accepts global constants, but all sibcalls must be indirect. */
175 #define TARGET_SIBCALLS \
176 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
177
178 /* True if we need to use a global offset table to access some symbols. */
179 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
180
181 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
182 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
183
184 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
185 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
186
187 /* True if we should use .cprestore to store to the cprestore slot.
188
189 We continue to use .cprestore for explicit-reloc code so that JALs
190 inside inline asms will work correctly. */
191 #define TARGET_CPRESTORE_DIRECTIVE \
192 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
193
194 /* True if we can use the J and JAL instructions. */
195 #define TARGET_ABSOLUTE_JUMPS \
196 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
197
198 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
199 This is true for both the PIC and non-PIC VxWorks RTP modes. */
200 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
201
202 /* True if .gpword or .gpdword should be used for switch tables. */
203 #define TARGET_GPWORD \
204 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
205
206 /* True if the output must have a writable .eh_frame.
207 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
208 #ifdef HAVE_LD_PERSONALITY_RELAXATION
209 #define TARGET_WRITABLE_EH_FRAME 0
210 #else
211 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
212 #endif
213
214 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
215 #ifdef HAVE_AS_DSPR1_MULT
216 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
217 #else
218 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
219 #endif
220
221 /* ISA has LSA available. */
222 #define ISA_HAS_LSA (mips_isa_rev >= 6 || ISA_HAS_MSA)
223
224 /* ISA has DLSA available. */
225 #define ISA_HAS_DLSA (TARGET_64BIT \
226 && (mips_isa_rev >= 6 \
227 || ISA_HAS_MSA))
228
229 /* The ISA compression flags that are currently in effect. */
230 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
231
232 /* Generate mips16 code */
233 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
234 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
235 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
236 /* Generate mips16e register save/restore sequences. */
237 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
238
239 /* True if we're generating a form of MIPS16 code in which general
240 text loads are allowed. */
241 #define TARGET_MIPS16_TEXT_LOADS \
242 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
243
244 /* True if we're generating a form of MIPS16 code in which PC-relative
245 loads are allowed. */
246 #define TARGET_MIPS16_PCREL_LOADS \
247 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
248
249 /* Generic ISA defines. */
250 #define ISA_MIPS1 (mips_isa == 1)
251 #define ISA_MIPS2 (mips_isa == 2)
252 #define ISA_MIPS3 (mips_isa == 3)
253 #define ISA_MIPS4 (mips_isa == 4)
254 #define ISA_MIPS32 (mips_isa == 32)
255 #define ISA_MIPS32R2 (mips_isa == 33)
256 #define ISA_MIPS32R3 (mips_isa == 34)
257 #define ISA_MIPS32R5 (mips_isa == 36)
258 #define ISA_MIPS32R6 (mips_isa == 37)
259 #define ISA_MIPS64 (mips_isa == 64)
260 #define ISA_MIPS64R2 (mips_isa == 65)
261 #define ISA_MIPS64R3 (mips_isa == 66)
262 #define ISA_MIPS64R5 (mips_isa == 68)
263 #define ISA_MIPS64R6 (mips_isa == 69)
264
265 /* Architecture target defines. */
266 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
267 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
268 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
269 #define TARGET_GS464 (mips_arch == PROCESSOR_GS464)
270 #define TARGET_GS464E (mips_arch == PROCESSOR_GS464E)
271 #define TARGET_GS264E (mips_arch == PROCESSOR_GS264E)
272 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
273 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
274 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
275 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
276 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
277 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
278 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
279 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
280 #define TARGET_MIPS8000 (mips_arch == PROCESSOR_R8000)
281 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
282 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
283 || mips_arch == PROCESSOR_OCTEON2 \
284 || mips_arch == PROCESSOR_OCTEON3)
285 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \
286 || mips_arch == PROCESSOR_OCTEON3)
287 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
288 || mips_arch == PROCESSOR_SB1A)
289 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
290 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
291
292 /* Scheduling target defines. */
293 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
294 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
295 || mips_tune == PROCESSOR_24KF2_1 \
296 || mips_tune == PROCESSOR_24KF1_1)
297 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
298 || mips_tune == PROCESSOR_74KF2_1 \
299 || mips_tune == PROCESSOR_74KF1_1 \
300 || mips_tune == PROCESSOR_74KF3_2)
301 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
302 || mips_tune == PROCESSOR_LOONGSON_2F)
303 #define TUNE_GS464 (mips_tune == PROCESSOR_GS464)
304 #define TUNE_GS464E (mips_tune == PROCESSOR_GS464E)
305 #define TUNE_GS264E (mips_tune == PROCESSOR_GS264E)
306 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
307 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
308 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
309 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
310 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
311 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
312 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
313 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
314 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
315 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
316 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
317 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
318 || mips_tune == PROCESSOR_OCTEON2 \
319 || mips_tune == PROCESSOR_OCTEON3)
320 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
321 || mips_tune == PROCESSOR_SB1A)
322 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
323 #define TUNE_I6400 (mips_tune == PROCESSOR_I6400)
324 #define TUNE_P6600 (mips_tune == PROCESSOR_P6600)
325
326 /* True if the pre-reload scheduler should try to create chains of
327 multiply-add or multiply-subtract instructions. For example,
328 suppose we have:
329
330 t1 = a * b
331 t2 = t1 + c * d
332 t3 = e * f
333 t4 = t3 - g * h
334
335 t1 will have a higher priority than t2 and t3 will have a higher
336 priority than t4. However, before reload, there is no dependence
337 between t1 and t3, and they can often have similar priorities.
338 The scheduler will then tend to prefer:
339
340 t1 = a * b
341 t3 = e * f
342 t2 = t1 + c * d
343 t4 = t3 - g * h
344
345 which stops us from making full use of macc/madd-style instructions.
346 This sort of situation occurs frequently in Fourier transforms and
347 in unrolled loops.
348
349 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
350 queue so that chained multiply-add and multiply-subtract instructions
351 appear ahead of any other instruction that is likely to clobber lo.
352 In the example above, if t2 and t3 become ready at the same time,
353 the code ensures that t2 is scheduled first.
354
355 Multiply-accumulate instructions are a bigger win for some targets
356 than others, so this macro is defined on an opt-in basis. */
357 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
358 || TUNE_MIPS4120 \
359 || TUNE_MIPS4130 \
360 || TUNE_24K \
361 || TUNE_P5600)
362
363 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
364 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
365
366 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
367 directly accessible, while the command-line options select
368 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
369 in use. */
370 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
371 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
372
373 /* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents
374 -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */
375 #define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX)
376
377 /* TARGET_O32_FP64A_ABI represents all the conditions that form the
378 o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */
379 #define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \
380 && !TARGET_ODD_SPREG)
381
382 /* False if SC acts as a memory barrier with respect to itself,
383 otherwise a SYNC will be emitted after SC for atomic operations
384 that require ordering between the SC and following loads and
385 stores. It does not tell anything about ordering of loads and
386 stores prior to and following the SC, only about the SC itself and
387 those loads and stores follow it. */
388 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
389
390 /* Define preprocessor macros for the -march and -mtune options.
391 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
392 processor. If INFO's canonical name is "foo", define PREFIX to
393 be "foo", and define an additional macro PREFIX_FOO. */
394 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
395 do \
396 { \
397 char *macro, *p; \
398 \
399 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
400 for (p = macro; *p != 0; p++) \
401 if (*p == '+') \
402 *p = 'P'; \
403 else \
404 *p = TOUPPER (*p); \
405 \
406 builtin_define (macro); \
407 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
408 free (macro); \
409 } \
410 while (0)
411
412 /* Target CPU builtins. */
413 #define TARGET_CPU_CPP_BUILTINS() \
414 do \
415 { \
416 builtin_assert ("machine=mips"); \
417 builtin_assert ("cpu=mips"); \
418 builtin_define ("__mips__"); \
419 builtin_define ("_mips"); \
420 \
421 /* We do this here because __mips is defined below and so we \
422 can't use builtin_define_std. We don't ever want to define \
423 "mips" for VxWorks because some of the VxWorks headers \
424 construct include filenames from a root directory macro, \
425 an architecture macro and a filename, where the architecture \
426 macro expands to 'mips'. If we define 'mips' to 1, the \
427 architecture macro expands to 1 as well. */ \
428 if (!flag_iso && !TARGET_VXWORKS) \
429 builtin_define ("mips"); \
430 \
431 if (TARGET_64BIT) \
432 builtin_define ("__mips64"); \
433 \
434 /* Treat _R3000 and _R4000 like register-size \
435 defines, which is how they've historically \
436 been used. */ \
437 if (TARGET_64BIT) \
438 { \
439 builtin_define_std ("R4000"); \
440 builtin_define ("_R4000"); \
441 } \
442 else \
443 { \
444 builtin_define_std ("R3000"); \
445 builtin_define ("_R3000"); \
446 } \
447 \
448 if (TARGET_FLOAT64) \
449 builtin_define ("__mips_fpr=64"); \
450 else if (TARGET_FLOATXX) \
451 builtin_define ("__mips_fpr=0"); \
452 else \
453 builtin_define ("__mips_fpr=32"); \
454 \
455 if (mips_base_compression_flags & MASK_MIPS16) \
456 builtin_define ("__mips16"); \
457 \
458 if (TARGET_MIPS3D) \
459 builtin_define ("__mips3d"); \
460 \
461 if (TARGET_SMARTMIPS) \
462 builtin_define ("__mips_smartmips"); \
463 \
464 if (mips_base_compression_flags & MASK_MICROMIPS) \
465 builtin_define ("__mips_micromips"); \
466 \
467 if (TARGET_MCU) \
468 builtin_define ("__mips_mcu"); \
469 \
470 if (TARGET_EVA) \
471 builtin_define ("__mips_eva"); \
472 \
473 if (TARGET_DSP) \
474 { \
475 builtin_define ("__mips_dsp"); \
476 if (TARGET_DSPR2) \
477 { \
478 builtin_define ("__mips_dspr2"); \
479 builtin_define ("__mips_dsp_rev=2"); \
480 } \
481 else \
482 builtin_define ("__mips_dsp_rev=1"); \
483 } \
484 \
485 if (ISA_HAS_MSA) \
486 { \
487 builtin_define ("__mips_msa"); \
488 builtin_define ("__mips_msa_width=128"); \
489 } \
490 \
491 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
492 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
493 \
494 if (ISA_MIPS1) \
495 { \
496 builtin_define ("__mips=1"); \
497 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
498 } \
499 else if (ISA_MIPS2) \
500 { \
501 builtin_define ("__mips=2"); \
502 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
503 } \
504 else if (ISA_MIPS3) \
505 { \
506 builtin_define ("__mips=3"); \
507 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
508 } \
509 else if (ISA_MIPS4) \
510 { \
511 builtin_define ("__mips=4"); \
512 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
513 } \
514 else if (mips_isa >= 32 && mips_isa < 64) \
515 { \
516 builtin_define ("__mips=32"); \
517 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
518 } \
519 else if (mips_isa >= 64) \
520 { \
521 builtin_define ("__mips=64"); \
522 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
523 } \
524 if (mips_isa_rev > 0) \
525 builtin_define_with_int_value ("__mips_isa_rev", \
526 mips_isa_rev); \
527 \
528 switch (mips_abi) \
529 { \
530 case ABI_32: \
531 builtin_define ("_ABIO32=1"); \
532 builtin_define ("_MIPS_SIM=_ABIO32"); \
533 break; \
534 \
535 case ABI_N32: \
536 builtin_define ("_ABIN32=2"); \
537 builtin_define ("_MIPS_SIM=_ABIN32"); \
538 break; \
539 \
540 case ABI_64: \
541 builtin_define ("_ABI64=3"); \
542 builtin_define ("_MIPS_SIM=_ABI64"); \
543 break; \
544 \
545 case ABI_O64: \
546 builtin_define ("_ABIO64=4"); \
547 builtin_define ("_MIPS_SIM=_ABIO64"); \
548 break; \
549 } \
550 \
551 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
552 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
553 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
554 builtin_define_with_int_value ("_MIPS_FPSET", \
555 32 / MAX_FPRS_PER_FMT); \
556 builtin_define_with_int_value ("_MIPS_SPFPSET", \
557 TARGET_ODD_SPREG ? 32 : 16); \
558 \
559 /* These defines reflect the ABI in use, not whether the \
560 FPU is directly accessible. */ \
561 if (TARGET_NO_FLOAT) \
562 builtin_define ("__mips_no_float"); \
563 else if (TARGET_HARD_FLOAT_ABI) \
564 builtin_define ("__mips_hard_float"); \
565 else \
566 builtin_define ("__mips_soft_float"); \
567 \
568 if (TARGET_SINGLE_FLOAT) \
569 builtin_define ("__mips_single_float"); \
570 \
571 if (TARGET_PAIRED_SINGLE_FLOAT) \
572 builtin_define ("__mips_paired_single_float"); \
573 \
574 if (mips_abs == MIPS_IEEE_754_2008) \
575 builtin_define ("__mips_abs2008"); \
576 \
577 if (mips_nan == MIPS_IEEE_754_2008) \
578 builtin_define ("__mips_nan2008"); \
579 \
580 if (TARGET_BIG_ENDIAN) \
581 { \
582 builtin_define_std ("MIPSEB"); \
583 builtin_define ("_MIPSEB"); \
584 } \
585 else \
586 { \
587 builtin_define_std ("MIPSEL"); \
588 builtin_define ("_MIPSEL"); \
589 } \
590 \
591 /* Whether calls should go through $25. The separate __PIC__ \
592 macro indicates whether abicalls code might use a GOT. */ \
593 if (TARGET_ABICALLS) \
594 builtin_define ("__mips_abicalls"); \
595 \
596 /* Whether Loongson vector modes are enabled. */ \
597 if (TARGET_LOONGSON_MMI) \
598 { \
599 builtin_define ("__mips_loongson_vector_rev"); \
600 builtin_define ("__mips_loongson_mmi"); \
601 } \
602 \
603 /* Whether Loongson EXT modes are enabled. */ \
604 if (TARGET_LOONGSON_EXT) \
605 { \
606 builtin_define ("__mips_loongson_ext"); \
607 if (TARGET_LOONGSON_EXT2) \
608 { \
609 builtin_define ("__mips_loongson_ext2"); \
610 builtin_define ("__mips_loongson_ext_rev=2"); \
611 } \
612 else \
613 builtin_define ("__mips_loongson_ext_rev=1"); \
614 } \
615 \
616 /* Historical Octeon macro. */ \
617 if (TARGET_OCTEON) \
618 builtin_define ("__OCTEON__"); \
619 \
620 if (TARGET_SYNCI) \
621 builtin_define ("__mips_synci"); \
622 \
623 /* Macros dependent on the C dialect. */ \
624 if (preprocessing_asm_p ()) \
625 { \
626 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
627 builtin_define ("_LANGUAGE_ASSEMBLY"); \
628 } \
629 else if (c_dialect_cxx ()) \
630 { \
631 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
632 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
633 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
634 } \
635 else \
636 { \
637 builtin_define_std ("LANGUAGE_C"); \
638 builtin_define ("_LANGUAGE_C"); \
639 } \
640 if (c_dialect_objc ()) \
641 { \
642 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
643 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
644 /* Bizarre, but retained for backwards compatibility. */ \
645 builtin_define_std ("LANGUAGE_C"); \
646 builtin_define ("_LANGUAGE_C"); \
647 } \
648 \
649 if (mips_abi == ABI_EABI) \
650 builtin_define ("__mips_eabi"); \
651 \
652 if (TARGET_CACHE_BUILTIN) \
653 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
654 if (!ISA_HAS_LXC1_SXC1) \
655 builtin_define ("__mips_no_lxc1_sxc1"); \
656 if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4) \
657 builtin_define ("__mips_no_madd4"); \
658 } \
659 while (0)
660
661 /* Target CPU versions for D. */
662 #define TARGET_D_CPU_VERSIONS mips_d_target_versions
663
664 /* Default target_flags if no switches are specified */
665
666 #ifndef TARGET_DEFAULT
667 #define TARGET_DEFAULT 0
668 #endif
669
670 #ifndef TARGET_CPU_DEFAULT
671 #define TARGET_CPU_DEFAULT 0
672 #endif
673
674 #ifndef TARGET_ENDIAN_DEFAULT
675 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
676 #endif
677
678 #ifdef IN_LIBGCC2
679 #undef TARGET_64BIT
680 /* Make this compile time constant for libgcc2 */
681 #ifdef __mips64
682 #define TARGET_64BIT 1
683 #else
684 #define TARGET_64BIT 0
685 #endif
686 #endif /* IN_LIBGCC2 */
687
688 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
689 when compiled with hardware floating point. This is because MIPS16
690 code cannot save and restore the floating-point registers, which is
691 important if in a mixed MIPS16/non-MIPS16 environment. */
692
693 #ifdef IN_LIBGCC2
694 #if __mips_hard_float
695 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
696 #endif
697 #endif /* IN_LIBGCC2 */
698
699 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
700
701 #ifndef MULTILIB_ENDIAN_DEFAULT
702 #if TARGET_ENDIAN_DEFAULT == 0
703 #define MULTILIB_ENDIAN_DEFAULT "EL"
704 #else
705 #define MULTILIB_ENDIAN_DEFAULT "EB"
706 #endif
707 #endif
708
709 #ifndef MULTILIB_ISA_DEFAULT
710 #if MIPS_ISA_DEFAULT == 1
711 #define MULTILIB_ISA_DEFAULT "mips1"
712 #elif MIPS_ISA_DEFAULT == 2
713 #define MULTILIB_ISA_DEFAULT "mips2"
714 #elif MIPS_ISA_DEFAULT == 3
715 #define MULTILIB_ISA_DEFAULT "mips3"
716 #elif MIPS_ISA_DEFAULT == 4
717 #define MULTILIB_ISA_DEFAULT "mips4"
718 #elif MIPS_ISA_DEFAULT == 32
719 #define MULTILIB_ISA_DEFAULT "mips32"
720 #elif MIPS_ISA_DEFAULT == 33
721 #define MULTILIB_ISA_DEFAULT "mips32r2"
722 #elif MIPS_ISA_DEFAULT == 37
723 #define MULTILIB_ISA_DEFAULT "mips32r6"
724 #elif MIPS_ISA_DEFAULT == 64
725 #define MULTILIB_ISA_DEFAULT "mips64"
726 #elif MIPS_ISA_DEFAULT == 65
727 #define MULTILIB_ISA_DEFAULT "mips64r2"
728 #elif MIPS_ISA_DEFAULT == 69
729 #define MULTILIB_ISA_DEFAULT "mips64r6"
730 #else
731 #define MULTILIB_ISA_DEFAULT "mips1"
732 #endif
733 #endif
734
735 #ifndef MIPS_ABI_DEFAULT
736 #define MIPS_ABI_DEFAULT ABI_32
737 #endif
738
739 /* Use the most portable ABI flag for the ASM specs. */
740
741 #if MIPS_ABI_DEFAULT == ABI_32
742 #define MULTILIB_ABI_DEFAULT "mabi=32"
743 #elif MIPS_ABI_DEFAULT == ABI_O64
744 #define MULTILIB_ABI_DEFAULT "mabi=o64"
745 #elif MIPS_ABI_DEFAULT == ABI_N32
746 #define MULTILIB_ABI_DEFAULT "mabi=n32"
747 #elif MIPS_ABI_DEFAULT == ABI_64
748 #define MULTILIB_ABI_DEFAULT "mabi=64"
749 #elif MIPS_ABI_DEFAULT == ABI_EABI
750 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
751 #endif
752
753 #ifndef MULTILIB_DEFAULTS
754 #define MULTILIB_DEFAULTS \
755 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
756 #endif
757
758 /* We must pass -EL to the linker by default for little endian embedded
759 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
760 linker will default to using big-endian output files. The OUTPUT_FORMAT
761 line must be in the linker script, otherwise -EB/-EL will not work. */
762
763 #ifndef ENDIAN_SPEC
764 #if TARGET_ENDIAN_DEFAULT == 0
765 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
766 #else
767 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
768 #endif
769 #endif
770
771 /* A spec condition that matches all non-mips16 -mips arguments. */
772
773 #define MIPS_ISA_LEVEL_OPTION_SPEC \
774 "mips1|mips2|mips3|mips4|mips32*|mips64*"
775
776 /* A spec condition that matches all non-mips16 architecture arguments. */
777
778 #define MIPS_ARCH_OPTION_SPEC \
779 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
780
781 /* A spec that infers a -mips argument from an -march argument. */
782
783 #define MIPS_ISA_LEVEL_SPEC \
784 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
785 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
786 %{march=mips2|march=r6000:-mips2} \
787 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
788 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
789 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
790 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
791 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
792 |march=34k*|march=74k*|march=m14k*|march=1004k* \
793 |march=interaptiv: -mips32r2} \
794 %{march=mips32r3: -mips32r3} \
795 %{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \
796 %{march=mips32r6: -mips32r6} \
797 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
798 |march=xlr: -mips64} \
799 %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=gs264e \
800 |march=octeon|march=xlp: -mips64r2} \
801 %{march=mips64r3: -mips64r3} \
802 %{march=mips64r5: -mips64r5} \
803 %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}"
804
805 /* A spec that injects the default multilib ISA if no architecture is
806 specified. */
807
808 #define MIPS_DEFAULT_ISA_LEVEL_SPEC \
809 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
810 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
811
812 /* A spec that infers a -mhard-float or -msoft-float setting from an
813 -march argument. Note that soft-float and hard-float code are not
814 link-compatible. */
815
816 #define MIPS_ARCH_FLOAT_SPEC \
817 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
818 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
819 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
820 |march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \
821 march=*: -mhard-float}"
822
823 /* A spec condition that matches 32-bit options. It only works if
824 MIPS_ISA_LEVEL_SPEC has been applied. */
825
826 #define MIPS_32BIT_OPTION_SPEC \
827 "mips1|mips2|mips32*|mgp32"
828
829 /* A spec condition that matches architectures should be targeted with
830 o32 FPXX for compatibility reasons. */
831 #define MIPS_FPXX_OPTION_SPEC \
832 "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \
833 mips64|mips64r2|mips64r3|mips64r5"
834
835 /* Infer a -msynci setting from a -mips argument, on the assumption that
836 -msynci is desired where possible. */
837 #define MIPS_ISA_SYNCI_SPEC \
838 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \
839 |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}"
840
841 /* Infer a -mnan=2008 setting from a -mips argument. */
842 #define MIPS_ISA_NAN2008_SPEC \
843 "%{mnan*:;mips32r6|mips64r6:-mnan=2008;march=m51*: \
844 %{!msoft-float:-mnan=2008}}"
845
846 #if (MIPS_ABI_DEFAULT == ABI_O64 \
847 || MIPS_ABI_DEFAULT == ABI_N32 \
848 || MIPS_ABI_DEFAULT == ABI_64)
849 #define OPT_ARCH64 "mabi=32|mgp32:;"
850 #define OPT_ARCH32 "mabi=32|mgp32"
851 #else
852 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
853 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
854 #endif
855
856 /* Support for a compile-time default CPU, et cetera. The rules are:
857 --with-arch is ignored if -march is specified or a -mips is specified
858 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
859 --with-tune is ignored if -mtune is specified; likewise
860 --with-tune-32 and --with-tune-64.
861 --with-abi is ignored if -mabi is specified.
862 --with-float is ignored if -mhard-float or -msoft-float are
863 specified.
864 --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are
865 specified.
866 --with-nan is ignored if -mnan is specified.
867 --with-fp-32 is ignored if -msoft-float, -msingle-float, -mmsa or -mfp are
868 specified.
869 --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg
870 or -mno-odd-spreg are specified.
871 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
872 specified. */
873 #define OPTION_DEFAULT_SPECS \
874 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
875 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
876 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
877 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
878 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
879 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
880 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
881 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
882 {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \
883 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
884 {"fp_32", "%{" OPT_ARCH32 \
885 ":%{!msoft-float:%{!msingle-float:%{!mfp*:%{!mmsa:-mfp%(VALUE)}}}}}" }, \
886 {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \
887 "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \
888 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
889 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
890 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
891 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \
892 {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \
893 {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" } \
894
895 /* A spec that infers the:
896 -mnan=2008 setting from a -mips argument,
897 -mdsp setting from a -march argument.
898 -mloongson-mmi setting from a -march argument. */
899 #define BASE_DRIVER_SELF_SPECS \
900 MIPS_ISA_NAN2008_SPEC, \
901 MIPS_ASE_DSP_SPEC, \
902 MIPS_ASE_LOONGSON_MMI_SPEC, \
903 MIPS_ASE_LOONGSON_EXT_SPEC, \
904 MIPS_ASE_MSA_SPEC
905
906
907 #define MIPS_ASE_DSP_SPEC \
908 "%{!mno-dsp: \
909 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k* \
910 |march=interaptiv: -mdsp} \
911 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
912
913 #define MIPS_ASE_LOONGSON_MMI_SPEC \
914 "%{!mno-loongson-mmi: \
915 %{march=loongson2e|march=loongson2f|march=loongson3a: -mloongson-mmi}}"
916
917 #define MIPS_ASE_LOONGSON_EXT_SPEC \
918 "%{!mno-loongson-ext: \
919 %{march=loongson3a|march=gs464: -mloongson-ext} \
920 %{march=gs464e|march=gs264e: %{!mno-loongson-ext2: \
921 -mloongson-ext2 -mloongson-ext}}}"
922
923 #define MIPS_ASE_MSA_SPEC \
924 "%{!mno-msa: \
925 %{march=gs264e: -mmsa}}"
926
927 #define DRIVER_SELF_SPECS \
928 MIPS_ISA_LEVEL_SPEC, \
929 BASE_DRIVER_SELF_SPECS
930
931 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
932 && ISA_HAS_COND_TRAP)
933
934 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
935
936 /* True if the ABI can only work with 64-bit integer registers. We
937 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
938 otherwise floating-point registers must also be 64-bit. */
939 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
940
941 /* Likewise for 32-bit regs. */
942 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
943
944 /* True if the file format uses 64-bit symbols. At present, this is
945 only true for n64, which uses 64-bit ELF. */
946 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
947
948 /* True if symbols are 64 bits wide. This is usually determined by
949 the ABI's file format, but it can be overridden by -msym32. Note that
950 overriding the size with -msym32 changes the ABI of relocatable objects,
951 although it doesn't change the ABI of a fully-linked object. */
952 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
953 && Pmode == DImode \
954 && !TARGET_SYM32)
955
956 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
957 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
958 || ISA_MIPS4 \
959 || ISA_MIPS64 \
960 || ISA_MIPS64R2 \
961 || ISA_MIPS64R3 \
962 || ISA_MIPS64R5 \
963 || ISA_MIPS64R6)
964
965 #define ISA_HAS_JR (mips_isa_rev <= 5)
966
967 #define ISA_HAS_DELAY_SLOTS 1
968
969 #define ISA_HAS_COMPACT_BRANCHES (mips_isa_rev >= 6)
970
971 /* ISA has branch likely instructions (e.g. mips2). */
972 /* Disable branchlikely for tx39 until compare rewrite. They haven't
973 been generated up to this point. */
974 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5)
975
976 /* ISA has 32 single-precision registers. */
977 #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \
978 && !TARGET_GS464) \
979 || TARGET_FLOAT64 \
980 || TARGET_MIPS5900)
981
982 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
983 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
984 || TARGET_MIPS5400 \
985 || TARGET_MIPS5500 \
986 || TARGET_MIPS5900 \
987 || TARGET_MIPS7000 \
988 || TARGET_MIPS9000 \
989 || TARGET_MAD \
990 || (mips_isa_rev >= 1 \
991 && mips_isa_rev <= 5)) \
992 && !TARGET_MIPS16)
993
994 /* ISA has a three-operand multiplication instruction. */
995 #define ISA_HAS_DMUL3 (TARGET_64BIT \
996 && TARGET_OCTEON \
997 && !TARGET_MIPS16)
998
999 /* ISA has HI and LO registers. */
1000 #define ISA_HAS_HILO (mips_isa_rev <= 5)
1001
1002 /* ISA supports instructions DMULT and DMULTU. */
1003 #define ISA_HAS_DMULT (TARGET_64BIT \
1004 && !TARGET_MIPS5900 \
1005 && mips_isa_rev <= 5)
1006
1007 /* ISA supports instructions MULT and MULTU. */
1008 #define ISA_HAS_MULT (mips_isa_rev <= 5)
1009
1010 /* ISA supports instructions MUL, MULU, MUH, MUHU. */
1011 #define ISA_HAS_R6MUL (mips_isa_rev >= 6)
1012
1013 /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */
1014 #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6)
1015
1016 /* For Loongson, it is preferable to use the Loongson-specific division and
1017 modulo instructions instead of the regular (D)DIV(U) instruction,
1018 because the former are faster and can also have the effect of reducing
1019 code size. */
1020 #define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \
1021 || TARGET_GS464) \
1022 && !TARGET_MIPS16)
1023
1024 /* ISA supports instructions DDIV and DDIVU. */
1025 #define ISA_HAS_DDIV (TARGET_64BIT \
1026 && !TARGET_MIPS5900 \
1027 && !ISA_AVOID_DIV_HILO \
1028 && mips_isa_rev <= 5)
1029
1030 /* ISA supports instructions DIV and DIVU.
1031 This is always true, but the macro is needed for ISA_HAS_<D>DIV
1032 in mips.md. */
1033 #define ISA_HAS_DIV (!ISA_AVOID_DIV_HILO \
1034 && mips_isa_rev <= 5)
1035
1036 /* ISA supports instructions DIV, DIVU, MOD and MODU. */
1037 #define ISA_HAS_R6DIV (mips_isa_rev >= 6)
1038
1039 /* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */
1040 #define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6)
1041
1042 /* ISA has the floating-point conditional move instructions introduced
1043 in mips4. */
1044 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
1045 || (mips_isa_rev >= 1 \
1046 && mips_isa_rev <= 5)) \
1047 && !TARGET_MIPS5500 \
1048 && !TARGET_MIPS16)
1049
1050 /* ISA has the integer conditional move instructions introduced in mips4 and
1051 ST Loongson 2E/2F. */
1052 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
1053 || TARGET_MIPS5900 \
1054 || TARGET_LOONGSON_2EF)
1055
1056 /* ISA has LDC1 and SDC1. */
1057 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
1058 && !TARGET_MIPS5900 \
1059 && !TARGET_MIPS16)
1060
1061 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
1062 branch on CC, and move (both FP and non-FP) on CC. */
1063 #define ISA_HAS_8CC (ISA_MIPS4 \
1064 || (mips_isa_rev >= 1 \
1065 && mips_isa_rev <= 5))
1066
1067 /* ISA has the FP condition code instructions that store the flag in an
1068 FP register. */
1069 #define ISA_HAS_CCF (mips_isa_rev >= 6)
1070
1071 #define ISA_HAS_SEL (mips_isa_rev >= 6)
1072
1073 /* This is a catch all for other mips4 instructions: indexed load, the
1074 FP madd and msub instructions, and the FP recip and recip sqrt
1075 instructions. Note that this macro should only be used by other
1076 ISA_HAS_* macros. */
1077 #define ISA_HAS_FP4 ((ISA_MIPS4 \
1078 || ISA_MIPS64 \
1079 || (mips_isa_rev >= 2 \
1080 && mips_isa_rev <= 5)) \
1081 && !TARGET_MIPS16)
1082
1083 /* ISA has floating-point indexed load and store instructions
1084 (LWXC1, LDXC1, SWXC1 and SDXC1). */
1085 #define ISA_HAS_LXC1_SXC1 (ISA_HAS_FP4 \
1086 && mips_lxc1_sxc1)
1087
1088 /* ISA has paired-single instructions. */
1089 #define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \
1090 || (mips_isa_rev >= 2 \
1091 && mips_isa_rev <= 5)) \
1092 && !TARGET_OCTEON)
1093
1094 /* ISA has conditional trap instructions. */
1095 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
1096 && !TARGET_MIPS16)
1097
1098 /* ISA has conditional trap with immediate instructions. */
1099 #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \
1100 && mips_isa_rev <= 5 \
1101 && !TARGET_MIPS16)
1102
1103 /* ISA has integer multiply-accumulate instructions, madd and msub. */
1104 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \
1105 && mips_isa_rev <= 5)
1106
1107 /* Integer multiply-accumulate instructions should be generated. */
1108 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
1109
1110 /* ISA has 4 operand fused madd instructions of the form
1111 'd = [+-] (a * b [+-] c)'. */
1112 #define ISA_HAS_FUSED_MADD4 (mips_madd4 \
1113 && (TARGET_MIPS8000 \
1114 || TARGET_GS464 \
1115 || TARGET_GS464E \
1116 || TARGET_GS264E))
1117
1118 /* ISA has 4 operand unfused madd instructions of the form
1119 'd = [+-] (a * b [+-] c)'. */
1120 #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \
1121 && ISA_HAS_FP4 \
1122 && !TARGET_MIPS8000 \
1123 && !TARGET_GS464 \
1124 && !TARGET_GS464E \
1125 && !TARGET_GS264E)
1126
1127 /* ISA has 3 operand r6 fused madd instructions of the form
1128 'c = c [+-] (a * b)'. */
1129 #define ISA_HAS_FUSED_MADDF (mips_isa_rev >= 6)
1130
1131 /* ISA has 3 operand loongson fused madd instructions of the form
1132 'c = [+-] (a * b [+-] c)'. */
1133 #define ISA_HAS_FUSED_MADD3 TARGET_LOONGSON_2EF
1134
1135 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
1136 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
1137 doubles are stored in pairs of FPRs, so for safety's sake, we apply
1138 this restriction to the MIPS IV ISA too. */
1139 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
1140 (((ISA_HAS_FP4 \
1141 && ((MODE) == SFmode \
1142 || ((TARGET_FLOAT64 \
1143 || mips_isa_rev >= 2) \
1144 && (MODE) == DFmode))) \
1145 || (((MODE) == SFmode \
1146 || (MODE) == DFmode) \
1147 && (mips_isa_rev >= 6)) \
1148 || (TARGET_SB1 \
1149 && (MODE) == V2SFmode)) \
1150 && !TARGET_MIPS16)
1151
1152 #define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16)
1153
1154 #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5)
1155
1156 #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2)
1157
1158 /* ISA has count leading zeroes/ones instruction (not implemented). */
1159 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
1160
1161 /* ISA has count trailing zeroes/ones instruction. */
1162 #define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2)
1163
1164 /* ISA has three operand multiply instructions that put
1165 the high part in an accumulator: mulhi or mulhiu. */
1166 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
1167 || TARGET_MIPS5500 \
1168 || TARGET_SR71K) \
1169 && !TARGET_MIPS16)
1170
1171 /* ISA has three operand multiply instructions that negate the
1172 result and put the result in an accumulator. */
1173 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
1174 || TARGET_MIPS5500 \
1175 || TARGET_SR71K) \
1176 && !TARGET_MIPS16)
1177
1178 /* ISA has three operand multiply instructions that subtract the
1179 result from a 4th operand and put the result in an accumulator. */
1180 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
1181 || TARGET_MIPS5500 \
1182 || TARGET_SR71K) \
1183 && !TARGET_MIPS16)
1184
1185 /* ISA has three operand multiply instructions that add the result
1186 to a 4th operand and put the result in an accumulator. */
1187 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
1188 || TARGET_MIPS4130 \
1189 || TARGET_MIPS5400 \
1190 || TARGET_MIPS5500 \
1191 || TARGET_SR71K) \
1192 && !TARGET_MIPS16)
1193
1194 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
1195 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
1196 || TARGET_MIPS4130) \
1197 && !TARGET_MIPS16)
1198
1199 /* ISA has the "ror" (rotate right) instructions. */
1200 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
1201 || TARGET_MIPS5400 \
1202 || TARGET_MIPS5500 \
1203 || TARGET_SR71K \
1204 || TARGET_SMARTMIPS) \
1205 && !TARGET_MIPS16)
1206
1207 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1208 64-bit targets also provide DSBH and DSHD. */
1209 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1210
1211 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1212 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1213 || TARGET_LOONGSON_2EF \
1214 || TARGET_MIPS5900 \
1215 || mips_isa_rev >= 1) \
1216 && !TARGET_MIPS16)
1217
1218 /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */
1219 #define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6)
1220
1221 /* ISA has data indexed prefetch instructions. This controls use of
1222 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1223 (prefx is a cop1x instruction, so can only be used if FP is
1224 enabled.) */
1225 #define ISA_HAS_PREFETCHX (ISA_HAS_FP4 \
1226 || TARGET_LOONGSON_EXT \
1227 || TARGET_LOONGSON_EXT2)
1228
1229 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1230 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1231 also requires TARGET_DOUBLE_FLOAT. */
1232 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1233
1234 /* ISA includes the MIPS32r2 seb and seh instructions. */
1235 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1236
1237 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1238 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
1239
1240 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1241 #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \
1242 && mips_isa_rev >= 2)
1243
1244 /* ISA has lwxs instruction (load w/scaled index address. */
1245 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1246 && !TARGET_MIPS16)
1247
1248 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1249 #define ISA_HAS_LBX (TARGET_OCTEON2)
1250 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1251 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1252 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1253 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1254 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1255 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1256 && TARGET_64BIT)
1257
1258 /* The DSP ASE is available. */
1259 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1260
1261 /* Revision 2 of the DSP ASE is available. */
1262 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1263
1264 /* The MSA ASE is available. */
1265 #define ISA_HAS_MSA (TARGET_MSA && !TARGET_MIPS16)
1266
1267 /* True if the result of a load is not available to the next instruction.
1268 A nop will then be needed between instructions like "lw $4,..."
1269 and "addiu $4,$4,1". */
1270 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1271 && !TARGET_MIPS3900 \
1272 && !TARGET_MIPS5900 \
1273 && !TARGET_MIPS16 \
1274 && !TARGET_MICROMIPS)
1275
1276 /* Likewise mtc1 and mfc1. */
1277 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1278 && !TARGET_MIPS5900 \
1279 && !TARGET_LOONGSON_2EF)
1280
1281 /* Likewise floating-point comparisons. */
1282 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1283 && !TARGET_MIPS5900 \
1284 && !TARGET_LOONGSON_2EF)
1285
1286 /* True if mflo and mfhi can be immediately followed by instructions
1287 which write to the HI and LO registers.
1288
1289 According to MIPS specifications, MIPS ISAs I, II, and III need
1290 (at least) two instructions between the reads of HI/LO and
1291 instructions which write them, and later ISAs do not. Contradicting
1292 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1293 the UM for the NEC Vr5000) document needing the instructions between
1294 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1295 MIPS64 and later ISAs to have the interlocks, plus any specific
1296 earlier-ISA CPUs for which CPU documentation declares that the
1297 instructions are really interlocked. */
1298 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1299 || TARGET_MIPS5500 \
1300 || TARGET_MIPS5900 \
1301 || TARGET_LOONGSON_2EF)
1302
1303 /* ISA includes synci, jr.hb and jalr.hb. */
1304 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1305
1306 /* ISA includes sync. */
1307 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1308 #define GENERATE_SYNC \
1309 (target_flags_explicit & MASK_LLSC \
1310 ? TARGET_LLSC && !TARGET_MIPS16 \
1311 : ISA_HAS_SYNC)
1312
1313 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1314 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1315 instructions. */
1316 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1317 #define GENERATE_LL_SC \
1318 (target_flags_explicit & MASK_LLSC \
1319 ? TARGET_LLSC && !TARGET_MIPS16 \
1320 : ISA_HAS_LL_SC)
1321
1322 #define ISA_HAS_SWAP (TARGET_XLP)
1323 #define ISA_HAS_LDADD (TARGET_XLP)
1324
1325 /* ISA includes the baddu instruction. */
1326 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1327
1328 /* ISA includes the bbit* instructions. */
1329 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1330
1331 /* ISA includes the cins instruction. */
1332 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1333
1334 /* ISA includes the exts instruction. */
1335 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1336
1337 /* ISA includes the seq and sne instructions. */
1338 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1339
1340 /* ISA includes the pop instruction. */
1341 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1342
1343 /* The CACHE instruction is available in non-MIPS16 code. */
1344 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1345
1346 /* The CACHE instruction is available. */
1347 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1348 \f
1349 /* Tell collect what flags to pass to nm. */
1350 #ifndef NM_FLAGS
1351 #define NM_FLAGS "-Bn"
1352 #endif
1353
1354 \f
1355 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1356 the assembler. It may be overridden by subtargets.
1357
1358 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1359 COFF debugging info. */
1360
1361 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1362 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1363 %{g} %{g0} %{g1} %{g2} %{g3} \
1364 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1365 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1366 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3}"
1367 #endif
1368
1369 /* FP_ASM_SPEC represents the floating-point options that must be passed
1370 to the assembler when FPXX support exists. Prior to that point the
1371 assembler could accept the options but were not required for
1372 correctness. We only add the options when absolutely necessary
1373 because passing -msoft-float to the assembler will cause it to reject
1374 all hard-float instructions which may require some user code to be
1375 updated. */
1376
1377 #ifdef HAVE_AS_DOT_MODULE
1378 #define FP_ASM_SPEC "\
1379 %{mhard-float} %{msoft-float} \
1380 %{msingle-float} %{mdouble-float}"
1381 #else
1382 #define FP_ASM_SPEC
1383 #endif
1384
1385 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1386 overridden by subtargets. */
1387
1388 #ifndef SUBTARGET_ASM_SPEC
1389 #define SUBTARGET_ASM_SPEC ""
1390 #endif
1391
1392 #undef ASM_SPEC
1393 #define ASM_SPEC "\
1394 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1395 %{mips32*} %{mips64*} \
1396 %{mips16} %{mno-mips16:-no-mips16} \
1397 %{mmicromips} %{mno-micromips} \
1398 %{mips3d} %{mno-mips3d:-no-mips3d} \
1399 %{mdmx} %{mno-mdmx:-no-mdmx} \
1400 %{mdsp} %{mno-dsp} \
1401 %{mdspr2} %{mno-dspr2} \
1402 %{mmcu} %{mno-mcu} \
1403 %{meva} %{mno-eva} \
1404 %{mvirt} %{mno-virt} \
1405 %{mxpa} %{mno-xpa} \
1406 %{mcrc} %{mno-crc} \
1407 %{mginv} %{mno-ginv} \
1408 %{mmsa} %{mno-msa} \
1409 %{mloongson-mmi} %{mno-loongson-mmi} \
1410 %{mloongson-ext} %{mno-loongson-ext} \
1411 %{mloongson-ext2} %{mno-loongson-ext2} \
1412 %{msmartmips} %{mno-smartmips} \
1413 %{mmt} %{mno-mt} \
1414 %{mfix-r5900} %{mno-fix-r5900} \
1415 %{mfix-rm7000} %{mno-fix-rm7000} \
1416 %{mfix-vr4120} %{mfix-vr4130} \
1417 %{mfix-24k} \
1418 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1419 %(subtarget_asm_debugging_spec) \
1420 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1421 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1422 %{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \
1423 %{modd-spreg} %{mno-odd-spreg} \
1424 %{mshared} %{mno-shared} \
1425 %{msym32} %{mno-sym32} \
1426 %{mtune=*}" \
1427 FP_ASM_SPEC "\
1428 %(subtarget_asm_spec)"
1429
1430 /* Extra switches sometimes passed to the linker. */
1431
1432 #ifndef LINK_SPEC
1433 #define LINK_SPEC "\
1434 %(endian_spec) \
1435 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1436 %{shared}"
1437 #endif /* LINK_SPEC defined */
1438
1439
1440 /* Specs for the compiler proper */
1441
1442 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1443 overridden by subtargets. */
1444 #ifndef SUBTARGET_CC1_SPEC
1445 #define SUBTARGET_CC1_SPEC ""
1446 #endif
1447
1448 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1449
1450 #undef CC1_SPEC
1451 #define CC1_SPEC "\
1452 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1453 %(subtarget_cc1_spec)"
1454
1455 /* Preprocessor specs. */
1456
1457 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1458 overridden by subtargets. */
1459 #ifndef SUBTARGET_CPP_SPEC
1460 #define SUBTARGET_CPP_SPEC ""
1461 #endif
1462
1463 #define CPP_SPEC "%(subtarget_cpp_spec)"
1464
1465 /* This macro defines names of additional specifications to put in the specs
1466 that can be used in various specifications like CC1_SPEC. Its definition
1467 is an initializer with a subgrouping for each command option.
1468
1469 Each subgrouping contains a string constant, that defines the
1470 specification name, and a string constant that used by the GCC driver
1471 program.
1472
1473 Do not define this macro if it does not need to do anything. */
1474
1475 #define EXTRA_SPECS \
1476 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1477 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1478 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1479 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1480 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1481 { "endian_spec", ENDIAN_SPEC }, \
1482 SUBTARGET_EXTRA_SPECS
1483
1484 #ifndef SUBTARGET_EXTRA_SPECS
1485 #define SUBTARGET_EXTRA_SPECS
1486 #endif
1487 \f
1488 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1489 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1490
1491 #ifndef PREFERRED_DEBUGGING_TYPE
1492 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1493 #endif
1494
1495 /* The size of DWARF addresses should be the same as the size of symbols
1496 in the target file format. They shouldn't depend on things like -msym32,
1497 because many DWARF consumers do not allow the mixture of address sizes
1498 that one would then get from linking -msym32 code with -msym64 code.
1499
1500 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1501 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1502 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1503
1504 /* By default, turn on GDB extensions. */
1505 #define DEFAULT_GDB_EXTENSIONS 1
1506
1507 /* Registers may have a prefix which can be ignored when matching
1508 user asm and register definitions. */
1509 #ifndef REGISTER_PREFIX
1510 #define REGISTER_PREFIX "$"
1511 #endif
1512
1513 /* Local compiler-generated symbols must have a prefix that the assembler
1514 understands. By default, this is $, although some targets (e.g.,
1515 NetBSD-ELF) need to override this. */
1516
1517 #ifndef LOCAL_LABEL_PREFIX
1518 #define LOCAL_LABEL_PREFIX "$"
1519 #endif
1520
1521 /* By default on the mips, external symbols do not have an underscore
1522 prepended, but some targets (e.g., NetBSD) require this. */
1523
1524 #ifndef USER_LABEL_PREFIX
1525 #define USER_LABEL_PREFIX ""
1526 #endif
1527
1528 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1529 since the length can run past this up to a continuation point. */
1530 #undef DBX_CONTIN_LENGTH
1531 #define DBX_CONTIN_LENGTH 1500
1532
1533 /* How to renumber registers for dbx and gdb. */
1534 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1535
1536 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1537 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1538
1539 /* The DWARF 2 CFA column which tracks the return address. */
1540 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1541
1542 /* Before the prologue, RA lives in r31. */
1543 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
1544
1545 /* Describe how we implement __builtin_eh_return. */
1546 #define EH_RETURN_DATA_REGNO(N) \
1547 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1548
1549 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1550
1551 #define EH_USES(N) mips_eh_uses (N)
1552
1553 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1554 The default for this in 64-bit mode is 8, which causes problems with
1555 SFmode register saves. */
1556 #define DWARF_CIE_DATA_ALIGNMENT -4
1557
1558 /* Correct the offset of automatic variables and arguments. Note that
1559 the MIPS debug format wants all automatic variables and arguments
1560 to be in terms of the virtual frame pointer (stack pointer before
1561 any adjustment in the function), while the MIPS 3.0 linker wants
1562 the frame pointer to be the stack pointer after the initial
1563 adjustment. */
1564
1565 #define DEBUGGER_AUTO_OFFSET(X) \
1566 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1567 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1568 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1569 \f
1570 /* Target machine storage layout */
1571
1572 #define BITS_BIG_ENDIAN 0
1573 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1574 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1575
1576 #define MAX_BITS_PER_WORD 64
1577
1578 /* Width of a word, in units (bytes). */
1579 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1580 #ifndef IN_LIBGCC2
1581 #define MIN_UNITS_PER_WORD 4
1582 #endif
1583
1584 /* Width of a MSA vector register in bytes. */
1585 #define UNITS_PER_MSA_REG 16
1586 /* Width of a MSA vector register in bits. */
1587 #define BITS_PER_MSA_REG (UNITS_PER_MSA_REG * BITS_PER_UNIT)
1588
1589 /* For MIPS, width of a floating point register. */
1590 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1591
1592 /* The number of consecutive floating-point registers needed to store the
1593 largest format supported by the FPU. */
1594 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1595
1596 /* The number of consecutive floating-point registers needed to store the
1597 smallest format supported by the FPU. */
1598 #define MIN_FPRS_PER_FMT \
1599 (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT)
1600
1601 /* The largest size of value that can be held in floating-point
1602 registers and moved with a single instruction. */
1603 #define UNITS_PER_HWFPVALUE \
1604 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1605
1606 /* The largest size of value that can be held in floating-point
1607 registers. */
1608 #define UNITS_PER_FPVALUE \
1609 (TARGET_SOFT_FLOAT_ABI ? 0 \
1610 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1611 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1612
1613 /* The number of bytes in a double. */
1614 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1615
1616 /* Set the sizes of the core types. */
1617 #define SHORT_TYPE_SIZE 16
1618 #define INT_TYPE_SIZE 32
1619 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1620 #define LONG_LONG_TYPE_SIZE 64
1621
1622 #define FLOAT_TYPE_SIZE 32
1623 #define DOUBLE_TYPE_SIZE 64
1624 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1625
1626 /* Define the sizes of fixed-point types. */
1627 #define SHORT_FRACT_TYPE_SIZE 8
1628 #define FRACT_TYPE_SIZE 16
1629 #define LONG_FRACT_TYPE_SIZE 32
1630 #define LONG_LONG_FRACT_TYPE_SIZE 64
1631
1632 #define SHORT_ACCUM_TYPE_SIZE 16
1633 #define ACCUM_TYPE_SIZE 32
1634 #define LONG_ACCUM_TYPE_SIZE 64
1635 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1636 doesn't support 128-bit integers for MIPS32 currently. */
1637 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1638
1639 /* long double is not a fixed mode, but the idea is that, if we
1640 support long double, we also want a 128-bit integer type. */
1641 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1642
1643 /* Width in bits of a pointer. */
1644 #ifndef POINTER_SIZE
1645 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1646 #endif
1647
1648 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1649 #define PARM_BOUNDARY BITS_PER_WORD
1650
1651 /* Allocation boundary (in *bits*) for the code of a function. */
1652 #define FUNCTION_BOUNDARY 32
1653
1654 /* Alignment of field after `int : 0' in a structure. */
1655 #define EMPTY_FIELD_BOUNDARY 32
1656
1657 /* Every structure's size must be a multiple of this. */
1658 /* 8 is observed right on a DECstation and on riscos 4.02. */
1659 #define STRUCTURE_SIZE_BOUNDARY 8
1660
1661 /* There is no point aligning anything to a rounder boundary than
1662 LONG_DOUBLE_TYPE_SIZE, unless under MSA the bigggest alignment is
1663 BITS_PER_MSA_REG. */
1664 #define BIGGEST_ALIGNMENT \
1665 (ISA_HAS_MSA ? BITS_PER_MSA_REG : LONG_DOUBLE_TYPE_SIZE)
1666
1667 /* All accesses must be aligned. */
1668 #define STRICT_ALIGNMENT 1
1669
1670 /* Define this if you wish to imitate the way many other C compilers
1671 handle alignment of bitfields and the structures that contain
1672 them.
1673
1674 The behavior is that the type written for a bit-field (`int',
1675 `short', or other integer type) imposes an alignment for the
1676 entire structure, as if the structure really did contain an
1677 ordinary field of that type. In addition, the bit-field is placed
1678 within the structure so that it would fit within such a field,
1679 not crossing a boundary for it.
1680
1681 Thus, on most machines, a bit-field whose type is written as `int'
1682 would not cross a four-byte boundary, and would force four-byte
1683 alignment for the whole structure. (The alignment used may not
1684 be four bytes; it is controlled by the other alignment
1685 parameters.)
1686
1687 If the macro is defined, its definition should be a C expression;
1688 a nonzero value for the expression enables this behavior. */
1689
1690 #define PCC_BITFIELD_TYPE_MATTERS 1
1691
1692 /* If defined, a C expression to compute the alignment for a static
1693 variable. TYPE is the data type, and ALIGN is the alignment that
1694 the object would ordinarily have. The value of this macro is used
1695 instead of that alignment to align the object.
1696
1697 If this macro is not defined, then ALIGN is used.
1698
1699 One use of this macro is to increase alignment of medium-size
1700 data to make it all fit in fewer cache lines. Another is to
1701 cause character arrays to be word-aligned so that `strcpy' calls
1702 that copy constants to character arrays can be done inline. */
1703
1704 #undef DATA_ALIGNMENT
1705 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1706 ((((ALIGN) < BITS_PER_WORD) \
1707 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1708 || TREE_CODE (TYPE) == UNION_TYPE \
1709 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1710
1711 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1712 character arrays to be word-aligned so that `strcpy' calls that copy
1713 constants to character arrays can be done inline, and 'strcmp' can be
1714 optimised to use word loads. */
1715 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1716 DATA_ALIGNMENT (TYPE, ALIGN)
1717
1718 #define PAD_VARARGS_DOWN \
1719 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1720
1721 /* Define if operations between registers always perform the operation
1722 on the full register even if a narrower mode is specified. */
1723 #define WORD_REGISTER_OPERATIONS 1
1724
1725 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1726 moves. All other references are zero extended. */
1727 #define LOAD_EXTEND_OP(MODE) \
1728 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1729 ? SIGN_EXTEND : ZERO_EXTEND)
1730
1731 /* Define this macro if it is advisable to hold scalars in registers
1732 in a wider mode than that declared by the program. In such cases,
1733 the value is constrained to be within the bounds of the declared
1734 type, but kept valid in the wider mode. The signedness of the
1735 extension may differ from that of the type. */
1736
1737 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1738 if (GET_MODE_CLASS (MODE) == MODE_INT \
1739 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1740 { \
1741 if ((MODE) == SImode) \
1742 (UNSIGNEDP) = 0; \
1743 (MODE) = Pmode; \
1744 }
1745
1746 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1747 Extensions of pointers to word_mode must be signed. */
1748 #define POINTERS_EXTEND_UNSIGNED false
1749
1750 /* Define if loading short immediate values into registers sign extends. */
1751 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1752
1753 /* The [d]clz instructions have the natural values at 0. */
1754
1755 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1756 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1757 \f
1758 /* Standard register usage. */
1759
1760 /* Number of hardware registers. We have:
1761
1762 - 32 integer registers
1763 - 32 floating point registers
1764 - 8 condition code registers
1765 - 2 accumulator registers (hi and lo)
1766 - 32 registers each for coprocessors 0, 2 and 3
1767 - 4 fake registers:
1768 - ARG_POINTER_REGNUM
1769 - FRAME_POINTER_REGNUM
1770 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1771 - CPRESTORE_SLOT_REGNUM
1772 - 2 dummy entries that were used at various times in the past.
1773 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1774 - 6 DSP control registers */
1775
1776 #define FIRST_PSEUDO_REGISTER 188
1777
1778 /* By default, fix the kernel registers ($26 and $27), the global
1779 pointer ($28) and the stack pointer ($29). This can change
1780 depending on the command-line options.
1781
1782 Regarding coprocessor registers: without evidence to the contrary,
1783 it's best to assume that each coprocessor register has a unique
1784 use. This can be overridden, in, e.g., mips_option_override or
1785 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1786 inappropriate for a particular target. */
1787
1788 #define FIXED_REGISTERS \
1789 { \
1790 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1791 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1792 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1793 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1794 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1795 /* COP0 registers */ \
1796 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1797 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1798 /* COP2 registers */ \
1799 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1800 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1801 /* COP3 registers */ \
1802 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1803 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1804 /* 6 DSP accumulator registers & 6 control registers */ \
1805 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1806 }
1807
1808
1809 /* Set up this array for o32 by default.
1810
1811 Note that we don't mark $31 as a call-clobbered register. The idea is
1812 that it's really the call instructions themselves which clobber $31.
1813 We don't care what the called function does with it afterwards.
1814
1815 This approach makes it easier to implement sibcalls. Unlike normal
1816 calls, sibcalls don't clobber $31, so the register reaches the
1817 called function in tact. EPILOGUE_USES says that $31 is useful
1818 to the called function. */
1819
1820 #define CALL_REALLY_USED_REGISTERS \
1821 { /* General registers. */ \
1822 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1823 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1824 /* Floating-point registers. */ \
1825 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1826 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1827 /* Others. */ \
1828 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1829 /* COP0 registers */ \
1830 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1831 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1832 /* COP2 registers */ \
1833 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1834 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1835 /* COP3 registers */ \
1836 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1837 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1838 /* 6 DSP accumulator registers & 6 control registers */ \
1839 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1840 }
1841
1842 /* Internal macros to classify a register number as to whether it's a
1843 general purpose register, a floating point register, a
1844 multiply/divide register, or a status register. */
1845
1846 #define GP_REG_FIRST 0
1847 #define GP_REG_LAST 31
1848 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1849 #define GP_DBX_FIRST 0
1850 #define K0_REG_NUM (GP_REG_FIRST + 26)
1851 #define K1_REG_NUM (GP_REG_FIRST + 27)
1852 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1853
1854 #define FP_REG_FIRST 32
1855 #define FP_REG_LAST 63
1856 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1857 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1858
1859 #define MD_REG_FIRST 64
1860 #define MD_REG_LAST 65
1861 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1862 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1863
1864 #define MSA_REG_FIRST FP_REG_FIRST
1865 #define MSA_REG_LAST FP_REG_LAST
1866 #define MSA_REG_NUM FP_REG_NUM
1867
1868 /* The DWARF 2 CFA column which tracks the return address from a
1869 signal handler context. This means that to maintain backwards
1870 compatibility, no hard register can be assigned this column if it
1871 would need to be handled by the DWARF unwinder. */
1872 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1873
1874 #define ST_REG_FIRST 67
1875 #define ST_REG_LAST 74
1876 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1877
1878
1879 /* FIXME: renumber. */
1880 #define COP0_REG_FIRST 80
1881 #define COP0_REG_LAST 111
1882 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1883
1884 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1885 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1886 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1887
1888 #define COP2_REG_FIRST 112
1889 #define COP2_REG_LAST 143
1890 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1891
1892 #define COP3_REG_FIRST 144
1893 #define COP3_REG_LAST 175
1894 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1895
1896 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1897 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1898 #define ALL_COP_REG_LAST COP3_REG_LAST
1899 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1900
1901 #define DSP_ACC_REG_FIRST 176
1902 #define DSP_ACC_REG_LAST 181
1903 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1904
1905 #define AT_REGNUM (GP_REG_FIRST + 1)
1906 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1907 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1908
1909 /* A few bitfield locations for the coprocessor registers. */
1910 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1911 the cause register for the EIC interrupt mode. */
1912 #define CAUSE_IPL 10
1913 /* COP1 Enable is at bit 29 of the status register. */
1914 #define SR_COP1 29
1915 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1916 #define SR_IPL 10
1917 /* Interrupt masks start with IM0 at bit 8 to IM7 at bit 15 of the status
1918 register. */
1919 #define SR_IM0 8
1920 /* Exception Level is at bit 1 of the status register. */
1921 #define SR_EXL 1
1922 /* Interrupt Enable is at bit 0 of the status register. */
1923 #define SR_IE 0
1924
1925 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1926 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1927 should be used instead. */
1928 #define FPSW_REGNUM ST_REG_FIRST
1929
1930 #define GP_REG_P(REGNO) \
1931 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1932 #define M16_REG_P(REGNO) \
1933 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1934 #define M16STORE_REG_P(REGNO) \
1935 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1936 #define FP_REG_P(REGNO) \
1937 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1938 #define MD_REG_P(REGNO) \
1939 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1940 #define ST_REG_P(REGNO) \
1941 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1942 #define COP0_REG_P(REGNO) \
1943 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1944 #define COP2_REG_P(REGNO) \
1945 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1946 #define COP3_REG_P(REGNO) \
1947 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1948 #define ALL_COP_REG_P(REGNO) \
1949 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1950 /* Test if REGNO is one of the 6 new DSP accumulators. */
1951 #define DSP_ACC_REG_P(REGNO) \
1952 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1953 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1954 #define ACC_REG_P(REGNO) \
1955 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1956 #define MSA_REG_P(REGNO) \
1957 ((unsigned int) ((int) (REGNO) - MSA_REG_FIRST) < MSA_REG_NUM)
1958
1959 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1960 #define MSA_REG_RTX_P(X) (REG_P (X) && MSA_REG_P (REGNO (X)))
1961
1962 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1963 to initialize the mips16 gp pseudo register. */
1964 #define CONST_GP_P(X) \
1965 (GET_CODE (X) == CONST \
1966 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1967 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1968
1969 /* Return coprocessor number from register number. */
1970
1971 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1972 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1973 : COP3_REG_P (REGNO) ? '3' : '?')
1974
1975
1976 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1977 mips_hard_regno_rename_ok (OLD_REG, NEW_REG)
1978
1979 /* Select a register mode required for caller save of hard regno REGNO. */
1980 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1981 mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE)
1982
1983 /* Register to use for pushing function arguments. */
1984 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1985
1986 /* These two registers don't really exist: they get eliminated to either
1987 the stack or hard frame pointer. */
1988 #define ARG_POINTER_REGNUM 77
1989 #define FRAME_POINTER_REGNUM 78
1990
1991 /* $30 is not available on the mips16, so we use $17 as the frame
1992 pointer. */
1993 #define HARD_FRAME_POINTER_REGNUM \
1994 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1995
1996 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1997 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1998
1999 /* Register in which static-chain is passed to a function. */
2000 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
2001
2002 /* Registers used as temporaries in prologue/epilogue code:
2003
2004 - If a MIPS16 PIC function needs access to _gp, it first loads
2005 the value into MIPS16_PIC_TEMP and then copies it to $gp.
2006
2007 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
2008 register. The register must not conflict with MIPS16_PIC_TEMP.
2009
2010 - If we aren't generating MIPS16 code, the prologue can also use
2011 MIPS_PROLOGUE_TEMP2 as a general temporary register.
2012
2013 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
2014 register.
2015
2016 If we're generating MIPS16 code, these registers must come from the
2017 core set of 8. The prologue registers mustn't conflict with any
2018 incoming arguments, the static chain pointer, or the frame pointer.
2019 The epilogue temporary mustn't conflict with the return registers,
2020 the PIC call register ($25), the frame pointer, the EH stack adjustment,
2021 or the EH data registers.
2022
2023 If we're generating interrupt handlers, we use K0 as a temporary register
2024 in prologue/epilogue code. */
2025
2026 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
2027 #define MIPS_PROLOGUE_TEMP_REGNUM \
2028 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
2029 #define MIPS_PROLOGUE_TEMP2_REGNUM \
2030 (TARGET_MIPS16 \
2031 ? (gcc_unreachable (), INVALID_REGNUM) \
2032 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
2033 #define MIPS_EPILOGUE_TEMP_REGNUM \
2034 (cfun->machine->interrupt_handler_p \
2035 ? K0_REG_NUM \
2036 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
2037
2038 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
2039 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
2040 #define MIPS_PROLOGUE_TEMP2(MODE) \
2041 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
2042 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
2043
2044 /* Define this macro if it is as good or better to call a constant
2045 function address than to call an address kept in a register. */
2046 #define NO_FUNCTION_CSE 1
2047
2048 /* The ABI-defined global pointer. Sometimes we use a different
2049 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
2050 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
2051
2052 /* We normally use $28 as the global pointer. However, when generating
2053 n32/64 PIC, it is better for leaf functions to use a call-clobbered
2054 register instead. They can then avoid saving and restoring $28
2055 and perhaps avoid using a frame at all.
2056
2057 When a leaf function uses something other than $28, mips_expand_prologue
2058 will modify pic_offset_table_rtx in place. Take the register number
2059 from there after reload. */
2060 #define PIC_OFFSET_TABLE_REGNUM \
2061 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
2062 \f
2063 /* Define the classes of registers for register constraints in the
2064 machine description. Also define ranges of constants.
2065
2066 One of the classes must always be named ALL_REGS and include all hard regs.
2067 If there is more than one class, another class must be named NO_REGS
2068 and contain no registers.
2069
2070 The name GENERAL_REGS must be the name of a class (or an alias for
2071 another name such as ALL_REGS). This is the class of registers
2072 that is allowed by "g" or "r" in a register constraint.
2073 Also, registers outside this class are allocated only when
2074 instructions express preferences for them.
2075
2076 The classes must be numbered in nondecreasing order; that is,
2077 a larger-numbered class must never be contained completely
2078 in a smaller-numbered class.
2079
2080 For any two classes, it is very desirable that there be another
2081 class that represents their union. */
2082
2083 enum reg_class
2084 {
2085 NO_REGS, /* no registers in set */
2086 M16_STORE_REGS, /* microMIPS store registers */
2087 M16_REGS, /* mips16 directly accessible registers */
2088 M16_SP_REGS, /* mips16 + $sp */
2089 T_REG, /* mips16 T register ($24) */
2090 M16_T_REGS, /* mips16 registers plus T register */
2091 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
2092 V1_REG, /* Register $v1 ($3) used for TLS access. */
2093 SPILL_REGS, /* All but $sp and call preserved regs are in here */
2094 LEA_REGS, /* Every GPR except $25 */
2095 GR_REGS, /* integer registers */
2096 FP_REGS, /* floating point registers */
2097 MD0_REG, /* first multiply/divide register */
2098 MD1_REG, /* second multiply/divide register */
2099 MD_REGS, /* multiply/divide registers (hi/lo) */
2100 COP0_REGS, /* generic coprocessor classes */
2101 COP2_REGS,
2102 COP3_REGS,
2103 ST_REGS, /* status registers (fp status) */
2104 DSP_ACC_REGS, /* DSP accumulator registers */
2105 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
2106 FRAME_REGS, /* $arg and $frame */
2107 GR_AND_MD0_REGS, /* union classes */
2108 GR_AND_MD1_REGS,
2109 GR_AND_MD_REGS,
2110 GR_AND_ACC_REGS,
2111 ALL_REGS, /* all registers */
2112 LIM_REG_CLASSES /* max value + 1 */
2113 };
2114
2115 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2116
2117 #define GENERAL_REGS GR_REGS
2118
2119 /* An initializer containing the names of the register classes as C
2120 string constants. These names are used in writing some of the
2121 debugging dumps. */
2122
2123 #define REG_CLASS_NAMES \
2124 { \
2125 "NO_REGS", \
2126 "M16_STORE_REGS", \
2127 "M16_REGS", \
2128 "M16_SP_REGS", \
2129 "T_REG", \
2130 "M16_T_REGS", \
2131 "PIC_FN_ADDR_REG", \
2132 "V1_REG", \
2133 "SPILL_REGS", \
2134 "LEA_REGS", \
2135 "GR_REGS", \
2136 "FP_REGS", \
2137 "MD0_REG", \
2138 "MD1_REG", \
2139 "MD_REGS", \
2140 /* coprocessor registers */ \
2141 "COP0_REGS", \
2142 "COP2_REGS", \
2143 "COP3_REGS", \
2144 "ST_REGS", \
2145 "DSP_ACC_REGS", \
2146 "ACC_REGS", \
2147 "FRAME_REGS", \
2148 "GR_AND_MD0_REGS", \
2149 "GR_AND_MD1_REGS", \
2150 "GR_AND_MD_REGS", \
2151 "GR_AND_ACC_REGS", \
2152 "ALL_REGS" \
2153 }
2154
2155 /* An initializer containing the contents of the register classes,
2156 as integers which are bit masks. The Nth integer specifies the
2157 contents of class N. The way the integer MASK is interpreted is
2158 that register R is in the class if `MASK & (1 << R)' is 1.
2159
2160 When the machine has more than 32 registers, an integer does not
2161 suffice. Then the integers are replaced by sub-initializers,
2162 braced groupings containing several integers. Each
2163 sub-initializer must be suitable as an initializer for the type
2164 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2165
2166 #define REG_CLASS_CONTENTS \
2167 { \
2168 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
2169 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
2170 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
2171 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \
2172 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
2173 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
2174 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
2175 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
2176 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \
2177 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
2178 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
2179 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
2180 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
2181 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
2182 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
2183 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
2184 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
2185 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
2186 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
2187 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
2188 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
2189 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
2190 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
2191 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
2192 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
2193 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
2194 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
2195 }
2196
2197
2198 /* A C expression whose value is a register class containing hard
2199 register REGNO. In general there is more that one such class;
2200 choose a class which is "minimal", meaning that no smaller class
2201 also contains the register. */
2202
2203 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2204
2205 /* A macro whose definition is the name of the class to which a
2206 valid base register must belong. A base register is one used in
2207 an address which is the register value plus a displacement. */
2208
2209 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS)
2210
2211 /* A macro whose definition is the name of the class to which a
2212 valid index register must belong. An index register is one used
2213 in an address where its value is either multiplied by a scale
2214 factor or added to another register (as well as added to a
2215 displacement). */
2216
2217 #define INDEX_REG_CLASS NO_REGS
2218
2219 /* We generally want to put call-clobbered registers ahead of
2220 call-saved ones. (IRA expects this.) */
2221
2222 #define REG_ALLOC_ORDER \
2223 { /* Accumulator registers. When GPRs and accumulators have equal \
2224 cost, we generally prefer to use accumulators. For example, \
2225 a division of multiplication result is better allocated to LO, \
2226 so that we put the MFLO at the point of use instead of at the \
2227 point of definition. It's also needed if we're to take advantage \
2228 of the extra accumulators available with -mdspr2. In some cases, \
2229 it can also help to reduce register pressure. */ \
2230 64, 65,176,177,178,179,180,181, \
2231 /* Call-clobbered GPRs. */ \
2232 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2233 24, 25, 31, \
2234 /* The global pointer. This is call-clobbered for o32 and o64 \
2235 abicalls, call-saved for n32 and n64 abicalls, and a program \
2236 invariant otherwise. Putting it between the call-clobbered \
2237 and call-saved registers should cope with all eventualities. */ \
2238 28, \
2239 /* Call-saved GPRs. */ \
2240 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2241 /* GPRs that can never be exposed to the register allocator. */ \
2242 0, 26, 27, 29, \
2243 /* Call-clobbered FPRs. */ \
2244 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2245 48, 49, 50, 51, \
2246 /* FPRs that are usually call-saved. The odd ones are actually \
2247 call-clobbered for n32, but listing them ahead of the even \
2248 registers might encourage the register allocator to fragment \
2249 the available FPR pairs. We need paired FPRs to store long \
2250 doubles, so it isn't clear that using a different order \
2251 for n32 would be a win. */ \
2252 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2253 /* None of the remaining classes have defined call-saved \
2254 registers. */ \
2255 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2256 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2257 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2258 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2259 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2260 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2261 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2262 182,183,184,185,186,187 \
2263 }
2264
2265 /* True if VALUE is an unsigned 6-bit number. */
2266
2267 #define UIMM6_OPERAND(VALUE) \
2268 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2269
2270 /* True if VALUE is a signed 10-bit number. */
2271
2272 #define IMM10_OPERAND(VALUE) \
2273 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2274
2275 /* True if VALUE is a signed 16-bit number. */
2276
2277 #define SMALL_OPERAND(VALUE) \
2278 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2279
2280 /* True if VALUE is an unsigned 16-bit number. */
2281
2282 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2283 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2284
2285 /* True if VALUE can be loaded into a register using LUI. */
2286
2287 #define LUI_OPERAND(VALUE) \
2288 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2289 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2290
2291 /* Return a value X with the low 16 bits clear, and such that
2292 VALUE - X is a signed 16-bit value. */
2293
2294 #define CONST_HIGH_PART(VALUE) \
2295 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2296
2297 #define CONST_LOW_PART(VALUE) \
2298 ((VALUE) - CONST_HIGH_PART (VALUE))
2299
2300 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2301 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2302 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2303 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2304 #define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255))
2305
2306 /* The HI and LO registers can only be reloaded via the general
2307 registers. Condition code registers can only be loaded to the
2308 general registers, and from the floating point registers. */
2309
2310 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2311 mips_secondary_reload_class (CLASS, MODE, X, true)
2312 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2313 mips_secondary_reload_class (CLASS, MODE, X, false)
2314
2315 /* Return the maximum number of consecutive registers
2316 needed to represent mode MODE in a register of class CLASS. */
2317
2318 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2319 \f
2320 /* Stack layout; function entry, exit and calling. */
2321
2322 #define STACK_GROWS_DOWNWARD 1
2323
2324 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
2325 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
2326
2327 /* Size of the area allocated in the frame to save the GP. */
2328
2329 #define MIPS_GP_SAVE_AREA_SIZE \
2330 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2331
2332 #define RETURN_ADDR_RTX mips_return_addr
2333
2334 /* Mask off the MIPS16 ISA bit in unwind addresses.
2335
2336 The reason for this is a little subtle. When unwinding a call,
2337 we are given the call's return address, which on most targets
2338 is the address of the following instruction. However, what we
2339 actually want to find is the EH region for the call itself.
2340 The target-independent unwind code therefore searches for "RA - 1".
2341
2342 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2343 RA - 1 is therefore the real (even-valued) start of the return
2344 instruction. EH region labels are usually odd-valued MIPS16 symbols
2345 too, so a search for an even address within a MIPS16 region would
2346 usually work.
2347
2348 However, there is an exception. If the end of an EH region is also
2349 the end of a function, the end label is allowed to be even. This is
2350 necessary because a following non-MIPS16 function may also need EH
2351 information for its first instruction.
2352
2353 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2354 non-ISA-encoded address. This probably isn't ideal, but it is
2355 the traditional (legacy) behavior. It is therefore only safe
2356 to search MIPS EH regions for an _odd-valued_ address.
2357
2358 Masking off the ISA bit means that the target-independent code
2359 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2360 #define MASK_RETURN_ADDR GEN_INT (-2)
2361
2362
2363 /* Similarly, don't use the least-significant bit to tell pointers to
2364 code from vtable index. */
2365
2366 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2367
2368 /* The eliminations to $17 are only used for mips16 code. See the
2369 definition of HARD_FRAME_POINTER_REGNUM. */
2370
2371 #define ELIMINABLE_REGS \
2372 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2373 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2374 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2375 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2376 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2377 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2378
2379 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2380 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2381
2382 /* Allocate stack space for arguments at the beginning of each function. */
2383 #define ACCUMULATE_OUTGOING_ARGS 1
2384
2385 /* The argument pointer always points to the first argument. */
2386 #define FIRST_PARM_OFFSET(FNDECL) 0
2387
2388 /* o32 and o64 reserve stack space for all argument registers. */
2389 #define REG_PARM_STACK_SPACE(FNDECL) \
2390 (TARGET_OLDABI \
2391 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2392 : 0)
2393
2394 /* Define this if it is the responsibility of the caller to
2395 allocate the area reserved for arguments passed in registers.
2396 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2397 of this macro is to determine whether the space is included in
2398 `crtl->outgoing_args_size'. */
2399 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2400
2401 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2402 \f
2403 /* Symbolic macros for the registers used to return integer and floating
2404 point values. */
2405
2406 #define GP_RETURN (GP_REG_FIRST + 2)
2407 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2408
2409 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2410
2411 /* Symbolic macros for the first/last argument registers. */
2412
2413 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2414 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2415 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2416 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2417
2418 /* True if MODE is vector and supported in a MSA vector register. */
2419 #define MSA_SUPPORTED_MODE_P(MODE) \
2420 (ISA_HAS_MSA \
2421 && GET_MODE_SIZE (MODE) == UNITS_PER_MSA_REG \
2422 && (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \
2423 || GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT))
2424
2425 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2426 are used for returning complex double values in soft-float code, so $6 is the
2427 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2428 $gp itself as the temporary. */
2429 #define POST_CALL_TMP_REG \
2430 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2431
2432 /* 1 if N is a possible register number for function argument passing.
2433 We have no FP argument registers when soft-float. Special handling
2434 is required for O32 where only even numbered registers are used for
2435 O32-FPXX and O32-FP64. */
2436
2437 #define FUNCTION_ARG_REGNO_P(N) \
2438 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2439 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2440 && (mips_abi != ABI_32 \
2441 || TARGET_FLOAT32 \
2442 || ((N) % 2 == 0)))) \
2443 && !fixed_regs[N])
2444 \f
2445 /* This structure has to cope with two different argument allocation
2446 schemes. Most MIPS ABIs view the arguments as a structure, of which
2447 the first N words go in registers and the rest go on the stack. If I
2448 < N, the Ith word might go in Ith integer argument register or in a
2449 floating-point register. For these ABIs, we only need to remember
2450 the offset of the current argument into the structure.
2451
2452 The EABI instead allocates the integer and floating-point arguments
2453 separately. The first N words of FP arguments go in FP registers,
2454 the rest go on the stack. Likewise, the first N words of the other
2455 arguments go in integer registers, and the rest go on the stack. We
2456 need to maintain three counts: the number of integer registers used,
2457 the number of floating-point registers used, and the number of words
2458 passed on the stack.
2459
2460 We could keep separate information for the two ABIs (a word count for
2461 the standard ABIs, and three separate counts for the EABI). But it
2462 seems simpler to view the standard ABIs as forms of EABI that do not
2463 allocate floating-point registers.
2464
2465 So for the standard ABIs, the first N words are allocated to integer
2466 registers, and mips_function_arg decides on an argument-by-argument
2467 basis whether that argument should really go in an integer register,
2468 or in a floating-point one. */
2469
2470 typedef struct mips_args {
2471 /* Always true for varargs functions. Otherwise true if at least
2472 one argument has been passed in an integer register. */
2473 int gp_reg_found;
2474
2475 /* The number of arguments seen so far. */
2476 unsigned int arg_number;
2477
2478 /* The number of integer registers used so far. For all ABIs except
2479 EABI, this is the number of words that have been added to the
2480 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2481 unsigned int num_gprs;
2482
2483 /* For EABI, the number of floating-point registers used so far. */
2484 unsigned int num_fprs;
2485
2486 /* The number of words passed on the stack. */
2487 unsigned int stack_words;
2488
2489 /* On the mips16, we need to keep track of which floating point
2490 arguments were passed in general registers, but would have been
2491 passed in the FP regs if this were a 32-bit function, so that we
2492 can move them to the FP regs if we wind up calling a 32-bit
2493 function. We record this information in fp_code, encoded in base
2494 four. A zero digit means no floating point argument, a one digit
2495 means an SFmode argument, and a two digit means a DFmode argument,
2496 and a three digit is not used. The low order digit is the first
2497 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2498 an SFmode argument. ??? A more sophisticated approach will be
2499 needed if MIPS_ABI != ABI_32. */
2500 int fp_code;
2501
2502 /* True if the function has a prototype. */
2503 int prototype;
2504 } CUMULATIVE_ARGS;
2505
2506 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2507 for a call to a function whose data type is FNTYPE.
2508 For a library call, FNTYPE is 0. */
2509
2510 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2511 mips_init_cumulative_args (&CUM, FNTYPE)
2512
2513 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2514 (mips_pad_reg_upward (MODE, TYPE) ? PAD_UPWARD : PAD_DOWNWARD)
2515
2516 /* True if using EABI and varargs can be passed in floating-point
2517 registers. Under these conditions, we need a more complex form
2518 of va_list, which tracks GPR, FPR and stack arguments separately. */
2519 #define EABI_FLOAT_VARARGS_P \
2520 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2521
2522 \f
2523 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2524
2525 /* Treat LOC as a byte offset from the stack pointer and round it up
2526 to the next fully-aligned offset. */
2527 #define MIPS_STACK_ALIGN(LOC) \
2528 (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8))
2529
2530 \f
2531 /* Output assembler code to FILE to increment profiler label # LABELNO
2532 for profiling a function entry. */
2533
2534 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2535
2536 /* The profiler preserves all interesting registers, including $31. */
2537 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2538
2539 /* No mips port has ever used the profiler counter word, so don't emit it
2540 or the label for it. */
2541
2542 #define NO_PROFILE_COUNTERS 1
2543
2544 /* Define this macro if the code for function profiling should come
2545 before the function prologue. Normally, the profiling code comes
2546 after. */
2547
2548 /* #define PROFILE_BEFORE_PROLOGUE */
2549
2550 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2551 the stack pointer does not matter. The value is tested only in
2552 functions that have frame pointers.
2553 No definition is equivalent to always zero. */
2554
2555 #define EXIT_IGNORE_STACK 1
2556
2557 \f
2558 /* Trampolines are a block of code followed by two pointers. */
2559
2560 #define TRAMPOLINE_SIZE \
2561 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2562
2563 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2564 pointers from a single LUI base. */
2565
2566 #define TRAMPOLINE_ALIGNMENT 64
2567
2568 /* mips_trampoline_init calls this library function to flush
2569 program and data caches. */
2570
2571 #ifndef CACHE_FLUSH_FUNC
2572 #define CACHE_FLUSH_FUNC "_flush_cache"
2573 #endif
2574
2575 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2576 /* Flush both caches. We need to flush the data cache in case \
2577 the system has a write-back cache. */ \
2578 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2579 LCT_NORMAL, VOIDmode, ADDR, Pmode, SIZE, Pmode, \
2580 GEN_INT (3), TYPE_MODE (integer_type_node))
2581
2582 \f
2583 /* Addressing modes, and classification of registers for them. */
2584
2585 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2586 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2587 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2588 \f
2589 /* Maximum number of registers that can appear in a valid memory address. */
2590
2591 #define MAX_REGS_PER_ADDRESS 1
2592
2593 /* Check for constness inline but use mips_legitimate_address_p
2594 to check whether a constant really is an address. */
2595
2596 #define CONSTANT_ADDRESS_P(X) \
2597 (CONSTANT_P (X) && memory_address_p (SImode, X))
2598
2599 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2600 'the start of the function that this code is output in'. */
2601
2602 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2603 do { \
2604 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2605 asm_fprintf ((FILE), "%U%s", \
2606 XSTR (XEXP (DECL_RTL (current_function_decl), \
2607 0), 0)); \
2608 else \
2609 asm_fprintf ((FILE), "%U%s", (NAME)); \
2610 } while (0)
2611 \f
2612 /* Flag to mark a function decl symbol that requires a long call. */
2613 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2614 #define SYMBOL_REF_LONG_CALL_P(X) \
2615 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2616
2617 /* This flag marks functions that cannot be lazily bound. */
2618 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2619 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2620 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2621
2622 /* True if we're generating a form of MIPS16 code in which jump tables
2623 are stored in the text section and encoded as 16-bit PC-relative
2624 offsets. This is only possible when general text loads are allowed,
2625 since the table access itself will be an "lh" instruction. If the
2626 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2627 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2628
2629 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2630
2631 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2632
2633 /* Only use short offsets if their range will not overflow. */
2634 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2635 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2636 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2637 : SImode)
2638
2639 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2640
2641 /* Define this as 1 if `char' should by default be signed; else as 0. */
2642 #ifndef DEFAULT_SIGNED_CHAR
2643 #define DEFAULT_SIGNED_CHAR 1
2644 #endif
2645
2646 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2647 we generally don't want to use them for copying arbitrary data.
2648 A single N-word move is usually the same cost as N single-word moves. */
2649 #define MOVE_MAX UNITS_PER_WORD
2650 /* We don't modify it for MSA as it is only used by the classic reload. */
2651 #define MAX_MOVE_MAX 8
2652
2653 /* Define this macro as a C expression which is nonzero if
2654 accessing less than a word of memory (i.e. a `char' or a
2655 `short') is no faster than accessing a word of memory, i.e., if
2656 such access require more than one instruction or if there is no
2657 difference in cost between byte and (aligned) word loads.
2658
2659 On RISC machines, it tends to generate better code to define
2660 this as 1, since it avoids making a QI or HI mode register.
2661
2662 But, generating word accesses for -mips16 is generally bad as shifts
2663 (often extended) would be needed for byte accesses. */
2664 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2665
2666 /* Standard MIPS integer shifts truncate the shift amount to the
2667 width of the shifted operand. However, Loongson MMI shifts
2668 do not truncate the shift amount at all. */
2669 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_MMI)
2670
2671
2672 /* Specify the machine mode that pointers have.
2673 After generation of rtl, the compiler makes no further distinction
2674 between pointers and any other objects of this machine mode. */
2675
2676 #ifndef Pmode
2677 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2678 #endif
2679
2680 /* Give call MEMs SImode since it is the "most permissive" mode
2681 for both 32-bit and 64-bit targets. */
2682
2683 #define FUNCTION_MODE SImode
2684
2685 \f
2686 /* We allocate $fcc registers by hand and can't cope with moves of
2687 CCmode registers to and from pseudos (or memory). */
2688 #define AVOID_CCMODE_COPIES
2689
2690 /* A C expression for the cost of a branch instruction. A value of
2691 1 is the default; other values are interpreted relative to that. */
2692
2693 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2694 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2695
2696 /* The MIPS port has several functions that return an instruction count.
2697 Multiplying the count by this value gives the number of bytes that
2698 the instructions occupy. */
2699 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2700
2701 /* The length of a NOP in bytes. */
2702 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2703
2704 /* If defined, modifies the length assigned to instruction INSN as a
2705 function of the context in which it is used. LENGTH is an lvalue
2706 that contains the initially computed length of the insn and should
2707 be updated with the correct length of the insn. */
2708 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2709 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2710
2711 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2712 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2713 its operands. */
2714 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2715 "%*" OPCODE "%?\t" OPERANDS "%/"
2716
2717 #define MIPS_BRANCH_C(OPCODE, OPERANDS) \
2718 "%*" OPCODE "%:\t" OPERANDS
2719
2720 /* Return an asm string that forces INSN to be treated as an absolute
2721 J or JAL instruction instead of an assembler macro. */
2722 #define MIPS_ABSOLUTE_JUMP(INSN) \
2723 (TARGET_ABICALLS_PIC2 \
2724 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2725 : INSN)
2726
2727 \f
2728 /* Control the assembler format that we output. */
2729
2730 /* Output to assembler file text saying following lines
2731 may contain character constants, extra white space, comments, etc. */
2732
2733 #ifndef ASM_APP_ON
2734 #define ASM_APP_ON " #APP\n"
2735 #endif
2736
2737 /* Output to assembler file text saying following lines
2738 no longer contain unusual constructs. */
2739
2740 #ifndef ASM_APP_OFF
2741 #define ASM_APP_OFF " #NO_APP\n"
2742 #endif
2743
2744 #define REGISTER_NAMES \
2745 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2746 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2747 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2748 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2749 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2750 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2751 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2752 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2753 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2754 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2755 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2756 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2757 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2758 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2759 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2760 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2761 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2762 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2763 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2764 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2765 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2766 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2767 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2768 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2769
2770 /* List the "software" names for each register. Also list the numerical
2771 names for $fp and $sp. */
2772
2773 #define ADDITIONAL_REGISTER_NAMES \
2774 { \
2775 { "$29", 29 + GP_REG_FIRST }, \
2776 { "$30", 30 + GP_REG_FIRST }, \
2777 { "at", 1 + GP_REG_FIRST }, \
2778 { "v0", 2 + GP_REG_FIRST }, \
2779 { "v1", 3 + GP_REG_FIRST }, \
2780 { "a0", 4 + GP_REG_FIRST }, \
2781 { "a1", 5 + GP_REG_FIRST }, \
2782 { "a2", 6 + GP_REG_FIRST }, \
2783 { "a3", 7 + GP_REG_FIRST }, \
2784 { "t0", 8 + GP_REG_FIRST }, \
2785 { "t1", 9 + GP_REG_FIRST }, \
2786 { "t2", 10 + GP_REG_FIRST }, \
2787 { "t3", 11 + GP_REG_FIRST }, \
2788 { "t4", 12 + GP_REG_FIRST }, \
2789 { "t5", 13 + GP_REG_FIRST }, \
2790 { "t6", 14 + GP_REG_FIRST }, \
2791 { "t7", 15 + GP_REG_FIRST }, \
2792 { "s0", 16 + GP_REG_FIRST }, \
2793 { "s1", 17 + GP_REG_FIRST }, \
2794 { "s2", 18 + GP_REG_FIRST }, \
2795 { "s3", 19 + GP_REG_FIRST }, \
2796 { "s4", 20 + GP_REG_FIRST }, \
2797 { "s5", 21 + GP_REG_FIRST }, \
2798 { "s6", 22 + GP_REG_FIRST }, \
2799 { "s7", 23 + GP_REG_FIRST }, \
2800 { "t8", 24 + GP_REG_FIRST }, \
2801 { "t9", 25 + GP_REG_FIRST }, \
2802 { "k0", 26 + GP_REG_FIRST }, \
2803 { "k1", 27 + GP_REG_FIRST }, \
2804 { "gp", 28 + GP_REG_FIRST }, \
2805 { "sp", 29 + GP_REG_FIRST }, \
2806 { "fp", 30 + GP_REG_FIRST }, \
2807 { "ra", 31 + GP_REG_FIRST }, \
2808 { "$w0", 0 + FP_REG_FIRST }, \
2809 { "$w1", 1 + FP_REG_FIRST }, \
2810 { "$w2", 2 + FP_REG_FIRST }, \
2811 { "$w3", 3 + FP_REG_FIRST }, \
2812 { "$w4", 4 + FP_REG_FIRST }, \
2813 { "$w5", 5 + FP_REG_FIRST }, \
2814 { "$w6", 6 + FP_REG_FIRST }, \
2815 { "$w7", 7 + FP_REG_FIRST }, \
2816 { "$w8", 8 + FP_REG_FIRST }, \
2817 { "$w9", 9 + FP_REG_FIRST }, \
2818 { "$w10", 10 + FP_REG_FIRST }, \
2819 { "$w11", 11 + FP_REG_FIRST }, \
2820 { "$w12", 12 + FP_REG_FIRST }, \
2821 { "$w13", 13 + FP_REG_FIRST }, \
2822 { "$w14", 14 + FP_REG_FIRST }, \
2823 { "$w15", 15 + FP_REG_FIRST }, \
2824 { "$w16", 16 + FP_REG_FIRST }, \
2825 { "$w17", 17 + FP_REG_FIRST }, \
2826 { "$w18", 18 + FP_REG_FIRST }, \
2827 { "$w19", 19 + FP_REG_FIRST }, \
2828 { "$w20", 20 + FP_REG_FIRST }, \
2829 { "$w21", 21 + FP_REG_FIRST }, \
2830 { "$w22", 22 + FP_REG_FIRST }, \
2831 { "$w23", 23 + FP_REG_FIRST }, \
2832 { "$w24", 24 + FP_REG_FIRST }, \
2833 { "$w25", 25 + FP_REG_FIRST }, \
2834 { "$w26", 26 + FP_REG_FIRST }, \
2835 { "$w27", 27 + FP_REG_FIRST }, \
2836 { "$w28", 28 + FP_REG_FIRST }, \
2837 { "$w29", 29 + FP_REG_FIRST }, \
2838 { "$w30", 30 + FP_REG_FIRST }, \
2839 { "$w31", 31 + FP_REG_FIRST } \
2840 }
2841
2842 #define DBR_OUTPUT_SEQEND(STREAM) \
2843 do \
2844 { \
2845 /* Undo the effect of '%*'. */ \
2846 mips_pop_asm_switch (&mips_nomacro); \
2847 mips_pop_asm_switch (&mips_noreorder); \
2848 /* Emit a blank line after the delay slot for emphasis. */ \
2849 fputs ("\n", STREAM); \
2850 } \
2851 while (0)
2852
2853 /* The MIPS implementation uses some labels for its own purpose. The
2854 following lists what labels are created, and are all formed by the
2855 pattern $L[a-z].*. The machine independent portion of GCC creates
2856 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2857
2858 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2859 $Lb[0-9]+ Begin blocks for MIPS debug support
2860 $Lc[0-9]+ Label for use in s<xx> operation.
2861 $Le[0-9]+ End blocks for MIPS debug support */
2862
2863 #undef ASM_DECLARE_OBJECT_NAME
2864 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2865 mips_declare_object (STREAM, NAME, "", ":\n")
2866
2867 /* Globalizing directive for a label. */
2868 #define GLOBAL_ASM_OP "\t.globl\t"
2869
2870 /* This says how to define a global common symbol. */
2871
2872 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2873
2874 /* This says how to define a local common symbol (i.e., not visible to
2875 linker). */
2876
2877 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2878 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2879 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2880 #endif
2881
2882 /* This says how to output an external. It would be possible not to
2883 output anything and let undefined symbol become external. However
2884 the assembler uses length information on externals to allocate in
2885 data/sdata bss/sbss, thereby saving exec time. */
2886
2887 #undef ASM_OUTPUT_EXTERNAL
2888 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2889 mips_output_external(STREAM,DECL,NAME)
2890
2891 /* This is how to declare a function name. The actual work of
2892 emitting the label is moved to function_prologue, so that we can
2893 get the line number correctly emitted before the .ent directive,
2894 and after any .file directives. Define as empty so that the function
2895 is not declared before the .ent directive elsewhere. */
2896
2897 #undef ASM_DECLARE_FUNCTION_NAME
2898 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2899
2900 /* This is how to store into the string LABEL
2901 the symbol_ref name of an internal numbered label where
2902 PREFIX is the class of label and NUM is the number within the class.
2903 This is suitable for output with `assemble_name'. */
2904
2905 #undef ASM_GENERATE_INTERNAL_LABEL
2906 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2907 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2908
2909 /* Print debug labels as "foo = ." rather than "foo:" because they should
2910 represent a byte pointer rather than an ISA-encoded address. This is
2911 particularly important for code like:
2912
2913 $LFBxxx = .
2914 .cfi_startproc
2915 ...
2916 .section .gcc_except_table,...
2917 ...
2918 .uleb128 foo-$LFBxxx
2919
2920 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2921 likewise a byte pointer rather than an ISA-encoded address.
2922
2923 At the time of writing, this hook is not used for the function end
2924 label:
2925
2926 $LFExxx:
2927 .end foo
2928
2929 But this doesn't matter, because GAS doesn't treat a pre-.end label
2930 as a MIPS16 one anyway. */
2931
2932 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2933 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2934
2935 /* This is how to output an element of a case-vector that is absolute. */
2936
2937 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2938 fprintf (STREAM, "\t%s\t%sL%d\n", \
2939 ptr_mode == DImode ? ".dword" : ".word", \
2940 LOCAL_LABEL_PREFIX, \
2941 VALUE)
2942
2943 /* This is how to output an element of a case-vector. We can make the
2944 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2945 is supported. */
2946
2947 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2948 do { \
2949 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2950 { \
2951 if (GET_MODE (BODY) == HImode) \
2952 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2953 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2954 else \
2955 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2956 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2957 } \
2958 else if (TARGET_GPWORD) \
2959 fprintf (STREAM, "\t%s\t%sL%d\n", \
2960 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2961 LOCAL_LABEL_PREFIX, VALUE); \
2962 else if (TARGET_RTP_PIC) \
2963 { \
2964 /* Make the entry relative to the start of the function. */ \
2965 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2966 fprintf (STREAM, "\t%s\t%sL%d-", \
2967 Pmode == DImode ? ".dword" : ".word", \
2968 LOCAL_LABEL_PREFIX, VALUE); \
2969 assemble_name (STREAM, XSTR (fnsym, 0)); \
2970 fprintf (STREAM, "\n"); \
2971 } \
2972 else \
2973 fprintf (STREAM, "\t%s\t%sL%d\n", \
2974 ptr_mode == DImode ? ".dword" : ".word", \
2975 LOCAL_LABEL_PREFIX, VALUE); \
2976 } while (0)
2977
2978 /* Mark inline jump tables as data for the purpose of disassembly. For
2979 simplicity embed the jump table's label number in the local symbol
2980 produced so that multiple jump tables within a single function end
2981 up marked with unique symbols. Retain the alignment setting from
2982 `elfos.h' as we are replacing the definition from there. */
2983
2984 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
2985 #define ASM_OUTPUT_BEFORE_CASE_LABEL(STREAM, PREFIX, NUM, TABLE) \
2986 do \
2987 { \
2988 ASM_OUTPUT_ALIGN ((STREAM), 2); \
2989 if (JUMP_TABLES_IN_TEXT_SECTION) \
2990 mips_set_text_contents_type (STREAM, "__jump_", NUM, FALSE); \
2991 } \
2992 while (0)
2993
2994 /* Reset text marking to code after an inline jump table. Like with
2995 the beginning of a jump table use the label number to keep symbols
2996 unique. */
2997
2998 #define ASM_OUTPUT_CASE_END(STREAM, NUM, TABLE) \
2999 do \
3000 if (JUMP_TABLES_IN_TEXT_SECTION) \
3001 mips_set_text_contents_type (STREAM, "__jend_", NUM, TRUE); \
3002 while (0)
3003
3004 /* This is how to output an assembler line
3005 that says to advance the location counter
3006 to a multiple of 2**LOG bytes. */
3007
3008 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3009 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3010
3011 /* This is how to output an assembler line to advance the location
3012 counter by SIZE bytes. */
3013
3014 #undef ASM_OUTPUT_SKIP
3015 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3016 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3017
3018 /* This is how to output a string. */
3019 #undef ASM_OUTPUT_ASCII
3020 #define ASM_OUTPUT_ASCII mips_output_ascii
3021
3022 \f
3023 /* Default to -G 8 */
3024 #ifndef MIPS_DEFAULT_GVALUE
3025 #define MIPS_DEFAULT_GVALUE 8
3026 #endif
3027
3028 /* Define the strings to put out for each section in the object file. */
3029 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3030 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3031
3032 #undef READONLY_DATA_SECTION_ASM_OP
3033 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3034 \f
3035 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3036 do \
3037 { \
3038 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
3039 TARGET_64BIT ? "daddiu" : "addiu", \
3040 reg_names[STACK_POINTER_REGNUM], \
3041 reg_names[STACK_POINTER_REGNUM], \
3042 TARGET_64BIT ? "sd" : "sw", \
3043 reg_names[REGNO], \
3044 reg_names[STACK_POINTER_REGNUM]); \
3045 } \
3046 while (0)
3047
3048 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3049 do \
3050 { \
3051 mips_push_asm_switch (&mips_noreorder); \
3052 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3053 TARGET_64BIT ? "ld" : "lw", \
3054 reg_names[REGNO], \
3055 reg_names[STACK_POINTER_REGNUM], \
3056 TARGET_64BIT ? "daddu" : "addu", \
3057 reg_names[STACK_POINTER_REGNUM], \
3058 reg_names[STACK_POINTER_REGNUM]); \
3059 mips_pop_asm_switch (&mips_noreorder); \
3060 } \
3061 while (0)
3062
3063 /* How to start an assembler comment.
3064 The leading space is important (the mips native assembler requires it). */
3065 #ifndef ASM_COMMENT_START
3066 #define ASM_COMMENT_START " #"
3067 #endif
3068 \f
3069 #undef SIZE_TYPE
3070 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3071
3072 #undef PTRDIFF_TYPE
3073 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3074
3075 /* The minimum alignment of any expanded block move. */
3076 #define MIPS_MIN_MOVE_MEM_ALIGN 16
3077
3078 /* The maximum number of bytes that can be copied by one iteration of
3079 a cpymemsi loop; see mips_block_move_loop. */
3080 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
3081 (UNITS_PER_WORD * 4)
3082
3083 /* The maximum number of bytes that can be copied by a straight-line
3084 implementation of cpymemsi; see mips_block_move_straight. We want
3085 to make sure that any loop-based implementation will iterate at
3086 least twice. */
3087 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
3088 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
3089
3090 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
3091 values were determined experimentally by benchmarking with CSiBE.
3092 In theory, the call overhead is higher for TARGET_ABICALLS (especially
3093 for o32 where we have to restore $gp afterwards as well as make an
3094 indirect call), but in practice, bumping this up higher for
3095 TARGET_ABICALLS doesn't make much difference to code size. */
3096
3097 #define MIPS_CALL_RATIO 8
3098
3099 /* Any loop-based implementation of cpymemsi will have at least
3100 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
3101 moves, so allow individual copies of fewer elements.
3102
3103 When cpymemsi is not available, use a value approximating
3104 the length of a memcpy call sequence, so that move_by_pieces
3105 will generate inline code if it is shorter than a function call.
3106 Since move_by_pieces_ninsns counts memory-to-memory moves, but
3107 we'll have to generate a load/store pair for each, halve the
3108 value of MIPS_CALL_RATIO to take that into account. */
3109
3110 #define MOVE_RATIO(speed) \
3111 (HAVE_cpymemsi \
3112 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
3113 : MIPS_CALL_RATIO / 2)
3114
3115 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
3116 of the length of a memset call, but use the default otherwise. */
3117
3118 #define CLEAR_RATIO(speed)\
3119 ((speed) ? 15 : MIPS_CALL_RATIO)
3120
3121 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3122 optimizing for size adjust the ratio to account for the overhead of
3123 loading the constant and replicating it across the word. */
3124
3125 #define SET_RATIO(speed) \
3126 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3127 \f
3128 /* Since the bits of the _init and _fini function is spread across
3129 many object files, each potentially with its own GP, we must assume
3130 we need to load our GP. We don't preserve $gp or $ra, since each
3131 init/fini chunk is supposed to initialize $gp, and crti/crtn
3132 already take care of preserving $ra and, when appropriate, $gp. */
3133 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3134 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3135 asm (SECTION_OP "\n\
3136 .set push\n\
3137 .set nomips16\n\
3138 .set noreorder\n\
3139 bal 1f\n\
3140 nop\n\
3141 1: .cpload $31\n\
3142 .set reorder\n\
3143 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3144 jalr $25\n\
3145 .set pop\n\
3146 " TEXT_SECTION_ASM_OP);
3147 #elif (defined _ABIN32 && _MIPS_SIM == _ABIN32)
3148 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3149 asm (SECTION_OP "\n\
3150 .set push\n\
3151 .set nomips16\n\
3152 .set noreorder\n\
3153 bal 1f\n\
3154 nop\n\
3155 1: .set reorder\n\
3156 .cpsetup $31, $2, 1b\n\
3157 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3158 jalr $25\n\
3159 .set pop\n\
3160 " TEXT_SECTION_ASM_OP);
3161 #elif (defined _ABI64 && _MIPS_SIM == _ABI64)
3162 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3163 asm (SECTION_OP "\n\
3164 .set push\n\
3165 .set nomips16\n\
3166 .set noreorder\n\
3167 bal 1f\n\
3168 nop\n\
3169 1: .set reorder\n\
3170 .cpsetup $31, $2, 1b\n\
3171 dla $25, " USER_LABEL_PREFIX #FUNC "\n\
3172 jalr $25\n\
3173 .set pop\n\
3174 " TEXT_SECTION_ASM_OP);
3175 #endif
3176
3177 #ifndef HAVE_AS_TLS
3178 #define HAVE_AS_TLS 0
3179 #endif
3180
3181 #ifndef HAVE_AS_NAN
3182 #define HAVE_AS_NAN 0
3183 #endif
3184
3185 #ifndef USED_FOR_TARGET
3186 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3187 struct mips_asm_switch {
3188 /* The FOO in the description above. */
3189 const char *name;
3190
3191 /* The current block nesting level, or 0 if we aren't in a block. */
3192 int nesting_level;
3193 };
3194
3195 extern const enum reg_class mips_regno_to_class[];
3196 extern const char *current_function_file; /* filename current function is in */
3197 extern int num_source_filenames; /* current .file # */
3198 extern struct mips_asm_switch mips_noreorder;
3199 extern struct mips_asm_switch mips_nomacro;
3200 extern struct mips_asm_switch mips_noat;
3201 extern int mips_dbx_regno[];
3202 extern int mips_dwarf_regno[];
3203 extern bool mips_split_p[];
3204 extern bool mips_split_hi_p[];
3205 extern bool mips_use_pcrel_pool_p[];
3206 extern const char *mips_lo_relocs[];
3207 extern const char *mips_hi_relocs[];
3208 extern enum processor mips_arch; /* which cpu to codegen for */
3209 extern enum processor mips_tune; /* which cpu to schedule for */
3210 extern int mips_isa; /* architectural level */
3211 extern int mips_isa_rev;
3212 extern const struct mips_cpu_info *mips_arch_info;
3213 extern const struct mips_cpu_info *mips_tune_info;
3214 extern unsigned int mips_base_compression_flags;
3215 extern GTY(()) struct target_globals *mips16_globals;
3216 extern GTY(()) struct target_globals *micromips_globals;
3217
3218 /* Information about a function's frame layout. */
3219 struct GTY(()) mips_frame_info {
3220 /* The size of the frame in bytes. */
3221 HOST_WIDE_INT total_size;
3222
3223 /* The number of bytes allocated to variables. */
3224 HOST_WIDE_INT var_size;
3225
3226 /* The number of bytes allocated to outgoing function arguments. */
3227 HOST_WIDE_INT args_size;
3228
3229 /* The number of bytes allocated to the .cprestore slot, or 0 if there
3230 is no such slot. */
3231 HOST_WIDE_INT cprestore_size;
3232
3233 /* Bit X is set if the function saves or restores GPR X. */
3234 unsigned int mask;
3235
3236 /* Likewise FPR X. */
3237 unsigned int fmask;
3238
3239 /* Likewise doubleword accumulator X ($acX). */
3240 unsigned int acc_mask;
3241
3242 /* The number of GPRs, FPRs, doubleword accumulators and COP0
3243 registers saved. */
3244 unsigned int num_gp;
3245 unsigned int num_fp;
3246 unsigned int num_acc;
3247 unsigned int num_cop0_regs;
3248
3249 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
3250 save slots from the top of the frame, or zero if no such slots are
3251 needed. */
3252 HOST_WIDE_INT gp_save_offset;
3253 HOST_WIDE_INT fp_save_offset;
3254 HOST_WIDE_INT acc_save_offset;
3255 HOST_WIDE_INT cop0_save_offset;
3256
3257 /* Likewise, but giving offsets from the bottom of the frame. */
3258 HOST_WIDE_INT gp_sp_offset;
3259 HOST_WIDE_INT fp_sp_offset;
3260 HOST_WIDE_INT acc_sp_offset;
3261 HOST_WIDE_INT cop0_sp_offset;
3262
3263 /* Similar, but the value passed to _mcount. */
3264 HOST_WIDE_INT ra_fp_offset;
3265
3266 /* The offset of arg_pointer_rtx from the bottom of the frame. */
3267 HOST_WIDE_INT arg_pointer_offset;
3268
3269 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
3270 HOST_WIDE_INT hard_frame_pointer_offset;
3271 };
3272
3273 /* Enumeration for masked vectored (VI) and non-masked (EIC) interrupts. */
3274 enum mips_int_mask
3275 {
3276 INT_MASK_EIC = -1,
3277 INT_MASK_SW0 = 0,
3278 INT_MASK_SW1 = 1,
3279 INT_MASK_HW0 = 2,
3280 INT_MASK_HW1 = 3,
3281 INT_MASK_HW2 = 4,
3282 INT_MASK_HW3 = 5,
3283 INT_MASK_HW4 = 6,
3284 INT_MASK_HW5 = 7
3285 };
3286
3287 /* Enumeration to mark the existence of the shadow register set.
3288 SHADOW_SET_INTSTACK indicates a shadow register set with a valid stack
3289 pointer. */
3290 enum mips_shadow_set
3291 {
3292 SHADOW_SET_NO,
3293 SHADOW_SET_YES,
3294 SHADOW_SET_INTSTACK
3295 };
3296
3297 struct GTY(()) machine_function {
3298 /* The next floating-point condition-code register to allocate
3299 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
3300 unsigned int next_fcc;
3301
3302 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
3303 rtx mips16_gp_pseudo_rtx;
3304
3305 /* The number of extra stack bytes taken up by register varargs.
3306 This area is allocated by the callee at the very top of the frame. */
3307 int varargs_size;
3308
3309 /* The current frame information, calculated by mips_compute_frame_info. */
3310 struct mips_frame_info frame;
3311
3312 /* The register to use as the function's global pointer, or INVALID_REGNUM
3313 if the function doesn't need one. */
3314 unsigned int global_pointer;
3315
3316 /* How many instructions it takes to load a label into $AT, or 0 if
3317 this property hasn't yet been calculated. */
3318 unsigned int load_label_num_insns;
3319
3320 /* True if mips_adjust_insn_length should ignore an instruction's
3321 hazard attribute. */
3322 bool ignore_hazard_length_p;
3323
3324 /* True if the whole function is suitable for .set noreorder and
3325 .set nomacro. */
3326 bool all_noreorder_p;
3327
3328 /* True if the function has "inflexible" and "flexible" references
3329 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
3330 and mips_cfun_has_flexible_gp_ref_p for details. */
3331 bool has_inflexible_gp_insn_p;
3332 bool has_flexible_gp_insn_p;
3333
3334 /* True if the function's prologue must load the global pointer
3335 value into pic_offset_table_rtx and store the same value in
3336 the function's cprestore slot (if any). Even if this value
3337 is currently false, we may decide to set it to true later;
3338 see mips_must_initialize_gp_p () for details. */
3339 bool must_initialize_gp_p;
3340
3341 /* True if the current function must restore $gp after any potential
3342 clobber. This value is only meaningful during the first post-epilogue
3343 split_insns pass; see mips_must_initialize_gp_p () for details. */
3344 bool must_restore_gp_when_clobbered_p;
3345
3346 /* True if this is an interrupt handler. */
3347 bool interrupt_handler_p;
3348
3349 /* Records the way in which interrupts should be masked. Only used if
3350 interrupts are not kept masked. */
3351 enum mips_int_mask int_mask;
3352
3353 /* Records if this is an interrupt handler that uses shadow registers. */
3354 enum mips_shadow_set use_shadow_register_set;
3355
3356 /* True if this is an interrupt handler that should keep interrupts
3357 masked. */
3358 bool keep_interrupts_masked_p;
3359
3360 /* True if this is an interrupt handler that should use DERET
3361 instead of ERET. */
3362 bool use_debug_exception_return_p;
3363
3364 /* True if at least one of the formal parameters to a function must be
3365 written to the frame header (probably so its address can be taken). */
3366 bool does_not_use_frame_header;
3367
3368 /* True if none of the functions that are called by this function need
3369 stack space allocated for their arguments. */
3370 bool optimize_call_stack;
3371
3372 /* True if one of the functions calling this function may not allocate
3373 a frame header. */
3374 bool callers_may_not_allocate_frame;
3375
3376 /* True if GCC stored callee saved registers in the frame header. */
3377 bool use_frame_header_for_callee_saved_regs;
3378 };
3379 #endif
3380
3381 /* Enable querying of DFA units. */
3382 #define CPU_UNITS_QUERY 1
3383
3384 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3385 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3386
3387 /* As on most targets, we want the .eh_frame section to be read-only where
3388 possible. And as on most targets, this means two things:
3389
3390 (a) Non-locally-binding pointers must have an indirect encoding,
3391 so that the addresses in the .eh_frame section itself become
3392 locally-binding.
3393
3394 (b) A shared library's .eh_frame section must encode locally-binding
3395 pointers in a relative (relocation-free) form.
3396
3397 However, MIPS has traditionally not allowed directives like:
3398
3399 .long x-.
3400
3401 in cases where "x" is in a different section, or is not defined in the
3402 same assembly file. We are therefore unable to emit the PC-relative
3403 form required by (b) at assembly time.
3404
3405 Fortunately, the linker is able to convert absolute addresses into
3406 PC-relative addresses on our behalf. Unfortunately, only certain
3407 versions of the linker know how to do this for indirect pointers,
3408 and for personality data. We must fall back on using writable
3409 .eh_frame sections for shared libraries if the linker does not
3410 support this feature. */
3411 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3412 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
3413
3414 /* For switching between MIPS16 and non-MIPS16 modes. */
3415 #define SWITCHABLE_TARGET 1
3416
3417 /* Several named MIPS patterns depend on Pmode. These patterns have the
3418 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3419 Add the appropriate suffix to generator function NAME and invoke it
3420 with arguments ARGS. */
3421 #define PMODE_INSN(NAME, ARGS) \
3422 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)
3423
3424 /* If we are *not* using multilibs and the default ABI is not ABI_32 we
3425 need to change these from /lib and /usr/lib. */
3426 #if MIPS_ABI_DEFAULT == ABI_N32
3427 #define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
3428 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
3429 #elif MIPS_ABI_DEFAULT == ABI_64
3430 #define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
3431 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
3432 #endif
3433
3434 /* Load store bonding is not supported by micromips and fix_24k. The
3435 performance can be degraded for those targets. Hence, do not bond for
3436 micromips or fix_24k. */
3437 #define ENABLE_LD_ST_PAIRS \
3438 (TARGET_LOAD_STORE_PAIRS \
3439 && (TUNE_P5600 || TUNE_I6400 || TUNE_P6600) \
3440 && !TARGET_MICROMIPS && !TARGET_FIX_24K)
3441
3442 #define NEED_INDICATE_EXEC_STACK 0
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