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[committed] Fix previously latent bug in reorg affecting cris port
[official-gcc.git] / gcc / config / mips / mips.h
blob84dd64d98a0f609743f923fcb6b4374508afc04b
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2024 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.cc. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 enum mips_isa {
46 MIPS_ISA_MIPS1 = 1,
47 MIPS_ISA_MIPS2 = 2,
48 MIPS_ISA_MIPS3 = 3,
49 MIPS_ISA_MIPS4 = 4,
50 MIPS_ISA_MIPS32 = 32,
51 MIPS_ISA_MIPS32R2 = 33,
52 MIPS_ISA_MIPS32R3 = 34,
53 MIPS_ISA_MIPS32R5 = 36,
54 MIPS_ISA_MIPS32R6 = 37,
55 MIPS_ISA_MIPS64 = 64,
56 MIPS_ISA_MIPS64R2 = 65,
57 MIPS_ISA_MIPS64R3 = 66,
58 MIPS_ISA_MIPS64R5 = 68,
59 MIPS_ISA_MIPS64R6 = 69
60 };
61
62 /* Masks that affect tuning.
63
64 PTF_AVOID_BRANCHLIKELY_SPEED
65 Set if it is usually not profitable to use branch-likely instructions
66 for this target when optimizing code for speed, typically because
67 the branches are always predicted taken and so incur a large overhead
68 when not taken.
69
70 PTF_AVOID_BRANCHLIKELY_SIZE
71 As above but when optimizing for size.
72
73 PTF_AVOID_BRANCHLIKELY_ALWAYS
74 As above but regardless of whether we optimize for speed or size.
75
76 PTF_AVOID_IMADD
77 Set if it is usually not profitable to use the integer MADD or MSUB
78 instructions because of the overhead of getting the result out of
79 the HI/LO registers. */
80
81 #define PTF_AVOID_BRANCHLIKELY_SPEED 0x1
82 #define PTF_AVOID_BRANCHLIKELY_SIZE 0x2
83 #define PTF_AVOID_BRANCHLIKELY_ALWAYS (PTF_AVOID_BRANCHLIKELY_SPEED | \
84 PTF_AVOID_BRANCHLIKELY_SIZE)
85 #define PTF_AVOID_IMADD 0x4
86
87 /* Information about one recognized processor. Defined here for the
88 benefit of TARGET_CPU_CPP_BUILTINS. */
89 struct mips_cpu_info {
90 /* The 'canonical' name of the processor as far as GCC is concerned.
91 It's typically a manufacturer's prefix followed by a numerical
92 designation. It should be lowercase. */
93 const char *name;
94
95 /* The internal processor number that most closely matches this
96 entry. Several processors can have the same value, if there's no
97 difference between them from GCC's point of view. */
98 enum processor cpu;
99
100 /* The ISA level that the processor implements. */
101 enum mips_isa isa;
102
103 /* A mask of PTF_* values. */
104 unsigned int tune_flags;
105 };
106
107 #include "config/mips/mips-opts.h"
108
109 /* Macros to silence warnings about numbers being signed in traditional
110 C and unsigned in ISO C when compiled on 32-bit hosts. */
111
112 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
113 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
114 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
115
116 \f
117 /* Run-time compilation parameters selecting different hardware subsets. */
118
119 /* True if we are generating position-independent VxWorks RTP code. */
120 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
121
122 /* Compact branches must not be used if the user either selects the
123 'never' policy or the 'optimal' / 'always' policy on a core that lacks
124 compact branch instructions. */
125 #define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER || !ISA_HAS_COMPACT_BRANCHES)
126
127 /* Compact branches may be used if the user either selects the
128 'always' policy or the 'optimal' policy on a core that supports
129 compact branch instructions. */
130 #define TARGET_CB_MAYBE (TARGET_CB_ALWAYS \
131 || (mips_cb == MIPS_CB_OPTIMAL \
132 && ISA_HAS_COMPACT_BRANCHES))
133
134 /* Compact branches must always be generated if the user selects
135 the 'always' policy on a core support compact branches,
136 or the 'optimal' policy on a core that lacks delay slot branch instructions. */
137 #define TARGET_CB_ALWAYS ((mips_cb == MIPS_CB_ALWAYS \
138 && ISA_HAS_COMPACT_BRANCHES) \
139 || (mips_cb == MIPS_CB_OPTIMAL \
140 && !ISA_HAS_DELAY_SLOTS))
141
142 /* Special handling for JRC that exists in microMIPSR3 as well as R6
143 ISAs with full compact branch support. */
144 #define ISA_HAS_JRC ((ISA_HAS_COMPACT_BRANCHES \
145 || TARGET_MICROMIPS) \
146 && mips_cb != MIPS_CB_NEVER)
147
148 /* True if assembler support %gp_rel etc. */
149 #define TARGET_EXPLICIT_RELOCS \
150 (mips_opt_explicit_relocs >= MIPS_EXPLICIT_RELOCS_BASE)
151
152 /* True if assembler support %pcrel_hi/%pcrel_lo. */
153 #define TARGET_EXPLICIT_RELOCS_PCREL \
154 (mips_opt_explicit_relocs >= MIPS_EXPLICIT_RELOCS_PCREL)
155
156 /* True if the output file is marked as ".abicalls; .option pic0"
157 (-call_nonpic). */
158 #define TARGET_ABICALLS_PIC0 \
159 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
160
161 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
162 #define TARGET_ABICALLS_PIC2 \
163 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
164
165 /* True if the call patterns should be split into a jalr followed by
166 an instruction to restore $gp. It is only safe to split the load
167 from the call when every use of $gp is explicit.
168
169 See mips_must_initialize_gp_p for details about how we manage the
170 global pointer. */
171
172 #define TARGET_SPLIT_CALLS \
173 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
174
175 /* True if we're generating a form of -mabicalls in which we can use
176 operators like %hi and %lo to refer to locally-binding symbols.
177 We can only do this for -mno-shared, and only then if we can use
178 relocation operations instead of assembly macros. It isn't really
179 worth using absolute sequences for 64-bit symbols because GOT
180 accesses are so much shorter. */
181
182 #define TARGET_ABSOLUTE_ABICALLS \
183 (TARGET_ABICALLS \
184 && !TARGET_SHARED \
185 && TARGET_EXPLICIT_RELOCS \
186 && !ABI_HAS_64BIT_SYMBOLS)
187
188 /* True if we can optimize sibling calls. For simplicity, we only
189 handle cases in which call_insn_operand will reject invalid
190 sibcall addresses. There are two cases in which this isn't true:
191
192 - TARGET_MIPS16. call_insn_operand accepts constant addresses
193 but there is no direct jump instruction. It isn't worth
194 using sibling calls in this case anyway; they would usually
195 be longer than normal calls.
196
197 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
198 accepts global constants, but all sibcalls must be indirect. */
199 #define TARGET_SIBCALLS \
200 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
201
202 /* True if we need to use a global offset table to access some symbols. */
203 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
204
205 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
206 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
207
208 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
209 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
210
211 /* True if we should use .cprestore to store to the cprestore slot.
212
213 We continue to use .cprestore for explicit-reloc code so that JALs
214 inside inline asms will work correctly. */
215 #define TARGET_CPRESTORE_DIRECTIVE \
216 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
217
218 /* True if we can use the J and JAL instructions. */
219 #define TARGET_ABSOLUTE_JUMPS \
220 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
221
222 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
223 This is true for both the PIC and non-PIC VxWorks RTP modes. */
224 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
225
226 /* True if .gpword or .gpdword should be used for switch tables. */
227 #define TARGET_GPWORD \
228 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
229
230 /* True if the output must have a writable .eh_frame.
231 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
232 #ifdef HAVE_LD_PERSONALITY_RELAXATION
233 #define TARGET_WRITABLE_EH_FRAME 0
234 #else
235 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
236 #endif
237
238 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
239 #ifdef HAVE_AS_DSPR1_MULT
240 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
241 #else
242 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
243 #endif
244
245 /* ISA has LSA available. */
246 #define ISA_HAS_LSA (mips_isa_rev >= 6 || ISA_HAS_MSA)
247
248 /* ISA has DLSA available. */
249 #define ISA_HAS_DLSA (TARGET_64BIT \
250 && (mips_isa_rev >= 6 \
251 || ISA_HAS_MSA))
252
253 /* ISA load/store instructions can handle unaligned address */
254 #define ISA_HAS_UNALIGNED_ACCESS (!TARGET_STRICT_ALIGN \
255 && (mips_isa_rev >= 6))
256
257 /* The ISA compression flags that are currently in effect. */
258 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
259
260 /* Generate mips16 code */
261 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
262 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
263 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= MIPS_ISA_MIPS32)
264 /* Generate mips16e register save/restore sequences. */
265 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
266
267 /* True if we're generating a form of MIPS16 code in which general
268 text loads are allowed. */
269 #define TARGET_MIPS16_TEXT_LOADS \
270 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
271
272 /* True if we're generating a form of MIPS16 code in which PC-relative
273 loads are allowed. */
274 #define TARGET_MIPS16_PCREL_LOADS \
275 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
276
277 /* Generic ISA defines. */
278 #define ISA_MIPS1 (mips_isa == MIPS_ISA_MIPS1)
279 #define ISA_MIPS2 (mips_isa == MIPS_ISA_MIPS2)
280 #define ISA_MIPS3 (mips_isa == MIPS_ISA_MIPS3)
281 #define ISA_MIPS4 (mips_isa == MIPS_ISA_MIPS4)
282 #define ISA_MIPS32 (mips_isa == MIPS_ISA_MIPS32)
283 #define ISA_MIPS32R2 (mips_isa == MIPS_ISA_MIPS32R2)
284 #define ISA_MIPS32R3 (mips_isa == MIPS_ISA_MIPS32R3)
285 #define ISA_MIPS32R5 (mips_isa == MIPS_ISA_MIPS32R5)
286 #define ISA_MIPS32R6 (mips_isa == MIPS_ISA_MIPS32R6)
287 #define ISA_MIPS64 (mips_isa == MIPS_ISA_MIPS64)
288 #define ISA_MIPS64R2 (mips_isa == MIPS_ISA_MIPS64R2)
289 #define ISA_MIPS64R3 (mips_isa == MIPS_ISA_MIPS64R3)
290 #define ISA_MIPS64R5 (mips_isa == MIPS_ISA_MIPS64R5)
291 #define ISA_MIPS64R6 (mips_isa == MIPS_ISA_MIPS64R6)
292
293 /* Architecture target defines. */
294 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
295 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
296 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
297 #define TARGET_GS464 (mips_arch == PROCESSOR_GS464)
298 #define TARGET_GS464E (mips_arch == PROCESSOR_GS464E)
299 #define TARGET_GS264E (mips_arch == PROCESSOR_GS264E)
300 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
301 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
302 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
303 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
304 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
305 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
306 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
307 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
308 #define TARGET_MIPS8000 (mips_arch == PROCESSOR_R8000)
309 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
310 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
311 || mips_arch == PROCESSOR_OCTEON2 \
312 || mips_arch == PROCESSOR_OCTEON3)
313 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \
314 || mips_arch == PROCESSOR_OCTEON3)
315 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
316 || mips_arch == PROCESSOR_SB1A)
317 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
318 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
319
320 /* Scheduling target defines. */
321 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
322 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
323 || mips_tune == PROCESSOR_24KF2_1 \
324 || mips_tune == PROCESSOR_24KF1_1)
325 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
326 || mips_tune == PROCESSOR_74KF2_1 \
327 || mips_tune == PROCESSOR_74KF1_1 \
328 || mips_tune == PROCESSOR_74KF3_2)
329 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
330 || mips_tune == PROCESSOR_LOONGSON_2F)
331 #define TUNE_GS464 (mips_tune == PROCESSOR_GS464)
332 #define TUNE_GS464E (mips_tune == PROCESSOR_GS464E)
333 #define TUNE_GS264E (mips_tune == PROCESSOR_GS264E)
334 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
335 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
336 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
337 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
338 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
339 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
340 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
341 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
342 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
343 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
344 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
345 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
346 || mips_tune == PROCESSOR_OCTEON2 \
347 || mips_tune == PROCESSOR_OCTEON3)
348 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
349 || mips_tune == PROCESSOR_SB1A)
350 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
351 #define TUNE_I6400 (mips_tune == PROCESSOR_I6400)
352 #define TUNE_P6600 (mips_tune == PROCESSOR_P6600)
353
354 /* True if the pre-reload scheduler should try to create chains of
355 multiply-add or multiply-subtract instructions. For example,
356 suppose we have:
357
358 t1 = a * b
359 t2 = t1 + c * d
360 t3 = e * f
361 t4 = t3 - g * h
362
363 t1 will have a higher priority than t2 and t3 will have a higher
364 priority than t4. However, before reload, there is no dependence
365 between t1 and t3, and they can often have similar priorities.
366 The scheduler will then tend to prefer:
367
368 t1 = a * b
369 t3 = e * f
370 t2 = t1 + c * d
371 t4 = t3 - g * h
372
373 which stops us from making full use of macc/madd-style instructions.
374 This sort of situation occurs frequently in Fourier transforms and
375 in unrolled loops.
376
377 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
378 queue so that chained multiply-add and multiply-subtract instructions
379 appear ahead of any other instruction that is likely to clobber lo.
380 In the example above, if t2 and t3 become ready at the same time,
381 the code ensures that t2 is scheduled first.
382
383 Multiply-accumulate instructions are a bigger win for some targets
384 than others, so this macro is defined on an opt-in basis. */
385 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
386 || TUNE_MIPS4120 \
387 || TUNE_MIPS4130 \
388 || TUNE_24K \
389 || TUNE_P5600)
390
391 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
392 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
393
394 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
395 directly accessible, while the command-line options select
396 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
397 in use. */
398 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
399 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
400
401 /* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents
402 -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */
403 #define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX)
404
405 /* TARGET_O32_FP64A_ABI represents all the conditions that form the
406 o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */
407 #define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \
408 && !TARGET_ODD_SPREG)
409
410 /* False if SC acts as a memory barrier with respect to itself,
411 otherwise a SYNC will be emitted after SC for atomic operations
412 that require ordering between the SC and following loads and
413 stores. It does not tell anything about ordering of loads and
414 stores prior to and following the SC, only about the SC itself and
415 those loads and stores follow it. */
416 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
417
418 /* Define preprocessor macros for the -march and -mtune options.
419 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
420 processor. If INFO's canonical name is "foo", define PREFIX to
421 be "foo", and define an additional macro PREFIX_FOO. */
422 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
423 do \
424 { \
425 char *macro, *p; \
426 \
427 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
428 for (p = macro; *p != 0; p++) \
429 if (*p == '+') \
430 *p = 'P'; \
431 else \
432 *p = TOUPPER (*p); \
433 \
434 builtin_define (macro); \
435 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
436 free (macro); \
437 } \
438 while (0)
439
440 /* Target CPU builtins. */
441 #define TARGET_CPU_CPP_BUILTINS() \
442 do \
443 { \
444 builtin_assert ("machine=mips"); \
445 builtin_assert ("cpu=mips"); \
446 builtin_define ("__mips__"); \
447 builtin_define ("_mips"); \
448 \
449 /* We do this here because __mips is defined below and so we \
450 can't use builtin_define_std. We don't ever want to define \
451 "mips" for VxWorks because some of the VxWorks headers \
452 construct include filenames from a root directory macro, \
453 an architecture macro and a filename, where the architecture \
454 macro expands to 'mips'. If we define 'mips' to 1, the \
455 architecture macro expands to 1 as well. */ \
456 if (!flag_iso && !TARGET_VXWORKS) \
457 builtin_define ("mips"); \
458 \
459 if (TARGET_64BIT) \
460 builtin_define ("__mips64"); \
461 \
462 /* Treat _R3000 and _R4000 like register-size \
463 defines, which is how they've historically \
464 been used. */ \
465 if (TARGET_64BIT) \
466 { \
467 builtin_define_std ("R4000"); \
468 builtin_define ("_R4000"); \
469 } \
470 else \
471 { \
472 builtin_define_std ("R3000"); \
473 builtin_define ("_R3000"); \
474 } \
475 \
476 if (TARGET_FLOAT64) \
477 builtin_define ("__mips_fpr=64"); \
478 else if (TARGET_FLOATXX) \
479 builtin_define ("__mips_fpr=0"); \
480 else \
481 builtin_define ("__mips_fpr=32"); \
482 \
483 if (mips_base_compression_flags & MASK_MIPS16) \
484 builtin_define ("__mips16"); \
485 \
486 if (TARGET_MIPS16E2) \
487 builtin_define ("__mips_mips16e2"); \
488 \
489 if (TARGET_MIPS3D) \
490 builtin_define ("__mips3d"); \
491 \
492 if (TARGET_SMARTMIPS) \
493 builtin_define ("__mips_smartmips"); \
494 \
495 if (mips_base_compression_flags & MASK_MICROMIPS) \
496 builtin_define ("__mips_micromips"); \
497 \
498 if (TARGET_MCU) \
499 builtin_define ("__mips_mcu"); \
500 \
501 if (TARGET_EVA) \
502 builtin_define ("__mips_eva"); \
503 \
504 if (TARGET_DSP) \
505 { \
506 builtin_define ("__mips_dsp"); \
507 if (TARGET_DSPR2) \
508 { \
509 builtin_define ("__mips_dspr2"); \
510 builtin_define ("__mips_dsp_rev=2"); \
511 } \
512 else \
513 builtin_define ("__mips_dsp_rev=1"); \
514 } \
515 \
516 if (ISA_HAS_MSA) \
517 { \
518 builtin_define ("__mips_msa"); \
519 builtin_define ("__mips_msa_width=128"); \
520 } \
521 \
522 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
523 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
524 \
525 if (ISA_MIPS1) \
526 { \
527 builtin_define ("__mips=1"); \
528 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
529 } \
530 else if (ISA_MIPS2) \
531 { \
532 builtin_define ("__mips=2"); \
533 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
534 } \
535 else if (ISA_MIPS3) \
536 { \
537 builtin_define ("__mips=3"); \
538 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
539 } \
540 else if (ISA_MIPS4) \
541 { \
542 builtin_define ("__mips=4"); \
543 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
544 } \
545 else if (mips_isa >= MIPS_ISA_MIPS32 \
546 && mips_isa < MIPS_ISA_MIPS64) \
547 { \
548 builtin_define ("__mips=32"); \
549 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
550 } \
551 else if (mips_isa >= MIPS_ISA_MIPS64) \
552 { \
553 builtin_define ("__mips=64"); \
554 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
555 } \
556 if (mips_isa_rev > 0) \
557 builtin_define_with_int_value ("__mips_isa_rev", \
558 mips_isa_rev); \
559 \
560 switch (mips_abi) \
561 { \
562 case ABI_32: \
563 builtin_define ("_ABIO32=1"); \
564 builtin_define ("_MIPS_SIM=_ABIO32"); \
565 break; \
566 \
567 case ABI_N32: \
568 builtin_define ("_ABIN32=2"); \
569 builtin_define ("_MIPS_SIM=_ABIN32"); \
570 break; \
571 \
572 case ABI_64: \
573 builtin_define ("_ABI64=3"); \
574 builtin_define ("_MIPS_SIM=_ABI64"); \
575 break; \
576 \
577 case ABI_O64: \
578 builtin_define ("_ABIO64=4"); \
579 builtin_define ("_MIPS_SIM=_ABIO64"); \
580 break; \
581 } \
582 \
583 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
584 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
585 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
586 builtin_define_with_int_value ("_MIPS_FPSET", \
587 32 / MAX_FPRS_PER_FMT); \
588 builtin_define_with_int_value ("_MIPS_SPFPSET", \
589 TARGET_ODD_SPREG ? 32 : 16); \
590 \
591 /* These defines reflect the ABI in use, not whether the \
592 FPU is directly accessible. */ \
593 if (TARGET_NO_FLOAT) \
594 builtin_define ("__mips_no_float"); \
595 else if (TARGET_HARD_FLOAT_ABI) \
596 builtin_define ("__mips_hard_float"); \
597 else \
598 builtin_define ("__mips_soft_float"); \
599 \
600 if (TARGET_SINGLE_FLOAT) \
601 builtin_define ("__mips_single_float"); \
602 \
603 if (TARGET_PAIRED_SINGLE_FLOAT) \
604 builtin_define ("__mips_paired_single_float"); \
605 \
606 if (mips_abs == MIPS_IEEE_754_2008) \
607 builtin_define ("__mips_abs2008"); \
608 \
609 if (mips_nan == MIPS_IEEE_754_2008) \
610 builtin_define ("__mips_nan2008"); \
611 \
612 if (TARGET_BIG_ENDIAN) \
613 { \
614 builtin_define_std ("MIPSEB"); \
615 builtin_define ("_MIPSEB"); \
616 } \
617 else \
618 { \
619 builtin_define_std ("MIPSEL"); \
620 builtin_define ("_MIPSEL"); \
621 } \
622 \
623 /* Whether calls should go through $25. The separate __PIC__ \
624 macro indicates whether abicalls code might use a GOT. */ \
625 if (TARGET_ABICALLS) \
626 builtin_define ("__mips_abicalls"); \
627 \
628 /* Whether Loongson vector modes are enabled. */ \
629 if (TARGET_LOONGSON_MMI) \
630 { \
631 builtin_define ("__mips_loongson_vector_rev"); \
632 builtin_define ("__mips_loongson_mmi"); \
633 } \
634 \
635 /* Whether Loongson EXT modes are enabled. */ \
636 if (TARGET_LOONGSON_EXT) \
637 { \
638 builtin_define ("__mips_loongson_ext"); \
639 if (TARGET_LOONGSON_EXT2) \
640 { \
641 builtin_define ("__mips_loongson_ext2"); \
642 builtin_define ("__mips_loongson_ext_rev=2"); \
643 } \
644 else \
645 builtin_define ("__mips_loongson_ext_rev=1"); \
646 } \
647 \
648 /* Historical Octeon macro. */ \
649 if (TARGET_OCTEON) \
650 builtin_define ("__OCTEON__"); \
651 \
652 if (TARGET_SYNCI) \
653 builtin_define ("__mips_synci"); \
654 \
655 /* Macros dependent on the C dialect. */ \
656 if (preprocessing_asm_p ()) \
657 { \
658 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
659 builtin_define ("_LANGUAGE_ASSEMBLY"); \
660 } \
661 else if (c_dialect_cxx ()) \
662 { \
663 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
664 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
665 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
666 } \
667 else \
668 { \
669 builtin_define_std ("LANGUAGE_C"); \
670 builtin_define ("_LANGUAGE_C"); \
671 } \
672 if (c_dialect_objc ()) \
673 { \
674 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
675 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
676 /* Bizarre, but retained for backwards compatibility. */ \
677 builtin_define_std ("LANGUAGE_C"); \
678 builtin_define ("_LANGUAGE_C"); \
679 } \
680 \
681 if (mips_abi == ABI_EABI) \
682 builtin_define ("__mips_eabi"); \
683 \
684 if (TARGET_CACHE_BUILTIN) \
685 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
686 if (!ISA_HAS_LXC1_SXC1) \
687 builtin_define ("__mips_no_lxc1_sxc1"); \
688 if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4) \
689 builtin_define ("__mips_no_madd4"); \
690 \
691 if (TARGET_CB_NEVER) \
692 builtin_define ("__mips_compact_branches_never"); \
693 else if (TARGET_CB_ALWAYS) \
694 builtin_define ("__mips_compact_branches_always"); \
695 else \
696 builtin_define ("__mips_compact_branches_optimal"); \
697 \
698 if (STRICT_ALIGNMENT) \
699 builtin_define ("__mips_strict_alignment"); \
700 } \
701 while (0)
702
703 /* Default target_flags if no switches are specified */
704
705 #ifndef TARGET_DEFAULT
706 #define TARGET_DEFAULT 0
707 #endif
708
709 #ifndef TARGET_CPU_DEFAULT
710 #define TARGET_CPU_DEFAULT 0
711 #endif
712
713 #ifndef TARGET_ENDIAN_DEFAULT
714 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
715 #endif
716
717 #ifdef IN_LIBGCC2
718 #undef TARGET_64BIT
719 /* Make this compile time constant for libgcc2 */
720 #ifdef __mips64
721 #define TARGET_64BIT 1
722 #else
723 #define TARGET_64BIT 0
724 #endif
725 #endif /* IN_LIBGCC2 */
726
727 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
728 when compiled with hardware floating point. This is because MIPS16
729 code cannot save and restore the floating-point registers, which is
730 important if in a mixed MIPS16/non-MIPS16 environment. */
731
732 #ifdef IN_LIBGCC2
733 #if __mips_hard_float
734 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
735 #endif
736 #endif /* IN_LIBGCC2 */
737
738 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
739
740 #ifndef MULTILIB_ENDIAN_DEFAULT
741 #if TARGET_ENDIAN_DEFAULT == 0
742 #define MULTILIB_ENDIAN_DEFAULT "EL"
743 #else
744 #define MULTILIB_ENDIAN_DEFAULT "EB"
745 #endif
746 #endif
747
748 #ifndef MULTILIB_ISA_DEFAULT
749 #if MIPS_ISA_DEFAULT == MIPS_ISA_MIPS1
750 #define MULTILIB_ISA_DEFAULT "mips1"
751 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS2
752 #define MULTILIB_ISA_DEFAULT "mips2"
753 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS3
754 #define MULTILIB_ISA_DEFAULT "mips3"
755 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS4
756 #define MULTILIB_ISA_DEFAULT "mips4"
757 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32
758 #define MULTILIB_ISA_DEFAULT "mips32"
759 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32R2
760 #define MULTILIB_ISA_DEFAULT "mips32r2"
761 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32R6
762 #define MULTILIB_ISA_DEFAULT "mips32r6"
763 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64
764 #define MULTILIB_ISA_DEFAULT "mips64"
765 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64R2
766 #define MULTILIB_ISA_DEFAULT "mips64r2"
767 #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64R6
768 #define MULTILIB_ISA_DEFAULT "mips64r6"
769 #else
770 #define MULTILIB_ISA_DEFAULT "mips1"
771 #endif
772 #endif
773
774 #ifndef MIPS_ABI_DEFAULT
775 #define MIPS_ABI_DEFAULT ABI_32
776 #endif
777
778 /* Use the most portable ABI flag for the ASM specs. */
779
780 #if MIPS_ABI_DEFAULT == ABI_32
781 #define MULTILIB_ABI_DEFAULT "mabi=32"
782 #elif MIPS_ABI_DEFAULT == ABI_O64
783 #define MULTILIB_ABI_DEFAULT "mabi=o64"
784 #elif MIPS_ABI_DEFAULT == ABI_N32
785 #define MULTILIB_ABI_DEFAULT "mabi=n32"
786 #elif MIPS_ABI_DEFAULT == ABI_64
787 #define MULTILIB_ABI_DEFAULT "mabi=64"
788 #elif MIPS_ABI_DEFAULT == ABI_EABI
789 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
790 #endif
791
792 #ifndef MULTILIB_DEFAULTS
793 #define MULTILIB_DEFAULTS \
794 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
795 #endif
796
797 /* We must pass -EL to the linker by default for little endian embedded
798 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
799 linker will default to using big-endian output files. The OUTPUT_FORMAT
800 line must be in the linker script, otherwise -EB/-EL will not work. */
801
802 #ifndef ENDIAN_SPEC
803 #if TARGET_ENDIAN_DEFAULT == 0
804 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
805 #else
806 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
807 #endif
808 #endif
809
810 /* A spec condition that matches all non-mips16 -mips arguments. */
811
812 #define MIPS_ISA_LEVEL_OPTION_SPEC \
813 "mips1|mips2|mips3|mips4|mips32*|mips64*"
814
815 /* A spec condition that matches all non-mips16 architecture arguments. */
816
817 #define MIPS_ARCH_OPTION_SPEC \
818 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
819
820 /* A spec that infers a -mips argument from an -march argument. */
821
822 #define MIPS_ISA_LEVEL_SPEC \
823 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
824 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
825 %{march=mips2|march=r6000:-mips2} \
826 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
827 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
828 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
829 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
830 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
831 |march=34k*|march=74k*|march=m14k*|march=1004k* \
832 |march=interaptiv: -mips32r2} \
833 %{march=mips32r3: -mips32r3} \
834 %{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \
835 %{march=mips32r6: -mips32r6} \
836 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
837 |march=xlr: -mips64} \
838 %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=gs264e \
839 |march=octeon|march=xlp: -mips64r2} \
840 %{march=mips64r3: -mips64r3} \
841 %{march=mips64r5: -mips64r5} \
842 %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}"
843
844 /* A spec that injects the default multilib ISA if no architecture is
845 specified. */
846
847 #define MIPS_DEFAULT_ISA_LEVEL_SPEC \
848 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
849 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
850
851 /* A spec that infers a -mhard-float or -msoft-float setting from an
852 -march argument. Note that soft-float and hard-float code are not
853 link-compatible. */
854
855 #define MIPS_ARCH_FLOAT_SPEC \
856 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
857 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
858 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
859 |march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \
860 march=*: -mhard-float}"
861
862 /* A spec condition that matches 32-bit options. It only works if
863 MIPS_ISA_LEVEL_SPEC has been applied. */
864
865 #define MIPS_32BIT_OPTION_SPEC \
866 "mips1|mips2|mips32*|mgp32"
867
868 /* A spec condition that matches architectures should be targeted with
869 o32 FPXX for compatibility reasons. */
870 #define MIPS_FPXX_OPTION_SPEC \
871 "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \
872 mips64|mips64r2|mips64r3|mips64r5"
873
874 /* Infer a -msynci setting from a -mips argument, on the assumption that
875 -msynci is desired where possible. */
876 #define MIPS_ISA_SYNCI_SPEC \
877 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \
878 |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}"
879
880 /* Infer a -mnan=2008 setting from a -mips argument. */
881 #define MIPS_ISA_NAN2008_SPEC \
882 "%{mnan*:;mips32r6|mips64r6:-mnan=2008;march=m51*: \
883 %{!msoft-float:-mnan=2008}}"
884
885 #if (MIPS_ABI_DEFAULT == ABI_O64 \
886 || MIPS_ABI_DEFAULT == ABI_N32 \
887 || MIPS_ABI_DEFAULT == ABI_64)
888 #define OPT_ARCH64 "mabi=32|mgp32:;"
889 #define OPT_ARCH32 "mabi=32|mgp32"
890 #else
891 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
892 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
893 #endif
894
895 /* Support for a compile-time default CPU, et cetera. The rules are:
896 --with-arch is ignored if -march is specified or a -mips is specified
897 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
898 --with-tune is ignored if -mtune is specified; likewise
899 --with-tune-32 and --with-tune-64.
900 --with-abi is ignored if -mabi is specified.
901 --with-float is ignored if -mhard-float or -msoft-float are
902 specified.
903 --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are
904 specified.
905 --with-nan is ignored if -mnan is specified.
906 --with-fp-32 is ignored if -msoft-float, -msingle-float, -mmsa or -mfp are
907 specified.
908 --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg
909 or -mno-odd-spreg are specified.
910 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
911 specified. */
912 #define OPTION_DEFAULT_SPECS \
913 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
914 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
915 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
916 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
917 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
918 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
919 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
920 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
921 {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \
922 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
923 {"fp_32", "%{" OPT_ARCH32 \
924 ":%{!msoft-float:%{!msingle-float:%{!mfp*:%{!mmsa:-mfp%(VALUE)}}}}}" }, \
925 {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \
926 "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \
927 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
928 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
929 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
930 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \
931 {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \
932 {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" }, \
933 {"compact-branches", "%{!mcompact-branches=*:-mcompact-branches=%(VALUE)}" }, \
934 {"msa", "%{!mmsa:%{!mno-msa:-m%(VALUE)}}" } \
935
936 /* A spec that infers the:
937 -mnan=2008 setting from a -mips argument,
938 -mdsp setting from a -march argument.
939 -mloongson-mmi setting from a -march argument. */
940 #define BASE_DRIVER_SELF_SPECS \
941 MIPS_ISA_NAN2008_SPEC, \
942 MIPS_ASE_DSP_SPEC, \
943 MIPS_ASE_LOONGSON_MMI_SPEC, \
944 MIPS_ASE_LOONGSON_EXT_SPEC, \
945 MIPS_ASE_MSA_SPEC
946
947
948 #define MIPS_ASE_DSP_SPEC \
949 "%{!mno-dsp: \
950 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k* \
951 |march=interaptiv: -mdsp} \
952 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
953
954 #define MIPS_ASE_LOONGSON_MMI_SPEC \
955 "%{!mno-loongson-mmi: \
956 %{march=loongson2e|march=loongson2f|march=loongson3a: -mloongson-mmi}}"
957
958 #define MIPS_ASE_LOONGSON_EXT_SPEC \
959 "%{!mno-loongson-ext: \
960 %{march=loongson3a|march=gs464: -mloongson-ext} \
961 %{march=gs464e|march=gs264e: %{!mno-loongson-ext2: \
962 -mloongson-ext2 -mloongson-ext}}}"
963
964 #define MIPS_ASE_MSA_SPEC \
965 "%{!mno-msa: \
966 %{march=gs264e: -mmsa}}"
967
968 #define DRIVER_SELF_SPECS \
969 MIPS_ISA_LEVEL_SPEC, \
970 BASE_DRIVER_SELF_SPECS
971
972 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
973 && ISA_HAS_COND_TRAP)
974
975 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
976
977 /* True if the ABI can only work with 64-bit integer registers. We
978 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
979 otherwise floating-point registers must also be 64-bit. */
980 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
981
982 /* Likewise for 32-bit regs. */
983 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
984
985 /* True if the file format uses 64-bit symbols. At present, this is
986 only true for n64, which uses 64-bit ELF. */
987 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
988
989 /* True if symbols are 64 bits wide. This is usually determined by
990 the ABI's file format, but it can be overridden by -msym32. Note that
991 overriding the size with -msym32 changes the ABI of relocatable objects,
992 although it doesn't change the ABI of a fully-linked object. */
993 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
994 && Pmode == DImode \
995 && !TARGET_SYM32)
996
997 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
998 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
999 || ISA_MIPS4 \
1000 || ISA_MIPS64 \
1001 || ISA_MIPS64R2 \
1002 || ISA_MIPS64R3 \
1003 || ISA_MIPS64R5 \
1004 || ISA_MIPS64R6)
1005
1006 #define ISA_HAS_JR (mips_isa_rev <= 5)
1007
1008 #define ISA_HAS_DELAY_SLOTS 1
1009
1010 #define ISA_HAS_COMPACT_BRANCHES (mips_isa_rev >= 6)
1011
1012 /* ISA has branch likely instructions (e.g. mips2). */
1013 /* Disable branchlikely for tx39 until compare rewrite. They haven't
1014 been generated up to this point. */
1015 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5)
1016
1017 /* ISA has 32 single-precision registers. */
1018 #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \
1019 && !TARGET_GS464) \
1020 || TARGET_FLOAT64 \
1021 || TARGET_MIPS5900)
1022
1023 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
1024 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
1025 || TARGET_MIPS5400 \
1026 || TARGET_MIPS5500 \
1027 || TARGET_MIPS5900 \
1028 || TARGET_MIPS7000 \
1029 || TARGET_MIPS9000 \
1030 || TARGET_MAD \
1031 || (mips_isa_rev >= 1 \
1032 && mips_isa_rev <= 5)) \
1033 && !TARGET_MIPS16)
1034
1035 /* ISA has a three-operand multiplication instruction. */
1036 #define ISA_HAS_DMUL3 (TARGET_64BIT \
1037 && TARGET_OCTEON \
1038 && !TARGET_MIPS16)
1039
1040 /* ISA has HI and LO registers. */
1041 #define ISA_HAS_HILO (mips_isa_rev <= 5)
1042
1043 /* ISA supports instructions DMULT and DMULTU. */
1044 #define ISA_HAS_DMULT (TARGET_64BIT \
1045 && !TARGET_MIPS5900 \
1046 && mips_isa_rev <= 5)
1047
1048 /* ISA supports instructions MULT and MULTU. */
1049 #define ISA_HAS_MULT (mips_isa_rev <= 5)
1050
1051 /* ISA supports instructions MUL, MULU, MUH, MUHU. */
1052 #define ISA_HAS_R6MUL (mips_isa_rev >= 6)
1053
1054 /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */
1055 #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6)
1056
1057 /* For Loongson, it is preferable to use the Loongson-specific division and
1058 modulo instructions instead of the regular (D)DIV(U) instruction,
1059 because the former are faster and can also have the effect of reducing
1060 code size. */
1061 #define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \
1062 || TARGET_GS464) \
1063 && !TARGET_MIPS16)
1064
1065 /* ISA supports instructions DDIV and DDIVU. */
1066 #define ISA_HAS_DDIV (TARGET_64BIT \
1067 && !TARGET_MIPS5900 \
1068 && !ISA_AVOID_DIV_HILO \
1069 && mips_isa_rev <= 5)
1070
1071 /* ISA supports instructions DIV and DIVU.
1072 This is always true, but the macro is needed for ISA_HAS_<D>DIV
1073 in mips.md. */
1074 #define ISA_HAS_DIV (!ISA_AVOID_DIV_HILO \
1075 && mips_isa_rev <= 5)
1076
1077 /* ISA supports instructions DIV, DIVU, MOD and MODU. */
1078 #define ISA_HAS_R6DIV (mips_isa_rev >= 6)
1079
1080 /* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */
1081 #define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6)
1082
1083 /* ISA has the floating-point conditional move instructions introduced
1084 in mips4. */
1085 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
1086 || (mips_isa_rev >= 1 \
1087 && mips_isa_rev <= 5)) \
1088 && !TARGET_MIPS5500 \
1089 && !TARGET_MIPS16)
1090
1091 /* ISA has the integer conditional move instructions introduced in mips4 and
1092 ST Loongson 2E/2F. */
1093 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
1094 || TARGET_MIPS5900 \
1095 || ISA_HAS_MIPS16E2 \
1096 || TARGET_LOONGSON_2EF)
1097
1098 /* ISA has LDC1 and SDC1. */
1099 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
1100 && !TARGET_MIPS5900 \
1101 && !TARGET_MIPS16)
1102
1103 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
1104 branch on CC, and move (both FP and non-FP) on CC. */
1105 #define ISA_HAS_8CC (ISA_MIPS4 \
1106 || (mips_isa_rev >= 1 \
1107 && mips_isa_rev <= 5))
1108
1109 /* ISA has the FP condition code instructions that store the flag in an
1110 FP register. */
1111 #define ISA_HAS_CCF (mips_isa_rev >= 6)
1112
1113 #define ISA_HAS_SEL (mips_isa_rev >= 6)
1114
1115 /* This is a catch all for other mips4 instructions: indexed load, the
1116 FP madd and msub instructions, and the FP recip and recip sqrt
1117 instructions. Note that this macro should only be used by other
1118 ISA_HAS_* macros. */
1119 #define ISA_HAS_FP4 ((ISA_MIPS4 \
1120 || ISA_MIPS64 \
1121 || (mips_isa_rev >= 2 \
1122 && mips_isa_rev <= 5)) \
1123 && !TARGET_MIPS16)
1124
1125 /* ISA has floating-point indexed load and store instructions
1126 (LWXC1, LDXC1, SWXC1 and SDXC1). */
1127 #define ISA_HAS_LXC1_SXC1 (ISA_HAS_FP4 \
1128 && mips_lxc1_sxc1)
1129
1130 /* ISA has paired-single instructions. */
1131 #define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \
1132 || (mips_isa_rev >= 2 \
1133 && mips_isa_rev <= 5)) \
1134 && !TARGET_OCTEON)
1135
1136 /* ISA has conditional trap instructions. */
1137 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
1138 && !TARGET_MIPS16)
1139
1140 /* ISA has conditional trap with immediate instructions. */
1141 #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \
1142 && mips_isa_rev <= 5 \
1143 && !TARGET_MIPS16)
1144
1145 /* ISA has integer multiply-accumulate instructions, madd and msub. */
1146 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \
1147 && mips_isa_rev <= 5)
1148
1149 /* Integer multiply-accumulate instructions should be generated. */
1150 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
1151
1152 /* ISA has 4 operand fused madd instructions of the form
1153 'd = [+-] (a * b [+-] c)'. */
1154 #define ISA_HAS_FUSED_MADD4 (mips_madd4 \
1155 && (TARGET_MIPS8000 \
1156 || TARGET_GS464 \
1157 || TARGET_GS464E \
1158 || TARGET_GS264E))
1159
1160 /* ISA has 4 operand unfused madd instructions of the form
1161 'd = [+-] (a * b [+-] c)'. */
1162 #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \
1163 && ISA_HAS_FP4 \
1164 && !TARGET_MIPS8000 \
1165 && !TARGET_GS464 \
1166 && !TARGET_GS464E \
1167 && !TARGET_GS264E)
1168
1169 /* ISA has 3 operand r6 fused madd instructions of the form
1170 'c = c [+-] (a * b)'. */
1171 #define ISA_HAS_FUSED_MADDF (mips_isa_rev >= 6)
1172
1173 /* ISA has 3 operand loongson fused madd instructions of the form
1174 'c = [+-] (a * b [+-] c)'. */
1175 #define ISA_HAS_FUSED_MADD3 TARGET_LOONGSON_2EF
1176
1177 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
1178 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
1179 doubles are stored in pairs of FPRs, so for safety's sake, we apply
1180 this restriction to the MIPS IV ISA too. */
1181 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
1182 (((ISA_HAS_FP4 \
1183 && ((MODE) == SFmode \
1184 || ((TARGET_FLOAT64 \
1185 || mips_isa_rev >= 2) \
1186 && (MODE) == DFmode))) \
1187 || (((MODE) == SFmode \
1188 || (MODE) == DFmode) \
1189 && (mips_isa_rev >= 6)) \
1190 || (TARGET_SB1 \
1191 && (MODE) == V2SFmode)) \
1192 && !TARGET_MIPS16)
1193
1194 #define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 \
1195 && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2))
1196
1197 #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5)
1198
1199 #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2)
1200
1201 /* ISA has count leading zeroes/ones instruction (not implemented). */
1202 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
1203
1204 /* ISA has count trailing zeroes/ones instruction. */
1205 #define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2)
1206
1207 /* ISA has three operand multiply instructions that put
1208 the high part in an accumulator: mulhi or mulhiu. */
1209 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
1210 || TARGET_MIPS5500 \
1211 || TARGET_SR71K) \
1212 && !TARGET_MIPS16)
1213
1214 /* ISA has three operand multiply instructions that negate the
1215 result and put the result in an accumulator. */
1216 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
1217 || TARGET_MIPS5500 \
1218 || TARGET_SR71K) \
1219 && !TARGET_MIPS16)
1220
1221 /* ISA has three operand multiply instructions that subtract the
1222 result from a 4th operand and put the result in an accumulator. */
1223 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
1224 || TARGET_MIPS5500 \
1225 || TARGET_SR71K) \
1226 && !TARGET_MIPS16)
1227
1228 /* ISA has three operand multiply instructions that add the result
1229 to a 4th operand and put the result in an accumulator. */
1230 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
1231 || TARGET_MIPS4130 \
1232 || TARGET_MIPS5400 \
1233 || TARGET_MIPS5500 \
1234 || TARGET_SR71K) \
1235 && !TARGET_MIPS16)
1236
1237 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
1238 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
1239 || TARGET_MIPS4130) \
1240 && !TARGET_MIPS16)
1241
1242 /* ISA has the "ror" (rotate right) instructions. */
1243 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
1244 || TARGET_MIPS5400 \
1245 || TARGET_MIPS5500 \
1246 || TARGET_SR71K \
1247 || TARGET_SMARTMIPS) \
1248 && !TARGET_MIPS16)
1249
1250 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1251 64-bit targets also provide DSBH and DSHD. */
1252 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1253
1254 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1255 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1256 || TARGET_LOONGSON_2EF \
1257 || TARGET_MIPS5900 \
1258 || mips_isa_rev >= 1) \
1259 && !TARGET_MIPS16)
1260
1261 /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */
1262 #define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6 \
1263 || ISA_HAS_MIPS16E2)
1264
1265 #define ISA_HAS_FMIN_FMAX (mips_isa_rev >= 6)
1266
1267 /* ISA has data indexed prefetch instructions. This controls use of
1268 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1269 (prefx is a cop1x instruction, so can only be used if FP is
1270 enabled.) */
1271 #define ISA_HAS_PREFETCHX (ISA_HAS_FP4 \
1272 || TARGET_LOONGSON_EXT \
1273 || TARGET_LOONGSON_EXT2)
1274
1275 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1276 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1277 also requires TARGET_DOUBLE_FLOAT. */
1278 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1279
1280 /* ISA includes the MIPS32r2 seb and seh instructions. */
1281 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1282
1283 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1284 #define ISA_HAS_EXT_INS ((mips_isa_rev >= 2 && !TARGET_MIPS16) \
1285 || ISA_HAS_MIPS16E2)
1286
1287 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1288 #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \
1289 && mips_isa_rev >= 2)
1290
1291 /* ISA has lwxs instruction (load w/scaled index address. */
1292 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1293 && !TARGET_MIPS16)
1294
1295 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1296 #define ISA_HAS_LBX (TARGET_OCTEON2)
1297 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1298 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1299 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1300 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1301 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1302 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1303 && TARGET_64BIT)
1304
1305 /* The DSP ASE is available. */
1306 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1307
1308 /* Revision 2 of the DSP ASE is available. */
1309 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1310
1311 /* The MSA ASE is available. */
1312 #define ISA_HAS_MSA (TARGET_MSA && !TARGET_MIPS16)
1313
1314 /* The MIPS16e V2 instructions are available. */
1315 #define ISA_HAS_MIPS16E2 (TARGET_MIPS16 && TARGET_MIPS16E2 \
1316 && !TARGET_64BIT)
1317
1318 /* True if the result of a load is not available to the next instruction.
1319 A nop will then be needed between instructions like "lw $4,..."
1320 and "addiu $4,$4,1". */
1321 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1322 && !TARGET_MIPS3900 \
1323 && !TARGET_MIPS5900 \
1324 && !TARGET_MIPS16 \
1325 && !TARGET_MICROMIPS)
1326
1327 /* Likewise mtc1 and mfc1. */
1328 #define ISA_HAS_XFER_DELAY (mips_isa <= MIPS_ISA_MIPS3 \
1329 && !TARGET_MIPS5900 \
1330 && !TARGET_LOONGSON_2EF)
1331
1332 /* Likewise floating-point comparisons. */
1333 #define ISA_HAS_FCMP_DELAY (mips_isa <= MIPS_ISA_MIPS3 \
1334 && !TARGET_MIPS5900 \
1335 && !TARGET_LOONGSON_2EF)
1336
1337 /* True if mflo and mfhi can be immediately followed by instructions
1338 which write to the HI and LO registers.
1339
1340 According to MIPS specifications, MIPS ISAs I, II, and III need
1341 (at least) two instructions between the reads of HI/LO and
1342 instructions which write them, and later ISAs do not. Contradicting
1343 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1344 the UM for the NEC Vr5000) document needing the instructions between
1345 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1346 MIPS64 and later ISAs to have the interlocks, plus any specific
1347 earlier-ISA CPUs for which CPU documentation declares that the
1348 instructions are really interlocked. */
1349 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1350 || TARGET_MIPS5500 \
1351 || TARGET_MIPS5900 \
1352 || TARGET_LOONGSON_2EF)
1353
1354 /* ISA includes synci, jr.hb and jalr.hb. */
1355 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1356
1357 /* ISA includes sync. */
1358 #define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900) \
1359 && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2))
1360 #define GENERATE_SYNC \
1361 (target_flags_explicit & MASK_LLSC \
1362 ? TARGET_LLSC && !TARGET_MIPS16 \
1363 : ISA_HAS_SYNC)
1364
1365 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1366 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1367 instructions. */
1368 #define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900 \
1369 && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2))
1370 #define GENERATE_LL_SC \
1371 (target_flags_explicit & MASK_LLSC \
1372 ? TARGET_LLSC && !TARGET_MIPS16 \
1373 : ISA_HAS_LL_SC)
1374
1375 #define ISA_HAS_SWAP (TARGET_XLP)
1376 #define ISA_HAS_LDADD (TARGET_XLP)
1377
1378 /* ISA includes the baddu instruction. */
1379 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1380
1381 /* ISA includes the bbit* instructions. */
1382 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1383
1384 /* ISA includes the cins instruction. */
1385 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1386
1387 /* ISA includes the exts instruction. */
1388 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1389
1390 /* ISA includes the seq and sne instructions. */
1391 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1392
1393 /* ISA includes the pop instruction. */
1394 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1395
1396 #define MIPS16_GP_LOADS (ISA_HAS_MIPS16E2 && !TARGET_64BIT)
1397
1398 /* The CACHE instruction is available in non-MIPS16 code. */
1399 #define TARGET_CACHE_BUILTIN (mips_isa >= MIPS_ISA_MIPS3)
1400
1401 /* The CACHE instruction is available. */
1402 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && (!TARGET_MIPS16 \
1403 || TARGET_MIPS16E2))
1404 \f
1405 /* Tell collect what flags to pass to nm. */
1406 #ifndef NM_FLAGS
1407 #define NM_FLAGS "-Bn"
1408 #endif
1409
1410 \f
1411 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1412 the assembler. It may be overridden by subtargets.
1413
1414 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1415 COFF debugging info. */
1416
1417 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1418 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1419 %{g} %{g0} %{g1} %{g2} %{g3} \
1420 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3}"
1421 #endif
1422
1423 /* FP_ASM_SPEC represents the floating-point options that must be passed
1424 to the assembler when FPXX support exists. Prior to that point the
1425 assembler could accept the options but were not required for
1426 correctness. We only add the options when absolutely necessary
1427 because passing -msoft-float to the assembler will cause it to reject
1428 all hard-float instructions which may require some user code to be
1429 updated. */
1430
1431 #ifdef HAVE_AS_DOT_MODULE
1432 #define FP_ASM_SPEC "\
1433 %{mhard-float} %{msoft-float} \
1434 %{msingle-float} %{mdouble-float}"
1435 #else
1436 #define FP_ASM_SPEC
1437 #endif
1438
1439 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1440 overridden by subtargets. */
1441
1442 #ifndef SUBTARGET_ASM_SPEC
1443 #define SUBTARGET_ASM_SPEC ""
1444 #endif
1445
1446 #undef ASM_SPEC
1447 #define ASM_SPEC "\
1448 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1449 %{mips32*} %{mips64*} \
1450 %{mips16} %{mno-mips16:-no-mips16} \
1451 %{mmicromips} %{mno-micromips} \
1452 %{mips3d} %{mno-mips3d:-no-mips3d} \
1453 %{mdmx} %{mno-mdmx:-no-mdmx} \
1454 %{mdsp} %{mno-dsp} \
1455 %{mdspr2} %{mno-dspr2} \
1456 %{mmcu} %{mno-mcu} \
1457 %{meva} %{mno-eva} \
1458 %{mvirt} %{mno-virt} \
1459 %{mxpa} %{mno-xpa} \
1460 %{mcrc} %{mno-crc} \
1461 %{mginv} %{mno-ginv} \
1462 %{mmsa} %{mno-msa} \
1463 %{mloongson-mmi} %{mno-loongson-mmi} \
1464 %{mloongson-ext} %{mno-loongson-ext} \
1465 %{mloongson-ext2} %{mno-loongson-ext2} \
1466 %{msmartmips} %{mno-smartmips} \
1467 %{mmt} %{mno-mt} \
1468 %{mfix-r5900} %{mno-fix-r5900} \
1469 %{mfix-rm7000} %{mno-fix-rm7000} \
1470 %{mfix-vr4120} %{mfix-vr4130} \
1471 %{mfix-24k} \
1472 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1473 %(subtarget_asm_debugging_spec) \
1474 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1475 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1476 %{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \
1477 %{modd-spreg} %{mno-odd-spreg} \
1478 %{mshared} %{mno-shared} \
1479 %{msym32} %{mno-sym32} \
1480 %{mtune=*}" \
1481 FP_ASM_SPEC "\
1482 %{mmips16e2} \
1483 %(subtarget_asm_spec)"
1484
1485 /* Extra switches sometimes passed to the linker. */
1486
1487 #ifndef LINK_SPEC
1488 #define LINK_SPEC "\
1489 %(endian_spec) \
1490 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1491 %{shared}"
1492 #endif /* LINK_SPEC defined */
1493
1494
1495 /* Specs for the compiler proper */
1496
1497 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1498 overridden by subtargets. */
1499 #ifndef SUBTARGET_CC1_SPEC
1500 #define SUBTARGET_CC1_SPEC ""
1501 #endif
1502
1503 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1504
1505 #undef CC1_SPEC
1506 #define CC1_SPEC "\
1507 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1508 %(subtarget_cc1_spec)"
1509
1510 /* Preprocessor specs. */
1511
1512 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1513 overridden by subtargets. */
1514 #ifndef SUBTARGET_CPP_SPEC
1515 #define SUBTARGET_CPP_SPEC ""
1516 #endif
1517
1518 #define CPP_SPEC "%(subtarget_cpp_spec)"
1519
1520 /* This macro defines names of additional specifications to put in the specs
1521 that can be used in various specifications like CC1_SPEC. Its definition
1522 is an initializer with a subgrouping for each command option.
1523
1524 Each subgrouping contains a string constant, that defines the
1525 specification name, and a string constant that used by the GCC driver
1526 program.
1527
1528 Do not define this macro if it does not need to do anything. */
1529
1530 #define EXTRA_SPECS \
1531 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1532 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1533 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1534 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1535 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1536 { "endian_spec", ENDIAN_SPEC }, \
1537 SUBTARGET_EXTRA_SPECS
1538
1539 #ifndef SUBTARGET_EXTRA_SPECS
1540 #define SUBTARGET_EXTRA_SPECS
1541 #endif
1542 \f
1543 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1544
1545 #ifndef PREFERRED_DEBUGGING_TYPE
1546 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1547 #endif
1548
1549 /* The size of DWARF addresses should be the same as the size of symbols
1550 in the target file format. They shouldn't depend on things like -msym32,
1551 because many DWARF consumers do not allow the mixture of address sizes
1552 that one would then get from linking -msym32 code with -msym64 code.
1553
1554 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1555 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1556 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1557
1558 /* By default, turn on GDB extensions. */
1559 #define DEFAULT_GDB_EXTENSIONS 1
1560
1561 /* Registers may have a prefix which can be ignored when matching
1562 user asm and register definitions. */
1563 #ifndef REGISTER_PREFIX
1564 #define REGISTER_PREFIX "$"
1565 #endif
1566
1567 /* Local compiler-generated symbols must have a prefix that the assembler
1568 understands. By default, this is $, although some targets (e.g.,
1569 NetBSD-ELF) need to override this. */
1570
1571 #ifndef LOCAL_LABEL_PREFIX
1572 #define LOCAL_LABEL_PREFIX "$"
1573 #endif
1574
1575 /* By default on the mips, external symbols do not have an underscore
1576 prepended, but some targets (e.g., NetBSD) require this. */
1577
1578 #ifndef USER_LABEL_PREFIX
1579 #define USER_LABEL_PREFIX ""
1580 #endif
1581
1582 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1583 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1584
1585 /* The DWARF 2 CFA column which tracks the return address. */
1586 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1587
1588 /* Before the prologue, RA lives in r31. */
1589 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
1590
1591 /* Describe how we implement __builtin_eh_return. */
1592 #define EH_RETURN_DATA_REGNO(N) \
1593 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1594
1595 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1596
1597 #define EH_USES(N) mips_eh_uses (N)
1598
1599 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1600 The default for this in 64-bit mode is 8, which causes problems with
1601 SFmode register saves. */
1602 #define DWARF_CIE_DATA_ALIGNMENT -4
1603
1604 /* Correct the offset of automatic variables and arguments. Note that
1605 the MIPS debug format wants all automatic variables and arguments
1606 to be in terms of the virtual frame pointer (stack pointer before
1607 any adjustment in the function), while the MIPS 3.0 linker wants
1608 the frame pointer to be the stack pointer after the initial
1609 adjustment. */
1610
1611 #define DEBUGGER_AUTO_OFFSET(X) \
1612 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1613 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1614 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1615 \f
1616 /* Target machine storage layout */
1617
1618 #define BITS_BIG_ENDIAN 0
1619 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1620 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1621
1622 #define MAX_BITS_PER_WORD 64
1623
1624 /* Width of a word, in units (bytes). */
1625 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1626 #ifndef IN_LIBGCC2
1627 #define MIN_UNITS_PER_WORD 4
1628 #endif
1629
1630 /* Width of a MSA vector register in bytes. */
1631 #define UNITS_PER_MSA_REG 16
1632 /* Width of a MSA vector register in bits. */
1633 #define BITS_PER_MSA_REG (UNITS_PER_MSA_REG * BITS_PER_UNIT)
1634
1635 /* For MIPS, width of a floating point register. */
1636 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1637
1638 /* The number of consecutive floating-point registers needed to store the
1639 largest format supported by the FPU. */
1640 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1641
1642 /* The number of consecutive floating-point registers needed to store the
1643 smallest format supported by the FPU. */
1644 #define MIN_FPRS_PER_FMT \
1645 (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT)
1646
1647 /* The largest size of value that can be held in floating-point
1648 registers and moved with a single instruction. */
1649 #define UNITS_PER_HWFPVALUE \
1650 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1651
1652 /* The largest size of value that can be held in floating-point
1653 registers. */
1654 #define UNITS_PER_FPVALUE \
1655 (TARGET_SOFT_FLOAT_ABI ? 0 \
1656 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1657 : MIPS_LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1658
1659 /* The number of bytes in a double. */
1660 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1661
1662 /* Set the sizes of the core types. */
1663 #define SHORT_TYPE_SIZE 16
1664 #define INT_TYPE_SIZE 32
1665 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1666 #define LONG_LONG_TYPE_SIZE 64
1667
1668 /* LONG_DOUBLE_TYPE_SIZE gets poisoned, so add MIPS_ prefix. */
1669 #define MIPS_LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1670
1671 /* Define the sizes of fixed-point types. */
1672 #define SHORT_FRACT_TYPE_SIZE 8
1673 #define FRACT_TYPE_SIZE 16
1674 #define LONG_FRACT_TYPE_SIZE 32
1675 #define LONG_LONG_FRACT_TYPE_SIZE 64
1676
1677 #define SHORT_ACCUM_TYPE_SIZE 16
1678 #define ACCUM_TYPE_SIZE 32
1679 #define LONG_ACCUM_TYPE_SIZE 64
1680 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1681 doesn't support 128-bit integers for MIPS32 currently. */
1682 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1683
1684 /* long double is not a fixed mode, but the idea is that, if we
1685 support long double, we also want a 128-bit integer type. */
1686 #define MAX_FIXED_MODE_SIZE MIPS_LONG_DOUBLE_TYPE_SIZE
1687
1688 /* Width in bits of a pointer. */
1689 #ifndef POINTER_SIZE
1690 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1691 #endif
1692
1693 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1694 #define PARM_BOUNDARY BITS_PER_WORD
1695
1696 /* Allocation boundary (in *bits*) for the code of a function. */
1697 #define FUNCTION_BOUNDARY 32
1698
1699 /* Alignment of field after `int : 0' in a structure. */
1700 #define EMPTY_FIELD_BOUNDARY 32
1701
1702 /* Every structure's size must be a multiple of this. */
1703 /* 8 is observed right on a DECstation and on riscos 4.02. */
1704 #define STRUCTURE_SIZE_BOUNDARY 8
1705
1706 /* There is no point aligning anything to a rounder boundary than
1707 MIPS_LONG_DOUBLE_TYPE_SIZE, unless under MSA the bigggest alignment is
1708 BITS_PER_MSA_REG. */
1709 #define BIGGEST_ALIGNMENT \
1710 (ISA_HAS_MSA ? BITS_PER_MSA_REG : MIPS_LONG_DOUBLE_TYPE_SIZE)
1711
1712 /* All accesses must be aligned. */
1713 #define STRICT_ALIGNMENT (!ISA_HAS_UNALIGNED_ACCESS)
1714
1715 /* Define this if you wish to imitate the way many other C compilers
1716 handle alignment of bitfields and the structures that contain
1717 them.
1718
1719 The behavior is that the type written for a bit-field (`int',
1720 `short', or other integer type) imposes an alignment for the
1721 entire structure, as if the structure really did contain an
1722 ordinary field of that type. In addition, the bit-field is placed
1723 within the structure so that it would fit within such a field,
1724 not crossing a boundary for it.
1725
1726 Thus, on most machines, a bit-field whose type is written as `int'
1727 would not cross a four-byte boundary, and would force four-byte
1728 alignment for the whole structure. (The alignment used may not
1729 be four bytes; it is controlled by the other alignment
1730 parameters.)
1731
1732 If the macro is defined, its definition should be a C expression;
1733 a nonzero value for the expression enables this behavior. */
1734
1735 #define PCC_BITFIELD_TYPE_MATTERS 1
1736
1737 /* If defined, a C expression to compute the alignment for a static
1738 variable. TYPE is the data type, and ALIGN is the alignment that
1739 the object would ordinarily have. The value of this macro is used
1740 instead of that alignment to align the object.
1741
1742 If this macro is not defined, then ALIGN is used.
1743
1744 One use of this macro is to increase alignment of medium-size
1745 data to make it all fit in fewer cache lines. Another is to
1746 cause character arrays to be word-aligned so that `strcpy' calls
1747 that copy constants to character arrays can be done inline. */
1748
1749 #undef DATA_ALIGNMENT
1750 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1751 ((((ALIGN) < BITS_PER_WORD) \
1752 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1753 || TREE_CODE (TYPE) == UNION_TYPE \
1754 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1755
1756 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1757 character arrays to be word-aligned so that `strcpy' calls that copy
1758 constants to character arrays can be done inline, and 'strcmp' can be
1759 optimised to use word loads. */
1760 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1761 DATA_ALIGNMENT (TYPE, ALIGN)
1762
1763 #define PAD_VARARGS_DOWN \
1764 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1765
1766 /* Define if operations between registers always perform the operation
1767 on the full register even if a narrower mode is specified. */
1768 #define WORD_REGISTER_OPERATIONS 1
1769
1770 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1771 moves. All other references are zero extended. */
1772 #define LOAD_EXTEND_OP(MODE) \
1773 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode || (MODE) == CCEmode) \
1774 ? SIGN_EXTEND : ZERO_EXTEND)
1775
1776 /* Define this macro if it is advisable to hold scalars in registers
1777 in a wider mode than that declared by the program. In such cases,
1778 the value is constrained to be within the bounds of the declared
1779 type, but kept valid in the wider mode. The signedness of the
1780 extension may differ from that of the type. */
1781
1782 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1783 if (GET_MODE_CLASS (MODE) == MODE_INT \
1784 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1785 { \
1786 if ((MODE) == SImode) \
1787 (UNSIGNEDP) = 0; \
1788 (MODE) = Pmode; \
1789 }
1790
1791 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1792 Extensions of pointers to word_mode must be signed. */
1793 #define POINTERS_EXTEND_UNSIGNED false
1794
1795 /* Define if loading short immediate values into registers sign extends. */
1796 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1797
1798 /* The [d]clz instructions have the natural values at 0. */
1799
1800 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1801 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1802 \f
1803 /* Standard register usage. */
1804
1805 /* Number of hardware registers. We have:
1806
1807 - 32 integer registers
1808 - 32 floating point registers
1809 - 8 condition code registers
1810 - 2 accumulator registers (hi and lo)
1811 - 32 registers each for coprocessors 0, 2 and 3
1812 - 4 fake registers:
1813 - ARG_POINTER_REGNUM
1814 - FRAME_POINTER_REGNUM
1815 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1816 - CPRESTORE_SLOT_REGNUM
1817 - 2 dummy entries that were used at various times in the past.
1818 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1819 - 6 DSP control registers */
1820
1821 #define FIRST_PSEUDO_REGISTER 188
1822
1823 /* By default, fix the kernel registers ($26 and $27), the global
1824 pointer ($28) and the stack pointer ($29). This can change
1825 depending on the command-line options.
1826
1827 Regarding coprocessor registers: without evidence to the contrary,
1828 it's best to assume that each coprocessor register has a unique
1829 use. This can be overridden, in, e.g., mips_option_override or
1830 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1831 inappropriate for a particular target. */
1832
1833 #define FIXED_REGISTERS \
1834 { \
1835 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1836 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1837 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1838 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1839 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1840 /* COP0 registers */ \
1841 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1842 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1843 /* COP2 registers */ \
1844 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1845 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1846 /* COP3 registers */ \
1847 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1848 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1849 /* 6 DSP accumulator registers & 6 control registers */ \
1850 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1851 }
1852
1853
1854 /* Set up this array for o32 by default.
1855
1856 Note that we don't mark $31 as a call-clobbered register. The idea is
1857 that it's really the call instructions themselves which clobber $31.
1858 We don't care what the called function does with it afterwards.
1859
1860 This approach makes it easier to implement sibcalls. Unlike normal
1861 calls, sibcalls don't clobber $31, so the register reaches the
1862 called function in tact. EPILOGUE_USES says that $31 is useful
1863 to the called function. */
1864
1865 #define CALL_REALLY_USED_REGISTERS \
1866 { /* General registers. */ \
1867 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1868 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1869 /* Floating-point registers. */ \
1870 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1871 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1872 /* Others. */ \
1873 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1874 /* COP0 registers */ \
1875 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1876 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1877 /* COP2 registers */ \
1878 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1879 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1880 /* COP3 registers */ \
1881 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1882 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1883 /* 6 DSP accumulator registers & 6 control registers */ \
1884 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1885 }
1886
1887 /* Internal macros to classify a register number as to whether it's a
1888 general purpose register, a floating point register, a
1889 multiply/divide register, or a status register. */
1890
1891 #define GP_REG_FIRST 0
1892 #define GP_REG_LAST 31
1893 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1894 #define K0_REG_NUM (GP_REG_FIRST + 26)
1895 #define K1_REG_NUM (GP_REG_FIRST + 27)
1896 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1897
1898 #define FP_REG_FIRST 32
1899 #define FP_REG_LAST 63
1900 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1901
1902 #define MD_REG_FIRST 64
1903 #define MD_REG_LAST 65
1904 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1905
1906 #define MSA_REG_FIRST FP_REG_FIRST
1907 #define MSA_REG_LAST FP_REG_LAST
1908 #define MSA_REG_NUM FP_REG_NUM
1909
1910 /* The DWARF 2 CFA column which tracks the return address from a
1911 signal handler context. This means that to maintain backwards
1912 compatibility, no hard register can be assigned this column if it
1913 would need to be handled by the DWARF unwinder. */
1914 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1915
1916 #define ST_REG_FIRST 67
1917 #define ST_REG_LAST 74
1918 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1919
1920
1921 /* FIXME: renumber. */
1922 #define COP0_REG_FIRST 80
1923 #define COP0_REG_LAST 111
1924 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1925
1926 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1927 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1928 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1929
1930 #define COP2_REG_FIRST 112
1931 #define COP2_REG_LAST 143
1932 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1933
1934 #define COP3_REG_FIRST 144
1935 #define COP3_REG_LAST 175
1936 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1937
1938 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1939 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1940 #define ALL_COP_REG_LAST COP3_REG_LAST
1941 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1942
1943 #define DSP_ACC_REG_FIRST 176
1944 #define DSP_ACC_REG_LAST 181
1945 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1946
1947 #define AT_REGNUM (GP_REG_FIRST + 1)
1948 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1949 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1950
1951 /* A few bitfield locations for the coprocessor registers. */
1952 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1953 the cause register for the EIC interrupt mode. */
1954 #define CAUSE_IPL 10
1955 /* COP1 Enable is at bit 29 of the status register. */
1956 #define SR_COP1 29
1957 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1958 #define SR_IPL 10
1959 /* Interrupt masks start with IM0 at bit 8 to IM7 at bit 15 of the status
1960 register. */
1961 #define SR_IM0 8
1962 /* Exception Level is at bit 1 of the status register. */
1963 #define SR_EXL 1
1964 /* Interrupt Enable is at bit 0 of the status register. */
1965 #define SR_IE 0
1966
1967 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1968 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1969 should be used instead. */
1970 #define FPSW_REGNUM ST_REG_FIRST
1971
1972 #define GP_REG_P(REGNO) \
1973 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1974 #define M16_REG_P(REGNO) \
1975 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1976 #define M16STORE_REG_P(REGNO) \
1977 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1978 #define FP_REG_P(REGNO) \
1979 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1980 #define MD_REG_P(REGNO) \
1981 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1982 #define ST_REG_P(REGNO) \
1983 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1984 #define COP0_REG_P(REGNO) \
1985 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1986 #define COP2_REG_P(REGNO) \
1987 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1988 #define COP3_REG_P(REGNO) \
1989 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1990 #define ALL_COP_REG_P(REGNO) \
1991 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1992 /* Test if REGNO is one of the 6 new DSP accumulators. */
1993 #define DSP_ACC_REG_P(REGNO) \
1994 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1995 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1996 #define ACC_REG_P(REGNO) \
1997 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1998 #define MSA_REG_P(REGNO) \
1999 ((unsigned int) ((int) (REGNO) - MSA_REG_FIRST) < MSA_REG_NUM)
2000
2001 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
2002 #define MSA_REG_RTX_P(X) (REG_P (X) && MSA_REG_P (REGNO (X)))
2003
2004 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
2005 to initialize the mips16 gp pseudo register. */
2006 #define CONST_GP_P(X) \
2007 (GET_CODE (X) == CONST \
2008 && GET_CODE (XEXP (X, 0)) == UNSPEC \
2009 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
2010
2011 /* Return coprocessor number from register number. */
2012
2013 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
2014 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
2015 : COP3_REG_P (REGNO) ? '3' : '?')
2016
2017
2018 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
2019 mips_hard_regno_rename_ok (OLD_REG, NEW_REG)
2020
2021 /* Select a register mode required for caller save of hard regno REGNO. */
2022 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
2023 mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE)
2024
2025 /* Register to use for pushing function arguments. */
2026 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
2027
2028 /* These two registers don't really exist: they get eliminated to either
2029 the stack or hard frame pointer. */
2030 #define ARG_POINTER_REGNUM 77
2031 #define FRAME_POINTER_REGNUM 78
2032
2033 /* $30 is not available on the mips16, so we use $17 as the frame
2034 pointer. */
2035 #define HARD_FRAME_POINTER_REGNUM \
2036 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
2037
2038 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
2039 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
2040
2041 /* Register in which static-chain is passed to a function. */
2042 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
2043
2044 /* Registers used as temporaries in prologue/epilogue code:
2045
2046 - If a MIPS16 PIC function needs access to _gp, it first loads
2047 the value into MIPS16_PIC_TEMP and then copies it to $gp.
2048
2049 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
2050 register. The register must not conflict with MIPS16_PIC_TEMP.
2051
2052 - If we aren't generating MIPS16 code, the prologue can also use
2053 MIPS_PROLOGUE_TEMP2 as a general temporary register.
2054
2055 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
2056 register.
2057
2058 If we're generating MIPS16 code, these registers must come from the
2059 core set of 8. The prologue registers mustn't conflict with any
2060 incoming arguments, the static chain pointer, or the frame pointer.
2061 The epilogue temporary mustn't conflict with the return registers,
2062 the PIC call register ($25), the frame pointer, the EH stack adjustment,
2063 or the EH data registers.
2064
2065 If we're generating interrupt handlers, we use K0 as a temporary register
2066 in prologue/epilogue code. */
2067
2068 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
2069 #define MIPS_PROLOGUE_TEMP_REGNUM \
2070 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
2071 #define MIPS_PROLOGUE_TEMP2_REGNUM \
2072 (TARGET_MIPS16 \
2073 ? (gcc_unreachable (), INVALID_REGNUM) \
2074 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
2075 #define MIPS_EPILOGUE_TEMP_REGNUM \
2076 (cfun->machine->interrupt_handler_p \
2077 ? K0_REG_NUM \
2078 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
2079
2080 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
2081 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
2082 #define MIPS_PROLOGUE_TEMP2(MODE) \
2083 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
2084 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
2085
2086 /* Define this macro if it is as good or better to call a constant
2087 function address than to call an address kept in a register. */
2088 #define NO_FUNCTION_CSE 1
2089
2090 /* We normally use $28 as the global pointer. However, when generating
2091 n32/64 PIC, it is better for leaf functions to use a call-clobbered
2092 register instead. They can then avoid saving and restoring $28
2093 and perhaps avoid using a frame at all.
2094
2095 When a leaf function uses something other than $28, mips_expand_prologue
2096 will modify pic_offset_table_rtx in place. Take the register number
2097 from there after reload. */
2098 #define PIC_OFFSET_TABLE_REGNUM \
2099 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
2100 \f
2101 /* Define the classes of registers for register constraints in the
2102 machine description. Also define ranges of constants.
2103
2104 One of the classes must always be named ALL_REGS and include all hard regs.
2105 If there is more than one class, another class must be named NO_REGS
2106 and contain no registers.
2107
2108 The name GENERAL_REGS must be the name of a class (or an alias for
2109 another name such as ALL_REGS). This is the class of registers
2110 that is allowed by "g" or "r" in a register constraint.
2111 Also, registers outside this class are allocated only when
2112 instructions express preferences for them.
2113
2114 The classes must be numbered in nondecreasing order; that is,
2115 a larger-numbered class must never be contained completely
2116 in a smaller-numbered class.
2117
2118 For any two classes, it is very desirable that there be another
2119 class that represents their union. */
2120
2121 enum reg_class
2122 {
2123 NO_REGS, /* no registers in set */
2124 M16_STORE_REGS, /* microMIPS store registers */
2125 M16_REGS, /* mips16 directly accessible registers */
2126 M16_SP_REGS, /* mips16 + $sp */
2127 T_REG, /* mips16 T register ($24) */
2128 M16_T_REGS, /* mips16 registers plus T register */
2129 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
2130 V1_REG, /* Register $v1 ($3) used for TLS access. */
2131 SPILL_REGS, /* All but $sp and call preserved regs are in here */
2132 LEA_REGS, /* Every GPR except $25 */
2133 GR_REGS, /* integer registers */
2134 FP_REGS, /* floating point registers */
2135 MD0_REG, /* first multiply/divide register */
2136 MD1_REG, /* second multiply/divide register */
2137 MD_REGS, /* multiply/divide registers (hi/lo) */
2138 COP0_REGS, /* generic coprocessor classes */
2139 COP2_REGS,
2140 COP3_REGS,
2141 ST_REGS, /* status registers (fp status) */
2142 DSP_ACC_REGS, /* DSP accumulator registers */
2143 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
2144 FRAME_REGS, /* $arg and $frame */
2145 GR_AND_MD0_REGS, /* union classes */
2146 GR_AND_MD1_REGS,
2147 GR_AND_MD_REGS,
2148 GR_AND_ACC_REGS,
2149 ALL_REGS, /* all registers */
2150 LIM_REG_CLASSES /* max value + 1 */
2151 };
2152
2153 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2154
2155 #define GENERAL_REGS GR_REGS
2156
2157 /* An initializer containing the names of the register classes as C
2158 string constants. These names are used in writing some of the
2159 debugging dumps. */
2160
2161 #define REG_CLASS_NAMES \
2162 { \
2163 "NO_REGS", \
2164 "M16_STORE_REGS", \
2165 "M16_REGS", \
2166 "M16_SP_REGS", \
2167 "T_REG", \
2168 "M16_T_REGS", \
2169 "PIC_FN_ADDR_REG", \
2170 "V1_REG", \
2171 "SPILL_REGS", \
2172 "LEA_REGS", \
2173 "GR_REGS", \
2174 "FP_REGS", \
2175 "MD0_REG", \
2176 "MD1_REG", \
2177 "MD_REGS", \
2178 /* coprocessor registers */ \
2179 "COP0_REGS", \
2180 "COP2_REGS", \
2181 "COP3_REGS", \
2182 "ST_REGS", \
2183 "DSP_ACC_REGS", \
2184 "ACC_REGS", \
2185 "FRAME_REGS", \
2186 "GR_AND_MD0_REGS", \
2187 "GR_AND_MD1_REGS", \
2188 "GR_AND_MD_REGS", \
2189 "GR_AND_ACC_REGS", \
2190 "ALL_REGS" \
2191 }
2192
2193 /* An initializer containing the contents of the register classes,
2194 as integers which are bit masks. The Nth integer specifies the
2195 contents of class N. The way the integer MASK is interpreted is
2196 that register R is in the class if `MASK & (1 << R)' is 1.
2197
2198 When the machine has more than 32 registers, an integer does not
2199 suffice. Then the integers are replaced by sub-initializers,
2200 braced groupings containing several integers. Each
2201 sub-initializer must be suitable as an initializer for the type
2202 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2203
2204 #define REG_CLASS_CONTENTS \
2205 { \
2206 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
2207 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
2208 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
2209 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \
2210 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
2211 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
2212 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
2213 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
2214 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \
2215 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
2216 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
2217 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
2218 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
2219 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
2220 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
2221 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
2222 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
2223 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
2224 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
2225 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
2226 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
2227 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
2228 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
2229 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
2230 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
2231 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
2232 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
2233 }
2234
2235
2236 /* A C expression whose value is a register class containing hard
2237 register REGNO. In general there is more that one such class;
2238 choose a class which is "minimal", meaning that no smaller class
2239 also contains the register. */
2240
2241 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2242
2243 /* A macro whose definition is the name of the class to which a
2244 valid base register must belong. A base register is one used in
2245 an address which is the register value plus a displacement. */
2246
2247 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS)
2248
2249 /* A macro whose definition is the name of the class to which a
2250 valid index register must belong. An index register is one used
2251 in an address where its value is either multiplied by a scale
2252 factor or added to another register (as well as added to a
2253 displacement). */
2254
2255 #define INDEX_REG_CLASS NO_REGS
2256
2257 /* We generally want to put call-clobbered registers ahead of
2258 call-saved ones. (IRA expects this.) */
2259
2260 #define REG_ALLOC_ORDER \
2261 { /* Accumulator registers. When GPRs and accumulators have equal \
2262 cost, we generally prefer to use accumulators. For example, \
2263 a division of multiplication result is better allocated to LO, \
2264 so that we put the MFLO at the point of use instead of at the \
2265 point of definition. It's also needed if we're to take advantage \
2266 of the extra accumulators available with -mdspr2. In some cases, \
2267 it can also help to reduce register pressure. */ \
2268 64, 65,176,177,178,179,180,181, \
2269 /* Call-clobbered GPRs. */ \
2270 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2271 24, 25, 31, \
2272 /* The global pointer. This is call-clobbered for o32 and o64 \
2273 abicalls, call-saved for n32 and n64 abicalls, and a program \
2274 invariant otherwise. Putting it between the call-clobbered \
2275 and call-saved registers should cope with all eventualities. */ \
2276 28, \
2277 /* Call-saved GPRs. */ \
2278 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2279 /* GPRs that can never be exposed to the register allocator. */ \
2280 0, 26, 27, 29, \
2281 /* Call-clobbered FPRs. */ \
2282 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2283 48, 49, 50, 51, \
2284 /* FPRs that are usually call-saved. The odd ones are actually \
2285 call-clobbered for n32, but listing them ahead of the even \
2286 registers might encourage the register allocator to fragment \
2287 the available FPR pairs. We need paired FPRs to store long \
2288 doubles, so it isn't clear that using a different order \
2289 for n32 would be a win. */ \
2290 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2291 /* None of the remaining classes have defined call-saved \
2292 registers. */ \
2293 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2294 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2295 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2296 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2297 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2298 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2299 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2300 182,183,184,185,186,187 \
2301 }
2302
2303 /* True if VALUE is an unsigned 6-bit number. */
2304
2305 #define UIMM6_OPERAND(VALUE) \
2306 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2307
2308 /* True if VALUE is a signed 10-bit number. */
2309
2310 #define IMM10_OPERAND(VALUE) \
2311 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2312
2313 /* True if VALUE is a signed 16-bit number. */
2314
2315 #define SMALL_OPERAND(VALUE) \
2316 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2317
2318 /* True if VALUE is an unsigned 16-bit number. */
2319
2320 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2321 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2322
2323 /* True if VALUE can be loaded into a register using LUI. */
2324
2325 #define LUI_OPERAND(VALUE) \
2326 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2327 || ((unsigned HOST_WIDE_INT) (VALUE) | 0x7fff0000) + 0x10000 == 0)
2328
2329 /* Return a value X with the low 16 bits clear, and such that
2330 VALUE - X is a signed 16-bit value. */
2331
2332 #define CONST_HIGH_PART(VALUE) \
2333 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2334
2335 #define CONST_LOW_PART(VALUE) \
2336 ((VALUE) - CONST_HIGH_PART (VALUE))
2337
2338 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2339 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2340 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2341 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2342 #define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255))
2343
2344 /* The HI and LO registers can only be reloaded via the general
2345 registers. Condition code registers can only be loaded to the
2346 general registers, and from the floating point registers. */
2347
2348 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2349 mips_secondary_reload_class (CLASS, MODE, X, true)
2350 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2351 mips_secondary_reload_class (CLASS, MODE, X, false)
2352
2353 /* Return the maximum number of consecutive registers
2354 needed to represent mode MODE in a register of class CLASS. */
2355
2356 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2357 \f
2358 /* Stack layout; function entry, exit and calling. */
2359
2360 #define STACK_GROWS_DOWNWARD 1
2361
2362 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
2363 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
2364
2365 /* Size of the area allocated in the frame to save the GP. */
2366
2367 #define MIPS_GP_SAVE_AREA_SIZE \
2368 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2369
2370 #define RETURN_ADDR_RTX mips_return_addr
2371
2372 /* Mask off the MIPS16 ISA bit in unwind addresses.
2373
2374 The reason for this is a little subtle. When unwinding a call,
2375 we are given the call's return address, which on most targets
2376 is the address of the following instruction. However, what we
2377 actually want to find is the EH region for the call itself.
2378 The target-independent unwind code therefore searches for "RA - 1".
2379
2380 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2381 RA - 1 is therefore the real (even-valued) start of the return
2382 instruction. EH region labels are usually odd-valued MIPS16 symbols
2383 too, so a search for an even address within a MIPS16 region would
2384 usually work.
2385
2386 However, there is an exception. If the end of an EH region is also
2387 the end of a function, the end label is allowed to be even. This is
2388 necessary because a following non-MIPS16 function may also need EH
2389 information for its first instruction.
2390
2391 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2392 non-ISA-encoded address. This probably isn't ideal, but it is
2393 the traditional (legacy) behavior. It is therefore only safe
2394 to search MIPS EH regions for an _odd-valued_ address.
2395
2396 Masking off the ISA bit means that the target-independent code
2397 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2398 #define MASK_RETURN_ADDR GEN_INT (-2)
2399
2400
2401 /* Similarly, don't use the least-significant bit to tell pointers to
2402 code from vtable index. */
2403
2404 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2405
2406 /* The eliminations to $17 are only used for mips16 code. See the
2407 definition of HARD_FRAME_POINTER_REGNUM. */
2408
2409 #define ELIMINABLE_REGS \
2410 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2411 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2412 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2413 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2414 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2415 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2416
2417 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2418 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2419
2420 /* Allocate stack space for arguments at the beginning of each function. */
2421 #define ACCUMULATE_OUTGOING_ARGS 1
2422
2423 /* The argument pointer always points to the first argument. */
2424 #define FIRST_PARM_OFFSET(FNDECL) 0
2425
2426 /* o32 and o64 reserve stack space for all argument registers. */
2427 #define REG_PARM_STACK_SPACE(FNDECL) \
2428 (TARGET_OLDABI \
2429 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2430 : 0)
2431
2432 /* Define this if it is the responsibility of the caller to
2433 allocate the area reserved for arguments passed in registers.
2434 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2435 of this macro is to determine whether the space is included in
2436 `crtl->outgoing_args_size'. */
2437 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2438
2439 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2440 \f
2441 /* Symbolic macros for the registers used to return integer and floating
2442 point values. */
2443
2444 #define GP_RETURN (GP_REG_FIRST + 2)
2445 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2446
2447 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2448
2449 /* Symbolic macros for the first/last argument registers. */
2450
2451 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2452 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2453 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2454 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2455
2456 /* True if MODE is vector and supported in a MSA vector register. */
2457 #define MSA_SUPPORTED_MODE_P(MODE) \
2458 (ISA_HAS_MSA \
2459 && GET_MODE_SIZE (MODE) == UNITS_PER_MSA_REG \
2460 && (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \
2461 || GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT))
2462
2463 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2464 are used for returning complex double values in soft-float code, so $6 is the
2465 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2466 $gp itself as the temporary. */
2467 #define POST_CALL_TMP_REG \
2468 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2469
2470 /* 1 if N is a possible register number for function argument passing.
2471 We have no FP argument registers when soft-float. Special handling
2472 is required for O32 where only even numbered registers are used for
2473 O32-FPXX and O32-FP64. */
2474
2475 #define FUNCTION_ARG_REGNO_P(N) \
2476 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2477 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2478 && (mips_abi != ABI_32 \
2479 || TARGET_FLOAT32 \
2480 || ((N) % 2 == 0)))) \
2481 && !fixed_regs[N])
2482 \f
2483 /* This structure has to cope with two different argument allocation
2484 schemes. Most MIPS ABIs view the arguments as a structure, of which
2485 the first N words go in registers and the rest go on the stack. If I
2486 < N, the Ith word might go in Ith integer argument register or in a
2487 floating-point register. For these ABIs, we only need to remember
2488 the offset of the current argument into the structure.
2489
2490 The EABI instead allocates the integer and floating-point arguments
2491 separately. The first N words of FP arguments go in FP registers,
2492 the rest go on the stack. Likewise, the first N words of the other
2493 arguments go in integer registers, and the rest go on the stack. We
2494 need to maintain three counts: the number of integer registers used,
2495 the number of floating-point registers used, and the number of words
2496 passed on the stack.
2497
2498 We could keep separate information for the two ABIs (a word count for
2499 the standard ABIs, and three separate counts for the EABI). But it
2500 seems simpler to view the standard ABIs as forms of EABI that do not
2501 allocate floating-point registers.
2502
2503 So for the standard ABIs, the first N words are allocated to integer
2504 registers, and mips_function_arg decides on an argument-by-argument
2505 basis whether that argument should really go in an integer register,
2506 or in a floating-point one. */
2507
2508 typedef struct mips_args {
2509 /* Always true for varargs functions. Otherwise true if at least
2510 one argument has been passed in an integer register. */
2511 int gp_reg_found;
2512
2513 /* The number of arguments seen so far. */
2514 unsigned int arg_number;
2515
2516 /* The number of integer registers used so far. For all ABIs except
2517 EABI, this is the number of words that have been added to the
2518 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2519 unsigned int num_gprs;
2520
2521 /* For EABI, the number of floating-point registers used so far. */
2522 unsigned int num_fprs;
2523
2524 /* The number of words passed on the stack. */
2525 unsigned int stack_words;
2526
2527 /* On the mips16, we need to keep track of which floating point
2528 arguments were passed in general registers, but would have been
2529 passed in the FP regs if this were a 32-bit function, so that we
2530 can move them to the FP regs if we wind up calling a 32-bit
2531 function. We record this information in fp_code, encoded in base
2532 four. A zero digit means no floating point argument, a one digit
2533 means an SFmode argument, and a two digit means a DFmode argument,
2534 and a three digit is not used. The low order digit is the first
2535 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2536 an SFmode argument. ??? A more sophisticated approach will be
2537 needed if MIPS_ABI != ABI_32. */
2538 int fp_code;
2539
2540 /* True if the function has a prototype. */
2541 int prototype;
2542 } CUMULATIVE_ARGS;
2543
2544 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2545 for a call to a function whose data type is FNTYPE.
2546 For a library call, FNTYPE is 0. */
2547
2548 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2549 mips_init_cumulative_args (&CUM, FNTYPE)
2550
2551 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2552 (mips_pad_reg_upward (MODE, TYPE) ? PAD_UPWARD : PAD_DOWNWARD)
2553
2554 /* True if using EABI and varargs can be passed in floating-point
2555 registers. Under these conditions, we need a more complex form
2556 of va_list, which tracks GPR, FPR and stack arguments separately. */
2557 #define EABI_FLOAT_VARARGS_P \
2558 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2559
2560 \f
2561 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2562
2563 /* Treat LOC as a byte offset from the stack pointer and round it up
2564 to the next fully-aligned offset. */
2565 #define MIPS_STACK_ALIGN(LOC) \
2566 (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8))
2567
2568 \f
2569 /* Output assembler code to FILE to increment profiler label # LABELNO
2570 for profiling a function entry. */
2571
2572 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2573
2574 /* The profiler preserves all interesting registers, including $31. */
2575 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2576
2577 /* No mips port has ever used the profiler counter word, so don't emit it
2578 or the label for it. */
2579
2580 #define NO_PROFILE_COUNTERS 1
2581
2582 /* Define this macro if the code for function profiling should come
2583 before the function prologue. Normally, the profiling code comes
2584 after. */
2585
2586 /* #define PROFILE_BEFORE_PROLOGUE */
2587
2588 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2589 the stack pointer does not matter. The value is tested only in
2590 functions that have frame pointers.
2591 No definition is equivalent to always zero. */
2592
2593 #define EXIT_IGNORE_STACK 1
2594
2595 \f
2596 /* Trampolines are a block of code followed by two pointers. */
2597
2598 #define TRAMPOLINE_SIZE \
2599 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2600
2601 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2602 pointers from a single LUI base. */
2603
2604 #define TRAMPOLINE_ALIGNMENT 64
2605
2606 /* mips_trampoline_init calls this library function to flush
2607 program and data caches. */
2608
2609 #ifndef CACHE_FLUSH_FUNC
2610 #define CACHE_FLUSH_FUNC "_flush_cache"
2611 #endif
2612
2613 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2614 /* Flush both caches. We need to flush the data cache in case \
2615 the system has a write-back cache. */ \
2616 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2617 LCT_NORMAL, VOIDmode, ADDR, Pmode, SIZE, Pmode, \
2618 GEN_INT (3), TYPE_MODE (integer_type_node))
2619
2620 \f
2621 /* Addressing modes, and classification of registers for them. */
2622
2623 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2624 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2625 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2626 \f
2627 /* Maximum number of registers that can appear in a valid memory address. */
2628
2629 #define MAX_REGS_PER_ADDRESS 1
2630
2631 /* Check for constness inline but use mips_legitimate_address_p
2632 to check whether a constant really is an address. */
2633
2634 #define CONSTANT_ADDRESS_P(X) \
2635 (CONSTANT_P (X) && memory_address_p (SImode, X))
2636
2637 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2638 'the start of the function that this code is output in'. */
2639
2640 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2641 do { \
2642 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2643 asm_fprintf ((FILE), "%U%s", \
2644 XSTR (XEXP (DECL_RTL (current_function_decl), \
2645 0), 0)); \
2646 else \
2647 asm_fprintf ((FILE), "%U%s", (NAME)); \
2648 } while (0)
2649 \f
2650 /* Flag to mark a function decl symbol that requires a long call. */
2651 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2652 #define SYMBOL_REF_LONG_CALL_P(X) \
2653 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2654
2655 /* This flag marks functions that cannot be lazily bound. */
2656 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2657 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2658 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2659
2660 /* True if we're generating a form of MIPS16 code in which jump tables
2661 are stored in the text section and encoded as 16-bit PC-relative
2662 offsets. This is only possible when general text loads are allowed,
2663 since the table access itself will be an "lh" instruction. If the
2664 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2665 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2666
2667 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2668
2669 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2670
2671 /* Only use short offsets if their range will not overflow. */
2672 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2673 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2674 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2675 : SImode)
2676
2677 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2678
2679 /* Define this as 1 if `char' should by default be signed; else as 0. */
2680 #ifndef DEFAULT_SIGNED_CHAR
2681 #define DEFAULT_SIGNED_CHAR 1
2682 #endif
2683
2684 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2685 we generally don't want to use them for copying arbitrary data.
2686 A single N-word move is usually the same cost as N single-word moves. */
2687 #define MOVE_MAX UNITS_PER_WORD
2688 /* We don't modify it for MSA as it is only used by the classic reload. */
2689 #define MAX_MOVE_MAX 8
2690
2691 /* Define this macro as a C expression which is nonzero if
2692 accessing less than a word of memory (i.e. a `char' or a
2693 `short') is no faster than accessing a word of memory, i.e., if
2694 such access require more than one instruction or if there is no
2695 difference in cost between byte and (aligned) word loads.
2696
2697 On RISC machines, it tends to generate better code to define
2698 this as 1, since it avoids making a QI or HI mode register.
2699
2700 But, generating word accesses for -mips16 is generally bad as shifts
2701 (often extended) would be needed for byte accesses. */
2702 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2703
2704 /* Standard MIPS integer shifts truncate the shift amount to the
2705 width of the shifted operand. However, Loongson MMI shifts
2706 do not truncate the shift amount at all. */
2707 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_MMI)
2708
2709
2710 /* Specify the machine mode that pointers have.
2711 After generation of rtl, the compiler makes no further distinction
2712 between pointers and any other objects of this machine mode. */
2713
2714 #ifndef Pmode
2715 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2716 #endif
2717
2718 /* Give call MEMs SImode since it is the "most permissive" mode
2719 for both 32-bit and 64-bit targets. */
2720
2721 #define FUNCTION_MODE SImode
2722
2723 \f
2724 /* We allocate $fcc registers by hand and can't cope with moves of
2725 CCmode registers to and from pseudos (or memory). */
2726 #define AVOID_CCMODE_COPIES
2727
2728 /* A C expression for the cost of a branch instruction. A value of
2729 1 is the default; other values are interpreted relative to that. */
2730
2731 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2732 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2733
2734 /* The MIPS port has several functions that return an instruction count.
2735 Multiplying the count by this value gives the number of bytes that
2736 the instructions occupy. */
2737 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2738
2739 /* The length of a NOP in bytes. */
2740 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2741
2742 /* If defined, modifies the length assigned to instruction INSN as a
2743 function of the context in which it is used. LENGTH is an lvalue
2744 that contains the initially computed length of the insn and should
2745 be updated with the correct length of the insn. */
2746 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2747 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2748
2749 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2750 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2751 its operands. */
2752 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2753 "%*" OPCODE "%?\t" OPERANDS "%/"
2754
2755 #define MIPS_BRANCH_C(OPCODE, OPERANDS) \
2756 "%*" OPCODE "%:\t" OPERANDS
2757
2758 /* Return an asm string that forces INSN to be treated as an absolute
2759 J or JAL instruction instead of an assembler macro. */
2760 #define MIPS_ABSOLUTE_JUMP(INSN) \
2761 (TARGET_ABICALLS_PIC2 \
2762 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2763 : INSN)
2764
2765 \f
2766 /* Control the assembler format that we output. */
2767
2768 /* Output to assembler file text saying following lines
2769 may contain character constants, extra white space, comments, etc. */
2770
2771 #ifndef ASM_APP_ON
2772 #define ASM_APP_ON " #APP\n"
2773 #endif
2774
2775 /* Output to assembler file text saying following lines
2776 no longer contain unusual constructs. */
2777
2778 #ifndef ASM_APP_OFF
2779 #define ASM_APP_OFF " #NO_APP\n"
2780 #endif
2781
2782 #define REGISTER_NAMES \
2783 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2784 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2785 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2786 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2787 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2788 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2789 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2790 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2791 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2792 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2793 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2794 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2795 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2796 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2797 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2798 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2799 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2800 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2801 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2802 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2803 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2804 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2805 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2806 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2807
2808 /* List the "software" names for each register. Also list the numerical
2809 names for $fp and $sp. */
2810
2811 #define ADDITIONAL_REGISTER_NAMES \
2812 { \
2813 { "$29", 29 + GP_REG_FIRST }, \
2814 { "$30", 30 + GP_REG_FIRST }, \
2815 { "at", 1 + GP_REG_FIRST }, \
2816 { "v0", 2 + GP_REG_FIRST }, \
2817 { "v1", 3 + GP_REG_FIRST }, \
2818 { "a0", 4 + GP_REG_FIRST }, \
2819 { "a1", 5 + GP_REG_FIRST }, \
2820 { "a2", 6 + GP_REG_FIRST }, \
2821 { "a3", 7 + GP_REG_FIRST }, \
2822 { "t0", 8 + GP_REG_FIRST }, \
2823 { "t1", 9 + GP_REG_FIRST }, \
2824 { "t2", 10 + GP_REG_FIRST }, \
2825 { "t3", 11 + GP_REG_FIRST }, \
2826 { "t4", 12 + GP_REG_FIRST }, \
2827 { "t5", 13 + GP_REG_FIRST }, \
2828 { "t6", 14 + GP_REG_FIRST }, \
2829 { "t7", 15 + GP_REG_FIRST }, \
2830 { "s0", 16 + GP_REG_FIRST }, \
2831 { "s1", 17 + GP_REG_FIRST }, \
2832 { "s2", 18 + GP_REG_FIRST }, \
2833 { "s3", 19 + GP_REG_FIRST }, \
2834 { "s4", 20 + GP_REG_FIRST }, \
2835 { "s5", 21 + GP_REG_FIRST }, \
2836 { "s6", 22 + GP_REG_FIRST }, \
2837 { "s7", 23 + GP_REG_FIRST }, \
2838 { "t8", 24 + GP_REG_FIRST }, \
2839 { "t9", 25 + GP_REG_FIRST }, \
2840 { "k0", 26 + GP_REG_FIRST }, \
2841 { "k1", 27 + GP_REG_FIRST }, \
2842 { "gp", 28 + GP_REG_FIRST }, \
2843 { "sp", 29 + GP_REG_FIRST }, \
2844 { "fp", 30 + GP_REG_FIRST }, \
2845 { "ra", 31 + GP_REG_FIRST }, \
2846 { "$w0", 0 + FP_REG_FIRST }, \
2847 { "$w1", 1 + FP_REG_FIRST }, \
2848 { "$w2", 2 + FP_REG_FIRST }, \
2849 { "$w3", 3 + FP_REG_FIRST }, \
2850 { "$w4", 4 + FP_REG_FIRST }, \
2851 { "$w5", 5 + FP_REG_FIRST }, \
2852 { "$w6", 6 + FP_REG_FIRST }, \
2853 { "$w7", 7 + FP_REG_FIRST }, \
2854 { "$w8", 8 + FP_REG_FIRST }, \
2855 { "$w9", 9 + FP_REG_FIRST }, \
2856 { "$w10", 10 + FP_REG_FIRST }, \
2857 { "$w11", 11 + FP_REG_FIRST }, \
2858 { "$w12", 12 + FP_REG_FIRST }, \
2859 { "$w13", 13 + FP_REG_FIRST }, \
2860 { "$w14", 14 + FP_REG_FIRST }, \
2861 { "$w15", 15 + FP_REG_FIRST }, \
2862 { "$w16", 16 + FP_REG_FIRST }, \
2863 { "$w17", 17 + FP_REG_FIRST }, \
2864 { "$w18", 18 + FP_REG_FIRST }, \
2865 { "$w19", 19 + FP_REG_FIRST }, \
2866 { "$w20", 20 + FP_REG_FIRST }, \
2867 { "$w21", 21 + FP_REG_FIRST }, \
2868 { "$w22", 22 + FP_REG_FIRST }, \
2869 { "$w23", 23 + FP_REG_FIRST }, \
2870 { "$w24", 24 + FP_REG_FIRST }, \
2871 { "$w25", 25 + FP_REG_FIRST }, \
2872 { "$w26", 26 + FP_REG_FIRST }, \
2873 { "$w27", 27 + FP_REG_FIRST }, \
2874 { "$w28", 28 + FP_REG_FIRST }, \
2875 { "$w29", 29 + FP_REG_FIRST }, \
2876 { "$w30", 30 + FP_REG_FIRST }, \
2877 { "$w31", 31 + FP_REG_FIRST } \
2878 }
2879
2880 #define DBR_OUTPUT_SEQEND(STREAM) \
2881 do \
2882 { \
2883 /* Undo the effect of '%*'. */ \
2884 mips_pop_asm_switch (&mips_nomacro); \
2885 mips_pop_asm_switch (&mips_noreorder); \
2886 /* Emit a blank line after the delay slot for emphasis. */ \
2887 fputs ("\n", STREAM); \
2888 } \
2889 while (0)
2890
2891 /* The MIPS implementation uses some labels for its own purpose. The
2892 following lists what labels are created, and are all formed by the
2893 pattern $L[a-z].*. The machine independent portion of GCC creates
2894 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2895
2896 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2897 $Lb[0-9]+ Begin blocks for MIPS debug support
2898 $Lc[0-9]+ Label for use in s<xx> operation.
2899 $Le[0-9]+ End blocks for MIPS debug support */
2900
2901 #undef ASM_DECLARE_OBJECT_NAME
2902 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2903 mips_declare_object (STREAM, NAME, "", ":\n")
2904
2905 /* Globalizing directive for a label. */
2906 #define GLOBAL_ASM_OP "\t.globl\t"
2907
2908 /* This says how to define a global common symbol. */
2909
2910 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2911
2912 /* This says how to define a local common symbol (i.e., not visible to
2913 linker). */
2914
2915 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2916 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2917 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2918 #endif
2919
2920 /* This says how to output an external. It would be possible not to
2921 output anything and let undefined symbol become external. However
2922 the assembler uses length information on externals to allocate in
2923 data/sdata bss/sbss, thereby saving exec time. */
2924
2925 #undef ASM_OUTPUT_EXTERNAL
2926 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2927 mips_output_external(STREAM,DECL,NAME)
2928
2929 /* This is how to declare a function name. The actual work of
2930 emitting the label is moved to function_prologue, so that we can
2931 get the line number correctly emitted before the .ent directive,
2932 and after any .file directives. Define as empty so that the function
2933 is not declared before the .ent directive elsewhere. */
2934
2935 #undef ASM_DECLARE_FUNCTION_NAME
2936 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2937
2938 /* This is how to store into the string LABEL
2939 the symbol_ref name of an internal numbered label where
2940 PREFIX is the class of label and NUM is the number within the class.
2941 This is suitable for output with `assemble_name'. */
2942
2943 #undef ASM_GENERATE_INTERNAL_LABEL
2944 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2945 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2946
2947 /* Print debug labels as "foo = ." rather than "foo:" because they should
2948 represent a byte pointer rather than an ISA-encoded address. This is
2949 particularly important for code like:
2950
2951 $LFBxxx = .
2952 .cfi_startproc
2953 ...
2954 .section .gcc_except_table,...
2955 ...
2956 .uleb128 foo-$LFBxxx
2957
2958 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2959 likewise a byte pointer rather than an ISA-encoded address.
2960
2961 At the time of writing, this hook is not used for the function end
2962 label:
2963
2964 $LFExxx:
2965 .end foo
2966
2967 But this doesn't matter, because GAS doesn't treat a pre-.end label
2968 as a MIPS16 one anyway. */
2969
2970 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2971 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2972
2973 /* This is how to output an element of a case-vector that is absolute. */
2974
2975 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2976 fprintf (STREAM, "\t%s\t%sL%d\n", \
2977 ptr_mode == DImode ? ".dword" : ".word", \
2978 LOCAL_LABEL_PREFIX, \
2979 VALUE)
2980
2981 /* This is how to output an element of a case-vector. We can make the
2982 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2983 is supported. */
2984
2985 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2986 do { \
2987 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2988 { \
2989 if (GET_MODE (BODY) == HImode) \
2990 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2991 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2992 else \
2993 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2994 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2995 } \
2996 else if (TARGET_GPWORD) \
2997 fprintf (STREAM, "\t%s\t%sL%d\n", \
2998 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2999 LOCAL_LABEL_PREFIX, VALUE); \
3000 else if (TARGET_RTP_PIC) \
3001 { \
3002 /* Make the entry relative to the start of the function. */ \
3003 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
3004 fprintf (STREAM, "\t%s\t%sL%d-", \
3005 Pmode == DImode ? ".dword" : ".word", \
3006 LOCAL_LABEL_PREFIX, VALUE); \
3007 assemble_name (STREAM, XSTR (fnsym, 0)); \
3008 fprintf (STREAM, "\n"); \
3009 } \
3010 else \
3011 fprintf (STREAM, "\t%s\t%sL%d\n", \
3012 ptr_mode == DImode ? ".dword" : ".word", \
3013 LOCAL_LABEL_PREFIX, VALUE); \
3014 } while (0)
3015
3016 /* Mark inline jump tables as data for the purpose of disassembly. For
3017 simplicity embed the jump table's label number in the local symbol
3018 produced so that multiple jump tables within a single function end
3019 up marked with unique symbols. Retain the alignment setting from
3020 `elfos.h' as we are replacing the definition from there. */
3021
3022 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
3023 #define ASM_OUTPUT_BEFORE_CASE_LABEL(STREAM, PREFIX, NUM, TABLE) \
3024 do \
3025 { \
3026 ASM_OUTPUT_ALIGN ((STREAM), 2); \
3027 if (JUMP_TABLES_IN_TEXT_SECTION) \
3028 mips_set_text_contents_type (STREAM, "__jump_", NUM, FALSE); \
3029 } \
3030 while (0)
3031
3032 /* Reset text marking to code after an inline jump table. Like with
3033 the beginning of a jump table use the label number to keep symbols
3034 unique. */
3035
3036 #define ASM_OUTPUT_CASE_END(STREAM, NUM, TABLE) \
3037 do \
3038 if (JUMP_TABLES_IN_TEXT_SECTION) \
3039 mips_set_text_contents_type (STREAM, "__jend_", NUM, TRUE); \
3040 while (0)
3041
3042 /* This is how to output an assembler line
3043 that says to advance the location counter
3044 to a multiple of 2**LOG bytes. */
3045
3046 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3047 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3048
3049 /* This is how to output an assembler line to advance the location
3050 counter by SIZE bytes. */
3051
3052 #undef ASM_OUTPUT_SKIP
3053 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3054 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3055
3056 /* This is how to output a string. */
3057 #undef ASM_OUTPUT_ASCII
3058 #define ASM_OUTPUT_ASCII mips_output_ascii
3059
3060 \f
3061 /* Default to -G 8 */
3062 #ifndef MIPS_DEFAULT_GVALUE
3063 #define MIPS_DEFAULT_GVALUE 8
3064 #endif
3065
3066 /* Define the strings to put out for each section in the object file. */
3067 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3068 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3069
3070 #undef READONLY_DATA_SECTION_ASM_OP
3071 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3072 \f
3073 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3074 do \
3075 { \
3076 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
3077 TARGET_64BIT ? "daddiu" : "addiu", \
3078 reg_names[STACK_POINTER_REGNUM], \
3079 reg_names[STACK_POINTER_REGNUM], \
3080 TARGET_64BIT ? "sd" : "sw", \
3081 reg_names[REGNO], \
3082 reg_names[STACK_POINTER_REGNUM]); \
3083 } \
3084 while (0)
3085
3086 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3087 do \
3088 { \
3089 mips_push_asm_switch (&mips_noreorder); \
3090 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3091 TARGET_64BIT ? "ld" : "lw", \
3092 reg_names[REGNO], \
3093 reg_names[STACK_POINTER_REGNUM], \
3094 TARGET_64BIT ? "daddu" : "addu", \
3095 reg_names[STACK_POINTER_REGNUM], \
3096 reg_names[STACK_POINTER_REGNUM]); \
3097 mips_pop_asm_switch (&mips_noreorder); \
3098 } \
3099 while (0)
3100
3101 /* How to start an assembler comment.
3102 The leading space is important (the mips native assembler requires it). */
3103 #ifndef ASM_COMMENT_START
3104 #define ASM_COMMENT_START " #"
3105 #endif
3106 \f
3107 #undef SIZE_TYPE
3108 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3109
3110 #undef PTRDIFF_TYPE
3111 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3112
3113 /* The minimum alignment of any expanded block move. */
3114 #define MIPS_MIN_MOVE_MEM_ALIGN 16
3115
3116 /* The maximum number of bytes that can be copied by one iteration of
3117 a cpymemsi loop; see mips_block_move_loop. */
3118 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
3119 (UNITS_PER_WORD * 4)
3120
3121 /* The maximum number of bytes that can be copied by a straight-line
3122 implementation of cpymemsi; see mips_block_move_straight. We want
3123 to make sure that any loop-based implementation will iterate at
3124 least twice. */
3125 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
3126 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
3127
3128 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
3129 values were determined experimentally by benchmarking with CSiBE.
3130 In theory, the call overhead is higher for TARGET_ABICALLS (especially
3131 for o32 where we have to restore $gp afterwards as well as make an
3132 indirect call), but in practice, bumping this up higher for
3133 TARGET_ABICALLS doesn't make much difference to code size. */
3134
3135 #define MIPS_CALL_RATIO 8
3136
3137 /* Any loop-based implementation of cpymemsi will have at least
3138 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
3139 moves, so allow individual copies of fewer elements.
3140
3141 When cpymemsi is not available, use a value approximating
3142 the length of a memcpy call sequence, so that move_by_pieces
3143 will generate inline code if it is shorter than a function call.
3144 Since move_by_pieces_ninsns counts memory-to-memory moves, but
3145 we'll have to generate a load/store pair for each, halve the
3146 value of MIPS_CALL_RATIO to take that into account. */
3147
3148 #define MOVE_RATIO(speed) \
3149 (HAVE_cpymemsi \
3150 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
3151 : MIPS_CALL_RATIO / 2)
3152
3153 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
3154 of the length of a memset call, but use the default otherwise. */
3155
3156 #define CLEAR_RATIO(speed)\
3157 ((speed) ? 15 : MIPS_CALL_RATIO)
3158
3159 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3160 optimizing for size adjust the ratio to account for the overhead of
3161 loading the constant and replicating it across the word. */
3162
3163 #define SET_RATIO(speed) \
3164 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3165 \f
3166 /* Since the bits of the _init and _fini function is spread across
3167 many object files, each potentially with its own GP, we must assume
3168 we need to load our GP. We don't preserve $gp or $ra, since each
3169 init/fini chunk is supposed to initialize $gp, and crti/crtn
3170 already take care of preserving $ra and, when appropriate, $gp. */
3171 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3172 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3173 asm (SECTION_OP "\n\
3174 .set push\n\
3175 .set nomips16\n\
3176 .set noreorder\n\
3177 bal 1f\n\
3178 nop\n\
3179 1: .cpload $31\n\
3180 .set reorder\n\
3181 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3182 jalr $25\n\
3183 .set pop\n\
3184 " TEXT_SECTION_ASM_OP);
3185 #elif (defined _ABIN32 && _MIPS_SIM == _ABIN32)
3186 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3187 asm (SECTION_OP "\n\
3188 .set push\n\
3189 .set nomips16\n\
3190 .set noreorder\n\
3191 bal 1f\n\
3192 nop\n\
3193 1: .set reorder\n\
3194 .cpsetup $31, $2, 1b\n\
3195 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3196 jalr $25\n\
3197 .set pop\n\
3198 " TEXT_SECTION_ASM_OP);
3199 #elif (defined _ABI64 && _MIPS_SIM == _ABI64)
3200 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3201 asm (SECTION_OP "\n\
3202 .set push\n\
3203 .set nomips16\n\
3204 .set noreorder\n\
3205 bal 1f\n\
3206 nop\n\
3207 1: .set reorder\n\
3208 .cpsetup $31, $2, 1b\n\
3209 dla $25, " USER_LABEL_PREFIX #FUNC "\n\
3210 jalr $25\n\
3211 .set pop\n\
3212 " TEXT_SECTION_ASM_OP);
3213 #endif
3214
3215 #ifndef HAVE_AS_TLS
3216 #define HAVE_AS_TLS 0
3217 #endif
3218
3219 #ifndef HAVE_AS_NAN
3220 #define HAVE_AS_NAN 0
3221 #endif
3222
3223 #ifndef USED_FOR_TARGET
3224 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3225 struct mips_asm_switch {
3226 /* The FOO in the description above. */
3227 const char *name;
3228
3229 /* The current block nesting level, or 0 if we aren't in a block. */
3230 int nesting_level;
3231 };
3232
3233 extern const enum reg_class mips_regno_to_class[];
3234 extern const char *current_function_file; /* filename current function is in */
3235 extern int num_source_filenames; /* current .file # */
3236 extern struct mips_asm_switch mips_noreorder;
3237 extern struct mips_asm_switch mips_nomacro;
3238 extern struct mips_asm_switch mips_noat;
3239 extern int mips_dwarf_regno[];
3240 extern bool mips_split_p[];
3241 extern bool mips_split_hi_p[];
3242 extern bool mips_use_pcrel_pool_p[];
3243 extern const char *mips_lo_relocs[];
3244 extern const char *mips_hi_relocs[];
3245 extern enum processor mips_arch; /* which cpu to codegen for */
3246 extern enum processor mips_tune; /* which cpu to schedule for */
3247 extern int mips_isa; /* architectural level */
3248 extern int mips_isa_rev;
3249 extern const struct mips_cpu_info *mips_arch_info;
3250 extern const struct mips_cpu_info *mips_tune_info;
3251 extern unsigned int mips_base_compression_flags;
3252 extern GTY(()) struct target_globals *mips16_globals;
3253 extern GTY(()) struct target_globals *micromips_globals;
3254
3255 /* Information about a function's frame layout. */
3256 struct GTY(()) mips_frame_info {
3257 /* The size of the frame in bytes. */
3258 HOST_WIDE_INT total_size;
3259
3260 /* The number of bytes allocated to variables. */
3261 HOST_WIDE_INT var_size;
3262
3263 /* The number of bytes allocated to outgoing function arguments. */
3264 HOST_WIDE_INT args_size;
3265
3266 /* The number of bytes allocated to the .cprestore slot, or 0 if there
3267 is no such slot. */
3268 HOST_WIDE_INT cprestore_size;
3269
3270 /* Bit X is set if the function saves or restores GPR X. */
3271 unsigned int mask;
3272
3273 /* Likewise FPR X. */
3274 unsigned int fmask;
3275
3276 /* Likewise doubleword accumulator X ($acX). */
3277 unsigned int acc_mask;
3278
3279 /* The number of GPRs, FPRs, doubleword accumulators and COP0
3280 registers saved. */
3281 unsigned int num_gp;
3282 unsigned int num_fp;
3283 unsigned int num_acc;
3284 unsigned int num_cop0_regs;
3285
3286 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
3287 save slots from the top of the frame, or zero if no such slots are
3288 needed. */
3289 HOST_WIDE_INT gp_save_offset;
3290 HOST_WIDE_INT fp_save_offset;
3291 HOST_WIDE_INT acc_save_offset;
3292 HOST_WIDE_INT cop0_save_offset;
3293
3294 /* Likewise, but giving offsets from the bottom of the frame. */
3295 HOST_WIDE_INT gp_sp_offset;
3296 HOST_WIDE_INT fp_sp_offset;
3297 HOST_WIDE_INT acc_sp_offset;
3298 HOST_WIDE_INT cop0_sp_offset;
3299
3300 /* Similar, but the value passed to _mcount. */
3301 HOST_WIDE_INT ra_fp_offset;
3302
3303 /* The offset of arg_pointer_rtx from the bottom of the frame. */
3304 HOST_WIDE_INT arg_pointer_offset;
3305
3306 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
3307 HOST_WIDE_INT hard_frame_pointer_offset;
3308 };
3309
3310 /* Enumeration for masked vectored (VI) and non-masked (EIC) interrupts. */
3311 enum mips_int_mask
3312 {
3313 INT_MASK_EIC = -1,
3314 INT_MASK_SW0 = 0,
3315 INT_MASK_SW1 = 1,
3316 INT_MASK_HW0 = 2,
3317 INT_MASK_HW1 = 3,
3318 INT_MASK_HW2 = 4,
3319 INT_MASK_HW3 = 5,
3320 INT_MASK_HW4 = 6,
3321 INT_MASK_HW5 = 7
3322 };
3323
3324 /* Enumeration to mark the existence of the shadow register set.
3325 SHADOW_SET_INTSTACK indicates a shadow register set with a valid stack
3326 pointer. */
3327 enum mips_shadow_set
3328 {
3329 SHADOW_SET_NO,
3330 SHADOW_SET_YES,
3331 SHADOW_SET_INTSTACK
3332 };
3333
3334 struct GTY(()) machine_function {
3335 /* The next floating-point condition-code register to allocate
3336 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
3337 unsigned int next_fcc;
3338
3339 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
3340 rtx mips16_gp_pseudo_rtx;
3341
3342 /* The number of extra stack bytes taken up by register varargs.
3343 This area is allocated by the callee at the very top of the frame. */
3344 int varargs_size;
3345
3346 /* The current frame information, calculated by mips_compute_frame_info. */
3347 struct mips_frame_info frame;
3348
3349 /* The register to use as the function's global pointer, or INVALID_REGNUM
3350 if the function doesn't need one. */
3351 unsigned int global_pointer;
3352
3353 /* How many instructions it takes to load a label into $AT, or 0 if
3354 this property hasn't yet been calculated. */
3355 unsigned int load_label_num_insns;
3356
3357 /* True if mips_adjust_insn_length should ignore an instruction's
3358 hazard attribute. */
3359 bool ignore_hazard_length_p;
3360
3361 /* True if the whole function is suitable for .set noreorder and
3362 .set nomacro. */
3363 bool all_noreorder_p;
3364
3365 /* True if the function has "inflexible" and "flexible" references
3366 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
3367 and mips_cfun_has_flexible_gp_ref_p for details. */
3368 bool has_inflexible_gp_insn_p;
3369 bool has_flexible_gp_insn_p;
3370
3371 /* True if the function's prologue must load the global pointer
3372 value into pic_offset_table_rtx and store the same value in
3373 the function's cprestore slot (if any). Even if this value
3374 is currently false, we may decide to set it to true later;
3375 see mips_must_initialize_gp_p () for details. */
3376 bool must_initialize_gp_p;
3377
3378 /* True if the current function must restore $gp after any potential
3379 clobber. This value is only meaningful during the first post-epilogue
3380 split_insns pass; see mips_must_initialize_gp_p () for details. */
3381 bool must_restore_gp_when_clobbered_p;
3382
3383 /* True if this is an interrupt handler. */
3384 bool interrupt_handler_p;
3385
3386 /* Records the way in which interrupts should be masked. Only used if
3387 interrupts are not kept masked. */
3388 enum mips_int_mask int_mask;
3389
3390 /* Records if this is an interrupt handler that uses shadow registers. */
3391 enum mips_shadow_set use_shadow_register_set;
3392
3393 /* True if this is an interrupt handler that should keep interrupts
3394 masked. */
3395 bool keep_interrupts_masked_p;
3396
3397 /* True if this is an interrupt handler that should use DERET
3398 instead of ERET. */
3399 bool use_debug_exception_return_p;
3400
3401 /* True if at least one of the formal parameters to a function must be
3402 written to the frame header (probably so its address can be taken). */
3403 bool does_not_use_frame_header;
3404
3405 /* True if none of the functions that are called by this function need
3406 stack space allocated for their arguments. */
3407 bool optimize_call_stack;
3408
3409 /* True if one of the functions calling this function may not allocate
3410 a frame header. */
3411 bool callers_may_not_allocate_frame;
3412
3413 /* True if GCC stored callee saved registers in the frame header. */
3414 bool use_frame_header_for_callee_saved_regs;
3415
3416 /* True if the function should generate hazard barrier return. */
3417 bool use_hazard_barrier_return_p;
3418 };
3419 #endif
3420
3421 /* Enable querying of DFA units. */
3422 #define CPU_UNITS_QUERY 1
3423
3424 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3425 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3426
3427 /* As on most targets, we want the .eh_frame section to be read-only where
3428 possible. And as on most targets, this means two things:
3429
3430 (a) Non-locally-binding pointers must have an indirect encoding,
3431 so that the addresses in the .eh_frame section itself become
3432 locally-binding.
3433
3434 (b) A shared library's .eh_frame section must encode locally-binding
3435 pointers in a relative (relocation-free) form.
3436
3437 However, MIPS has traditionally not allowed directives like:
3438
3439 .long x-.
3440
3441 in cases where "x" is in a different section, or is not defined in the
3442 same assembly file. We are therefore unable to emit the PC-relative
3443 form required by (b) at assembly time.
3444
3445 Fortunately, the linker is able to convert absolute addresses into
3446 PC-relative addresses on our behalf. Unfortunately, only certain
3447 versions of the linker know how to do this for indirect pointers,
3448 and for personality data. We must fall back on using writable
3449 .eh_frame sections for shared libraries if the linker does not
3450 support this feature. */
3451 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3452 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
3453
3454 /* For switching between MIPS16 and non-MIPS16 modes. */
3455 #define SWITCHABLE_TARGET 1
3456
3457 /* Several named MIPS patterns depend on Pmode. These patterns have the
3458 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3459 Add the appropriate suffix to generator function NAME and invoke it
3460 with arguments ARGS. */
3461 #define PMODE_INSN(NAME, ARGS) \
3462 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)
3463
3464 /* If we are *not* using multilibs and the default ABI is not ABI_32 we
3465 need to change these from /lib and /usr/lib. */
3466 #ifndef ENABLE_MULTIARCH
3467 #if MIPS_ABI_DEFAULT == ABI_N32
3468 #define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
3469 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
3470 #elif MIPS_ABI_DEFAULT == ABI_64
3471 #define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
3472 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
3473 #endif
3474 #endif
3475
3476 /* Load store bonding is not supported by micromips and fix_24k. The
3477 performance can be degraded for those targets. Hence, do not bond for
3478 micromips or fix_24k. */
3479 #define ENABLE_LD_ST_PAIRS \
3480 (TARGET_LOAD_STORE_PAIRS \
3481 && (TUNE_P5600 || TUNE_I6400 || TUNE_P6600) \
3482 && !TARGET_MICROMIPS && !TARGET_FIX_24K)
3483
3484 #define NEED_INDICATE_EXEC_STACK 0
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