| blob | b0415087fafc614de7095149040b0a21bfde748c |
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
35 /* MIPS external variables defined in mips.c. */
37 /* comparison type */
43 CMP_MAX /* max comparison type */
44 };
46 /* types of delay slot */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
52 };
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
60 PROCESSOR_DEFAULT,
61 PROCESSOR_R3000,
62 PROCESSOR_R3900,
63 PROCESSOR_R6000,
64 PROCESSOR_R4000,
65 PROCESSOR_R4100,
66 PROCESSOR_R4300,
67 PROCESSOR_R4600,
68 PROCESSOR_R4650,
69 PROCESSOR_R5000,
70 PROCESSOR_R8000,
71 PROCESSOR_R4KC,
72 PROCESSOR_R5KC,
73 PROCESSOR_R20KC
74 };
76 /* Recast the cpu class to be the cpu attribute. */
77 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
79 /* Which ABI to use. These are constants because abi64.h must check their
80 value at preprocessing time.
82 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
83 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
85 #define ABI_32 0
86 #define ABI_N32 1
87 #define ABI_64 2
88 #define ABI_EABI 3
89 #define ABI_O64 4
90 /* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
91 which is not the same as the above EABI (defined by Cygnus,
92 Greenhills, and Toshiba?). MEABI is not yet complete or published,
93 but at this point it looks like N32 as far as calling conventions go,
94 but allows for either 32 or 64 bit registers.
96 Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
97 EABI the legacy EABI. In the end we may end up calling both ABI's
98 EABI but give them different version numbers, but for now I'm going
99 with different names. */
100 #define ABI_MEABI 5
102 /* Whether to emit abicalls code sequences or not. */
105 MIPS_ABICALLS_NO,
106 MIPS_ABICALLS_YES
107 };
109 /* Recast the abicalls class to be the abicalls attribute. */
110 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
112 /* Which type of block move to do (whether or not the last store is
113 split out so it can fill a branch delay slot). */
118 BLOCK_MOVE_LAST /* generate just the last store */
119 };
173 /* Functions to change what output section we are using. */
178 /* Stubs for half-pic support if not OSF/1 reference platform. */
180 #ifndef HALF_PIC_P
181 #define HALF_PIC_P() 0
182 #define HALF_PIC_NUMBER_PTRS 0
183 #define HALF_PIC_NUMBER_REFS 0
184 #define HALF_PIC_ENCODE(DECL)
185 #define HALF_PIC_DECLARE(NAME)
187 #define HALF_PIC_ADDRESS_P(X) 0
188 #define HALF_PIC_PTR(X) X
189 #define HALF_PIC_FINISH(STREAM)
190 #endif
192 /* Macros to silence warnings about numbers being signed in traditional
193 C and unsigned in ISO C when compiled on 32-bit hosts. */
199 \f
200 /* Run-time compilation parameters selecting different hardware subsets. */
202 /* Macros used in the machine description to test the flags. */
204 /* Bits for real switches */
226 #define MASK_NO_CHECK_ZERO_DIV \
228 #define MASK_CHECK_RANGE_DIV \
230 #define MASK_UNINIT_CONST_IN_RODATA \
232 consts in rodata */
234 multiply-add operations. */
236 /* Debug switches, not documented */
248 /* Dummy switches used only in specs */
251 /* r4000 64 bit sizes */
252 #define TARGET_INT64 (target_flags & MASK_INT64)
253 #define TARGET_LONG64 (target_flags & MASK_LONG64)
254 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
255 #define TARGET_64BIT (target_flags & MASK_64BIT)
257 /* Mips vs. GNU linker */
258 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
260 /* Mips vs. GNU assembler */
261 #define TARGET_GAS (target_flags & MASK_GAS)
262 #define TARGET_MIPS_AS (!TARGET_GAS)
264 /* Debug Modes */
265 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
266 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
267 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
268 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
269 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
270 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
271 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
272 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
273 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
274 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
276 /* Reg. Naming in .s ($21 vs. $a0) */
277 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
279 /* Optimize for Sdata/Sbss */
280 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
282 /* print program statistics */
283 #define TARGET_STATS (target_flags & MASK_STATS)
285 /* call memcpy instead of inline code */
286 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
288 /* .abicalls, etc from Pyramid V.4 */
289 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
291 /* OSF pic references to externs */
292 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
294 /* software floating point */
295 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
296 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
298 /* always call through a register */
299 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
301 /* generate embedded PIC code;
302 requires gas. */
303 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
305 /* for embedded systems, optimize for
306 reduced RAM space instead of for
307 fastest code. */
308 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
310 /* always store uninitialized const
311 variables in rodata, requires
312 TARGET_EMBEDDED_DATA. */
313 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
315 /* generate big endian code. */
316 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
318 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
319 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
321 #define TARGET_MAD (target_flags & MASK_MAD)
323 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
325 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
327 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
328 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
330 /* This is true if we must enable the assembly language file switching
331 code. */
333 #define TARGET_FILE_SWITCHING \
334 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
336 /* We must disable the function end stabs when doing the file switching trick,
337 because the Lscope stabs end up in the wrong place, making it impossible
338 to debug the resulting code. */
339 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
341 /* Generate mips16 code */
342 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
344 /* Architecture target defines. */
345 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
346 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
347 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
348 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
349 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
350 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
352 /* Scheduling target defines. */
353 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
354 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
355 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
356 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
357 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
359 /* Macro to define tables used to set the flags.
360 This is a list in braces of pairs in braces,
361 each pair being { "NAME", VALUE }
362 where VALUE is the bits to set or minus the bits to clear.
363 An empty string NAME is used to identify the default VALUE. */
365 #define TARGET_SWITCHES \
366 { \
476 NULL}, \
478 NULL}, \
480 NULL}, \
482 NULL}, \
484 NULL}, \
486 NULL}, \
488 NULL}, \
490 NULL}, \
492 NULL}, \
494 NULL}, \
496 | TARGET_CPU_DEFAULT \
497 | TARGET_ENDIAN_DEFAULT), \
498 NULL}, \
499 }
501 /* Default target_flags if no switches are specified */
503 #ifndef TARGET_DEFAULT
504 #define TARGET_DEFAULT 0
505 #endif
507 #ifndef TARGET_CPU_DEFAULT
508 #define TARGET_CPU_DEFAULT 0
509 #endif
511 #ifndef TARGET_ENDIAN_DEFAULT
512 #ifndef DECSTATION
513 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
514 #else
515 #define TARGET_ENDIAN_DEFAULT 0
516 #endif
517 #endif
519 #ifndef MIPS_ISA_DEFAULT
520 #define MIPS_ISA_DEFAULT 1
521 #endif
523 #ifdef IN_LIBGCC2
524 #undef TARGET_64BIT
525 /* Make this compile time constant for libgcc2 */
526 #ifdef __mips64
527 #define TARGET_64BIT 1
528 #else
529 #define TARGET_64BIT 0
530 #endif
533 #ifndef MULTILIB_ENDIAN_DEFAULT
534 #if TARGET_ENDIAN_DEFAULT == 0
536 #else
538 #endif
539 #endif
541 #ifndef MULTILIB_ISA_DEFAULT
542 # if MIPS_ISA_DEFAULT == 1
544 # else
545 # if MIPS_ISA_DEFAULT == 2
547 # else
548 # if MIPS_ISA_DEFAULT == 3
550 # else
551 # if MIPS_ISA_DEFAULT == 4
553 # else
554 # if MIPS_ISA_DEFAULT == 32
556 # else
557 # if MIPS_ISA_DEFAULT == 64
559 # else
561 # endif
562 # endif
563 # endif
564 # endif
565 # endif
566 # endif
567 #endif
569 #ifndef MULTILIB_DEFAULTS
570 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
571 #endif
573 /* We must pass -EL to the linker by default for little endian embedded
574 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
575 linker will default to using big-endian output files. The OUTPUT_FORMAT
576 line must be in the linker script, otherwise -EB/-EL will not work. */
578 #ifndef ENDIAN_SPEC
579 #if TARGET_ENDIAN_DEFAULT == 0
581 #else
583 #endif
584 #endif
586 /* This macro is similar to `TARGET_SWITCHES' but defines names of
587 command options that have values. Its definition is an
588 initializer with a subgrouping for each command option.
590 Each subgrouping contains a string constant, that defines the
591 fixed part of the option name, and the address of a variable.
592 The variable, type `char *', is set to the variable part of the
593 given option if the fixed part matches. The actual option name
594 is made by appending `-m' to the specified name.
596 Here is an example which defines `-mshort-data-NUMBER'. If the
597 given option is `-mshort-data-512', the variable `m88k_short_data'
598 will be set to the string `"512"'.
600 extern char *m88k_short_data;
601 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
603 #define TARGET_OPTIONS \
604 { \
605 SUBTARGET_TARGET_OPTIONS \
619 NULL}, \
624 }
626 /* This is meant to be redefined in the host dependent files. */
627 #define SUBTARGET_TARGET_OPTIONS
629 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
631 /* Generate three-operand multiply instructions for SImode. */
632 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
633 || mips_isa == 32 \
634 || mips_isa == 64) \
635 && !TARGET_MIPS16)
637 /* Generate three-operand multiply instructions for DImode. */
638 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
639 && !TARGET_MIPS16)
641 /* Macros to decide whether certain features are available or not,
642 depending on the instruction set architecture level. */
644 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
645 #define HAVE_SQRT_P() (mips_isa != 1)
647 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
648 #define ISA_HAS_64BIT_REGS (mips_isa == 3 \
649 || mips_isa == 4 \
650 || mips_isa == 64)
652 /* ISA has branch likely instructions (eg. mips2). */
653 /* Disable branchlikely for tx39 until compare rewrite. They haven't
654 been generated up to this point. */
655 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
658 /* ISA has the conditional move instructions introduced in mips4. */
659 #define ISA_HAS_CONDMOVE (mips_isa == 4 \
660 || mips_isa == 32 \
661 || mips_isa == 64)
663 /* ISA has just the integer condition move instructions (movn,movz) */
664 #define ISA_HAS_INT_CONDMOVE 0
668 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
669 branch on CC, and move (both FP and non-FP) on CC. */
670 #define ISA_HAS_8CC (mips_isa == 4 \
671 || mips_isa == 32 \
672 || mips_isa == 64)
675 /* This is a catch all for the other new mips4 instructions: indexed load and
676 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
677 and the FP recip and recip sqrt instructions */
678 #define ISA_HAS_FP4 (mips_isa == 4 \
679 )
681 /* ISA has conditional trap instructions. */
682 #define ISA_HAS_COND_TRAP (mips_isa >= 2)
684 /* ISA has multiply-accumulate instructions, madd and msub. */
685 #define ISA_HAS_MADD_MSUB (mips_isa == 32 \
686 || mips_isa == 64 \
687 )
689 /* ISA has nmadd and nmsub instructions. */
690 #define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \
691 )
693 /* ISA has count leading zeroes/ones instruction (not implemented). */
694 #define ISA_HAS_CLZ_CLO (mips_isa == 32 \
695 || mips_isa == 64 \
696 )
698 /* ISA has double-word count leading zeroes/ones instruction (not
699 implemented). */
700 #define ISA_HAS_DCLZ_DCLO (mips_isa == 64)
703 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
704 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
705 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
706 target_flags, and -mgp64 sets MASK_64BIT.
708 Setting MASK_64BIT in target_flags will cause gcc to assume that
709 registers are 64 bits wide. int, long and void * will be 32 bit;
710 this may be changed with -mint64 or -mlong64.
712 The gen* programs link code that refers to MASK_64BIT. They don't
713 actually use the information in target_flags; they just refer to
714 it. */
715 \f
716 /* Switch Recognition by gcc.c. Add -G xx support */
718 #undef SWITCH_TAKES_ARG
719 #define SWITCH_TAKES_ARG(CHAR) \
722 /* Sometimes certain combinations of command options do not make sense
723 on a particular target machine. You can define a macro
724 `OVERRIDE_OPTIONS' to take account of this. This macro, if
725 defined, is executed once just after all the command options have
726 been parsed.
728 On the MIPS, it is used to handle -G. We also use it to set up all
729 of the tables referenced in the other macros. */
731 #define OVERRIDE_OPTIONS override_options ()
733 /* Zero or more C statements that may conditionally modify two
734 variables `fixed_regs' and `call_used_regs' (both of type `char
735 []') after they have been initialized from the two preceding
736 macros.
738 This is necessary in case the fixed or call-clobbered registers
739 depend on target flags.
741 You need not define this macro if it has no work to do.
743 If the usage of an entire class of registers depends on the target
744 flags, you may indicate this to GCC by using this macro to modify
745 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
746 the classes which should not be used by GCC. Also define the macro
747 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
748 letter for a class that shouldn't be used.
750 (However, if this class is not included in `GENERAL_REGS' and all
751 of the insn patterns whose constraints permit this class are
752 controlled by target switches, then GCC will automatically avoid
753 using these registers when the target switches are opposed to
754 them.) */
756 #define CONDITIONAL_REGISTER_USAGE \
757 do \
758 { \
759 if (!TARGET_HARD_FLOAT) \
760 { \
761 int regno; \
762 \
763 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
764 fixed_regs[regno] = call_used_regs[regno] = 1; \
765 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
766 fixed_regs[regno] = call_used_regs[regno] = 1; \
767 } \
768 else if (! ISA_HAS_8CC) \
769 { \
770 int regno; \
771 \
772 /* We only have a single condition code register. We \
773 implement this by hiding all the condition code registers, \
775 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
776 fixed_regs[regno] = call_used_regs[regno] = 1; \
777 } \
778 /* In mips16 mode, we permit the $t temporary registers to be used \
779 for reload. We prohibit the unused $s registers, since they \
780 are caller saved, and saving them via a mips16 register would \
782 if (TARGET_MIPS16) \
783 { \
784 fixed_regs[18] = call_used_regs[18] = 1; \
785 fixed_regs[19] = call_used_regs[19] = 1; \
786 fixed_regs[20] = call_used_regs[20] = 1; \
787 fixed_regs[21] = call_used_regs[21] = 1; \
788 fixed_regs[22] = call_used_regs[22] = 1; \
789 fixed_regs[23] = call_used_regs[23] = 1; \
790 fixed_regs[26] = call_used_regs[26] = 1; \
791 fixed_regs[27] = call_used_regs[27] = 1; \
792 fixed_regs[30] = call_used_regs[30] = 1; \
793 } \
794 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
795 } \
796 while (0)
798 /* This is meant to be redefined in the host dependent files. */
799 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
801 /* Show we can debug even without a frame pointer. */
802 #define CAN_DEBUG_WITHOUT_FP
803 \f
804 /* Complain about missing specs and predefines that should be defined in each
805 of the target tm files to override the defaults. This is mostly a place-
806 holder until I can get each of the files updated [mm]. */
808 #if defined(OSF_OS) \
809 || defined(DECSTATION) \
810 || defined(SGI_TARGET) \
811 || defined(MIPS_NEWS) \
812 || defined(MIPS_SYSV) \
813 || defined(MIPS_SVR4) \
814 || defined(MIPS_BSD43)
816 #ifndef CPP_PREDEFINES
818 #endif
820 #ifndef LIB_SPEC
822 #endif
824 #ifndef STARTFILE_SPEC
826 #endif
828 #ifndef MACHINE_TYPE
830 #endif
831 #endif
833 /* Tell collect what flags to pass to nm. */
834 #ifndef NM_FLAGS
836 #endif
838 \f
839 /* Names to predefine in the preprocessor for this target machine. */
841 #ifndef CPP_PREDEFINES
843 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
844 -Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
845 #endif
847 /* Assembler specs. */
849 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
850 than gas. */
853 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
854 %{pipe: %e-pipe is not supported} \
855 %{K} %(subtarget_mips_as_asm_spec)"
857 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
858 rather than gas. It may be overridden by subtargets. */
860 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
862 #endif
864 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
865 assembler. */
867 #define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64} %(abi_gas_asm_spec) %{mabi=32:%{!mips*:-mips1}}"
870 /* We use the o32 abi as default for mips1 and mips2. SGI uses n32/n64 for
871 mips3 and mips4 by default, however, this is unsupported at this point in
872 binutils so we use o64. This should change when n32/n64 is supported. */
876 #ifndef MIPS_ABI_DEFAULT
877 #define MIPS_ABI_DEFAULT ABI_32
878 #endif
880 #if MIPS_ABI_DEFAULT == ABI_32
882 %{!mabi=*:%{mips3|mips4|mips5|mips64:-mabi=o64} %{!mips3:%{!mips4:%{!mips5:%{!mips64:-mabi=32}}}}}"
883 #endif
885 #if MIPS_ABI_DEFAULT == ABI_N32
887 #endif
889 #if MIPS_ABI_DEFAULT == ABI_64
891 #endif
893 #if MIPS_ABI_DEFAULT == ABI_EABI
895 #endif
897 #if MIPS_ABI_DEFAULT == ABI_O64
899 %{mabi=*} \
900 %{!mabi=*:%{mips1|mips2|mips32:-mabi=32} %{!mips1:%{!mips2:%{!mips3:%{!mips32:-mabi=o64}}}}}"
901 #endif
903 #if MIPS_ABI_DEFAULT == ABI_MEABI
905 %{mabi=*} \
906 %{!mabi=*:-mabi=meabi }"
907 #endif
909 #ifndef ABI_GAS_ASM_SPEC
911 #endif
913 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
914 GAS_ASM_SPEC as the default, depending upon the value of
915 TARGET_DEFAULT. */
917 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
918 /* GAS */
921 %{mmips-as: %(mips_as_asm_spec)} \
922 %{!mmips-as: %(gas_asm_spec)}"
927 %{!mgas: %(mips_as_asm_spec)} \
928 %{mgas: %(gas_asm_spec)}"
932 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
933 to the assembler. It may be overridden by subtargets. */
934 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
936 %{noasmopt:-O0} \
937 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
938 #endif
940 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
941 the assembler. It may be overridden by subtargets. */
942 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
944 %{g} %{g0} %{g1} %{g2} %{g3} \
945 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
946 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
947 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
948 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
949 #endif
951 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
952 overridden by subtargets. */
954 #ifndef SUBTARGET_ASM_SPEC
956 #endif
958 /* ASM_SPEC is the set of arguments to pass to the assembler. */
960 #undef ASM_SPEC
962 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\
963 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
964 %(subtarget_asm_optimizing_spec) \
965 %(subtarget_asm_debugging_spec) \
966 %{membedded-pic} \
967 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
968 %(target_asm_spec) \
969 %(subtarget_asm_spec)"
971 /* Specify to run a post-processor, mips-tfile after the assembler
972 has run to stuff the mips debug information into the object file.
973 This is needed because the $#!%^ MIPS assembler provides no way
974 of specifying such information in the assembly file. If we are
975 cross compiling, disable mips-tfile unless the user specifies
976 -mmips-tfile. */
978 #ifndef ASM_FINAL_SPEC
979 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
980 /* GAS */
982 %{mmips-as: %{!mno-mips-tfile: \
984 %{K: -I %b.o~} \
985 %{!K: %{save-temps: -I %b.o~}} \
986 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
987 %{.s:%i} %{!.s:%g.s}}}"
989 #else
990 /* not GAS */
992 %{!mgas: %{!mno-mips-tfile: \
994 %{K: -I %b.o~} \
995 %{!K: %{save-temps: -I %b.o~}} \
996 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
997 %{.s:%i} %{!.s:%g.s}}}"
999 #endif
1002 /* Redefinition of libraries used. Mips doesn't support normal
1003 UNIX style profiling via calling _mcount. It does offer
1004 profiling that samples the PC, so do what we can... */
1006 #ifndef LIB_SPEC
1008 #endif
1010 /* Extra switches sometimes passed to the linker. */
1011 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1012 will interpret it as a -b option. */
1014 #ifndef LINK_SPEC
1016 %(endian_spec) \
1017 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
1018 %{bestGnum} %{shared} %{non_shared}"
1022 /* Specs for the compiler proper */
1024 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1025 overridden by subtargets. */
1026 #ifndef SUBTARGET_CC1_SPEC
1028 #endif
1030 /* Deal with historic options. */
1031 #ifndef CC1_CPU_SPEC
1033 %{!mcpu*: \
1034 %{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
1036 %{m4650:-march=r4650 -mmad -msingle-float \
1038 #endif
1040 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1041 /* Note, we will need to adjust the following if we ever find a MIPS variant
1042 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1043 that show up in this case. */
1045 #ifndef CC1_SPEC
1047 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1048 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
1049 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1050 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1051 %{mips32:-mfp32 -mgp32} \
1052 %{mips64:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1053 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
1054 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
1055 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
1056 %{mgp32: %{mfp64:%emay not use both -mgp32 and -mfp64} %{!mfp32: -mfp32}} \
1057 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1058 %{pic-none: -mno-half-pic} \
1059 %{pic-lib: -mhalf-pic} \
1060 %{pic-extern: -mhalf-pic} \
1061 %{pic-calls: -mhalf-pic} \
1062 %{save-temps: } \
1063 %(subtarget_cc1_spec) \
1064 %(cc1_cpu_spec)"
1065 #endif
1067 /* Preprocessor specs. */
1069 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
1070 be overridden by subtargets. */
1072 #ifndef SUBTARGET_CPP_SIZE_SPEC
1074 %{mlong64:%{!mips1:%{!mips2:%{!mips32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}} \
1076 #endif
1078 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1079 overridden by subtargets. */
1080 #ifndef SUBTARGET_CPP_SPEC
1082 #endif
1084 /* If we're using 64bit longs, then we have to define __LONG_MAX__
1085 correctly. Similarly for 64bit ints and __INT_MAX__. */
1086 #ifndef LONG_MAX_SPEC
1087 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
1089 #else
1091 #endif
1092 #endif
1094 /* Define appropriate macros for fpr register size. */
1095 #ifndef CPP_FPR_SPEC
1096 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_FLOAT64)
1098 #else
1100 #endif
1101 #endif
1103 /* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent
1104 of the source file extension. */
1105 #undef CPLUSPLUS_CPP_SPEC
1107 -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
1108 %(cpp) \
1109 "
1110 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
1112 #ifndef CPP_SPEC
1114 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
1115 %{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
1116 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \
1117 %(subtarget_cpp_size_spec) \
1118 %{mips3:-U__mips -D__mips=3 -D__mips64} \
1119 %{mips4:-U__mips -D__mips=4 -D__mips64} \
1120 %{mips32:-U__mips -D__mips=32} \
1121 %{mips64:-U__mips -D__mips=64 -D__mips64} \
1122 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
1123 %{mfp32:-D__mips_fpr=32} %{mfp64:-D__mips_fpr=64} %{!mfp32: %{!mfp64: %{mgp32:-D__mips_fpr=32} %{!mgp32: %(cpp_fpr_spec)}}} \
1124 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
1125 %{m4650:%{!msoft-float:-D__mips_single_float}} \
1126 %{msoft-float:-D__mips_soft_float} \
1127 %{mabi=eabi:-D__mips_eabi} \
1128 %{mips16:%{!mno-mips16:-D__mips16}} \
1129 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
1130 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
1131 %(long_max_spec) \
1132 %(subtarget_cpp_spec) "
1133 #endif
1135 /* This macro defines names of additional specifications to put in the specs
1136 that can be used in various specifications like CC1_SPEC. Its definition
1137 is an initializer with a subgrouping for each command option.
1139 Each subgrouping contains a string constant, that defines the
1140 specification name, and a string constant that used by the GNU CC driver
1141 program.
1143 Do not define this macro if it does not need to do anything. */
1145 #define EXTRA_SPECS \
1161 SUBTARGET_EXTRA_SPECS
1163 #ifndef SUBTARGET_EXTRA_SPECS
1164 #define SUBTARGET_EXTRA_SPECS
1165 #endif
1167 /* If defined, this macro is an additional prefix to try after
1168 `STANDARD_EXEC_PREFIX'. */
1170 #ifndef MD_EXEC_PREFIX
1172 #endif
1174 #ifndef MD_STARTFILE_PREFIX
1176 #endif
1178 \f
1179 /* Print subsidiary information on the compiler version in use. */
1183 #ifndef MACHINE_TYPE
1185 #endif
1187 #ifndef TARGET_VERSION_INTERNAL
1188 #define TARGET_VERSION_INTERNAL(STREAM) \
1190 #endif
1192 #ifndef TARGET_VERSION
1193 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1194 #endif
1196 \f
1202 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1203 #endif
1205 /* By default, turn on GDB extensions. */
1206 #define DEFAULT_GDB_EXTENSIONS 1
1208 /* If we are passing smuggling stabs through the MIPS ECOFF object
1209 format, put a comment in front of the .stab<x> operation so
1210 that the MIPS assembler does not choke. The mips-tfile program
1211 will correctly put the stab into the object file. */
1217 /* Local compiler-generated symbols must have a prefix that the assembler
1218 understands. By default, this is $, although some targets (e.g.,
1219 NetBSD-ELF) need to override this. */
1221 #ifndef LOCAL_LABEL_PREFIX
1223 #endif
1225 /* By default on the mips, external symbols do not have an underscore
1226 prepended, but some targets (e.g., NetBSD) require this. */
1228 #ifndef USER_LABEL_PREFIX
1230 #endif
1232 /* Forward references to tags are allowed. */
1233 #define SDB_ALLOW_FORWARD_REFERENCES
1235 /* Unknown tags are also allowed. */
1236 #define SDB_ALLOW_UNKNOWN_REFERENCES
1238 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1239 since the length can run past this up to a continuation point. */
1240 #undef DBX_CONTIN_LENGTH
1241 #define DBX_CONTIN_LENGTH 1500
1243 /* How to renumber registers for dbx and gdb. */
1244 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1246 /* The mapping from gcc register number to DWARF 2 CFA column number.
1247 This mapping does not allow for tracking register 0, since SGI's broken
1248 dwarf reader thinks column 0 is used for the frame address, but since
1249 register 0 is fixed this is not a problem. */
1250 #define DWARF_FRAME_REGNUM(REG) \
1251 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1253 /* The DWARF 2 CFA column which tracks the return address. */
1254 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1256 /* Before the prologue, RA lives in r31. */
1257 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1259 /* Describe how we implement __builtin_eh_return. */
1260 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1261 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1263 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1264 The default for this in 64-bit mode is 8, which causes problems with
1265 SFmode register saves. */
1266 #define DWARF_CIE_DATA_ALIGNMENT 4
1268 /* Overrides for the COFF debug format. */
1269 #define PUT_SDB_SCL(a) \
1270 do { \
1271 extern FILE *asm_out_text_file; \
1273 } while (0)
1275 #define PUT_SDB_INT_VAL(a) \
1276 do { \
1277 extern FILE *asm_out_text_file; \
1279 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1281 } while (0)
1283 #define PUT_SDB_VAL(a) \
1284 do { \
1285 extern FILE *asm_out_text_file; \
1287 output_addr_const (asm_out_text_file, (a)); \
1289 } while (0)
1291 #define PUT_SDB_DEF(a) \
1292 do { \
1293 extern FILE *asm_out_text_file; \
1296 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1298 } while (0)
1300 #define PUT_SDB_PLAIN_DEF(a) \
1301 do { \
1302 extern FILE *asm_out_text_file; \
1305 } while (0)
1307 #define PUT_SDB_ENDEF \
1308 do { \
1309 extern FILE *asm_out_text_file; \
1311 } while (0)
1313 #define PUT_SDB_TYPE(a) \
1314 do { \
1315 extern FILE *asm_out_text_file; \
1317 } while (0)
1319 #define PUT_SDB_SIZE(a) \
1320 do { \
1321 extern FILE *asm_out_text_file; \
1323 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1325 } while (0)
1327 #define PUT_SDB_DIM(a) \
1328 do { \
1329 extern FILE *asm_out_text_file; \
1331 } while (0)
1333 #ifndef PUT_SDB_START_DIM
1334 #define PUT_SDB_START_DIM \
1335 do { \
1336 extern FILE *asm_out_text_file; \
1338 } while (0)
1339 #endif
1341 #ifndef PUT_SDB_NEXT_DIM
1342 #define PUT_SDB_NEXT_DIM(a) \
1343 do { \
1344 extern FILE *asm_out_text_file; \
1346 } while (0)
1347 #endif
1349 #ifndef PUT_SDB_LAST_DIM
1350 #define PUT_SDB_LAST_DIM(a) \
1351 do { \
1352 extern FILE *asm_out_text_file; \
1354 } while (0)
1355 #endif
1357 #define PUT_SDB_TAG(a) \
1358 do { \
1359 extern FILE *asm_out_text_file; \
1361 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1363 } while (0)
1365 /* For block start and end, we create labels, so that
1366 later we can figure out where the correct offset is.
1367 The normal .ent/.end serve well enough for functions,
1368 so those are just commented out. */
1370 #define PUT_SDB_BLOCK_START(LINE) \
1371 do { \
1372 extern FILE *asm_out_text_file; \
1373 fprintf (asm_out_text_file, \
1375 LOCAL_LABEL_PREFIX, \
1376 sdb_label_count, \
1378 LOCAL_LABEL_PREFIX, \
1379 sdb_label_count, \
1380 (LINE)); \
1381 sdb_label_count++; \
1382 } while (0)
1384 #define PUT_SDB_BLOCK_END(LINE) \
1385 do { \
1386 extern FILE *asm_out_text_file; \
1387 fprintf (asm_out_text_file, \
1389 LOCAL_LABEL_PREFIX, \
1390 sdb_label_count, \
1392 LOCAL_LABEL_PREFIX, \
1393 sdb_label_count, \
1394 (LINE)); \
1395 sdb_label_count++; \
1396 } while (0)
1398 #define PUT_SDB_FUNCTION_START(LINE)
1400 #define PUT_SDB_FUNCTION_END(LINE) \
1401 do { \
1402 extern FILE *asm_out_text_file; \
1403 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1404 } while (0)
1406 #define PUT_SDB_EPILOGUE_END(NAME)
1408 #define PUT_SDB_SRC_FILE(FILENAME) \
1409 do { \
1410 extern FILE *asm_out_text_file; \
1411 output_file_directive (asm_out_text_file, (FILENAME)); \
1412 } while (0)
1414 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1417 /* Correct the offset of automatic variables and arguments. Note that
1418 the MIPS debug format wants all automatic variables and arguments
1419 to be in terms of the virtual frame pointer (stack pointer before
1420 any adjustment in the function), while the MIPS 3.0 linker wants
1421 the frame pointer to be the stack pointer after the initial
1422 adjustment. */
1424 #define DEBUGGER_AUTO_OFFSET(X) \
1425 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1426 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1427 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1429 /* Tell collect that the object format is ECOFF */
1430 #ifndef OBJECT_FORMAT_ROSE
1433 #endif
1434 \f
1435 /* Target machine storage layout */
1437 /* Define in order to support both big and little endian float formats
1438 in the same gcc binary. */
1439 #define REAL_ARITHMETIC
1441 /* Define this if most significant bit is lowest numbered
1442 in instructions that operate on numbered bit-fields.
1443 */
1444 #define BITS_BIG_ENDIAN 0
1446 /* Define this if most significant byte of a word is the lowest numbered. */
1447 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1449 /* Define this if most significant word of a multiword number is the lowest. */
1450 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1452 /* Define this to set the endianness to use in libgcc2.c, which can
1453 not depend on target_flags. */
1454 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1455 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1456 #else
1457 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1458 #endif
1460 /* Number of bits in an addressable storage unit */
1461 #define BITS_PER_UNIT 8
1463 /* Width in bits of a "word", which is the contents of a machine register.
1464 Note that this is not necessarily the width of data type `int';
1465 if using 16-bit ints on a 68000, this would still be 32.
1466 But on a machine with 16-bit registers, this would be 16. */
1467 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1468 #define MAX_BITS_PER_WORD 64
1470 /* Width of a word, in units (bytes). */
1471 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1472 #define MIN_UNITS_PER_WORD 4
1474 /* For MIPS, width of a floating point register. */
1475 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1477 /* A C expression for the size in bits of the type `int' on the
1478 target machine. If you don't define this, the default is one
1479 word. */
1480 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1481 #define MAX_INT_TYPE_SIZE 64
1483 /* Tell the preprocessor the maximum size of wchar_t. */
1484 #ifndef MAX_WCHAR_TYPE_SIZE
1485 #ifndef WCHAR_TYPE_SIZE
1486 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1487 #endif
1488 #endif
1490 /* A C expression for the size in bits of the type `short' on the
1491 target machine. If you don't define this, the default is half a
1492 word. (If this would be less than one storage unit, it is
1493 rounded up to one unit.) */
1494 #define SHORT_TYPE_SIZE 16
1496 /* A C expression for the size in bits of the type `long' on the
1497 target machine. If you don't define this, the default is one
1498 word. */
1499 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1500 #define MAX_LONG_TYPE_SIZE 64
1502 /* A C expression for the size in bits of the type `long long' on the
1503 target machine. If you don't define this, the default is two
1504 words. */
1505 #define LONG_LONG_TYPE_SIZE 64
1507 /* A C expression for the size in bits of the type `char' on the
1508 target machine. If you don't define this, the default is one
1509 quarter of a word. (If this would be less than one storage unit,
1510 it is rounded up to one unit.) */
1511 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1513 /* A C expression for the size in bits of the type `float' on the
1514 target machine. If you don't define this, the default is one
1515 word. */
1516 #define FLOAT_TYPE_SIZE 32
1518 /* A C expression for the size in bits of the type `double' on the
1519 target machine. If you don't define this, the default is two
1520 words. */
1521 #define DOUBLE_TYPE_SIZE 64
1523 /* A C expression for the size in bits of the type `long double' on
1524 the target machine. If you don't define this, the default is two
1525 words. */
1526 #define LONG_DOUBLE_TYPE_SIZE 64
1528 /* Width in bits of a pointer.
1529 See also the macro `Pmode' defined below. */
1530 #ifndef POINTER_SIZE
1531 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1532 #endif
1534 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1535 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1537 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1538 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1540 /* Allocation boundary (in *bits*) for the code of a function. */
1541 #define FUNCTION_BOUNDARY 32
1543 /* Alignment of field after `int : 0' in a structure. */
1544 #define EMPTY_FIELD_BOUNDARY 32
1546 /* Every structure's size must be a multiple of this. */
1547 /* 8 is observed right on a DECstation and on riscos 4.02. */
1548 #define STRUCTURE_SIZE_BOUNDARY 8
1550 /* There is no point aligning anything to a rounder boundary than this. */
1551 #define BIGGEST_ALIGNMENT 64
1553 /* Set this nonzero if move instructions will actually fail to work
1554 when given unaligned data. */
1555 #define STRICT_ALIGNMENT 1
1557 /* Define this if you wish to imitate the way many other C compilers
1558 handle alignment of bitfields and the structures that contain
1559 them.
1561 The behavior is that the type written for a bitfield (`int',
1562 `short', or other integer type) imposes an alignment for the
1563 entire structure, as if the structure really did contain an
1564 ordinary field of that type. In addition, the bitfield is placed
1565 within the structure so that it would fit within such a field,
1566 not crossing a boundary for it.
1568 Thus, on most machines, a bitfield whose type is written as `int'
1569 would not cross a four-byte boundary, and would force four-byte
1570 alignment for the whole structure. (The alignment used may not
1571 be four bytes; it is controlled by the other alignment
1572 parameters.)
1574 If the macro is defined, its definition should be a C expression;
1575 a nonzero value for the expression enables this behavior. */
1577 #define PCC_BITFIELD_TYPE_MATTERS 1
1579 /* If defined, a C expression to compute the alignment given to a
1580 constant that is being placed in memory. CONSTANT is the constant
1581 and ALIGN is the alignment that the object would ordinarily have.
1582 The value of this macro is used instead of that alignment to align
1583 the object.
1585 If this macro is not defined, then ALIGN is used.
1587 The typical use of this macro is to increase alignment for string
1588 constants to be word aligned so that `strcpy' calls that copy
1589 constants can be done inline. */
1591 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1592 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1593 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1595 /* If defined, a C expression to compute the alignment for a static
1596 variable. TYPE is the data type, and ALIGN is the alignment that
1597 the object would ordinarily have. The value of this macro is used
1598 instead of that alignment to align the object.
1600 If this macro is not defined, then ALIGN is used.
1602 One use of this macro is to increase alignment of medium-size
1603 data to make it all fit in fewer cache lines. Another is to
1604 cause character arrays to be word-aligned so that `strcpy' calls
1605 that copy constants to character arrays can be done inline. */
1607 #undef DATA_ALIGNMENT
1608 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1609 ((((ALIGN) < BITS_PER_WORD) \
1610 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1611 || TREE_CODE (TYPE) == UNION_TYPE \
1612 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1615 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1617 #define PAD_VARARGS_DOWN (TARGET_64BIT \
1618 || mips_abi == ABI_MEABI \
1619 ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1621 /* Define this macro if an argument declared as `char' or `short' in a
1622 prototype should actually be passed as an `int'. In addition to
1623 avoiding errors in certain cases of mismatch, it also makes for
1624 better code on certain machines. */
1626 #define PROMOTE_PROTOTYPES 1
1628 /* Define if operations between registers always perform the operation
1629 on the full register even if a narrower mode is specified. */
1630 #define WORD_REGISTER_OPERATIONS
1632 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1633 will either zero-extend or sign-extend. The value of this macro should
1634 be the code that says which one of the two operations is implicitly
1635 done, NIL if none.
1637 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1638 moves. All other referces are zero extended. */
1639 #define LOAD_EXTEND_OP(MODE) \
1640 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1641 ? SIGN_EXTEND : ZERO_EXTEND)
1643 /* Define this macro if it is advisable to hold scalars in registers
1644 in a wider mode than that declared by the program. In such cases,
1645 the value is constrained to be within the bounds of the declared
1646 type, but kept valid in the wider mode. The signedness of the
1647 extension may differ from that of the type.
1649 We promote any value smaller than SImode up to SImode. We don't
1650 want to promote to DImode when in 64 bit mode, because that would
1651 prevent us from using the faster SImode multiply and divide
1652 instructions. */
1654 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1655 if (GET_MODE_CLASS (MODE) == MODE_INT \
1656 && GET_MODE_SIZE (MODE) < 4) \
1657 (MODE) = SImode;
1659 /* Define this if function arguments should also be promoted using the above
1660 procedure. */
1662 #define PROMOTE_FUNCTION_ARGS
1664 /* Likewise, if the function return value is promoted. */
1666 #define PROMOTE_FUNCTION_RETURN
1667 \f
1668 /* Standard register usage. */
1670 /* Number of actual hardware registers.
1671 The hardware registers are assigned numbers for the compiler
1672 from 0 to just below FIRST_PSEUDO_REGISTER.
1673 All registers that the compiler knows about must be given numbers,
1674 even those that are not normally considered general registers.
1676 On the Mips, we have 32 integer registers, 32 floating point
1677 registers, 8 condition code registers, and the special registers
1678 hi, lo, hilo, and rap. The 8 condition code registers are only
1679 used if mips_isa >= 4. The hilo register is only used in 64 bit
1680 mode. It represents a 64 bit value stored as two 32 bit values in
1681 the hi and lo registers; this is the result of the mult
1682 instruction. rap is a pointer to the stack where the return
1683 address reg ($31) was stored. This is needed for C++ exception
1684 handling. */
1686 #define FIRST_PSEUDO_REGISTER 76
1688 /* 1 for registers that have pervasive standard uses
1689 and are not available for the register allocator.
1691 On the MIPS, see conventions, page D-2 */
1693 #define FIXED_REGISTERS \
1694 { \
1695 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1696 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1697 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1698 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1699 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1700 }
1703 /* 1 for registers not available across function calls.
1704 These must include the FIXED_REGISTERS and also any
1705 registers that can be used without being saved.
1706 The latter must include the registers where values are returned
1707 and the register where structure-value addresses are passed.
1708 Aside from that, you can include as many other registers as you like. */
1710 #define CALL_USED_REGISTERS \
1711 { \
1712 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1713 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1714 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1715 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1716 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1717 }
1719 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1720 problem which makes CALL_USED_REGISTERS *always* include
1721 all the FIXED_REGISTERS. Until this problem has been
1722 resolved this macro can be used to overcome this situation.
1723 In particular, block_propagate() requires this list
1724 be acurate, or we can remove registers which should be live.
1725 This macro is used in regs_invalidated_by_call. */
1728 #define CALL_REALLY_USED_REGISTERS \
1730 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1731 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \
1733 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1734 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1736 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1737 }
1739 /* Internal macros to classify a register number as to whether it's a
1740 general purpose register, a floating point register, a
1741 multiply/divide register, or a status register. */
1743 #define GP_REG_FIRST 0
1744 #define GP_REG_LAST 31
1745 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1746 #define GP_DBX_FIRST 0
1748 #define FP_REG_FIRST 32
1749 #define FP_REG_LAST 63
1750 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1751 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1753 #define MD_REG_FIRST 64
1754 #define MD_REG_LAST 66
1755 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1757 #define ST_REG_FIRST 67
1758 #define ST_REG_LAST 74
1759 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1761 #define RAP_REG_NUM 75
1763 #define AT_REGNUM (GP_REG_FIRST + 1)
1764 #define HI_REGNUM (MD_REG_FIRST + 0)
1765 #define LO_REGNUM (MD_REG_FIRST + 1)
1766 #define HILO_REGNUM (MD_REG_FIRST + 2)
1768 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1769 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1770 should be used instead. */
1771 #define FPSW_REGNUM ST_REG_FIRST
1773 #define GP_REG_P(REGNO) \
1774 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1775 #define M16_REG_P(REGNO) \
1776 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1777 #define FP_REG_P(REGNO) \
1778 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1779 #define MD_REG_P(REGNO) \
1780 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1781 #define ST_REG_P(REGNO) \
1782 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1784 /* Return number of consecutive hard regs needed starting at reg REGNO
1785 to hold something of mode MODE.
1786 This is ordinarily the length in words of a value of mode MODE
1787 but can be less for certain modes in special long registers.
1789 On the MIPS, all general registers are one word long. Except on
1790 the R4000 with the FR bit set, the floating point uses register
1791 pairs, with the second register not being allocable. */
1793 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1795 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1796 MODE. In 32 bit mode, require that DImode and DFmode be in even
1797 registers. For DImode, this makes some of the insns easier to
1798 write, since you don't have to worry about a DImode value in
1799 registers 3 & 4, producing a result in 4 & 5.
1801 To make the code simpler HARD_REGNO_MODE_OK now just references an
1802 array built in override_options. Because machmodes.h is not yet
1803 included before this file is processed, the MODE bound can't be
1804 expressed here. */
1808 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1809 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1811 /* Value is 1 if it is a good idea to tie two pseudo registers
1812 when one has mode MODE1 and one has mode MODE2.
1813 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1814 for any hard reg, then this must be 0 for correct output. */
1815 #define MODES_TIEABLE_P(MODE1, MODE2) \
1816 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1817 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1818 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1819 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1821 /* MIPS pc is not overloaded on a register. */
1822 /* #define PC_REGNUM xx */
1824 /* Register to use for pushing function arguments. */
1825 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1827 /* Offset from the stack pointer to the first available location. Use
1828 the default value zero. */
1829 /* #define STACK_POINTER_OFFSET 0 */
1831 /* Base register for access to local variables of the function. We
1832 pretend that the frame pointer is $1, and then eliminate it to
1833 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1834 a fixed register, and will not be used for anything else. */
1835 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1837 /* Temporary scratch register for use by the assembler. */
1838 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1840 /* $30 is not available on the mips16, so we use $17 as the frame
1841 pointer. */
1842 #define HARD_FRAME_POINTER_REGNUM \
1843 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1845 /* Value should be nonzero if functions must have frame pointers.
1846 Zero means the frame pointer need not be set up (and parms
1847 may be accessed via the stack pointer) in functions that seem suitable.
1848 This is computed in `reload', in reload1.c. */
1849 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1851 /* Base register for access to arguments of the function. */
1852 #define ARG_POINTER_REGNUM GP_REG_FIRST
1854 /* Fake register that holds the address on the stack of the
1855 current function's return address. */
1856 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1858 /* Register in which static-chain is passed to a function. */
1859 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1861 /* If the structure value address is passed in a register, then
1862 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1863 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1865 /* If the structure value address is not passed in a register, define
1866 `STRUCT_VALUE' as an expression returning an RTX for the place
1867 where the address is passed. If it returns 0, the address is
1868 passed as an "invisible" first argument. */
1869 #define STRUCT_VALUE 0
1871 /* Mips registers used in prologue/epilogue code when the stack frame
1872 is larger than 32K bytes. These registers must come from the
1873 scratch register set, and not used for passing and returning
1874 arguments and any other information used in the calling sequence
1875 (such as pic). Must start at 12, since t0/t3 are parameter passing
1876 registers in the 64 bit ABI. */
1878 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1879 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1881 /* Define this macro if it is as good or better to call a constant
1882 function address than to call an address kept in a register. */
1883 #define NO_FUNCTION_CSE 1
1885 /* Define this macro if it is as good or better for a function to
1886 call itself with an explicit address than to call an address
1887 kept in a register. */
1888 #define NO_RECURSIVE_FUNCTION_CSE 1
1890 /* The register number of the register used to address a table of
1891 static data addresses in memory. In some cases this register is
1892 defined by a processor's "application binary interface" (ABI).
1893 When this macro is defined, RTL is generated for this register
1894 once, as with the stack pointer and frame pointer registers. If
1895 this macro is not defined, it is up to the machine-dependent
1896 files to allocate such a register (if necessary). */
1897 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1899 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1901 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1902 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1903 isn't always called for static inline functions. */
1904 #define INIT_EXPANDERS \
1905 do { \
1906 embedded_pic_fnaddr_rtx = NULL; \
1907 mips16_gp_pseudo_rtx = NULL; \
1908 } while (0)
1909 \f
1910 /* Define the classes of registers for register constraints in the
1911 machine description. Also define ranges of constants.
1913 One of the classes must always be named ALL_REGS and include all hard regs.
1914 If there is more than one class, another class must be named NO_REGS
1915 and contain no registers.
1917 The name GENERAL_REGS must be the name of a class (or an alias for
1918 another name such as ALL_REGS). This is the class of registers
1919 that is allowed by "g" or "r" in a register constraint.
1920 Also, registers outside this class are allocated only when
1921 instructions express preferences for them.
1923 The classes must be numbered in nondecreasing order; that is,
1924 a larger-numbered class must never be contained completely
1925 in a smaller-numbered class.
1927 For any two classes, it is very desirable that there be another
1928 class that represents their union. */
1930 enum reg_class
1931 {
1944 LO_AND_GR_REGS,
1945 HILO_AND_GR_REGS,
1948 LIM_REG_CLASSES /* max value + 1 */
1949 };
1951 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1953 #define GENERAL_REGS GR_REGS
1955 /* An initializer containing the names of the register classes as C
1956 string constants. These names are used in writing some of the
1957 debugging dumps. */
1959 #define REG_CLASS_NAMES \
1960 { \
1977 }
1979 /* An initializer containing the contents of the register classes,
1980 as integers which are bit masks. The Nth integer specifies the
1981 contents of class N. The way the integer MASK is interpreted is
1982 that register R is in the class if `MASK & (1 << R)' is 1.
1984 When the machine has more than 32 registers, an integer does not
1985 suffice. Then the integers are replaced by sub-initializers,
1986 braced groupings containing several integers. Each
1987 sub-initializer must be suitable as an initializer for the type
1988 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1990 #define REG_CLASS_CONTENTS \
1991 { \
2004 { 0xffffffff, 0x00000000, 0x00000002 }, \
2005 { 0xffffffff, 0x00000000, 0x00000004 }, \
2008 }
2011 /* A C expression whose value is a register class containing hard
2012 register REGNO. In general there is more that one such class;
2013 choose a class which is "minimal", meaning that no smaller class
2014 also contains the register. */
2018 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2020 /* A macro whose definition is the name of the class to which a
2021 valid base register must belong. A base register is one used in
2022 an address which is the register value plus a displacement. */
2024 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2026 /* A macro whose definition is the name of the class to which a
2027 valid index register must belong. An index register is one used
2028 in an address where its value is either multiplied by a scale
2029 factor or added to another register (as well as added to a
2030 displacement). */
2032 #define INDEX_REG_CLASS NO_REGS
2034 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2035 registers explicitly used in the rtl to be used as spill registers
2036 but prevents the compiler from extending the lifetime of these
2037 registers. */
2039 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2041 /* This macro is used later on in the file. */
2042 #define GR_REG_CLASS_P(CLASS) \
2043 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2044 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
2046 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2047 is the default value (allocate the registers in numeric order). We
2048 define it just so that we can override it for the mips16 target in
2049 ORDER_REGS_FOR_LOCAL_ALLOC. */
2051 #define REG_ALLOC_ORDER \
2052 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2053 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2054 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2055 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2056 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
2057 }
2059 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2060 to be rearranged based on a particular function. On the mips16, we
2061 want to allocate $24 (T_REG) before other registers for
2062 instructions for which it is possible. */
2064 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2066 /* REGISTER AND CONSTANT CLASSES */
2068 /* Get reg_class from a letter such as appears in the machine
2069 description.
2071 DEFINED REGISTER CLASSES:
2073 'd' General (aka integer) registers
2074 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2075 'y' General registers (in both mips16 and non mips16 mode)
2076 'e' mips16 non argument registers (M16_NA_REGS)
2077 't' mips16 temporary register ($24)
2078 'f' Floating point registers
2079 'h' Hi register
2080 'l' Lo register
2081 'x' Multiply/divide registers
2082 'a' HILO_REG
2083 'z' FP Status register
2084 'b' All registers */
2088 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2090 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2091 string can be used to stand for particular ranges of immediate
2092 operands. This macro defines what the ranges are. C is the
2093 letter, and VALUE is a constant value. Return 1 if VALUE is
2094 in the range specified by C. */
2096 /* For MIPS:
2098 `I' is used for the range of constants an arithmetic insn can
2099 actually contain (16 bits signed integers).
2101 `J' is used for the range which is just zero (ie, $r0).
2103 `K' is used for the range of constants a logical insn can actually
2104 contain (16 bit zero-extended integers).
2106 `L' is used for the range of constants that be loaded with lui
2107 (ie, the bottom 16 bits are zero).
2109 `M' is used for the range of constants that take two words to load
2110 (ie, not matched by `I', `K', and `L').
2112 `N' is used for negative 16 bit constants other than -65536.
2114 `O' is a 15 bit signed integer.
2116 `P' is used for positive 16 bit constants. */
2118 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2119 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
2121 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2126 && (((VALUE) & ~2147483647) == 0 \
2127 || ((VALUE) & ~2147483647) == ~2147483647)) \
2129 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2130 && (((VALUE) & 0x0000ffff) != 0 \
2131 || (((VALUE) & ~2147483647) != 0 \
2132 && ((VALUE) & ~2147483647) != ~2147483647))) \
2136 : 0)
2138 /* Similar, but for floating constants, and defining letters G and H.
2139 Here VALUE is the CONST_DOUBLE rtx itself. */
2141 /* For Mips
2143 'G' : Floating point 0 */
2145 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2147 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2149 /* Letters in the range `Q' through `U' may be defined in a
2150 machine-dependent fashion to stand for arbitrary operand types.
2151 The machine description macro `EXTRA_CONSTRAINT' is passed the
2152 operand as its first argument and the constraint letter as its
2153 second operand.
2155 `Q' is for mips16 GP relative constants
2156 `R' is for memory references which take 1 word for the instruction.
2157 `S' is for references to extern items which are PIC for OSF/rose.
2158 `T' is for memory addresses that can be used to load two words. */
2160 #define EXTRA_CONSTRAINT(OP,CODE) \
2163 && mips16_gp_offset_p (OP)) \
2164 : (GET_CODE (OP) != MEM) ? FALSE \
2167 && HALF_PIC_ADDRESS_P (OP)) \
2168 : FALSE)
2170 /* Given an rtx X being reloaded into a reg required to be
2171 in class CLASS, return the class of reg to actually use.
2172 In general this is just CLASS; but on some machines
2173 in some cases it is preferable to use a more restrictive class. */
2175 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2176 ((CLASS) != ALL_REGS \
2177 ? (! TARGET_MIPS16 \
2178 ? (CLASS) \
2179 : ((CLASS) != GR_REGS \
2180 ? (CLASS) \
2181 : M16_REGS)) \
2182 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2183 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2184 ? (TARGET_SOFT_FLOAT \
2185 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2186 : FP_REGS) \
2187 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2188 || GET_MODE (X) == VOIDmode) \
2189 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2190 : (CLASS))))
2192 /* Certain machines have the property that some registers cannot be
2193 copied to some other registers without using memory. Define this
2194 macro on those machines to be a C expression that is non-zero if
2195 objects of mode MODE in registers of CLASS1 can only be copied to
2196 registers of class CLASS2 by storing a register of CLASS1 into
2197 memory and loading that memory location into a register of CLASS2.
2199 Do not define this macro if its value would always be zero. */
2201 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2202 ((!TARGET_DEBUG_H_MODE \
2203 && GET_MODE_CLASS (MODE) == MODE_INT \
2204 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2205 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2206 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2207 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2208 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2210 /* The HI and LO registers can only be reloaded via the general
2211 registers. Condition code registers can only be loaded to the
2212 general registers, and from the floating point registers. */
2214 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2215 mips_secondary_reload_class (CLASS, MODE, X, 1)
2216 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2217 mips_secondary_reload_class (CLASS, MODE, X, 0)
2219 /* Return the maximum number of consecutive registers
2220 needed to represent mode MODE in a register of class CLASS. */
2222 #define CLASS_UNITS(mode, size) \
2223 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2225 #define CLASS_MAX_NREGS(CLASS, MODE) \
2226 ((CLASS) == FP_REGS \
2227 ? (TARGET_FLOAT64 \
2228 ? CLASS_UNITS (MODE, 8) \
2229 : 2 * CLASS_UNITS (MODE, 8)) \
2230 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2232 /* If defined, gives a class of registers that cannot be used as the
2233 operand of a SUBREG that changes the mode of the object illegally. */
2235 #define CLASS_CANNOT_CHANGE_MODE \
2236 (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
2238 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2240 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2241 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2242 \f
2243 /* Stack layout; function entry, exit and calling. */
2245 /* Define this if pushing a word on the stack
2246 makes the stack pointer a smaller address. */
2247 #define STACK_GROWS_DOWNWARD
2249 /* Define this if the nominal address of the stack frame
2250 is at the high-address end of the local variables;
2251 that is, each additional local variable allocated
2252 goes at a more negative offset in the frame. */
2253 /* #define FRAME_GROWS_DOWNWARD */
2255 /* Offset within stack frame to start allocating local variables at.
2256 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2257 first local allocated. Otherwise, it is the offset to the BEGINNING
2258 of the first local allocated. */
2259 #define STARTING_FRAME_OFFSET \
2260 (current_function_outgoing_args_size \
2261 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2263 /* Offset from the stack pointer register to an item dynamically
2264 allocated on the stack, e.g., by `alloca'.
2266 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2267 length of the outgoing arguments. The default is correct for most
2268 machines. See `function.c' for details.
2270 The MIPS ABI states that functions which dynamically allocate the
2271 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2272 we are trying to create a second frame pointer to the function, so
2273 allocate some stack space to make it happy.
2275 However, the linker currently complains about linking any code that
2276 dynamically allocates stack space, and there seems to be a bug in
2277 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2279 #if 0
2280 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2281 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2282 ? 4*UNITS_PER_WORD \
2283 : current_function_outgoing_args_size)
2284 #endif
2286 /* The return address for the current frame is in r31 is this is a leaf
2287 function. Otherwise, it is on the stack. It is at a variable offset
2288 from sp/fp/ap, so we define a fake hard register rap which is a
2289 poiner to the return address on the stack. This always gets eliminated
2290 during reload to be either the frame pointer or the stack pointer plus
2291 an offset. */
2293 /* ??? This definition fails for leaf functions. There is currently no
2294 general solution for this problem. */
2296 /* ??? There appears to be no way to get the return address of any previous
2297 frame except by disassembling instructions in the prologue/epilogue.
2298 So currently we support only the current frame. */
2300 #define RETURN_ADDR_RTX(count, frame) \
2301 ((count == 0) \
2302 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2303 : (rtx) 0)
2305 /* Structure to be filled in by compute_frame_size with register
2306 save masks, and offsets for the current function. */
2308 struct mips_frame_info
2309 {
2326 };
2330 /* If defined, this macro specifies a table of register pairs used to
2331 eliminate unneeded registers that point into the stack frame. If
2332 it is not defined, the only elimination attempted by the compiler
2333 is to replace references to the frame pointer with references to
2334 the stack pointer.
2336 The definition of this macro is a list of structure
2337 initializations, each of which specifies an original and
2338 replacement register.
2340 On some machines, the position of the argument pointer is not
2341 known until the compilation is completed. In such a case, a
2342 separate hard register must be used for the argument pointer.
2343 This register can be eliminated by replacing it with either the
2344 frame pointer or the argument pointer, depending on whether or not
2345 the frame pointer has been eliminated.
2347 In this case, you might specify:
2348 #define ELIMINABLE_REGS \
2349 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2350 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2351 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2353 Note that the elimination of the argument pointer with the stack
2354 pointer is specified first since that is the preferred elimination.
2356 The eliminations to $17 are only used on the mips16. See the
2357 definition of HARD_FRAME_POINTER_REGNUM. */
2359 #define ELIMINABLE_REGS \
2360 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2361 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2362 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2363 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2364 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2365 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2366 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2367 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2368 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2369 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2371 /* A C expression that returns non-zero if the compiler is allowed to
2372 try to replace register number FROM-REG with register number
2373 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2374 defined, and will usually be the constant 1, since most of the
2375 cases preventing register elimination are things that the compiler
2376 already knows about.
2378 When not in mips16 and mips64, we can always eliminate to the
2379 frame pointer. We can eliminate to the stack pointer unless
2380 a frame pointer is needed. In mips16 mode, we need a frame
2381 pointer for a large frame; otherwise, reload may be unable
2382 to compute the address of a local variable, since there is
2383 no way to add a large constant to the stack pointer
2384 without using a temporary register.
2386 In mips16, for some instructions (eg lwu), we can't eliminate the
2387 frame pointer for the stack pointer. These instructions are
2388 only generated in TARGET_64BIT mode.
2389 */
2391 #define CAN_ELIMINATE(FROM, TO) \
2392 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2393 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2394 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2395 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2396 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2397 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2398 && (! TARGET_MIPS16 \
2399 || compute_frame_size (get_frame_size ()) < 32768)))))
2401 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2402 specifies the initial difference between the specified pair of
2403 registers. This macro must be defined if `ELIMINABLE_REGS' is
2404 defined. */
2406 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2407 { compute_frame_size (get_frame_size ()); \
2408 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2409 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2410 (OFFSET) = - current_function_outgoing_args_size; \
2411 else if ((FROM) == FRAME_POINTER_REGNUM) \
2412 (OFFSET) = 0; \
2413 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2414 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2415 (OFFSET) = (current_frame_info.total_size \
2416 - current_function_outgoing_args_size \
2417 - ((mips_abi != ABI_32 \
2418 && mips_abi != ABI_O64 \
2419 && mips_abi != ABI_EABI) \
2420 ? current_function_pretend_args_size \
2421 : 0)); \
2422 else if ((FROM) == ARG_POINTER_REGNUM) \
2423 (OFFSET) = (current_frame_info.total_size \
2424 - ((mips_abi != ABI_32 \
2425 && mips_abi != ABI_O64 \
2426 && mips_abi != ABI_EABI) \
2427 ? current_function_pretend_args_size \
2428 : 0)); \
2429 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2431 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2432 { \
2433 if (leaf_function_p ()) \
2434 (OFFSET) = 0; \
2435 else (OFFSET) = current_frame_info.gp_sp_offset \
2436 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2437 * (BYTES_BIG_ENDIAN != 0)); \
2438 } \
2439 else \
2440 abort(); \
2441 }
2443 /* If we generate an insn to push BYTES bytes,
2444 this says how many the stack pointer really advances by.
2445 On the VAX, sp@- in a byte insn really pushes a word. */
2447 /* #define PUSH_ROUNDING(BYTES) 0 */
2449 /* If defined, the maximum amount of space required for outgoing
2450 arguments will be computed and placed into the variable
2451 `current_function_outgoing_args_size'. No space will be pushed
2452 onto the stack for each call; instead, the function prologue
2453 should increase the stack frame size by this amount.
2455 It is not proper to define both `PUSH_ROUNDING' and
2456 `ACCUMULATE_OUTGOING_ARGS'. */
2457 #define ACCUMULATE_OUTGOING_ARGS 1
2459 /* Offset from the argument pointer register to the first argument's
2460 address. On some machines it may depend on the data type of the
2461 function.
2463 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2464 the first argument's address.
2466 On the MIPS, we must skip the first argument position if we are
2467 returning a structure or a union, to account for its address being
2468 passed in $4. However, at the current time, this produces a compiler
2469 that can't bootstrap, so comment it out for now. */
2471 #if 0
2472 #define FIRST_PARM_OFFSET(FNDECL) \
2473 (FNDECL != 0 \
2474 && TREE_TYPE (FNDECL) != 0 \
2475 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2476 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2477 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2478 ? UNITS_PER_WORD \
2479 : 0)
2480 #else
2481 #define FIRST_PARM_OFFSET(FNDECL) 0
2482 #endif
2484 /* When a parameter is passed in a register, stack space is still
2485 allocated for it. For the MIPS, stack space must be allocated, cf
2486 Asm Lang Prog Guide page 7-8.
2488 BEWARE that some space is also allocated for non existing arguments
2489 in register. In case an argument list is of form GF used registers
2490 are a0 (a2,a3), but we should push over a1... */
2492 #define REG_PARM_STACK_SPACE(FNDECL) \
2493 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2495 /* Define this if it is the responsibility of the caller to
2496 allocate the area reserved for arguments passed in registers.
2497 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2498 of this macro is to determine whether the space is included in
2499 `current_function_outgoing_args_size'. */
2500 #define OUTGOING_REG_PARM_STACK_SPACE
2502 /* Align stack frames on 64 bits (Double Word ). */
2503 #ifndef STACK_BOUNDARY
2504 #define STACK_BOUNDARY 64
2505 #endif
2507 /* Make sure 4 words are always allocated on the stack. */
2509 #ifndef STACK_ARGS_ADJUST
2510 #define STACK_ARGS_ADJUST(SIZE) \
2511 { \
2512 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2513 SIZE.constant = 4 * UNITS_PER_WORD; \
2514 }
2515 #endif
2517 \f
2518 /* A C expression that should indicate the number of bytes of its
2519 own arguments that a function pops on returning, or 0
2520 if the function pops no arguments and the caller must therefore
2521 pop them all after the function returns.
2523 FUNDECL is the declaration node of the function (as a tree).
2525 FUNTYPE is a C variable whose value is a tree node that
2526 describes the function in question. Normally it is a node of
2527 type `FUNCTION_TYPE' that describes the data type of the function.
2528 From this it is possible to obtain the data types of the value
2529 and arguments (if known).
2531 When a call to a library function is being considered, FUNTYPE
2532 will contain an identifier node for the library function. Thus,
2533 if you need to distinguish among various library functions, you
2534 can do so by their names. Note that "library function" in this
2535 context means a function used to perform arithmetic, whose name
2536 is known specially in the compiler and was not mentioned in the
2537 C code being compiled.
2539 STACK-SIZE is the number of bytes of arguments passed on the
2540 stack. If a variable number of bytes is passed, it is zero, and
2541 argument popping will always be the responsibility of the
2542 calling function. */
2544 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2547 /* Symbolic macros for the registers used to return integer and floating
2548 point values. */
2550 #define GP_RETURN (GP_REG_FIRST + 2)
2551 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2553 /* Symbolic macros for the first/last argument registers. */
2555 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2556 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2557 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2558 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2560 #define MAX_ARGS_IN_REGISTERS 4
2562 /* Define how to find the value returned by a library function
2563 assuming the value has mode MODE. Because we define
2564 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2565 PROMOTE_MODE does. */
2567 #define LIBCALL_VALUE(MODE) \
2568 gen_rtx (REG, \
2569 ((GET_MODE_CLASS (MODE) != MODE_INT \
2570 || GET_MODE_SIZE (MODE) >= 4) \
2571 ? (MODE) \
2572 : SImode), \
2573 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2574 && (! TARGET_SINGLE_FLOAT \
2575 || GET_MODE_SIZE (MODE) <= 4)) \
2576 ? FP_RETURN \
2577 : GP_RETURN))
2579 /* Define how to find the value returned by a function.
2580 VALTYPE is the data type of the value (as a tree).
2581 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2582 otherwise, FUNC is 0. */
2584 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2587 /* 1 if N is a possible register number for a function value.
2588 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2589 Currently, R2 and F0 are only implemented here (C has no complex type) */
2591 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2593 /* 1 if N is a possible register number for function argument passing.
2594 We have no FP argument registers when soft-float. When FP registers
2595 are 32 bits, we can't directly reference the odd numbered ones. */
2597 #define FUNCTION_ARG_REGNO_P(N) \
2598 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2599 || ((! TARGET_SOFT_FLOAT \
2600 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2601 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2602 && ! fixed_regs[N]))
2604 /* A C expression which can inhibit the returning of certain function
2605 values in registers, based on the type of value. A nonzero value says
2606 to return the function value in memory, just as large structures are
2607 always returned. Here TYPE will be a C expression of type
2608 `tree', representing the data type of the value.
2610 Note that values of mode `BLKmode' must be explicitly
2611 handled by this macro. Also, the option `-fpcc-struct-return'
2612 takes effect regardless of this macro. On most systems, it is
2613 possible to leave the macro undefined; this causes a default
2614 definition to be used, whose value is the constant 1 for BLKmode
2615 values, and 0 otherwise.
2617 GCC normally converts 1 byte structures into chars, 2 byte
2618 structs into shorts, and 4 byte structs into ints, and returns
2619 them this way. Defining the following macro overrides this,
2620 to give us MIPS cc compatibility. */
2622 #define RETURN_IN_MEMORY(TYPE) \
2623 (TYPE_MODE (TYPE) == BLKmode)
2624 \f
2625 /* A code distinguishing the floating point format of the target
2626 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2627 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2629 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2631 \f
2632 /* Define a data type for recording info about an argument list
2633 during the scan of that argument list. This data type should
2634 hold all necessary information about the function itself
2635 and about the args processed so far, enough to enable macros
2636 such as FUNCTION_ARG to determine where the next arg should go.
2638 On the mips16, we need to keep track of which floating point
2639 arguments were passed in general registers, but would have been
2640 passed in the FP regs if this were a 32 bit function, so that we
2641 can move them to the FP regs if we wind up calling a 32 bit
2642 function. We record this information in fp_code, encoded in base
2643 four. A zero digit means no floating point argument, a one digit
2644 means an SFmode argument, and a two digit means a DFmode argument,
2645 and a three digit is not used. The low order digit is the first
2646 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2647 an SFmode argument. ??? A more sophisticated approach will be
2648 needed if MIPS_ABI != ABI_32. */
2658 /* Adjustments made to args pass in regs. */
2659 /* ??? The size is doubled to work around a
2660 bug in the code that sets the adjustments
2661 in function_arg. */
2666 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2667 for a call to a function whose data type is FNTYPE.
2668 For a library call, FNTYPE is 0.
2670 */
2672 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2673 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2675 /* Update the data in CUM to advance over an argument
2676 of mode MODE and data type TYPE.
2677 (TYPE is null for libcalls where that information may not be available.) */
2679 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2680 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2682 /* Determine where to put an argument to a function.
2683 Value is zero to push the argument on the stack,
2684 or a hard register in which to store the argument.
2686 MODE is the argument's machine mode.
2687 TYPE is the data type of the argument (as a tree).
2688 This is null for libcalls where that information may
2689 not be available.
2690 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2691 the preceding args and about the function being called.
2692 NAMED is nonzero if this argument is a named parameter
2693 (otherwise it is an extra parameter matching an ellipsis). */
2695 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2696 function_arg( &CUM, MODE, TYPE, NAMED)
2698 /* For an arg passed partly in registers and partly in memory,
2699 this is the number of registers used.
2700 For args passed entirely in registers or entirely in memory, zero. */
2702 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2703 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2705 /* If defined, a C expression that gives the alignment boundary, in
2706 bits, of an argument with the specified mode and type. If it is
2707 not defined, `PARM_BOUNDARY' is used for all arguments. */
2709 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2710 (((TYPE) != 0) \
2711 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2712 ? PARM_BOUNDARY \
2713 : TYPE_ALIGN(TYPE)) \
2714 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2715 ? PARM_BOUNDARY \
2716 : GET_MODE_ALIGNMENT(MODE)))
2718 \f
2719 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2721 #define MUST_SAVE_REGISTER(regno) \
2722 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2723 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2724 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2726 /* ALIGN FRAMES on double word boundaries */
2727 #ifndef MIPS_STACK_ALIGN
2728 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2729 #endif
2731 \f
2732 /* Define the `__builtin_va_list' type for the ABI. */
2733 #define BUILD_VA_LIST_TYPE(VALIST) \
2734 (VALIST) = mips_build_va_list ()
2736 /* Implement `va_start' for varargs and stdarg. */
2737 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2738 mips_va_start (stdarg, valist, nextarg)
2740 /* Implement `va_arg'. */
2741 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2742 mips_va_arg (valist, type)
2743 \f
2744 /* Output assembler code to FILE to increment profiler label # LABELNO
2745 for profiling a function entry. */
2747 #define FUNCTION_PROFILER(FILE, LABELNO) \
2748 { \
2749 if (TARGET_MIPS16) \
2754 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2756 fprintf (FILE, \
2759 reg_names[STACK_POINTER_REGNUM], \
2760 reg_names[STACK_POINTER_REGNUM], \
2761 Pmode == DImode ? 16 : 8); \
2764 }
2766 /* Define this macro if the code for function profiling should come
2767 before the function prologue. Normally, the profiling code comes
2768 after. */
2770 /* #define PROFILE_BEFORE_PROLOGUE */
2772 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2773 the stack pointer does not matter. The value is tested only in
2774 functions that have frame pointers.
2775 No definition is equivalent to always zero. */
2777 #define EXIT_IGNORE_STACK 1
2779 \f
2780 /* A C statement to output, on the stream FILE, assembler code for a
2781 block of data that contains the constant parts of a trampoline.
2782 This code should not include a label--the label is taken care of
2783 automatically. */
2785 #define TRAMPOLINE_TEMPLATE(STREAM) \
2786 { \
2790 if (Pmode == DImode) \
2791 { \
2794 } \
2795 else \
2796 { \
2799 } \
2803 if (Pmode == DImode) \
2804 { \
2807 } \
2808 else \
2809 { \
2812 } \
2813 }
2815 /* A C expression for the size in bytes of the trampoline, as an
2816 integer. */
2818 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2820 /* Alignment required for trampolines, in bits. */
2822 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2824 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2825 program and data caches. */
2827 #ifndef CACHE_FLUSH_FUNC
2829 #endif
2831 /* A C statement to initialize the variable parts of a trampoline.
2832 ADDR is an RTX for the address of the trampoline; FNADDR is an
2833 RTX for the address of the nested function; STATIC_CHAIN is an
2834 RTX for the static chain value that should be passed to the
2835 function when it is called. */
2837 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2838 { \
2839 rtx addr = ADDR; \
2840 if (Pmode == DImode) \
2841 { \
2842 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2843 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2844 } \
2845 else \
2846 { \
2847 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2848 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2849 } \
2850 \
2851 /* Flush both caches. We need to flush the data cache in case \
2854 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2855 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2856 0, VOIDmode, 3, addr, Pmode, \
2857 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2858 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2859 }
2860 \f
2861 /* Addressing modes, and classification of registers for them. */
2863 /* #define HAVE_POST_INCREMENT 0 */
2864 /* #define HAVE_POST_DECREMENT 0 */
2866 /* #define HAVE_PRE_DECREMENT 0 */
2867 /* #define HAVE_PRE_INCREMENT 0 */
2869 /* These assume that REGNO is a hard or pseudo reg number.
2870 They give nonzero only if REGNO is a hard reg of the suitable class
2871 or a pseudo reg currently allocated to a suitable hard reg.
2872 These definitions are NOT overridden anywhere. */
2874 #define BASE_REG_P(regno, mode) \
2875 (TARGET_MIPS16 \
2876 ? (M16_REG_P (regno) \
2877 || (regno) == FRAME_POINTER_REGNUM \
2878 || (regno) == ARG_POINTER_REGNUM \
2879 || ((regno) == STACK_POINTER_REGNUM \
2880 && (GET_MODE_SIZE (mode) == 4 \
2881 || GET_MODE_SIZE (mode) == 8))) \
2882 : GP_REG_P (regno))
2884 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2885 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2886 (mode))
2888 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2889 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2891 #define REGNO_OK_FOR_INDEX_P(regno) 0
2892 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2893 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2895 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2896 and check its validity for a certain class.
2897 We have two alternate definitions for each of them.
2898 The usual definition accepts all pseudo regs; the other rejects them all.
2899 The symbol REG_OK_STRICT causes the latter definition to be used.
2901 Most source files want to accept pseudo regs in the hope that
2902 they will get allocated to the class that the insn wants them to be in.
2903 Some source files that are used after register allocation
2904 need to be strict. */
2906 #ifndef REG_OK_STRICT
2907 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2908 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2909 #else
2910 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2911 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2912 #endif
2914 #define REG_OK_FOR_INDEX_P(X) 0
2916 \f
2917 /* Maximum number of registers that can appear in a valid memory address. */
2919 #define MAX_REGS_PER_ADDRESS 1
2921 /* A C compound statement with a conditional `goto LABEL;' executed
2922 if X (an RTX) is a legitimate memory address on the target
2923 machine for a memory operand of mode MODE.
2925 It usually pays to define several simpler macros to serve as
2926 subroutines for this one. Otherwise it may be too complicated
2927 to understand.
2929 This macro must exist in two variants: a strict variant and a
2930 non-strict one. The strict variant is used in the reload pass.
2931 It must be defined so that any pseudo-register that has not been
2932 allocated a hard register is considered a memory reference. In
2933 contexts where some kind of register is required, a
2934 pseudo-register with no hard register must be rejected.
2936 The non-strict variant is used in other passes. It must be
2937 defined to accept all pseudo-registers in every context where
2938 some kind of register is required.
2940 Compiler source files that want to use the strict variant of
2941 this macro define the macro `REG_OK_STRICT'. You should use an
2942 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2943 in that case and the non-strict variant otherwise.
2945 Typically among the subroutines used to define
2946 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2947 acceptable registers for various purposes (one for base
2948 registers, one for index registers, and so on). Then only these
2949 subroutine macros need have two variants; the higher levels of
2950 macros may be the same whether strict or not.
2952 Normally, constant addresses which are the sum of a `symbol_ref'
2953 and an integer are stored inside a `const' RTX to mark them as
2954 constant. Therefore, there is no need to recognize such sums
2955 specifically as legitimate addresses. Normally you would simply
2956 recognize any `const' as legitimate.
2958 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2959 constant sums that are not marked with `const'. It assumes
2960 that a naked `plus' indicates indexing. If so, then you *must*
2961 reject such naked constant sums as illegitimate addresses, so
2962 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2964 On some machines, whether a symbolic address is legitimate
2965 depends on the section that the address refers to. On these
2966 machines, define the macro `ENCODE_SECTION_INFO' to store the
2967 information into the `symbol_ref', and then check for it here.
2968 When you see a `const', you will have to look inside it to find
2969 the `symbol_ref' in order to determine the section. */
2971 #if 1
2972 #define GO_PRINTF(x) fprintf(stderr, (x))
2973 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2974 #define GO_DEBUG_RTX(x) debug_rtx(x)
2976 #else
2977 #define GO_PRINTF(x)
2978 #define GO_PRINTF2(x,y)
2979 #define GO_DEBUG_RTX(x)
2980 #endif
2982 #ifdef REG_OK_STRICT
2983 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2984 { \
2985 if (mips_legitimate_address_p (MODE, X, 1)) \
2986 goto ADDR; \
2987 }
2988 #else
2989 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2990 { \
2991 if (mips_legitimate_address_p (MODE, X, 0)) \
2992 goto ADDR; \
2993 }
2994 #endif
2996 /* A C expression that is 1 if the RTX X is a constant which is a
2997 valid address. This is defined to be the same as `CONSTANT_P (X)',
2998 but rejecting CONST_DOUBLE. */
2999 /* When pic, we must reject addresses of the form symbol+large int.
3000 This is because an instruction `sw $4,s+70000' needs to be converted
3001 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
3002 assembler would use $at as a temp to load in the large offset. In this
3003 case $at is already in use. We convert such problem addresses to
3004 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
3005 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
3006 #define CONSTANT_ADDRESS_P(X) \
3007 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
3008 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
3009 || (GET_CODE (X) == CONST \
3010 && ! (flag_pic && pic_address_needs_scratch (X)) \
3011 && (mips_abi == ABI_32 \
3012 || mips_abi == ABI_O64 \
3013 || mips_abi == ABI_EABI))) \
3014 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
3016 /* Define this, so that when PIC, reload won't try to reload invalid
3017 addresses which require two reload registers. */
3019 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
3021 /* Nonzero if the constant value X is a legitimate general operand.
3022 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3024 At present, GAS doesn't understand li.[sd], so don't allow it
3025 to be generated at present. Also, the MIPS assembler does not
3026 grok li.d Infinity. */
3028 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3029 Note that the Irix 6 assembler problem may already be fixed.
3030 Note also that the GET_CODE (X) == CONST test catches the mips16
3031 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3032 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3033 ABI_64 to work together, we'll need to fix this. */
3034 #define LEGITIMATE_CONSTANT_P(X) \
3035 ((GET_CODE (X) != CONST_DOUBLE \
3036 || mips_const_double_ok (X, GET_MODE (X))) \
3037 && ! (GET_CODE (X) == CONST \
3038 && ! TARGET_GAS \
3039 && (mips_abi == ABI_N32 \
3040 || mips_abi == ABI_64)) \
3041 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
3043 /* A C compound statement that attempts to replace X with a valid
3044 memory address for an operand of mode MODE. WIN will be a C
3045 statement label elsewhere in the code; the macro definition may
3046 use
3048 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3050 to avoid further processing if the address has become legitimate.
3052 X will always be the result of a call to `break_out_memory_refs',
3053 and OLDX will be the operand that was given to that function to
3054 produce X.
3056 The code generated by this macro should not alter the
3057 substructure of X. If it transforms X into a more legitimate
3058 form, it should assign X (which will always be a C variable) a
3059 new value.
3061 It is not necessary for this macro to come up with a legitimate
3062 address. The compiler has standard ways of doing so in all
3063 cases. In fact, it is safe for this macro to do nothing. But
3064 often a machine-dependent strategy can generate better code.
3066 For the MIPS, transform:
3068 memory(X + <large int>)
3070 into:
3072 Y = <large int> & ~0x7fff;
3073 Z = X + Y
3074 memory (Z + (<large int> & 0x7fff));
3076 This is for CSE to find several similar references, and only use one Z.
3078 When PIC, convert addresses of the form memory (symbol+large int) to
3079 memory (reg+large int). */
3082 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3083 { \
3084 register rtx xinsn = (X); \
3085 \
3086 if (TARGET_DEBUG_B_MODE) \
3087 { \
3089 GO_DEBUG_RTX (xinsn); \
3090 } \
3091 \
3092 if (mips_split_addresses && mips_check_split (X, MODE)) \
3093 { \
3095 X = gen_rtx_LO_SUM (Pmode, \
3096 copy_to_mode_reg (Pmode, \
3097 gen_rtx (HIGH, Pmode, X)), \
3098 X); \
3099 goto WIN; \
3100 } \
3101 \
3102 if (GET_CODE (xinsn) == CONST \
3103 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3105 || (mips_abi != ABI_32 \
3106 && mips_abi != ABI_O64 \
3107 && mips_abi != ABI_EABI))) \
3108 { \
3109 rtx ptr_reg = gen_reg_rtx (Pmode); \
3110 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3111 \
3112 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3113 \
3114 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
3115 if (SMALL_INT (constant)) \
3116 goto WIN; \
3117 /* Otherwise we fall through so the code below will fix the \
3119 xinsn = X; \
3120 } \
3121 \
3122 if (GET_CODE (xinsn) == PLUS) \
3123 { \
3124 register rtx xplus0 = XEXP (xinsn, 0); \
3125 register rtx xplus1 = XEXP (xinsn, 1); \
3126 register enum rtx_code code0 = GET_CODE (xplus0); \
3127 register enum rtx_code code1 = GET_CODE (xplus1); \
3128 \
3129 if (code0 != REG && code1 == REG) \
3130 { \
3131 xplus0 = XEXP (xinsn, 1); \
3132 xplus1 = XEXP (xinsn, 0); \
3133 code0 = GET_CODE (xplus0); \
3134 code1 = GET_CODE (xplus1); \
3135 } \
3136 \
3137 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3138 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3139 { \
3140 rtx int_reg = gen_reg_rtx (Pmode); \
3141 rtx ptr_reg = gen_reg_rtx (Pmode); \
3142 \
3143 emit_move_insn (int_reg, \
3144 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3145 \
3146 emit_insn (gen_rtx_SET (VOIDmode, \
3147 ptr_reg, \
3148 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3149 \
3150 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3151 goto WIN; \
3152 } \
3153 } \
3154 \
3155 if (TARGET_DEBUG_B_MODE) \
3157 }
3160 /* A C statement or compound statement with a conditional `goto
3161 LABEL;' executed if memory address X (an RTX) can have different
3162 meanings depending on the machine mode of the memory reference it
3163 is used for.
3165 Autoincrement and autodecrement addresses typically have
3166 mode-dependent effects because the amount of the increment or
3167 decrement is the size of the operand being addressed. Some
3168 machines have other mode-dependent addresses. Many RISC machines
3169 have no mode-dependent addresses.
3171 You may assume that ADDR is a valid address for the machine. */
3173 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3176 /* Define this macro if references to a symbol must be treated
3177 differently depending on something about the variable or
3178 function named by the symbol (such as what section it is in).
3180 The macro definition, if any, is executed immediately after the
3181 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3182 The value of the rtl will be a `mem' whose address is a
3183 `symbol_ref'.
3185 The usual thing for this macro to do is to a flag in the
3186 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3187 name string in the `symbol_ref' (if one bit is not enough
3188 information).
3190 The best way to modify the name string is by adding text to the
3191 beginning, with suitable punctuation to prevent any ambiguity.
3192 Allocate the new name in `saveable_obstack'. You will have to
3193 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3194 and output the name accordingly.
3196 You can also check the information stored in the `symbol_ref' in
3197 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3198 `PRINT_OPERAND_ADDRESS'.
3200 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3201 small objects.
3203 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3204 symbols which are not in the .text section.
3206 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3207 constants which are put in the .text section. We also record the
3208 total length of all such strings; this total is used to decide
3209 whether we need to split the constant table, and need not be
3210 precisely correct.
3212 When not mips16 code nor embedded PIC, if a symbol is in a
3213 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3214 splitting the reference so that gas can generate a gp relative
3215 reference.
3217 When TARGET_EMBEDDED_DATA is set, we assume that all const
3218 variables will be stored in ROM, which is too far from %gp to use
3219 %gprel addressing. Note that (1) we include "extern const"
3220 variables in this, which mips_select_section doesn't, and (2) we
3221 can't always tell if they're really const (they might be const C++
3222 objects with non-const constructors), so we err on the side of
3223 caution and won't use %gprel anyway (otherwise we'd have to defer
3224 this decision to the linker/loader). The handling of extern consts
3225 is why the DECL_INITIAL macros differ from mips_select_section.
3227 If you are changing this macro, you should look at
3228 mips_select_section and see if it needs a similar change. */
3230 #define ENCODE_SECTION_INFO(DECL) \
3231 do \
3232 { \
3233 if (TARGET_MIPS16) \
3234 { \
3235 if (TREE_CODE (DECL) == STRING_CST \
3236 && ! flag_writable_strings \
3237 /* If this string is from a function, and the function will \
3238 go in a gnu linkonce section, then we can't directly \
3239 access the string. This gets an assembler error \
3240 "unsupported PC relative reference to different section".\
3241 If we modify SELECT_SECTION to put it in function_section\
3242 instead of text_section, it still fails because \
3243 DECL_SECTION_NAME isn't set until assemble_start_function.\
3244 If we fix that, it still fails because strings are shared\
3245 among multiple functions, and we have cross section \
3246 references again. We force it to work by putting string \
3248 && (! current_function_decl \
3249 || ! DECL_ONE_ONLY (current_function_decl))) \
3250 { \
3251 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3252 mips_string_length += TREE_STRING_LENGTH (DECL); \
3253 } \
3254 } \
3255 \
3256 if (TARGET_EMBEDDED_DATA \
3257 && (TREE_CODE (DECL) == VAR_DECL \
3258 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3259 && (!DECL_INITIAL (DECL) \
3260 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3261 { \
3262 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3263 } \
3264 \
3265 else if (TARGET_EMBEDDED_PIC) \
3266 { \
3267 if (TREE_CODE (DECL) == VAR_DECL) \
3268 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3269 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3270 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3271 else if (TREE_CODE (DECL) == STRING_CST \
3272 && ! flag_writable_strings) \
3273 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3274 else \
3275 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3276 } \
3277 \
3278 else if (TREE_CODE (DECL) == VAR_DECL \
3279 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3280 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3282 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3284 { \
3285 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3286 } \
3287 \
3288 /* We can not perform GP optimizations on variables which are in \
3289 specific sections, except for .sdata and .sbss which are \
3291 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3292 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3293 { \
3294 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3295 \
3296 if (size > 0 && size <= mips_section_threshold) \
3297 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3298 } \
3299 \
3300 else if (HALF_PIC_P ()) \
3301 { \
3302 HALF_PIC_ENCODE (DECL); \
3303 } \
3304 } \
3305 while (0)
3307 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3308 'the start of the function that this code is output in'. */
3310 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3313 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3314 else \
3317 /* The mips16 wants the constant pool to be after the function,
3318 because the PC relative load instructions use unsigned offsets. */
3320 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3322 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3323 mips_string_length = 0;
3325 #if 0
3326 /* In mips16 mode, put most string constants after the function. */
3327 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3328 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3329 #endif
3330 \f
3331 /* Specify the machine mode that this machine uses
3332 for the index in the tablejump instruction.
3333 ??? Using HImode in mips16 mode can cause overflow. However, the
3334 overflow is no more likely than the overflow in a branch
3335 instruction. Large functions can currently break in both ways. */
3336 #define CASE_VECTOR_MODE \
3337 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3339 /* Define as C expression which evaluates to nonzero if the tablejump
3340 instruction expects the table to contain offsets from the address of the
3341 table.
3342 Do not define this if the table should contain absolute addresses. */
3343 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3345 /* Specify the tree operation to be used to convert reals to integers. */
3346 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3348 /* This is the kind of divide that is easiest to do in the general case. */
3349 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3351 /* Define this as 1 if `char' should by default be signed; else as 0. */
3352 #ifndef DEFAULT_SIGNED_CHAR
3353 #define DEFAULT_SIGNED_CHAR 1
3354 #endif
3356 /* Max number of bytes we can move from memory to memory
3357 in one reasonably fast instruction. */
3358 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3359 #define MAX_MOVE_MAX 8
3361 /* Define this macro as a C expression which is nonzero if
3362 accessing less than a word of memory (i.e. a `char' or a
3363 `short') is no faster than accessing a word of memory, i.e., if
3364 such access require more than one instruction or if there is no
3365 difference in cost between byte and (aligned) word loads.
3367 On RISC machines, it tends to generate better code to define
3368 this as 1, since it avoids making a QI or HI mode register. */
3369 #define SLOW_BYTE_ACCESS 1
3371 /* We assume that the store-condition-codes instructions store 0 for false
3372 and some other value for true. This is the value stored for true. */
3374 #define STORE_FLAG_VALUE 1
3376 /* Define this if zero-extension is slow (more than one real instruction). */
3377 #define SLOW_ZERO_EXTEND
3379 /* Define this to be nonzero if shift instructions ignore all but the low-order
3380 few bits. */
3381 #define SHIFT_COUNT_TRUNCATED 1
3383 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3384 is done just by pretending it is already truncated. */
3385 /* In 64 bit mode, 32 bit instructions require that register values be properly
3386 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3387 converts a value >32 bits to a value <32 bits. */
3388 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3389 Something needs to be done about this. Perhaps not use any 32 bit
3390 instructions? Perhaps use PROMOTE_MODE? */
3391 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3392 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3394 /* Specify the machine mode that pointers have.
3395 After generation of rtl, the compiler makes no further distinction
3396 between pointers and any other objects of this machine mode.
3398 For MIPS we make pointers are the smaller of longs and gp-registers. */
3400 #ifndef Pmode
3401 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3402 #endif
3404 /* A function address in a call instruction
3405 is a word address (for indexing purposes)
3406 so give the MEM rtx a words's mode. */
3408 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3410 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3411 memset, instead of the BSD functions bcopy and bzero. */
3413 #if defined(MIPS_SYSV) || defined(OSF_OS)
3414 #define TARGET_MEM_FUNCTIONS
3415 #endif
3417 \f
3418 /* A part of a C `switch' statement that describes the relative
3419 costs of constant RTL expressions. It must contain `case'
3420 labels for expression codes `const_int', `const', `symbol_ref',
3421 `label_ref' and `const_double'. Each case must ultimately reach
3422 a `return' statement to return the relative cost of the use of
3423 that kind of constant value in an expression. The cost may
3424 depend on the precise value of the constant, which is available
3425 for examination in X.
3427 CODE is the expression code--redundant, since it can be obtained
3428 with `GET_CODE (X)'. */
3430 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3431 case CONST_INT: \
3432 if (! TARGET_MIPS16) \
3433 { \
3434 /* Always return 0, since we don't have different sized \
3435 instructions, hence different costs according to Richard \
3437 return 0; \
3438 } \
3439 if ((OUTER_CODE) == SET) \
3440 { \
3441 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3442 return 0; \
3443 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3444 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3445 return COSTS_N_INSNS (1); \
3446 else \
3447 return COSTS_N_INSNS (2); \
3448 } \
3449 /* A PLUS could be an address. We don't want to force an address \
3450 to use a register, so accept any signed 16 bit value without \
3452 if ((OUTER_CODE) == PLUS \
3453 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3454 return 0; \
3455 /* A number between 1 and 8 inclusive is efficient for a shift. \
3457 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3458 || (OUTER_CODE) == LSHIFTRT) \
3459 { \
3460 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3461 return 0; \
3462 return COSTS_N_INSNS (1); \
3463 } \
3465 if ((OUTER_CODE) == XOR \
3466 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3467 return 0; \
3468 /* We may be able to use slt or sltu for a comparison with a \
3469 signed 16 bit value. (The boundary conditions aren't quite \
3471 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3472 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3473 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3474 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3475 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3476 return 0; \
3478 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3479 && INTVAL (X) == 0) \
3480 return 0; \
3481 \
3482 /* Otherwise, work out the cost to load the value into a \
3484 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3485 return COSTS_N_INSNS (1); \
3486 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3487 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3488 return COSTS_N_INSNS (2); \
3489 else \
3490 return COSTS_N_INSNS (3); \
3491 \
3492 case LABEL_REF: \
3493 return COSTS_N_INSNS (2); \
3494 \
3495 case CONST: \
3496 { \
3497 rtx offset = const0_rtx; \
3498 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3499 \
3500 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3501 { \
3503 if ((OUTER_CODE) == PLUS) \
3504 return 0; \
3505 else if ((OUTER_CODE) == SET) \
3506 return COSTS_N_INSNS (1); \
3507 else \
3508 return COSTS_N_INSNS (2); \
3509 } \
3510 \
3511 if (GET_CODE (symref) == LABEL_REF) \
3512 return COSTS_N_INSNS (2); \
3513 \
3514 if (GET_CODE (symref) != SYMBOL_REF) \
3515 return COSTS_N_INSNS (4); \
3516 \
3518 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3519 return COSTS_N_INSNS (2); \
3520 \
3521 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3522 } \
3523 \
3524 case SYMBOL_REF: \
3525 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3526 \
3527 case CONST_DOUBLE: \
3528 { \
3529 rtx high, low; \
3530 if (TARGET_MIPS16) \
3531 return COSTS_N_INSNS (4); \
3532 split_double (X, &high, &low); \
3533 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3534 || low == CONST0_RTX (GET_MODE (low))) \
3535 ? 2 : 4); \
3536 }
3538 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3539 This can be used, for example, to indicate how costly a multiply
3540 instruction is. In writing this macro, you can use the construct
3541 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3543 This macro is optional; do not define it if the default cost
3544 assumptions are adequate for the target machine.
3546 If -mdebugd is used, change the multiply cost to 2, so multiply by
3547 a constant isn't converted to a series of shifts. This helps
3548 strength reduction, and also makes it easier to identify what the
3549 compiler is doing. */
3551 /* ??? Fix this to be right for the R8000. */
3552 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3553 case MEM: \
3554 { \
3555 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3556 if (simple_memory_operand (X, GET_MODE (X))) \
3557 return COSTS_N_INSNS (num_words); \
3558 \
3559 return COSTS_N_INSNS (2*num_words); \
3560 } \
3561 \
3562 case FFS: \
3563 return COSTS_N_INSNS (6); \
3564 \
3565 case NOT: \
3566 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3567 \
3568 case AND: \
3569 case IOR: \
3570 case XOR: \
3571 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3572 return COSTS_N_INSNS (2); \
3573 \
3574 break; \
3575 \
3576 case ASHIFT: \
3577 case ASHIFTRT: \
3578 case LSHIFTRT: \
3579 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3580 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3581 \
3582 break; \
3583 \
3584 case ABS: \
3585 { \
3586 enum machine_mode xmode = GET_MODE (X); \
3587 if (xmode == SFmode || xmode == DFmode) \
3588 return COSTS_N_INSNS (1); \
3589 \
3590 return COSTS_N_INSNS (4); \
3591 } \
3592 \
3593 case PLUS: \
3594 case MINUS: \
3595 { \
3596 enum machine_mode xmode = GET_MODE (X); \
3597 if (xmode == SFmode || xmode == DFmode) \
3598 { \
3599 if (TUNE_MIPS3000 \
3600 || TUNE_MIPS3900) \
3601 return COSTS_N_INSNS (2); \
3602 else if (TUNE_MIPS6000) \
3603 return COSTS_N_INSNS (3); \
3604 else \
3605 return COSTS_N_INSNS (6); \
3606 } \
3607 \
3608 if (xmode == DImode && !TARGET_64BIT) \
3609 return COSTS_N_INSNS (4); \
3610 \
3611 break; \
3612 } \
3613 \
3614 case NEG: \
3615 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3616 return 4; \
3617 \
3618 break; \
3619 \
3620 case MULT: \
3621 { \
3622 enum machine_mode xmode = GET_MODE (X); \
3623 if (xmode == SFmode) \
3624 { \
3625 if (TUNE_MIPS3000 \
3626 || TUNE_MIPS3900 \
3627 || TUNE_MIPS5000) \
3628 return COSTS_N_INSNS (4); \
3629 else if (TUNE_MIPS6000) \
3630 return COSTS_N_INSNS (5); \
3631 else \
3632 return COSTS_N_INSNS (7); \
3633 } \
3634 \
3635 if (xmode == DFmode) \
3636 { \
3637 if (TUNE_MIPS3000 \
3638 || TUNE_MIPS3900 \
3639 || TUNE_MIPS5000) \
3640 return COSTS_N_INSNS (5); \
3641 else if (TUNE_MIPS6000) \
3642 return COSTS_N_INSNS (6); \
3643 else \
3644 return COSTS_N_INSNS (8); \
3645 } \
3646 \
3647 if (TUNE_MIPS3000) \
3648 return COSTS_N_INSNS (12); \
3649 else if (TUNE_MIPS3900) \
3650 return COSTS_N_INSNS (2); \
3651 else if (TUNE_MIPS6000) \
3652 return COSTS_N_INSNS (17); \
3653 else if (TUNE_MIPS5000) \
3654 return COSTS_N_INSNS (5); \
3655 else \
3656 return COSTS_N_INSNS (10); \
3657 } \
3658 \
3659 case DIV: \
3660 case MOD: \
3661 { \
3662 enum machine_mode xmode = GET_MODE (X); \
3663 if (xmode == SFmode) \
3664 { \
3665 if (TUNE_MIPS3000 \
3666 || TUNE_MIPS3900) \
3667 return COSTS_N_INSNS (12); \
3668 else if (TUNE_MIPS6000) \
3669 return COSTS_N_INSNS (15); \
3670 else \
3671 return COSTS_N_INSNS (23); \
3672 } \
3673 \
3674 if (xmode == DFmode) \
3675 { \
3676 if (TUNE_MIPS3000 \
3677 || TUNE_MIPS3900) \
3678 return COSTS_N_INSNS (19); \
3679 else if (TUNE_MIPS6000) \
3680 return COSTS_N_INSNS (16); \
3681 else \
3682 return COSTS_N_INSNS (36); \
3683 } \
3684 } \
3686 \
3687 case UDIV: \
3688 case UMOD: \
3689 if (TUNE_MIPS3000 \
3690 || TUNE_MIPS3900) \
3691 return COSTS_N_INSNS (35); \
3692 else if (TUNE_MIPS6000) \
3693 return COSTS_N_INSNS (38); \
3694 else if (TUNE_MIPS5000) \
3695 return COSTS_N_INSNS (36); \
3696 else \
3697 return COSTS_N_INSNS (69); \
3698 \
3699 case SIGN_EXTEND: \
3700 /* A sign extend from SImode to DImode in 64 bit mode is often \
3701 zero instructions, because the result can often be used \
3703 if (TARGET_64BIT && GET_MODE (X) == DImode \
3704 && GET_MODE (XEXP (X, 0)) == SImode) \
3705 return COSTS_N_INSNS (1); \
3706 else \
3707 return COSTS_N_INSNS (2); \
3708 \
3709 case ZERO_EXTEND: \
3710 if (TARGET_64BIT && GET_MODE (X) == DImode \
3711 && GET_MODE (XEXP (X, 0)) == SImode) \
3712 return COSTS_N_INSNS (2); \
3713 else \
3714 return COSTS_N_INSNS (1);
3716 /* An expression giving the cost of an addressing mode that
3717 contains ADDRESS. If not defined, the cost is computed from the
3718 form of the ADDRESS expression and the `CONST_COSTS' values.
3720 For most CISC machines, the default cost is a good approximation
3721 of the true cost of the addressing mode. However, on RISC
3722 machines, all instructions normally have the same length and
3723 execution time. Hence all addresses will have equal costs.
3725 In cases where more than one form of an address is known, the
3726 form with the lowest cost will be used. If multiple forms have
3727 the same, lowest, cost, the one that is the most complex will be
3728 used.
3730 For example, suppose an address that is equal to the sum of a
3731 register and a constant is used twice in the same basic block.
3732 When this macro is not defined, the address will be computed in
3733 a register and memory references will be indirect through that
3734 register. On machines where the cost of the addressing mode
3735 containing the sum is no higher than that of a simple indirect
3736 reference, this will produce an additional instruction and
3737 possibly require an additional register. Proper specification
3738 of this macro eliminates this overhead for such machines.
3740 Similar use of this macro is made in strength reduction of loops.
3742 ADDRESS need not be valid as an address. In such a case, the
3743 cost is not relevant and can be any value; invalid addresses
3744 need not be assigned a different cost.
3746 On machines where an address involving more than one register is
3747 as cheap as an address computation involving only one register,
3748 defining `ADDRESS_COST' to reflect this can cause two registers
3749 to be live over a region of code where only one would have been
3750 if `ADDRESS_COST' were not defined in that manner. This effect
3751 should be considered in the definition of this macro.
3752 Equivalent costs should probably only be given to addresses with
3753 different numbers of registers on machines with lots of registers.
3755 This macro will normally either not be defined or be defined as
3756 a constant. */
3758 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3760 /* A C expression for the cost of moving data from a register in
3761 class FROM to one in class TO. The classes are expressed using
3762 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3763 the default; other values are interpreted relative to that.
3765 It is not required that the cost always equal 2 when FROM is the
3766 same as TO; on some machines it is expensive to move between
3767 registers if they are not general registers.
3769 If reload sees an insn consisting of a single `set' between two
3770 hard registers, and if `REGISTER_MOVE_COST' applied to their
3771 classes returns a value of 2, reload does not check to ensure
3772 that the constraints of the insn are met. Setting a cost of
3773 other than 2 will allow reload to verify that the constraints are
3774 met. You should do this if the `movM' pattern's constraints do
3775 not allow such copying.
3777 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3778 registers the same as for one of moving general registers to
3779 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3780 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3781 isn't clear if it is wise. And it might not work in all cases. We
3782 could solve the DImode LO reg problem by using a multiply, just like
3783 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3784 by using divide instructions. divu puts the remainder in the HI
3785 reg, so doing a divide by -1 will move the value in the HI reg for
3786 all values except -1. We could handle that case by using a signed
3787 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3788 compare/branch to test the input value to see which instruction we
3789 need to use. This gets pretty messy, but it is feasible. */
3791 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3792 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3793 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3794 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3795 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3796 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3797 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3798 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3799 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3800 : (((FROM) == HI_REG || (FROM) == LO_REG \
3801 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3802 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3803 : (((TO) == HI_REG || (TO) == LO_REG \
3804 || (TO) == MD_REGS || (TO) == HILO_REG) \
3805 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3806 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3807 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3808 : 12)
3810 /* ??? Fix this to be right for the R8000. */
3811 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3812 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3813 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3815 /* Define if copies to/from condition code registers should be avoided.
3817 This is needed for the MIPS because reload_outcc is not complete;
3818 it needs to handle cases where the source is a general or another
3819 condition code register. */
3820 #define AVOID_CCMODE_COPIES
3822 /* A C expression for the cost of a branch instruction. A value of
3823 1 is the default; other values are interpreted relative to that. */
3825 /* ??? Fix this to be right for the R8000. */
3826 #define BRANCH_COST \
3827 ((! TARGET_MIPS16 \
3828 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3829 ? 2 : 1)
3831 /* If defined, modifies the length assigned to instruction INSN as a
3832 function of the context in which it is used. LENGTH is an lvalue
3833 that contains the initially computed length of the insn and should
3834 be updated with the correct length of the insn. */
3835 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3836 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3838 \f
3839 /* Optionally define this if you have added predicates to
3840 `MACHINE.c'. This macro is called within an initializer of an
3841 array of structures. The first field in the structure is the
3842 name of a predicate and the second field is an array of rtl
3843 codes. For each predicate, list all rtl codes that can be in
3844 expressions matched by the predicate. The list should have a
3845 trailing comma. Here is an example of two entries in the list
3846 for a typical RISC machine:
3848 #define PREDICATE_CODES \
3849 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3850 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3852 Defining this macro does not affect the generated code (however,
3853 incorrect definitions that omit an rtl code that may be matched
3854 by the predicate can cause the compiler to malfunction).
3855 Instead, it allows the table built by `genrecog' to be more
3856 compact and efficient, thus speeding up the compiler. The most
3857 important predicates to include in the list specified by this
3858 macro are thoses used in the most insn patterns. */
3860 #define PREDICATE_CODES \
3873 LTU, LEU }}, \
3878 SYMBOL_REF, LABEL_REF, SUBREG, \
3879 REG, MEM}}, \
3881 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3882 MEM, SIGN_EXTEND }}, \
3885 SIGN_EXTEND }}, \
3887 SIGN_EXTEND }}, \
3889 SIGN_EXTEND }}, \
3891 SYMBOL_REF, LABEL_REF, SUBREG, \
3892 REG, SIGN_EXTEND }}, \
3895 CONST_DOUBLE, CONST }}, \
3899 /* A list of predicates that do special things with modes, and so
3900 should not elicit warnings for VOIDmode match_operand. */
3902 #define SPECIAL_MODE_PREDICATES \
3905 \f
3906 /* If defined, a C statement to be executed just prior to the
3907 output of assembler code for INSN, to modify the extracted
3908 operands so they will be output differently.
3910 Here the argument OPVEC is the vector containing the operands
3911 extracted from INSN, and NOPERANDS is the number of elements of
3912 the vector which contain meaningful data for this insn. The
3913 contents of this vector are what will be used to convert the
3914 insn template into assembler code, so you can change the
3915 assembler output by changing the contents of the vector.
3917 We use it to check if the current insn needs a nop in front of it
3918 because of load delays, and also to update the delay slot
3919 statistics. */
3921 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3922 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3924 \f
3925 /* Control the assembler format that we output. */
3927 /* Output at beginning of assembler file.
3928 If we are optimizing to use the global pointer, create a temporary
3929 file to hold all of the text stuff, and write it out to the end.
3930 This is needed because the MIPS assembler is evidently one pass,
3931 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3932 declaration when the code is processed, it generates a two
3933 instruction sequence. */
3935 #undef ASM_FILE_START
3936 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3938 /* Output to assembler file text saying following lines
3939 may contain character constants, extra white space, comments, etc. */
3941 #ifndef ASM_APP_ON
3943 #endif
3945 /* Output to assembler file text saying following lines
3946 no longer contain unusual constructs. */
3948 #ifndef ASM_APP_OFF
3950 #endif
3952 /* How to refer to registers in assembler output.
3953 This sequence is indexed by compiler's hard-register-number (see above).
3955 In order to support the two different conventions for register names,
3956 we use the name of a table set up in mips.c, which is overwritten
3957 if -mrnames is used. */
3959 #define REGISTER_NAMES \
3960 { \
3961 &mips_reg_names[ 0][0], \
3962 &mips_reg_names[ 1][0], \
3963 &mips_reg_names[ 2][0], \
3964 &mips_reg_names[ 3][0], \
3965 &mips_reg_names[ 4][0], \
3966 &mips_reg_names[ 5][0], \
3967 &mips_reg_names[ 6][0], \
3968 &mips_reg_names[ 7][0], \
3969 &mips_reg_names[ 8][0], \
3970 &mips_reg_names[ 9][0], \
3971 &mips_reg_names[10][0], \
3972 &mips_reg_names[11][0], \
3973 &mips_reg_names[12][0], \
3974 &mips_reg_names[13][0], \
3975 &mips_reg_names[14][0], \
3976 &mips_reg_names[15][0], \
3977 &mips_reg_names[16][0], \
3978 &mips_reg_names[17][0], \
3979 &mips_reg_names[18][0], \
3980 &mips_reg_names[19][0], \
3981 &mips_reg_names[20][0], \
3982 &mips_reg_names[21][0], \
3983 &mips_reg_names[22][0], \
3984 &mips_reg_names[23][0], \
3985 &mips_reg_names[24][0], \
3986 &mips_reg_names[25][0], \
3987 &mips_reg_names[26][0], \
3988 &mips_reg_names[27][0], \
3989 &mips_reg_names[28][0], \
3990 &mips_reg_names[29][0], \
3991 &mips_reg_names[30][0], \
3992 &mips_reg_names[31][0], \
3993 &mips_reg_names[32][0], \
3994 &mips_reg_names[33][0], \
3995 &mips_reg_names[34][0], \
3996 &mips_reg_names[35][0], \
3997 &mips_reg_names[36][0], \
3998 &mips_reg_names[37][0], \
3999 &mips_reg_names[38][0], \
4000 &mips_reg_names[39][0], \
4001 &mips_reg_names[40][0], \
4002 &mips_reg_names[41][0], \
4003 &mips_reg_names[42][0], \
4004 &mips_reg_names[43][0], \
4005 &mips_reg_names[44][0], \
4006 &mips_reg_names[45][0], \
4007 &mips_reg_names[46][0], \
4008 &mips_reg_names[47][0], \
4009 &mips_reg_names[48][0], \
4010 &mips_reg_names[49][0], \
4011 &mips_reg_names[50][0], \
4012 &mips_reg_names[51][0], \
4013 &mips_reg_names[52][0], \
4014 &mips_reg_names[53][0], \
4015 &mips_reg_names[54][0], \
4016 &mips_reg_names[55][0], \
4017 &mips_reg_names[56][0], \
4018 &mips_reg_names[57][0], \
4019 &mips_reg_names[58][0], \
4020 &mips_reg_names[59][0], \
4021 &mips_reg_names[60][0], \
4022 &mips_reg_names[61][0], \
4023 &mips_reg_names[62][0], \
4024 &mips_reg_names[63][0], \
4025 &mips_reg_names[64][0], \
4026 &mips_reg_names[65][0], \
4027 &mips_reg_names[66][0], \
4028 &mips_reg_names[67][0], \
4029 &mips_reg_names[68][0], \
4030 &mips_reg_names[69][0], \
4031 &mips_reg_names[70][0], \
4032 &mips_reg_names[71][0], \
4033 &mips_reg_names[72][0], \
4034 &mips_reg_names[73][0], \
4035 &mips_reg_names[74][0], \
4036 &mips_reg_names[75][0], \
4037 }
4039 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
4040 So define this for it. */
4041 #define DEBUG_REGISTER_NAMES \
4042 { \
4053 }
4055 /* If defined, a C initializer for an array of structures
4056 containing a name and a register number. This macro defines
4057 additional names for hard registers, thus allowing the `asm'
4058 option in declarations to refer to registers using alternate
4059 names.
4061 We define both names for the integer registers here. */
4063 #define ADDITIONAL_REGISTER_NAMES \
4064 { \
4132 }
4134 /* A C compound statement to output to stdio stream STREAM the
4135 assembler syntax for an instruction operand X. X is an RTL
4136 expression.
4138 CODE is a value that can be used to specify one of several ways
4139 of printing the operand. It is used when identical operands
4140 must be printed differently depending on the context. CODE
4141 comes from the `%' specification that was used to request
4142 printing of the operand. If the specification was just `%DIGIT'
4143 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4144 is the ASCII code for LTR.
4146 If X is a register, this macro should print the register's name.
4147 The names can be found in an array `reg_names' whose type is
4148 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4150 When the machine description has a specification `%PUNCT' (a `%'
4151 followed by a punctuation character), this macro is called with
4152 a null pointer for X and the punctuation character for CODE.
4154 See mips.c for the MIPS specific codes. */
4156 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4158 /* A C expression which evaluates to true if CODE is a valid
4159 punctuation character for use in the `PRINT_OPERAND' macro. If
4160 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4161 punctuation characters (except for the standard one, `%') are
4162 used in this way. */
4164 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4166 /* A C compound statement to output to stdio stream STREAM the
4167 assembler syntax for an instruction operand that is a memory
4168 reference whose address is ADDR. ADDR is an RTL expression.
4170 On some machines, the syntax for a symbolic address depends on
4171 the section that the address refers to. On these machines,
4172 define the macro `ENCODE_SECTION_INFO' to store the information
4173 into the `symbol_ref', and then check for it here. */
4175 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4178 /* A C statement, to be executed after all slot-filler instructions
4179 have been output. If necessary, call `dbr_sequence_length' to
4180 determine the number of slots filled in a sequence (zero if not
4181 currently outputting a sequence), to decide how many no-ops to
4182 output, or whatever.
4184 Don't define this macro if it has nothing to do, but it is
4185 helpful in reading assembly output if the extent of the delay
4186 sequence is made explicit (e.g. with white space).
4188 Note that output routines for instructions with delay slots must
4189 be prepared to deal with not being output as part of a sequence
4190 (i.e. when the scheduling pass is not run, or when no slot
4191 fillers could be found.) The variable `final_sequence' is null
4192 when not processing a sequence, otherwise it contains the
4193 `sequence' rtx being output. */
4195 #define DBR_OUTPUT_SEQEND(STREAM) \
4196 do \
4197 { \
4198 if (set_nomacro > 0 && --set_nomacro == 0) \
4200 \
4201 if (set_noreorder > 0 && --set_noreorder == 0) \
4203 \
4204 dslots_jump_filled++; \
4206 } \
4207 while (0)
4210 /* How to tell the debugger about changes of source files. Note, the
4211 mips ECOFF format cannot deal with changes of files inside of
4212 functions, which means the output of parser generators like bison
4213 is generally not debuggable without using the -l switch. Lose,
4214 lose, lose. Silicon graphics seems to want all .file's hardwired
4215 to 1. */
4217 #ifndef SET_FILE_NUMBER
4218 #define SET_FILE_NUMBER() ++num_source_filenames
4219 #endif
4221 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4222 mips_output_filename (STREAM, NAME)
4224 /* This is defined so that it can be overridden in iris6.h. */
4225 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4226 do \
4227 { \
4229 output_quoted_string (STREAM, NAME); \
4231 } \
4232 while (0)
4234 /* This is how to output a note the debugger telling it the line number
4235 to which the following sequence of instructions corresponds.
4236 Silicon graphics puts a label after each .loc. */
4238 #ifndef LABEL_AFTER_LOC
4239 #define LABEL_AFTER_LOC(STREAM)
4240 #endif
4242 #ifndef ASM_OUTPUT_SOURCE_LINE
4243 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4244 mips_output_lineno (STREAM, LINE)
4245 #endif
4247 /* The MIPS implementation uses some labels for its own purpose. The
4248 following lists what labels are created, and are all formed by the
4249 pattern $L[a-z].*. The machine independent portion of GCC creates
4250 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4252 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4253 $Lb[0-9]+ Begin blocks for MIPS debug support
4254 $Lc[0-9]+ Label for use in s<xx> operation.
4255 $Le[0-9]+ End blocks for MIPS debug support
4256 $Lp\..+ Half-pic labels. */
4258 /* This is how to output the definition of a user-level label named NAME,
4259 such as the label on a static function or variable NAME.
4261 If we are optimizing the gp, remember that this label has been put
4262 out, so we know not to emit an .extern for it in mips_asm_file_end.
4263 We use one of the common bits in the IDENTIFIER tree node for this,
4264 since those bits seem to be unused, and we don't have any method
4265 of getting the decl nodes from the name. */
4267 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4268 do { \
4269 assemble_name (STREAM, NAME); \
4271 } while (0)
4274 /* A C statement (sans semicolon) to output to the stdio stream
4275 STREAM any text necessary for declaring the name NAME of an
4276 initialized variable which is being defined. This macro must
4277 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4278 The argument DECL is the `VAR_DECL' tree node representing the
4279 variable.
4281 If this macro is not defined, then the variable name is defined
4282 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4284 #undef ASM_DECLARE_OBJECT_NAME
4285 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4286 do \
4287 { \
4289 HALF_PIC_DECLARE (NAME); \
4290 } \
4291 while (0)
4294 /* This is how to output a command to make the user-level label named NAME
4295 defined for reference from other files. */
4297 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4298 do { \
4300 assemble_name (STREAM, NAME); \
4302 } while (0)
4304 /* This says how to define a global common symbol. */
4306 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4307 do { \
4308 /* If the target wants uninitialized const declarations in \
4310 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4311 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4312 && (DECL_INITIAL (DECL) == 0 \
4313 || DECL_INITIAL (DECL) == error_mark_node)) \
4314 { \
4315 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4316 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4317 \
4318 READONLY_DATA_SECTION (); \
4319 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4321 (SIZE)); \
4322 } \
4323 else \
4325 (SIZE)); \
4326 } while (0)
4329 /* This says how to define a local common symbol (ie, not visible to
4330 linker). */
4332 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4336 /* This says how to output an external. It would be possible not to
4337 output anything and let undefined symbol become external. However
4338 the assembler uses length information on externals to allocate in
4339 data/sdata bss/sbss, thereby saving exec time. */
4341 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4342 mips_output_external(STREAM,DECL,NAME)
4344 /* This says what to print at the end of the assembly file */
4345 #undef ASM_FILE_END
4346 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4349 /* Play switch file games if we're optimizing the global pointer. */
4351 #undef TEXT_SECTION
4352 #define TEXT_SECTION() \
4353 do { \
4354 extern FILE *asm_out_text_file; \
4355 if (TARGET_FILE_SWITCHING) \
4356 asm_out_file = asm_out_text_file; \
4357 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
4359 } while (0)
4362 /* This is how to declare a function name. The actual work of
4363 emitting the label is moved to function_prologue, so that we can
4364 get the line number correctly emitted before the .ent directive,
4365 and after any .file directives. */
4367 #undef ASM_DECLARE_FUNCTION_NAME
4368 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4369 HALF_PIC_DECLARE (NAME)
4371 /* This is how to output an internal numbered label where
4372 PREFIX is the class of label and NUM is the number within the class. */
4374 #undef ASM_OUTPUT_INTERNAL_LABEL
4375 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4378 /* This is how to store into the string LABEL
4379 the symbol_ref name of an internal numbered label where
4380 PREFIX is the class of label and NUM is the number within the class.
4381 This is suitable for output with `assemble_name'. */
4383 #undef ASM_GENERATE_INTERNAL_LABEL
4384 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4387 /* This is how to output an assembler line defining a `double' constant. */
4389 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4390 mips_output_double (STREAM, VALUE)
4393 /* This is how to output an assembler line defining a `float' constant. */
4395 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4396 mips_output_float (STREAM, VALUE)
4399 /* This is how to output an assembler line defining an `int' constant. */
4401 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4402 do { \
4404 output_addr_const (STREAM, (VALUE)); \
4406 } while (0)
4408 /* Likewise for 64 bit, `char' and `short' constants.
4410 FIXME: operand_subword can't handle some complex constant expressions
4411 that output_addr_const can (for example it does not call
4412 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4413 rely on that to avoid operand_subword for most of the cases where this
4414 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4415 or the same case with the type of 'i' changed to long long.
4417 */
4419 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4420 do { \
4421 if (TARGET_64BIT || TARGET_GAS) \
4422 { \
4424 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4425 /* We can't use 'X' for negative numbers, because then we won't \
4427 output_addr_const (STREAM, VALUE); \
4428 else \
4429 /* We must use 'X', because otherwise LONG_MIN will print as \
4433 } \
4434 else \
4435 { \
4436 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4437 UNITS_PER_WORD, BITS_PER_WORD, 1); \
4438 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4439 UNITS_PER_WORD, BITS_PER_WORD, 1); \
4440 } \
4441 } while (0)
4443 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4444 { \
4446 output_addr_const (STREAM, (VALUE)); \
4448 }
4450 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4451 { \
4453 output_addr_const (STREAM, (VALUE)); \
4455 }
4457 /* This is how to output an assembler line for a numeric constant byte. */
4459 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4462 /* This is how to output an element of a case-vector that is absolute. */
4464 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4467 LOCAL_LABEL_PREFIX, \
4468 VALUE)
4470 /* This is how to output an element of a case-vector that is relative.
4471 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4472 TARGET_EMBEDDED_PIC). */
4474 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4475 do { \
4476 if (TARGET_MIPS16) \
4478 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4479 else if (TARGET_EMBEDDED_PIC) \
4482 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4483 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4486 LOCAL_LABEL_PREFIX, VALUE); \
4487 else \
4490 LOCAL_LABEL_PREFIX, VALUE); \
4491 } while (0)
4493 /* When generating embedded PIC or mips16 code we want to put the jump
4494 table in the .text section. In all other cases, we want to put the
4495 jump table in the .rdata section. Unfortunately, we can't use
4496 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4497 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4498 section if appropriate. */
4499 #undef ASM_OUTPUT_CASE_LABEL
4500 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4501 do { \
4502 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4503 function_section (current_function_decl); \
4504 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4505 } while (0)
4507 /* This is how to output an assembler line
4508 that says to advance the location counter
4509 to a multiple of 2**LOG bytes. */
4511 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4514 /* This is how to output an assembler line to advance the location
4515 counter by SIZE bytes. */
4517 #undef ASM_OUTPUT_SKIP
4518 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4521 /* This is how to output a string. */
4522 #undef ASM_OUTPUT_ASCII
4523 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4524 mips_output_ascii (STREAM, STRING, LEN)
4526 /* Handle certain cpp directives used in header files on sysV. */
4527 #define SCCS_DIRECTIVE
4529 /* Output #ident as a in the read-only data section. */
4530 #undef ASM_OUTPUT_IDENT
4531 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4532 { \
4533 const char *p = STRING; \
4534 int size = strlen (p) + 1; \
4535 rdata_section (); \
4536 assemble_string (p, size); \
4537 }
4538 \f
4539 /* Default to -G 8 */
4540 #ifndef MIPS_DEFAULT_GVALUE
4541 #define MIPS_DEFAULT_GVALUE 8
4542 #endif
4544 /* Define the strings to put out for each section in the object file. */
4549 #undef READONLY_DATA_SECTION
4550 #define READONLY_DATA_SECTION rdata_section
4551 #define SMALL_DATA_SECTION sdata_section
4553 /* What other sections we support other than the normal .data/.text. */
4555 #undef EXTRA_SECTIONS
4556 #define EXTRA_SECTIONS in_sdata, in_rdata
4558 /* Define the additional functions to select our additional sections. */
4560 /* on the MIPS it is not a good idea to put constants in the text
4561 section, since this defeats the sdata/data mechanism. This is
4562 especially true when -O is used. In this case an effort is made to
4563 address with faster (gp) register relative addressing, which can
4564 only get at sdata and sbss items (there is no stext !!) However,
4565 if the constant is too large for sdata, and it's readonly, it
4566 will go into the .rdata section. */
4568 #undef EXTRA_SECTION_FUNCTIONS
4569 #define EXTRA_SECTION_FUNCTIONS \
4570 void \
4571 sdata_section () \
4572 { \
4573 if (in_section != in_sdata) \
4574 { \
4576 in_section = in_sdata; \
4577 } \
4578 } \
4579 \
4580 void \
4581 rdata_section () \
4582 { \
4583 if (in_section != in_rdata) \
4584 { \
4586 in_section = in_rdata; \
4587 } \
4588 }
4590 /* Given a decl node or constant node, choose the section to output it in
4591 and select that section. */
4593 #undef SELECT_RTX_SECTION
4594 #define SELECT_RTX_SECTION(MODE, RTX, ALIGN) \
4595 mips_select_rtx_section (MODE, RTX)
4597 #undef SELECT_SECTION
4598 #define SELECT_SECTION(DECL, RELOC, ALIGN) \
4599 mips_select_section (DECL, RELOC)
4601 \f
4602 /* Store in OUTPUT a string (made with alloca) containing
4603 an assembler-name for a local static variable named NAME.
4604 LABELNO is an integer which is different for each call. */
4606 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4607 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4610 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4611 do \
4612 { \
4615 reg_names[STACK_POINTER_REGNUM], \
4616 reg_names[STACK_POINTER_REGNUM], \
4618 reg_names[REGNO], \
4619 reg_names[STACK_POINTER_REGNUM]); \
4620 } \
4621 while (0)
4623 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4624 do \
4625 { \
4626 if (! set_noreorder) \
4628 \
4629 dslots_load_total++; \
4630 dslots_load_filled++; \
4633 reg_names[REGNO], \
4634 reg_names[STACK_POINTER_REGNUM], \
4636 reg_names[STACK_POINTER_REGNUM], \
4637 reg_names[STACK_POINTER_REGNUM]); \
4638 \
4639 if (! set_noreorder) \
4641 } \
4642 while (0)
4644 /* How to start an assembler comment.
4645 The leading space is important (the mips native assembler requires it). */
4646 #ifndef ASM_COMMENT_START
4648 #endif
4649 \f
4651 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4652 and mips-tdump.c to print them out.
4654 These must match the corresponding definitions in gdb/mipsread.c.
4655 Unfortunately, gcc and gdb do not currently share any directories. */
4657 #define CODE_MASK 0x8F300
4658 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4659 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4660 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4662 \f
4663 /* Default definitions for size_t and ptrdiff_t. */
4665 #ifndef SIZE_TYPE
4666 #define NO_BUILTIN_SIZE_TYPE
4668 #endif
4670 #ifndef PTRDIFF_TYPE
4671 #define NO_BUILTIN_PTRDIFF_TYPE
4673 #endif
4675 /* See mips_expand_prologue's use of loadgp for when this should be
4676 true. */
4678 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4679 && mips_abi != ABI_32 \
4680 && mips_abi != ABI_O64)
4681 \f
4682 /* In mips16 mode, we need to look through the function to check for
4683 PC relative loads that are out of range. */
4684 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4686 /* We need to use a special set of functions to handle hard floating
4687 point code in mips16 mode. */
4689 #ifndef INIT_SUBTARGET_OPTABS
4690 #define INIT_SUBTARGET_OPTABS
4691 #endif
4693 #define INIT_TARGET_OPTABS \
4694 do \
4695 { \
4696 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4697 INIT_SUBTARGET_OPTABS; \
4698 else \
4699 { \
4700 add_optab->handlers[(int) SFmode].libfunc = \
4702 sub_optab->handlers[(int) SFmode].libfunc = \
4704 smul_optab->handlers[(int) SFmode].libfunc = \
4706 sdiv_optab->handlers[(int) SFmode].libfunc = \
4708 \
4715 \
4716 floatsisf_libfunc = \
4718 fixsfsi_libfunc = \
4720 \
4721 if (TARGET_DOUBLE_FLOAT) \
4722 { \
4723 add_optab->handlers[(int) DFmode].libfunc = \
4725 sub_optab->handlers[(int) DFmode].libfunc = \
4727 smul_optab->handlers[(int) DFmode].libfunc = \
4729 sdiv_optab->handlers[(int) DFmode].libfunc = \
4731 \
4732 extendsfdf2_libfunc = \
4734 truncdfsf2_libfunc = \
4736 \
4737 eqdf2_libfunc = \
4739 nedf2_libfunc = \
4741 gtdf2_libfunc = \
4743 gedf2_libfunc = \
4745 ltdf2_libfunc = \
4747 ledf2_libfunc = \
4749 \
4750 floatsidf_libfunc = \
4752 fixdfsi_libfunc = \
4754 } \
4755 } \
4756 } \
4757 while (0)